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GET /api/patches/102011/?format=api
{ "id": 102011, "url": "http://patches.dpdk.org/api/patches/102011/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211018123835.1080174-7-conor.walsh@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211018123835.1080174-7-conor.walsh@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211018123835.1080174-7-conor.walsh@intel.com", "date": "2021-10-18T12:38:29", "name": "[v8,06/12] dma/ioat: add data path job submission functions", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "7029f53d77d7bcd3c466002f913da61fbe6048f2", "submitter": { "id": 1935, "url": "http://patches.dpdk.org/api/people/1935/?format=api", "name": "Conor Walsh", "email": "conor.walsh@intel.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211018123835.1080174-7-conor.walsh@intel.com/mbox/", "series": [ { "id": 19738, "url": "http://patches.dpdk.org/api/series/19738/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19738", "date": "2021-10-18T12:38:23", "name": "dma: add dmadev driver for ioat devices", "version": 8, "mbox": "http://patches.dpdk.org/series/19738/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/102011/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/102011/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1602CA0C43;\n\tMon, 18 Oct 2021 14:39:22 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C8FED4114A;\n\tMon, 18 Oct 2021 14:38:57 +0200 (CEST)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by mails.dpdk.org (Postfix) with ESMTP id 92F6041130\n for <dev@dpdk.org>; Mon, 18 Oct 2021 14:38:56 +0200 (CEST)", "from orsmga005.jf.intel.com ([10.7.209.41])\n by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 18 Oct 2021 05:38:56 -0700", "from silpixa00401160.ir.intel.com ([10.55.129.96])\n by orsmga005.jf.intel.com with ESMTP; 18 Oct 2021 05:38:53 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10140\"; a=\"228117652\"", "E=Sophos;i=\"5.85,382,1624345200\"; d=\"scan'208\";a=\"228117652\"", "E=Sophos;i=\"5.85,382,1624345200\"; d=\"scan'208\";a=\"661361110\"" ], "X-ExtLoop1": "1", "From": "Conor Walsh <conor.walsh@intel.com>", "To": "bruce.richardson@intel.com, thomas@monjalon.net, fengchengwen@huawei.com,\n jerinj@marvell.com, kevin.laatz@intel.com", "Cc": "dev@dpdk.org,\n\tConor Walsh <conor.walsh@intel.com>", "Date": "Mon, 18 Oct 2021 12:38:29 +0000", "Message-Id": "<20211018123835.1080174-7-conor.walsh@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20211018123835.1080174-1-conor.walsh@intel.com>", "References": "<20210827172550.1522362-1-conor.walsh@intel.com>\n <20211018123835.1080174-1-conor.walsh@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v8 06/12] dma/ioat: add data path job submission\n functions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add data path functions for enqueuing and submitting operations to\nIOAT devices.\n\nSigned-off-by: Conor Walsh <conor.walsh@intel.com>\nReviewed-by: Kevin Laatz <kevin.laatz@intel.com>\nReviewed-by: Chengwen Feng <fengchengwen@huawei.com>\n---\n doc/guides/dmadevs/ioat.rst | 9 ++++\n drivers/dma/ioat/ioat_dmadev.c | 92 ++++++++++++++++++++++++++++++++++\n 2 files changed, 101 insertions(+)", "diff": "diff --git a/doc/guides/dmadevs/ioat.rst b/doc/guides/dmadevs/ioat.rst\nindex df159f9957..9ee4e372a8 100644\n--- a/doc/guides/dmadevs/ioat.rst\n+++ b/doc/guides/dmadevs/ioat.rst\n@@ -85,3 +85,12 @@ IOAT configuration requirements:\n \n Once configured, the device can then be made ready for use by calling the\n ``rte_dma_start()`` API.\n+\n+Performing Data Copies\n+~~~~~~~~~~~~~~~~~~~~~~~\n+\n+Refer to the :ref:`Enqueue / Dequeue APIs <dmadev_enqueue_dequeue>` section of the dmadev library\n+documentation for details on operation enqueue and submission API usage.\n+\n+It is expected that, for efficiency reasons, a burst of operations will be enqueued to the\n+device via multiple enqueue calls between calls to the ``rte_dma_submit()`` function.\ndiff --git a/drivers/dma/ioat/ioat_dmadev.c b/drivers/dma/ioat/ioat_dmadev.c\nindex cf28f4a7e6..4d00fec5c8 100644\n--- a/drivers/dma/ioat/ioat_dmadev.c\n+++ b/drivers/dma/ioat/ioat_dmadev.c\n@@ -5,6 +5,7 @@\n #include <rte_bus_pci.h>\n #include <rte_dmadev_pmd.h>\n #include <rte_malloc.h>\n+#include <rte_prefetch.h>\n \n #include \"ioat_internal.h\"\n \n@@ -17,6 +18,12 @@ RTE_LOG_REGISTER_DEFAULT(ioat_pmd_logtype, INFO);\n #define IOAT_PMD_NAME dmadev_ioat\n #define IOAT_PMD_NAME_STR RTE_STR(IOAT_PMD_NAME)\n \n+/* IOAT operations. */\n+enum rte_ioat_ops {\n+\tioat_op_copy = 0,\t/* Standard DMA Operation */\n+\tioat_op_fill\t\t/* Block Fill */\n+};\n+\n /* Configure a device. */\n static int\n ioat_dev_configure(struct rte_dma_dev *dev __rte_unused, const struct rte_dma_conf *dev_conf,\n@@ -208,6 +215,87 @@ ioat_dev_close(struct rte_dma_dev *dev)\n \treturn 0;\n }\n \n+/* Trigger hardware to begin performing enqueued operations. */\n+static inline void\n+__submit(struct ioat_dmadev *ioat)\n+{\n+\t*ioat->doorbell = ioat->next_write - ioat->offset;\n+\n+\tioat->last_write = ioat->next_write;\n+}\n+\n+/* External submit function wrapper. */\n+static int\n+ioat_submit(void *dev_private, uint16_t qid __rte_unused)\n+{\n+\tstruct ioat_dmadev *ioat = dev_private;\n+\n+\t__submit(ioat);\n+\n+\treturn 0;\n+}\n+\n+/* Write descriptor for enqueue. */\n+static inline int\n+__write_desc(void *dev_private, uint32_t op, uint64_t src, phys_addr_t dst,\n+\t\tunsigned int length, uint64_t flags)\n+{\n+\tstruct ioat_dmadev *ioat = dev_private;\n+\tuint16_t ret;\n+\tconst unsigned short mask = ioat->qcfg.nb_desc - 1;\n+\tconst unsigned short read = ioat->next_read;\n+\tunsigned short write = ioat->next_write;\n+\tconst unsigned short space = mask + read - write;\n+\tstruct ioat_dma_hw_desc *desc;\n+\n+\tif (space == 0)\n+\t\treturn -ENOSPC;\n+\n+\tioat->next_write = write + 1;\n+\twrite &= mask;\n+\n+\tdesc = &ioat->desc_ring[write];\n+\tdesc->size = length;\n+\tdesc->u.control_raw = (uint32_t)((op << IOAT_CMD_OP_SHIFT) |\n+\t\t\t(1 << IOAT_COMP_UPDATE_SHIFT));\n+\n+\t/* In IOAT the fence ensures that all operations including the current one\n+\t * are completed before moving on, DMAdev assumes that the fence ensures\n+\t * all operations before the current one are completed before starting\n+\t * the current one, so in IOAT we set the fence for the previous descriptor.\n+\t */\n+\tif (flags & RTE_DMA_OP_FLAG_FENCE)\n+\t\tioat->desc_ring[(write - 1) & mask].u.control.fence = 1;\n+\n+\tdesc->src_addr = src;\n+\tdesc->dest_addr = dst;\n+\n+\trte_prefetch0(&ioat->desc_ring[ioat->next_write & mask]);\n+\n+\tret = (uint16_t)(ioat->next_write - 1);\n+\n+\tif (flags & RTE_DMA_OP_FLAG_SUBMIT)\n+\t\t__submit(ioat);\n+\n+\treturn ret;\n+}\n+\n+/* Enqueue a fill operation onto the ioat device. */\n+static int\n+ioat_enqueue_fill(void *dev_private, uint16_t qid __rte_unused, uint64_t pattern,\n+\t\trte_iova_t dst, unsigned int length, uint64_t flags)\n+{\n+\treturn __write_desc(dev_private, ioat_op_fill, pattern, dst, length, flags);\n+}\n+\n+/* Enqueue a copy operation onto the ioat device. */\n+static int\n+ioat_enqueue_copy(void *dev_private, uint16_t qid __rte_unused, rte_iova_t src,\n+\t\trte_iova_t dst, unsigned int length, uint64_t flags)\n+{\n+\treturn __write_desc(dev_private, ioat_op_copy, src, dst, length, flags);\n+}\n+\n /* Dump DMA device info. */\n static int\n __dev_dump(void *dev_private, FILE *f)\n@@ -310,6 +398,10 @@ ioat_dmadev_create(const char *name, struct rte_pci_device *dev)\n \n \tdmadev->dev_ops = &ioat_dmadev_ops;\n \n+\tdmadev->fp_obj->copy = ioat_enqueue_copy;\n+\tdmadev->fp_obj->fill = ioat_enqueue_fill;\n+\tdmadev->fp_obj->submit = ioat_submit;\n+\n \tioat = dmadev->data->dev_private;\n \tioat->dmadev = dmadev;\n \tioat->regs = dev->mem_resource[0].addr;\n", "prefixes": [ "v8", "06/12" ] }