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GET /api/patches/102008/?format=api
{ "id": 102008, "url": "http://patches.dpdk.org/api/patches/102008/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211018123835.1080174-4-conor.walsh@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211018123835.1080174-4-conor.walsh@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211018123835.1080174-4-conor.walsh@intel.com", "date": "2021-10-18T12:38:26", "name": "[v8,03/12] dma/ioat: add datapath structures", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "5b6411dc786c63318add73fde47196ae50e1d5d0", "submitter": { "id": 1935, "url": "http://patches.dpdk.org/api/people/1935/?format=api", "name": "Conor Walsh", "email": "conor.walsh@intel.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211018123835.1080174-4-conor.walsh@intel.com/mbox/", "series": [ { "id": 19738, "url": "http://patches.dpdk.org/api/series/19738/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19738", "date": "2021-10-18T12:38:23", "name": "dma: add dmadev driver for ioat devices", "version": 8, "mbox": "http://patches.dpdk.org/series/19738/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/102008/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/102008/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 09446A0C43;\n\tMon, 18 Oct 2021 14:39:03 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 77EDA410E4;\n\tMon, 18 Oct 2021 14:38:51 +0200 (CEST)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by mails.dpdk.org (Postfix) with ESMTP id 0EA0041109\n for <dev@dpdk.org>; Mon, 18 Oct 2021 14:38:48 +0200 (CEST)", "from orsmga005.jf.intel.com ([10.7.209.41])\n by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 18 Oct 2021 05:38:48 -0700", "from silpixa00401160.ir.intel.com ([10.55.129.96])\n by orsmga005.jf.intel.com with ESMTP; 18 Oct 2021 05:38:46 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10140\"; a=\"228117639\"", "E=Sophos;i=\"5.85,382,1624345200\"; d=\"scan'208\";a=\"228117639\"", "E=Sophos;i=\"5.85,382,1624345200\"; d=\"scan'208\";a=\"661361075\"" ], "X-ExtLoop1": "1", "From": "Conor Walsh <conor.walsh@intel.com>", "To": "bruce.richardson@intel.com, thomas@monjalon.net, fengchengwen@huawei.com,\n jerinj@marvell.com, kevin.laatz@intel.com", "Cc": "dev@dpdk.org,\n\tConor Walsh <conor.walsh@intel.com>", "Date": "Mon, 18 Oct 2021 12:38:26 +0000", "Message-Id": "<20211018123835.1080174-4-conor.walsh@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20211018123835.1080174-1-conor.walsh@intel.com>", "References": "<20210827172550.1522362-1-conor.walsh@intel.com>\n <20211018123835.1080174-1-conor.walsh@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v8 03/12] dma/ioat: add datapath structures", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add data structures required for the data path of IOAT devices.\n\nSigned-off-by: Conor Walsh <conor.walsh@intel.com>\nSigned-off-by: Bruce Richardson <bruce.richardson@intel.com>\nReviewed-by: Kevin Laatz <kevin.laatz@intel.com>\n---\n drivers/dma/ioat/ioat_dmadev.c | 70 ++++++++++-\n drivers/dma/ioat/ioat_hw_defs.h | 215 ++++++++++++++++++++++++++++++++\n 2 files changed, 284 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/dma/ioat/ioat_dmadev.c b/drivers/dma/ioat/ioat_dmadev.c\nindex 90f54567a4..876e17f320 100644\n--- a/drivers/dma/ioat/ioat_dmadev.c\n+++ b/drivers/dma/ioat/ioat_dmadev.c\n@@ -15,11 +15,79 @@ RTE_LOG_REGISTER_DEFAULT(ioat_pmd_logtype, INFO);\n #define IOAT_PMD_NAME dmadev_ioat\n #define IOAT_PMD_NAME_STR RTE_STR(IOAT_PMD_NAME)\n \n+/* Dump DMA device info. */\n+static int\n+__dev_dump(void *dev_private, FILE *f)\n+{\n+\tstruct ioat_dmadev *ioat = dev_private;\n+\tuint64_t chansts_masked = ioat->regs->chansts & IOAT_CHANSTS_STATUS;\n+\tuint32_t chanerr = ioat->regs->chanerr;\n+\tuint64_t mask = (ioat->qcfg.nb_desc - 1);\n+\tchar ver = ioat->version;\n+\tfprintf(f, \"========= IOAT =========\\n\");\n+\tfprintf(f, \" IOAT version: %d.%d\\n\", ver >> 4, ver & 0xF);\n+\tfprintf(f, \" Channel status: %s [0x%\"PRIx64\"]\\n\",\n+\t\t\tchansts_readable[chansts_masked], chansts_masked);\n+\tfprintf(f, \" ChainADDR: 0x%\"PRIu64\"\\n\", ioat->regs->chainaddr);\n+\tif (chanerr == 0) {\n+\t\tfprintf(f, \" No Channel Errors\\n\");\n+\t} else {\n+\t\tfprintf(f, \" ChanERR: 0x%\"PRIu32\"\\n\", chanerr);\n+\t\tif (chanerr & IOAT_CHANERR_INVALID_SRC_ADDR_MASK)\n+\t\t\tfprintf(f, \" Invalid Source Address\\n\");\n+\t\tif (chanerr & IOAT_CHANERR_INVALID_DST_ADDR_MASK)\n+\t\t\tfprintf(f, \" Invalid Destination Address\\n\");\n+\t\tif (chanerr & IOAT_CHANERR_INVALID_LENGTH_MASK)\n+\t\t\tfprintf(f, \" Invalid Descriptor Length\\n\");\n+\t\tif (chanerr & IOAT_CHANERR_DESCRIPTOR_READ_ERROR_MASK)\n+\t\t\tfprintf(f, \" Descriptor Read Error\\n\");\n+\t\tif ((chanerr & ~(IOAT_CHANERR_INVALID_SRC_ADDR_MASK |\n+\t\t\t\tIOAT_CHANERR_INVALID_DST_ADDR_MASK |\n+\t\t\t\tIOAT_CHANERR_INVALID_LENGTH_MASK |\n+\t\t\t\tIOAT_CHANERR_DESCRIPTOR_READ_ERROR_MASK)) != 0)\n+\t\t\tfprintf(f, \" Unknown Error(s)\\n\");\n+\t}\n+\tfprintf(f, \"== Private Data ==\\n\");\n+\tfprintf(f, \" Config: { ring_size: %u }\\n\", ioat->qcfg.nb_desc);\n+\tfprintf(f, \" Status: 0x%\"PRIx64\"\\n\", ioat->status);\n+\tfprintf(f, \" Status IOVA: 0x%\"PRIx64\"\\n\", ioat->status_addr);\n+\tfprintf(f, \" Status ADDR: %p\\n\", &ioat->status);\n+\tfprintf(f, \" Ring IOVA: 0x%\"PRIx64\"\\n\", ioat->ring_addr);\n+\tfprintf(f, \" Ring ADDR: 0x%\"PRIx64\"\\n\", ioat->desc_ring[0].next-64);\n+\tfprintf(f, \" Next write: %\"PRIu16\"\\n\", ioat->next_write);\n+\tfprintf(f, \" Next read: %\"PRIu16\"\\n\", ioat->next_read);\n+\tstruct ioat_dma_hw_desc *desc_ring = &ioat->desc_ring[(ioat->next_write - 1) & mask];\n+\tfprintf(f, \" Last Descriptor Written {\\n\");\n+\tfprintf(f, \" Size: %\"PRIu32\"\\n\", desc_ring->size);\n+\tfprintf(f, \" Control: 0x%\"PRIx32\"\\n\", desc_ring->u.control_raw);\n+\tfprintf(f, \" Src: 0x%\"PRIx64\"\\n\", desc_ring->src_addr);\n+\tfprintf(f, \" Dest: 0x%\"PRIx64\"\\n\", desc_ring->dest_addr);\n+\tfprintf(f, \" Next: 0x%\"PRIx64\"\\n\", desc_ring->next);\n+\tfprintf(f, \" }\\n\");\n+\tfprintf(f, \" Next Descriptor {\\n\");\n+\tfprintf(f, \" Size: %\"PRIu32\"\\n\", ioat->desc_ring[ioat->next_read & mask].size);\n+\tfprintf(f, \" Src: 0x%\"PRIx64\"\\n\", ioat->desc_ring[ioat->next_read & mask].src_addr);\n+\tfprintf(f, \" Dest: 0x%\"PRIx64\"\\n\", ioat->desc_ring[ioat->next_read & mask].dest_addr);\n+\tfprintf(f, \" Next: 0x%\"PRIx64\"\\n\", ioat->desc_ring[ioat->next_read & mask].next);\n+\tfprintf(f, \" }\\n\");\n+\n+\treturn 0;\n+}\n+\n+/* Public wrapper for dump. */\n+static int\n+ioat_dev_dump(const struct rte_dma_dev *dev, FILE *f)\n+{\n+\treturn __dev_dump(dev->fp_obj->dev_private, f);\n+}\n+\n /* Create a DMA device. */\n static int\n ioat_dmadev_create(const char *name, struct rte_pci_device *dev)\n {\n-\tstatic const struct rte_dma_dev_ops ioat_dmadev_ops = { };\n+\tstatic const struct rte_dma_dev_ops ioat_dmadev_ops = {\n+\t\t.dev_dump = ioat_dev_dump,\n+\t};\n \n \tstruct rte_dma_dev *dmadev = NULL;\n \tstruct ioat_dmadev *ioat = NULL;\ndiff --git a/drivers/dma/ioat/ioat_hw_defs.h b/drivers/dma/ioat/ioat_hw_defs.h\nindex 73bdf548b3..dc3493a78f 100644\n--- a/drivers/dma/ioat/ioat_hw_defs.h\n+++ b/drivers/dma/ioat/ioat_hw_defs.h\n@@ -15,6 +15,7 @@ extern \"C\" {\n \n #define IOAT_VER_3_0\t0x30\n #define IOAT_VER_3_3\t0x33\n+#define IOAT_VER_3_4\t0x34\n \n #define IOAT_VENDOR_ID\t\t0x8086\n #define IOAT_DEVICE_ID_SKX\t0x2021\n@@ -43,6 +44,14 @@ extern \"C\" {\n #define IOAT_CHANCTRL_ERR_COMPLETION_EN\t\t\t0x0004\n #define IOAT_CHANCTRL_INT_REARM\t\t\t\t0x0001\n \n+/* DMA Channel Capabilities */\n+#define\tIOAT_DMACAP_PB\t\t(1 << 0)\n+#define\tIOAT_DMACAP_DCA\t\t(1 << 4)\n+#define\tIOAT_DMACAP_BFILL\t(1 << 6)\n+#define\tIOAT_DMACAP_XOR\t\t(1 << 8)\n+#define\tIOAT_DMACAP_PQ\t\t(1 << 9)\n+#define\tIOAT_DMACAP_DMA_DIF\t(1 << 10)\n+\n struct ioat_registers {\n \tuint8_t\t\tchancnt;\n \tuint8_t\t\txfercap;\n@@ -71,8 +80,214 @@ struct ioat_registers {\n #define IOAT_CHANCMD_RESET\t0x20\n #define IOAT_CHANCMD_SUSPEND\t0x04\n \n+#define IOAT_CHANSTS_STATUS\t0x7ULL\n+#define IOAT_CHANSTS_ACTIVE\t0x0\n+#define IOAT_CHANSTS_IDLE\t0x1\n+#define IOAT_CHANSTS_SUSPENDED\t0x2\n+#define IOAT_CHANSTS_HALTED\t0x3\n+#define IOAT_CHANSTS_ARMED\t0x4\n+\n+#define IOAT_CHANERR_INVALID_SRC_ADDR_MASK\t\t(1 << 0)\n+#define IOAT_CHANERR_INVALID_DST_ADDR_MASK\t\t(1 << 1)\n+#define IOAT_CHANERR_DESCRIPTOR_READ_ERROR_MASK\t\t(1 << 8)\n+#define IOAT_CHANERR_INVALID_LENGTH_MASK\t\t(1 << 10)\n+\n+const char *chansts_readable[] = {\n+\t\"ACTIVE\",\t/* 0x0 */\n+\t\"IDLE\",\t\t/* 0x1 */\n+\t\"SUSPENDED\",\t/* 0x2 */\n+\t\"HALTED\",\t/* 0x3 */\n+\t\"ARMED\"\t\t/* 0x4 */\n+};\n+\n+#define IOAT_CHANSTS_UNAFFILIATED_ERROR\t0x8ULL\n+#define IOAT_CHANSTS_SOFT_ERROR\t\t0x10ULL\n+\n+#define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK\t(~0x3FULL)\n+\n #define IOAT_CHANCMP_ALIGN\t8 /* CHANCMP address must be 64-bit aligned */\n \n+struct ioat_dma_hw_desc {\n+\tuint32_t size;\n+\tunion {\n+\t\tuint32_t control_raw;\n+\t\tstruct {\n+\t\t\tuint32_t int_enable: 1;\n+\t\t\tuint32_t src_snoop_disable: 1;\n+\t\t\tuint32_t dest_snoop_disable: 1;\n+\t\t\tuint32_t completion_update: 1;\n+\t\t\tuint32_t fence: 1;\n+\t\t\tuint32_t null: 1;\n+\t\t\tuint32_t src_page_break: 1;\n+\t\t\tuint32_t dest_page_break: 1;\n+\t\t\tuint32_t bundle: 1;\n+\t\t\tuint32_t dest_dca: 1;\n+\t\t\tuint32_t hint: 1;\n+\t\t\tuint32_t reserved: 13;\n+#define IOAT_OP_COPY 0x00\n+\t\t\tuint32_t op: 8;\n+\t\t} control;\n+\t} u;\n+\tuint64_t src_addr;\n+\tuint64_t dest_addr;\n+\tuint64_t next;\n+\tuint64_t reserved;\n+\tuint64_t reserved2;\n+\tuint64_t user1;\n+\tuint64_t user2;\n+};\n+\n+struct ioat_fill_hw_desc {\n+\tuint32_t size;\n+\tunion {\n+\t\tuint32_t control_raw;\n+\t\tstruct {\n+\t\t\tuint32_t int_enable: 1;\n+\t\t\tuint32_t reserved: 1;\n+\t\t\tuint32_t dest_snoop_disable: 1;\n+\t\t\tuint32_t completion_update: 1;\n+\t\t\tuint32_t fence: 1;\n+\t\t\tuint32_t reserved2: 2;\n+\t\t\tuint32_t dest_page_break: 1;\n+\t\t\tuint32_t bundle: 1;\n+\t\t\tuint32_t reserved3: 15;\n+#define IOAT_OP_FILL 0x01\n+\t\t\tuint32_t op: 8;\n+\t\t} control;\n+\t} u;\n+\tuint64_t src_data;\n+\tuint64_t dest_addr;\n+\tuint64_t next;\n+\tuint64_t reserved;\n+\tuint64_t next_dest_addr;\n+\tuint64_t user1;\n+\tuint64_t user2;\n+};\n+\n+struct ioat_xor_hw_desc {\n+\tuint32_t size;\n+\tunion {\n+\t\tuint32_t control_raw;\n+\t\tstruct {\n+\t\t\tuint32_t int_enable: 1;\n+\t\t\tuint32_t src_snoop_disable: 1;\n+\t\t\tuint32_t dest_snoop_disable: 1;\n+\t\t\tuint32_t completion_update: 1;\n+\t\t\tuint32_t fence: 1;\n+\t\t\tuint32_t src_count: 3;\n+\t\t\tuint32_t bundle: 1;\n+\t\t\tuint32_t dest_dca: 1;\n+\t\t\tuint32_t hint: 1;\n+\t\t\tuint32_t reserved: 13;\n+#define IOAT_OP_XOR 0x87\n+#define IOAT_OP_XOR_VAL 0x88\n+\t\t\tuint32_t op: 8;\n+\t\t} control;\n+\t} u;\n+\tuint64_t src_addr;\n+\tuint64_t dest_addr;\n+\tuint64_t next;\n+\tuint64_t src_addr2;\n+\tuint64_t src_addr3;\n+\tuint64_t src_addr4;\n+\tuint64_t src_addr5;\n+};\n+\n+struct ioat_xor_ext_hw_desc {\n+\tuint64_t src_addr6;\n+\tuint64_t src_addr7;\n+\tuint64_t src_addr8;\n+\tuint64_t next;\n+\tuint64_t reserved[4];\n+};\n+\n+struct ioat_pq_hw_desc {\n+\tuint32_t size;\n+\tunion {\n+\t\tuint32_t control_raw;\n+\t\tstruct {\n+\t\t\tuint32_t int_enable: 1;\n+\t\t\tuint32_t src_snoop_disable: 1;\n+\t\t\tuint32_t dest_snoop_disable: 1;\n+\t\t\tuint32_t completion_update: 1;\n+\t\t\tuint32_t fence: 1;\n+\t\t\tuint32_t src_count: 3;\n+\t\t\tuint32_t bundle: 1;\n+\t\t\tuint32_t dest_dca: 1;\n+\t\t\tuint32_t hint: 1;\n+\t\t\tuint32_t p_disable: 1;\n+\t\t\tuint32_t q_disable: 1;\n+\t\t\tuint32_t reserved: 11;\n+#define IOAT_OP_PQ 0x89\n+#define IOAT_OP_PQ_VAL 0x8a\n+\t\t\tuint32_t op: 8;\n+\t\t} control;\n+\t} u;\n+\tuint64_t src_addr;\n+\tuint64_t p_addr;\n+\tuint64_t next;\n+\tuint64_t src_addr2;\n+\tuint64_t src_addr3;\n+\tuint8_t coef[8];\n+\tuint64_t q_addr;\n+};\n+\n+struct ioat_pq_ext_hw_desc {\n+\tuint64_t src_addr4;\n+\tuint64_t src_addr5;\n+\tuint64_t src_addr6;\n+\tuint64_t next;\n+\tuint64_t src_addr7;\n+\tuint64_t src_addr8;\n+\tuint64_t reserved[2];\n+};\n+\n+struct ioat_pq_update_hw_desc {\n+\tuint32_t size;\n+\tunion {\n+\t\tuint32_t control_raw;\n+\t\tstruct {\n+\t\t\tuint32_t int_enable: 1;\n+\t\t\tuint32_t src_snoop_disable: 1;\n+\t\t\tuint32_t dest_snoop_disable: 1;\n+\t\t\tuint32_t completion_update: 1;\n+\t\t\tuint32_t fence: 1;\n+\t\t\tuint32_t src_cnt: 3;\n+\t\t\tuint32_t bundle: 1;\n+\t\t\tuint32_t dest_dca: 1;\n+\t\t\tuint32_t hint: 1;\n+\t\t\tuint32_t p_disable: 1;\n+\t\t\tuint32_t q_disable: 1;\n+\t\t\tuint32_t reserved: 3;\n+\t\t\tuint32_t coef: 8;\n+#define IOAT_OP_PQ_UP 0x8b\n+\t\t\tuint32_t op: 8;\n+\t\t} control;\n+\t} u;\n+\tuint64_t src_addr;\n+\tuint64_t p_addr;\n+\tuint64_t next;\n+\tuint64_t src_addr2;\n+\tuint64_t p_src;\n+\tuint64_t q_src;\n+\tuint64_t q_addr;\n+};\n+\n+union ioat_hw_desc {\n+\tstruct ioat_dma_hw_desc dma;\n+\tstruct ioat_fill_hw_desc fill;\n+\tstruct ioat_xor_hw_desc xor_desc;\n+\tstruct ioat_xor_ext_hw_desc xor_ext;\n+\tstruct ioat_pq_hw_desc pq;\n+\tstruct ioat_pq_ext_hw_desc pq_ext;\n+\tstruct ioat_pq_update_hw_desc pq_update;\n+};\n+\n+#define GENSTS_DEV_STATE_MASK 0x03\n+#define CMDSTATUS_ACTIVE_SHIFT 31\n+#define CMDSTATUS_ACTIVE_MASK (1 << 31)\n+#define CMDSTATUS_ERR_MASK 0xFF\n+\n #ifdef __cplusplus\n }\n #endif\n", "prefixes": [ "v8", "03/12" ] }