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GET /api/patches/101465/?format=api
{ "id": 101465, "url": "http://patches.dpdk.org/api/patches/101465/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211013182720.32486-12-hemant.agrawal@nxp.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211013182720.32486-12-hemant.agrawal@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211013182720.32486-12-hemant.agrawal@nxp.com", "date": "2021-10-13T18:27:16", "name": "[v3,11/15] crypto/dpaa_sec: support raw datapath APIs", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0644de96e0bce53fa82837dfa9bf58580a9d98f9", "submitter": { "id": 477, "url": "http://patches.dpdk.org/api/people/477/?format=api", "name": "Hemant Agrawal", "email": "hemant.agrawal@nxp.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211013182720.32486-12-hemant.agrawal@nxp.com/mbox/", "series": [ { "id": 19612, "url": "http://patches.dpdk.org/api/series/19612/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19612", "date": "2021-10-13T18:27:05", "name": "crypto: add raw vector support in DPAAx", "version": 3, "mbox": "http://patches.dpdk.org/series/19612/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/101465/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/101465/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", 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3PYdMCvN0mLQIHiN7cZToDsgipuw1hpEzKKneIFV4b6wr8DYAIliotqCnh1NXfWksfwwFCJToJzrE5ZUvRkLnqLr9lwdOYrL8mPD4iPs6HXQ0S04tCOW2unj0Mv+hjeF1w+8jt/GU+H5lqwSqe5E0lvXlY0Nrsn0waTFFU3EYIa5iDvMAXvinNfSwoJDWWempJ3GDyk9B851/slv1gSKJASNn3uV4ZmRIL02GFwGqrKP/Gb6fP/Se6wYXpJaS7gdfv6rBl6h4ug/xNL3u0QijlGThU/J0FWA80JmPD9CW23Na0WuJQIBgbsNsufL2JYSm1VF0CanhB2qxxrssLhqIC7BxbbJ9BvaMEPzbbdWmHmiI29f7T73BucXVaKLxiIEoCQTybN3+2PNlB6bHw48BAWtNaUzLEfzSR69Ok5s6UIvq+z2ZsnXaXsM0llJXXrdzWE4Emzd7nHcXoy35vB6/sRG5KiWVKwIkhJOx/k8MlvpqukDIGWBTfaJA2tSMc1Fb4KRTnDFpyyyj1zCIp8gveD1Fr4zXH9Hc/w8QCBh0lsR/bEQiUCOMNvctUqKjCM5s8ffUB8556nqAR7CF9B6C/t8EB/eusuEAggnSTr1tS21Z6uumNy5tF6+bmbzUPvZffvP3640M/1sN8xCRub1htCXy8yAaQNYQT3Aik1ohchR8Y0JTT6QWFpFIkMm6+/0LNYUlMET68PEF83ucQ+cWrVNcII66lsIvhoD9zvmz38aArQyfUsk4eo1lezGcGwBVXDOxrTsjpIbr8HfXNsRLwvzWBbYJ3VhX3/mtBwwfrQiz3DuQVdIwdsnKYp/vXaifc+SHRbkwG0sN8vj9hyrkKQsYhYQalWvRb85XO7RDFd+b/7WctLtHEEy1EGTqmBNJwnTf3Pp1F1XrhiEisH+LU3GIE+d0Y+urM1YmzD/COA+1tTa3vxEunti6ef3H/MqfOYySIlQ4S6UuLdFptFzlKopc6b0mW/qkfNm+q5NQO5xiWwlIh369G+TbVo7qEp6Hb7t5hX7VMPr5XjH/dKpu0qv59jycMFKy3Aq1rcP1/mDUzJzsf4YE2XUGagvxIr/aIZfkpH6wr4fXhulitSt5XFPXizCIk3bxnAhyLcTDKFjvuXf2p9QgPNshNedAfoOdE8R0+KnqvQj88oXJo6KbxWbl9CG+Wp0zvXPSiUlyEQpeoH+UDpri7t1tGgK5ngxVoKSYRC+nDtm98T7c3iSXyhXhh9bW93onuj+52gxKlj99pE6jBpVaI1MJ+4LhdCj9MGdFKsAHdCa/Bq/0iF94ze+ak/Jpc5HRdYX7yrIbZBF+a+wYQvd1vhAWOR1vQi8", "X-OriginatorOrg": "nxp.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 02818216-fe4c-467b-0699-08d98e77c681", "X-MS-Exchange-CrossTenant-AuthSource": "DU2PR04MB8630.eurprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "13 Oct 2021 18:32:13.4064 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n rYq56YhQd2Uqo4kBwiysTJcRLC0CeS9MsGqeGK75GFtg1seh50Vws3rIJCusqWHMyAQ5XsXQd0UMyZnbv9vnwg==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DU2PR04MB8805", "Subject": "[dpdk-dev] [PATCH v3 11/15] crypto/dpaa_sec: support raw datapath\n APIs", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Gagandeep Singh <g.singh@nxp.com>\n\nThis patch add raw vector API framework for dpaa_sec driver.\n\nSigned-off-by: Gagandeep Singh <g.singh@nxp.com>\n---\n doc/guides/rel_notes/release_21_11.rst | 1 +\n drivers/crypto/dpaa_sec/dpaa_sec.c | 23 +-\n drivers/crypto/dpaa_sec/dpaa_sec.h | 39 +-\n drivers/crypto/dpaa_sec/dpaa_sec_raw_dp.c | 485 ++++++++++++++++++++++\n drivers/crypto/dpaa_sec/meson.build | 4 +-\n 5 files changed, 538 insertions(+), 14 deletions(-)\n create mode 100644 drivers/crypto/dpaa_sec/dpaa_sec_raw_dp.c", "diff": "diff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst\nindex b1049a92e3..cc3845c96e 100644\n--- a/doc/guides/rel_notes/release_21_11.rst\n+++ b/doc/guides/rel_notes/release_21_11.rst\n@@ -102,6 +102,7 @@ New Features\n \n * Added DES-CBC, AES-XCBC-MAC, AES-CMAC and non-HMAC algo support.\n * Added PDCP short MAC-I support.\n+ * Added raw vector datapath API support\n \n * **Updated NXP dpaa2_sec crypto PMD.**\n \ndiff --git a/drivers/crypto/dpaa_sec/dpaa_sec.c b/drivers/crypto/dpaa_sec/dpaa_sec.c\nindex d5aa2748d6..c7ef1c7b0f 100644\n--- a/drivers/crypto/dpaa_sec/dpaa_sec.c\n+++ b/drivers/crypto/dpaa_sec/dpaa_sec.c\n@@ -45,10 +45,7 @@\n #include <dpaa_sec_log.h>\n #include <dpaax_iova_table.h>\n \n-static uint8_t cryptodev_driver_id;\n-\n-static int\n-dpaa_sec_attach_sess_q(struct dpaa_sec_qp *qp, dpaa_sec_session *sess);\n+uint8_t dpaa_cryptodev_driver_id;\n \n static inline void\n dpaa_sec_op_ending(struct dpaa_sec_op_ctx *ctx)\n@@ -1787,8 +1784,8 @@ dpaa_sec_enqueue_burst(void *qp, struct rte_crypto_op **ops,\n \t\t\tcase RTE_CRYPTO_OP_WITH_SESSION:\n \t\t\t\tses = (dpaa_sec_session *)\n \t\t\t\t\tget_sym_session_private_data(\n-\t\t\t\t\t\t\top->sym->session,\n-\t\t\t\t\t\t\tcryptodev_driver_id);\n+\t\t\t\t\t\top->sym->session,\n+\t\t\t\t\t\tdpaa_cryptodev_driver_id);\n \t\t\t\tbreak;\n #ifdef RTE_LIB_SECURITY\n \t\t\tcase RTE_CRYPTO_OP_SECURITY_SESSION:\n@@ -2400,7 +2397,7 @@ dpaa_sec_detach_rxq(struct dpaa_sec_dev_private *qi, struct qman_fq *fq)\n \treturn -1;\n }\n \n-static int\n+int\n dpaa_sec_attach_sess_q(struct dpaa_sec_qp *qp, dpaa_sec_session *sess)\n {\n \tint ret;\n@@ -3216,7 +3213,7 @@ dpaa_sec_dev_infos_get(struct rte_cryptodev *dev,\n \t\tinfo->feature_flags = dev->feature_flags;\n \t\tinfo->capabilities = dpaa_sec_capabilities;\n \t\tinfo->sym.max_nb_sessions = internals->max_nb_sessions;\n-\t\tinfo->driver_id = cryptodev_driver_id;\n+\t\tinfo->driver_id = dpaa_cryptodev_driver_id;\n \t}\n }\n \n@@ -3412,7 +3409,10 @@ static struct rte_cryptodev_ops crypto_ops = {\n \t.queue_pair_release = dpaa_sec_queue_pair_release,\n \t.sym_session_get_size = dpaa_sec_sym_session_get_size,\n \t.sym_session_configure = dpaa_sec_sym_session_configure,\n-\t.sym_session_clear = dpaa_sec_sym_session_clear\n+\t.sym_session_clear = dpaa_sec_sym_session_clear,\n+\t/* Raw data-path API related operations */\n+\t.sym_get_raw_dp_ctx_size = dpaa_sec_get_dp_ctx_size,\n+\t.sym_configure_raw_dp_ctx = dpaa_sec_configure_raw_dp_ctx,\n };\n \n #ifdef RTE_LIB_SECURITY\n@@ -3463,7 +3463,7 @@ dpaa_sec_dev_init(struct rte_cryptodev *cryptodev)\n \n \tPMD_INIT_FUNC_TRACE();\n \n-\tcryptodev->driver_id = cryptodev_driver_id;\n+\tcryptodev->driver_id = dpaa_cryptodev_driver_id;\n \tcryptodev->dev_ops = &crypto_ops;\n \n \tcryptodev->enqueue_burst = dpaa_sec_enqueue_burst;\n@@ -3472,6 +3472,7 @@ dpaa_sec_dev_init(struct rte_cryptodev *cryptodev)\n \t\t\tRTE_CRYPTODEV_FF_HW_ACCELERATED |\n \t\t\tRTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |\n \t\t\tRTE_CRYPTODEV_FF_SECURITY |\n+\t\t\tRTE_CRYPTODEV_FF_SYM_RAW_DP |\n \t\t\tRTE_CRYPTODEV_FF_IN_PLACE_SGL |\n \t\t\tRTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT |\n \t\t\tRTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |\n@@ -3637,5 +3638,5 @@ static struct cryptodev_driver dpaa_sec_crypto_drv;\n \n RTE_PMD_REGISTER_DPAA(CRYPTODEV_NAME_DPAA_SEC_PMD, rte_dpaa_sec_driver);\n RTE_PMD_REGISTER_CRYPTO_DRIVER(dpaa_sec_crypto_drv, rte_dpaa_sec_driver.driver,\n-\t\tcryptodev_driver_id);\n+\t\tdpaa_cryptodev_driver_id);\n RTE_LOG_REGISTER(dpaa_logtype_sec, pmd.crypto.dpaa, NOTICE);\ndiff --git a/drivers/crypto/dpaa_sec/dpaa_sec.h b/drivers/crypto/dpaa_sec/dpaa_sec.h\nindex 503047879e..77288cd1eb 100644\n--- a/drivers/crypto/dpaa_sec/dpaa_sec.h\n+++ b/drivers/crypto/dpaa_sec/dpaa_sec.h\n@@ -19,6 +19,8 @@\n #define AES_CTR_IV_LEN\t\t16\n #define AES_GCM_IV_LEN\t\t12\n \n+extern uint8_t dpaa_cryptodev_driver_id;\n+\n #define DPAA_IPv6_DEFAULT_VTC_FLOW\t0x60000000\n \n /* Minimum job descriptor consists of a oneword job descriptor HEADER and\n@@ -117,6 +119,24 @@ struct sec_pdcp_ctxt {\n \tuint32_t hfn_threshold;\t/*!< HFN Threashold for key renegotiation */\n };\n #endif\n+\n+typedef int (*dpaa_sec_build_fd_t)(\n+\tvoid *qp, uint8_t *drv_ctx, struct rte_crypto_vec *data_vec,\n+\tuint16_t n_data_vecs, union rte_crypto_sym_ofs ofs,\n+\tstruct rte_crypto_va_iova_ptr *iv,\n+\tstruct rte_crypto_va_iova_ptr *digest,\n+\tstruct rte_crypto_va_iova_ptr *aad_or_auth_iv,\n+\tvoid *user_data);\n+\n+typedef struct dpaa_sec_job* (*dpaa_sec_build_raw_dp_fd_t)(uint8_t *drv_ctx,\n+\t\t\tstruct rte_crypto_sgl *sgl,\n+\t\t\tstruct rte_crypto_sgl *dest_sgl,\n+\t\t\tstruct rte_crypto_va_iova_ptr *iv,\n+\t\t\tstruct rte_crypto_va_iova_ptr *digest,\n+\t\t\tstruct rte_crypto_va_iova_ptr *auth_iv,\n+\t\t\tunion rte_crypto_sym_ofs ofs,\n+\t\t\tvoid *userdata);\n+\n typedef struct dpaa_sec_session_entry {\n \tstruct sec_cdb cdb;\t/**< cmd block associated with qp */\n \tstruct dpaa_sec_qp *qp[MAX_DPAA_CORES];\n@@ -129,6 +149,8 @@ typedef struct dpaa_sec_session_entry {\n #ifdef RTE_LIB_SECURITY\n \tenum rte_security_session_protocol proto_alg; /*!< Security Algorithm*/\n #endif\n+\tdpaa_sec_build_fd_t build_fd;\n+\tdpaa_sec_build_raw_dp_fd_t build_raw_dp_fd;\n \tunion {\n \t\tstruct {\n \t\t\tuint8_t *data;\t/**< pointer to key data */\n@@ -211,7 +233,10 @@ struct dpaa_sec_job {\n #define DPAA_MAX_NB_MAX_DIGEST\t32\n struct dpaa_sec_op_ctx {\n \tstruct dpaa_sec_job job;\n-\tstruct rte_crypto_op *op;\n+\tunion {\n+\t\tstruct rte_crypto_op *op;\n+\t\tvoid *userdata;\n+\t};\n \tstruct rte_mempool *ctx_pool; /* mempool pointer for dpaa_sec_op_ctx */\n \tuint32_t fd_status;\n \tint64_t vtop_offset;\n@@ -1001,4 +1026,16 @@ calc_chksum(void *buffer, int len)\n \treturn result;\n }\n \n+int\n+dpaa_sec_configure_raw_dp_ctx(struct rte_cryptodev *dev, uint16_t qp_id,\n+\tstruct rte_crypto_raw_dp_ctx *raw_dp_ctx,\n+\tenum rte_crypto_op_sess_type sess_type,\n+\tunion rte_cryptodev_session_ctx session_ctx, uint8_t is_update);\n+\n+int\n+dpaa_sec_get_dp_ctx_size(struct rte_cryptodev *dev);\n+\n+int\n+dpaa_sec_attach_sess_q(struct dpaa_sec_qp *qp, dpaa_sec_session *sess);\n+\n #endif /* _DPAA_SEC_H_ */\ndiff --git a/drivers/crypto/dpaa_sec/dpaa_sec_raw_dp.c b/drivers/crypto/dpaa_sec/dpaa_sec_raw_dp.c\nnew file mode 100644\nindex 0000000000..7376da4cbc\n--- /dev/null\n+++ b/drivers/crypto/dpaa_sec/dpaa_sec_raw_dp.c\n@@ -0,0 +1,485 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2021 NXP\n+ */\n+\n+#include <rte_byteorder.h>\n+#include <rte_common.h>\n+#include <cryptodev_pmd.h>\n+#include <rte_crypto.h>\n+#include <rte_cryptodev.h>\n+#ifdef RTE_LIB_SECURITY\n+#include <rte_security_driver.h>\n+#endif\n+\n+/* RTA header files */\n+#include <desc/ipsec.h>\n+\n+#include <rte_dpaa_bus.h>\n+#include <dpaa_sec.h>\n+#include <dpaa_sec_log.h>\n+\n+struct dpaa_sec_raw_dp_ctx {\n+\tdpaa_sec_session *session;\n+\tuint32_t tail;\n+\tuint32_t head;\n+\tuint16_t cached_enqueue;\n+\tuint16_t cached_dequeue;\n+};\n+\n+static __rte_always_inline int\n+dpaa_sec_raw_enqueue_done(void *qp_data, uint8_t *drv_ctx, uint32_t n)\n+{\n+\tRTE_SET_USED(qp_data);\n+\tRTE_SET_USED(drv_ctx);\n+\tRTE_SET_USED(n);\n+\n+\treturn 0;\n+}\n+\n+static __rte_always_inline int\n+dpaa_sec_raw_dequeue_done(void *qp_data, uint8_t *drv_ctx, uint32_t n)\n+{\n+\tRTE_SET_USED(qp_data);\n+\tRTE_SET_USED(drv_ctx);\n+\tRTE_SET_USED(n);\n+\n+\treturn 0;\n+}\n+\n+static inline struct dpaa_sec_op_ctx *\n+dpaa_sec_alloc_raw_ctx(dpaa_sec_session *ses, int sg_count)\n+{\n+\tstruct dpaa_sec_op_ctx *ctx;\n+\tint i, retval;\n+\n+\tretval = rte_mempool_get(\n+\t\t\tses->qp[rte_lcore_id() % MAX_DPAA_CORES]->ctx_pool,\n+\t\t\t(void **)(&ctx));\n+\tif (!ctx || retval) {\n+\t\tDPAA_SEC_DP_WARN(\"Alloc sec descriptor failed!\");\n+\t\treturn NULL;\n+\t}\n+\t/*\n+\t * Clear SG memory. There are 16 SG entries of 16 Bytes each.\n+\t * one call to dcbz_64() clear 64 bytes, hence calling it 4 times\n+\t * to clear all the SG entries. dpaa_sec_alloc_ctx() is called for\n+\t * each packet, memset is costlier than dcbz_64().\n+\t */\n+\tfor (i = 0; i < sg_count && i < MAX_JOB_SG_ENTRIES; i += 4)\n+\t\tdcbz_64(&ctx->job.sg[i]);\n+\n+\tctx->ctx_pool = ses->qp[rte_lcore_id() % MAX_DPAA_CORES]->ctx_pool;\n+\tctx->vtop_offset = (size_t) ctx - rte_mempool_virt2iova(ctx);\n+\n+\treturn ctx;\n+}\n+\n+static struct dpaa_sec_job *\n+build_dpaa_raw_dp_auth_fd(uint8_t *drv_ctx,\n+\t\t\tstruct rte_crypto_sgl *sgl,\n+\t\t\tstruct rte_crypto_sgl *dest_sgl,\n+\t\t\tstruct rte_crypto_va_iova_ptr *iv,\n+\t\t\tstruct rte_crypto_va_iova_ptr *digest,\n+\t\t\tstruct rte_crypto_va_iova_ptr *auth_iv,\n+\t\t\tunion rte_crypto_sym_ofs ofs,\n+\t\t\tvoid *userdata)\n+{\n+\tRTE_SET_USED(drv_ctx);\n+\tRTE_SET_USED(sgl);\n+\tRTE_SET_USED(dest_sgl);\n+\tRTE_SET_USED(iv);\n+\tRTE_SET_USED(digest);\n+\tRTE_SET_USED(auth_iv);\n+\tRTE_SET_USED(ofs);\n+\tRTE_SET_USED(userdata);\n+\n+\treturn NULL;\n+}\n+\n+static struct dpaa_sec_job *\n+build_dpaa_raw_dp_cipher_fd(uint8_t *drv_ctx,\n+\t\t\tstruct rte_crypto_sgl *sgl,\n+\t\t\tstruct rte_crypto_sgl *dest_sgl,\n+\t\t\tstruct rte_crypto_va_iova_ptr *iv,\n+\t\t\tstruct rte_crypto_va_iova_ptr *digest,\n+\t\t\tstruct rte_crypto_va_iova_ptr *auth_iv,\n+\t\t\tunion rte_crypto_sym_ofs ofs,\n+\t\t\tvoid *userdata)\n+{\n+\tRTE_SET_USED(digest);\n+\tRTE_SET_USED(auth_iv);\n+\tdpaa_sec_session *ses =\n+\t\t((struct dpaa_sec_raw_dp_ctx *)drv_ctx)->session;\n+\tstruct dpaa_sec_job *cf;\n+\tstruct dpaa_sec_op_ctx *ctx;\n+\tstruct qm_sg_entry *sg, *out_sg, *in_sg;\n+\tunsigned int i;\n+\tuint8_t *IV_ptr = iv->va;\n+\tint data_len, total_len = 0, data_offset;\n+\n+\tfor (i = 0; i < sgl->num; i++)\n+\t\ttotal_len += sgl->vec[i].len;\n+\n+\tdata_len = total_len - ofs.ofs.cipher.head - ofs.ofs.cipher.tail;\n+\tdata_offset = ofs.ofs.cipher.head;\n+\n+\t/* Support lengths in bits only for SNOW3G and ZUC */\n+\tif (sgl->num > MAX_SG_ENTRIES) {\n+\t\tDPAA_SEC_DP_ERR(\"Cipher: Max sec segs supported is %d\",\n+\t\t\t\tMAX_SG_ENTRIES);\n+\t\treturn NULL;\n+\t}\n+\n+\tctx = dpaa_sec_alloc_raw_ctx(ses, sgl->num * 2 + 3);\n+\tif (!ctx)\n+\t\treturn NULL;\n+\n+\tcf = &ctx->job;\n+\tctx->userdata = (void *)userdata;\n+\n+\t/* output */\n+\tout_sg = &cf->sg[0];\n+\tout_sg->extension = 1;\n+\tout_sg->length = data_len;\n+\tqm_sg_entry_set64(out_sg, rte_dpaa_mem_vtop(&cf->sg[2]));\n+\tcpu_to_hw_sg(out_sg);\n+\n+\tif (dest_sgl) {\n+\t\t/* 1st seg */\n+\t\tsg = &cf->sg[2];\n+\t\tqm_sg_entry_set64(sg, dest_sgl->vec[0].iova);\n+\t\tsg->length = dest_sgl->vec[0].len - data_offset;\n+\t\tsg->offset = data_offset;\n+\n+\t\t/* Successive segs */\n+\t\tfor (i = 1; i < dest_sgl->num; i++) {\n+\t\t\tcpu_to_hw_sg(sg);\n+\t\t\tsg++;\n+\t\t\tqm_sg_entry_set64(sg, dest_sgl->vec[i].iova);\n+\t\t\tsg->length = dest_sgl->vec[i].len;\n+\t\t}\n+\t} else {\n+\t\t/* 1st seg */\n+\t\tsg = &cf->sg[2];\n+\t\tqm_sg_entry_set64(sg, sgl->vec[0].iova);\n+\t\tsg->length = sgl->vec[0].len - data_offset;\n+\t\tsg->offset = data_offset;\n+\n+\t\t/* Successive segs */\n+\t\tfor (i = 1; i < sgl->num; i++) {\n+\t\t\tcpu_to_hw_sg(sg);\n+\t\t\tsg++;\n+\t\t\tqm_sg_entry_set64(sg, sgl->vec[i].iova);\n+\t\t\tsg->length = sgl->vec[i].len;\n+\t\t}\n+\n+\t}\n+\tsg->final = 1;\n+\tcpu_to_hw_sg(sg);\n+\n+\t/* input */\n+\tin_sg = &cf->sg[1];\n+\tin_sg->extension = 1;\n+\tin_sg->final = 1;\n+\tin_sg->length = data_len + ses->iv.length;\n+\n+\tsg++;\n+\tqm_sg_entry_set64(in_sg, rte_dpaa_mem_vtop(sg));\n+\tcpu_to_hw_sg(in_sg);\n+\n+\t/* IV */\n+\tqm_sg_entry_set64(sg, rte_dpaa_mem_vtop(IV_ptr));\n+\tsg->length = ses->iv.length;\n+\tcpu_to_hw_sg(sg);\n+\n+\t/* 1st seg */\n+\tsg++;\n+\tqm_sg_entry_set64(sg, sgl->vec[0].iova);\n+\tsg->length = sgl->vec[0].len - data_offset;\n+\tsg->offset = data_offset;\n+\n+\t/* Successive segs */\n+\tfor (i = 1; i < sgl->num; i++) {\n+\t\tcpu_to_hw_sg(sg);\n+\t\tsg++;\n+\t\tqm_sg_entry_set64(sg, sgl->vec[i].iova);\n+\t\tsg->length = sgl->vec[i].len;\n+\t}\n+\tsg->final = 1;\n+\tcpu_to_hw_sg(sg);\n+\n+\treturn cf;\n+}\n+\n+static uint32_t\n+dpaa_sec_raw_enqueue_burst(void *qp_data, uint8_t *drv_ctx,\n+\tstruct rte_crypto_sym_vec *vec, union rte_crypto_sym_ofs ofs,\n+\tvoid *user_data[], int *status)\n+{\n+\t/* Function to transmit the frames to given device and queuepair */\n+\tuint32_t loop;\n+\tstruct dpaa_sec_qp *dpaa_qp = (struct dpaa_sec_qp *)qp_data;\n+\tuint16_t num_tx = 0;\n+\tstruct qm_fd fds[DPAA_SEC_BURST], *fd;\n+\tuint32_t frames_to_send;\n+\tstruct dpaa_sec_job *cf;\n+\tdpaa_sec_session *ses =\n+\t\t\t((struct dpaa_sec_raw_dp_ctx *)drv_ctx)->session;\n+\tuint32_t flags[DPAA_SEC_BURST] = {0};\n+\tstruct qman_fq *inq[DPAA_SEC_BURST];\n+\n+\tif (unlikely(!DPAA_PER_LCORE_PORTAL)) {\n+\t\tif (rte_dpaa_portal_init((void *)0)) {\n+\t\t\tDPAA_SEC_ERR(\"Failure in affining portal\");\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\n+\twhile (vec->num) {\n+\t\tframes_to_send = (vec->num > DPAA_SEC_BURST) ?\n+\t\t\t\tDPAA_SEC_BURST : vec->num;\n+\t\tfor (loop = 0; loop < frames_to_send; loop++) {\n+\t\t\tif (unlikely(!ses->qp[rte_lcore_id() % MAX_DPAA_CORES])) {\n+\t\t\t\tif (dpaa_sec_attach_sess_q(dpaa_qp, ses)) {\n+\t\t\t\t\tframes_to_send = loop;\n+\t\t\t\t\tgoto send_pkts;\n+\t\t\t\t}\n+\t\t\t} else if (unlikely(ses->qp[rte_lcore_id() %\n+\t\t\t\t\t\tMAX_DPAA_CORES] != dpaa_qp)) {\n+\t\t\t\tDPAA_SEC_DP_ERR(\"Old:sess->qp = %p\"\n+\t\t\t\t\t\" New qp = %p\\n\",\n+\t\t\t\t\tses->qp[rte_lcore_id() %\n+\t\t\t\t\tMAX_DPAA_CORES], dpaa_qp);\n+\t\t\t\tframes_to_send = loop;\n+\t\t\t\tgoto send_pkts;\n+\t\t\t}\n+\n+\t\t\t/*Clear the unused FD fields before sending*/\n+\t\t\tfd = &fds[loop];\n+\t\t\tmemset(fd, 0, sizeof(struct qm_fd));\n+\t\t\tcf = ses->build_raw_dp_fd(drv_ctx,\n+\t\t\t\t\t\t&vec->src_sgl[loop],\n+\t\t\t\t\t\t&vec->dest_sgl[loop],\n+\t\t\t\t\t\t&vec->iv[loop],\n+\t\t\t\t\t\t&vec->digest[loop],\n+\t\t\t\t\t\t&vec->auth_iv[loop],\n+\t\t\t\t\t\tofs,\n+\t\t\t\t\t\tuser_data[loop]);\n+\t\t\tif (!cf) {\n+\t\t\t\tDPAA_SEC_ERR(\"error: Improper packet contents\"\n+\t\t\t\t\t\" for crypto operation\");\n+\t\t\t\tgoto skip_tx;\n+\t\t\t}\n+\t\t\tinq[loop] = ses->inq[rte_lcore_id() % MAX_DPAA_CORES];\n+\t\t\tfd->opaque_addr = 0;\n+\t\t\tfd->cmd = 0;\n+\t\t\tqm_fd_addr_set64(fd, rte_dpaa_mem_vtop(cf->sg));\n+\t\t\tfd->_format1 = qm_fd_compound;\n+\t\t\tfd->length29 = 2 * sizeof(struct qm_sg_entry);\n+\n+\t\t\tstatus[loop] = 1;\n+\t\t}\n+send_pkts:\n+\t\tloop = 0;\n+\t\twhile (loop < frames_to_send) {\n+\t\t\tloop += qman_enqueue_multi_fq(&inq[loop], &fds[loop],\n+\t\t\t\t\t&flags[loop], frames_to_send - loop);\n+\t\t}\n+\t\tvec->num -= frames_to_send;\n+\t\tnum_tx += frames_to_send;\n+\t}\n+\n+skip_tx:\n+\tdpaa_qp->tx_pkts += num_tx;\n+\tdpaa_qp->tx_errs += vec->num - num_tx;\n+\n+\treturn num_tx;\n+}\n+\n+static int\n+dpaa_sec_deq_raw(struct dpaa_sec_qp *qp, void **out_user_data,\n+\t\tuint8_t is_user_data_array,\n+\t\trte_cryptodev_raw_post_dequeue_t post_dequeue,\n+\t\tint nb_ops)\n+{\n+\tstruct qman_fq *fq;\n+\tunsigned int pkts = 0;\n+\tint num_rx_bufs, ret;\n+\tstruct qm_dqrr_entry *dq;\n+\tuint32_t vdqcr_flags = 0;\n+\tuint8_t is_success = 0;\n+\n+\tfq = &qp->outq;\n+\t/*\n+\t * Until request for four buffers, we provide exact number of buffers.\n+\t * Otherwise we do not set the QM_VDQCR_EXACT flag.\n+\t * Not setting QM_VDQCR_EXACT flag can provide two more buffers than\n+\t * requested, so we request two less in this case.\n+\t */\n+\tif (nb_ops < 4) {\n+\t\tvdqcr_flags = QM_VDQCR_EXACT;\n+\t\tnum_rx_bufs = nb_ops;\n+\t} else {\n+\t\tnum_rx_bufs = nb_ops > DPAA_MAX_DEQUEUE_NUM_FRAMES ?\n+\t\t\t(DPAA_MAX_DEQUEUE_NUM_FRAMES - 2) : (nb_ops - 2);\n+\t}\n+\tret = qman_set_vdq(fq, num_rx_bufs, vdqcr_flags);\n+\tif (ret)\n+\t\treturn 0;\n+\n+\tdo {\n+\t\tconst struct qm_fd *fd;\n+\t\tstruct dpaa_sec_job *job;\n+\t\tstruct dpaa_sec_op_ctx *ctx;\n+\n+\t\tdq = qman_dequeue(fq);\n+\t\tif (!dq)\n+\t\t\tcontinue;\n+\n+\t\tfd = &dq->fd;\n+\t\t/* sg is embedded in an op ctx,\n+\t\t * sg[0] is for output\n+\t\t * sg[1] for input\n+\t\t */\n+\t\tjob = rte_dpaa_mem_ptov(qm_fd_addr_get64(fd));\n+\n+\t\tctx = container_of(job, struct dpaa_sec_op_ctx, job);\n+\t\tctx->fd_status = fd->status;\n+\t\tif (is_user_data_array)\n+\t\t\tout_user_data[pkts] = ctx->userdata;\n+\t\telse\n+\t\t\tout_user_data[0] = ctx->userdata;\n+\n+\t\tif (!ctx->fd_status) {\n+\t\t\tis_success = true;\n+\t\t} else {\n+\t\t\tis_success = false;\n+\t\t\tDPAA_SEC_DP_WARN(\"SEC return err:0x%x\", ctx->fd_status);\n+\t\t}\n+\t\tpost_dequeue(ctx->op, pkts, is_success);\n+\t\tpkts++;\n+\n+\t\t/* report op status to sym->op and then free the ctx memory */\n+\t\trte_mempool_put(ctx->ctx_pool, (void *)ctx);\n+\n+\t\tqman_dqrr_consume(fq, dq);\n+\t} while (fq->flags & QMAN_FQ_STATE_VDQCR);\n+\n+\treturn pkts;\n+}\n+\n+\n+static __rte_always_inline uint32_t\n+dpaa_sec_raw_dequeue_burst(void *qp_data, uint8_t *drv_ctx,\n+\trte_cryptodev_raw_get_dequeue_count_t get_dequeue_count,\n+\tuint32_t max_nb_to_dequeue,\n+\trte_cryptodev_raw_post_dequeue_t post_dequeue,\n+\tvoid **out_user_data, uint8_t is_user_data_array,\n+\tuint32_t *n_success, int *dequeue_status)\n+{\n+\tRTE_SET_USED(drv_ctx);\n+\tRTE_SET_USED(get_dequeue_count);\n+\tuint16_t num_rx;\n+\tstruct dpaa_sec_qp *dpaa_qp = (struct dpaa_sec_qp *)qp_data;\n+\tuint32_t nb_ops = max_nb_to_dequeue;\n+\n+\tif (unlikely(!DPAA_PER_LCORE_PORTAL)) {\n+\t\tif (rte_dpaa_portal_init((void *)0)) {\n+\t\t\tDPAA_SEC_ERR(\"Failure in affining portal\");\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\n+\tnum_rx = dpaa_sec_deq_raw(dpaa_qp, out_user_data,\n+\t\t\tis_user_data_array, post_dequeue, nb_ops);\n+\n+\tdpaa_qp->rx_pkts += num_rx;\n+\t*dequeue_status = 1;\n+\t*n_success = num_rx;\n+\n+\tDPAA_SEC_DP_DEBUG(\"SEC Received %d Packets\\n\", num_rx);\n+\n+\treturn num_rx;\n+}\n+\n+static __rte_always_inline int\n+dpaa_sec_raw_enqueue(void *qp_data, uint8_t *drv_ctx,\n+\tstruct rte_crypto_vec *data_vec,\n+\tuint16_t n_data_vecs, union rte_crypto_sym_ofs ofs,\n+\tstruct rte_crypto_va_iova_ptr *iv,\n+\tstruct rte_crypto_va_iova_ptr *digest,\n+\tstruct rte_crypto_va_iova_ptr *aad_or_auth_iv,\n+\tvoid *user_data)\n+{\n+\tRTE_SET_USED(qp_data);\n+\tRTE_SET_USED(drv_ctx);\n+\tRTE_SET_USED(data_vec);\n+\tRTE_SET_USED(n_data_vecs);\n+\tRTE_SET_USED(ofs);\n+\tRTE_SET_USED(iv);\n+\tRTE_SET_USED(digest);\n+\tRTE_SET_USED(aad_or_auth_iv);\n+\tRTE_SET_USED(user_data);\n+\n+\treturn 0;\n+}\n+\n+static __rte_always_inline void *\n+dpaa_sec_raw_dequeue(void *qp_data, uint8_t *drv_ctx, int *dequeue_status,\n+\tenum rte_crypto_op_status *op_status)\n+{\n+\tRTE_SET_USED(qp_data);\n+\tRTE_SET_USED(drv_ctx);\n+\tRTE_SET_USED(dequeue_status);\n+\tRTE_SET_USED(op_status);\n+\n+\treturn NULL;\n+}\n+\n+int\n+dpaa_sec_configure_raw_dp_ctx(struct rte_cryptodev *dev, uint16_t qp_id,\n+\tstruct rte_crypto_raw_dp_ctx *raw_dp_ctx,\n+\tenum rte_crypto_op_sess_type sess_type,\n+\tunion rte_cryptodev_session_ctx session_ctx, uint8_t is_update)\n+{\n+\tdpaa_sec_session *sess;\n+\tstruct dpaa_sec_raw_dp_ctx *dp_ctx;\n+\tRTE_SET_USED(qp_id);\n+\n+\tif (!is_update) {\n+\t\tmemset(raw_dp_ctx, 0, sizeof(*raw_dp_ctx));\n+\t\traw_dp_ctx->qp_data = dev->data->queue_pairs[qp_id];\n+\t}\n+\n+\tif (sess_type == RTE_CRYPTO_OP_SECURITY_SESSION)\n+\t\tsess = (dpaa_sec_session *)get_sec_session_private_data(\n+\t\t\t\tsession_ctx.sec_sess);\n+\telse if (sess_type == RTE_CRYPTO_OP_WITH_SESSION)\n+\t\tsess = (dpaa_sec_session *)get_sym_session_private_data(\n+\t\t\tsession_ctx.crypto_sess, dpaa_cryptodev_driver_id);\n+\telse\n+\t\treturn -ENOTSUP;\n+\traw_dp_ctx->dequeue_burst = dpaa_sec_raw_dequeue_burst;\n+\traw_dp_ctx->dequeue = dpaa_sec_raw_dequeue;\n+\traw_dp_ctx->dequeue_done = dpaa_sec_raw_dequeue_done;\n+\traw_dp_ctx->enqueue_burst = dpaa_sec_raw_enqueue_burst;\n+\traw_dp_ctx->enqueue = dpaa_sec_raw_enqueue;\n+\traw_dp_ctx->enqueue_done = dpaa_sec_raw_enqueue_done;\n+\n+\tif (sess->ctxt == DPAA_SEC_CIPHER)\n+\t\tsess->build_raw_dp_fd = build_dpaa_raw_dp_cipher_fd;\n+\telse if (sess->ctxt == DPAA_SEC_AUTH)\n+\t\tsess->build_raw_dp_fd = build_dpaa_raw_dp_auth_fd;\n+\telse\n+\t\treturn -ENOTSUP;\n+\tdp_ctx = (struct dpaa_sec_raw_dp_ctx *)raw_dp_ctx->drv_ctx_data;\n+\tdp_ctx->session = sess;\n+\n+\treturn 0;\n+}\n+\n+int\n+dpaa_sec_get_dp_ctx_size(__rte_unused struct rte_cryptodev *dev)\n+{\n+\treturn sizeof(struct dpaa_sec_raw_dp_ctx);\n+}\ndiff --git a/drivers/crypto/dpaa_sec/meson.build b/drivers/crypto/dpaa_sec/meson.build\nindex 44fd60e5ae..f87ad6c7e7 100644\n--- a/drivers/crypto/dpaa_sec/meson.build\n+++ b/drivers/crypto/dpaa_sec/meson.build\n@@ -1,5 +1,5 @@\n # SPDX-License-Identifier: BSD-3-Clause\n-# Copyright 2018 NXP\n+# Copyright 2018-2021 NXP\n \n if not is_linux\n build = false\n@@ -7,7 +7,7 @@ if not is_linux\n endif\n \n deps += ['bus_dpaa', 'mempool_dpaa', 'security']\n-sources = files('dpaa_sec.c')\n+sources = files('dpaa_sec.c', 'dpaa_sec_raw_dp.c')\n \n includes += include_directories('../../bus/dpaa/include')\n includes += include_directories('../../common/dpaax')\n", "prefixes": [ "v3", "11/15" ] }