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{
    "id": 101459,
    "url": "http://patches.dpdk.org/api/patches/101459/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211013182720.32486-6-hemant.agrawal@nxp.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
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        "commit_url_format": ""
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    "msgid": "<20211013182720.32486-6-hemant.agrawal@nxp.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20211013182720.32486-6-hemant.agrawal@nxp.com",
    "date": "2021-10-13T18:27:10",
    "name": "[v3,05/15] crypto/dpaa2_sec: support raw datapath APIs",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "981fb39d470ae64e97c6f830f554ee5794c70762",
    "submitter": {
        "id": 477,
        "url": "http://patches.dpdk.org/api/people/477/?format=api",
        "name": "Hemant Agrawal",
        "email": "hemant.agrawal@nxp.com"
    },
    "delegate": {
        "id": 6690,
        "url": "http://patches.dpdk.org/api/users/6690/?format=api",
        "username": "akhil",
        "first_name": "akhil",
        "last_name": "goyal",
        "email": "gakhil@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211013182720.32486-6-hemant.agrawal@nxp.com/mbox/",
    "series": [
        {
            "id": 19612,
            "url": "http://patches.dpdk.org/api/series/19612/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19612",
            "date": "2021-10-13T18:27:05",
            "name": "crypto: add raw vector support in DPAAx",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/19612/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/101459/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/101459/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Hemant Agrawal <hemant.agrawal@nxp.com>",
        "To": "dev@dpdk.org,\n\tgakhil@marvell.com",
        "Cc": "roy.fan.zhang@intel.com, konstantin.ananyev@intel.com,\n Gagandeep Singh <g.singh@nxp.com>",
        "Date": "Wed, 13 Oct 2021 23:57:10 +0530",
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        "Subject": "[dpdk-dev] [PATCH v3 05/15] crypto/dpaa2_sec: support raw datapath\n APIs",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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    },
    "content": "From: Gagandeep Singh <g.singh@nxp.com>\n\nThis path add framework for raw API support.\nThe initial patch only test cipher only part.\n\nSigned-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>\nSigned-off-by: Gagandeep Singh <g.singh@nxp.com>\n---\n doc/guides/rel_notes/release_21_11.rst      |   1 +\n drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c |  13 +-\n drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h   |  60 +-\n drivers/crypto/dpaa2_sec/dpaa2_sec_raw_dp.c | 595 ++++++++++++++++++++\n drivers/crypto/dpaa2_sec/meson.build        |   3 +-\n 5 files changed, 643 insertions(+), 29 deletions(-)\n create mode 100644 drivers/crypto/dpaa2_sec/dpaa2_sec_raw_dp.c",
    "diff": "diff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst\nindex a8900a3079..b1049a92e3 100644\n--- a/doc/guides/rel_notes/release_21_11.rst\n+++ b/doc/guides/rel_notes/release_21_11.rst\n@@ -106,6 +106,7 @@ New Features\n * **Updated NXP dpaa2_sec crypto PMD.**\n \n   * Added PDCP short MAC-I support.\n+  * Added raw vector datapath API support\n \n * **Updated the turbo_sw bbdev PMD.**\n \ndiff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c\nindex dfa72f3f93..4eb3615250 100644\n--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c\n+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c\n@@ -49,15 +49,8 @@\n #define FSL_MC_DPSECI_DEVID     3\n \n #define NO_PREFETCH 0\n-/* FLE_POOL_NUM_BUFS is set as per the ipsec-secgw application */\n-#define FLE_POOL_NUM_BUFS\t32000\n-#define FLE_POOL_BUF_SIZE\t256\n-#define FLE_POOL_CACHE_SIZE\t512\n-#define FLE_SG_MEM_SIZE(num)\t(FLE_POOL_BUF_SIZE + ((num) * 32))\n-#define SEC_FLC_DHR_OUTBOUND\t-114\n-#define SEC_FLC_DHR_INBOUND\t0\n \n-static uint8_t cryptodev_driver_id;\n+uint8_t cryptodev_driver_id;\n \n #ifdef RTE_LIB_SECURITY\n static inline int\n@@ -3828,6 +3821,9 @@ static struct rte_cryptodev_ops crypto_ops = {\n \t.sym_session_get_size     = dpaa2_sec_sym_session_get_size,\n \t.sym_session_configure    = dpaa2_sec_sym_session_configure,\n \t.sym_session_clear        = dpaa2_sec_sym_session_clear,\n+\t/* Raw data-path API related operations */\n+\t.sym_get_raw_dp_ctx_size = dpaa2_sec_get_dp_ctx_size,\n+\t.sym_configure_raw_dp_ctx = dpaa2_sec_configure_raw_dp_ctx,\n };\n \n #ifdef RTE_LIB_SECURITY\n@@ -3910,6 +3906,7 @@ dpaa2_sec_dev_init(struct rte_cryptodev *cryptodev)\n \t\t\tRTE_CRYPTODEV_FF_HW_ACCELERATED |\n \t\t\tRTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |\n \t\t\tRTE_CRYPTODEV_FF_SECURITY |\n+\t\t\tRTE_CRYPTODEV_FF_SYM_RAW_DP |\n \t\t\tRTE_CRYPTODEV_FF_IN_PLACE_SGL |\n \t\t\tRTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT |\n \t\t\tRTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |\ndiff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h b/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h\nindex 8dee0a4bda..e9b888186e 100644\n--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h\n+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h\n@@ -15,6 +15,16 @@\n #define CRYPTODEV_NAME_DPAA2_SEC_PMD\tcrypto_dpaa2_sec\n /**< NXP DPAA2 - SEC PMD device name */\n \n+extern uint8_t cryptodev_driver_id;\n+\n+/* FLE_POOL_NUM_BUFS is set as per the ipsec-secgw application */\n+#define FLE_POOL_NUM_BUFS\t32000\n+#define FLE_POOL_BUF_SIZE\t256\n+#define FLE_POOL_CACHE_SIZE\t512\n+#define FLE_SG_MEM_SIZE(num)\t(FLE_POOL_BUF_SIZE + ((num) * 32))\n+#define SEC_FLC_DHR_OUTBOUND\t-114\n+#define SEC_FLC_DHR_INBOUND\t0\n+\n #define MAX_QUEUES\t\t64\n #define MAX_DESC_SIZE\t\t64\n /** private data structure for each DPAA2_SEC device */\n@@ -158,6 +168,24 @@ struct dpaa2_pdcp_ctxt {\n \tuint32_t hfn_threshold;\t/*!< HFN Threashold for key renegotiation */\n };\n #endif\n+\n+typedef int (*dpaa2_sec_build_fd_t)(\n+\tvoid *qp, uint8_t *drv_ctx, struct rte_crypto_vec *data_vec,\n+\tuint16_t n_data_vecs, union rte_crypto_sym_ofs ofs,\n+\tstruct rte_crypto_va_iova_ptr *iv,\n+\tstruct rte_crypto_va_iova_ptr *digest,\n+\tstruct rte_crypto_va_iova_ptr *aad_or_auth_iv,\n+\tvoid *user_data);\n+\n+typedef int (*dpaa2_sec_build_raw_dp_fd_t)(uint8_t *drv_ctx,\n+\t\t       struct rte_crypto_sgl *sgl,\n+\t\t       struct rte_crypto_va_iova_ptr *iv,\n+\t\t       struct rte_crypto_va_iova_ptr *digest,\n+\t\t       struct rte_crypto_va_iova_ptr *auth_iv,\n+\t\t       union rte_crypto_sym_ofs ofs,\n+\t\t       void *userdata,\n+\t\t       struct qbman_fd *fd);\n+\n typedef struct dpaa2_sec_session_entry {\n \tvoid *ctxt;\n \tuint8_t ctxt_type;\n@@ -165,6 +193,8 @@ typedef struct dpaa2_sec_session_entry {\n \tenum rte_crypto_cipher_algorithm cipher_alg; /*!< Cipher Algorithm*/\n \tenum rte_crypto_auth_algorithm auth_alg; /*!< Authentication Algorithm*/\n \tenum rte_crypto_aead_algorithm aead_alg; /*!< AEAD Algorithm*/\n+\tdpaa2_sec_build_fd_t build_fd;\n+\tdpaa2_sec_build_raw_dp_fd_t build_raw_dp_fd;\n \tunion {\n \t\tstruct {\n \t\t\tuint8_t *data;\t/**< pointer to key data */\n@@ -547,26 +577,6 @@ static const struct rte_cryptodev_capabilities dpaa2_sec_capabilities[] = {\n \t\t\t}, }\n \t\t}, }\n \t},\n-\t{\t/* NULL (CIPHER) */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n-\t\t\t{.cipher = {\n-\t\t\t\t.algo = RTE_CRYPTO_CIPHER_NULL,\n-\t\t\t\t.block_size = 1,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 0,\n-\t\t\t\t\t.max = 0,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t\t.iv_size = {\n-\t\t\t\t\t.min = 0,\n-\t\t\t\t\t.max = 0,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t}\n-\t\t\t}, },\n-\t\t}, }\n-\t},\n \t{\t/* AES CBC */\n \t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n \t\t{.sym = {\n@@ -983,4 +993,14 @@ calc_chksum(void *buffer, int len)\n \treturn  result;\n }\n \n+int\n+dpaa2_sec_configure_raw_dp_ctx(struct rte_cryptodev *dev, uint16_t qp_id,\n+\tstruct rte_crypto_raw_dp_ctx *raw_dp_ctx,\n+\tenum rte_crypto_op_sess_type sess_type,\n+\tunion rte_cryptodev_session_ctx session_ctx, uint8_t is_update);\n+\n+int\n+dpaa2_sec_get_dp_ctx_size(struct rte_cryptodev *dev);\n+\n+\n #endif /* _DPAA2_SEC_PMD_PRIVATE_H_ */\ndiff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_raw_dp.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_raw_dp.c\nnew file mode 100644\nindex 0000000000..8925c8e938\n--- /dev/null\n+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_raw_dp.c\n@@ -0,0 +1,595 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2021 NXP\n+ */\n+\n+#include <cryptodev_pmd.h>\n+#include <rte_fslmc.h>\n+#include <fslmc_vfio.h>\n+#include <dpaa2_hw_pvt.h>\n+#include <dpaa2_hw_dpio.h>\n+\n+#include \"dpaa2_sec_priv.h\"\n+#include \"dpaa2_sec_logs.h\"\n+\n+struct dpaa2_sec_raw_dp_ctx {\n+\tdpaa2_sec_session *session;\n+\tuint32_t tail;\n+\tuint32_t head;\n+\tuint16_t cached_enqueue;\n+\tuint16_t cached_dequeue;\n+};\n+\n+static int\n+build_raw_dp_chain_fd(uint8_t *drv_ctx,\n+\t\t       struct rte_crypto_sgl *sgl,\n+\t\t       struct rte_crypto_va_iova_ptr *iv,\n+\t\t       struct rte_crypto_va_iova_ptr *digest,\n+\t\t       struct rte_crypto_va_iova_ptr *auth_iv,\n+\t\t       union rte_crypto_sym_ofs ofs,\n+\t\t       void *userdata,\n+\t\t       struct qbman_fd *fd)\n+{\n+\tRTE_SET_USED(drv_ctx);\n+\tRTE_SET_USED(sgl);\n+\tRTE_SET_USED(iv);\n+\tRTE_SET_USED(digest);\n+\tRTE_SET_USED(auth_iv);\n+\tRTE_SET_USED(ofs);\n+\tRTE_SET_USED(userdata);\n+\tRTE_SET_USED(fd);\n+\n+\treturn 0;\n+}\n+\n+static int\n+build_raw_dp_aead_fd(uint8_t *drv_ctx,\n+\t\t       struct rte_crypto_sgl *sgl,\n+\t\t       struct rte_crypto_va_iova_ptr *iv,\n+\t\t       struct rte_crypto_va_iova_ptr *digest,\n+\t\t       struct rte_crypto_va_iova_ptr *auth_iv,\n+\t\t       union rte_crypto_sym_ofs ofs,\n+\t\t       void *userdata,\n+\t\t       struct qbman_fd *fd)\n+{\n+\tRTE_SET_USED(drv_ctx);\n+\tRTE_SET_USED(sgl);\n+\tRTE_SET_USED(iv);\n+\tRTE_SET_USED(digest);\n+\tRTE_SET_USED(auth_iv);\n+\tRTE_SET_USED(ofs);\n+\tRTE_SET_USED(userdata);\n+\tRTE_SET_USED(fd);\n+\n+\treturn 0;\n+}\n+\n+static int\n+build_raw_dp_auth_fd(uint8_t *drv_ctx,\n+\t\t       struct rte_crypto_sgl *sgl,\n+\t\t       struct rte_crypto_va_iova_ptr *iv,\n+\t\t       struct rte_crypto_va_iova_ptr *digest,\n+\t\t       struct rte_crypto_va_iova_ptr *auth_iv,\n+\t\t       union rte_crypto_sym_ofs ofs,\n+\t\t       void *userdata,\n+\t\t       struct qbman_fd *fd)\n+{\n+\tRTE_SET_USED(drv_ctx);\n+\tRTE_SET_USED(sgl);\n+\tRTE_SET_USED(iv);\n+\tRTE_SET_USED(digest);\n+\tRTE_SET_USED(auth_iv);\n+\tRTE_SET_USED(ofs);\n+\tRTE_SET_USED(userdata);\n+\tRTE_SET_USED(fd);\n+\n+\treturn 0;\n+}\n+\n+static int\n+build_raw_dp_proto_fd(uint8_t *drv_ctx,\n+\t\t       struct rte_crypto_sgl *sgl,\n+\t\t       struct rte_crypto_va_iova_ptr *iv,\n+\t\t       struct rte_crypto_va_iova_ptr *digest,\n+\t\t       struct rte_crypto_va_iova_ptr *auth_iv,\n+\t\t       union rte_crypto_sym_ofs ofs,\n+\t\t       void *userdata,\n+\t\t       struct qbman_fd *fd)\n+{\n+\tRTE_SET_USED(drv_ctx);\n+\tRTE_SET_USED(sgl);\n+\tRTE_SET_USED(iv);\n+\tRTE_SET_USED(digest);\n+\tRTE_SET_USED(auth_iv);\n+\tRTE_SET_USED(ofs);\n+\tRTE_SET_USED(userdata);\n+\tRTE_SET_USED(fd);\n+\n+\treturn 0;\n+}\n+\n+static int\n+build_raw_dp_proto_compound_fd(uint8_t *drv_ctx,\n+\t\t       struct rte_crypto_sgl *sgl,\n+\t\t       struct rte_crypto_va_iova_ptr *iv,\n+\t\t       struct rte_crypto_va_iova_ptr *digest,\n+\t\t       struct rte_crypto_va_iova_ptr *auth_iv,\n+\t\t       union rte_crypto_sym_ofs ofs,\n+\t\t       void *userdata,\n+\t\t       struct qbman_fd *fd)\n+{\n+\tRTE_SET_USED(drv_ctx);\n+\tRTE_SET_USED(sgl);\n+\tRTE_SET_USED(iv);\n+\tRTE_SET_USED(digest);\n+\tRTE_SET_USED(auth_iv);\n+\tRTE_SET_USED(ofs);\n+\tRTE_SET_USED(userdata);\n+\tRTE_SET_USED(fd);\n+\n+\treturn 0;\n+}\n+\n+static int\n+build_raw_dp_cipher_fd(uint8_t *drv_ctx,\n+\t\t       struct rte_crypto_sgl *sgl,\n+\t\t       struct rte_crypto_va_iova_ptr *iv,\n+\t\t       struct rte_crypto_va_iova_ptr *digest,\n+\t\t       struct rte_crypto_va_iova_ptr *auth_iv,\n+\t\t       union rte_crypto_sym_ofs ofs,\n+\t\t       void *userdata,\n+\t\t       struct qbman_fd *fd)\n+{\n+\tRTE_SET_USED(digest);\n+\tRTE_SET_USED(auth_iv);\n+\n+\tdpaa2_sec_session *sess =\n+\t\t((struct dpaa2_sec_raw_dp_ctx *)drv_ctx)->session;\n+\tstruct qbman_fle *ip_fle, *op_fle, *sge, *fle;\n+\tint total_len = 0, data_len = 0, data_offset;\n+\tstruct sec_flow_context *flc;\n+\tstruct ctxt_priv *priv = sess->ctxt;\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < sgl->num; i++)\n+\t\ttotal_len += sgl->vec[i].len;\n+\n+\tdata_len = total_len - ofs.ofs.cipher.head - ofs.ofs.cipher.tail;\n+\tdata_offset = ofs.ofs.cipher.head;\n+\n+\tif (sess->cipher_alg == RTE_CRYPTO_CIPHER_SNOW3G_UEA2 ||\n+\t\tsess->cipher_alg == RTE_CRYPTO_CIPHER_ZUC_EEA3) {\n+\t\tif ((data_len & 7) || (data_offset & 7)) {\n+\t\t\tDPAA2_SEC_ERR(\"CIPHER: len/offset must be full bytes\");\n+\t\t\treturn -ENOTSUP;\n+\t\t}\n+\n+\t\tdata_len = data_len >> 3;\n+\t\tdata_offset = data_offset >> 3;\n+\t}\n+\n+\t/* first FLE entry used to store mbuf and session ctxt */\n+\tfle = (struct qbman_fle *)rte_malloc(NULL,\n+\t\t\tFLE_SG_MEM_SIZE(2*sgl->num),\n+\t\t\tRTE_CACHE_LINE_SIZE);\n+\tif (!fle) {\n+\t\tDPAA2_SEC_ERR(\"RAW CIPHER SG: Memory alloc failed for SGE\");\n+\t\treturn -ENOMEM;\n+\t}\n+\tmemset(fle, 0, FLE_SG_MEM_SIZE(2*sgl->num));\n+\t/* first FLE entry used to store userdata and session ctxt */\n+\tDPAA2_SET_FLE_ADDR(fle, (size_t)userdata);\n+\tDPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv);\n+\n+\top_fle = fle + 1;\n+\tip_fle = fle + 2;\n+\tsge = fle + 3;\n+\n+\tflc = &priv->flc_desc[0].flc;\n+\n+\tDPAA2_SEC_DP_DEBUG(\n+\t\t\"RAW CIPHER SG: cipher_off: 0x%x/length %d, ivlen=%d\\n\",\n+\t\tdata_offset,\n+\t\tdata_len,\n+\t\tsess->iv.length);\n+\n+\t/* o/p fle */\n+\tDPAA2_SET_FLE_ADDR(op_fle, DPAA2_VADDR_TO_IOVA(sge));\n+\top_fle->length = data_len;\n+\tDPAA2_SET_FLE_SG_EXT(op_fle);\n+\n+\t/* o/p 1st seg */\n+\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n+\tDPAA2_SET_FLE_OFFSET(sge, data_offset);\n+\tsge->length = sgl->vec[0].len - data_offset;\n+\n+\t/* o/p segs */\n+\tfor (i = 1; i < sgl->num; i++) {\n+\t\tsge++;\n+\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n+\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\tsge->length = sgl->vec[i].len;\n+\t}\n+\tDPAA2_SET_FLE_FIN(sge);\n+\n+\tDPAA2_SEC_DP_DEBUG(\n+\t\t\"RAW CIPHER SG: 1 - flc = %p, fle = %p FLEaddr = %x-%x, len %d\\n\",\n+\t\tflc, fle, fle->addr_hi, fle->addr_lo,\n+\t\tfle->length);\n+\n+\t/* i/p fle */\n+\tsge++;\n+\tDPAA2_SET_FLE_ADDR(ip_fle, DPAA2_VADDR_TO_IOVA(sge));\n+\tip_fle->length = sess->iv.length + data_len;\n+\tDPAA2_SET_FLE_SG_EXT(ip_fle);\n+\n+\t/* i/p IV */\n+\tDPAA2_SET_FLE_ADDR(sge, iv->iova);\n+\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\tsge->length = sess->iv.length;\n+\n+\tsge++;\n+\n+\t/* i/p 1st seg */\n+\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n+\tDPAA2_SET_FLE_OFFSET(sge, data_offset);\n+\tsge->length = sgl->vec[0].len - data_offset;\n+\n+\t/* i/p segs */\n+\tfor (i = 1; i < sgl->num; i++) {\n+\t\tsge++;\n+\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n+\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\tsge->length = sgl->vec[i].len;\n+\t}\n+\tDPAA2_SET_FLE_FIN(sge);\n+\tDPAA2_SET_FLE_FIN(ip_fle);\n+\n+\t/* sg fd */\n+\tDPAA2_SET_FD_ADDR(fd, DPAA2_VADDR_TO_IOVA(op_fle));\n+\tDPAA2_SET_FD_LEN(fd, ip_fle->length);\n+\tDPAA2_SET_FD_COMPOUND_FMT(fd);\n+\tDPAA2_SET_FD_FLC(fd, DPAA2_VADDR_TO_IOVA(flc));\n+\n+\tDPAA2_SEC_DP_DEBUG(\n+\t\t\"RAW CIPHER SG: fdaddr =%\" PRIx64 \" off =%d, len =%d\\n\",\n+\t\tDPAA2_GET_FD_ADDR(fd),\n+\t\tDPAA2_GET_FD_OFFSET(fd),\n+\t\tDPAA2_GET_FD_LEN(fd));\n+\n+\treturn 0;\n+}\n+\n+static __rte_always_inline uint32_t\n+dpaa2_sec_raw_enqueue_burst(void *qp_data, uint8_t *drv_ctx,\n+\tstruct rte_crypto_sym_vec *vec, union rte_crypto_sym_ofs ofs,\n+\tvoid *user_data[], int *status)\n+{\n+\tRTE_SET_USED(user_data);\n+\tuint32_t loop;\n+\tint32_t ret;\n+\tstruct qbman_fd fd_arr[MAX_TX_RING_SLOTS];\n+\tuint32_t frames_to_send, retry_count;\n+\tstruct qbman_eq_desc eqdesc;\n+\tstruct dpaa2_sec_qp *dpaa2_qp = (struct dpaa2_sec_qp *)qp_data;\n+\tdpaa2_sec_session *sess =\n+\t\t((struct dpaa2_sec_raw_dp_ctx *)drv_ctx)->session;\n+\tstruct qbman_swp *swp;\n+\tuint16_t num_tx = 0;\n+\tuint32_t flags[MAX_TX_RING_SLOTS] = {0};\n+\n+\tif (unlikely(vec->num == 0))\n+\t\treturn 0;\n+\n+\tif (sess == NULL) {\n+\t\tDPAA2_SEC_ERR(\"sessionless raw crypto not supported\");\n+\t\treturn 0;\n+\t}\n+\t/*Prepare enqueue descriptor*/\n+\tqbman_eq_desc_clear(&eqdesc);\n+\tqbman_eq_desc_set_no_orp(&eqdesc, DPAA2_EQ_RESP_ERR_FQ);\n+\tqbman_eq_desc_set_response(&eqdesc, 0, 0);\n+\tqbman_eq_desc_set_fq(&eqdesc, dpaa2_qp->tx_vq.fqid);\n+\n+\tif (!DPAA2_PER_LCORE_DPIO) {\n+\t\tret = dpaa2_affine_qbman_swp();\n+\t\tif (ret) {\n+\t\t\tDPAA2_SEC_ERR(\n+\t\t\t\t\"Failed to allocate IO portal, tid: %d\\n\",\n+\t\t\t\trte_gettid());\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\tswp = DPAA2_PER_LCORE_PORTAL;\n+\n+\twhile (vec->num) {\n+\t\tframes_to_send = (vec->num > dpaa2_eqcr_size) ?\n+\t\t\tdpaa2_eqcr_size : vec->num;\n+\n+\t\tfor (loop = 0; loop < frames_to_send; loop++) {\n+\t\t\t/*Clear the unused FD fields before sending*/\n+\t\t\tmemset(&fd_arr[loop], 0, sizeof(struct qbman_fd));\n+\t\t\tret = sess->build_raw_dp_fd(drv_ctx,\n+\t\t\t\t\t\t    &vec->src_sgl[loop],\n+\t\t\t\t\t\t    &vec->iv[loop],\n+\t\t\t\t\t\t    &vec->digest[loop],\n+\t\t\t\t\t\t    &vec->auth_iv[loop],\n+\t\t\t\t\t\t    ofs,\n+\t\t\t\t\t\t    user_data[loop],\n+\t\t\t\t\t\t    &fd_arr[loop]);\n+\t\t\tif (ret) {\n+\t\t\t\tDPAA2_SEC_ERR(\"error: Improper packet contents\"\n+\t\t\t\t\t      \" for crypto operation\");\n+\t\t\t\tgoto skip_tx;\n+\t\t\t}\n+\t\t\tstatus[loop] = 1;\n+\t\t}\n+\n+\t\tloop = 0;\n+\t\tretry_count = 0;\n+\t\twhile (loop < frames_to_send) {\n+\t\t\tret = qbman_swp_enqueue_multiple(swp, &eqdesc,\n+\t\t\t\t\t\t\t &fd_arr[loop],\n+\t\t\t\t\t\t\t &flags[loop],\n+\t\t\t\t\t\t\t frames_to_send - loop);\n+\t\t\tif (unlikely(ret < 0)) {\n+\t\t\t\tretry_count++;\n+\t\t\t\tif (retry_count > DPAA2_MAX_TX_RETRY_COUNT) {\n+\t\t\t\t\tnum_tx += loop;\n+\t\t\t\t\tvec->num -= loop;\n+\t\t\t\t\tgoto skip_tx;\n+\t\t\t\t}\n+\t\t\t} else {\n+\t\t\t\tloop += ret;\n+\t\t\t\tretry_count = 0;\n+\t\t\t}\n+\t\t}\n+\n+\t\tnum_tx += loop;\n+\t\tvec->num -= loop;\n+\t}\n+skip_tx:\n+\tdpaa2_qp->tx_vq.tx_pkts += num_tx;\n+\tdpaa2_qp->tx_vq.err_pkts += vec->num;\n+\n+\treturn num_tx;\n+}\n+\n+static __rte_always_inline int\n+dpaa2_sec_raw_enqueue(void *qp_data, uint8_t *drv_ctx,\n+\tstruct rte_crypto_vec *data_vec,\n+\tuint16_t n_data_vecs, union rte_crypto_sym_ofs ofs,\n+\tstruct rte_crypto_va_iova_ptr *iv,\n+\tstruct rte_crypto_va_iova_ptr *digest,\n+\tstruct rte_crypto_va_iova_ptr *aad_or_auth_iv,\n+\tvoid *user_data)\n+{\n+\tRTE_SET_USED(qp_data);\n+\tRTE_SET_USED(drv_ctx);\n+\tRTE_SET_USED(data_vec);\n+\tRTE_SET_USED(n_data_vecs);\n+\tRTE_SET_USED(ofs);\n+\tRTE_SET_USED(iv);\n+\tRTE_SET_USED(digest);\n+\tRTE_SET_USED(aad_or_auth_iv);\n+\tRTE_SET_USED(user_data);\n+\n+\treturn 0;\n+}\n+\n+static inline void *\n+sec_fd_to_userdata(const struct qbman_fd *fd)\n+{\n+\tstruct qbman_fle *fle;\n+\tvoid *userdata;\n+\tfle = (struct qbman_fle *)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd));\n+\n+\tDPAA2_SEC_DP_DEBUG(\"FLE addr = %x - %x, offset = %x\\n\",\n+\t\t\t   fle->addr_hi, fle->addr_lo, fle->fin_bpid_offset);\n+\tuserdata = (struct rte_crypto_op *)DPAA2_GET_FLE_ADDR((fle - 1));\n+\t/* free the fle memory */\n+\trte_free((void *)(fle-1));\n+\n+\treturn userdata;\n+}\n+\n+static __rte_always_inline uint32_t\n+dpaa2_sec_raw_dequeue_burst(void *qp_data, uint8_t *drv_ctx,\n+\trte_cryptodev_raw_get_dequeue_count_t get_dequeue_count,\n+\tuint32_t max_nb_to_dequeue,\n+\trte_cryptodev_raw_post_dequeue_t post_dequeue,\n+\tvoid **out_user_data, uint8_t is_user_data_array,\n+\tuint32_t *n_success, int *dequeue_status)\n+{\n+\tRTE_SET_USED(drv_ctx);\n+\tRTE_SET_USED(get_dequeue_count);\n+\n+\t/* Function is responsible to receive frames for a given device and VQ*/\n+\tstruct dpaa2_sec_qp *dpaa2_qp = (struct dpaa2_sec_qp *)qp_data;\n+\tstruct qbman_result *dq_storage;\n+\tuint32_t fqid = dpaa2_qp->rx_vq.fqid;\n+\tint ret, num_rx = 0;\n+\tuint8_t is_last = 0, status;\n+\tstruct qbman_swp *swp;\n+\tconst struct qbman_fd *fd;\n+\tstruct qbman_pull_desc pulldesc;\n+\tvoid *user_data;\n+\tuint32_t nb_ops = max_nb_to_dequeue;\n+\n+\tif (!DPAA2_PER_LCORE_DPIO) {\n+\t\tret = dpaa2_affine_qbman_swp();\n+\t\tif (ret) {\n+\t\t\tDPAA2_SEC_ERR(\n+\t\t\t\t\"Failed to allocate IO portal, tid: %d\\n\",\n+\t\t\t\trte_gettid());\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\tswp = DPAA2_PER_LCORE_PORTAL;\n+\tdq_storage = dpaa2_qp->rx_vq.q_storage->dq_storage[0];\n+\n+\tqbman_pull_desc_clear(&pulldesc);\n+\tqbman_pull_desc_set_numframes(&pulldesc,\n+\t\t\t\t      (nb_ops > dpaa2_dqrr_size) ?\n+\t\t\t\t      dpaa2_dqrr_size : nb_ops);\n+\tqbman_pull_desc_set_fq(&pulldesc, fqid);\n+\tqbman_pull_desc_set_storage(&pulldesc, dq_storage,\n+\t\t\t\t    (uint64_t)DPAA2_VADDR_TO_IOVA(dq_storage),\n+\t\t\t\t    1);\n+\n+\t/*Issue a volatile dequeue command. */\n+\twhile (1) {\n+\t\tif (qbman_swp_pull(swp, &pulldesc)) {\n+\t\t\tDPAA2_SEC_WARN(\n+\t\t\t\t\"SEC VDQ command is not issued : QBMAN busy\");\n+\t\t\t/* Portal was busy, try again */\n+\t\t\tcontinue;\n+\t\t}\n+\t\tbreak;\n+\t};\n+\n+\t/* Receive the packets till Last Dequeue entry is found with\n+\t * respect to the above issues PULL command.\n+\t */\n+\twhile (!is_last) {\n+\t\t/* Check if the previous issued command is completed.\n+\t\t * Also seems like the SWP is shared between the Ethernet Driver\n+\t\t * and the SEC driver.\n+\t\t */\n+\t\twhile (!qbman_check_command_complete(dq_storage))\n+\t\t\t;\n+\n+\t\t/* Loop until the dq_storage is updated with\n+\t\t * new token by QBMAN\n+\t\t */\n+\t\twhile (!qbman_check_new_result(dq_storage))\n+\t\t\t;\n+\t\t/* Check whether Last Pull command is Expired and\n+\t\t * setting Condition for Loop termination\n+\t\t */\n+\t\tif (qbman_result_DQ_is_pull_complete(dq_storage)) {\n+\t\t\tis_last = 1;\n+\t\t\t/* Check for valid frame. */\n+\t\t\tstatus = (uint8_t)qbman_result_DQ_flags(dq_storage);\n+\t\t\tif (unlikely(\n+\t\t\t\t(status & QBMAN_DQ_STAT_VALIDFRAME) == 0)) {\n+\t\t\t\tDPAA2_SEC_DP_DEBUG(\"No frame is delivered\\n\");\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\t\t}\n+\n+\t\tfd = qbman_result_DQ_fd(dq_storage);\n+\t\tuser_data = sec_fd_to_userdata(fd);\n+\t\tif (is_user_data_array)\n+\t\t\tout_user_data[num_rx] = user_data;\n+\t\telse\n+\t\t\tout_user_data[0] = user_data;\n+\t\tif (unlikely(fd->simple.frc)) {\n+\t\t\t/* TODO Parse SEC errors */\n+\t\t\tDPAA2_SEC_ERR(\"SEC returned Error - %x\",\n+\t\t\t\t      fd->simple.frc);\n+\t\t\tstatus = RTE_CRYPTO_OP_STATUS_ERROR;\n+\t\t} else {\n+\t\t\tstatus = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+\t\t}\n+\t\tpost_dequeue(user_data, num_rx, status);\n+\n+\t\tnum_rx++;\n+\t\tdq_storage++;\n+\t} /* End of Packet Rx loop */\n+\n+\tdpaa2_qp->rx_vq.rx_pkts += num_rx;\n+\t*dequeue_status = 1;\n+\t*n_success = num_rx;\n+\n+\tDPAA2_SEC_DP_DEBUG(\"SEC Received %d Packets\\n\", num_rx);\n+\t/*Return the total number of packets received to DPAA2 app*/\n+\treturn num_rx;\n+}\n+\n+static __rte_always_inline void *\n+dpaa2_sec_raw_dequeue(void *qp_data, uint8_t *drv_ctx, int *dequeue_status,\n+\t\tenum rte_crypto_op_status *op_status)\n+{\n+\tRTE_SET_USED(qp_data);\n+\tRTE_SET_USED(drv_ctx);\n+\tRTE_SET_USED(dequeue_status);\n+\tRTE_SET_USED(op_status);\n+\n+\treturn NULL;\n+}\n+\n+static __rte_always_inline int\n+dpaa2_sec_raw_enqueue_done(void *qp_data, uint8_t *drv_ctx, uint32_t n)\n+{\n+\tRTE_SET_USED(qp_data);\n+\tRTE_SET_USED(drv_ctx);\n+\tRTE_SET_USED(n);\n+\n+\treturn 0;\n+}\n+\n+static __rte_always_inline int\n+dpaa2_sec_raw_dequeue_done(void *qp_data, uint8_t *drv_ctx, uint32_t n)\n+{\n+\tRTE_SET_USED(qp_data);\n+\tRTE_SET_USED(drv_ctx);\n+\tRTE_SET_USED(n);\n+\n+\treturn 0;\n+}\n+\n+int\n+dpaa2_sec_configure_raw_dp_ctx(struct rte_cryptodev *dev, uint16_t qp_id,\n+\tstruct rte_crypto_raw_dp_ctx *raw_dp_ctx,\n+\tenum rte_crypto_op_sess_type sess_type,\n+\tunion rte_cryptodev_session_ctx session_ctx, uint8_t is_update)\n+{\n+\tdpaa2_sec_session *sess;\n+\tstruct dpaa2_sec_raw_dp_ctx *dp_ctx;\n+\tRTE_SET_USED(qp_id);\n+\n+\tif (!is_update) {\n+\t\tmemset(raw_dp_ctx, 0, sizeof(*raw_dp_ctx));\n+\t\traw_dp_ctx->qp_data = dev->data->queue_pairs[qp_id];\n+\t}\n+\n+\tif (sess_type == RTE_CRYPTO_OP_SECURITY_SESSION)\n+\t\tsess = (dpaa2_sec_session *)get_sec_session_private_data(\n+\t\t\t\tsession_ctx.sec_sess);\n+\telse if (sess_type == RTE_CRYPTO_OP_WITH_SESSION)\n+\t\tsess = (dpaa2_sec_session *)get_sym_session_private_data(\n+\t\t\tsession_ctx.crypto_sess, cryptodev_driver_id);\n+\telse\n+\t\treturn -ENOTSUP;\n+\traw_dp_ctx->dequeue_burst = dpaa2_sec_raw_dequeue_burst;\n+\traw_dp_ctx->dequeue = dpaa2_sec_raw_dequeue;\n+\traw_dp_ctx->dequeue_done = dpaa2_sec_raw_dequeue_done;\n+\traw_dp_ctx->enqueue_burst = dpaa2_sec_raw_enqueue_burst;\n+\traw_dp_ctx->enqueue = dpaa2_sec_raw_enqueue;\n+\traw_dp_ctx->enqueue_done = dpaa2_sec_raw_enqueue_done;\n+\n+\tif (sess->ctxt_type == DPAA2_SEC_CIPHER_HASH)\n+\t\tsess->build_raw_dp_fd = build_raw_dp_chain_fd;\n+\telse if (sess->ctxt_type == DPAA2_SEC_AEAD)\n+\t\tsess->build_raw_dp_fd = build_raw_dp_aead_fd;\n+\telse if (sess->ctxt_type == DPAA2_SEC_AUTH)\n+\t\tsess->build_raw_dp_fd = build_raw_dp_auth_fd;\n+\telse if (sess->ctxt_type == DPAA2_SEC_CIPHER)\n+\t\tsess->build_raw_dp_fd = build_raw_dp_cipher_fd;\n+\telse if (sess->ctxt_type == DPAA2_SEC_IPSEC)\n+\t\tsess->build_raw_dp_fd = build_raw_dp_proto_fd;\n+\telse if (sess->ctxt_type == DPAA2_SEC_PDCP)\n+\t\tsess->build_raw_dp_fd = build_raw_dp_proto_compound_fd;\n+\telse\n+\t\treturn -ENOTSUP;\n+\tdp_ctx = (struct dpaa2_sec_raw_dp_ctx *)raw_dp_ctx->drv_ctx_data;\n+\tdp_ctx->session = sess;\n+\n+\treturn 0;\n+}\n+\n+int\n+dpaa2_sec_get_dp_ctx_size(__rte_unused struct rte_cryptodev *dev)\n+{\n+\treturn sizeof(struct dpaa2_sec_raw_dp_ctx);\n+}\ndiff --git a/drivers/crypto/dpaa2_sec/meson.build b/drivers/crypto/dpaa2_sec/meson.build\nindex ea1d73a13d..e6e5abb3c1 100644\n--- a/drivers/crypto/dpaa2_sec/meson.build\n+++ b/drivers/crypto/dpaa2_sec/meson.build\n@@ -1,5 +1,5 @@\n # SPDX-License-Identifier: BSD-3-Clause\n-# Copyright 2018 NXP\n+# Copyright 2018,2021 NXP\n \n if not is_linux\n     build = false\n@@ -9,6 +9,7 @@ endif\n deps += ['security', 'mempool_dpaa2']\n sources = files(\n         'dpaa2_sec_dpseci.c',\n+\t'dpaa2_sec_raw_dp.c',\n         'mc/dpseci.c',\n )\n \n",
    "prefixes": [
        "v3",
        "05/15"
    ]
}