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GET /api/patches/100219/?format=api
{ "id": 100219, "url": "http://patches.dpdk.org/api/patches/100219/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211001095130.3343083-2-radu.nicolau@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211001095130.3343083-2-radu.nicolau@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211001095130.3343083-2-radu.nicolau@intel.com", "date": "2021-10-01T09:51:25", "name": "[v4,1/6] common/iavf: add iAVF IPsec inline crypto support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e46ea972b6dfae3c585197163a343146bf9e7d8e", "submitter": { "id": 743, "url": "http://patches.dpdk.org/api/people/743/?format=api", "name": "Radu Nicolau", "email": "radu.nicolau@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211001095130.3343083-2-radu.nicolau@intel.com/mbox/", "series": [ { "id": 19321, "url": "http://patches.dpdk.org/api/series/19321/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19321", "date": "2021-10-01T09:51:24", "name": "iavf: add iAVF IPsec inline crypto support", "version": 4, "mbox": "http://patches.dpdk.org/series/19321/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/100219/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/100219/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5BEFAA0032;\n\tFri, 1 Oct 2021 12:02:10 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id F0F944115E;\n\tFri, 1 Oct 2021 12:01:52 +0200 (CEST)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n by mails.dpdk.org (Postfix) with ESMTP id A18AF41144\n for <dev@dpdk.org>; Fri, 1 Oct 2021 12:01:50 +0200 (CEST)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 01 Oct 2021 03:01:38 -0700", "from silpixa00400884.ir.intel.com ([10.243.22.82])\n by FMSMGA003.fm.intel.com with ESMTP; 01 Oct 2021 03:01:36 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10123\"; a=\"310931181\"", "E=Sophos;i=\"5.85,337,1624345200\"; d=\"scan'208\";a=\"310931181\"", "E=Sophos;i=\"5.85,337,1624345200\"; d=\"scan'208\";a=\"556222456\"" ], "X-ExtLoop1": "1", "From": "Radu Nicolau <radu.nicolau@intel.com>", "To": "Jingjing Wu <jingjing.wu@intel.com>,\n\tBeilei Xing <beilei.xing@intel.com>", "Cc": "dev@dpdk.org, declan.doherty@intel.com, abhijit.sinha@intel.com,\n qi.z.zhang@intel.com, bruce.richardson@intel.com,\n konstantin.ananyev@intel.com, Radu Nicolau <radu.nicolau@intel.com>", "Date": "Fri, 1 Oct 2021 10:51:25 +0100", "Message-Id": "<20211001095130.3343083-2-radu.nicolau@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20211001095130.3343083-1-radu.nicolau@intel.com>", "References": "<20210909142428.750634-1-radu.nicolau@intel.com>\n <20211001095130.3343083-1-radu.nicolau@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v4 1/6] common/iavf: add iAVF IPsec inline crypto\n support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add support for inline crypto for IPsec.\n\nSigned-off-by: Declan Doherty <declan.doherty@intel.com>\nSigned-off-by: Abhijit Sinha <abhijit.sinha@intel.com>\nSigned-off-by: Radu Nicolau <radu.nicolau@intel.com>\n---\n drivers/common/iavf/iavf_type.h | 215 +++++++-\n drivers/common/iavf/virtchnl.h | 17 +-\n drivers/common/iavf/virtchnl_inline_ipsec.h | 553 ++++++++++++++++++++\n 3 files changed, 775 insertions(+), 10 deletions(-)\n create mode 100644 drivers/common/iavf/virtchnl_inline_ipsec.h", "diff": "diff --git a/drivers/common/iavf/iavf_type.h b/drivers/common/iavf/iavf_type.h\nindex 73dfb47e70..1f8f8ae5fd 100644\n--- a/drivers/common/iavf/iavf_type.h\n+++ b/drivers/common/iavf/iavf_type.h\n@@ -709,11 +709,29 @@ enum iavf_rx_prog_status_desc_error_bits {\n #define IAVF_FOUR_BIT_MASK\t0xF\n #define IAVF_EIGHTEEN_BIT_MASK\t0x3FFFF\n \n-/* TX Descriptor */\n+/* TX Data Descriptor */\n struct iavf_tx_desc {\n-\t__le64 buffer_addr; /* Address of descriptor's data buf */\n-\t__le64 cmd_type_offset_bsz;\n-};\n+\tunion {\n+\t\tstruct {\n+\t\t\t__le64 buffer_addr; /* Addr of descriptor's data buf */\n+\t\t\t__le64 cmd_type_offset_bsz;\n+\t\t};\n+\t\tstruct {\n+\t\t\t__le64 qw0; /**< data buffer address */\n+\t\t\t__le64 qw1; /**< dtyp, cmd, offset, buf_sz and l2tag1 */\n+\t\t};\n+\t\tstruct {\n+\t\t\t__le64 buffer_addr;\t/**< Data buffer address */\n+\t\t\t__le64 type:4;\t\t/**< Descriptor type */\n+\t\t\t__le64 cmd:12;\t\t/**< Command field */\n+\t\t\t__le64 offset_l2len:7;\t/**< L2 header length */\n+\t\t\t__le64 offset_l3len:7;\t/**< L3 header length */\n+\t\t\t__le64 offset_l4len:4;\t/**< L4 header length */\n+\t\t\t__le64 buffer_sz:14;\t/**< Data buffer size */\n+\t\t\t__le64 l2tag1:16;\t/**< L2 Tag 1 value */\n+\t\t} debug __rte_packed;\n+\t};\n+} __rte_packed;\n \n #define IAVF_TXD_QW1_DTYPE_SHIFT\t0\n #define IAVF_TXD_QW1_DTYPE_MASK\t\t(0xFUL << IAVF_TXD_QW1_DTYPE_SHIFT)\n@@ -723,6 +741,7 @@ enum iavf_tx_desc_dtype_value {\n \tIAVF_TX_DESC_DTYPE_NOP\t\t= 0x1, /* same as Context desc */\n \tIAVF_TX_DESC_DTYPE_CONTEXT\t= 0x1,\n \tIAVF_TX_DESC_DTYPE_FCOE_CTX\t= 0x2,\n+\tIAVF_TX_DESC_DTYPE_IPSEC\t= 0x3,\n \tIAVF_TX_DESC_DTYPE_FILTER_PROG\t= 0x8,\n \tIAVF_TX_DESC_DTYPE_DDP_CTX\t= 0x9,\n \tIAVF_TX_DESC_DTYPE_FLEX_DATA\t= 0xB,\n@@ -734,7 +753,7 @@ enum iavf_tx_desc_dtype_value {\n #define IAVF_TXD_QW1_CMD_SHIFT\t4\n #define IAVF_TXD_QW1_CMD_MASK\t(0x3FFUL << IAVF_TXD_QW1_CMD_SHIFT)\n \n-enum iavf_tx_desc_cmd_bits {\n+enum iavf_tx_data_desc_cmd_bits {\n \tIAVF_TX_DESC_CMD_EOP\t\t\t= 0x0001,\n \tIAVF_TX_DESC_CMD_RS\t\t\t= 0x0002,\n \tIAVF_TX_DESC_CMD_ICRC\t\t\t= 0x0004,\n@@ -778,18 +797,79 @@ enum iavf_tx_desc_length_fields {\n #define IAVF_TXD_QW1_L2TAG1_SHIFT\t48\n #define IAVF_TXD_QW1_L2TAG1_MASK\t(0xFFFFULL << IAVF_TXD_QW1_L2TAG1_SHIFT)\n \n+#define IAVF_TXD_DATA_QW1_DTYPE_SHIFT\t(0)\n+#define IAVF_TXD_DATA_QW1_DTYPE_MASK\t(0xFUL << IAVF_TXD_QW1_DTYPE_SHIFT)\n+\n+#define IAVF_TXD_DATA_QW1_CMD_SHIFT\t(4)\n+#define IAVF_TXD_DATA_QW1_CMD_MASK\t(0x3FFUL << IAVF_TXD_DATA_QW1_CMD_SHIFT)\n+\n+#define IAVF_TXD_DATA_QW1_OFFSET_SHIFT\t(16)\n+#define IAVF_TXD_DATA_QW1_OFFSET_MASK\t(0x3FFFFULL << \\\n+\t\t\t\t\tIAVF_TXD_DATA_QW1_OFFSET_SHIFT)\n+\n+#define IAVF_TXD_DATA_QW1_OFFSET_MACLEN_SHIFT\t(IAVF_TXD_DATA_QW1_OFFSET_SHIFT)\n+#define IAVF_TXD_DATA_QW1_OFFSET_MACLEN_MASK\t\\\n+\t(0x7FUL << IAVF_TXD_DATA_QW1_OFFSET_MACLEN_SHIFT)\n+\n+#define IAVF_TXD_DATA_QW1_OFFSET_IPLEN_SHIFT\t\\\n+\t(IAVF_TXD_DATA_QW1_OFFSET_SHIFT + IAVF_TX_DESC_LENGTH_IPLEN_SHIFT)\n+#define IAVF_TXD_DATA_QW1_OFFSET_IPLEN_MASK\t\\\n+\t(0x7FUL << IAVF_TXD_DATA_QW1_OFFSET_IPLEN_SHIFT)\n+\n+#define IAVF_TXD_DATA_QW1_OFFSET_L4LEN_SHIFT\t\\\n+\t(IAVF_TXD_DATA_QW1_OFFSET_SHIFT + IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)\n+#define IAVF_TXD_DATA_QW1_OFFSET_L4LEN_MASK\t\\\n+\t(0xFUL << IAVF_TXD_DATA_QW1_OFFSET_L4LEN_SHIFT)\n+\n+#define IAVF_TXD_DATA_QW1_MACLEN_MASK\t\\\n+\t(0x7FUL << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT)\n+#define IAVF_TXD_DATA_QW1_IPLEN_MASK\t\\\n+\t(0x7FUL << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT)\n+#define IAVF_TXD_DATA_QW1_L4LEN_MASK\t\\\n+\t(0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)\n+#define IAVF_TXD_DATA_QW1_FCLEN_MASK\t\\\n+\t(0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)\n+\n+#define IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT\t(34)\n+#define IAVF_TXD_DATA_QW1_TX_BUF_SZ_MASK\t\\\n+\t(0x3FFFULL << IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT)\n+\n+#define IAVF_TXD_DATA_QW1_L2TAG1_SHIFT\t\t(48)\n+#define IAVF_TXD_DATA_QW1_L2TAG1_MASK\t\t\\\n+\t(0xFFFFULL << IAVF_TXD_DATA_QW1_L2TAG1_SHIFT)\n+\n /* Context descriptors */\n struct iavf_tx_context_desc {\n+\tunion {\n+\t\tstruct {\n \t__le32 tunneling_params;\n \t__le16 l2tag2;\n \t__le16 rsvd;\n \t__le64 type_cmd_tso_mss;\n };\n-\n-#define IAVF_TXD_CTX_QW1_DTYPE_SHIFT\t0\n+\t\tstruct {\n+\t\t\t__le64 qw0;\n+\t\t\t__le64 qw1;\n+\t\t};\n+\t\tstruct {\n+\t\t\t__le32 tunneling;\n+\t\t\t__le16 l2tag2;\n+\t\t\t__le16 rsvd0;\n+\t\t\t__le64 type:4;\n+\t\t\t__le64 cmd:7;\n+\t\t\t__le64 ipsec:7;\n+\t\t\t__le64 rsvd1:12;\n+\t\t\t__le64 tlen_tsyn:18;\n+\t\t\t__le64 rsvd2:2;\n+\t\t\t__le64 mss_target_vsi:14;\n+\t\t} debug __rte_packed;\n+\t};\n+} __rte_packed;\n+\n+#define IAVF_TXD_CTX_QW1_DTYPE_SHIFT\t(0)\n #define IAVF_TXD_CTX_QW1_DTYPE_MASK\t(0xFUL << IAVF_TXD_CTX_QW1_DTYPE_SHIFT)\n \n-#define IAVF_TXD_CTX_QW1_CMD_SHIFT\t4\n+#define IAVF_TXD_CTX_QW1_CMD_SHIFT\t(4)\n #define IAVF_TXD_CTX_QW1_CMD_MASK\t(0xFFFFUL << IAVF_TXD_CTX_QW1_CMD_SHIFT)\n \n enum iavf_tx_ctx_desc_cmd_bits {\n@@ -804,6 +884,63 @@ enum iavf_tx_ctx_desc_cmd_bits {\n \tIAVF_TX_CTX_DESC_SWPE\t\t= 0x40\n };\n \n+#define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_SHIFT\t(11)\n+#define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_MASK\t\\\n+\t(0x7UL << IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_SHIFT)\n+\n+#define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_ICVLEN_SHIFT\t(14)\n+#define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_ICVLEN_MASK\t\\\n+\t(0xFUL << IAVF_TXD_CTX_QW1_IPSEC_PARAMS_ICVLEN_SHIFT)\n+\n+#define IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_SHIFT\t\t(30)\n+#define IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_MASK\t\t\\\n+\t(0x3FFFFUL << IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_SHIFT)\n+\n+#define IAVF_TXD_CTX_QW1_TSYNC_PARAMS_TLEN_SHIFT\t(30)\n+#define IAVF_TXD_CTX_QW1_TSYNC_PARAMS_TLEN_MASK\t\t\\\n+\t(0x3FUL << IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_SHIFT)\n+\n+#define IAVF_TXD_CTX_QW1_SEG_PARAMS_MSS_SHIFT\t\t(50)\n+#define IAVF_TXD_CTX_QW1_SEG_PARAMS_MSS_MASK\t\t\\\n+\t(0x3FFFUL << IAVF_TXD_CTX_QW1_SEG_PARAMS_MSS_SHIFT)\n+\n+#define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPT_SHIFT\t\t(0)\n+#define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPT_MASK\t\t(0x3UL)\n+\n+enum iavf_tx_ctx_desc_tunnel_external_ip_type {\n+\tIAVF_TX_CTX_DESC_EIPT_NONE,\n+\tIAVF_TX_CTX_DESC_EIPT_IPV6,\n+\tIAVF_TX_CTX_DESC_EIPT_IPV4_NO_CHECKSUM_OFFLOAD,\n+\tIAVF_TX_CTX_DESC_EIPT_IPV4_CHECKSUM_OFFLOAD\n+};\n+\n+#define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPLEN_SHIFT\t(2)\n+#define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPLEN_MASK\t\t(0x7FUL)\n+\n+#define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNT_SHIFT\t(9)\n+#define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNT_MASK\t\t(0x3UL)\n+\n+enum iavf_tx_ctx_desc_tunnel_l4_tunnel_type {\n+\tIAVF_TX_CTX_DESC_L4_TUN_TYP_NO_UDP_GRE,\n+\tIAVF_TX_CTX_DESC_L4_TUN_TYP_UDP,\n+\tIAVF_TX_CTX_DESC_L4_TUN_TYP_GRE\n+};\n+\n+#define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIP_NOINC_SHIFT\t(11)\n+#define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIP_NOINC_MASK\t(0x1UL)\n+\n+#define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNLEN_SHIFT\t(12)\n+#define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNLEN_MASK\t(0x7FUL)\n+\n+#define IAVF_TXD_CTX_QW0_TUN_PARAMS_DECTTL_SHIFT\t(19)\n+#define IAVF_TXD_CTX_QW0_TUN_PARAMS_DECTTL_MASK\t\t(0xFUL)\n+\n+#define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4T_CS_SHIFT\t(23)\n+#define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4T_CS_MASK\t\t(0x1UL)\n+\n+#define IAVF_TXD_CTX_QW0_L2TAG2_PARAM\t\t\t(32)\n+#define IAVF_TXD_CTX_QW0_L2TAG2_MASK\t\t\t(0xFFFFUL)\n+\n struct iavf_nop_desc {\n \t__le64 rsvd;\n \t__le64 dtype_cmd;\n@@ -911,6 +1048,68 @@ enum iavf_tx_ctx_desc_eipt_offload {\n #define IAVF_TXD_CTX_QW0_L4T_CS_SHIFT\t23\n #define IAVF_TXD_CTX_QW0_L4T_CS_MASK\tBIT_ULL(IAVF_TXD_CTX_QW0_L4T_CS_SHIFT)\n \n+\n+struct iavf_tx_ipsec_desc {\n+\tunion {\n+\t\tstruct {\n+\t\t\t__le64 qw0;\n+\t\t\t__le64 qw1;\n+\t\t};\n+\t\tstruct {\n+\t\t\t__le16 l4payload_length;\n+\t\t\t__le32 esn;\n+\t\t\t__le16 trailer_length;\n+\t\t\tu8 type:4;\n+\t\t\tu8 rsv:1;\n+\t\t\tu8 udp:1;\n+\t\t\tu8 ivlen:2;\n+\t\t\tu8 next_header;\n+\t\t\t__le16 ipv6_ext_hdr_length;\n+\t\t\t__le32 said;\n+\t\t} __rte_packed;\n+\t};\n+} __rte_packed;\n+\n+#define IAVF_IPSEC_TX_DESC_QW0_L4PAYLEN_SHIFT 0\n+#define IAVF_IPSEC_TX_DESC_QW0_L4PAYLEN_MASK (0x3FFFULL << \\\n+\t\t\tIAVF_IPSEC_TX_DESC_QW0_L4PAYLEN_SHIFT)\n+\n+#define IAVF_IPSEC_TX_DESC_QW0_IPSECESN_SHIFT 16\n+#define IAVF_IPSEC_TX_DESC_QW0_IPSECESN_MASK (0xFFFFFFFFULL << \\\n+\t\t\tIAVF_IPSEC_TX_DESC_QW0_IPSECESN_SHIFT)\n+\n+#define IAVF_IPSEC_TX_DESC_QW0_TRAILERLEN_SHIFT 48\n+#define IAVF_IPSEC_TX_DESC_QW0_TRAILERLEN_MASK (0x3FULL << \\\n+\t\t\tIAVF_IPSEC_TX_DESC_QW0_TRAILERLEN_SHIFT)\n+\n+#define IAVF_IPSEC_TX_DESC_QW1_UDP_SHIFT 5\n+#define IAVF_IPSEC_TX_DESC_QW1_UDP_MASK (0x1ULL << \\\n+\t\t\tIAVF_IPSEC_TX_DESC_QW1_UDP_SHIFT)\n+\n+#define IAVF_IPSEC_TX_DESC_QW1_IVLEN_SHIFT 6\n+#define IAVF_IPSEC_TX_DESC_QW1_IVLEN_MASK (0x3ULL << \\\n+\t\t\tIAVF_IPSEC_TX_DESC_QW1_IVLEN_SHIFT)\n+\n+#define IAVF_IPSEC_TX_DESC_QW1_IPSECNH_SHIFT 8\n+#define IAVF_IPSEC_TX_DESC_QW1_IPSECNH_MASK (0xFFULL << \\\n+\t\t\tIAVF_IPSEC_TX_DESC_QW1_IPSECNH_SHIFT)\n+\n+#define IAVF_IPSEC_TX_DESC_QW1_EXTLEN_SHIFT 16\n+#define IAVF_IPSEC_TX_DESC_QW1_EXTLEN_MASK (0xFFULL << \\\n+\t\t\tIAVF_IPSEC_TX_DESC_QW1_EXTLEN_SHIFT)\n+\n+#define IAVF_IPSEC_TX_DESC_QW1_IPSECSA_SHIFT 32\n+#define IAVF_IPSEC_TX_DESC_QW1_IPSECSA_MASK (0xFFFFFULL << \\\n+\t\t\tIAVF_IPSEC_TX_DESC_QW1_IPSECSA_SHIFT)\n+\n+/* Initialization Vector Length type */\n+enum iavf_ipsec_iv_len {\n+\tIAVF_IPSEC_IV_LEN_NONE,\t\t/* No IV */\n+\tIAVF_IPSEC_IV_LEN_DW,\t\t/* 4B IV */\n+\tIAVF_IPSEC_IV_LEN_DDW,\t\t/* 8B IV */\n+\tIAVF_IPSEC_IV_LEN_QDW,\t\t/* 16B IV */\n+};\n+\n /* Statistics collected by each port, VSI, VEB, and S-channel */\n struct iavf_eth_stats {\n \tu64 rx_bytes;\t\t\t/* gorc */\ndiff --git a/drivers/common/iavf/virtchnl.h b/drivers/common/iavf/virtchnl.h\nindex 83f51d889f..5cc326c035 100644\n--- a/drivers/common/iavf/virtchnl.h\n+++ b/drivers/common/iavf/virtchnl.h\n@@ -38,6 +38,8 @@\n * value in current and future projects\n */\n \n+#include \"virtchnl_inline_ipsec.h\"\n+\n /* Error Codes */\n enum virtchnl_status_code {\n \tVIRTCHNL_STATUS_SUCCESS\t\t\t\t= 0,\n@@ -133,7 +135,8 @@ enum virtchnl_ops {\n \tVIRTCHNL_OP_DISABLE_CHANNELS = 31,\n \tVIRTCHNL_OP_ADD_CLOUD_FILTER = 32,\n \tVIRTCHNL_OP_DEL_CLOUD_FILTER = 33,\n-\t/* opcodes 34, 35, 36, and 37 are reserved */\n+\tVIRTCHNL_OP_INLINE_IPSEC_CRYPTO = 34,\n+\t/* opcodes 35 and 36 are reserved */\n \tVIRTCHNL_OP_DCF_CONFIG_BW = 37,\n \tVIRTCHNL_OP_DCF_VLAN_OFFLOAD = 38,\n \tVIRTCHNL_OP_DCF_CMD_DESC = 39,\n@@ -225,6 +228,8 @@ static inline const char *virtchnl_op_str(enum virtchnl_ops v_opcode)\n \t\treturn \"VIRTCHNL_OP_ADD_CLOUD_FILTER\";\n \tcase VIRTCHNL_OP_DEL_CLOUD_FILTER:\n \t\treturn \"VIRTCHNL_OP_DEL_CLOUD_FILTER\";\n+\tcase VIRTCHNL_OP_INLINE_IPSEC_CRYPTO:\n+\t\treturn \"VIRTCHNL_OP_INLINE_IPSEC_CRYPTO\";\n \tcase VIRTCHNL_OP_DCF_CMD_DESC:\n \t\treturn \"VIRTCHNL_OP_DCF_CMD_DESC\";\n \tcase VIRTCHNL_OP_DCF_CMD_BUFF:\n@@ -385,7 +390,7 @@ VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_vsi_resource);\n #define VIRTCHNL_VF_OFFLOAD_REQ_QUEUES\t\tBIT(6)\n /* used to negotiate communicating link speeds in Mbps */\n #define VIRTCHNL_VF_CAP_ADV_LINK_SPEED\t\tBIT(7)\n-\t/* BIT(8) is reserved */\n+#define VIRTCHNL_VF_OFFLOAD_INLINE_IPSEC_CRYPTO\tBIT(8)\n #define VIRTCHNL_VF_LARGE_NUM_QPAIRS\t\tBIT(9)\n #define VIRTCHNL_VF_OFFLOAD_CRC\t\t\tBIT(10)\n #define VIRTCHNL_VF_OFFLOAD_VLAN_V2\t\tBIT(15)\n@@ -2290,6 +2295,14 @@ virtchnl_vc_validate_vf_msg(struct virtchnl_version_info *ver, u32 v_opcode,\n \t\t\t\t sizeof(struct virtchnl_queue_vector);\n \t\t}\n \t\tbreak;\n+\n+\tcase VIRTCHNL_OP_INLINE_IPSEC_CRYPTO:\n+\t{\n+\t\tstruct inline_ipsec_msg *iim = (struct inline_ipsec_msg *)msg;\n+\t\tvalid_len =\n+\t\t\tvirtchnl_inline_ipsec_val_msg_len(iim->ipsec_opcode);\n+\t\tbreak;\n+\t}\n \t/* These are always errors coming from the VF. */\n \tcase VIRTCHNL_OP_EVENT:\n \tcase VIRTCHNL_OP_UNKNOWN:\ndiff --git a/drivers/common/iavf/virtchnl_inline_ipsec.h b/drivers/common/iavf/virtchnl_inline_ipsec.h\nnew file mode 100644\nindex 0000000000..1e9134501e\n--- /dev/null\n+++ b/drivers/common/iavf/virtchnl_inline_ipsec.h\n@@ -0,0 +1,553 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2021 Intel Corporation\n+ */\n+\n+#ifndef _VIRTCHNL_INLINE_IPSEC_H_\n+#define _VIRTCHNL_INLINE_IPSEC_H_\n+\n+#define VIRTCHNL_IPSEC_MAX_CRYPTO_CAP_NUM\t3\n+#define VIRTCHNL_IPSEC_MAX_ALGO_CAP_NUM\t\t16\n+#define VIRTCHNL_IPSEC_MAX_TX_DESC_NUM\t\t128\n+#define VIRTCHNL_IPSEC_MAX_CRYPTO_ITEM_NUMBER\t2\n+#define VIRTCHNL_IPSEC_MAX_KEY_LEN\t\t128\n+#define VIRTCHNL_IPSEC_MAX_SA_DESTROY_NUM\t8\n+#define VIRTCHNL_IPSEC_SA_DESTROY\t\t0\n+#define VIRTCHNL_IPSEC_BROADCAST_VFID\t\t0xFFFFFFFF\n+#define VIRTCHNL_IPSEC_INVALID_REQ_ID\t\t0xFFFF\n+#define VIRTCHNL_IPSEC_INVALID_SA_CFG_RESP\t0xFFFFFFFF\n+#define VIRTCHNL_IPSEC_INVALID_SP_CFG_RESP\t0xFFFFFFFF\n+\n+/* crypto type */\n+#define VIRTCHNL_AUTH\t\t1\n+#define VIRTCHNL_CIPHER\t\t2\n+#define VIRTCHNL_AEAD\t\t3\n+\n+/* caps enabled */\n+#define VIRTCHNL_IPSEC_ESN_ENA\t\t\tBIT(0)\n+#define VIRTCHNL_IPSEC_UDP_ENCAP_ENA\t\tBIT(1)\n+#define VIRTCHNL_IPSEC_SA_INDEX_SW_ENA\t\tBIT(2)\n+#define VIRTCHNL_IPSEC_AUDIT_ENA\t\tBIT(3)\n+#define VIRTCHNL_IPSEC_BYTE_LIMIT_ENA\t\tBIT(4)\n+#define VIRTCHNL_IPSEC_DROP_ON_AUTH_FAIL_ENA\tBIT(5)\n+#define VIRTCHNL_IPSEC_ARW_CHECK_ENA\t\tBIT(6)\n+#define VIRTCHNL_IPSEC_24BIT_SPI_ENA\t\tBIT(7)\n+\n+/* algorithm type */\n+/* Hash Algorithm */\n+#define VIRTCHNL_HASH_NO_ALG\t0 /* NULL algorithm */\n+#define VIRTCHNL_AES_CBC_MAC\t1 /* AES-CBC-MAC algorithm */\n+#define VIRTCHNL_AES_CMAC\t2 /* AES CMAC algorithm */\n+#define VIRTCHNL_AES_GMAC\t3 /* AES GMAC algorithm */\n+#define VIRTCHNL_AES_XCBC_MAC\t4 /* AES XCBC algorithm */\n+#define VIRTCHNL_MD5_HMAC\t5 /* HMAC using MD5 algorithm */\n+#define VIRTCHNL_SHA1_HMAC\t6 /* HMAC using 128 bit SHA algorithm */\n+#define VIRTCHNL_SHA224_HMAC\t7 /* HMAC using 224 bit SHA algorithm */\n+#define VIRTCHNL_SHA256_HMAC\t8 /* HMAC using 256 bit SHA algorithm */\n+#define VIRTCHNL_SHA384_HMAC\t9 /* HMAC using 384 bit SHA algorithm */\n+#define VIRTCHNL_SHA512_HMAC\t10 /* HMAC using 512 bit SHA algorithm */\n+#define VIRTCHNL_SHA3_224_HMAC\t11 /* HMAC using 224 bit SHA3 algorithm */\n+#define VIRTCHNL_SHA3_256_HMAC\t12 /* HMAC using 256 bit SHA3 algorithm */\n+#define VIRTCHNL_SHA3_384_HMAC\t13 /* HMAC using 384 bit SHA3 algorithm */\n+#define VIRTCHNL_SHA3_512_HMAC\t14 /* HMAC using 512 bit SHA3 algorithm */\n+/* Cipher Algorithm */\n+#define VIRTCHNL_CIPHER_NO_ALG\t15 /* NULL algorithm */\n+#define VIRTCHNL_3DES_CBC\t16 /* Triple DES algorithm in CBC mode */\n+#define VIRTCHNL_AES_CBC\t17 /* AES algorithm in CBC mode */\n+#define VIRTCHNL_AES_CTR\t18 /* AES algorithm in Counter mode */\n+/* AEAD Algorithm */\n+#define VIRTCHNL_AES_CCM\t19 /* AES algorithm in CCM mode */\n+#define VIRTCHNL_AES_GCM\t20 /* AES algorithm in GCM mode */\n+#define VIRTCHNL_CHACHA20_POLY1305 21 /* algorithm of ChaCha20-Poly1305 */\n+\n+/* protocol type */\n+#define VIRTCHNL_PROTO_ESP\t1\n+#define VIRTCHNL_PROTO_AH\t2\n+#define VIRTCHNL_PROTO_RSVD1\t3\n+\n+/* sa mode */\n+#define VIRTCHNL_SA_MODE_TRANSPORT\t1\n+#define VIRTCHNL_SA_MODE_TUNNEL\t\t2\n+#define VIRTCHNL_SA_MODE_TRAN_TUN\t3\n+#define VIRTCHNL_SA_MODE_UNKNOWN\t4\n+\n+/* sa direction */\n+#define VIRTCHNL_DIR_INGRESS\t\t1\n+#define VIRTCHNL_DIR_EGRESS\t\t2\n+#define VIRTCHNL_DIR_INGRESS_EGRESS\t3\n+\n+/* sa termination */\n+#define VIRTCHNL_TERM_SOFTWARE\t1\n+#define VIRTCHNL_TERM_HARDWARE\t2\n+\n+/* sa ip type */\n+#define VIRTCHNL_IPV4\t1\n+#define VIRTCHNL_IPV6\t2\n+\n+/* for virtchnl_ipsec_resp */\n+enum inline_ipsec_resp {\n+\tINLINE_IPSEC_SUCCESS = 0,\n+\tINLINE_IPSEC_FAIL = -1,\n+\tINLINE_IPSEC_ERR_FIFO_FULL = -2,\n+\tINLINE_IPSEC_ERR_NOT_READY = -3,\n+\tINLINE_IPSEC_ERR_VF_DOWN = -4,\n+\tINLINE_IPSEC_ERR_INVALID_PARAMS = -5,\n+\tINLINE_IPSEC_ERR_NO_MEM = -6,\n+};\n+\n+/* Detailed opcodes for DPDK and IPsec use */\n+enum inline_ipsec_ops {\n+\tINLINE_IPSEC_OP_GET_CAP = 0,\n+\tINLINE_IPSEC_OP_GET_STATUS = 1,\n+\tINLINE_IPSEC_OP_SA_CREATE = 2,\n+\tINLINE_IPSEC_OP_SA_UPDATE = 3,\n+\tINLINE_IPSEC_OP_SA_DESTROY = 4,\n+\tINLINE_IPSEC_OP_SP_CREATE = 5,\n+\tINLINE_IPSEC_OP_SP_DESTROY = 6,\n+\tINLINE_IPSEC_OP_SA_READ = 7,\n+\tINLINE_IPSEC_OP_EVENT = 8,\n+\tINLINE_IPSEC_OP_RESP = 9,\n+};\n+\n+/* Not all valid, if certain field is invalid, set 1 for all bits */\n+struct virtchnl_algo_cap {\n+\tu32 algo_type;\n+\n+\tu16 block_size;\n+\n+\tu16 min_key_size;\n+\tu16 max_key_size;\n+\tu16 inc_key_size;\n+\n+\tu16 min_iv_size;\n+\tu16 max_iv_size;\n+\tu16 inc_iv_size;\n+\n+\tu16 min_digest_size;\n+\tu16 max_digest_size;\n+\tu16 inc_digest_size;\n+\n+\tu16 min_aad_size;\n+\tu16 max_aad_size;\n+\tu16 inc_aad_size;\n+} __rte_packed;\n+\n+/* vf record the capability of crypto from the virtchnl */\n+struct virtchnl_sym_crypto_cap {\n+\tu8 crypto_type;\n+\tu8 algo_cap_num;\n+\tstruct virtchnl_algo_cap algo_cap_list[VIRTCHNL_IPSEC_MAX_ALGO_CAP_NUM];\n+} __rte_packed;\n+\n+/* VIRTCHNL_OP_GET_IPSEC_CAP\n+ * VF pass virtchnl_ipsec_cap to PF\n+ * and PF return capability of ipsec from virtchnl.\n+ */\n+struct virtchnl_ipsec_cap {\n+\t/* max number of SA per VF */\n+\tu16 max_sa_num;\n+\n+\t/* IPsec SA Protocol - value ref VIRTCHNL_PROTO_XXX */\n+\tu8 virtchnl_protocol_type;\n+\n+\t/* IPsec SA Mode - value ref VIRTCHNL_SA_MODE_XXX */\n+\tu8 virtchnl_sa_mode;\n+\n+\t/* IPSec SA Direction - value ref VIRTCHNL_DIR_XXX */\n+\tu8 virtchnl_direction;\n+\n+\t/* termination mode - value ref VIRTCHNL_TERM_XXX */\n+\tu8 termination_mode;\n+\n+\t/* number of supported crypto capability */\n+\tu8 crypto_cap_num;\n+\n+\t/* descriptor ID */\n+\tu16 desc_id;\n+\n+\t/* capabilities enabled - value ref VIRTCHNL_IPSEC_XXX_ENA */\n+\tu32 caps_enabled;\n+\n+\t/* crypto capabilities */\n+\tstruct virtchnl_sym_crypto_cap cap[VIRTCHNL_IPSEC_MAX_CRYPTO_CAP_NUM];\n+} __rte_packed;\n+\n+/* configuration of crypto function */\n+struct virtchnl_ipsec_crypto_cfg_item {\n+\tu8 crypto_type;\n+\n+\tu32 algo_type;\n+\n+\t/* Length of valid IV data. */\n+\tu16 iv_len;\n+\n+\t/* Length of digest */\n+\tu16 digest_len;\n+\n+\t/* SA salt */\n+\tu32 salt;\n+\n+\t/* The length of the symmetric key */\n+\tu16 key_len;\n+\n+\t/* key data buffer */\n+\tu8 key_data[VIRTCHNL_IPSEC_MAX_KEY_LEN];\n+} __rte_packed;\n+\n+struct virtchnl_ipsec_sym_crypto_cfg {\n+\tstruct virtchnl_ipsec_crypto_cfg_item\n+\t\titems[VIRTCHNL_IPSEC_MAX_CRYPTO_ITEM_NUMBER];\n+};\n+\n+/* VIRTCHNL_OP_IPSEC_SA_CREATE\n+ * VF send this SA configuration to PF using virtchnl;\n+ * PF create SA as configuration and PF driver will return\n+ * an unique index (sa_idx) for the created SA.\n+ */\n+struct virtchnl_ipsec_sa_cfg {\n+\t/* IPsec SA Protocol - AH/ESP */\n+\tu8 virtchnl_protocol_type;\n+\n+\t/* termination mode - value ref VIRTCHNL_TERM_XXX */\n+\tu8 virtchnl_termination;\n+\n+\t/* type of outer IP - IPv4/IPv6 */\n+\tu8 virtchnl_ip_type;\n+\n+\t/* type of esn - !0:enable/0:disable */\n+\tu8 esn_enabled;\n+\n+\t/* udp encap - !0:enable/0:disable */\n+\tu8 udp_encap_enabled;\n+\n+\t/* IPSec SA Direction - value ref VIRTCHNL_DIR_XXX */\n+\tu8 virtchnl_direction;\n+\n+\t/* reserved */\n+\tu8 reserved1;\n+\n+\t/* SA security parameter index */\n+\tu32 spi;\n+\n+\t/* outer src ip address */\n+\tu8 src_addr[16];\n+\n+\t/* outer dst ip address */\n+\tu8 dst_addr[16];\n+\n+\t/* SPD reference. Used to link an SA with its policy.\n+\t * PF drivers may ignore this field.\n+\t */\n+\tu16 spd_ref;\n+\n+\t/* high 32 bits of esn */\n+\tu32 esn_hi;\n+\n+\t/* low 32 bits of esn */\n+\tu32 esn_low;\n+\n+\t/* When enabled, sa_index must be valid */\n+\tu8 sa_index_en;\n+\n+\t/* SA index when sa_index_en is true */\n+\tu32 sa_index;\n+\n+\t/* auditing mode - enable/disable */\n+\tu8 audit_en;\n+\n+\t/* lifetime byte limit - enable/disable\n+\t * When enabled, byte_limit_hard and byte_limit_soft\n+\t * must be valid.\n+\t */\n+\tu8 byte_limit_en;\n+\n+\t/* hard byte limit count */\n+\tu64 byte_limit_hard;\n+\n+\t/* soft byte limit count */\n+\tu64 byte_limit_soft;\n+\n+\t/* drop on authentication failure - enable/disable */\n+\tu8 drop_on_auth_fail_en;\n+\n+\t/* anti-reply window check - enable/disable\n+\t * When enabled, arw_size must be valid.\n+\t */\n+\tu8 arw_check_en;\n+\n+\t/* size of arw window, offset by 1. Setting to 0\n+\t * represents ARW window size of 1. Setting to 127\n+\t * represents ARW window size of 128\n+\t */\n+\tu8 arw_size;\n+\n+\t/* no ip offload mode - enable/disable\n+\t * When enabled, ip type and address must not be valid.\n+\t */\n+\tu8 no_ip_offload_en;\n+\n+\t/* SA Domain. Used to logical separate an SADB into groups.\n+\t * PF drivers supporting a single group ignore this field.\n+\t */\n+\tu16 sa_domain;\n+\n+\t/* crypto configuration */\n+\tstruct virtchnl_ipsec_sym_crypto_cfg crypto_cfg;\n+} __rte_packed;\n+\n+/* VIRTCHNL_OP_IPSEC_SA_UPDATE\n+ * VF send configuration of index of SA to PF\n+ * PF will update SA according to configuration\n+ */\n+struct virtchnl_ipsec_sa_update {\n+\tu32 sa_index; /* SA to update */\n+\tu32 esn_hi; /* high 32 bits of esn */\n+\tu32 esn_low; /* low 32 bits of esn */\n+} __rte_packed;\n+\n+/* VIRTCHNL_OP_IPSEC_SA_DESTROY\n+ * VF send configuration of index of SA to PF\n+ * PF will destroy SA according to configuration\n+ * flag bitmap indicate all SA or just selected SA will\n+ * be destroyed\n+ */\n+struct virtchnl_ipsec_sa_destroy {\n+\t/* All zero bitmap indicates all SA will be destroyed.\n+\t * Non-zero bitmap indicates the selected SA in\n+\t * array sa_index will be destroyed.\n+\t */\n+\tu8 flag;\n+\n+\t/* selected SA index */\n+\tu32 sa_index[VIRTCHNL_IPSEC_MAX_SA_DESTROY_NUM];\n+} __rte_packed;\n+\n+/* VIRTCHNL_OP_IPSEC_SA_READ\n+ * VF send this SA configuration to PF using virtchnl;\n+ * PF read SA and will return configuration for the created SA.\n+ */\n+struct virtchnl_ipsec_sa_read {\n+\t/* SA valid - invalid/valid */\n+\tu8 valid;\n+\n+\t/* SA active - inactive/active */\n+\tu8 active;\n+\n+\t/* SA SN rollover - not_rollover/rollover */\n+\tu8 sn_rollover;\n+\n+\t/* IPsec SA Protocol - AH/ESP */\n+\tu8 virtchnl_protocol_type;\n+\n+\t/* termination mode - value ref VIRTCHNL_TERM_XXX */\n+\tu8 virtchnl_termination;\n+\n+\t/* auditing mode - enable/disable */\n+\tu8 audit_en;\n+\n+\t/* lifetime byte limit - enable/disable\n+\t * When set to limit, byte_limit_hard and byte_limit_soft\n+\t * must be valid.\n+\t */\n+\tu8 byte_limit_en;\n+\n+\t/* hard byte limit count */\n+\tu64 byte_limit_hard;\n+\n+\t/* soft byte limit count */\n+\tu64 byte_limit_soft;\n+\n+\t/* drop on authentication failure - enable/disable */\n+\tu8 drop_on_auth_fail_en;\n+\n+\t/* anti-replay window check - enable/disable\n+\t * When set to check, arw_size, arw_top, and arw must be valid\n+\t */\n+\tu8 arw_check_en;\n+\n+\t/* size of arw window, offset by 1. Setting to 0\n+\t * represents ARW window size of 1. Setting to 127\n+\t * represents ARW window size of 128\n+\t */\n+\tu8 arw_size;\n+\n+\t/* reserved */\n+\tu8 reserved1;\n+\n+\t/* top of anti-replay-window */\n+\tu64 arw_top;\n+\n+\t/* anti-replay-window */\n+\tu8 arw[16];\n+\n+\t/* packets processed */\n+\tu64 packets_processed;\n+\n+\t/* bytes processed */\n+\tu64 bytes_processed;\n+\n+\t/* packets dropped */\n+\tu32 packets_dropped;\n+\n+\t/* authentication failures */\n+\tu32 auth_fails;\n+\n+\t/* ARW check failures */\n+\tu32 arw_fails;\n+\n+\t/* type of esn - enable/disable */\n+\tu8 esn;\n+\n+\t/* IPSec SA Direction - value ref VIRTCHNL_DIR_XXX */\n+\tu8 virtchnl_direction;\n+\n+\t/* SA security parameter index */\n+\tu32 spi;\n+\n+\t/* SA salt */\n+\tu32 salt;\n+\n+\t/* high 32 bits of esn */\n+\tu32 esn_hi;\n+\n+\t/* low 32 bits of esn */\n+\tu32 esn_low;\n+\n+\t/* SA Domain. Used to logical separate an SADB into groups.\n+\t * PF drivers supporting a single group ignore this field.\n+\t */\n+\tu16 sa_domain;\n+\n+\t/* SPD reference. Used to link an SA with its policy.\n+\t * PF drivers may ignore this field.\n+\t */\n+\tu16 spd_ref;\n+\n+\t/* crypto configuration. Salt and keys are set to 0 */\n+\tstruct virtchnl_ipsec_sym_crypto_cfg crypto_cfg;\n+} __rte_packed;\n+\n+\n+#define VIRTCHNL_IPSEC_INBOUND_SPD_TBL_IPV4\t(0)\n+#define VIRTCHNL_IPSEC_INBOUND_SPD_TBL_IPV6\t(1)\n+\n+/* Add allowlist entry in IES */\n+struct virtchnl_ipsec_sp_cfg {\n+\tu32 spi;\n+\tu32 dip[4];\n+\n+\t/* Drop frame if true or redirect to QAT if false. */\n+\tu8 drop;\n+\n+\t/* Congestion domain. For future use. */\n+\tu8 cgd;\n+\n+\t/* 0 for IPv4 table, 1 for IPv6 table. */\n+\tu8 table_id;\n+\n+\t/* Set TC (congestion domain) if true. For future use. */\n+\tu8 set_tc;\n+} __rte_packed;\n+\n+\n+/* Delete allowlist entry in IES */\n+struct virtchnl_ipsec_sp_destroy {\n+\t/* 0 for IPv4 table, 1 for IPv6 table. */\n+\tu8 table_id;\n+\tu32 rule_id;\n+} __rte_packed;\n+\n+/* Response from IES to allowlist operations */\n+struct virtchnl_ipsec_sp_cfg_resp {\n+\tu32 rule_id;\n+};\n+\n+struct virtchnl_ipsec_sa_cfg_resp {\n+\tu32 sa_handle;\n+};\n+\n+#define INLINE_IPSEC_EVENT_RESET\t0x1\n+#define INLINE_IPSEC_EVENT_CRYPTO_ON\t0x2\n+#define INLINE_IPSEC_EVENT_CRYPTO_OFF\t0x4\n+\n+struct virtchnl_ipsec_event {\n+\tu32 ipsec_event_data;\n+};\n+\n+#define INLINE_IPSEC_STATUS_AVAILABLE\t0x1\n+#define INLINE_IPSEC_STATUS_UNAVAILABLE\t0x2\n+\n+struct virtchnl_ipsec_status {\n+\tu32 status;\n+};\n+\n+struct virtchnl_ipsec_resp {\n+\tu32 resp;\n+};\n+\n+/* Internal message descriptor for VF <-> IPsec communication */\n+struct inline_ipsec_msg {\n+\tu16 ipsec_opcode;\n+\tu16 req_id;\n+\n+\tunion {\n+\t\t/* IPsec request */\n+\t\tstruct virtchnl_ipsec_sa_cfg sa_cfg[0];\n+\t\tstruct virtchnl_ipsec_sp_cfg sp_cfg[0];\n+\t\tstruct virtchnl_ipsec_sa_update sa_update[0];\n+\t\tstruct virtchnl_ipsec_sa_destroy sa_destroy[0];\n+\t\tstruct virtchnl_ipsec_sp_destroy sp_destroy[0];\n+\n+\t\t/* IPsec response */\n+\t\tstruct virtchnl_ipsec_sa_cfg_resp sa_cfg_resp[0];\n+\t\tstruct virtchnl_ipsec_sp_cfg_resp sp_cfg_resp[0];\n+\t\tstruct virtchnl_ipsec_cap ipsec_cap[0];\n+\t\tstruct virtchnl_ipsec_status ipsec_status[0];\n+\t\t/* response to del_sa, del_sp, update_sa */\n+\t\tstruct virtchnl_ipsec_resp ipsec_resp[0];\n+\n+\t\t/* IPsec event (no req_id is required) */\n+\t\tstruct virtchnl_ipsec_event event[0];\n+\n+\t\t/* Reserved */\n+\t\tstruct virtchnl_ipsec_sa_read sa_read[0];\n+\t} ipsec_data;\n+} __rte_packed;\n+\n+static inline u16 virtchnl_inline_ipsec_val_msg_len(u16 opcode)\n+{\n+\tu16 valid_len = sizeof(struct inline_ipsec_msg);\n+\n+\tswitch (opcode) {\n+\tcase INLINE_IPSEC_OP_GET_CAP:\n+\tcase INLINE_IPSEC_OP_GET_STATUS:\n+\t\tbreak;\n+\tcase INLINE_IPSEC_OP_SA_CREATE:\n+\t\tvalid_len += sizeof(struct virtchnl_ipsec_sa_cfg);\n+\t\tbreak;\n+\tcase INLINE_IPSEC_OP_SP_CREATE:\n+\t\tvalid_len += sizeof(struct virtchnl_ipsec_sp_cfg);\n+\t\tbreak;\n+\tcase INLINE_IPSEC_OP_SA_UPDATE:\n+\t\tvalid_len += sizeof(struct virtchnl_ipsec_sa_update);\n+\t\tbreak;\n+\tcase INLINE_IPSEC_OP_SA_DESTROY:\n+\t\tvalid_len += sizeof(struct virtchnl_ipsec_sa_destroy);\n+\t\tbreak;\n+\tcase INLINE_IPSEC_OP_SP_DESTROY:\n+\t\tvalid_len += sizeof(struct virtchnl_ipsec_sp_destroy);\n+\t\tbreak;\n+\t/* Only for msg length calculation of response to VF in case of\n+\t * inline ipsec failure.\n+\t */\n+\tcase INLINE_IPSEC_OP_RESP:\n+\t\tvalid_len += sizeof(struct virtchnl_ipsec_resp);\n+\t\tbreak;\n+\tdefault:\n+\t\tvalid_len = 0;\n+\t\tbreak;\n+\t}\n+\n+\treturn valid_len;\n+}\n+\n+#endif /* _VIRTCHNL_INLINE_IPSEC_H_ */\n", "prefixes": [ "v4", "1/6" ] }