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GET /api/patches/100187/?format=api
{ "id": 100187, "url": "http://patches.dpdk.org/api/patches/100187/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210930172822.1949969-19-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210930172822.1949969-19-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210930172822.1949969-19-michaelba@nvidia.com", "date": "2021-09-30T17:28:22", "name": "[18/18] common/mlx5: share MR mempool registration", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "fdd7516ad1ef5694a34a1f6743d11ce807f8c3b9", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210930172822.1949969-19-michaelba@nvidia.com/mbox/", "series": [ { "id": 19311, "url": "http://patches.dpdk.org/api/series/19311/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19311", "date": "2021-09-30T17:28:04", "name": "mlx5: sharing global MR cache between drivers", "version": 1, "mbox": "http://patches.dpdk.org/series/19311/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/100187/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/100187/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", 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SFS:(4636009)(36840700001)(46966006)(86362001)(70206006)(8936002)(82310400003)(70586007)(6666004)(55016002)(426003)(107886003)(83380400001)(186003)(2616005)(16526019)(1076003)(7696005)(336012)(6286002)(26005)(2876002)(4326008)(8676002)(5660300002)(30864003)(36860700001)(2906002)(356005)(36756003)(508600001)(6916009)(54906003)(316002)(47076005)(7636003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Sep 2021 17:29:17.0303 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 8f649d0d-a76b-4973-e64a-08d98437d470", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT036.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY4PR12MB1367", "X-Mailman-Approved-At": "Thu, 30 Sep 2021 19:39:43 +0200", "Subject": "[dpdk-dev] [PATCH 18/18] common/mlx5: share MR mempool registration", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Michael Baum <michaelba@oss.nvidia.com>\n\nExpand the use of mempool registration to MR management for other\ndrivers.\n\nSigned-off-by: Michael Baum <michaelba@oss.nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_common.c | 148 ++++++++++++++++++++++++++\n drivers/common/mlx5/mlx5_common.h | 9 ++\n drivers/common/mlx5/mlx5_common_mp.h | 11 ++\n drivers/common/mlx5/mlx5_common_mr.c | 94 +++++++++++++---\n drivers/common/mlx5/mlx5_common_mr.h | 41 ++++++-\n drivers/common/mlx5/version.map | 6 +-\n drivers/compress/mlx5/mlx5_compress.c | 5 +-\n drivers/crypto/mlx5/mlx5_crypto.c | 5 +-\n drivers/net/mlx5/linux/mlx5_mp_os.c | 3 +-\n drivers/net/mlx5/meson.build | 1 -\n drivers/net/mlx5/mlx5.c | 106 ++----------------\n drivers/net/mlx5/mlx5.h | 13 ---\n drivers/net/mlx5/mlx5_mr.c | 89 ----------------\n drivers/net/mlx5/mlx5_rx.c | 15 +--\n drivers/net/mlx5/mlx5_rx.h | 14 ---\n drivers/net/mlx5/mlx5_rxq.c | 1 +\n drivers/net/mlx5/mlx5_rxtx.h | 26 -----\n drivers/net/mlx5/mlx5_tx.h | 27 ++---\n drivers/regex/mlx5/mlx5_regex.c | 6 +-\n 19 files changed, 322 insertions(+), 298 deletions(-)\n delete mode 100644 drivers/net/mlx5/mlx5_mr.c", "diff": "diff --git a/drivers/common/mlx5/mlx5_common.c b/drivers/common/mlx5/mlx5_common.c\nindex 0ed1477eb8..e6ff045c95 100644\n--- a/drivers/common/mlx5/mlx5_common.c\n+++ b/drivers/common/mlx5/mlx5_common.c\n@@ -13,6 +13,7 @@\n \n #include \"mlx5_common.h\"\n #include \"mlx5_common_os.h\"\n+#include \"mlx5_common_mp.h\"\n #include \"mlx5_common_log.h\"\n #include \"mlx5_common_defs.h\"\n #include \"mlx5_common_private.h\"\n@@ -302,6 +303,152 @@ mlx5_dev_to_pci_str(const struct rte_device *dev, char *addr, size_t size)\n #endif\n }\n \n+/**\n+ * Register the mempool for the protection domain.\n+ *\n+ * @param cdev\n+ * Pointer to the mlx5 common device.\n+ * @param mp\n+ * Mempool being registered.\n+ *\n+ * @return\n+ * 0 on success, (-1) on failure and rte_errno is set.\n+ */\n+static int\n+mlx5_dev_mempool_register(struct mlx5_common_device *cdev,\n+\t\t\t struct rte_mempool *mp)\n+{\n+\tstruct mlx5_mp_id mp_id;\n+\n+\tmlx5_mp_id_init(&mp_id, 0);\n+\treturn mlx5_mr_mempool_register(&cdev->mr_scache, cdev->pd, mp, &mp_id);\n+}\n+\n+/**\n+ * Unregister the mempool from the protection domain.\n+ *\n+ * @param cdev\n+ * Pointer to the mlx5 common device.\n+ * @param mp\n+ * Mempool being unregistered.\n+ */\n+void\n+mlx5_dev_mempool_unregister(struct mlx5_common_device *cdev,\n+\t\t\t struct rte_mempool *mp)\n+{\n+\tstruct mlx5_mp_id mp_id;\n+\n+\tmlx5_mp_id_init(&mp_id, 0);\n+\tif (mlx5_mr_mempool_unregister(&cdev->mr_scache, mp, &mp_id) < 0)\n+\t\tDRV_LOG(WARNING, \"Failed to unregister mempool %s for PD %p: %s\",\n+\t\t\tmp->name, cdev->pd, rte_strerror(rte_errno));\n+}\n+\n+/**\n+ * rte_mempool_walk() callback to register mempools for the protection domain.\n+ *\n+ * @param mp\n+ * The mempool being walked.\n+ * @param arg\n+ * Pointer to the device shared context.\n+ */\n+static void\n+mlx5_dev_mempool_register_cb(struct rte_mempool *mp, void *arg)\n+{\n+\tstruct mlx5_common_device *cdev = arg;\n+\tint ret;\n+\n+\tret = mlx5_dev_mempool_register(cdev, mp);\n+\tif (ret < 0 && rte_errno != EEXIST)\n+\t\tDRV_LOG(ERR,\n+\t\t\t\"Failed to register existing mempool %s for PD %p: %s\",\n+\t\t\tmp->name, cdev->pd, rte_strerror(rte_errno));\n+}\n+\n+/**\n+ * rte_mempool_walk() callback to unregister mempools\n+ * from the protection domain.\n+ *\n+ * @param mp\n+ * The mempool being walked.\n+ * @param arg\n+ * Pointer to the device shared context.\n+ */\n+static void\n+mlx5_dev_mempool_unregister_cb(struct rte_mempool *mp, void *arg)\n+{\n+\tmlx5_dev_mempool_unregister((struct mlx5_common_device *)arg, mp);\n+}\n+\n+/**\n+ * Mempool life cycle callback for mlx5 common devices.\n+ *\n+ * @param event\n+ * Mempool life cycle event.\n+ * @param mp\n+ * Associated mempool.\n+ * @param arg\n+ * Pointer to a device shared context.\n+ */\n+static void\n+mlx5_dev_mempool_event_cb(enum rte_mempool_event event, struct rte_mempool *mp,\n+\t\t\t void *arg)\n+{\n+\tstruct mlx5_common_device *cdev = arg;\n+\n+\tswitch (event) {\n+\tcase RTE_MEMPOOL_EVENT_READY:\n+\t\tif (mlx5_dev_mempool_register(cdev, mp) < 0)\n+\t\t\tDRV_LOG(ERR,\n+\t\t\t\t\"Failed to register new mempool %s for PD %p: %s\",\n+\t\t\t\tmp->name, cdev->pd, rte_strerror(rte_errno));\n+\t\tbreak;\n+\tcase RTE_MEMPOOL_EVENT_DESTROY:\n+\t\tmlx5_dev_mempool_unregister(cdev, mp);\n+\t\tbreak;\n+\t}\n+}\n+\n+int\n+mlx5_dev_mempool_subscribe(struct mlx5_common_device *cdev)\n+{\n+\tint ret = 0;\n+\n+\tif (!cdev->config.mr_mempool_reg_en)\n+\t\treturn 0;\n+\trte_rwlock_write_lock(&cdev->mr_scache.mprwlock);\n+\tif (cdev->mr_scache.mp_cb_registered)\n+\t\tgoto exit;\n+\t/* Callback for this device may be already registered. */\n+\tret = rte_mempool_event_callback_register(mlx5_dev_mempool_event_cb,\n+\t\t\t\t\t\t cdev);\n+\tif (ret != 0 && rte_errno != EEXIST)\n+\t\tgoto exit;\n+\t/* Register mempools only once for this device. */\n+\tif (ret == 0)\n+\t\trte_mempool_walk(mlx5_dev_mempool_register_cb, cdev);\n+\tret = 0;\n+\tcdev->mr_scache.mp_cb_registered = 1;\n+exit:\n+\trte_rwlock_write_unlock(&cdev->mr_scache.mprwlock);\n+\treturn ret;\n+}\n+\n+static void\n+mlx5_dev_mempool_unsubscribe(struct mlx5_common_device *cdev)\n+{\n+\tint ret;\n+\n+\tif (!cdev->mr_scache.mp_cb_registered ||\n+\t !cdev->config.mr_mempool_reg_en)\n+\t\treturn;\n+\t/* Stop watching for mempool events and unregister all mempools. */\n+\tret = rte_mempool_event_callback_unregister(mlx5_dev_mempool_event_cb,\n+\t\t\t\t\t\t cdev);\n+\tif (ret == 0)\n+\t\trte_mempool_walk(mlx5_dev_mempool_unregister_cb, cdev);\n+}\n+\n /**\n * Callback for memory event.\n *\n@@ -409,6 +556,7 @@ mlx5_common_dev_release(struct mlx5_common_device *cdev)\n \t\tif (TAILQ_EMPTY(&devices_list))\n \t\t\trte_mem_event_callback_unregister(\"MLX5_MEM_EVENT_CB\",\n \t\t\t\t\t\t\t NULL);\n+\t\tmlx5_dev_mempool_unsubscribe(cdev);\n \t\tmlx5_mr_release_cache(&cdev->mr_scache);\n \t\tmlx5_dev_hw_global_release(cdev);\n \t}\ndiff --git a/drivers/common/mlx5/mlx5_common.h b/drivers/common/mlx5/mlx5_common.h\nindex 72ff0ff809..744c6a72b3 100644\n--- a/drivers/common/mlx5/mlx5_common.h\n+++ b/drivers/common/mlx5/mlx5_common.h\n@@ -408,6 +408,15 @@ __rte_internal\n bool\n mlx5_dev_is_pci(const struct rte_device *dev);\n \n+__rte_internal\n+int\n+mlx5_dev_mempool_subscribe(struct mlx5_common_device *cdev);\n+\n+__rte_internal\n+void\n+mlx5_dev_mempool_unregister(struct mlx5_common_device *cdev,\n+\t\t\t struct rte_mempool *mp);\n+\n /* mlx5_common_mr.c */\n \n __rte_internal\ndiff --git a/drivers/common/mlx5/mlx5_common_mp.h b/drivers/common/mlx5/mlx5_common_mp.h\nindex 527bf3cad8..2276dc921c 100644\n--- a/drivers/common/mlx5/mlx5_common_mp.h\n+++ b/drivers/common/mlx5/mlx5_common_mp.h\n@@ -64,6 +64,17 @@ struct mlx5_mp_id {\n \tuint16_t port_id;\n };\n \n+/** Key string for IPC. */\n+#define MLX5_MP_NAME \"common_mlx5_mp\"\n+\n+/** Initialize a multi-process ID. */\n+static inline void\n+mlx5_mp_id_init(struct mlx5_mp_id *mp_id, uint16_t port_id)\n+{\n+\tmp_id->port_id = port_id;\n+\tstrlcpy(mp_id->name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);\n+}\n+\n /** Request timeout for IPC. */\n #define MLX5_MP_REQ_TIMEOUT_SEC 5\n \ndiff --git a/drivers/common/mlx5/mlx5_common_mr.c b/drivers/common/mlx5/mlx5_common_mr.c\nindex 5bfddac08e..b582e28d59 100644\n--- a/drivers/common/mlx5/mlx5_common_mr.c\n+++ b/drivers/common/mlx5/mlx5_common_mr.c\n@@ -12,8 +12,10 @@\n #include <rte_rwlock.h>\n \n #include \"mlx5_glue.h\"\n+#include \"mlx5_common.h\"\n #include \"mlx5_common_mp.h\"\n #include \"mlx5_common_mr.h\"\n+#include \"mlx5_common_os.h\"\n #include \"mlx5_common_log.h\"\n #include \"mlx5_malloc.h\"\n \n@@ -47,6 +49,20 @@ struct mlx5_mempool_reg {\n \tunsigned int mrs_n;\n };\n \n+void\n+mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)\n+{\n+\tstruct mlx5_mprq_buf *buf = opaque;\n+\n+\tif (__atomic_load_n(&buf->refcnt, __ATOMIC_RELAXED) == 1) {\n+\t\trte_mempool_put(buf->mp, buf);\n+\t} else if (unlikely(__atomic_sub_fetch(&buf->refcnt, 1,\n+\t\t\t\t\t __ATOMIC_RELAXED) == 0)) {\n+\t\t__atomic_store_n(&buf->refcnt, 1, __ATOMIC_RELAXED);\n+\t\trte_mempool_put(buf->mp, buf);\n+\t}\n+}\n+\n /**\n * Expand B-tree table to a given size. Can't be called with holding\n * memory_hotplug_lock or share_cache.rwlock due to rte_realloc().\n@@ -600,6 +616,10 @@ mlx5_mr_create_secondary(void *pd __rte_unused,\n {\n \tint ret;\n \n+\tif (mp_id == NULL) {\n+\t\trte_errno = EINVAL;\n+\t\treturn UINT32_MAX;\n+\t}\n \tDRV_LOG(DEBUG, \"port %u requesting MR creation for address (%p)\",\n \t mp_id->port_id, (void *)addr);\n \tret = mlx5_mp_req_mr_create(mp_id, addr);\n@@ -995,10 +1015,11 @@ mr_lookup_caches(void *pd, struct mlx5_mp_id *mp_id,\n * @return\n * Searched LKey on success, UINT32_MAX on no match.\n */\n-uint32_t mlx5_mr_addr2mr_bh(void *pd, struct mlx5_mp_id *mp_id,\n-\t\t\t struct mlx5_mr_share_cache *share_cache,\n-\t\t\t struct mlx5_mr_ctrl *mr_ctrl,\n-\t\t\t uintptr_t addr, unsigned int mr_ext_memseg_en)\n+static uint32_t\n+mlx5_mr_addr2mr_bh(void *pd, struct mlx5_mp_id *mp_id,\n+\t\t struct mlx5_mr_share_cache *share_cache,\n+\t\t struct mlx5_mr_ctrl *mr_ctrl, uintptr_t addr,\n+\t\t unsigned int mr_ext_memseg_en)\n {\n \tuint32_t lkey;\n \tuint16_t bh_idx = 0;\n@@ -1029,7 +1050,7 @@ uint32_t mlx5_mr_addr2mr_bh(void *pd, struct mlx5_mp_id *mp_id,\n }\n \n /**\n- * Release all the created MRs and resources on global MR cache of a device.\n+ * Release all the created MRs and resources on global MR cache of a device\n * list.\n *\n * @param share_cache\n@@ -1076,6 +1097,8 @@ mlx5_mr_create_cache(struct mlx5_mr_share_cache *share_cache, int socket)\n \tmlx5_os_set_reg_mr_cb(&share_cache->reg_mr_cb,\n \t\t\t &share_cache->dereg_mr_cb);\n \trte_rwlock_init(&share_cache->rwlock);\n+\trte_rwlock_init(&share_cache->mprwlock);\n+\tshare_cache->mp_cb_registered = 0;\n \t/* Initialize B-tree and allocate memory for global MR cache table. */\n \treturn mlx5_mr_btree_init(&share_cache->cache,\n \t\t\t\t MLX5_MR_BTREE_CACHE_N * 2, socket);\n@@ -1245,8 +1268,8 @@ mlx5_free_mr_by_addr(struct mlx5_mr_share_cache *share_cache,\n /**\n * Dump all the created MRs and the global cache entries.\n *\n- * @param sh\n- * Pointer to Ethernet device shared context.\n+ * @param share_cache\n+ * Pointer to a global shared MR cache.\n */\n void\n mlx5_mr_dump_cache(struct mlx5_mr_share_cache *share_cache __rte_unused)\n@@ -1581,8 +1604,7 @@ mlx5_mr_mempool_register_primary(struct mlx5_mr_share_cache *share_cache,\n \tmpr = mlx5_mempool_reg_lookup(share_cache, mp);\n \tif (mpr == NULL) {\n \t\tmlx5_mempool_reg_attach(new_mpr);\n-\t\tLIST_INSERT_HEAD(&share_cache->mempool_reg_list,\n-\t\t\t\t new_mpr, next);\n+\t\tLIST_INSERT_HEAD(&share_cache->mempool_reg_list, new_mpr, next);\n \t\tret = 0;\n \t}\n \trte_rwlock_write_unlock(&share_cache->rwlock);\n@@ -1837,6 +1859,56 @@ mlx5_mr_mempool2mr_bh(struct mlx5_mr_share_cache *share_cache,\n \treturn lkey;\n }\n \n+/**\n+ * Bottom-half of LKey search on. If supported, lookup for the address from\n+ * the mempool. Otherwise, search in old mechanism caches.\n+ *\n+ * @param cdev\n+ * Pointer to mlx5 device.\n+ * @param mp_id\n+ * Multi-process identifier, may be NULL for the primary process.\n+ * @param mr_ctrl\n+ * Pointer to per-queue MR control structure.\n+ * @param mb\n+ * Pointer to mbuf.\n+ *\n+ * @return\n+ * Searched LKey on success, UINT32_MAX on no match.\n+ */\n+static uint32_t\n+mlx5_mr_mb2mr_bh(struct mlx5_common_device *cdev, struct mlx5_mp_id *mp_id,\n+\t\t struct mlx5_mr_ctrl *mr_ctrl, struct rte_mbuf *mb)\n+{\n+\tuint32_t lkey;\n+\tuintptr_t addr = (uintptr_t)mb->buf_addr;\n+\n+\tif (cdev->config.mr_mempool_reg_en) {\n+\t\tstruct rte_mempool *mp = NULL;\n+\t\tstruct mlx5_mprq_buf *buf;\n+\n+\t\tif (!RTE_MBUF_HAS_EXTBUF(mb)) {\n+\t\t\tmp = mlx5_mb2mp(mb);\n+\t\t} else if (mb->shinfo->free_cb == mlx5_mprq_buf_free_cb) {\n+\t\t\t/* Recover MPRQ mempool. */\n+\t\t\tbuf = mb->shinfo->fcb_opaque;\n+\t\t\tmp = buf->mp;\n+\t\t}\n+\t\tif (mp != NULL) {\n+\t\t\tlkey = mlx5_mr_mempool2mr_bh(&cdev->mr_scache,\n+\t\t\t\t\t\t mr_ctrl, mp, addr);\n+\t\t\t/*\n+\t\t\t * Lookup can only fail on invalid input, e.g. \"addr\"\n+\t\t\t * is not from \"mp\" or \"mp\" has MEMPOOL_F_NON_IO set.\n+\t\t\t */\n+\t\t\tif (lkey != UINT32_MAX)\n+\t\t\t\treturn lkey;\n+\t\t}\n+\t\t/* Fallback for generic mechanism in corner cases. */\n+\t}\n+\treturn mlx5_mr_addr2mr_bh(cdev->pd, mp_id, &cdev->mr_scache, mr_ctrl,\n+\t\t\t\t addr, cdev->config.mr_ext_memseg_en);\n+}\n+\n /**\n * Query LKey from a packet buffer.\n *\n@@ -1857,7 +1929,6 @@ mlx5_mr_mb2mr(struct mlx5_common_device *cdev, struct mlx5_mp_id *mp_id,\n \t struct mlx5_mr_ctrl *mr_ctrl, struct rte_mbuf *mbuf)\n {\n \tuint32_t lkey;\n-\tuintptr_t addr = (uintptr_t)mbuf->buf_addr;\n \n \t/* Check generation bit to see if there's any change on existing MRs. */\n \tif (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))\n@@ -1868,6 +1939,5 @@ mlx5_mr_mb2mr(struct mlx5_common_device *cdev, struct mlx5_mp_id *mp_id,\n \tif (likely(lkey != UINT32_MAX))\n \t\treturn lkey;\n \t/* Take slower bottom-half on miss. */\n-\treturn mlx5_mr_addr2mr_bh(cdev->pd, mp_id, &cdev->mr_scache, mr_ctrl,\n-\t\t\t\t addr, cdev->config.mr_ext_memseg_en);\n+\treturn mlx5_mr_mb2mr_bh(cdev, mp_id, mr_ctrl, mbuf);\n }\ndiff --git a/drivers/common/mlx5/mlx5_common_mr.h b/drivers/common/mlx5/mlx5_common_mr.h\nindex 8a7af05ca5..e74f81641c 100644\n--- a/drivers/common/mlx5/mlx5_common_mr.h\n+++ b/drivers/common/mlx5/mlx5_common_mr.h\n@@ -79,6 +79,8 @@ LIST_HEAD(mlx5_mempool_reg_list, mlx5_mempool_reg);\n struct mlx5_mr_share_cache {\n \tuint32_t dev_gen; /* Generation number to flush local caches. */\n \trte_rwlock_t rwlock; /* MR cache Lock. */\n+\trte_rwlock_t mprwlock; /* Mempool Registration Lock. */\n+\tuint8_t mp_cb_registered; /* Mempool are Registered. */\n \tstruct mlx5_mr_btree cache; /* Global MR cache table. */\n \tstruct mlx5_mr_list mr_list; /* Registered MR list. */\n \tstruct mlx5_mr_list mr_free_list; /* Freed MR list. */\n@@ -87,6 +89,40 @@ struct mlx5_mr_share_cache {\n \tmlx5_dereg_mr_t dereg_mr_cb; /* Callback to dereg_mr func */\n } __rte_packed;\n \n+/* Multi-Packet RQ buffer header. */\n+struct mlx5_mprq_buf {\n+\tstruct rte_mempool *mp;\n+\tuint16_t refcnt; /* Atomically accessed refcnt. */\n+\tuint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */\n+\tstruct rte_mbuf_ext_shared_info shinfos[];\n+\t/*\n+\t * Shared information per stride.\n+\t * More memory will be allocated for the first stride head-room and for\n+\t * the strides data.\n+\t */\n+} __rte_cache_aligned;\n+\n+__rte_internal\n+void mlx5_mprq_buf_free_cb(void *addr, void *opaque);\n+\n+/**\n+ * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the\n+ * cloned mbuf is allocated is returned instead.\n+ *\n+ * @param buf\n+ * Pointer to mbuf.\n+ *\n+ * @return\n+ * Memory pool where data is located for given mbuf.\n+ */\n+static inline struct rte_mempool *\n+mlx5_mb2mp(struct rte_mbuf *buf)\n+{\n+\tif (unlikely(RTE_MBUF_CLONED(buf)))\n+\t\treturn rte_mbuf_from_indirect(buf)->pool;\n+\treturn buf->pool;\n+}\n+\n /**\n * Look up LKey from given lookup table by linear search. Firstly look up the\n * last-hit entry. If miss, the entire array is searched. If found, update the\n@@ -133,11 +169,6 @@ __rte_internal\n void mlx5_mr_btree_free(struct mlx5_mr_btree *bt);\n void mlx5_mr_btree_dump(struct mlx5_mr_btree *bt __rte_unused);\n __rte_internal\n-uint32_t mlx5_mr_addr2mr_bh(void *pd, struct mlx5_mp_id *mp_id,\n-\t\t\t struct mlx5_mr_share_cache *share_cache,\n-\t\t\t struct mlx5_mr_ctrl *mr_ctrl,\n-\t\t\t uintptr_t addr, unsigned int mr_ext_memseg_en);\n-__rte_internal\n uint32_t mlx5_mr_mempool2mr_bh(struct mlx5_mr_share_cache *share_cache,\n \t\t\t struct mlx5_mr_ctrl *mr_ctrl,\n \t\t\t struct rte_mempool *mp, uintptr_t addr);\ndiff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map\nindex b41fdb883d..807043f22c 100644\n--- a/drivers/common/mlx5/version.map\n+++ b/drivers/common/mlx5/version.map\n@@ -13,6 +13,8 @@ INTERNAL {\n \tmlx5_common_verbs_dereg_mr; # WINDOWS_NO_EXPORT\n \n \tmlx5_dev_is_pci;\n+\tmlx5_dev_mempool_unregister;\n+\tmlx5_dev_mempool_subscribe;\n \n \tmlx5_devx_alloc_uar; # WINDOWS_NO_EXPORT\n \n@@ -101,10 +103,10 @@ INTERNAL {\n \tmlx5_mp_uninit_primary; # WINDOWS_NO_EXPORT\n \tmlx5_mp_uninit_secondary; # WINDOWS_NO_EXPORT\n \n-\tmlx5_mr_addr2mr_bh;\n+\tmlx5_mprq_buf_free_cb;\n \tmlx5_mr_btree_free;\n \tmlx5_mr_create_primary;\n- mlx5_mr_ctrl_init;\n+\tmlx5_mr_ctrl_init;\n \tmlx5_mr_flush_local_cache;\n \tmlx5_mr_mb2mr;\n \ndiff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c\nindex 83efc2cbc4..707716aaa2 100644\n--- a/drivers/compress/mlx5/mlx5_compress.c\n+++ b/drivers/compress/mlx5/mlx5_compress.c\n@@ -382,8 +382,9 @@ mlx5_compress_dev_stop(struct rte_compressdev *dev)\n static int\n mlx5_compress_dev_start(struct rte_compressdev *dev)\n {\n-\tRTE_SET_USED(dev);\n-\treturn 0;\n+\tstruct mlx5_compress_priv *priv = dev->data->dev_private;\n+\n+\treturn mlx5_dev_mempool_subscribe(priv->cdev);\n }\n \n static void\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex ad63cace10..2af5194c05 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -142,8 +142,9 @@ mlx5_crypto_dev_stop(struct rte_cryptodev *dev)\n static int\n mlx5_crypto_dev_start(struct rte_cryptodev *dev)\n {\n-\tRTE_SET_USED(dev);\n-\treturn 0;\n+\tstruct mlx5_crypto_priv *priv = dev->data->dev_private;\n+\n+\treturn mlx5_dev_mempool_subscribe(priv->cdev);\n }\n \n static int\ndiff --git a/drivers/net/mlx5/linux/mlx5_mp_os.c b/drivers/net/mlx5/linux/mlx5_mp_os.c\nindex c3b6495d9e..017a731b3f 100644\n--- a/drivers/net/mlx5/linux/mlx5_mp_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_mp_os.c\n@@ -90,8 +90,7 @@ mlx5_mp_os_primary_handle(const struct rte_mp_msg *mp_msg, const void *peer)\n \tswitch (param->type) {\n \tcase MLX5_MP_REQ_CREATE_MR:\n \t\tmp_init_msg(&priv->mp_id, &mp_res, param->type);\n-\t\tlkey = mlx5_mr_create_primary(cdev->pd,\n-\t\t\t\t\t &priv->sh->cdev->mr_scache,\n+\t\tlkey = mlx5_mr_create_primary(cdev->pd, &cdev->mr_scache,\n \t\t\t\t\t &entry, param->args.addr,\n \t\t\t\t\t cdev->config.mr_ext_memseg_en);\n \t\tif (lkey == UINT32_MAX)\ndiff --git a/drivers/net/mlx5/meson.build b/drivers/net/mlx5/meson.build\nindex dac7f1fabf..636a1be890 100644\n--- a/drivers/net/mlx5/meson.build\n+++ b/drivers/net/mlx5/meson.build\n@@ -18,7 +18,6 @@ sources = files(\n 'mlx5_flow_dv.c',\n 'mlx5_flow_aso.c',\n 'mlx5_mac.c',\n- 'mlx5_mr.c',\n 'mlx5_rss.c',\n 'mlx5_rx.c',\n 'mlx5_rxmode.c',\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 17113be873..e9aa41432e 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -1097,28 +1097,8 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,\n }\n \n /**\n- * Unregister the mempool from the protection domain.\n- *\n- * @param sh\n- * Pointer to the device shared context.\n- * @param mp\n- * Mempool being unregistered.\n- */\n-static void\n-mlx5_dev_ctx_shared_mempool_unregister(struct mlx5_dev_ctx_shared *sh,\n-\t\t\t\t struct rte_mempool *mp)\n-{\n-\tstruct mlx5_mp_id mp_id;\n-\n-\tmlx5_mp_id_init(&mp_id, 0);\n-\tif (mlx5_mr_mempool_unregister(&sh->cdev->mr_scache, mp, &mp_id) < 0)\n-\t\tDRV_LOG(WARNING, \"Failed to unregister mempool %s for PD %p: %s\",\n-\t\t\tmp->name, sh->cdev->pd, rte_strerror(rte_errno));\n-}\n-\n-/**\n- * rte_mempool_walk() callback to register mempools\n- * for the protection domain.\n+ * rte_mempool_walk() callback to unregister Rx mempools.\n+ * It used when implicit mempool registration is disabled.\n *\n * @param mp\n * The mempool being walked.\n@@ -1126,66 +1106,11 @@ mlx5_dev_ctx_shared_mempool_unregister(struct mlx5_dev_ctx_shared *sh,\n * Pointer to the device shared context.\n */\n static void\n-mlx5_dev_ctx_shared_mempool_register_cb(struct rte_mempool *mp, void *arg)\n+mlx5_dev_ctx_shared_rx_mempool_unregister_cb(struct rte_mempool *mp, void *arg)\n {\n \tstruct mlx5_dev_ctx_shared *sh = arg;\n-\tstruct mlx5_mp_id mp_id;\n-\tint ret;\n \n-\tmlx5_mp_id_init(&mp_id, 0);\n-\tret = mlx5_mr_mempool_register(&sh->cdev->mr_scache, sh->cdev->pd, mp,\n-\t\t\t\t &mp_id);\n-\tif (ret < 0 && rte_errno != EEXIST)\n-\t\tDRV_LOG(ERR, \"Failed to register existing mempool %s for PD %p: %s\",\n-\t\t\tmp->name, sh->cdev->pd, rte_strerror(rte_errno));\n-}\n-\n-/**\n- * rte_mempool_walk() callback to unregister mempools\n- * from the protection domain.\n- *\n- * @param mp\n- * The mempool being walked.\n- * @param arg\n- * Pointer to the device shared context.\n- */\n-static void\n-mlx5_dev_ctx_shared_mempool_unregister_cb(struct rte_mempool *mp, void *arg)\n-{\n-\tmlx5_dev_ctx_shared_mempool_unregister\n-\t\t\t\t((struct mlx5_dev_ctx_shared *)arg, mp);\n-}\n-\n-/**\n- * Mempool life cycle callback for Ethernet devices.\n- *\n- * @param event\n- * Mempool life cycle event.\n- * @param mp\n- * Associated mempool.\n- * @param arg\n- * Pointer to a device shared context.\n- */\n-static void\n-mlx5_dev_ctx_shared_mempool_event_cb(enum rte_mempool_event event,\n-\t\t\t\t struct rte_mempool *mp, void *arg)\n-{\n-\tstruct mlx5_dev_ctx_shared *sh = arg;\n-\tstruct mlx5_mp_id mp_id;\n-\n-\tswitch (event) {\n-\tcase RTE_MEMPOOL_EVENT_READY:\n-\t\tmlx5_mp_id_init(&mp_id, 0);\n-\t\tif (mlx5_mr_mempool_register(&sh->cdev->mr_scache, sh->cdev->pd,\n-\t\t\t\t\t mp, &mp_id) < 0)\n-\t\t\tDRV_LOG(ERR, \"Failed to register new mempool %s for PD %p: %s\",\n-\t\t\t\tmp->name, sh->cdev->pd,\n-\t\t\t\trte_strerror(rte_errno));\n-\t\tbreak;\n-\tcase RTE_MEMPOOL_EVENT_DESTROY:\n-\t\tmlx5_dev_ctx_shared_mempool_unregister(sh, mp);\n-\t\tbreak;\n-\t}\n+\tmlx5_dev_mempool_unregister(sh->cdev, mp);\n }\n \n /**\n@@ -1206,7 +1131,7 @@ mlx5_dev_ctx_shared_rx_mempool_event_cb(enum rte_mempool_event event,\n \tstruct mlx5_dev_ctx_shared *sh = arg;\n \n \tif (event == RTE_MEMPOOL_EVENT_DESTROY)\n-\t\tmlx5_dev_ctx_shared_mempool_unregister(sh, mp);\n+\t\tmlx5_dev_mempool_unregister(sh->cdev, mp);\n }\n \n int\n@@ -1222,15 +1147,7 @@ mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev)\n \t\t\t\t(mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);\n \t\treturn ret == 0 || rte_errno == EEXIST ? 0 : ret;\n \t}\n-\t/* Callback for this shared context may be already registered. */\n-\tret = rte_mempool_event_callback_register\n-\t\t\t\t(mlx5_dev_ctx_shared_mempool_event_cb, sh);\n-\tif (ret != 0 && rte_errno != EEXIST)\n-\t\treturn ret;\n-\t/* Register mempools only once for this shared context. */\n-\tif (ret == 0)\n-\t\trte_mempool_walk(mlx5_dev_ctx_shared_mempool_register_cb, sh);\n-\treturn 0;\n+\treturn mlx5_dev_mempool_subscribe(sh->cdev);\n }\n \n /**\n@@ -1414,14 +1331,13 @@ mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)\n \tif (--sh->refcnt)\n \t\tgoto exit;\n \t/* Stop watching for mempool events and unregister all mempools. */\n-\tret = rte_mempool_event_callback_unregister\n-\t\t\t\t(mlx5_dev_ctx_shared_mempool_event_cb, sh);\n-\tif (ret < 0 && rte_errno == ENOENT)\n+\tif (!sh->cdev->config.mr_mempool_reg_en) {\n \t\tret = rte_mempool_event_callback_unregister\n \t\t\t\t(mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);\n-\tif (ret == 0)\n-\t\trte_mempool_walk(mlx5_dev_ctx_shared_mempool_unregister_cb,\n-\t\t\t\t sh);\n+\t\tif (ret == 0)\n+\t\t\trte_mempool_walk\n+\t\t\t (mlx5_dev_ctx_shared_rx_mempool_unregister_cb, sh);\n+\t}\n \t/* Remove context from the global device list. */\n \tLIST_REMOVE(sh, next);\n \t/* Release flow workspaces objects on the last device. */\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 4f823baa6d..059d400384 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -153,17 +153,6 @@ struct mlx5_flow_dump_ack {\n \tint rc; /**< Return code. */\n };\n \n-/** Key string for IPC. */\n-#define MLX5_MP_NAME \"net_mlx5_mp\"\n-\n-/** Initialize a multi-process ID. */\n-static inline void\n-mlx5_mp_id_init(struct mlx5_mp_id *mp_id, uint16_t port_id)\n-{\n-\tmp_id->port_id = port_id;\n-\tstrlcpy(mp_id->name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);\n-}\n-\n LIST_HEAD(mlx5_dev_list, mlx5_dev_ctx_shared);\n \n /* Shared data between primary and secondary processes. */\n@@ -172,8 +161,6 @@ struct mlx5_shared_data {\n \t/* Global spinlock for primary and secondary processes. */\n \tint init_done; /* Whether primary has done initialization. */\n \tunsigned int secondary_cnt; /* Number of secondary processes init'd. */\n-\tstruct mlx5_dev_list mem_event_cb_list;\n-\trte_rwlock_t mem_event_rwlock;\n };\n \n /* Per-process data structure, not visible to other processes. */\ndiff --git a/drivers/net/mlx5/mlx5_mr.c b/drivers/net/mlx5/mlx5_mr.c\ndeleted file mode 100644\nindex ac3d8e2492..0000000000\n--- a/drivers/net/mlx5/mlx5_mr.c\n+++ /dev/null\n@@ -1,89 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright 2016 6WIND S.A.\n- * Copyright 2016 Mellanox Technologies, Ltd\n- */\n-\n-#include <rte_eal_memconfig.h>\n-#include <rte_mempool.h>\n-#include <rte_malloc.h>\n-#include <rte_rwlock.h>\n-\n-#include <mlx5_common_mp.h>\n-#include <mlx5_common_mr.h>\n-\n-#include \"mlx5.h\"\n-#include \"mlx5_rxtx.h\"\n-#include \"mlx5_rx.h\"\n-#include \"mlx5_tx.h\"\n-\n-/**\n- * Bottom-half of LKey search on Tx.\n- *\n- * @param txq\n- * Pointer to Tx queue structure.\n- * @param addr\n- * Search key.\n- *\n- * @return\n- * Searched LKey on success, UINT32_MAX on no match.\n- */\n-static uint32_t\n-mlx5_tx_addr2mr_bh(struct mlx5_txq_data *txq, uintptr_t addr)\n-{\n-\tstruct mlx5_txq_ctrl *txq_ctrl =\n-\t\tcontainer_of(txq, struct mlx5_txq_ctrl, txq);\n-\tstruct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl;\n-\tstruct mlx5_priv *priv = txq_ctrl->priv;\n-\n-\treturn mlx5_mr_addr2mr_bh(priv->sh->cdev->pd, &priv->mp_id,\n-\t\t\t\t &priv->sh->cdev->mr_scache, mr_ctrl, addr,\n-\t\t\t\t priv->sh->cdev->config.mr_ext_memseg_en);\n-}\n-\n-/**\n- * Bottom-half of LKey search on Tx. If it can't be searched in the memseg\n- * list, register the mempool of the mbuf as externally allocated memory.\n- *\n- * @param txq\n- * Pointer to Tx queue structure.\n- * @param mb\n- * Pointer to mbuf.\n- *\n- * @return\n- * Searched LKey on success, UINT32_MAX on no match.\n- */\n-uint32_t\n-mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb)\n-{\n-\tstruct mlx5_txq_ctrl *txq_ctrl =\n-\t\tcontainer_of(txq, struct mlx5_txq_ctrl, txq);\n-\tstruct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl;\n-\tstruct mlx5_priv *priv = txq_ctrl->priv;\n-\tuintptr_t addr = (uintptr_t)mb->buf_addr;\n-\tuint32_t lkey;\n-\n-\tif (priv->sh->cdev->config.mr_mempool_reg_en) {\n-\t\tstruct rte_mempool *mp = NULL;\n-\t\tstruct mlx5_mprq_buf *buf;\n-\n-\t\tif (!RTE_MBUF_HAS_EXTBUF(mb)) {\n-\t\t\tmp = mlx5_mb2mp(mb);\n-\t\t} else if (mb->shinfo->free_cb == mlx5_mprq_buf_free_cb) {\n-\t\t\t/* Recover MPRQ mempool. */\n-\t\t\tbuf = mb->shinfo->fcb_opaque;\n-\t\t\tmp = buf->mp;\n-\t\t}\n-\t\tif (mp != NULL) {\n-\t\t\tlkey = mlx5_mr_mempool2mr_bh(&priv->sh->cdev->mr_scache,\n-\t\t\t\t\t\t mr_ctrl, mp, addr);\n-\t\t\t/*\n-\t\t\t * Lookup can only fail on invalid input, e.g. \"addr\"\n-\t\t\t * is not from \"mp\" or \"mp\" has MEMPOOL_F_NON_IO set.\n-\t\t\t */\n-\t\t\tif (lkey != UINT32_MAX)\n-\t\t\t\treturn lkey;\n-\t\t}\n-\t\t/* Fallback for generic mechanism in corner cases. */\n-\t}\n-\treturn mlx5_tx_addr2mr_bh(txq, addr);\n-}\ndiff --git a/drivers/net/mlx5/mlx5_rx.c b/drivers/net/mlx5/mlx5_rx.c\nindex c83c7f4a39..8fa15e9820 100644\n--- a/drivers/net/mlx5/mlx5_rx.c\n+++ b/drivers/net/mlx5/mlx5_rx.c\n@@ -18,6 +18,7 @@\n \n #include <mlx5_prm.h>\n #include <mlx5_common.h>\n+#include <mlx5_common_mr.h>\n \n #include \"mlx5_autoconf.h\"\n #include \"mlx5_defs.h\"\n@@ -1027,20 +1028,6 @@ mlx5_lro_update_hdr(uint8_t *__rte_restrict padd,\n \tmlx5_lro_update_tcp_hdr(h.tcp, cqe, phcsum, l4_type);\n }\n \n-void\n-mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)\n-{\n-\tstruct mlx5_mprq_buf *buf = opaque;\n-\n-\tif (__atomic_load_n(&buf->refcnt, __ATOMIC_RELAXED) == 1) {\n-\t\trte_mempool_put(buf->mp, buf);\n-\t} else if (unlikely(__atomic_sub_fetch(&buf->refcnt, 1,\n-\t\t\t\t\t __ATOMIC_RELAXED) == 0)) {\n-\t\t__atomic_store_n(&buf->refcnt, 1, __ATOMIC_RELAXED);\n-\t\trte_mempool_put(buf->mp, buf);\n-\t}\n-}\n-\n void\n mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)\n {\ndiff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h\nindex 42a12151fc..84a21fbfb9 100644\n--- a/drivers/net/mlx5/mlx5_rx.h\n+++ b/drivers/net/mlx5/mlx5_rx.h\n@@ -43,19 +43,6 @@ struct rxq_zip {\n \tuint32_t cqe_cnt; /* Number of CQEs. */\n };\n \n-/* Multi-Packet RQ buffer header. */\n-struct mlx5_mprq_buf {\n-\tstruct rte_mempool *mp;\n-\tuint16_t refcnt; /* Atomically accessed refcnt. */\n-\tuint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */\n-\tstruct rte_mbuf_ext_shared_info shinfos[];\n-\t/*\n-\t * Shared information per stride.\n-\t * More memory will be allocated for the first stride head-room and for\n-\t * the strides data.\n-\t */\n-} __rte_cache_aligned;\n-\n /* Get pointer to the first stride. */\n #define mlx5_mprq_buf_addr(ptr, strd_n) (RTE_PTR_ADD((ptr), \\\n \t\t\t\tsizeof(struct mlx5_mprq_buf) + \\\n@@ -255,7 +242,6 @@ int mlx5_hrxq_modify(struct rte_eth_dev *dev, uint32_t hxrq_idx,\n uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);\n void mlx5_rxq_initialize(struct mlx5_rxq_data *rxq);\n __rte_noinline int mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec);\n-void mlx5_mprq_buf_free_cb(void *addr, void *opaque);\n void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf);\n uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts,\n \t\t\t uint16_t pkts_n);\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex 174899e661..e1a4ded688 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -21,6 +21,7 @@\n \n #include <mlx5_glue.h>\n #include <mlx5_malloc.h>\n+#include <mlx5_common_mr.h>\n \n #include \"mlx5_defs.h\"\n #include \"mlx5.h\"\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex b400295e7d..876aa14ae6 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -43,30 +43,4 @@ int mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,\n int mlx5_queue_state_modify(struct rte_eth_dev *dev,\n \t\t\t struct mlx5_mp_arg_queue_state_modify *sm);\n \n-/* mlx5_mr.c */\n-\n-void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl);\n-int mlx5_net_dma_map(struct rte_device *rte_dev, void *addr, uint64_t iova,\n-\t\t size_t len);\n-int mlx5_net_dma_unmap(struct rte_device *rte_dev, void *addr, uint64_t iova,\n-\t\t size_t len);\n-\n-/**\n- * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the\n- * cloned mbuf is allocated is returned instead.\n- *\n- * @param buf\n- * Pointer to mbuf.\n- *\n- * @return\n- * Memory pool where data is located for given mbuf.\n- */\n-static inline struct rte_mempool *\n-mlx5_mb2mp(struct rte_mbuf *buf)\n-{\n-\tif (unlikely(RTE_MBUF_CLONED(buf)))\n-\t\treturn rte_mbuf_from_indirect(buf)->pool;\n-\treturn buf->pool;\n-}\n-\n #endif /* RTE_PMD_MLX5_RXTX_H_ */\ndiff --git a/drivers/net/mlx5/mlx5_tx.h b/drivers/net/mlx5/mlx5_tx.h\nindex 1f124b92e6..de2e284929 100644\n--- a/drivers/net/mlx5/mlx5_tx.h\n+++ b/drivers/net/mlx5/mlx5_tx.h\n@@ -235,10 +235,6 @@ void mlx5_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,\n int mlx5_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,\n \t\t\t struct rte_eth_burst_mode *mode);\n \n-/* mlx5_mr.c */\n-\n-uint32_t mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb);\n-\n /* mlx5_tx_empw.c */\n \n MLX5_TXOFF_PRE_DECL(full_empw);\n@@ -356,12 +352,12 @@ __mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock)\n #endif\n \n /**\n- * Query LKey from a packet buffer for Tx. If not found, add the mempool.\n+ * Query LKey from a packet buffer for Tx.\n *\n * @param txq\n * Pointer to Tx queue structure.\n- * @param addr\n- * Address to search.\n+ * @param mb\n+ * Pointer to mbuf.\n *\n * @return\n * Searched LKey on success, UINT32_MAX on no match.\n@@ -370,19 +366,12 @@ static __rte_always_inline uint32_t\n mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)\n {\n \tstruct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl;\n-\tuintptr_t addr = (uintptr_t)mb->buf_addr;\n-\tuint32_t lkey;\n-\n-\t/* Check generation bit to see if there's any change on existing MRs. */\n-\tif (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))\n-\t\tmlx5_mr_flush_local_cache(mr_ctrl);\n-\t/* Linear search on MR cache array. */\n-\tlkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,\n-\t\t\t\t MLX5_MR_CACHE_N, addr);\n-\tif (likely(lkey != UINT32_MAX))\n-\t\treturn lkey;\n+\tstruct mlx5_txq_ctrl *txq_ctrl =\n+\t\t\tcontainer_of(txq, struct mlx5_txq_ctrl, txq);\n+\tstruct mlx5_priv *priv = txq_ctrl->priv;\n+\n \t/* Take slower bottom-half on miss. */\n-\treturn mlx5_tx_mb2mr_bh(txq, mb);\n+\treturn mlx5_mr_mb2mr(priv->sh->cdev, &priv->mp_id, mr_ctrl, mb);\n }\n \n /**\ndiff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c\nindex a79fb7e5be..cf46a0bd23 100644\n--- a/drivers/regex/mlx5/mlx5_regex.c\n+++ b/drivers/regex/mlx5/mlx5_regex.c\n@@ -36,9 +36,11 @@ const struct rte_regexdev_ops mlx5_regexdev_ops = {\n };\n \n int\n-mlx5_regex_start(struct rte_regexdev *dev __rte_unused)\n+mlx5_regex_start(struct rte_regexdev *dev)\n {\n-\treturn 0;\n+\tstruct mlx5_regex_priv *priv = dev->data->dev_private;\n+\n+\treturn mlx5_dev_mempool_subscribe(priv->cdev);\n }\n \n int\n", "prefixes": [ "18/18" ] }