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GET /api/patches/100178/?format=api
{ "id": 100178, "url": "http://patches.dpdk.org/api/patches/100178/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210930172822.1949969-9-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210930172822.1949969-9-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210930172822.1949969-9-michaelba@nvidia.com", "date": "2021-09-30T17:28:12", "name": "[08/18] common/mlx5: share device context object", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "92cdb6356020dc28bdedd2900ccb9340fab2dc85", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210930172822.1949969-9-michaelba@nvidia.com/mbox/", "series": [ { "id": 19311, "url": "http://patches.dpdk.org/api/series/19311/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19311", "date": "2021-09-30T17:28:04", "name": "mlx5: sharing global MR cache between drivers", "version": 1, "mbox": "http://patches.dpdk.org/series/19311/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/100178/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/100178/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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SFS:(4636009)(46966006)(36840700001)(336012)(186003)(6666004)(36860700001)(26005)(508600001)(7636003)(356005)(2616005)(8936002)(47076005)(7696005)(2906002)(86362001)(2876002)(55016002)(30864003)(83380400001)(5660300002)(426003)(8676002)(4326008)(1076003)(107886003)(316002)(70206006)(54906003)(70586007)(6916009)(6286002)(16526019)(36756003)(82310400003)(559001)(579004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Sep 2021 17:28:58.5009 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 05688933-f027-48dc-8a88-08d98437c96e", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT010.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR12MB3840", "X-Mailman-Approved-At": "Thu, 30 Sep 2021 19:39:43 +0200", "Subject": "[dpdk-dev] [PATCH 08/18] common/mlx5: share device context object", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Michael Baum <michaelba@oss.nvidia.com>\n\nCreate shared context device in common area and add it as a field of\ncommon device.\nUse this context device in all drivers and remove the ctx field from\ntheir private structure.\n\nSigned-off-by: Michael Baum <michaelba@oss.nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/linux/mlx5_common_os.c | 19 ++-\n drivers/common/mlx5/mlx5_common.c | 54 ++++++++-\n drivers/common/mlx5/mlx5_common.h | 4 +-\n drivers/common/mlx5/version.map | 1 -\n drivers/common/mlx5/windows/mlx5_common_os.c | 27 +++--\n drivers/compress/mlx5/mlx5_compress.c | 40 ++----\n drivers/crypto/mlx5/mlx5_crypto.c | 46 +++----\n drivers/crypto/mlx5/mlx5_crypto.h | 2 +-\n drivers/crypto/mlx5/mlx5_crypto_dek.c | 3 +-\n drivers/net/mlx5/linux/mlx5_ethdev_os.c | 6 +-\n drivers/net/mlx5/linux/mlx5_mp_os.c | 5 +-\n drivers/net/mlx5/linux/mlx5_os.c | 121 ++++++++-----------\n drivers/net/mlx5/linux/mlx5_verbs.c | 43 ++++---\n drivers/net/mlx5/mlx5.c | 45 +++----\n drivers/net/mlx5/mlx5.h | 2 -\n drivers/net/mlx5/mlx5_devx.c | 24 ++--\n drivers/net/mlx5/mlx5_flow.c | 4 +-\n drivers/net/mlx5/mlx5_flow_aso.c | 7 +-\n drivers/net/mlx5/mlx5_flow_dv.c | 31 ++---\n drivers/net/mlx5/mlx5_flow_verbs.c | 4 +-\n drivers/net/mlx5/mlx5_txpp.c | 13 +-\n drivers/net/mlx5/windows/mlx5_ethdev_os.c | 12 +-\n drivers/net/mlx5/windows/mlx5_os.c | 23 ++--\n drivers/regex/mlx5/mlx5_regex.c | 41 ++-----\n drivers/regex/mlx5/mlx5_regex.h | 2 +-\n drivers/regex/mlx5/mlx5_regex_control.c | 4 +-\n drivers/regex/mlx5/mlx5_regex_fastpath.c | 4 +-\n drivers/regex/mlx5/mlx5_rxp.c | 62 +++++-----\n 28 files changed, 321 insertions(+), 328 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/linux/mlx5_common_os.c b/drivers/common/mlx5/linux/mlx5_common_os.c\nindex 2aa5684b05..1589212172 100644\n--- a/drivers/common/mlx5/linux/mlx5_common_os.c\n+++ b/drivers/common/mlx5/linux/mlx5_common_os.c\n@@ -424,8 +424,13 @@ mlx5_os_get_ibv_device(const struct rte_pci_addr *addr)\n \t\tibv_match = ibv_list[n];\n \t\tbreak;\n \t}\n-\tif (ibv_match == NULL)\n+\tif (ibv_match == NULL) {\n+\t\tDRV_LOG(WARNING,\n+\t\t\t\"No Verbs device matches PCI device \" PCI_PRI_FMT \",\"\n+\t\t\t\" are kernel drivers loaded?\",\n+\t\t\taddr->domain, addr->bus, addr->devid, addr->function);\n \t\trte_errno = ENOENT;\n+\t}\n \tmlx5_glue->free_device_list(ibv_list);\n \treturn ibv_match;\n }\n@@ -465,14 +470,14 @@ mlx5_restore_doorbell_mapping_env(int value)\n *\n * @param cdev\n * Pointer to the mlx5 device.\n- * @param ctx_ptr\n- * Pointer to fill inside pointer to device context.\n+ * @param classes\n+ * Chosen classes come from device arguments.\n *\n * @return\n * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n int\n-mlx5_os_open_device(struct mlx5_common_device *cdev, void **ctx_ptr)\n+mlx5_os_open_device(struct mlx5_common_device *cdev, uint32_t classes)\n {\n \tstruct ibv_device *ibv;\n \tstruct ibv_context *ctx = NULL;\n@@ -494,18 +499,20 @@ mlx5_os_open_device(struct mlx5_common_device *cdev, void **ctx_ptr)\n \tif (ctx) {\n \t\tcdev->config.devx = 1;\n \t\tDRV_LOG(DEBUG, \"DevX is supported.\");\n-\t} else {\n+\t} else if (classes == MLX5_CLASS_ETH) {\n \t\t/* The environment variable is still configured. */\n \t\tctx = mlx5_glue->open_device(ibv);\n \t\tif (ctx == NULL)\n \t\t\tgoto error;\n \t\tDRV_LOG(DEBUG, \"DevX is NOT supported.\");\n+\t} else {\n+\t\tgoto error;\n \t}\n \t/* The device is created, no need for environment. */\n \tmlx5_restore_doorbell_mapping_env(dbmap_env);\n \t/* Hint libmlx5 to use PMD allocator for data plane resources */\n \tmlx5_set_context_attr(cdev->dev, ctx);\n-\t*ctx_ptr = (void *)ctx;\n+\tcdev->ctx = ctx;\n \treturn 0;\n error:\n \trte_errno = errno ? errno : ENODEV;\ndiff --git a/drivers/common/mlx5/mlx5_common.c b/drivers/common/mlx5/mlx5_common.c\nindex 0ad9e09972..5786b5c0b9 100644\n--- a/drivers/common/mlx5/mlx5_common.c\n+++ b/drivers/common/mlx5/mlx5_common.c\n@@ -308,17 +308,60 @@ mlx5_dev_to_pci_str(const struct rte_device *dev, char *addr, size_t size)\n #endif\n }\n \n+/**\n+ * Uninitialize all HW global of device context.\n+ *\n+ * @param cdev\n+ * Pointer to mlx5 device structure.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static void\n+mlx5_dev_hw_global_release(struct mlx5_common_device *cdev)\n+{\n+\tif (cdev->ctx != NULL) {\n+\t\tclaim_zero(mlx5_glue->close_device(cdev->ctx));\n+\t\tcdev->ctx = NULL;\n+\t}\n+}\n+\n+/**\n+ * Initialize all HW global of device context.\n+ *\n+ * @param cdev\n+ * Pointer to mlx5 device structure.\n+ * @param classes\n+ * Chosen classes come from user device arguments.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static int\n+mlx5_dev_hw_global_prepare(struct mlx5_common_device *cdev, uint32_t classes)\n+{\n+\tint ret;\n+\n+\t/* Create context device */\n+\tret = mlx5_os_open_device(cdev, classes);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\treturn 0;\n+}\n+\n static void\n mlx5_common_dev_release(struct mlx5_common_device *cdev)\n {\n \tpthread_mutex_lock(&devices_list_lock);\n \tTAILQ_REMOVE(&devices_list, cdev, next);\n \tpthread_mutex_unlock(&devices_list_lock);\n+\tif (rte_eal_process_type() == RTE_PROC_PRIMARY)\n+\t\tmlx5_dev_hw_global_release(cdev);\n \trte_free(cdev);\n }\n \n static struct mlx5_common_device *\n-mlx5_common_dev_create(struct rte_device *eal_dev)\n+mlx5_common_dev_create(struct rte_device *eal_dev, uint32_t classes)\n {\n \tstruct mlx5_common_device *cdev;\n \tint ret;\n@@ -341,6 +384,13 @@ mlx5_common_dev_create(struct rte_device *eal_dev)\n \t\treturn NULL;\n \t}\n \tmlx5_malloc_mem_select(cdev->config.sys_mem_en);\n+\t/* Initialize all HW global of device context. */\n+\tret = mlx5_dev_hw_global_prepare(cdev, classes);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Failed to initialize device context.\");\n+\t\trte_free(cdev);\n+\t\treturn NULL;\n+\t}\n exit:\n \tpthread_mutex_lock(&devices_list_lock);\n \tTAILQ_INSERT_HEAD(&devices_list, cdev, next);\n@@ -433,7 +483,7 @@ mlx5_common_dev_probe(struct rte_device *eal_dev)\n \t\tclasses = MLX5_CLASS_ETH;\n \tcdev = to_mlx5_device(eal_dev);\n \tif (!cdev) {\n-\t\tcdev = mlx5_common_dev_create(eal_dev);\n+\t\tcdev = mlx5_common_dev_create(eal_dev, classes);\n \t\tif (!cdev)\n \t\t\treturn -ENOMEM;\n \t\tnew_device = true;\ndiff --git a/drivers/common/mlx5/mlx5_common.h b/drivers/common/mlx5/mlx5_common.h\nindex f36791f24e..d7d9e43a4d 100644\n--- a/drivers/common/mlx5/mlx5_common.h\n+++ b/drivers/common/mlx5/mlx5_common.h\n@@ -346,6 +346,7 @@ struct mlx5_common_device {\n \tstruct rte_device *dev;\n \tTAILQ_ENTRY(mlx5_common_device) next;\n \tuint32_t classes_loaded;\n+\tvoid *ctx; /* Verbs/DV/DevX context. */\n \tstruct mlx5_common_dev_config config; /* Device configuration. */\n };\n \n@@ -446,7 +447,6 @@ mlx5_dev_is_pci(const struct rte_device *dev);\n \n /* mlx5_common_os.c */\n \n-__rte_internal\n-int mlx5_os_open_device(struct mlx5_common_device *cdev, void **ctx);\n+int mlx5_os_open_device(struct mlx5_common_device *cdev, uint32_t classes);\n \n #endif /* RTE_PMD_MLX5_COMMON_H_ */\ndiff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map\nindex bcee26b7ea..37a0ffef4b 100644\n--- a/drivers/common/mlx5/version.map\n+++ b/drivers/common/mlx5/version.map\n@@ -141,7 +141,6 @@ INTERNAL {\n \tmlx5_os_dealloc_pd;\n \tmlx5_os_dereg_mr;\n \tmlx5_os_get_ibv_dev; # WINDOWS_NO_EXPORT\n- mlx5_os_open_device;\n \tmlx5_os_reg_mr;\n \tmlx5_os_umem_dereg;\n \tmlx5_os_umem_reg;\ndiff --git a/drivers/common/mlx5/windows/mlx5_common_os.c b/drivers/common/mlx5/windows/mlx5_common_os.c\nindex e426a955ff..b7178cbbcf 100644\n--- a/drivers/common/mlx5/windows/mlx5_common_os.c\n+++ b/drivers/common/mlx5/windows/mlx5_common_os.c\n@@ -7,6 +7,7 @@\n #include <stdio.h>\n \n #include <rte_mempool.h>\n+#include <rte_bus_pci.h>\n #include <rte_malloc.h>\n #include <rte_errno.h>\n \n@@ -17,7 +18,7 @@\n #include \"mlx5_malloc.h\"\n \n /**\n- * Initialization routine for run-time dependency on external lib\n+ * Initialization routine for run-time dependency on external lib.\n */\n void\n mlx5_glue_constructor(void)\n@@ -25,7 +26,7 @@ mlx5_glue_constructor(void)\n }\n \n /**\n- * Allocate PD. Given a devx context object\n+ * Allocate PD. Given a DevX context object\n * return an mlx5-pd object.\n *\n * @param[in] ctx\n@@ -37,8 +38,8 @@ mlx5_glue_constructor(void)\n void *\n mlx5_os_alloc_pd(void *ctx)\n {\n-\tstruct mlx5_pd *ppd = mlx5_malloc(MLX5_MEM_ZERO,\n-\t\tsizeof(struct mlx5_pd), 0, SOCKET_ID_ANY);\n+\tstruct mlx5_pd *ppd = mlx5_malloc(MLX5_MEM_ZERO, sizeof(struct mlx5_pd),\n+\t\t\t\t\t 0, SOCKET_ID_ANY);\n \tif (!ppd)\n \t\treturn NULL;\n \n@@ -60,7 +61,7 @@ mlx5_os_alloc_pd(void *ctx)\n * Pointer to mlx5_pd.\n *\n * @return\n- * Zero if pd is released successfully, negative number otherwise.\n+ * Zero if pd is released successfully, negative number otherwise.\n */\n int\n mlx5_os_dealloc_pd(void *pd)\n@@ -184,22 +185,28 @@ mlx5_os_get_devx_device(struct rte_device *dev,\n *\n * This function calls the Windows glue APIs to open a device.\n *\n- * @param dev\n+ * @param cdev\n * Pointer to mlx5 device structure.\n- * @param ctx\n- * Pointer to fill inside pointer to device context.\n+ * @param classes\n+ * Chosen classes come from user device arguments.\n *\n * @return\n * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n int\n-mlx5_os_open_device(struct mlx5_common_device *cdev, void **ctx)\n+mlx5_os_open_device(struct mlx5_common_device *cdev, uint32_t classes)\n {\n \tstruct devx_device_bdf *devx_bdf_dev = NULL;\n \tstruct devx_device_bdf *devx_list;\n \tstruct mlx5_context *mlx5_ctx = NULL;\n \tint n;\n \n+\tif (classes != MLX5_CLASS_ETH) {\n+\t\tDRV_LOG(ERR,\n+\t\t\t\"The chosen classes are not supported on Windows.\");\n+\t\trte_errno = ENOTSUP;\n+\t\treturn -rte_errno;\n+\t}\n \terrno = 0;\n \tdevx_list = mlx5_glue->get_device_list(&n);\n \tif (devx_list == NULL) {\n@@ -223,7 +230,7 @@ mlx5_os_open_device(struct mlx5_common_device *cdev, void **ctx)\n \t\tgoto error;\n \t}\n \tcdev->config.devx = 1;\n-\t*ctx = (void *)mlx5_ctx;\n+\tcdev->ctx = mlx5_ctx;\n \tmlx5_glue->free_device_list(devx_list);\n \treturn 0;\n error:\ndiff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c\nindex afb63e9b8f..4967e71c96 100644\n--- a/drivers/compress/mlx5/mlx5_compress.c\n+++ b/drivers/compress/mlx5/mlx5_compress.c\n@@ -35,8 +35,8 @@ struct mlx5_compress_xform {\n \n struct mlx5_compress_priv {\n \tTAILQ_ENTRY(mlx5_compress_priv) next;\n-\tstruct ibv_context *ctx; /* Device context. */\n \tstruct rte_compressdev *compressdev;\n+\tstruct mlx5_common_device *cdev; /* Backend mlx5 device. */\n \tvoid *uar;\n \tuint32_t pdn; /* Protection Domain number. */\n \tuint8_t min_block_size;\n@@ -236,7 +236,7 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,\n \t\trte_errno = ENOMEM;\n \t\tgoto err;\n \t}\n-\tret = mlx5_devx_cq_create(priv->ctx, &qp->cq, log_ops_n, &cq_attr,\n+\tret = mlx5_devx_cq_create(priv->cdev->ctx, &qp->cq, log_ops_n, &cq_attr,\n \t\t\t\t socket_id);\n \tif (ret != 0) {\n \t\tDRV_LOG(ERR, \"Failed to create CQ.\");\n@@ -244,7 +244,7 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,\n \t}\n \tsq_attr.cqn = qp->cq.cq->id;\n \tsq_attr.ts_format = mlx5_ts_format_conv(priv->sq_ts_format);\n-\tret = mlx5_devx_sq_create(priv->ctx, &qp->sq, log_ops_n, &sq_attr,\n+\tret = mlx5_devx_sq_create(priv->cdev->ctx, &qp->sq, log_ops_n, &sq_attr,\n \t\t\t\t socket_id);\n \tif (ret != 0) {\n \t\tDRV_LOG(ERR, \"Failed to create SQ.\");\n@@ -707,7 +707,7 @@ mlx5_compress_pd_create(struct mlx5_compress_priv *priv)\n \tstruct mlx5dv_pd pd_info;\n \tint ret;\n \n-\tpriv->pd = mlx5_glue->alloc_pd(priv->ctx);\n+\tpriv->pd = mlx5_glue->alloc_pd(priv->cdev->ctx);\n \tif (priv->pd == NULL) {\n \t\tDRV_LOG(ERR, \"Failed to allocate PD.\");\n \t\treturn errno ? -errno : -ENOMEM;\n@@ -735,7 +735,7 @@ mlx5_compress_hw_global_prepare(struct mlx5_compress_priv *priv)\n {\n \tif (mlx5_compress_pd_create(priv) != 0)\n \t\treturn -1;\n-\tpriv->uar = mlx5_devx_alloc_uar(priv->ctx, -1);\n+\tpriv->uar = mlx5_devx_alloc_uar(priv->cdev->ctx, -1);\n \tif (priv->uar == NULL || mlx5_os_get_devx_uar_reg_addr(priv->uar) ==\n \t NULL) {\n \t\trte_errno = errno;\n@@ -775,7 +775,8 @@ mlx5_compress_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr,\n \t\t/* Iterate all the existing mlx5 devices. */\n \t\tTAILQ_FOREACH(priv, &mlx5_compress_priv_list, next)\n \t\t\tmlx5_free_mr_by_addr(&priv->mr_scache,\n-\t\t\t\t\t priv->ctx->device->name,\n+\t\t\t\t\t mlx5_os_get_ctx_device_name\n+\t\t\t\t\t\t\t (priv->cdev->ctx),\n \t\t\t\t\t addr, len);\n \t\tpthread_mutex_unlock(&priv_list_lock);\n \t\tbreak;\n@@ -788,60 +789,47 @@ mlx5_compress_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr,\n static int\n mlx5_compress_dev_probe(struct mlx5_common_device *cdev)\n {\n-\tstruct ibv_device *ibv;\n \tstruct rte_compressdev *compressdev;\n-\tstruct ibv_context *ctx;\n \tstruct mlx5_compress_priv *priv;\n \tstruct mlx5_hca_attr att = { 0 };\n \tstruct rte_compressdev_pmd_init_params init_params = {\n \t\t.name = \"\",\n \t\t.socket_id = cdev->dev->numa_node,\n \t};\n+\tconst char *ibdev_name = mlx5_os_get_ctx_device_name(cdev->ctx);\n \n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY) {\n \t\tDRV_LOG(ERR, \"Non-primary process type is not supported.\");\n \t\trte_errno = ENOTSUP;\n \t\treturn -rte_errno;\n \t}\n-\tibv = mlx5_os_get_ibv_dev(cdev->dev);\n-\tif (ibv == NULL)\n-\t\treturn -rte_errno;\n-\tctx = mlx5_glue->dv_open_device(ibv);\n-\tif (ctx == NULL) {\n-\t\tDRV_LOG(ERR, \"Failed to open IB device \\\"%s\\\".\", ibv->name);\n-\t\trte_errno = ENODEV;\n-\t\treturn -rte_errno;\n-\t}\n-\tif (mlx5_devx_cmd_query_hca_attr(ctx, &att) != 0 ||\n+\tif (mlx5_devx_cmd_query_hca_attr(cdev->ctx, &att) != 0 ||\n \t att.mmo_compress_en == 0 || att.mmo_decompress_en == 0 ||\n \t att.mmo_dma_en == 0) {\n \t\tDRV_LOG(ERR, \"Not enough capabilities to support compress \"\n \t\t\t\"operations, maybe old FW/OFED version?\");\n-\t\tclaim_zero(mlx5_glue->close_device(ctx));\n \t\trte_errno = ENOTSUP;\n \t\treturn -ENOTSUP;\n \t}\n-\tcompressdev = rte_compressdev_pmd_create(ibv->name, cdev->dev,\n+\tcompressdev = rte_compressdev_pmd_create(ibdev_name, cdev->dev,\n \t\t\t\t\t\t sizeof(*priv), &init_params);\n \tif (compressdev == NULL) {\n-\t\tDRV_LOG(ERR, \"Failed to create device \\\"%s\\\".\", ibv->name);\n-\t\tclaim_zero(mlx5_glue->close_device(ctx));\n+\t\tDRV_LOG(ERR, \"Failed to create device \\\"%s\\\".\", ibdev_name);\n \t\treturn -ENODEV;\n \t}\n \tDRV_LOG(INFO,\n-\t\t\"Compress device %s was created successfully.\", ibv->name);\n+\t\t\"Compress device %s was created successfully.\", ibdev_name);\n \tcompressdev->dev_ops = &mlx5_compress_ops;\n \tcompressdev->dequeue_burst = mlx5_compress_dequeue_burst;\n \tcompressdev->enqueue_burst = mlx5_compress_enqueue_burst;\n \tcompressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;\n \tpriv = compressdev->data->dev_private;\n-\tpriv->ctx = ctx;\n+\tpriv->cdev = cdev;\n \tpriv->compressdev = compressdev;\n \tpriv->min_block_size = att.compress_min_block_size;\n \tpriv->sq_ts_format = att.sq_ts_format;\n \tif (mlx5_compress_hw_global_prepare(priv) != 0) {\n \t\trte_compressdev_pmd_destroy(priv->compressdev);\n-\t\tclaim_zero(mlx5_glue->close_device(priv->ctx));\n \t\treturn -1;\n \t}\n \tif (mlx5_mr_btree_init(&priv->mr_scache.cache,\n@@ -849,7 +837,6 @@ mlx5_compress_dev_probe(struct mlx5_common_device *cdev)\n \t\tDRV_LOG(ERR, \"Failed to allocate shared cache MR memory.\");\n \t\tmlx5_compress_hw_global_release(priv);\n \t\trte_compressdev_pmd_destroy(priv->compressdev);\n-\t\tclaim_zero(mlx5_glue->close_device(priv->ctx));\n \t\trte_errno = ENOMEM;\n \t\treturn -rte_errno;\n \t}\n@@ -885,7 +872,6 @@ mlx5_compress_dev_remove(struct mlx5_common_device *cdev)\n \t\tmlx5_mr_release_cache(&priv->mr_scache);\n \t\tmlx5_compress_hw_global_release(priv);\n \t\trte_compressdev_pmd_destroy(priv->compressdev);\n-\t\tclaim_zero(mlx5_glue->close_device(priv->ctx));\n \t}\n \treturn 0;\n }\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex b07cff40f1..0902e3f082 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -652,7 +652,7 @@ mlx5_crypto_indirect_mkeys_prepare(struct mlx5_crypto_priv *priv,\n \tfor (umr = (struct mlx5_umr_wqe *)qp->umem_buf, i = 0;\n \t i < qp->entries_n; i++, umr = RTE_PTR_ADD(umr, priv->wqe_set_size)) {\n \t\tattr.klm_array = (struct mlx5_klm *)&umr->kseg[0];\n-\t\tqp->mkey[i] = mlx5_devx_cmd_mkey_create(priv->ctx, &attr);\n+\t\tqp->mkey[i] = mlx5_devx_cmd_mkey_create(priv->cdev->ctx, &attr);\n \t\tif (!qp->mkey[i])\n \t\t\tgoto error;\n \t}\n@@ -693,7 +693,7 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \t\trte_errno = ENOMEM;\n \t\treturn -rte_errno;\n \t}\n-\tif (mlx5_devx_cq_create(priv->ctx, &qp->cq_obj, log_nb_desc,\n+\tif (mlx5_devx_cq_create(priv->cdev->ctx, &qp->cq_obj, log_nb_desc,\n \t\t\t\t&cq_attr, socket_id) != 0) {\n \t\tDRV_LOG(ERR, \"Failed to create CQ.\");\n \t\tgoto error;\n@@ -704,7 +704,7 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \t\trte_errno = ENOMEM;\n \t\tgoto error;\n \t}\n-\tqp->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,\n+\tqp->umem_obj = mlx5_glue->devx_umem_reg(priv->cdev->ctx,\n \t\t\t\t\t (void *)(uintptr_t)qp->umem_buf,\n \t\t\t\t\t umem_size,\n \t\t\t\t\t IBV_ACCESS_LOCAL_WRITE);\n@@ -732,7 +732,7 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \tattr.dbr_umem_id = qp->umem_obj->umem_id;\n \tattr.ts_format = mlx5_ts_format_conv(priv->qp_ts_format);\n \tattr.dbr_address = RTE_BIT64(log_nb_desc) * priv->wqe_set_size;\n-\tqp->qp_obj = mlx5_devx_cmd_create_qp(priv->ctx, &attr);\n+\tqp->qp_obj = mlx5_devx_cmd_create_qp(priv->cdev->ctx, &attr);\n \tif (qp->qp_obj == NULL) {\n \t\tDRV_LOG(ERR, \"Failed to create QP(%u).\", rte_errno);\n \t\tgoto error;\n@@ -824,7 +824,7 @@ mlx5_crypto_pd_create(struct mlx5_crypto_priv *priv)\n \tstruct mlx5dv_pd pd_info;\n \tint ret;\n \n-\tpriv->pd = mlx5_glue->alloc_pd(priv->ctx);\n+\tpriv->pd = mlx5_glue->alloc_pd(priv->cdev->ctx);\n \tif (priv->pd == NULL) {\n \t\tDRV_LOG(ERR, \"Failed to allocate PD.\");\n \t\treturn errno ? -errno : -ENOMEM;\n@@ -852,7 +852,7 @@ mlx5_crypto_hw_global_prepare(struct mlx5_crypto_priv *priv)\n {\n \tif (mlx5_crypto_pd_create(priv) != 0)\n \t\treturn -1;\n-\tpriv->uar = mlx5_devx_alloc_uar(priv->ctx, -1);\n+\tpriv->uar = mlx5_devx_alloc_uar(priv->cdev->ctx, -1);\n \tif (priv->uar)\n \t\tpriv->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar);\n \tif (priv->uar == NULL || priv->uar_addr == NULL) {\n@@ -990,7 +990,8 @@ mlx5_crypto_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr,\n \t\t/* Iterate all the existing mlx5 devices. */\n \t\tTAILQ_FOREACH(priv, &mlx5_crypto_priv_list, next)\n \t\t\tmlx5_free_mr_by_addr(&priv->mr_scache,\n-\t\t\t\t\t priv->ctx->device->name,\n+\t\t\t\t\t mlx5_os_get_ctx_device_name\n+\t\t\t\t\t\t\t (priv->cdev->ctx),\n \t\t\t\t\t addr, len);\n \t\tpthread_mutex_unlock(&priv_list_lock);\n \t\tbreak;\n@@ -1003,9 +1004,7 @@ mlx5_crypto_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr,\n static int\n mlx5_crypto_dev_probe(struct mlx5_common_device *cdev)\n {\n-\tstruct ibv_device *ibv;\n \tstruct rte_cryptodev *crypto_dev;\n-\tstruct ibv_context *ctx;\n \tstruct mlx5_devx_obj *login;\n \tstruct mlx5_crypto_priv *priv;\n \tstruct mlx5_crypto_devarg_params devarg_prms = { 0 };\n@@ -1017,6 +1016,7 @@ mlx5_crypto_dev_probe(struct mlx5_common_device *cdev)\n \t\t.max_nb_queue_pairs =\n \t\t\t\tRTE_CRYPTODEV_PMD_DEFAULT_MAX_NB_QUEUE_PAIRS,\n \t};\n+\tconst char *ibdev_name = mlx5_os_get_ctx_device_name(cdev->ctx);\n \tuint16_t rdmw_wqe_size;\n \tint ret;\n \n@@ -1025,58 +1025,44 @@ mlx5_crypto_dev_probe(struct mlx5_common_device *cdev)\n \t\trte_errno = ENOTSUP;\n \t\treturn -rte_errno;\n \t}\n-\tibv = mlx5_os_get_ibv_dev(cdev->dev);\n-\tif (ibv == NULL)\n-\t\treturn -rte_errno;\n-\tctx = mlx5_glue->dv_open_device(ibv);\n-\tif (ctx == NULL) {\n-\t\tDRV_LOG(ERR, \"Failed to open IB device \\\"%s\\\".\", ibv->name);\n-\t\trte_errno = ENODEV;\n-\t\treturn -rte_errno;\n-\t}\n-\tif (mlx5_devx_cmd_query_hca_attr(ctx, &attr) != 0 ||\n+\tif (mlx5_devx_cmd_query_hca_attr(cdev->ctx, &attr) != 0 ||\n \t attr.crypto == 0 || attr.aes_xts == 0) {\n \t\tDRV_LOG(ERR, \"Not enough capabilities to support crypto \"\n \t\t\t\"operations, maybe old FW/OFED version?\");\n-\t\tclaim_zero(mlx5_glue->close_device(ctx));\n \t\trte_errno = ENOTSUP;\n \t\treturn -ENOTSUP;\n \t}\n \tret = mlx5_crypto_parse_devargs(cdev->dev->devargs, &devarg_prms);\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"Failed to parse devargs.\");\n-\t\tclaim_zero(mlx5_glue->close_device(ctx));\n \t\treturn -rte_errno;\n \t}\n-\tlogin = mlx5_devx_cmd_create_crypto_login_obj(ctx,\n+\tlogin = mlx5_devx_cmd_create_crypto_login_obj(cdev->ctx,\n \t\t\t\t\t\t &devarg_prms.login_attr);\n \tif (login == NULL) {\n \t\tDRV_LOG(ERR, \"Failed to configure login.\");\n-\t\tclaim_zero(mlx5_glue->close_device(ctx));\n \t\treturn -rte_errno;\n \t}\n-\tcrypto_dev = rte_cryptodev_pmd_create(ibv->name, cdev->dev,\n+\tcrypto_dev = rte_cryptodev_pmd_create(ibdev_name, cdev->dev,\n \t\t\t\t\t &init_params);\n \tif (crypto_dev == NULL) {\n-\t\tDRV_LOG(ERR, \"Failed to create device \\\"%s\\\".\", ibv->name);\n-\t\tclaim_zero(mlx5_glue->close_device(ctx));\n+\t\tDRV_LOG(ERR, \"Failed to create device \\\"%s\\\".\", ibdev_name);\n \t\treturn -ENODEV;\n \t}\n \tDRV_LOG(INFO,\n-\t\t\"Crypto device %s was created successfully.\", ibv->name);\n+\t\t\"Crypto device %s was created successfully.\", ibdev_name);\n \tcrypto_dev->dev_ops = &mlx5_crypto_ops;\n \tcrypto_dev->dequeue_burst = mlx5_crypto_dequeue_burst;\n \tcrypto_dev->enqueue_burst = mlx5_crypto_enqueue_burst;\n \tcrypto_dev->feature_flags = MLX5_CRYPTO_FEATURE_FLAGS;\n \tcrypto_dev->driver_id = mlx5_crypto_driver_id;\n \tpriv = crypto_dev->data->dev_private;\n-\tpriv->ctx = ctx;\n+\tpriv->cdev = cdev;\n \tpriv->login_obj = login;\n \tpriv->crypto_dev = crypto_dev;\n \tpriv->qp_ts_format = attr.qp_ts_format;\n \tif (mlx5_crypto_hw_global_prepare(priv) != 0) {\n \t\trte_cryptodev_pmd_destroy(priv->crypto_dev);\n-\t\tclaim_zero(mlx5_glue->close_device(priv->ctx));\n \t\treturn -1;\n \t}\n \tif (mlx5_mr_btree_init(&priv->mr_scache.cache,\n@@ -1084,7 +1070,6 @@ mlx5_crypto_dev_probe(struct mlx5_common_device *cdev)\n \t\tDRV_LOG(ERR, \"Failed to allocate shared cache MR memory.\");\n \t\tmlx5_crypto_hw_global_release(priv);\n \t\trte_cryptodev_pmd_destroy(priv->crypto_dev);\n-\t\tclaim_zero(mlx5_glue->close_device(priv->ctx));\n \t\trte_errno = ENOMEM;\n \t\treturn -rte_errno;\n \t}\n@@ -1134,7 +1119,6 @@ mlx5_crypto_dev_remove(struct mlx5_common_device *cdev)\n \t\tmlx5_crypto_hw_global_release(priv);\n \t\trte_cryptodev_pmd_destroy(priv->crypto_dev);\n \t\tclaim_zero(mlx5_devx_cmd_destroy(priv->login_obj));\n-\t\tclaim_zero(mlx5_glue->close_device(priv->ctx));\n \t}\n \treturn 0;\n }\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h\nindex d589e0ac3d..238881c584 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.h\n+++ b/drivers/crypto/mlx5/mlx5_crypto.h\n@@ -19,7 +19,7 @@\n \n struct mlx5_crypto_priv {\n \tTAILQ_ENTRY(mlx5_crypto_priv) next;\n-\tstruct ibv_context *ctx; /* Device context. */\n+\tstruct mlx5_common_device *cdev; /* Backend mlx5 device. */\n \tstruct rte_cryptodev *crypto_dev;\n \tvoid *uar; /* User Access Region. */\n \tvolatile uint64_t *uar_addr;\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto_dek.c b/drivers/crypto/mlx5/mlx5_crypto_dek.c\nindex 67b1fa3819..94f21ec036 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto_dek.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto_dek.c\n@@ -117,7 +117,8 @@ mlx5_crypto_dek_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)\n \t\treturn NULL;\n \t}\n \tmemcpy(&dek_attr.key, cipher_ctx->key.data, cipher_ctx->key.length);\n-\tdek->obj = mlx5_devx_cmd_create_dek_obj(ctx->priv->ctx, &dek_attr);\n+\tdek->obj = mlx5_devx_cmd_create_dek_obj(ctx->priv->cdev->ctx,\n+\t\t\t\t\t\t&dek_attr);\n \tif (dek->obj == NULL) {\n \t\trte_free(dek);\n \t\treturn NULL;\ndiff --git a/drivers/net/mlx5/linux/mlx5_ethdev_os.c b/drivers/net/mlx5/linux/mlx5_ethdev_os.c\nindex f34133e2c6..471c3f1bdc 100644\n--- a/drivers/net/mlx5/linux/mlx5_ethdev_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_ethdev_os.c\n@@ -324,7 +324,7 @@ int\n mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct ibv_context *ctx = priv->sh->ctx;\n+\tstruct ibv_context *ctx = priv->sh->cdev->ctx;\n \tstruct ibv_values_ex values;\n \tint err = 0;\n \n@@ -778,7 +778,7 @@ mlx5_dev_interrupt_handler(void *cb_arg)\n \t\tstruct rte_eth_dev *dev;\n \t\tuint32_t tmp;\n \n-\t\tif (mlx5_glue->get_async_event(sh->ctx, &event))\n+\t\tif (mlx5_glue->get_async_event(sh->cdev->ctx, &event))\n \t\t\tbreak;\n \t\t/* Retrieve and check IB port index. */\n \t\ttmp = (uint32_t)event.element.port_num;\n@@ -990,7 +990,7 @@ mlx5_is_removed(struct rte_eth_dev *dev)\n \tstruct ibv_device_attr device_attr;\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \n-\tif (mlx5_glue->query_device(priv->sh->ctx, &device_attr) == EIO)\n+\tif (mlx5_glue->query_device(priv->sh->cdev->ctx, &device_attr) == EIO)\n \t\treturn 1;\n \treturn 0;\n }\ndiff --git a/drivers/net/mlx5/linux/mlx5_mp_os.c b/drivers/net/mlx5/linux/mlx5_mp_os.c\nindex b0996813dc..35b2dfd3b2 100644\n--- a/drivers/net/mlx5/linux/mlx5_mp_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_mp_os.c\n@@ -101,7 +101,7 @@ mlx5_mp_os_primary_handle(const struct rte_mp_msg *mp_msg, const void *peer)\n \tcase MLX5_MP_REQ_VERBS_CMD_FD:\n \t\tmp_init_msg(&priv->mp_id, &mp_res, param->type);\n \t\tmp_res.num_fds = 1;\n-\t\tmp_res.fds[0] = ((struct ibv_context *)priv->sh->ctx)->cmd_fd;\n+\t\tmp_res.fds[0] = ((struct ibv_context *)cdev->ctx)->cmd_fd;\n \t\tres->result = 0;\n \t\tret = rte_mp_reply(&mp_res, peer);\n \t\tbreak;\n@@ -248,7 +248,8 @@ mp_req_on_rxtx(struct rte_eth_dev *dev, enum mlx5_mp_req_type type)\n \tmp_init_msg(&priv->mp_id, &mp_req, type);\n \tif (type == MLX5_MP_REQ_START_RXTX) {\n \t\tmp_req.num_fds = 1;\n-\t\tmp_req.fds[0] = ((struct ibv_context *)priv->sh->ctx)->cmd_fd;\n+\t\tmp_req.fds[0] =\n+\t\t\t((struct ibv_context *)priv->sh->cdev->ctx)->cmd_fd;\n \t}\n \tret = rte_mp_request_sync(&mp_req, &mp_rep, &ts);\n \tif (ret) {\ndiff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 07ba0ff43b..6b02decaec 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -257,7 +257,7 @@ __mlx5_discovery_misc5_cap(struct mlx5_priv *priv)\n \t\t\t metadata_reg_c_0, 0xffff);\n \t}\n #endif\n-\tmatcher = mlx5_glue->dv_create_flow_matcher(priv->sh->ctx,\n+\tmatcher = mlx5_glue->dv_create_flow_matcher(priv->sh->cdev->ctx,\n \t\t\t\t\t\t &dv_attr, tbl);\n \tif (matcher) {\n \t\tpriv->sh->misc5_cap = 1;\n@@ -341,7 +341,7 @@ mlx5_alloc_shared_dr(struct mlx5_priv *priv)\n \tvoid *domain;\n \n \t/* Reference counter is zero, we should initialize structures. */\n-\tdomain = mlx5_glue->dr_create_domain(sh->ctx,\n+\tdomain = mlx5_glue->dr_create_domain(sh->cdev->ctx,\n \t\t\t\t\t MLX5DV_DR_DOMAIN_TYPE_NIC_RX);\n \tif (!domain) {\n \t\tDRV_LOG(ERR, \"ingress mlx5dv_dr_create_domain failed\");\n@@ -349,7 +349,7 @@ mlx5_alloc_shared_dr(struct mlx5_priv *priv)\n \t\tgoto error;\n \t}\n \tsh->rx_domain = domain;\n-\tdomain = mlx5_glue->dr_create_domain(sh->ctx,\n+\tdomain = mlx5_glue->dr_create_domain(sh->cdev->ctx,\n \t\t\t\t\t MLX5DV_DR_DOMAIN_TYPE_NIC_TX);\n \tif (!domain) {\n \t\tDRV_LOG(ERR, \"egress mlx5dv_dr_create_domain failed\");\n@@ -359,8 +359,8 @@ mlx5_alloc_shared_dr(struct mlx5_priv *priv)\n \tsh->tx_domain = domain;\n #ifdef HAVE_MLX5DV_DR_ESWITCH\n \tif (priv->config.dv_esw_en) {\n-\t\tdomain = mlx5_glue->dr_create_domain\n-\t\t\t(sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB);\n+\t\tdomain = mlx5_glue->dr_create_domain(sh->cdev->ctx,\n+\t\t\t\t\t\t MLX5DV_DR_DOMAIN_TYPE_FDB);\n \t\tif (!domain) {\n \t\t\tDRV_LOG(ERR, \"FDB mlx5dv_dr_create_domain failed\");\n \t\t\terr = errno;\n@@ -768,7 +768,7 @@ static void\n mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tvoid *ctx = priv->sh->ctx;\n+\tvoid *ctx = priv->sh->cdev->ctx;\n \n \tpriv->q_counters = mlx5_devx_cmd_queue_counter_alloc(ctx);\n \tif (!priv->q_counters) {\n@@ -1041,7 +1041,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT\n \tdv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;\n #endif\n-\tmlx5_glue->dv_query_device(sh->ctx, &dv_attr);\n+\tmlx5_glue->dv_query_device(sh->cdev->ctx, &dv_attr);\n \tif (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {\n \t\tif (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {\n \t\t\tDRV_LOG(DEBUG, \"enhanced MPW is supported\");\n@@ -1118,7 +1118,8 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n #endif\n \tconfig->mpls_en = mpls_en;\n \t/* Check port status. */\n-\terr = mlx5_glue->query_port(sh->ctx, spawn->phys_port, &port_attr);\n+\terr = mlx5_glue->query_port(sh->cdev->ctx, spawn->phys_port,\n+\t\t\t\t &port_attr);\n \tif (err) {\n \t\tDRV_LOG(ERR, \"port query failed: %s\", strerror(err));\n \t\tgoto error;\n@@ -1168,7 +1169,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t * register is defined by mask.\n \t */\n \tif (switch_info->representor || switch_info->master) {\n-\t\terr = mlx5_glue->devx_port_query(sh->ctx,\n+\t\terr = mlx5_glue->devx_port_query(sh->cdev->ctx,\n \t\t\t\t\t\t spawn->phys_port,\n \t\t\t\t\t\t &vport_info);\n \t\tif (err) {\n@@ -1325,7 +1326,8 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\tconfig->mps == MLX5_MPW ? \"legacy \" : \"\",\n \t\tconfig->mps != MLX5_MPW_DISABLED ? \"enabled\" : \"disabled\");\n \tif (sh->devx) {\n-\t\terr = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr);\n+\t\terr = mlx5_devx_cmd_query_hca_attr(sh->cdev->ctx,\n+\t\t\t\t\t\t &config->hca_attr);\n \t\tif (err) {\n \t\t\terr = -err;\n \t\t\tgoto error;\n@@ -1548,7 +1550,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \n \t\terr = config->hca_attr.access_register_user ?\n \t\t\tmlx5_devx_cmd_register_read\n-\t\t\t\t(sh->ctx, MLX5_REGISTER_ID_MTUTC, 0,\n+\t\t\t\t(sh->cdev->ctx, MLX5_REGISTER_ID_MTUTC, 0,\n \t\t\t\treg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP;\n \t\tif (!err) {\n \t\t\tuint32_t ts_mode;\n@@ -1914,14 +1916,14 @@ mlx5_dev_spawn_data_cmp(const void *a, const void *b)\n /**\n * Match PCI information for possible slaves of bonding device.\n *\n- * @param[in] ibv_dev\n- * Pointer to Infiniband device structure.\n+ * @param[in] ibdev_name\n+ * Name of Infiniband device.\n * @param[in] pci_dev\n * Pointer to primary PCI address structure to match.\n * @param[in] nl_rdma\n * Netlink RDMA group socket handle.\n * @param[in] owner\n- * Rerepsentor owner PF index.\n+ * Representor owner PF index.\n * @param[out] bond_info\n * Pointer to bonding information.\n *\n@@ -1930,7 +1932,7 @@ mlx5_dev_spawn_data_cmp(const void *a, const void *b)\n * positive index of slave PF in bonding.\n */\n static int\n-mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev,\n+mlx5_device_bond_pci_match(const char *ibdev_name,\n \t\t\t const struct rte_pci_addr *pci_dev,\n \t\t\t int nl_rdma, uint16_t owner,\n \t\t\t struct mlx5_bond_info *bond_info)\n@@ -1943,27 +1945,25 @@ mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev,\n \tint ret;\n \n \t/*\n-\t * Try to get master device name. If something goes\n-\t * wrong suppose the lack of kernel support and no\n-\t * bonding devices.\n+\t * Try to get master device name. If something goes wrong suppose\n+\t * the lack of kernel support and no bonding devices.\n \t */\n \tmemset(bond_info, 0, sizeof(*bond_info));\n \tif (nl_rdma < 0)\n \t\treturn -1;\n-\tif (!strstr(ibv_dev->name, \"bond\"))\n+\tif (!strstr(ibdev_name, \"bond\"))\n \t\treturn -1;\n-\tnp = mlx5_nl_portnum(nl_rdma, ibv_dev->name);\n+\tnp = mlx5_nl_portnum(nl_rdma, ibdev_name);\n \tif (!np)\n \t\treturn -1;\n \t/*\n-\t * The Master device might not be on the predefined\n-\t * port (not on port index 1, it is not garanted),\n-\t * we have to scan all Infiniband device port and\n-\t * find master.\n+\t * The master device might not be on the predefined port(not on port\n+\t * index 1, it is not guaranteed), we have to scan all Infiniband\n+\t * device ports and find master.\n \t */\n \tfor (i = 1; i <= np; ++i) {\n \t\t/* Check whether Infiniband port is populated. */\n-\t\tifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i);\n+\t\tifindex = mlx5_nl_ifindex(nl_rdma, ibdev_name, i);\n \t\tif (!ifindex)\n \t\t\tcontinue;\n \t\tif (!if_indextoname(ifindex, ifname))\n@@ -1988,8 +1988,9 @@ mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev,\n \t\tsnprintf(tmp_str, sizeof(tmp_str),\n \t\t\t \"/sys/class/net/%s\", ifname);\n \t\tif (mlx5_get_pci_addr(tmp_str, &pci_addr)) {\n-\t\t\tDRV_LOG(WARNING, \"can not get PCI address\"\n-\t\t\t\t\t \" for netdev \\\"%s\\\"\", ifname);\n+\t\t\tDRV_LOG(WARNING,\n+\t\t\t\t\"Cannot get PCI address for netdev \\\"%s\\\".\",\n+\t\t\t\tifname);\n \t\t\tcontinue;\n \t\t}\n \t\t/* Slave interface PCI address match found. */\n@@ -2090,7 +2091,7 @@ mlx5_os_config_default(struct mlx5_dev_config *config)\n * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n static int\n-mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, void *ctx,\n+mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev,\n \t\t struct rte_eth_devargs *req_eth_da,\n \t\t uint16_t owner_id)\n {\n@@ -2148,9 +2149,8 @@ mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, void *ctx,\n \t\tstruct rte_pci_addr pci_addr;\n \n \t\tDRV_LOG(DEBUG, \"Checking device \\\"%s\\\"\", ibv_list[ret]->name);\n-\t\tbd = mlx5_device_bond_pci_match\n-\t\t\t\t(ibv_list[ret], &owner_pci, nl_rdma, owner_id,\n-\t\t\t\t &bond_info);\n+\t\tbd = mlx5_device_bond_pci_match(ibv_list[ret]->name, &owner_pci,\n+\t\t\t\t\t\tnl_rdma, owner_id, &bond_info);\n \t\tif (bd >= 0) {\n \t\t\t/*\n \t\t\t * Bonding device detected. Only one match is allowed,\n@@ -2170,9 +2170,9 @@ mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, void *ctx,\n \t\t\t/* Amend owner pci address if owner PF ID specified. */\n \t\t\tif (eth_da.nb_representor_ports)\n \t\t\t\towner_pci.function += owner_id;\n-\t\t\tDRV_LOG(INFO, \"PCI information matches for\"\n-\t\t\t\t \" slave %d bonding device \\\"%s\\\"\",\n-\t\t\t\t bd, ibv_list[ret]->name);\n+\t\t\tDRV_LOG(INFO,\n+\t\t\t\t\"PCI information matches for slave %d bonding device \\\"%s\\\"\",\n+\t\t\t\tbd, ibv_list[ret]->name);\n \t\t\tibv_match[nd++] = ibv_list[ret];\n \t\t\tbreak;\n \t\t} else {\n@@ -2246,7 +2246,6 @@ mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, void *ctx,\n \t\t\tlist[ns].max_port = np;\n \t\t\tlist[ns].phys_port = i;\n \t\t\tlist[ns].phys_dev_name = ibv_match[0]->name;\n-\t\t\tlist[ns].ctx = ctx;\n \t\t\tlist[ns].eth_dev = NULL;\n \t\t\tlist[ns].pci_dev = pci_dev;\n \t\t\tlist[ns].cdev = cdev;\n@@ -2342,7 +2341,6 @@ mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, void *ctx,\n \t\t\tlist[ns].max_port = 1;\n \t\t\tlist[ns].phys_port = 1;\n \t\t\tlist[ns].phys_dev_name = ibv_match[i]->name;\n-\t\t\tlist[ns].ctx = ctx;\n \t\t\tlist[ns].eth_dev = NULL;\n \t\t\tlist[ns].pci_dev = pci_dev;\n \t\t\tlist[ns].cdev = cdev;\n@@ -2391,10 +2389,9 @@ mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, void *ctx,\n \t\t\t}\n \t\t\tret = -1;\n \t\t\tif (nl_route >= 0)\n-\t\t\t\tret = mlx5_nl_switch_info\n-\t\t\t\t\t (nl_route,\n-\t\t\t\t\t\tlist[ns].ifindex,\n-\t\t\t\t\t\t&list[ns].info);\n+\t\t\t\tret = mlx5_nl_switch_info(nl_route,\n+\t\t\t\t\t\t\t list[ns].ifindex,\n+\t\t\t\t\t\t\t &list[ns].info);\n \t\t\tif (ret || (!list[ns].info.representor &&\n \t\t\t\t !list[ns].info.master)) {\n \t\t\t\t/*\n@@ -2431,10 +2428,9 @@ mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, void *ctx,\n \t\t}\n \t\t/*\n \t\t * New kernels may add the switch_id attribute for the case\n-\t\t * there is no E-Switch and we wrongly recognized the\n-\t\t * only device as master. Override this if there is the\n-\t\t * single device with single port and new device name\n-\t\t * format present.\n+\t\t * there is no E-Switch and we wrongly recognized the only\n+\t\t * device as master. Override this if there is the single\n+\t\t * device with single port and new device name format present.\n \t\t */\n \t\tif (nd == 1 &&\n \t\t list[0].info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) {\n@@ -2607,7 +2603,7 @@ mlx5_os_parse_eth_devargs(struct rte_device *dev,\n * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n static int\n-mlx5_os_pci_probe(struct mlx5_common_device *cdev, void *ctx)\n+mlx5_os_pci_probe(struct mlx5_common_device *cdev)\n {\n \tstruct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev);\n \tstruct rte_eth_devargs eth_da = { .nb_ports = 0 };\n@@ -2621,7 +2617,7 @@ mlx5_os_pci_probe(struct mlx5_common_device *cdev, void *ctx)\n \tif (eth_da.nb_ports > 0) {\n \t\t/* Iterate all port if devargs pf is range: \"pf[0-1]vf[...]\". */\n \t\tfor (p = 0; p < eth_da.nb_ports; p++) {\n-\t\t\tret = mlx5_os_pci_probe_pf(cdev, ctx, ð_da,\n+\t\t\tret = mlx5_os_pci_probe_pf(cdev, ð_da,\n \t\t\t\t\t\t eth_da.ports[p]);\n \t\t\tif (ret)\n \t\t\t\tbreak;\n@@ -2635,14 +2631,14 @@ mlx5_os_pci_probe(struct mlx5_common_device *cdev, void *ctx)\n \t\t\tmlx5_net_remove(cdev);\n \t\t}\n \t} else {\n-\t\tret = mlx5_os_pci_probe_pf(cdev, ctx, ð_da, 0);\n+\t\tret = mlx5_os_pci_probe_pf(cdev, ð_da, 0);\n \t}\n \treturn ret;\n }\n \n /* Probe a single SF device on auxiliary bus, no representor support. */\n static int\n-mlx5_os_auxiliary_probe(struct mlx5_common_device *cdev, void *ctx)\n+mlx5_os_auxiliary_probe(struct mlx5_common_device *cdev)\n {\n \tstruct rte_eth_devargs eth_da = { .nb_ports = 0 };\n \tstruct mlx5_dev_config config;\n@@ -2662,8 +2658,7 @@ mlx5_os_auxiliary_probe(struct mlx5_common_device *cdev, void *ctx)\n \t/* Init spawn data. */\n \tspawn.max_port = 1;\n \tspawn.phys_port = 1;\n-\tspawn.ctx = ctx;\n-\tspawn.phys_dev_name = mlx5_os_get_ctx_device_name(ctx);\n+\tspawn.phys_dev_name = mlx5_os_get_ctx_device_name(cdev->ctx);\n \tret = mlx5_auxiliary_get_ifindex(dev->name);\n \tif (ret < 0) {\n \t\tDRV_LOG(ERR, \"failed to get ethdev ifindex: %s\", dev->name);\n@@ -2701,28 +2696,19 @@ int\n mlx5_os_net_probe(struct mlx5_common_device *cdev)\n {\n \tint ret;\n-\tvoid *ctx = NULL;\n \n-\tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n-\t\tret = mlx5_os_open_device(cdev, &ctx);\n-\t\tif (ret) {\n-\t\t\tDRV_LOG(ERR, \"Fail to open device %s\", cdev->dev->name);\n-\t\t\treturn -rte_errno;\n-\t\t}\n+\tif (rte_eal_process_type() == RTE_PROC_PRIMARY)\n \t\tmlx5_pmd_socket_init();\n-\t}\n \tret = mlx5_init_once();\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"Unable to init PMD global data: %s\",\n \t\t\tstrerror(rte_errno));\n-\t\tif (ctx != NULL)\n-\t\t\tclaim_zero(mlx5_glue->close_device(ctx));\n \t\treturn -rte_errno;\n \t}\n \tif (mlx5_dev_is_pci(cdev->dev))\n-\t\treturn mlx5_os_pci_probe(cdev, ctx);\n+\t\treturn mlx5_os_pci_probe(cdev);\n \telse\n-\t\treturn mlx5_os_auxiliary_probe(cdev, ctx);\n+\t\treturn mlx5_os_auxiliary_probe(cdev);\n }\n \n /**\n@@ -2773,16 +2759,16 @@ mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh)\n {\n \tint ret;\n \tint flags;\n+\tstruct ibv_context *ctx = sh->cdev->ctx;\n \n \tsh->intr_handle.fd = -1;\n-\tflags = fcntl(((struct ibv_context *)sh->ctx)->async_fd, F_GETFL);\n-\tret = fcntl(((struct ibv_context *)sh->ctx)->async_fd,\n-\t\t F_SETFL, flags | O_NONBLOCK);\n+\tflags = fcntl(ctx->async_fd, F_GETFL);\n+\tret = fcntl(ctx->async_fd, F_SETFL, flags | O_NONBLOCK);\n \tif (ret) {\n \t\tDRV_LOG(INFO, \"failed to change file descriptor async event\"\n \t\t\t\" queue\");\n \t} else {\n-\t\tsh->intr_handle.fd = ((struct ibv_context *)sh->ctx)->async_fd;\n+\t\tsh->intr_handle.fd = ctx->async_fd;\n \t\tsh->intr_handle.type = RTE_INTR_HANDLE_EXT;\n \t\tif (rte_intr_callback_register(&sh->intr_handle,\n \t\t\t\t\tmlx5_dev_interrupt_handler, sh)) {\n@@ -2793,8 +2779,7 @@ mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh)\n \tif (sh->devx) {\n #ifdef HAVE_IBV_DEVX_ASYNC\n \t\tsh->intr_handle_devx.fd = -1;\n-\t\tsh->devx_comp =\n-\t\t\t(void *)mlx5_glue->devx_create_cmd_comp(sh->ctx);\n+\t\tsh->devx_comp = (void *)mlx5_glue->devx_create_cmd_comp(ctx);\n \t\tstruct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp;\n \t\tif (!devx_comp) {\n \t\t\tDRV_LOG(INFO, \"failed to allocate devx_comp.\");\ndiff --git a/drivers/net/mlx5/linux/mlx5_verbs.c b/drivers/net/mlx5/linux/mlx5_verbs.c\nindex d4fa202ac4..981fc2ee7c 100644\n--- a/drivers/net/mlx5/linux/mlx5_verbs.c\n+++ b/drivers/net/mlx5/linux/mlx5_verbs.c\n@@ -249,9 +249,10 @@ mlx5_rxq_ibv_cq_create(struct rte_eth_dev *dev, uint16_t idx)\n \t\tcq_attr.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;\n \t}\n #endif\n-\treturn mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq(priv->sh->ctx,\n-\t\t\t\t\t\t\t &cq_attr.ibv,\n-\t\t\t\t\t\t\t &cq_attr.mlx5));\n+\treturn mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq\n+\t\t\t\t\t\t\t (priv->sh->cdev->ctx,\n+\t\t\t\t\t\t\t &cq_attr.ibv,\n+\t\t\t\t\t\t\t &cq_attr.mlx5));\n }\n \n /**\n@@ -323,10 +324,10 @@ mlx5_rxq_ibv_wq_create(struct rte_eth_dev *dev, uint16_t idx)\n \t\t\t.two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,\n \t\t};\n \t}\n-\trxq_obj->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &wq_attr.ibv,\n+\trxq_obj->wq = mlx5_glue->dv_create_wq(priv->sh->cdev->ctx, &wq_attr.ibv,\n \t\t\t\t\t &wq_attr.mlx5);\n #else\n-\trxq_obj->wq = mlx5_glue->create_wq(priv->sh->ctx, &wq_attr.ibv);\n+\trxq_obj->wq = mlx5_glue->create_wq(priv->sh->cdev->ctx, &wq_attr.ibv);\n #endif\n \tif (rxq_obj->wq) {\n \t\t/*\n@@ -379,7 +380,7 @@ mlx5_rxq_ibv_obj_new(struct rte_eth_dev *dev, uint16_t idx)\n \ttmpl->rxq_ctrl = rxq_ctrl;\n \tif (rxq_ctrl->irq) {\n \t\ttmpl->ibv_channel =\n-\t\t\t\tmlx5_glue->create_comp_channel(priv->sh->ctx);\n+\t\t\tmlx5_glue->create_comp_channel(priv->sh->cdev->ctx);\n \t\tif (!tmpl->ibv_channel) {\n \t\t\tDRV_LOG(ERR, \"Port %u: comp channel creation failure.\",\n \t\t\t\tdev->data->port_id);\n@@ -542,12 +543,13 @@ mlx5_ibv_ind_table_new(struct rte_eth_dev *dev, const unsigned int log_n,\n \t/* Finalise indirection table. */\n \tfor (j = 0; i != (unsigned int)(1 << log_n); ++j, ++i)\n \t\twq[i] = wq[j];\n-\tind_tbl->ind_table = mlx5_glue->create_rwq_ind_table(priv->sh->ctx,\n-\t\t\t\t\t&(struct ibv_rwq_ind_table_init_attr){\n-\t\t\t\t\t\t.log_ind_tbl_size = log_n,\n-\t\t\t\t\t\t.ind_tbl = wq,\n-\t\t\t\t\t\t.comp_mask = 0,\n-\t\t\t\t\t});\n+\tind_tbl->ind_table = mlx5_glue->create_rwq_ind_table\n+\t\t\t\t\t(priv->sh->cdev->ctx,\n+\t\t\t\t\t &(struct ibv_rwq_ind_table_init_attr){\n+\t\t\t\t\t\t .log_ind_tbl_size = log_n,\n+\t\t\t\t\t\t .ind_tbl = wq,\n+\t\t\t\t\t\t .comp_mask = 0,\n+\t\t\t\t\t });\n \tif (!ind_tbl->ind_table) {\n \t\trte_errno = errno;\n \t\treturn -rte_errno;\n@@ -609,7 +611,7 @@ mlx5_ibv_hrxq_new(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,\n \t}\n #endif\n \tqp = mlx5_glue->dv_create_qp\n-\t\t\t(priv->sh->ctx,\n+\t\t\t(priv->sh->cdev->ctx,\n \t\t\t &(struct ibv_qp_init_attr_ex){\n \t\t\t\t.qp_type = IBV_QPT_RAW_PACKET,\n \t\t\t\t.comp_mask =\n@@ -630,7 +632,7 @@ mlx5_ibv_hrxq_new(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,\n \t\t\t &qp_init_attr);\n #else\n \tqp = mlx5_glue->create_qp_ex\n-\t\t\t(priv->sh->ctx,\n+\t\t\t(priv->sh->cdev->ctx,\n \t\t\t &(struct ibv_qp_init_attr_ex){\n \t\t\t\t.qp_type = IBV_QPT_RAW_PACKET,\n \t\t\t\t.comp_mask =\n@@ -715,7 +717,7 @@ static int\n mlx5_rxq_ibv_obj_drop_create(struct rte_eth_dev *dev)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct ibv_context *ctx = priv->sh->ctx;\n+\tstruct ibv_context *ctx = priv->sh->cdev->ctx;\n \tstruct mlx5_rxq_obj *rxq = priv->drop_queue.rxq;\n \n \tif (rxq)\n@@ -779,7 +781,7 @@ mlx5_ibv_drop_action_create(struct rte_eth_dev *dev)\n \t\tgoto error;\n \trxq = priv->drop_queue.rxq;\n \tind_tbl = mlx5_glue->create_rwq_ind_table\n-\t\t\t\t(priv->sh->ctx,\n+\t\t\t\t(priv->sh->cdev->ctx,\n \t\t\t\t &(struct ibv_rwq_ind_table_init_attr){\n \t\t\t\t\t.log_ind_tbl_size = 0,\n \t\t\t\t\t.ind_tbl = (struct ibv_wq **)&rxq->wq,\n@@ -792,7 +794,7 @@ mlx5_ibv_drop_action_create(struct rte_eth_dev *dev)\n \t\trte_errno = errno;\n \t\tgoto error;\n \t}\n-\thrxq->qp = mlx5_glue->create_qp_ex(priv->sh->ctx,\n+\thrxq->qp = mlx5_glue->create_qp_ex(priv->sh->cdev->ctx,\n \t\t &(struct ibv_qp_init_attr_ex){\n \t\t\t.qp_type = IBV_QPT_RAW_PACKET,\n \t\t\t.comp_mask = IBV_QP_INIT_ATTR_PD |\n@@ -901,7 +903,7 @@ mlx5_txq_ibv_qp_create(struct rte_eth_dev *dev, uint16_t idx)\n \t\tqp_attr.max_tso_header = txq_ctrl->max_tso_header;\n \t\tqp_attr.comp_mask |= IBV_QP_INIT_ATTR_MAX_TSO_HEADER;\n \t}\n-\tqp_obj = mlx5_glue->create_qp_ex(priv->sh->ctx, &qp_attr);\n+\tqp_obj = mlx5_glue->create_qp_ex(priv->sh->cdev->ctx, &qp_attr);\n \tif (qp_obj == NULL) {\n \t\tDRV_LOG(ERR, \"Port %u Tx queue %u QP creation failure.\",\n \t\t\tdev->data->port_id, idx);\n@@ -947,7 +949,8 @@ mlx5_txq_ibv_obj_new(struct rte_eth_dev *dev, uint16_t idx)\n \t}\n \tcqe_n = desc / MLX5_TX_COMP_THRESH +\n \t\t1 + MLX5_TX_COMP_THRESH_INLINE_DIV;\n-\ttxq_obj->cq = mlx5_glue->create_cq(priv->sh->ctx, cqe_n, NULL, NULL, 0);\n+\ttxq_obj->cq = mlx5_glue->create_cq(priv->sh->cdev->ctx, cqe_n,\n+\t\t\t\t\t NULL, NULL, 0);\n \tif (txq_obj->cq == NULL) {\n \t\tDRV_LOG(ERR, \"Port %u Tx queue %u CQ creation failure.\",\n \t\t\tdev->data->port_id, idx);\n@@ -1070,7 +1073,7 @@ mlx5_rxq_ibv_obj_dummy_lb_create(struct rte_eth_dev *dev)\n #if defined(HAVE_IBV_DEVICE_TUNNEL_SUPPORT) && defined(HAVE_IBV_FLOW_DV_SUPPORT)\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_dev_ctx_shared *sh = priv->sh;\n-\tstruct ibv_context *ctx = sh->ctx;\n+\tstruct ibv_context *ctx = sh->cdev->ctx;\n \tstruct mlx5dv_qp_init_attr qp_init_attr = {0};\n \tstruct {\n \t\tstruct ibv_cq_init_attr_ex ibv;\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex bfdce8da72..6c50c43951 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -916,7 +916,7 @@ mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)\n \t * start after the common header that with the length of a DW(u32).\n \t */\n \tnode.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);\n-\tprf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);\n+\tprf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->cdev->ctx, &node);\n \tif (!prf->obj) {\n \t\tDRV_LOG(ERR, \"Failed to create flex parser node object.\");\n \t\treturn (rte_errno == 0) ? -ENODEV : -rte_errno;\n@@ -991,7 +991,8 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,\n \t\t */\n \t\tuar_mapping = 0;\n #endif\n-\t\tsh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);\n+\t\tsh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,\n+\t\t\t\t\t\t uar_mapping);\n #ifdef MLX5DV_UAR_ALLOC_TYPE_NC\n \t\tif (!sh->tx_uar &&\n \t\t uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {\n@@ -1009,8 +1010,8 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,\n \t\t\t */\n \t\t\tDRV_LOG(DEBUG, \"Failed to allocate Tx DevX UAR (BF)\");\n \t\t\tuar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;\n-\t\t\tsh->tx_uar = mlx5_glue->devx_alloc_uar\n-\t\t\t\t\t\t\t(sh->ctx, uar_mapping);\n+\t\t\tsh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,\n+\t\t\t\t\t\t\t uar_mapping);\n \t\t} else if (!sh->tx_uar &&\n \t\t\t uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {\n \t\t\tif (config->dbnc == MLX5_TXDB_NCACHED)\n@@ -1022,8 +1023,8 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,\n \t\t\t */\n \t\t\tDRV_LOG(DEBUG, \"Failed to allocate Tx DevX UAR (NC)\");\n \t\t\tuar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;\n-\t\t\tsh->tx_uar = mlx5_glue->devx_alloc_uar\n-\t\t\t\t\t\t\t(sh->ctx, uar_mapping);\n+\t\t\tsh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,\n+\t\t\t\t\t\t\t uar_mapping);\n \t\t}\n #endif\n \t\tif (!sh->tx_uar) {\n@@ -1050,8 +1051,8 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,\n \t}\n \tfor (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {\n \t\tuar_mapping = 0;\n-\t\tsh->devx_rx_uar = mlx5_glue->devx_alloc_uar\n-\t\t\t\t\t\t\t(sh->ctx, uar_mapping);\n+\t\tsh->devx_rx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,\n+\t\t\t\t\t\t\t uar_mapping);\n #ifdef MLX5DV_UAR_ALLOC_TYPE_NC\n \t\tif (!sh->devx_rx_uar &&\n \t\t uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {\n@@ -1063,7 +1064,7 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,\n \t\t\tDRV_LOG(DEBUG, \"Failed to allocate Rx DevX UAR (BF)\");\n \t\t\tuar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;\n \t\t\tsh->devx_rx_uar = mlx5_glue->devx_alloc_uar\n-\t\t\t\t\t\t\t(sh->ctx, uar_mapping);\n+\t\t\t\t\t\t (sh->cdev->ctx, uar_mapping);\n \t\t}\n #endif\n \t\tif (!sh->devx_rx_uar) {\n@@ -1248,7 +1249,7 @@ mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev)\n */\n struct mlx5_dev_ctx_shared *\n mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,\n-\t\t\t const struct mlx5_dev_config *config)\n+\t\t\t const struct mlx5_dev_config *config)\n {\n \tstruct mlx5_dev_ctx_shared *sh;\n \tint err = 0;\n@@ -1261,8 +1262,7 @@ mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,\n \tpthread_mutex_lock(&mlx5_dev_ctx_list_mutex);\n \t/* Search for IB context by device name. */\n \tLIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {\n-\t\tif (!strcmp(sh->ibdev_name,\n-\t\t\tmlx5_os_get_ctx_device_name(spawn->ctx))) {\n+\t\tif (!strcmp(sh->ibdev_name, spawn->phys_dev_name)) {\n \t\t\tsh->refcnt++;\n \t\t\tgoto exit;\n \t\t}\n@@ -1283,10 +1283,9 @@ mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,\n \tsh->numa_node = spawn->cdev->dev->numa_node;\n \tsh->cdev = spawn->cdev;\n \tsh->devx = sh->cdev->config.devx;\n-\tsh->ctx = spawn->ctx;\n \tif (spawn->bond_info)\n \t\tsh->bond = *spawn->bond_info;\n-\terr = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);\n+\terr = mlx5_os_get_dev_attr(sh->cdev->ctx, &sh->device_attr);\n \tif (err) {\n \t\tDRV_LOG(DEBUG, \"mlx5_os_get_dev_attr() failed\");\n \t\tgoto error;\n@@ -1294,9 +1293,9 @@ mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,\n \tsh->refcnt = 1;\n \tsh->max_port = spawn->max_port;\n \tsh->reclaim_mode = config->reclaim_mode;\n-\tstrncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),\n+\tstrncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->cdev->ctx),\n \t\tsizeof(sh->ibdev_name) - 1);\n-\tstrncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),\n+\tstrncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->cdev->ctx),\n \t\tsizeof(sh->ibdev_path) - 1);\n \t/*\n \t * Setting port_id to max unallowed value means\n@@ -1307,7 +1306,7 @@ mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,\n \t\tsh->port[i].ih_port_id = RTE_MAX_ETHPORTS;\n \t\tsh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;\n \t}\n-\tsh->pd = mlx5_os_alloc_pd(sh->ctx);\n+\tsh->pd = mlx5_os_alloc_pd(sh->cdev->ctx);\n \tif (sh->pd == NULL) {\n \t\tDRV_LOG(ERR, \"PD allocation failure\");\n \t\terr = ENOMEM;\n@@ -1319,14 +1318,14 @@ mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,\n \t\t\tDRV_LOG(ERR, \"Fail to extract pdn from PD\");\n \t\t\tgoto error;\n \t\t}\n-\t\tsh->td = mlx5_devx_cmd_create_td(sh->ctx);\n+\t\tsh->td = mlx5_devx_cmd_create_td(sh->cdev->ctx);\n \t\tif (!sh->td) {\n \t\t\tDRV_LOG(ERR, \"TD allocation failure\");\n \t\t\terr = ENOMEM;\n \t\t\tgoto error;\n \t\t}\n \t\ttis_attr.transport_domain = sh->td->id;\n-\t\tsh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);\n+\t\tsh->tis = mlx5_devx_cmd_create_tis(sh->cdev->ctx, &tis_attr);\n \t\tif (!sh->tis) {\n \t\t\tDRV_LOG(ERR, \"TIS allocation failure\");\n \t\t\terr = ENOMEM;\n@@ -1408,8 +1407,6 @@ mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,\n \t\tmlx5_glue->devx_free_uar(sh->tx_uar);\n \tif (sh->pd)\n \t\tclaim_zero(mlx5_os_dealloc_pd(sh->pd));\n-\tif (sh->ctx)\n-\t\tclaim_zero(mlx5_glue->close_device(sh->ctx));\n \tmlx5_free(sh);\n \tMLX5_ASSERT(err > 0);\n \trte_errno = err;\n@@ -1498,8 +1495,6 @@ mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)\n \t\tclaim_zero(mlx5_devx_cmd_destroy(sh->td));\n \tif (sh->devx_rx_uar)\n \t\tmlx5_glue->devx_free_uar(sh->devx_rx_uar);\n-\tif (sh->ctx)\n-\t\tclaim_zero(mlx5_glue->close_device(sh->ctx));\n \tMLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);\n \tpthread_mutex_destroy(&sh->txpp.mutex);\n \tmlx5_free(sh);\n@@ -1705,8 +1700,8 @@ mlx5_dev_close(struct rte_eth_dev *dev)\n \t\treturn 0;\n \tDRV_LOG(DEBUG, \"port %u closing device \\\"%s\\\"\",\n \t\tdev->data->port_id,\n-\t\t((priv->sh->ctx != NULL) ?\n-\t\tmlx5_os_get_ctx_device_name(priv->sh->ctx) : \"\"));\n+\t\t((priv->sh->cdev->ctx != NULL) ?\n+\t\tmlx5_os_get_ctx_device_name(priv->sh->cdev->ctx) : \"\"));\n \t/*\n \t * If default mreg copy action is removed at the stop stage,\n \t * the search will return none and nothing will be done anymore.\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex d2eabe04a5..2c92b2ce13 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -137,7 +137,6 @@ struct mlx5_dev_spawn_data {\n \tint pf_bond; /**< bonding device PF index. < 0 - no bonding */\n \tstruct mlx5_switch_info info; /**< Switch information. */\n \tconst char *phys_dev_name; /**< Name of physical device. */\n-\tvoid *ctx; /**< Associated physical device context. */\n \tstruct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */\n \tstruct rte_pci_device *pci_dev; /**< Backend PCI device. */\n \tstruct mlx5_common_device *cdev; /**< Backend common device. */\n@@ -1141,7 +1140,6 @@ struct mlx5_dev_ctx_shared {\n \tuint32_t max_port; /* Maximal IB device port index. */\n \tstruct mlx5_bond_info bond; /* Bonding information. */\n \tstruct mlx5_common_device *cdev; /* Backend mlx5 device. */\n-\tvoid *ctx; /* Verbs/DV/DevX context. */\n \tvoid *pd; /* Protection Domain. */\n \tuint32_t pdn; /* Protection Domain number. */\n \tuint32_t tdn; /* Transport Domain number. */\ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex a1db53577a..1fb835cb0d 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -279,7 +279,7 @@ mlx5_rxq_create_devx_rq_resources(struct rte_eth_dev *dev, uint16_t idx)\n \trq_attr.wq_attr.pd = priv->sh->pdn;\n \trq_attr.counter_set_id = priv->counter_set_id;\n \t/* Create RQ using DevX API. */\n-\treturn mlx5_devx_rq_create(priv->sh->ctx, &rxq_ctrl->obj->rq_obj,\n+\treturn mlx5_devx_rq_create(priv->sh->cdev->ctx, &rxq_ctrl->obj->rq_obj,\n \t\t\t\t wqe_size, log_desc_n, &rq_attr,\n \t\t\t\t rxq_ctrl->socket);\n }\n@@ -365,8 +365,8 @@ mlx5_rxq_create_devx_cq_resources(struct rte_eth_dev *dev, uint16_t idx)\n \tcq_attr.uar_page_id = mlx5_os_get_devx_uar_page_id(sh->devx_rx_uar);\n \tlog_cqe_n = log2above(cqe_n);\n \t/* Create CQ using DevX API. */\n-\tret = mlx5_devx_cq_create(sh->ctx, &rxq_ctrl->obj->cq_obj, log_cqe_n,\n-\t\t\t\t &cq_attr, sh->numa_node);\n+\tret = mlx5_devx_cq_create(sh->cdev->ctx, &rxq_ctrl->obj->cq_obj,\n+\t\t\t\t log_cqe_n, &cq_attr, sh->numa_node);\n \tif (ret)\n \t\treturn ret;\n \tcq_obj = &rxq_ctrl->obj->cq_obj;\n@@ -442,7 +442,7 @@ mlx5_rxq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)\n \t\t\tattr.wq_attr.log_hairpin_data_sz -\n \t\t\tMLX5_HAIRPIN_QUEUE_STRIDE;\n \tattr.counter_set_id = priv->counter_set_id;\n-\ttmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &attr,\n+\ttmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->cdev->ctx, &attr,\n \t\t\t\t\t rxq_ctrl->socket);\n \tif (!tmpl->rq) {\n \t\tDRV_LOG(ERR,\n@@ -486,8 +486,8 @@ mlx5_rxq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx)\n \t\t\t MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA;\n \n \t\ttmpl->devx_channel = mlx5_os_devx_create_event_channel\n-\t\t\t\t\t\t\t\t(priv->sh->ctx,\n-\t\t\t\t\t\t\t\t devx_ev_flag);\n+\t\t\t\t\t\t\t(priv->sh->cdev->ctx,\n+\t\t\t\t\t\t\t devx_ev_flag);\n \t\tif (!tmpl->devx_channel) {\n \t\t\trte_errno = errno;\n \t\t\tDRV_LOG(ERR, \"Failed to create event channel %d.\",\n@@ -602,7 +602,7 @@ mlx5_devx_ind_table_new(struct rte_eth_dev *dev, const unsigned int log_n,\n \t\t\t\t\t\t\tind_tbl->queues_n);\n \tif (!rqt_attr)\n \t\treturn -rte_errno;\n-\tind_tbl->rqt = mlx5_devx_cmd_create_rqt(priv->sh->ctx, rqt_attr);\n+\tind_tbl->rqt = mlx5_devx_cmd_create_rqt(priv->sh->cdev->ctx, rqt_attr);\n \tmlx5_free(rqt_attr);\n \tif (!ind_tbl->rqt) {\n \t\tDRV_LOG(ERR, \"Port %u cannot create DevX RQT.\",\n@@ -770,7 +770,7 @@ mlx5_devx_hrxq_new(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,\n \n \tmlx5_devx_tir_attr_set(dev, hrxq->rss_key, hrxq->hash_fields,\n \t\t\t hrxq->ind_table, tunnel, &tir_attr);\n-\thrxq->tir = mlx5_devx_cmd_create_tir(priv->sh->ctx, &tir_attr);\n+\thrxq->tir = mlx5_devx_cmd_create_tir(priv->sh->cdev->ctx, &tir_attr);\n \tif (!hrxq->tir) {\n \t\tDRV_LOG(ERR, \"Port %u cannot create DevX TIR.\",\n \t\t\tdev->data->port_id);\n@@ -936,7 +936,7 @@ mlx5_txq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)\n \t\t\tattr.wq_attr.log_hairpin_data_sz -\n \t\t\tMLX5_HAIRPIN_QUEUE_STRIDE;\n \tattr.tis_num = priv->sh->tis->id;\n-\ttmpl->sq = mlx5_devx_cmd_create_sq(priv->sh->ctx, &attr);\n+\ttmpl->sq = mlx5_devx_cmd_create_sq(priv->sh->cdev->ctx, &attr);\n \tif (!tmpl->sq) {\n \t\tDRV_LOG(ERR,\n \t\t\t\"Port %u tx hairpin queue %u can't create SQ object.\",\n@@ -1001,8 +1001,8 @@ mlx5_txq_create_devx_sq_resources(struct rte_eth_dev *dev, uint16_t idx,\n \t\t.ts_format = mlx5_ts_format_conv(priv->sh->sq_ts_format),\n \t};\n \t/* Create Send Queue object with DevX. */\n-\treturn mlx5_devx_sq_create(priv->sh->ctx, &txq_obj->sq_obj, log_desc_n,\n-\t\t\t\t &sq_attr, priv->sh->numa_node);\n+\treturn mlx5_devx_sq_create(priv->sh->cdev->ctx, &txq_obj->sq_obj,\n+\t\t\t\t log_desc_n, &sq_attr, priv->sh->numa_node);\n }\n #endif\n \n@@ -1058,7 +1058,7 @@ mlx5_txq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx)\n \t\treturn 0;\n \t}\n \t/* Create completion queue object with DevX. */\n-\tret = mlx5_devx_cq_create(sh->ctx, &txq_obj->cq_obj, log_desc_n,\n+\tret = mlx5_devx_cq_create(sh->cdev->ctx, &txq_obj->cq_obj, log_desc_n,\n \t\t\t\t &cq_attr, priv->sh->numa_node);\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"Port %u Tx queue %u CQ creation failure.\",\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex c914a7120c..abe8a0d7fe 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -7628,7 +7628,7 @@ mlx5_flow_create_counter_stat_mem_mng(struct mlx5_dev_ctx_shared *sh)\n \t}\n \tmem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;\n \tsize = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;\n-\tmem_mng->umem = mlx5_os_umem_reg(sh->ctx, mem, size,\n+\tmem_mng->umem = mlx5_os_umem_reg(sh->cdev->ctx, mem, size,\n \t\t\t\t\t\t IBV_ACCESS_LOCAL_WRITE);\n \tif (!mem_mng->umem) {\n \t\trte_errno = errno;\n@@ -7642,7 +7642,7 @@ mlx5_flow_create_counter_stat_mem_mng(struct mlx5_dev_ctx_shared *sh)\n \tmkey_attr.pd = sh->pdn;\n \tmkey_attr.relaxed_ordering_write = sh->cmng.relaxed_ordering_write;\n \tmkey_attr.relaxed_ordering_read = sh->cmng.relaxed_ordering_read;\n-\tmem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);\n+\tmem_mng->dm = mlx5_devx_cmd_mkey_create(sh->cdev->ctx, &mkey_attr);\n \tif (!mem_mng->dm) {\n \t\tmlx5_os_umem_dereg(mem_mng->umem);\n \t\trte_errno = errno;\ndiff --git a/drivers/net/mlx5/mlx5_flow_aso.c b/drivers/net/mlx5/mlx5_flow_aso.c\nindex e11327a11b..49eec7a6b6 100644\n--- a/drivers/net/mlx5/mlx5_flow_aso.c\n+++ b/drivers/net/mlx5/mlx5_flow_aso.c\n@@ -309,13 +309,14 @@ mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh,\n \t\t enum mlx5_access_aso_opc_mod aso_opc_mod)\n {\n \tuint32_t sq_desc_n = 1 << MLX5_ASO_QUEUE_LOG_DESC;\n+\tstruct mlx5_common_device *cdev = sh->cdev;\n \n \tswitch (aso_opc_mod) {\n \tcase ASO_OPC_MOD_FLOW_HIT:\n \t\tif (mlx5_aso_reg_mr(sh, (MLX5_ASO_AGE_ACTIONS_PER_POOL / 8) *\n \t\t\t\t sq_desc_n, &sh->aso_age_mng->aso_sq.mr, 0))\n \t\t\treturn -1;\n-\t\tif (mlx5_aso_sq_create(sh->ctx, &sh->aso_age_mng->aso_sq, 0,\n+\t\tif (mlx5_aso_sq_create(cdev->ctx, &sh->aso_age_mng->aso_sq, 0,\n \t\t\t\t sh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC,\n \t\t\t\t sh->sq_ts_format)) {\n \t\t\tmlx5_aso_dereg_mr(sh, &sh->aso_age_mng->aso_sq.mr);\n@@ -324,7 +325,7 @@ mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh,\n \t\tmlx5_aso_age_init_sq(&sh->aso_age_mng->aso_sq);\n \t\tbreak;\n \tcase ASO_OPC_MOD_POLICER:\n-\t\tif (mlx5_aso_sq_create(sh->ctx, &sh->mtrmng->pools_mng.sq, 0,\n+\t\tif (mlx5_aso_sq_create(cdev->ctx, &sh->mtrmng->pools_mng.sq, 0,\n \t\t\t\t sh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC,\n \t\t\t\t sh->sq_ts_format))\n \t\t\treturn -1;\n@@ -335,7 +336,7 @@ mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh,\n \t\tif (mlx5_aso_reg_mr(sh, 64 * sq_desc_n,\n \t\t\t\t &sh->ct_mng->aso_sq.mr, 0))\n \t\t\treturn -1;\n-\t\tif (mlx5_aso_sq_create(sh->ctx, &sh->ct_mng->aso_sq, 0,\n+\t\tif (mlx5_aso_sq_create(cdev->ctx, &sh->ct_mng->aso_sq, 0,\n \t\t\t\tsh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC,\n \t\t\t\tsh->sq_ts_format)) {\n \t\t\tmlx5_aso_dereg_mr(sh, &sh->ct_mng->aso_sq.mr);\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 0f3288df96..ac97cd717a 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -3678,8 +3678,8 @@ flow_dv_encap_decap_create_cb(void *tool_ctx, void *cb_ctx)\n \t}\n \t*resource = *ctx_resource;\n \tresource->idx = idx;\n-\tret = mlx5_flow_os_create_flow_action_packet_reformat(sh->ctx, domain,\n-\t\t\t\t\t\t\t resource,\n+\tret = mlx5_flow_os_create_flow_action_packet_reformat(sh->cdev->ctx,\n+\t\t\t\t\t\t\t domain, resource,\n \t\t\t\t\t\t\t &resource->action);\n \tif (ret) {\n \t\tmlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);\n@@ -5479,7 +5479,7 @@ flow_dv_modify_create_cb(void *tool_ctx, void *cb_ctx)\n \telse\n \t\tns = sh->rx_domain;\n \tret = mlx5_flow_os_create_flow_action_modify_header\n-\t\t\t\t\t(sh->ctx, ns, entry,\n+\t\t\t\t\t(sh->cdev->ctx, ns, entry,\n \t\t\t\t\t data_len, &entry->action);\n \tif (ret) {\n \t\tmlx5_ipool_free(sh->mdh_ipools[ref->actions_num - 1], idx);\n@@ -6101,7 +6101,7 @@ flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,\n \n \tif (fallback) {\n \t\t/* bulk_bitmap must be 0 for single counter allocation. */\n-\t\tdcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);\n+\t\tdcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0);\n \t\tif (!dcs)\n \t\t\treturn NULL;\n \t\tpool = flow_dv_find_pool_by_id(cmng, dcs->id);\n@@ -6119,7 +6119,7 @@ flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,\n \t\t*cnt_free = cnt;\n \t\treturn pool;\n \t}\n-\tdcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);\n+\tdcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0x4);\n \tif (!dcs) {\n \t\trte_errno = ENODATA;\n \t\treturn NULL;\n@@ -6479,7 +6479,7 @@ flow_dv_mtr_pool_create(struct rte_eth_dev *dev,\n \tuint32_t log_obj_size;\n \n \tlog_obj_size = rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1);\n-\tdcs = mlx5_devx_cmd_create_flow_meter_aso_obj(priv->sh->ctx,\n+\tdcs = mlx5_devx_cmd_create_flow_meter_aso_obj(priv->sh->cdev->ctx,\n \t\t\tpriv->sh->pdn, log_obj_size);\n \tif (!dcs) {\n \t\trte_errno = ENODATA;\n@@ -9175,7 +9175,7 @@ flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,\n \t\t}\n \t} else {\n \t\t/* Create a GENEVE TLV object and resource. */\n-\t\tobj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,\n+\t\tobj = mlx5_devx_cmd_create_geneve_tlv_option(sh->cdev->ctx,\n \t\t\t\tgeneve_opt_v->option_class,\n \t\t\t\tgeneve_opt_v->option_type,\n \t\t\t\tgeneve_opt_v->option_len);\n@@ -10535,7 +10535,8 @@ flow_dv_matcher_create_cb(void *tool_ctx, void *cb_ctx)\n \tdv_attr.priority = ref->priority;\n \tif (tbl->is_egress)\n \t\tdv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;\n-\tret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,\n+\tret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,\n+\t\t\t\t\t tbl->tbl.obj,\n \t\t\t\t\t &resource->matcher_object);\n \tif (ret) {\n \t\tmlx5_free(resource);\n@@ -11954,7 +11955,7 @@ flow_dv_age_pool_create(struct rte_eth_dev *dev,\n \tstruct mlx5_devx_obj *obj = NULL;\n \tuint32_t i;\n \n-\tobj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,\n+\tobj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->cdev->ctx,\n \t\t\t\t\t\t priv->sh->pdn);\n \tif (!obj) {\n \t\trte_errno = ENODATA;\n@@ -12382,7 +12383,7 @@ flow_dv_ct_pool_create(struct rte_eth_dev *dev,\n \tuint32_t i;\n \tuint32_t log_obj_size = rte_log2_u32(MLX5_ASO_CT_ACTIONS_PER_POOL);\n \n-\tobj = mlx5_devx_cmd_create_conn_track_offload_obj(priv->sh->ctx,\n+\tobj = mlx5_devx_cmd_create_conn_track_offload_obj(priv->sh->cdev->ctx,\n \t\t\t\t\t\tpriv->sh->pdn, log_obj_size);\n \tif (!obj) {\n \t\trte_errno = ENODATA;\n@@ -17188,8 +17189,8 @@ mlx5_flow_discover_dr_action_support(struct rte_eth_dev *dev)\n \t\tgoto err;\n \tdv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);\n \t__flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);\n-\tret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,\n-\t\t\t\t\t &matcher);\n+\tret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,\n+\t\t\t\t\t tbl->obj, &matcher);\n \tif (ret)\n \t\tgoto err;\n \t__flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);\n@@ -17257,7 +17258,7 @@ mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)\n \t\t\t\t\t0, 0, 0, NULL);\n \tif (!tbl)\n \t\tgoto err;\n-\tdcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);\n+\tdcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0x4);\n \tif (!dcs)\n \t\tgoto err;\n \tret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,\n@@ -17266,8 +17267,8 @@ mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)\n \t\tgoto err;\n \tdv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);\n \t__flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);\n-\tret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,\n-\t\t\t\t\t &matcher);\n+\tret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,\n+\t\t\t\t\t tbl->obj, &matcher);\n \tif (ret)\n \t\tgoto err;\n \t__flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);\ndiff --git a/drivers/net/mlx5/mlx5_flow_verbs.c b/drivers/net/mlx5/mlx5_flow_verbs.c\nindex b93fd4d2c9..2df63b6cac 100644\n--- a/drivers/net/mlx5/mlx5_flow_verbs.c\n+++ b/drivers/net/mlx5/mlx5_flow_verbs.c\n@@ -198,7 +198,7 @@ flow_verbs_counter_create(struct rte_eth_dev *dev,\n {\n #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42)\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct ibv_context *ctx = priv->sh->ctx;\n+\tstruct ibv_context *ctx = priv->sh->cdev->ctx;\n \tstruct ibv_counter_set_init_attr init = {\n \t\t\t .counter_set_id = counter->shared_info.id};\n \n@@ -210,7 +210,7 @@ flow_verbs_counter_create(struct rte_eth_dev *dev,\n \treturn 0;\n #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct ibv_context *ctx = priv->sh->ctx;\n+\tstruct ibv_context *ctx = priv->sh->cdev->ctx;\n \tstruct ibv_counters_init_attr init = {0};\n \tstruct ibv_counter_attach_attr attach;\n \tint ret;\ndiff --git a/drivers/net/mlx5/mlx5_txpp.c b/drivers/net/mlx5/mlx5_txpp.c\nindex 4f6da9f2d1..baf6015d89 100644\n--- a/drivers/net/mlx5/mlx5_txpp.c\n+++ b/drivers/net/mlx5/mlx5_txpp.c\n@@ -49,7 +49,7 @@ static int\n mlx5_txpp_create_event_channel(struct mlx5_dev_ctx_shared *sh)\n {\n \tMLX5_ASSERT(!sh->txpp.echan);\n-\tsh->txpp.echan = mlx5_os_devx_create_event_channel(sh->ctx,\n+\tsh->txpp.echan = mlx5_os_devx_create_event_channel(sh->cdev->ctx,\n \t\t\tMLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA);\n \tif (!sh->txpp.echan) {\n \t\trte_errno = errno;\n@@ -104,7 +104,7 @@ mlx5_txpp_alloc_pp_index(struct mlx5_dev_ctx_shared *sh)\n \tMLX5_SET(set_pp_rate_limit_context, &pp, rate_mode,\n \t\t sh->txpp.test ? MLX5_DATA_RATE : MLX5_WQE_RATE);\n \tsh->txpp.pp = mlx5_glue->dv_alloc_pp\n-\t\t\t\t(sh->ctx, sizeof(pp), &pp,\n+\t\t\t\t(sh->cdev->ctx, sizeof(pp), &pp,\n \t\t\t\t MLX5DV_PP_ALLOC_FLAGS_DEDICATED_INDEX);\n \tif (sh->txpp.pp == NULL) {\n \t\tDRV_LOG(ERR, \"Failed to allocate packet pacing index.\");\n@@ -245,7 +245,7 @@ mlx5_txpp_create_rearm_queue(struct mlx5_dev_ctx_shared *sh)\n \tint ret;\n \n \t/* Create completion queue object for Rearm Queue. */\n-\tret = mlx5_devx_cq_create(sh->ctx, &wq->cq_obj,\n+\tret = mlx5_devx_cq_create(sh->cdev->ctx, &wq->cq_obj,\n \t\t\t\t log2above(MLX5_TXPP_REARM_CQ_SIZE), &cq_attr,\n \t\t\t\t sh->numa_node);\n \tif (ret) {\n@@ -259,7 +259,7 @@ mlx5_txpp_create_rearm_queue(struct mlx5_dev_ctx_shared *sh)\n \t/* Create send queue object for Rearm Queue. */\n \tsq_attr.cqn = wq->cq_obj.cq->id;\n \t/* There should be no WQE leftovers in the cyclic queue. */\n-\tret = mlx5_devx_sq_create(sh->ctx, &wq->sq_obj,\n+\tret = mlx5_devx_sq_create(sh->cdev->ctx, &wq->sq_obj,\n \t\t\t\t log2above(MLX5_TXPP_REARM_SQ_SIZE), &sq_attr,\n \t\t\t\t sh->numa_node);\n \tif (ret) {\n@@ -409,7 +409,7 @@ mlx5_txpp_create_clock_queue(struct mlx5_dev_ctx_shared *sh)\n \tsh->txpp.ts_p = 0;\n \tsh->txpp.ts_n = 0;\n \t/* Create completion queue object for Clock Queue. */\n-\tret = mlx5_devx_cq_create(sh->ctx, &wq->cq_obj,\n+\tret = mlx5_devx_cq_create(sh->cdev->ctx, &wq->cq_obj,\n \t\t\t\t log2above(MLX5_TXPP_CLKQ_SIZE), &cq_attr,\n \t\t\t\t sh->numa_node);\n \tif (ret) {\n@@ -446,7 +446,8 @@ mlx5_txpp_create_clock_queue(struct mlx5_dev_ctx_shared *sh)\n \tsq_attr.wq_attr.uar_page = mlx5_os_get_devx_uar_page_id(sh->tx_uar);\n \tsq_attr.wq_attr.pd = sh->pdn;\n \tsq_attr.ts_format = mlx5_ts_format_conv(sh->sq_ts_format);\n-\tret = mlx5_devx_sq_create(sh->ctx, &wq->sq_obj, log2above(wq->sq_size),\n+\tret = mlx5_devx_sq_create(sh->cdev->ctx, &wq->sq_obj,\n+\t\t\t\t log2above(wq->sq_size),\n \t\t\t\t &sq_attr, sh->numa_node);\n \tif (ret) {\n \t\trte_errno = errno;\ndiff --git a/drivers/net/mlx5/windows/mlx5_ethdev_os.c b/drivers/net/mlx5/windows/mlx5_ethdev_os.c\nindex c709dd19be..fddc7a6b12 100644\n--- a/drivers/net/mlx5/windows/mlx5_ethdev_os.c\n+++ b/drivers/net/mlx5/windows/mlx5_ethdev_os.c\n@@ -38,7 +38,7 @@ mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN])\n \t\treturn -rte_errno;\n \t}\n \tpriv = dev->data->dev_private;\n-\tcontext_obj = (mlx5_context_st *)priv->sh->ctx;\n+\tcontext_obj = (mlx5_context_st *)priv->sh->cdev->ctx;\n \tmemcpy(mac, context_obj->mlx5_dev.eth_mac, RTE_ETHER_ADDR_LEN);\n \treturn 0;\n }\n@@ -66,7 +66,7 @@ mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[MLX5_NAMESIZE])\n \t\treturn -rte_errno;\n \t}\n \tpriv = dev->data->dev_private;\n-\tcontext_obj = (mlx5_context_st *)priv->sh->ctx;\n+\tcontext_obj = (mlx5_context_st *)priv->sh->cdev->ctx;\n \tstrncpy(*ifname, context_obj->mlx5_dev.name, MLX5_NAMESIZE);\n \treturn 0;\n }\n@@ -93,7 +93,7 @@ mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu)\n \t\treturn -rte_errno;\n \t}\n \tpriv = dev->data->dev_private;\n-\tcontext_obj = (mlx5_context_st *)priv->sh->ctx;\n+\tcontext_obj = (mlx5_context_st *)priv->sh->cdev->ctx;\n \t*mtu = context_obj->mlx5_dev.mtu_bytes;\n \treturn 0;\n }\n@@ -253,7 +253,7 @@ mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete)\n \t\treturn -rte_errno;\n \t}\n \tpriv = dev->data->dev_private;\n-\tcontext_obj = (mlx5_context_st *)priv->sh->ctx;\n+\tcontext_obj = (mlx5_context_st *)priv->sh->cdev->ctx;\n \tdev_link.link_speed = context_obj->mlx5_dev.link_speed / (1000 * 1000);\n \tdev_link.link_status =\n \t (context_obj->mlx5_dev.link_state == 1 && !mlx5_is_removed(dev))\n@@ -359,7 +359,7 @@ mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock)\n \tint err;\n \tstruct mlx5_devx_clock mlx5_clock;\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tmlx5_context_st *context_obj = (mlx5_context_st *)priv->sh->ctx;\n+\tmlx5_context_st *context_obj = (mlx5_context_st *)priv->sh->cdev->ctx;\n \n \terr = mlx5_glue->query_rt_values(context_obj, &mlx5_clock);\n \tif (err != 0) {\n@@ -383,7 +383,7 @@ int\n mlx5_is_removed(struct rte_eth_dev *dev)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tmlx5_context_st *context_obj = (mlx5_context_st *)priv->sh->ctx;\n+\tmlx5_context_st *context_obj = (mlx5_context_st *)priv->sh->cdev->ctx;\n \n \tif (*context_obj->shutdown_event_obj.p_flag)\n \t\treturn 1;\ndiff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c\nindex a882a18439..e1010beeb5 100644\n--- a/drivers/net/mlx5/windows/mlx5_os.c\n+++ b/drivers/net/mlx5/windows/mlx5_os.c\n@@ -352,14 +352,14 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t/* Initialize the shutdown event in mlx5_dev_spawn to\n \t * support mlx5_is_removed for Windows.\n \t */\n-\terr = mlx5_glue->devx_init_showdown_event(sh->ctx);\n+\terr = mlx5_glue->devx_init_showdown_event(sh->cdev->ctx);\n \tif (err) {\n \t\tDRV_LOG(ERR, \"failed to init showdown event: %s\",\n \t\t\tstrerror(errno));\n \t\tgoto error;\n \t}\n \tDRV_LOG(DEBUG, \"MPW isn't supported\");\n-\tmlx5_os_get_dev_attr(sh->ctx, &device_attr);\n+\tmlx5_os_get_dev_attr(sh->cdev->ctx, &device_attr);\n \tconfig->swp = 0;\n \tconfig->ind_table_max_size =\n \t\tsh->device_attr.max_rwq_indirection_table_size;\n@@ -452,7 +452,8 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\tconfig->cqe_comp = 0;\n \t}\n \tif (sh->devx) {\n-\t\terr = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr);\n+\t\terr = mlx5_devx_cmd_query_hca_attr(sh->cdev->ctx,\n+\t\t\t\t\t\t &config->hca_attr);\n \t\tif (err) {\n \t\t\terr = -err;\n \t\t\tgoto error;\n@@ -475,7 +476,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \n \t\terr = config->hca_attr.access_register_user ?\n \t\t\tmlx5_devx_cmd_register_read\n-\t\t\t\t(sh->ctx, MLX5_REGISTER_ID_MTUTC, 0,\n+\t\t\t\t(sh->cdev->ctx, MLX5_REGISTER_ID_MTUTC, 0,\n \t\t\t\treg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP;\n \t\tif (!err) {\n \t\t\tuint32_t ts_mode;\n@@ -887,6 +888,7 @@ mlx5_os_net_probe(struct mlx5_common_device *cdev)\n \t\t.pf_bond = -1,\n \t\t.max_port = 1,\n \t\t.phys_port = 1,\n+\t\t.phys_dev_name = mlx5_os_get_ctx_device_name(cdev->ctx),\n \t\t.pci_dev = pci_dev,\n \t\t.cdev = cdev,\n \t\t.ifindex = -1, /* Spawn will assign */\n@@ -907,7 +909,6 @@ mlx5_os_net_probe(struct mlx5_common_device *cdev)\n \t\t.dv_flow_en = 1,\n \t\t.log_hp_size = MLX5_ARG_UNSET,\n \t};\n-\tvoid *ctx;\n \tint ret;\n \tuint32_t restore;\n \n@@ -915,20 +916,12 @@ mlx5_os_net_probe(struct mlx5_common_device *cdev)\n \t\tDRV_LOG(ERR, \"Secondary process is not supported on Windows.\");\n \t\treturn -ENOTSUP;\n \t}\n-\tret = mlx5_os_open_device(cdev, &ctx);\n-\tif (ret) {\n-\t\tDRV_LOG(ERR, \"Fail to open DevX device %s\", cdev->dev->name);\n-\t\treturn -rte_errno;\n-\t}\n \tret = mlx5_init_once();\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"unable to init PMD global data: %s\",\n \t\t\tstrerror(rte_errno));\n-\t\tclaim_zero(mlx5_glue->close_device(ctx));\n \t\treturn -rte_errno;\n \t}\n-\tspawn.ctx = ctx;\n-\tspawn.phys_dev_name = mlx5_os_get_ctx_device_name(ctx);\n \t/* Device specific configuration. */\n \tswitch (pci_dev->id.device_id) {\n \tcase PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:\n@@ -945,10 +938,8 @@ mlx5_os_net_probe(struct mlx5_common_device *cdev)\n \t\tbreak;\n \t}\n \tspawn.eth_dev = mlx5_dev_spawn(cdev->dev, &spawn, &dev_config);\n-\tif (!spawn.eth_dev) {\n-\t\tclaim_zero(mlx5_glue->close_device(ctx));\n+\tif (!spawn.eth_dev)\n \t\treturn -rte_errno;\n-\t}\n \trestore = spawn.eth_dev->data->dev_flags;\n \trte_eth_copy_pci_info(spawn.eth_dev, pci_dev);\n \t/* Restore non-PCI flags cleared by the above call. */\ndiff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c\nindex 5e27645c84..6474d3f73f 100644\n--- a/drivers/regex/mlx5/mlx5_regex.c\n+++ b/drivers/regex/mlx5/mlx5_regex.c\n@@ -110,7 +110,8 @@ mlx5_regex_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr,\n \t\t/* Iterate all the existing mlx5 devices. */\n \t\tTAILQ_FOREACH(priv, &mlx5_mem_event_list, mem_event_cb)\n \t\t\tmlx5_free_mr_by_addr(&priv->mr_scache,\n-\t\t\t\t\t priv->ctx->device->name,\n+\t\t\t\t\t mlx5_os_get_ctx_device_name\n+\t\t\t\t\t\t\t (priv->cdev->ctx),\n \t\t\t\t\t addr, len);\n \t\tpthread_mutex_unlock(&mem_event_list_lock);\n \t\tbreak;\n@@ -123,51 +124,39 @@ mlx5_regex_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr,\n static int\n mlx5_regex_dev_probe(struct mlx5_common_device *cdev)\n {\n-\tstruct ibv_device *ibv;\n \tstruct mlx5_regex_priv *priv = NULL;\n-\tstruct ibv_context *ctx = NULL;\n \tstruct mlx5_hca_attr attr;\n \tchar name[RTE_REGEXDEV_NAME_MAX_LEN];\n \tint ret;\n \tuint32_t val;\n \n-\tibv = mlx5_os_get_ibv_dev(cdev->dev);\n-\tif (ibv == NULL)\n-\t\treturn -rte_errno;\n-\tDRV_LOG(INFO, \"Probe device \\\"%s\\\".\", ibv->name);\n-\tctx = mlx5_glue->dv_open_device(ibv);\n-\tif (!ctx) {\n-\t\tDRV_LOG(ERR, \"Failed to open IB device \\\"%s\\\".\", ibv->name);\n-\t\trte_errno = ENODEV;\n-\t\treturn -rte_errno;\n-\t}\n-\tret = mlx5_devx_cmd_query_hca_attr(ctx, &attr);\n+\tret = mlx5_devx_cmd_query_hca_attr(cdev->ctx, &attr);\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"Unable to read HCA capabilities.\");\n \t\trte_errno = ENOTSUP;\n-\t\tgoto dev_error;\n+\t\treturn -rte_errno;\n \t} else if (!attr.regex || attr.regexp_num_of_engines == 0) {\n \t\tDRV_LOG(ERR, \"Not enough capabilities to support RegEx, maybe \"\n \t\t\t\"old FW/OFED version?\");\n \t\trte_errno = ENOTSUP;\n-\t\tgoto dev_error;\n+\t\treturn -rte_errno;\n \t}\n-\tif (mlx5_regex_engines_status(ctx, 2)) {\n+\tif (mlx5_regex_engines_status(cdev->ctx, 2)) {\n \t\tDRV_LOG(ERR, \"RegEx engine error.\");\n \t\trte_errno = ENOMEM;\n-\t\tgoto dev_error;\n+\t\treturn -rte_errno;\n \t}\n \tpriv = rte_zmalloc(\"mlx5 regex device private\", sizeof(*priv),\n \t\t\t RTE_CACHE_LINE_SIZE);\n \tif (!priv) {\n \t\tDRV_LOG(ERR, \"Failed to allocate private memory.\");\n \t\trte_errno = ENOMEM;\n-\t\tgoto dev_error;\n+\t\treturn -rte_errno;\n \t}\n \tpriv->sq_ts_format = attr.sq_ts_format;\n-\tpriv->ctx = ctx;\n+\tpriv->cdev = cdev;\n \tpriv->nb_engines = 2; /* attr.regexp_num_of_engines */\n-\tret = mlx5_devx_regex_register_read(priv->ctx, 0,\n+\tret = mlx5_devx_regex_register_read(priv->cdev->ctx, 0,\n \t\t\t\t\t MLX5_RXP_CSR_IDENTIFIER, &val);\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"CSR read failed!\");\n@@ -182,20 +171,20 @@ mlx5_regex_dev_probe(struct mlx5_common_device *cdev)\n \tif (priv->regexdev == NULL) {\n \t\tDRV_LOG(ERR, \"Failed to register RegEx device.\");\n \t\trte_errno = rte_errno ? rte_errno : EINVAL;\n-\t\tgoto error;\n+\t\tgoto dev_error;\n \t}\n \t/*\n \t * This PMD always claims the write memory barrier on UAR\n \t * registers writings, it is safe to allocate UAR with any\n \t * memory mapping type.\n \t */\n-\tpriv->uar = mlx5_devx_alloc_uar(ctx, -1);\n+\tpriv->uar = mlx5_devx_alloc_uar(priv->cdev->ctx, -1);\n \tif (!priv->uar) {\n \t\tDRV_LOG(ERR, \"can't allocate uar.\");\n \t\trte_errno = ENOMEM;\n \t\tgoto error;\n \t}\n-\tpriv->pd = mlx5_glue->alloc_pd(ctx);\n+\tpriv->pd = mlx5_glue->alloc_pd(priv->cdev->ctx);\n \tif (!priv->pd) {\n \t\tDRV_LOG(ERR, \"can't allocate pd.\");\n \t\trte_errno = ENOMEM;\n@@ -245,8 +234,6 @@ mlx5_regex_dev_probe(struct mlx5_common_device *cdev)\n \tif (priv->regexdev)\n \t\trte_regexdev_unregister(priv->regexdev);\n dev_error:\n-\tif (ctx)\n-\t\tmlx5_glue->close_device(ctx);\n \tif (priv)\n \t\trte_free(priv);\n \treturn -rte_errno;\n@@ -280,8 +267,6 @@ mlx5_regex_dev_remove(struct mlx5_common_device *cdev)\n \t\t\tmlx5_glue->devx_free_uar(priv->uar);\n \t\tif (priv->regexdev)\n \t\t\trte_regexdev_unregister(priv->regexdev);\n-\t\tif (priv->ctx)\n-\t\t\tmlx5_glue->close_device(priv->ctx);\n \t\trte_free(priv);\n \t}\n \treturn 0;\ndiff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h\nindex 514f3408f9..a9a010c437 100644\n--- a/drivers/regex/mlx5/mlx5_regex.h\n+++ b/drivers/regex/mlx5/mlx5_regex.h\n@@ -58,7 +58,7 @@ struct mlx5_regex_db {\n \n struct mlx5_regex_priv {\n \tTAILQ_ENTRY(mlx5_regex_priv) next;\n-\tstruct ibv_context *ctx; /* Device context. */\n+\tstruct mlx5_common_device *cdev; /* Backend mlx5 device. */\n \tstruct rte_regexdev *regexdev; /* Pointer to the RegEx dev. */\n \tuint16_t nb_queues; /* Number of queues. */\n \tstruct mlx5_regex_qp *qps; /* Pointer to the qp array. */\ndiff --git a/drivers/regex/mlx5/mlx5_regex_control.c b/drivers/regex/mlx5/mlx5_regex_control.c\nindex 8ce2dabb55..1580a51ccb 100644\n--- a/drivers/regex/mlx5/mlx5_regex_control.c\n+++ b/drivers/regex/mlx5/mlx5_regex_control.c\n@@ -83,7 +83,7 @@ regex_ctrl_create_cq(struct mlx5_regex_priv *priv, struct mlx5_regex_cq *cq)\n \tint ret;\n \n \tcq->ci = 0;\n-\tret = mlx5_devx_cq_create(priv->ctx, &cq->cq_obj, cq->log_nb_desc,\n+\tret = mlx5_devx_cq_create(priv->cdev->ctx, &cq->cq_obj, cq->log_nb_desc,\n \t\t\t\t &attr, SOCKET_ID_ANY);\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"Can't create CQ object.\");\n@@ -158,7 +158,7 @@ regex_ctrl_create_sq(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp,\n \tif (ret)\n \t\treturn ret;\n \tattr.wq_attr.pd = pd_num;\n-\tret = mlx5_devx_sq_create(priv->ctx, &sq->sq_obj,\n+\tret = mlx5_devx_sq_create(priv->cdev->ctx, &sq->sq_obj,\n \t\t\tMLX5_REGEX_WQE_LOG_NUM(priv->has_umr, log_nb_desc),\n \t\t\t&attr, SOCKET_ID_ANY);\n \tif (ret) {\ndiff --git a/drivers/regex/mlx5/mlx5_regex_fastpath.c b/drivers/regex/mlx5/mlx5_regex_fastpath.c\nindex c79445ce7d..7b3e209714 100644\n--- a/drivers/regex/mlx5/mlx5_regex_fastpath.c\n+++ b/drivers/regex/mlx5/mlx5_regex_fastpath.c\n@@ -752,8 +752,8 @@ mlx5_regexdev_setup_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id)\n \t\tfor (i = 0; i < qp->nb_desc; i++) {\n \t\t\tattr.klm_num = MLX5_REGEX_MAX_KLM_NUM;\n \t\t\tattr.klm_array = qp->jobs[i].imkey_array;\n-\t\t\tqp->jobs[i].imkey = mlx5_devx_cmd_mkey_create(priv->ctx,\n-\t\t\t\t\t\t\t\t &attr);\n+\t\t\tqp->jobs[i].imkey = mlx5_devx_cmd_mkey_create\n+\t\t\t\t\t\t (priv->cdev->ctx, &attr);\n \t\t\tif (!qp->jobs[i].imkey) {\n \t\t\t\terr = -rte_errno;\n \t\t\t\tDRV_LOG(ERR, \"Failed to allocate imkey.\");\ndiff --git a/drivers/regex/mlx5/mlx5_rxp.c b/drivers/regex/mlx5/mlx5_rxp.c\nindex 380037e24c..d9655bcdb7 100644\n--- a/drivers/regex/mlx5/mlx5_rxp.c\n+++ b/drivers/regex/mlx5/mlx5_rxp.c\n@@ -167,7 +167,7 @@ rxp_init_rtru(struct mlx5_regex_priv *priv, uint8_t id, uint32_t init_bits)\n \tuint32_t poll_value;\n \tuint32_t expected_value;\n \tuint32_t expected_mask;\n-\tstruct ibv_context *ctx = priv->ctx;\n+\tstruct ibv_context *ctx = priv->cdev->ctx;\n \tint ret = 0;\n \n \t/* Read the rtru ctrl CSR. */\n@@ -313,7 +313,7 @@ rxp_program_rof(struct mlx5_regex_priv *priv, const char *buf, uint32_t len,\n \t\t\ttmp_addr = rxp_get_reg_address(address);\n \t\t\tif (tmp_addr == UINT32_MAX)\n \t\t\t\tgoto parse_error;\n-\t\t\tret = mlx5_devx_regex_register_read(priv->ctx, id,\n+\t\t\tret = mlx5_devx_regex_register_read(priv->cdev->ctx, id,\n \t\t\t\t\t\t\t tmp_addr, ®_val);\n \t\t\tif (ret)\n \t\t\t\tgoto parse_error;\n@@ -337,7 +337,7 @@ rxp_program_rof(struct mlx5_regex_priv *priv, const char *buf, uint32_t len,\n \t\t\ttmp_addr = rxp_get_reg_address(address);\n \t\t\tif (tmp_addr == UINT32_MAX)\n \t\t\t\tgoto parse_error;\n-\t\t\tret = mlx5_devx_regex_register_read(priv->ctx, id,\n+\t\t\tret = mlx5_devx_regex_register_read(priv->cdev->ctx, id,\n \t\t\t\t\t\t\t tmp_addr, ®_val);\n \t\t\tif (ret)\n \t\t\t\tgoto parse_error;\n@@ -359,7 +359,7 @@ rxp_program_rof(struct mlx5_regex_priv *priv, const char *buf, uint32_t len,\n \t\t\ttmp_addr = rxp_get_reg_address(address);\n \t\t\tif (tmp_addr == UINT32_MAX)\n \t\t\t\tgoto parse_error;\n-\t\t\tret = mlx5_devx_regex_register_read(priv->ctx, id,\n+\t\t\tret = mlx5_devx_regex_register_read(priv->cdev->ctx, id,\n \t\t\t\t\t\t\t tmp_addr, ®_val);\n \t\t\tif (ret)\n \t\t\t\tgoto parse_error;\n@@ -395,7 +395,7 @@ rxp_program_rof(struct mlx5_regex_priv *priv, const char *buf, uint32_t len,\n \t\t\tif (tmp_addr == UINT32_MAX)\n \t\t\t\tgoto parse_error;\n \n-\t\t\tret = mlx5_devx_regex_register_read(priv->ctx, id,\n+\t\t\tret = mlx5_devx_regex_register_read(priv->cdev->ctx, id,\n \t\t\t\t\t\t\t tmp_addr, ®_val);\n \t\t\tif (ret) {\n \t\t\t\tDRV_LOG(ERR, \"RXP CSR read failed!\");\n@@ -418,17 +418,17 @@ rxp_program_rof(struct mlx5_regex_priv *priv, const char *buf, uint32_t len,\n \t\t\t */\n \t\t\ttemp = val;\n \t\t\tret |= mlx5_devx_regex_register_write\n-\t\t\t\t\t(priv->ctx, id,\n+\t\t\t\t\t(priv->cdev->ctx, id,\n \t\t\t\t\t MLX5_RXP_RTRU_CSR_DATA_0, temp);\n \t\t\ttemp = (uint32_t)(val >> 32);\n \t\t\tret |= mlx5_devx_regex_register_write\n-\t\t\t\t\t(priv->ctx, id,\n+\t\t\t\t\t(priv->cdev->ctx, id,\n \t\t\t\t\t MLX5_RXP_RTRU_CSR_DATA_0 +\n \t\t\t\t\t MLX5_RXP_CSR_WIDTH, temp);\n \t\t\ttemp = address;\n \t\t\tret |= mlx5_devx_regex_register_write\n-\t\t\t\t\t(priv->ctx, id, MLX5_RXP_RTRU_CSR_ADDR,\n-\t\t\t\t\t temp);\n+\t\t\t\t\t(priv->cdev->ctx, id,\n+\t\t\t\t\t MLX5_RXP_RTRU_CSR_ADDR, temp);\n \t\t\tif (ret) {\n \t\t\t\tDRV_LOG(ERR,\n \t\t\t\t\t\"Failed to copy instructions to RXP.\");\n@@ -506,13 +506,13 @@ mlnx_set_database(struct mlx5_regex_priv *priv, uint8_t id, uint8_t db_to_use)\n \tint ret;\n \tuint32_t umem_id;\n \n-\tret = mlx5_devx_regex_database_stop(priv->ctx, id);\n+\tret = mlx5_devx_regex_database_stop(priv->cdev->ctx, id);\n \tif (ret < 0) {\n \t\tDRV_LOG(ERR, \"stop engine failed!\");\n \t\treturn ret;\n \t}\n \tumem_id = mlx5_os_get_umem_id(priv->db[db_to_use].umem.umem);\n-\tret = mlx5_devx_regex_database_program(priv->ctx, id, umem_id, 0);\n+\tret = mlx5_devx_regex_database_program(priv->cdev->ctx, id, umem_id, 0);\n \tif (ret < 0) {\n \t\tDRV_LOG(ERR, \"program db failed!\");\n \t\treturn ret;\n@@ -523,7 +523,7 @@ mlnx_set_database(struct mlx5_regex_priv *priv, uint8_t id, uint8_t db_to_use)\n static int\n mlnx_resume_database(struct mlx5_regex_priv *priv, uint8_t id)\n {\n-\tmlx5_devx_regex_database_resume(priv->ctx, id);\n+\tmlx5_devx_regex_database_resume(priv->cdev->ctx, id);\n \treturn 0;\n }\n \n@@ -588,13 +588,13 @@ program_rxp_rules(struct mlx5_regex_priv *priv, const char *buf, uint32_t len,\n {\n \tint ret;\n \tuint32_t val;\n+\tstruct ibv_context *ctx = priv->cdev->ctx;\n \n \tret = rxp_init_eng(priv, id);\n \tif (ret < 0)\n \t\treturn ret;\n \t/* Confirm the RXP is initialised. */\n-\tif (mlx5_devx_regex_register_read(priv->ctx, id,\n-\t\t\t\t\t MLX5_RXP_CSR_STATUS, &val)) {\n+\tif (mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_STATUS, &val)) {\n \t\tDRV_LOG(ERR, \"Failed to read from RXP!\");\n \t\treturn -ENODEV;\n \t}\n@@ -602,14 +602,14 @@ program_rxp_rules(struct mlx5_regex_priv *priv, const char *buf, uint32_t len,\n \t\tDRV_LOG(ERR, \"RXP not initialised...\");\n \t\treturn -EBUSY;\n \t}\n-\tret = mlx5_devx_regex_register_read(priv->ctx, id,\n+\tret = mlx5_devx_regex_register_read(ctx, id,\n \t\t\t\t\t MLX5_RXP_RTRU_CSR_CTRL, &val);\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"CSR read failed!\");\n \t\treturn -1;\n \t}\n \tval |= MLX5_RXP_RTRU_CSR_CTRL_GO;\n-\tret = mlx5_devx_regex_register_write(priv->ctx, id,\n+\tret = mlx5_devx_regex_register_write(ctx, id,\n \t\t\t\t\t MLX5_RXP_RTRU_CSR_CTRL, val);\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"Can't program rof file!\");\n@@ -622,7 +622,7 @@ program_rxp_rules(struct mlx5_regex_priv *priv, const char *buf, uint32_t len,\n \t}\n \tif (priv->is_bf2) {\n \t\tret = rxp_poll_csr_for_value\n-\t\t\t(priv->ctx, &val, MLX5_RXP_RTRU_CSR_STATUS,\n+\t\t\t(ctx, &val, MLX5_RXP_RTRU_CSR_STATUS,\n \t\t\t MLX5_RXP_RTRU_CSR_STATUS_UPDATE_DONE,\n \t\t\t MLX5_RXP_RTRU_CSR_STATUS_UPDATE_DONE,\n \t\t\t MLX5_RXP_POLL_CSR_FOR_VALUE_TIMEOUT, id);\n@@ -632,30 +632,27 @@ program_rxp_rules(struct mlx5_regex_priv *priv, const char *buf, uint32_t len,\n \t\t}\n \t\tDRV_LOG(DEBUG, \"Rules update took %d cycles\", ret);\n \t}\n-\tif (mlx5_devx_regex_register_read(priv->ctx, id, MLX5_RXP_RTRU_CSR_CTRL,\n+\tif (mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,\n \t\t\t\t\t &val)) {\n \t\tDRV_LOG(ERR, \"CSR read failed!\");\n \t\treturn -1;\n \t}\n \tval &= ~(MLX5_RXP_RTRU_CSR_CTRL_GO);\n-\tif (mlx5_devx_regex_register_write(priv->ctx, id,\n+\tif (mlx5_devx_regex_register_write(ctx, id,\n \t\t\t\t\t MLX5_RXP_RTRU_CSR_CTRL, val)) {\n \t\tDRV_LOG(ERR, \"CSR write failed!\");\n \t\treturn -1;\n \t}\n-\tret = mlx5_devx_regex_register_read(priv->ctx, id, MLX5_RXP_CSR_CTRL,\n-\t\t\t\t\t &val);\n+\tret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &val);\n \tif (ret)\n \t\treturn ret;\n \tval &= ~MLX5_RXP_CSR_CTRL_INIT;\n-\tret = mlx5_devx_regex_register_write(priv->ctx, id, MLX5_RXP_CSR_CTRL,\n-\t\t\t\t\t val);\n+\tret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, val);\n \tif (ret)\n \t\treturn ret;\n \trxp_init_rtru(priv, id, MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_L1_L2);\n \tif (priv->is_bf2) {\n-\t\tret = rxp_poll_csr_for_value(priv->ctx, &val,\n-\t\t\t\t\t MLX5_RXP_CSR_STATUS,\n+\t\tret = rxp_poll_csr_for_value(ctx, &val, MLX5_RXP_CSR_STATUS,\n \t\t\t\t\t MLX5_RXP_CSR_STATUS_INIT_DONE,\n \t\t\t\t\t MLX5_RXP_CSR_STATUS_INIT_DONE,\n \t\t\t\t\t MLX5_RXP_CSR_STATUS_TRIAL_TIMEOUT,\n@@ -680,7 +677,7 @@ rxp_init_eng(struct mlx5_regex_priv *priv, uint8_t id)\n {\n \tuint32_t ctrl;\n \tuint32_t reg;\n-\tstruct ibv_context *ctx = priv->ctx;\n+\tstruct ibv_context *ctx = priv->cdev->ctx;\n \tint ret;\n \n \tret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);\n@@ -758,9 +755,10 @@ rxp_db_setup(struct mlx5_regex_priv *priv)\n \t\t\tgoto tidyup_error;\n \t\t}\n \t\t/* Register the memory. */\n-\t\tpriv->db[i].umem.umem = mlx5_glue->devx_umem_reg(priv->ctx,\n-\t\t\t\t\t\t\tpriv->db[i].ptr,\n-\t\t\t\t\t\t\tMLX5_MAX_DB_SIZE, 7);\n+\t\tpriv->db[i].umem.umem = mlx5_glue->devx_umem_reg\n+\t\t\t\t\t\t\t(priv->cdev->ctx,\n+\t\t\t\t\t\t\t priv->db[i].ptr,\n+\t\t\t\t\t\t\t MLX5_MAX_DB_SIZE, 7);\n \t\tif (!priv->db[i].umem.umem) {\n \t\t\tDRV_LOG(ERR, \"Failed to register memory!\");\n \t\t\tret = ENODEV;\n@@ -804,14 +802,14 @@ mlx5_regex_rules_db_import(struct rte_regexdev *dev,\n \t}\n \tif (rule_db_len == 0)\n \t\treturn -EINVAL;\n-\tif (mlx5_devx_regex_register_read(priv->ctx, 0,\n+\tif (mlx5_devx_regex_register_read(priv->cdev->ctx, 0,\n \t\t\t\t\t MLX5_RXP_CSR_BASE_ADDRESS, &ver)) {\n \t\tDRV_LOG(ERR, \"Failed to read Main CSRs Engine 0!\");\n \t\treturn -1;\n \t}\n \t/* Need to ensure RXP not busy before stop! */\n \tfor (id = 0; id < priv->nb_engines; id++) {\n-\t\tret = rxp_stop_engine(priv->ctx, id);\n+\t\tret = rxp_stop_engine(priv->cdev->ctx, id);\n \t\tif (ret) {\n \t\t\tDRV_LOG(ERR, \"Can't stop engine.\");\n \t\t\tret = -ENODEV;\n@@ -823,7 +821,7 @@ mlx5_regex_rules_db_import(struct rte_regexdev *dev,\n \t\t\tret = -ENODEV;\n \t\t\tgoto tidyup_error;\n \t\t}\n-\t\tret = rxp_start_engine(priv->ctx, id);\n+\t\tret = rxp_start_engine(priv->cdev->ctx, id);\n \t\tif (ret) {\n \t\t\tDRV_LOG(ERR, \"Can't start engine.\");\n \t\t\tret = -ENODEV;\n", "prefixes": [ "08/18" ] }