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GET /api/patches/100170/?format=api
{ "id": 100170, "url": "http://patches.dpdk.org/api/patches/100170/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210930172822.1949969-2-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210930172822.1949969-2-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210930172822.1949969-2-michaelba@nvidia.com", "date": "2021-09-30T17:28:05", "name": "[01/18] net/mlx5/windows: fix miss callback register for mem event", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "01b6ed2af80aa4d3182171e6b94120d24f17e50d", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210930172822.1949969-2-michaelba@nvidia.com/mbox/", "series": [ { "id": 19311, "url": "http://patches.dpdk.org/api/series/19311/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19311", "date": "2021-09-30T17:28:04", "name": "mlx5: sharing global MR cache between drivers", "version": 1, "mbox": "http://patches.dpdk.org/series/19311/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/100170/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/100170/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0AAC7A0C43;\n\tThu, 30 Sep 2021 19:39:52 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id F0C55410F0;\n\tThu, 30 Sep 2021 19:39:46 +0200 (CEST)", "from NAM04-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam08on2082.outbound.protection.outlook.com [40.107.100.82])\n by mails.dpdk.org (Postfix) with ESMTP id F40AD4067E;\n Thu, 30 Sep 2021 19:28:48 +0200 (CEST)", "from BN9PR03CA0872.namprd03.prod.outlook.com (2603:10b6:408:13c::7)\n by MWHPR1201MB0256.namprd12.prod.outlook.com (2603:10b6:301:53::8)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4544.20; 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dpdk.org; dkim=none (message not signed)\n header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "<michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Thomas Monjalon <thomas@monjalon.net>,\n Michael Baum <michaelba@oss.nvidia.com>, <stable@dpdk.org>", "Date": "Thu, 30 Sep 2021 20:28:05 +0300", "Message-ID": "<20210930172822.1949969-2-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210930172822.1949969-1-michaelba@nvidia.com>", "References": "<20210930172822.1949969-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "e9d76a4d-83a1-43b8-f7d8-08d98437c287", "X-MS-TrafficTypeDiagnostic": "MWHPR1201MB0256:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <MWHPR1201MB02561216714716BFE95F0608CCAA9@MWHPR1201MB0256.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:5516;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 0FHjYCkQ8xzG0QMTaHqRBVFluycoa/g5fJaqOHjr2iGH8x5gTX9kf9xkOCv/Y2Itu0/4xO8xp/gXneDRdQAyiQP6o/plKpD0K1/ADVn9h47dpCCQ5kz8UYh6FeEAxksTr0EspflP/blQte0heO7Em+Mk+fGRWuZkk3guATiJ/nnYxtjMV8hSnsA3PAsrmhV9YfU4OS13OGk4OWopyRRhzUL1urANA2lCKupAG/kroV1gJPcTBtreEoCEdsYJ9PTM7dQltu+WXgF7EgDqdWM0dr3n5gvpl9OPD2V7XBMgS2MdcJ3eIMe0PAqmWMUrn6QsUXARerAk9EoMOsfWUpX+7OOcfYY1OXE4AW8wFEhrs6HKL+c6JzKpeDTrjlOk/fKyQbG591z2MIwLuXn/jqdRLZWJ3sbHQGbxWmaUUM16YHnKXJnrxMdKDxV/ZXEgi0ltM81H+SZ8hBNcBZDh46ujPSDVwYWRtDw+1j3Z+deGCCgsz36W+OKxXSYoiEGfzTXUbTHXqqBmjqEA3Y9YlCsgom2RrHbvmhpu9dVIWxt/aC809DM1wOVuUox3G2UCxygLDPuB7jOTXEb+F5Xqmjr/iZezTlO9CRbintJibFQfV+rAbgMGZOh95sm7ik7b3MvfWGyD6jeO5H5vXWjiTshFi+js4EqefGj7djH+LOsBB67Es+cgFiJEEsNyx0QBCsa6dHUsmW562zGWtaPjgxhuoA==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(36840700001)(46966006)(82310400003)(26005)(426003)(16526019)(7696005)(356005)(5660300002)(55016002)(336012)(6666004)(508600001)(70586007)(83380400001)(2616005)(8936002)(36756003)(6916009)(36860700001)(54906003)(70206006)(47076005)(316002)(6286002)(86362001)(1076003)(7636003)(8676002)(2906002)(2876002)(4326008)(186003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Sep 2021 17:28:46.9705 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n e9d76a4d-83a1-43b8-f7d8-08d98437c287", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT058.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MWHPR1201MB0256", "X-Mailman-Approved-At": "Thu, 30 Sep 2021 19:39:43 +0200", "Subject": "[dpdk-dev] [PATCH 01/18] net/mlx5/windows: fix miss callback\n register for mem event", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Michael Baum <michaelba@oss.nvidia.com>\n\nIn device initialization, the driver registers to free hugepages events.\nWhen husepage is released, this callback frees all its related MRs.\n\nIn Windows initialization, this callback is not registered what may\ncause to use invalid memory.\n\nThis patch adds memory event callback registration in Windows\ninitialization.\n\nFixes: 980826dc6f0f (\"net/mlx5: probe on Windows\")\nCc: stable@dpdk.org\n\nSigned-off-by: Michael Baum <michaelba@oss.nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/windows/mlx5_os.c | 13 +++++++++++++\n 1 file changed, 13 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c\nindex 149253d174..459414d5c2 100644\n--- a/drivers/net/mlx5/windows/mlx5_os.c\n+++ b/drivers/net/mlx5/windows/mlx5_os.c\n@@ -122,8 +122,21 @@ mlx5_init_shared_data(void)\n static int\n mlx5_init_once(void)\n {\n+\tstruct mlx5_shared_data *sd;\n+\n \tif (mlx5_init_shared_data())\n \t\treturn -rte_errno;\n+\tsd = mlx5_shared_data;\n+\trte_spinlock_lock(&sd->lock);\n+\tMLX5_ASSERT(sd);\n+\tif (!sd->init_done) {\n+\t\tLIST_INIT(&sd->mem_event_cb_list);\n+\t\trte_rwlock_init(&sd->mem_event_rwlock);\n+\t\trte_mem_event_callback_register(\"MLX5_MEM_EVENT_CB\",\n+\t\t\t\t\t\tmlx5_mr_mem_event_cb, NULL);\n+\t\tsd->init_done = true;\n+\t}\n+\trte_spinlock_unlock(&sd->lock);\n \treturn 0;\n }\n \n", "prefixes": [ "01/18" ] }