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{ "id": 75297, "url": "http://patches.dpdk.org/api/covers/75297/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/cover/20200807155859.63888-1-ciara.power@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200807155859.63888-1-ciara.power@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200807155859.63888-1-ciara.power@intel.com", "date": "2020-08-07T15:58:47", "name": "[20.11,00/12] add max SIMD bitwidth to EAL", "submitter": { "id": 978, "url": "http://patches.dpdk.org/api/people/978/?format=api", "name": "Power, Ciara", "email": "ciara.power@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/cover/20200807155859.63888-1-ciara.power@intel.com/mbox/", "series": [ { "id": 11550, "url": "http://patches.dpdk.org/api/series/11550/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11550", "date": "2020-08-07T15:58:47", "name": "add max SIMD bitwidth to EAL", "version": 1, "mbox": "http://patches.dpdk.org/series/11550/mbox/" } ], "comments": "http://patches.dpdk.org/api/covers/75297/comments/", "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 50D2BA04B0;\n\tFri, 7 Aug 2020 18:06:30 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 81ACE2BF1;\n\tFri, 7 Aug 2020 18:06:29 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by dpdk.org (Postfix) with ESMTP id C295D2B84\n for <dev@dpdk.org>; Fri, 7 Aug 2020 18:06:27 +0200 (CEST)", "from fmsmga007.fm.intel.com ([10.253.24.52])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 07 Aug 2020 09:06:26 -0700", "from silpixa00399953.ir.intel.com (HELO\n silpixa00399953.ger.corp.intel.com) ([10.237.222.53])\n by fmsmga007.fm.intel.com with ESMTP; 07 Aug 2020 09:06:25 -0700" ], "IronPort-SDR": [ "\n qSoud/ESgQ2NlscqugbqIwxavKSE47S5tUkvyTEXj0VwUZM5OK1UMKHkKrLQ880kaCkNhlMGff\n Eq1BErUa0Myw==", "\n CwGNUE8j1xsAuJix2d3SwGnsJFJHNDLtJXVYcE9Ys9lKbrz17ti0Q1WgFvIK//lqGbL7SKJf64\n ns0FpkEsZIWg==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9705\"; a=\"171183016\"", "E=Sophos;i=\"5.75,446,1589266800\"; d=\"scan'208\";a=\"171183016\"", "E=Sophos;i=\"5.75,446,1589266800\"; d=\"scan'208\";a=\"275407853\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Ciara Power <ciara.power@intel.com>", "To": "dev@dpdk.org", "Cc": "bruce.richardson@intel.com,\n\tCiara Power <ciara.power@intel.com>", "Date": "Fri, 7 Aug 2020 16:58:47 +0100", "Message-Id": "<20200807155859.63888-1-ciara.power@intel.com>", "X-Mailer": "git-send-email 2.17.1", "Subject": "[dpdk-dev] [PATCH 20.11 00/12] add max SIMD bitwidth to EAL", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "A number of components in DPDK have optional AVX-512 or other vector\ncode paths which can be selected at runtime. Rather than having each\ncomponent provide its own mechanism to select a code path, this patchset\nadds support for a single setting to control what code paths are used.\nThis can be used to enable some non-default code paths e.g. ones using\nAVX-512, but also to limit the code paths to certain vector widths, or\nto scalar code only, which is useful for testing.\n\nThe max SIMD bitwidth setting can be set by the app itself through use of\nthe available API, or can be overriden by a commandline argument passed by\nthe user.\n\nCiara Power (12):\n eal: add max SIMD bitwidth\n eal: add default SIMD bitwidth values\n net/i40e: add checks for max SIMD bitwidth\n net/axgbe: add checks for max SIMD bitwidth\n net/bnxt: add checks for max SIMD bitwidth\n net/enic: add checks for max SIMD bitwidth\n net/fm10k: add checks for max SIMD bitwidth\n net/iavf: add checks for max SIMD bitwidth\n net/ice: add checks for max SIMD bitwidth\n net/ixgbe: add checks for max SIMD bitwidth\n net/mlx5: add checks for max SIMD bitwidth\n net/virtio: add checks for max SIMD bitwidth\n\n drivers/net/axgbe/axgbe_rxtx.c | 3 +-\n drivers/net/bnxt/bnxt_ethdev.c | 6 ++-\n drivers/net/enic/enic_rxtx_vec_avx2.c | 3 +-\n drivers/net/fm10k/fm10k_ethdev.c | 11 ++--\n drivers/net/i40e/i40e_rxtx.c | 19 ++++---\n drivers/net/iavf/iavf_rxtx.c | 16 +++---\n drivers/net/ice/ice_rxtx.c | 20 ++++---\n drivers/net/ixgbe/ixgbe_rxtx.c | 7 ++-\n drivers/net/mlx5/mlx5_ethdev.c | 3 +-\n drivers/net/virtio/virtio_ethdev.c | 12 +++--\n lib/librte_eal/arm/include/rte_vect.h | 2 +\n lib/librte_eal/common/eal_common_options.c | 63 ++++++++++++++++++++++\n lib/librte_eal/common/eal_internal_cfg.h | 8 +++\n lib/librte_eal/common/eal_options.h | 2 +\n lib/librte_eal/include/generic/rte_vect.h | 2 +\n lib/librte_eal/include/rte_eal.h | 31 +++++++++++\n lib/librte_eal/ppc/include/rte_vect.h | 2 +\n lib/librte_eal/rte_eal_version.map | 4 ++\n lib/librte_eal/x86/include/rte_vect.h | 2 +\n 19 files changed, 184 insertions(+), 32 deletions(-)" }