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{ "id": 110762, "url": "http://patches.dpdk.org/api/covers/110762/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/cover/20220506035645.4101714-1-spiked@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220506035645.4101714-1-spiked@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220506035645.4101714-1-spiked@nvidia.com", "date": "2022-05-06T03:56:38", "name": "[RFC,v1,0/7] net/mlx5: introduce limit watermark and host shaper", "submitter": { "id": 2637, "url": "http://patches.dpdk.org/api/people/2637/?format=api", "name": "Spike Du", "email": "spiked@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/cover/20220506035645.4101714-1-spiked@nvidia.com/mbox/", "series": [ { "id": 22804, "url": "http://patches.dpdk.org/api/series/22804/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=22804", "date": "2022-05-06T03:56:38", "name": "net/mlx5: introduce limit watermark and host shaper", "version": 1, "mbox": "http://patches.dpdk.org/series/22804/mbox/" } ], "comments": "http://patches.dpdk.org/api/covers/110762/comments/", "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 6E0E8A0503;\n\tFri, 6 May 2022 05:57:07 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 189724014F;\n\tFri, 6 May 2022 05:57:07 +0200 (CEST)", "from NAM12-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam12on2057.outbound.protection.outlook.com [40.107.237.57])\n by mails.dpdk.org (Postfix) with ESMTP id 80A4B40042\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Spike Du <spiked@nvidia.com>", "To": "<matan@nvidia.com>, <viacheslavo@nvidia.com>, <orika@nvidia.com>,\n <thomas@monjalon.net>", "CC": "<dev@dpdk.org>, <rasland@nvidia.com>", "Subject": "[RFC v1 0/7] net/mlx5: introduce limit watermark and host shaper", "Date": "Fri, 6 May 2022 06:56:38 +0300", "Message-ID": "<20220506035645.4101714-1-spiked@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20220401032232.1267376-2-spiked@nvidia.com>", "References": "<20220401032232.1267376-2-spiked@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "06aabeab-f501-4559-7bdb-08da2f147acc", "X-MS-TrafficTypeDiagnostic": "SJ1PR12MB6315:EE_", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <SJ1PR12MB63151EBB95FCFB25C0A7B4BFA8C59@SJ1PR12MB6315.namprd12.prod.outlook.com>", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n y14UZ9o7sR8zSzjekfU3faDDmkTe/+EqWCWCZq6bY0NRgXmILw8PNdhTdmGq1WFAMJJD+8HFnVZXG+lroiFXrK21Uv06I9hdcBCZ5m+kHOooDbWWNYhNRYagDjJ09/As0xBAt7RWufP/nwv+BsLqNxic+Ssu8Ld4+fa06pPTw1PKjWxbNauBsWVEL+0Jwl+WyP2/r8jpq7AvKm5VRKows8D2jTiiSIaE0Pw4PR+ziNctEyl4/0zmWO6sW1rnclYDT6IIxDvyvDBY/Bta0oqfyWaUL/lFj5DoYbUjV/vhO2Q45QWAUKkPcLwzrZR77iE3wSKzQ0iUMOG0yuPSdLSQ4VSUYfUYWTiJddo27445/XukQMJtgcvttoKhbYVw4U6pBRdv66rYiFyN337L1gj7Yl7nOdy/YBnychHpc5nrBsuLe3QOVSUPlngHhlMbvF761PRelE1CDGKwNREamMe7qVdVlfp1qFzZyIh9YcTop0FgvIr3bezbRj8gTBfba1G/Z1TYASCYtR2SrVA9pTp42/vLfgwi/3KGuXQczL5jSoKc78wETAXEZqnmomC/1RtIQK2DsGWlFKWe3sYWsg0PwJFnyteE0RQU38plfeU8Ur+OZBRNWLU2GqZOcMt4nzEVqycmQmAPBatM2AbcJLsOzedMZlIOuRzXaIFTdn57PCG259Yf0jTOJ/VIz3xSfDxOAll/Sy+Z1lwqPkEjBi8TKQ==", "X-Forefront-Antispam-Report": "CIP:12.22.5.235; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(8936002)(508600001)(70586007)(26005)(8676002)(6286002)(81166007)(86362001)(4326008)(36860700001)(70206006)(316002)(54906003)(110136005)(356005)(6666004)(7696005)(5660300002)(40460700003)(2616005)(186003)(16526019)(1076003)(107886003)(47076005)(336012)(82310400005)(426003)(36756003)(83380400001)(2906002)(55016003)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "06 May 2022 03:57:03.0700 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 06aabeab-f501-4559-7bdb-08da2f147acc", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT064.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SJ1PR12MB6315", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "LWM(limit watermark) is per RX queue attribute, when RX queue fullness reach\nthe LWM limit, HW sends an event to dpdk application.\nHost shaper can configure shaper rate and lwm-triggered for a host port.\nThe shaper limits the rate of traffic from host port to wire port.\nIf lwm-triggered is enabled, a 100Mbps shaper is enabled automatically\nwhen one of the host port's Rx queues receives LWM event.\n\nThese two features can combine to control traffic from host port to wire port.\nThe work flow is configure LWM to RX queue and enable lwm-triggered flag in\nhost shaper, after receiving LWM event, delay a while until RX queue is empty\n, then disable the shaper. We recycle this work flow to reduce RX queue drops.\n\nAdd new libethdev API to set LWM, add rte event RTE_ETH_EVENT_RXQ_LIMIT_REACHED\nto handle LWM event. For host shaper, because it doesn't align to existing DPDK\nframework and is specific to Nvidia NIC, use PMD private API.\n\nFor integration with testpmd, put the private cmdline function and LWM event\nhandler in mlx5 PMD directory by adding a new file mlx5_test.c. Only add minimal\ncode in testpmd to invoke interfaces from mlx5_test.c.\n\nSpike Du (7):\n net/mlx5: add LWM support for Rxq\n common/mlx5: share interrupt management\n ethdev: introduce Rx queue based limit watermark\n net/mlx5: add LWM event handling support\n net/mlx5: support Rx queue based limit watermark\n net/mlx5: add private API to config host port shaper\n app/testpmd: add LWM and Host Shaper command\n\n app/test-pmd/cmdline.c | 74 ++++++++\n app/test-pmd/config.c | 23 +++\n app/test-pmd/meson.build | 3 +\n app/test-pmd/testpmd.c | 13 ++\n app/test-pmd/testpmd.h | 1 +\n doc/guides/nics/mlx5.rst | 87 +++++++++\n doc/guides/rel_notes/release_22_07.rst | 2 +\n drivers/common/mlx5/linux/meson.build | 44 +++--\n drivers/common/mlx5/linux/mlx5_common_os.c | 131 ++++++++++++++\n drivers/common/mlx5/linux/mlx5_common_os.h | 11 ++\n drivers/common/mlx5/mlx5_prm.h | 26 +++\n drivers/common/mlx5/version.map | 3 +-\n drivers/common/mlx5/windows/mlx5_common_os.h | 24 +++\n drivers/net/mlx5/linux/mlx5_ethdev_os.c | 71 --------\n drivers/net/mlx5/linux/mlx5_os.c | 132 +++-----------\n drivers/net/mlx5/linux/mlx5_socket.c | 53 +-----\n drivers/net/mlx5/meson.build | 7 +-\n drivers/net/mlx5/mlx5.c | 62 +++++++\n drivers/net/mlx5/mlx5.h | 12 +-\n drivers/net/mlx5/mlx5_devx.c | 60 ++++++-\n drivers/net/mlx5/mlx5_devx.h | 1 +\n drivers/net/mlx5/mlx5_rx.c | 253 +++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_rx.h | 11 ++\n drivers/net/mlx5/mlx5_test.c | 191 ++++++++++++++++++++\n drivers/net/mlx5/mlx5_test.h | 27 +++\n drivers/net/mlx5/mlx5_txpp.c | 28 +--\n drivers/net/mlx5/rte_pmd_mlx5.h | 30 ++++\n drivers/net/mlx5/version.map | 2 +\n drivers/net/mlx5/windows/mlx5_ethdev_os.c | 22 ---\n drivers/vdpa/mlx5/mlx5_vdpa_virtq.c | 52 +-----\n lib/ethdev/ethdev_driver.h | 7 +\n lib/ethdev/rte_ethdev.c | 28 +++\n lib/ethdev/rte_ethdev.h | 30 +++-\n lib/ethdev/version.map | 3 +\n 34 files changed, 1193 insertions(+), 331 deletions(-)\n create mode 100644 drivers/net/mlx5/mlx5_test.c\n create mode 100644 drivers/net/mlx5/mlx5_test.h" }