From patchwork Sat Mar 7 09:56:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kiran Kumar Kokkilagadda X-Patchwork-Id: 66361 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2E56DA0564; Sat, 7 Mar 2020 10:57:33 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 208E41BF90; Sat, 7 Mar 2020 10:57:32 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id C0F143B5 for ; Sat, 7 Mar 2020 10:57:30 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 0279vUEw025993 for ; Sat, 7 Mar 2020 01:57:30 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=pfpt0818; bh=y4SnhI/ZbwtjB1LCX5atVoEe5pX2c4OKKnpkuucHVRI=; b=hxGWd3/Iz6jBgerSsnuulYL8iqoK5E7zqQC7ToAbUkdM4TwleNOvlPDRMbZZMEpxEaGV 8vkvYFhRY4AgMwIzMJIeJOZOw4ijHT8wWRixmh5PZUae/US+75oMvdnXq8Y7q0+BMdni IlvVefzGDZx/NjRPE+eyUT1kr+Q/dkUhrAoNhSbRXvwhl513Y3R0h0sIjwGYj1z0gupC nCzkca2fUNgU8G1Qb5+Uhj7Z90GWJv+lcYd7FdwWGXGEtdYM1Wp8Gpdq5tCZ+w9CcecT czMdpGujTCnnHKtcgais9NP8ZqtUstyQ//jJvk+qf9kCO1bnKbDsa79wIvGeo4rVUtfc gg== Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0b-0016f401.pphosted.com with ESMTP id 2ym0pk1uua-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 07 Mar 2020 01:57:29 -0800 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 7 Mar 2020 01:57:27 -0800 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 7 Mar 2020 01:57:27 -0800 Received: from localhost.localdomain (unknown [10.28.34.15]) by maili.marvell.com (Postfix) with ESMTP id 4C17A3F703F; Sat, 7 Mar 2020 01:57:26 -0800 (PST) From: To: Jerin Jacob , Nithin Dabilpuram , Kiran Kumar K CC: Date: Sat, 7 Mar 2020 15:26:53 +0530 Message-ID: <20200307095653.13471-1-kirankumark@marvell.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-03-07_02:2020-03-06, 2020-03-07 signatures=0 Subject: [dpdk-dev] [PATCH] net/octeontx2: offload bad L2/L3/L4 UDP lengths detection X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kiran Kumar K Octeontx2 HW has support for detecting the bad L2/L3/L4 UDP lengths. Since DPDK does not have specific error flag for this, exposing it as bad checksum failure in mbuff:ol_flags to leverage this feature. These errors will be propagated to the ol_flags as follows. L2 length error ==> (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD). Both Outer and Inner L3 length error ==> PKT_RX_IP_CKSUM_BAD. Outer L4 UDP length/port error ==> PKT_RX_OUTER_L4_CKSUM_BAD. Inner L4 UDP length/port error ==> PKT_RX_L4_CKSUM_BAD. Signed-off-by: Kiran Kumar K Acked-by: Jerin Jacob --- drivers/net/octeontx2/otx2_ethdev.c | 8 +++++++- drivers/net/octeontx2/otx2_lookup.c | 21 +++++++++++++++------ 2 files changed, 22 insertions(+), 7 deletions(-) diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c index e60f4901c..7202af625 100644 --- a/drivers/net/octeontx2/otx2_ethdev.c +++ b/drivers/net/octeontx2/otx2_ethdev.c @@ -70,7 +70,13 @@ nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq) req->rx_cfg |= BIT_ULL(37 /* CSUM_OL4 */); req->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */); } - req->rx_cfg |= BIT_ULL(32 /* DROP_RE */); + req->rx_cfg |= (BIT_ULL(32 /* DROP_RE */) | + BIT_ULL(33 /* Outer L2 Length */) | + BIT_ULL(38 /* Inner L4 UDP Length */) | + BIT_ULL(39 /* Inner L3 Length */) | + BIT_ULL(40 /* Outer L4 UDP Length */) | + BIT_ULL(41 /* Outer L3 Length */)); + if (dev->rss_tag_as_xor == 0) req->flags = NIX_LF_RSS_TAG_LSB_AS_ADDER; diff --git a/drivers/net/octeontx2/otx2_lookup.c b/drivers/net/octeontx2/otx2_lookup.c index 89365ffad..9dcfc750d 100644 --- a/drivers/net/octeontx2/otx2_lookup.c +++ b/drivers/net/octeontx2/otx2_lookup.c @@ -270,7 +270,9 @@ nix_create_rx_ol_flags_array(void *mem) switch (errlev) { case NPC_ERRLEV_RE: - /* Mark all errors as BAD checksum errors */ + /* Mark all errors as BAD checksum errors + * including Outer L2 length mismatch error + */ if (errcode) { val |= PKT_RX_IP_CKSUM_BAD; val |= PKT_RX_L4_CKSUM_BAD; @@ -295,18 +297,25 @@ nix_create_rx_ol_flags_array(void *mem) val |= PKT_RX_IP_CKSUM_GOOD; break; case NPC_ERRLEV_NIX: - val |= PKT_RX_IP_CKSUM_GOOD; - if (errcode == NIX_RX_PERRCODE_OL4_CHK) { + if (errcode == NIX_RX_PERRCODE_OL4_CHK || + errcode == NIX_RX_PERRCODE_OL4_LEN || + errcode == NIX_RX_PERRCODE_OL4_PORT) { + val |= PKT_RX_IP_CKSUM_GOOD; val |= PKT_RX_OUTER_L4_CKSUM_BAD; + } else if (errcode == NIX_RX_PERRCODE_IL4_CHK || + errcode == NIX_RX_PERRCODE_IL4_LEN || + errcode == NIX_RX_PERRCODE_IL4_PORT) { + val |= PKT_RX_IP_CKSUM_GOOD; val |= PKT_RX_L4_CKSUM_BAD; - } else if (errcode == NIX_RX_PERRCODE_IL4_CHK) { - val |= PKT_RX_L4_CKSUM_BAD; + } else if (errcode == NIX_RX_PERRCODE_IL3_LEN || + errcode == NIX_RX_PERRCODE_OL3_LEN) { + val |= PKT_RX_IP_CKSUM_BAD; } else { + val |= PKT_RX_IP_CKSUM_GOOD; val |= PKT_RX_L4_CKSUM_GOOD; } break; } - ol_flags[idx] = val; } }