From patchwork Tue Jan 14 09:26:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kiran Kumar Kokkilagadda X-Patchwork-Id: 64633 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id D3A4FA04FD; Tue, 14 Jan 2020 10:26:59 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id AA7101C224; Tue, 14 Jan 2020 10:26:58 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 70E561C223; Tue, 14 Jan 2020 10:26:57 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 00E9KRAh002199; Tue, 14 Jan 2020 01:26:56 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0818; bh=TOAwpstum2rGglYaFxVShxm9IXvtneUEp0XorIiou64=; b=uEFEW27MIIcSSu2Di+peJtUJvgmEEWQVznFSjzp/P5nm0gHOVrjgC9MFxj8C9EFVsXJH 22860jnnq3+YAPKvM+MD70wuBEvjVFYjBLxXuPDzYenQZwOcWKCC7SSM387ftrDrwfDa F0HHKLqv+oxtbx2G3g1/H/ZFlChmCnNEWAjc4sOfvcs0w/l3gX3bgtFroMcytu+xxELD onE4nP6TpPANTOZ868zr+hWORfxrn7mUVNN6qmBORlKqouLidKXnthIUx/ICfe5jAYbv 9ITCrW2AKNouDFUkWCm5Ugcb3/GwPjlWNReMmSnAv7GMjYm5LuXQBJkOJ9DCi7se9KjP VA== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0a-0016f401.pphosted.com with ESMTP id 2xfckusfpf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 14 Jan 2020 01:26:56 -0800 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 14 Jan 2020 01:26:55 -0800 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 14 Jan 2020 01:26:55 -0800 Received: from localhost.localdomain (unknown [10.28.34.15]) by maili.marvell.com (Postfix) with ESMTP id 816903F703F; Tue, 14 Jan 2020 01:26:53 -0800 (PST) From: To: Jerin Jacob , Nithin Dabilpuram , Kiran Kumar K CC: , Date: Tue, 14 Jan 2020 14:56:22 +0530 Message-ID: <20200114092622.13944-1-kirankumark@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200114082854.13198-1-kirankumark@marvell.com> References: <20200114082854.13198-1-kirankumark@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-14_02:2020-01-13, 2020-01-14 signatures=0 Subject: [dpdk-dev] [PATCH v3] net/octeontx2: fix PTP and HIGIG2 coexistence X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kiran Kumar K octeontx2 PMD does not support both PTP and HIGIG2 together. added a check to enforce this and updated the Rx offload capabilities when Higig2 mode enabled fixes: 602009ee2dfb (net/octeontx2: support HIGIG2) Signed-off-by: Kiran Kumar K Acked-by: Jerin Jacob --- V3 Changes: * Fixed commit log V2 Chanhes: * Fixed error message drivers/net/octeontx2/otx2_ethdev.c | 9 ++++++++- drivers/net/octeontx2/otx2_ptp.c | 5 +++++ 2 files changed, 13 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c index ed329273d..2e91a5ab7 100644 --- a/drivers/net/octeontx2/otx2_ethdev.c +++ b/drivers/net/octeontx2/otx2_ethdev.c @@ -18,7 +18,8 @@ nix_get_rx_offload_capa(struct otx2_eth_dev *dev) { uint64_t capa = NIX_RX_OFFLOAD_CAPA; - if (otx2_dev_is_vf(dev)) + if (otx2_dev_is_vf(dev) || + dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) capa &= ~DEV_RX_OFFLOAD_TIMESTAMP; return capa; @@ -1641,6 +1642,12 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev) goto fail_offloads; } + if (dev->ptp_en && + dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) { + otx2_err("Both PTP and switch header enabled"); + goto free_nix_lf; + } + rc = nix_lf_switch_header_type_enable(dev); if (rc) { otx2_err("Failed to enable switch type nix_lf rc=%d", rc); diff --git a/drivers/net/octeontx2/otx2_ptp.c b/drivers/net/octeontx2/otx2_ptp.c index f34b9339c..ae5a2b7cd 100644 --- a/drivers/net/octeontx2/otx2_ptp.c +++ b/drivers/net/octeontx2/otx2_ptp.c @@ -221,6 +221,11 @@ otx2_nix_timesync_enable(struct rte_eth_dev *eth_dev) return -EINVAL; } + if (dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) { + otx2_err("Both PTP and switch header enabled"); + return -EINVAL; + } + /* Allocating a iova address for tx tstamp */ const struct rte_memzone *ts; ts = rte_eth_dma_zone_reserve(eth_dev, "otx2_ts",