From patchwork Mon Jul 23 13:05:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fiona Trahe X-Patchwork-Id: 43267 X-Patchwork-Delegate: pablo.de.lara.guarch@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E3C23F72; Mon, 23 Jul 2018 15:05:45 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id A958DF72 for ; Mon, 23 Jul 2018 15:05:43 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Jul 2018 06:05:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,393,1526367600"; d="scan'208";a="218301556" Received: from sivswdev01.ir.intel.com (HELO localhost.localdomain) ([10.237.217.45]) by orsmga004.jf.intel.com with ESMTP; 23 Jul 2018 06:05:40 -0700 From: Fiona Trahe To: dev@dpdk.org Cc: pablo.de.lara.guarch@intel.com, fiona.trahe@intel.com, tomaszx.jozwiak@intel.com Date: Mon, 23 Jul 2018 14:05:35 +0100 Message-Id: <1532351135-10064-1-git-send-email-fiona.trahe@intel.com> X-Mailer: git-send-email 1.7.0.7 In-Reply-To: <1531850150-21767-1-git-send-email-fiona.trahe@intel.com> References: <1531850150-21767-1-git-send-email-fiona.trahe@intel.com> Subject: [dpdk-dev] [PATCH v2 1/2] common/qat: add sgl header X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch refactors the sgl struct so it includes a flexible array of flat buffers as sym and compress PMDs can have different size sgls. Signed-off-by: Tomasz Jozwiak Signed-off-by: Fiona Trahe --- v2 changes: - changed max_segs from int32_t to uint16_t to match max allowed by mbuf - declared loop index outside for statement to work for all compilers drivers/common/qat/qat_common.c | 57 +++++++++++++++++++++++++++++++---------- drivers/common/qat/qat_common.h | 23 +++++++++-------- drivers/crypto/qat/qat_sym.c | 12 +++++---- drivers/crypto/qat/qat_sym.h | 14 ++++++++-- 4 files changed, 75 insertions(+), 31 deletions(-) diff --git a/drivers/common/qat/qat_common.c b/drivers/common/qat/qat_common.c index c206d3b..81a99c1 100644 --- a/drivers/common/qat/qat_common.c +++ b/drivers/common/qat/qat_common.c @@ -8,40 +8,53 @@ int qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buf_start, - struct qat_sgl *list, uint32_t data_len) + void *list_in, uint32_t data_len, + const uint16_t max_segs) { int nr = 1; - - uint32_t buf_len = rte_pktmbuf_iova(buf) - - buf_start + rte_pktmbuf_data_len(buf); + struct qat_sgl *list = (struct qat_sgl *)list_in; + /* buf_start allows the first buffer to start at an address before or + * after the mbuf data start. It's used to either optimally align the + * dma to 64 or to start dma from an offset. + */ + uint32_t buf_len; + uint32_t first_buf_len = rte_pktmbuf_data_len(buf) + + (rte_pktmbuf_mtophys(buf) - buf_start); +#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG + uint8_t *virt_addr[max_segs]; + virt_addr[0] = rte_pktmbuf_mtod(buf, uint8_t*) + + (rte_pktmbuf_mtophys(buf) - buf_start); +#endif list->buffers[0].addr = buf_start; list->buffers[0].resrvd = 0; - list->buffers[0].len = buf_len; + list->buffers[0].len = first_buf_len; - if (data_len <= buf_len) { + if (data_len <= first_buf_len) { list->num_bufs = nr; list->buffers[0].len = data_len; - return 0; + goto sgl_end; } buf = buf->next; + buf_len = first_buf_len; while (buf) { - if (unlikely(nr == QAT_SGL_MAX_NUMBER)) { - QAT_LOG(ERR, - "QAT PMD exceeded size of QAT SGL entry(%u)", - QAT_SGL_MAX_NUMBER); + if (unlikely(nr == max_segs)) { + QAT_DP_LOG(ERR, "Exceeded max segments in QAT SGL (%u)", + max_segs); return -EINVAL; } list->buffers[nr].len = rte_pktmbuf_data_len(buf); list->buffers[nr].resrvd = 0; - list->buffers[nr].addr = rte_pktmbuf_iova(buf); - + list->buffers[nr].addr = rte_pktmbuf_mtophys(buf); +#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG + virt_addr[nr] = rte_pktmbuf_mtod(buf, uint8_t*); +#endif buf_len += list->buffers[nr].len; buf = buf->next; - if (buf_len > data_len) { + if (buf_len >= data_len) { list->buffers[nr].len -= buf_len - data_len; buf = NULL; @@ -50,6 +63,22 @@ qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buf_start, } list->num_bufs = nr; +sgl_end: +#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG + { + uint16_t i; + QAT_DP_LOG(INFO, "SGL with %d buffers:", list->num_bufs); + for (i = 0; i < list->num_bufs; i++) { + QAT_DP_LOG(INFO, + "QAT SGL buf %d, len = %d, iova = 0x%012lx", + i, list->buffers[i].len, + list->buffers[i].addr); + QAT_DP_HEXDUMP_LOG(DEBUG, "qat SGL", + virt_addr[i], list->buffers[i].len); + } + } +#endif + return 0; } diff --git a/drivers/common/qat/qat_common.h b/drivers/common/qat/qat_common.h index db85d54..b26aa26 100644 --- a/drivers/common/qat/qat_common.h +++ b/drivers/common/qat/qat_common.h @@ -10,11 +10,6 @@ /**< Intel(R) QAT device name for PCI registration */ #define QAT_PCI_NAME qat -/* - * Maximum number of SGL entries - */ -#define QAT_SGL_MAX_NUMBER 16 - #define QAT_64_BTYE_ALIGN_MASK (~0x3f) /* Intel(R) QuickAssist Technology device generation is enumerated @@ -31,6 +26,7 @@ enum qat_service_type { QAT_SERVICE_COMPRESSION, QAT_SERVICE_INVALID }; + #define QAT_MAX_SERVICES (QAT_SERVICE_INVALID) /**< Common struct for scatter-gather list operations */ @@ -40,11 +36,17 @@ struct qat_flat_buf { uint64_t addr; } __rte_packed; +#define qat_sgl_hdr struct { \ + uint64_t resrvd; \ + uint32_t num_bufs; \ + uint32_t num_mapped_bufs; \ +} + +__extension__ struct qat_sgl { - uint64_t resrvd; - uint32_t num_bufs; - uint32_t num_mapped_bufs; - struct qat_flat_buf buffers[QAT_SGL_MAX_NUMBER]; + qat_sgl_hdr; + /* flexible array of flat buffers*/ + struct qat_flat_buf buffers[0]; } __rte_packed __rte_cache_aligned; /** Common, i.e. not service-specific, statistics */ @@ -64,7 +66,8 @@ struct qat_pci_device; int qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buf_start, - struct qat_sgl *list, uint32_t data_len); + void *list_in, uint32_t data_len, + const uint16_t max_segs); void qat_stats_get(struct qat_pci_device *dev, struct qat_common_stats *stats, diff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c index 4ed7d95..8273968 100644 --- a/drivers/crypto/qat/qat_sym.c +++ b/drivers/crypto/qat/qat_sym.c @@ -495,8 +495,9 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg, ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags, QAT_COMN_PTR_TYPE_SGL); ret = qat_sgl_fill_array(op->sym->m_src, src_buf_start, - &cookie->qat_sgl_src, - qat_req->comn_mid.src_length); + &cookie->qat_sgl_src, + qat_req->comn_mid.src_length, + QAT_SYM_SGL_MAX_NUMBER); if (unlikely(ret)) { QAT_DP_LOG(ERR, "QAT PMD Cannot fill sgl array"); @@ -509,9 +510,10 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg, cookie->qat_sgl_src_phys_addr; else { ret = qat_sgl_fill_array(op->sym->m_dst, - dst_buf_start, - &cookie->qat_sgl_dst, - qat_req->comn_mid.dst_length); + dst_buf_start, + &cookie->qat_sgl_dst, + qat_req->comn_mid.dst_length, + QAT_SYM_SGL_MAX_NUMBER); if (unlikely(ret)) { QAT_DP_LOG(ERR, "QAT PMD can't fill sgl array"); diff --git a/drivers/crypto/qat/qat_sym.h b/drivers/crypto/qat/qat_sym.h index e4e1ae8..bc6426c 100644 --- a/drivers/crypto/qat/qat_sym.h +++ b/drivers/crypto/qat/qat_sym.h @@ -21,11 +21,21 @@ */ #define BPI_MAX_ENCR_IV_LEN ICP_QAT_HW_AES_BLK_SZ +/* + * Maximum number of SGL entries + */ +#define QAT_SYM_SGL_MAX_NUMBER 16 + struct qat_sym_session; +struct qat_sym_sgl { + qat_sgl_hdr; + struct qat_flat_buf buffers[QAT_SYM_SGL_MAX_NUMBER]; +} __rte_packed __rte_cache_aligned; + struct qat_sym_op_cookie { - struct qat_sgl qat_sgl_src; - struct qat_sgl qat_sgl_dst; + struct qat_sym_sgl qat_sgl_src; + struct qat_sym_sgl qat_sgl_dst; phys_addr_t qat_sgl_src_phys_addr; phys_addr_t qat_sgl_dst_phys_addr; };