From patchwork Thu Oct 24 05:58:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 61801 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 314C51C02E; Thu, 24 Oct 2019 08:06:58 +0200 (CEST) Received: from relay.smtp.broadcom.com (relay.smtp.broadcom.com [192.19.211.62]) by dpdk.org (Postfix) with ESMTP id 008B31C025 for ; Thu, 24 Oct 2019 08:06:56 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (bgccx-dev-host-lnx35.bec.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id 0BD3C28FA6B; Wed, 23 Oct 2019 23:06:56 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com 0BD3C28FA6B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1571897216; bh=H+s+6U0kjZT6gepK6UaQY1QbDuKM6zKzLliaKgO2+5Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fayqgteJtZjcSopKypl0IreeMHdYBrO/SDSE+CO5f7iJBauwaMHPN8/fdrHqlHsLx VblAgxrx9gqXxp237a9BWHNEo1Afp7/eWww+dvSxAVXh0wuJt294nnZuNDtxgb1Cj4 VJ7ic00Bm+e9gP/mcK2vAPiyfZGZYb6gjGTEuC5s= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Thu, 24 Oct 2019 11:28:56 +0530 Message-Id: <20191024055913.28817-2-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20191024055913.28817-1-somnath.kotur@broadcom.com> References: <20191024055913.28817-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 01/16] net/bnxt: fix unused value in free filter mem X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kalesh AP This patch fixes the coverity UNUSED_VALUE issue. Coverity issue: 349938 Fixes: 49d0709b257f ("net/bnxt: delete and flush L2 filters cleanly") Signed-off-by: Kalesh AP Reviewed-by: Ajit Kumar Khaparde Signed-off-by: Somnath Kotur --- drivers/net/bnxt/bnxt_filter.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/bnxt/bnxt_filter.c b/drivers/net/bnxt/bnxt_filter.c index 8120b39..1c8e3e3 100644 --- a/drivers/net/bnxt/bnxt_filter.c +++ b/drivers/net/bnxt/bnxt_filter.c @@ -120,6 +120,10 @@ void bnxt_free_filter_mem(struct bnxt *bp) filter->filter_type == HWRM_CFA_NTUPLE_FILTER) { /* Call HWRM to try to free filter again */ rc = bnxt_hwrm_clear_ntuple_filter(bp, filter); + if (rc) + PMD_DRV_LOG(ERR, + "Cannot free ntuple filter: %d\n", + rc); } filter->fw_ntuple_filter_id = UINT64_MAX; From patchwork Thu Oct 24 05:58:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 61803 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2A1731C19E; Thu, 24 Oct 2019 08:07:06 +0200 (CEST) Received: from relay.smtp.broadcom.com (unknown [192.19.211.62]) by dpdk.org (Postfix) with ESMTP id 46E4D1C02E for ; Thu, 24 Oct 2019 08:06:57 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (bgccx-dev-host-lnx35.bec.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id 6230B28FA88; Wed, 23 Oct 2019 23:06:56 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com 6230B28FA88 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1571897216; bh=Dljq8sUZiBCWwgDOuhTQNRkNUMZezizYGGFT7tENNmA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=inydwewe3H39JFCL5/JwHXUwhe1Odf8FhLFDmcSqz12P2HaPZ6q5aAWj7aI1zeQTC EWZAL71fw6USaVhrnfTAMw62HrLNp8MhOoX5usAuS4UROtxP1Sn+Fpp982HMjJWwzL LDUXHmnbRljOeaZiYCaWW2cPKiai2hCM7oXC03p4= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Thu, 24 Oct 2019 11:28:57 +0530 Message-Id: <20191024055913.28817-3-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20191024055913.28817-1-somnath.kotur@broadcom.com> References: <20191024055913.28817-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 02/16] net/bnxt: fix ping failure with MTU change X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Santoshkumar Karanappa Rastapur Driver was setting maximum receive unit differently in bnxt_mtu_set_op and bnxt_hwrm_vnic_alloc. Moreover firmware adds the 4 bytes for FCS. Fixed it by setting correct maximum receive unit value. Reviewed-by: Ajit Kumar Khaparde Signed-off-by: Santoshkumar Karanappa Rastapur Signed-off-by: Somnath Kotur --- drivers/net/bnxt/bnxt.h | 3 +++ drivers/net/bnxt/bnxt_ethdev.c | 3 +-- drivers/net/bnxt/bnxt_hwrm.c | 11 +++-------- 3 files changed, 7 insertions(+), 10 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index e5bdf63..975bcf9 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -77,6 +77,9 @@ #define BNXT_MAX_PKT_LEN (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\ RTE_ETHER_CRC_LEN +\ (BNXT_NUM_VLANS * VLAN_TAG_SIZE)) +/* FW adds extra 4 bytes for FCS */ +#define BNXT_VNIC_MRU(mtu)\ + ((mtu) + RTE_ETHER_HDR_LEN + VLAN_TAG_SIZE * BNXT_NUM_VLANS) #define BNXT_VF_RSV_NUM_RSS_CTX 1 #define BNXT_VF_RSV_NUM_L2_CTX 4 /* TODO: For now, do not support VMDq/RFS on VFs. */ diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index e7ec99e..c97fcac 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -2174,8 +2174,7 @@ static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; uint16_t size = 0; - vnic->mru = new_mtu + RTE_ETHER_HDR_LEN + - RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2; + vnic->mru = BNXT_VNIC_MRU(new_mtu); rc = bnxt_hwrm_vnic_cfg(bp, vnic); if (rc) break; diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index 18e7429..018113c 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -1592,8 +1592,7 @@ int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic) vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE; skip_ring_grps: - vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN + - RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE; + vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu); HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB); if (vnic->func_default) @@ -2954,9 +2953,7 @@ static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings) req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags); req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU); - req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN + - RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * - BNXT_NUM_VLANS); + req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu)); req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx); req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx); req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings); @@ -2995,9 +2992,7 @@ static void populate_vf_func_cfg_req(struct bnxt *bp, req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * BNXT_NUM_VLANS); - req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN + - RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * - BNXT_NUM_VLANS); + req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu)); req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx / (num_vfs + 1)); req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1)); From patchwork Thu Oct 24 05:58:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 61804 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7C7ED1C1AF; Thu, 24 Oct 2019 08:07:08 +0200 (CEST) Received: from relay.smtp.broadcom.com (unknown [192.19.211.62]) by dpdk.org (Postfix) with ESMTP id 8F52A1C025 for ; Thu, 24 Oct 2019 08:06:57 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (bgccx-dev-host-lnx35.bec.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id AFD9628FA75; Wed, 23 Oct 2019 23:06:56 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com AFD9628FA75 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1571897216; bh=ApFqlwh5C4EJOATQMNjmkgzp2qCBQeRa85ZedxLc4JI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CQi5+pXmmmtxc2o6n/Aw7mwu1iup9YduclB4ZSetr1BsYLyd3pRxx0f0o6e8p2Ai9 BdjDrQI9283s0wuKiAK55ncHofbl/j8MCtPO8efKgZYB4osGiAMQhaV5xRM7UAPAxB 8+5ZNzUioGtwAgSM/WQC6ai8YKR/DoT0cArLJjGw= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Thu, 24 Oct 2019 11:28:58 +0530 Message-Id: <20191024055913.28817-4-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20191024055913.28817-1-somnath.kotur@broadcom.com> References: <20191024055913.28817-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 03/16] net/bnxt: fix to set MAX RSS contexts for maximal reservation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ajit Khaparde Configure max RSS contexts in case the firmware indicates a maximal resource reservation strategy. Fixes: 6d8109bcb398 ("net/bnxt: check VF resources if resource manager is enabled) Signed-off-by: Ajit Khaparde Reviewed-by: Somnath Kotur Signed-off-by: Somnath Kotur --- drivers/net/bnxt/bnxt_hwrm.c | 4 ++++ drivers/net/bnxt/bnxt_hwrm.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index 018113c..ae26b30 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -859,6 +859,10 @@ int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test) req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX); req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX); req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC); + } else if (bp->vf_resv_strategy == + HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) + enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS; + req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx); } if (test) diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h index fcbce60..abe5de9 100644 --- a/drivers/net/bnxt/bnxt_hwrm.h +++ b/drivers/net/bnxt/bnxt_hwrm.h @@ -37,6 +37,8 @@ #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC \ HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC +#define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL \ + HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN \ HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED From patchwork Thu Oct 24 05:58:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 61805 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A299A1C1BE; Thu, 24 Oct 2019 08:07:10 +0200 (CEST) Received: from relay.smtp.broadcom.com (unknown [192.19.211.62]) by dpdk.org (Postfix) with ESMTP id D6C081C029 for ; Thu, 24 Oct 2019 08:06:57 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (bgccx-dev-host-lnx35.bec.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id 0A2E328FA89; Wed, 23 Oct 2019 23:06:56 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com 0A2E328FA89 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1571897217; bh=1BSm/yABxJfAaSxk2xekx0IARwnQnAt+UTPcCYOIMc8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=onmwIWZlqe0Yre00jxQ3RKyhC1GGau0b4sd2LPEowtr+gaY5ntbqt+Ukd2FzGsdOA 6hIIWv3egA+KdPgiD5W2lJAyX4De9jJhUItc/cF5xvZtcFt5wGT1Ky7yG3zThHKsMZ 1PTI55Rl8xiB3Jp0SeNcsYOBb6/Gq7CTVd9TM4HA= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Thu, 24 Oct 2019 11:28:59 +0530 Message-Id: <20191024055913.28817-5-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20191024055913.28817-1-somnath.kotur@broadcom.com> References: <20191024055913.28817-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 04/16] net/bnxt: fix to write the correct MTU to FW X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ajit Khaparde We are currently writing the MAX supported MTU size even though the MTU passed by the application is a different value. Configure the application specified MTU instead. Fixes: b7778e8a1c00 ("net/bnxt: refactor to properly allocate resources for PF/VF") Signed-off-by: Ajit Khaparde Reviewed-by: Somnath Kotur Signed-off-by: Somnath Kotur --- drivers/net/bnxt/bnxt_hwrm.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index ae26b30..c777c73 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -860,7 +860,7 @@ int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test) req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX); req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC); } else if (bp->vf_resv_strategy == - HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) + HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) { enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS; req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx); } @@ -2956,7 +2956,8 @@ static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings) } req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags); - req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU); + req.mtu = rte_cpu_to_le_16(RTE_MIN(bp->eth_dev->data->mtu, + BNXT_MAX_MTU)); //FW adds hdr sizes req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu)); req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx); req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx); From patchwork Thu Oct 24 05:59:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 61806 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C2EBA1C1D9; Thu, 24 Oct 2019 08:07:14 +0200 (CEST) Received: from relay.smtp.broadcom.com (unknown [192.19.211.62]) by dpdk.org (Postfix) with ESMTP id 408291C029 for ; Thu, 24 Oct 2019 08:06:58 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (bgccx-dev-host-lnx35.bec.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id 5791B28FA8A; Wed, 23 Oct 2019 23:06:57 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com 5791B28FA8A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1571897217; bh=a5f/NnGBKwFzFHH3y4Mrzk3tXNKYe+xCeBhs3ve5Yjs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OnIn2EjxxFzCkXgslm3AVZUMhPWxhRdvSE8DGMq/RX86QO3Q/L38J4Q8qLs4KAouG 106Yse9YbWP4sG5WSXHgxlBL3+PDgEm6Ycd/Mb5lNdjb34qAg9MImjc5wgy3nYhxCN MzpXBKpvT99vgJe8T6VyBuBX1Ky3J+P9BxTDzatU= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Thu, 24 Oct 2019 11:29:00 +0530 Message-Id: <20191024055913.28817-6-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20191024055913.28817-1-somnath.kotur@broadcom.com> References: <20191024055913.28817-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 05/16] net/bnxt: fix RSS configuration failure for thor-based controllers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Santoshkumar Karanappa Rastapur rss_table structure stores receive, completion ring IDs for Thor based controllers and receive queue id for others. Below commit accidentally left the old code and hence was always overwriting receive ring id with queue id for Thor. This causes subsequent VNIC_RSS_CFG command to fail. Fixes: 38412304b50a ("net/bnxt: enable RSS for thor-based controllers") Signed-off-by: Santoshkumar Karanappa Rastapur Reviewed-by: Kalesh Anakkur Purayil Reviewed-by: Lance Richardson Reviewed-by: Ajit Kumar Khaparde Signed-off-by: Somnath Kotur --- drivers/net/bnxt/bnxt_ethdev.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index c97fcac..ce3a03a 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -1322,9 +1322,6 @@ static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev, vnic->rss_table[i] = vnic->fw_grp_ids[reta_conf[idx].reta[sft]]; } - - vnic->rss_table[i] = - vnic->fw_grp_ids[reta_conf[idx].reta[sft]]; } bnxt_hwrm_vnic_rss_cfg(bp, vnic); From patchwork Thu Oct 24 05:59:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 61810 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5800D1C207; Thu, 24 Oct 2019 08:07:24 +0200 (CEST) Received: from relay.smtp.broadcom.com (unknown [192.19.211.62]) by dpdk.org (Postfix) with ESMTP id 6D9001C033 for ; Thu, 24 Oct 2019 08:06:58 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (bgccx-dev-host-lnx35.bec.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id AE4DC28FA8E; Wed, 23 Oct 2019 23:06:57 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com AE4DC28FA8E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1571897218; bh=cEsKsyMx48/KXFbEgbtAkISGZUJo9+E2cxBLA7ZlURE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cS4qgD7Qcsa7frSBmbttf28ZLWPsPvv9EPiXew1Xufly0QRaUc80JpB9Yop7NyPMI egA9dG3LCbrCByN6F0tMynY+s2eARTxASRdirNJSJs/n7ZUJojGpaOJw38g3cSW5DM 0Bsv4M3eZZSZ6QbOm38hNufT6oaeBMxAGlNVOqCI= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Thu, 24 Oct 2019 11:29:01 +0530 Message-Id: <20191024055913.28817-7-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20191024055913.28817-1-somnath.kotur@broadcom.com> References: <20191024055913.28817-1-somnath.kotur@broadcom.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 06/16] net/bnxt: update HWRM API to version 1.10.1.6 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ajit Khaparde Update HWRM API to version 1.10.1.6 Signed-off-by: Ajit Khaparde Reviewed-by: Kalesh Anakkur Purayil Signed-off-by: Somnath Kotur --- drivers/net/bnxt/hsi_struct_def_dpdk.h | 2273 +++++++++++++++++++++++++------- 1 file changed, 1818 insertions(+), 455 deletions(-) diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index c45d088..cb41768 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -80,16 +80,18 @@ struct hwrm_resp_hdr { #define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004) /* Engine CKV - The encrypted data. */ #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005) -/* Engine CKV - Supported algorithms. */ -#define TLV_TYPE_ENGINE_CKV_ALGORITHMS UINT32_C(0x8006) +/* Engine CKV - Supported host_algorithms. */ +#define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS UINT32_C(0x8006) /* Engine CKV - The Host EC curve name and ECC public key information. */ #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY UINT32_C(0x8007) /* Engine CKV - The ECDSA signature. */ #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008) -/* Engine CKV - The SRT EC curve name and ECC public key information. */ -#define TLV_TYPE_ENGINE_CKV_SRT_ECC_PUBLIC_KEY UINT32_C(0x8009) +/* Engine CKV - The firmware EC curve name and ECC public key information. */ +#define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY UINT32_C(0x8009) +/* Engine CKV - Supported firmware algorithms. */ +#define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS UINT32_C(0x800a) #define TLV_TYPE_LAST \ - TLV_TYPE_ENGINE_CKV_SRT_ECC_PUBLIC_KEY + TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS /* tlv (size:64b/8B) */ @@ -319,11 +321,8 @@ struct cmd_nums { #define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38) #define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39) #define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a) - /* Experimental */ #define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b) - /* Experimental */ #define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c) - /* Experimental */ #define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d) #define HWRM_VNIC_ALLOC UINT32_C(0x40) #define HWRM_VNIC_FREE UINT32_C(0x41) @@ -351,6 +350,9 @@ struct cmd_nums { #define HWRM_RESERVED6 UINT32_C(0x65) #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70) #define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71) + #define HWRM_QUEUE_MPLS_QCAPS UINT32_C(0x80) + #define HWRM_QUEUE_MPLSTC2PRI_QCFG UINT32_C(0x81) + #define HWRM_QUEUE_MPLSTC2PRI_CFG UINT32_C(0x82) #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90) #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91) #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92) @@ -382,11 +384,13 @@ struct cmd_nums { #define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4) #define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5) #define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6) + #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE UINT32_C(0xb7) + #define HWRM_PORT_PHY_MDIO_BUS_RELEASE UINT32_C(0xb8) #define HWRM_FW_RESET UINT32_C(0xc0) #define HWRM_FW_QSTATUS UINT32_C(0xc1) #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2) #define HWRM_FW_SYNC UINT32_C(0xc3) - #define HWRM_FW_STATE_BUFFER_QCAPS UINT32_C(0xc4) + #define HWRM_FW_STATE_QCAPS UINT32_C(0xc4) #define HWRM_FW_STATE_QUIESCE UINT32_C(0xc5) #define HWRM_FW_STATE_BACKUP UINT32_C(0xc6) #define HWRM_FW_STATE_RESTORE UINT32_C(0xc7) @@ -407,7 +411,14 @@ struct cmd_nums { #define HWRM_OEM_CMD UINT32_C(0xd4) /* Tells the fw to run PRBS test on a given port and lane. */ #define HWRM_PORT_PRBS_TEST UINT32_C(0xd5) + #define HWRM_PORT_SFP_SIDEBAND_CFG UINT32_C(0xd6) + #define HWRM_PORT_SFP_SIDEBAND_QCFG UINT32_C(0xd7) + #define HWRM_FW_STATE_UNQUIESCE UINT32_C(0xd8) + /* Tells the fw to collect dsc dump on a given port and lane. */ + #define HWRM_PORT_DSC_DUMP UINT32_C(0xd9) #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0) + #define HWRM_REG_POWER_QUERY UINT32_C(0xe1) + #define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2) #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0) #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1) #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2) @@ -561,6 +572,8 @@ struct cmd_nums { #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156) /* Engine - Query the statistics accumulator for an Engine. */ #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157) + /* Engine - Query statistics counters for continuous errors from all CDDIP Engines. */ + #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR UINT32_C(0x158) /* Engine - Allocate an Engine RQ. */ #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e) /* Engine - Free an Engine RQ. */ @@ -731,7 +744,7 @@ struct ret_codes { #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb) /* * This error code is only reported by the firmware when during - * flow allocation when a requeest for a flow counter fails because + * flow allocation when a request for a flow counter fails because * the number of flow counters are exhausted. */ #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc) @@ -753,10 +766,15 @@ struct ret_codes { */ #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf) /* + * Firmware is unable to service the request at the present time. Caller + * may try again later. + */ + #define HWRM_ERR_CODE_BUSY UINT32_C(0x10) + /* * This value indicates that the HWRM response is in TLV format and * should be interpreted as one or more TLVs starting with the - * hwrm_resp_hdr TLV. This value is not an indicatation of any error - * by itself, just an indicatation that the response should be parsed + * hwrm_resp_hdr TLV. This value is not an indication of any error + * by itself, just an indication that the response should be parsed * as TLV and the actual error code will be in the hwrm_resp_hdr TLV. */ #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000) @@ -837,10 +855,10 @@ struct hwrm_err_output { #define HWRM_TARGET_ID_TOOLS 0xFFFD #define HWRM_VERSION_MAJOR 1 #define HWRM_VERSION_MINOR 10 -#define HWRM_VERSION_UPDATE 0 +#define HWRM_VERSION_UPDATE 1 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 91 -#define HWRM_VERSION_STR "1.10.0.91" +#define HWRM_VERSION_RSVD 6 +#define HWRM_VERSION_STR "1.10.1.6" /**************** * hwrm_ver_get * @@ -1395,12 +1413,12 @@ struct bd_base { #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0) /* * Indicates that this BD is 1BB long and is an empty - * TX BD. Not valid for use by the driver. + * TX BD. Not valid for use by the driver. */ #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1) /* * Indicates that this BD is 16B long and is an RX Producer - * (ie. empty) buffer descriptor. + * (i.e. empty) buffer descriptor. */ #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4) /* @@ -1454,7 +1472,7 @@ struct tx_bd_short { #define TX_BD_SHORT_FLAGS_SFT 6 /* * If set to 1, the packet ends with the data in the buffer - * pointed to by this descriptor. This flag must be + * pointed to by this descriptor. This flag must be * valid on every BD. */ #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40) @@ -1472,9 +1490,9 @@ struct tx_bd_short { * This value indicates how many 16B BD locations are consumed * in the ring by this packet. * A value of 1 indicates that this BD is the only BD (and that - * the it is a short BD). A value + * it is a short BD). A value * of 3 indicates either 3 short BDs or 1 long BD and one short - * BD in the packet. A value of 0 indicates + * BD in the packet. A value of 0 indicates * that there are 32 BD locations in the packet (the maximum). * * This field is valid only on the first BD of a packet. @@ -1562,7 +1580,7 @@ struct tx_bd_long { #define TX_BD_LONG_FLAGS_SFT 6 /* * If set to 1, the packet ends with the data in the buffer - * pointed to by this descriptor. This flag must be + * pointed to by this descriptor. This flag must be * valid on every BD. */ #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40) @@ -1580,9 +1598,9 @@ struct tx_bd_long { * This value indicates how many 16B BD locations are consumed * in the ring by this packet. * A value of 1 indicates that this BD is the only BD (and that - * the it is a short BD). A value + * it is a short BD). A value * of 3 indicates either 3 short BDs or 1 long BD and one short - * BD in the packet. A value of 0 indicates + * BD in the packet. A value of 0 indicates * that there are 32 BD locations in the packet (the maximum). * * This field is valid only on the first BD of a packet. @@ -1663,7 +1681,7 @@ struct tx_bd_long_hi { */ #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1) /* - * If set to 1, the controller replaces the IP checksum of the + * If set to 1, the controller replaces the IP checksum of the * normal packets, or the inner IP checksum of the encapsulated * packets with the hardware calculated IP checksum for the * packet associated with this descriptor. @@ -1677,9 +1695,9 @@ struct tx_bd_long_hi { * * This bit must be valid on the first BD of a packet. * - * Packet must be 64B or longer when this flag is set. It is not + * Packet must be 64B or longer when this flag is set. It is not * useful to use this bit with any form of TX offload such as - * CSO or LSO. The intent is that the packet from the host already + * CSO or LSO. The intent is that the packet from the host already * has a valid Ethernet CRC on the packet. */ #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4) @@ -1708,9 +1726,9 @@ struct tx_bd_long_hi { */ #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10) /* - * If set to 1, the device will treat this packet with LSO(Large + * If set to 1, the device will treat this packet with LSO(Large * Send Offload) processing for both normal or encapsulated - * packets, which is a form of TCP segmentation. When this bit + * packets, which is a form of TCP segmentation. When this bit * is 1, the hdr_size and mss fields must be valid. The driver * doesn't need to set t_ip_chksum, ip_chksum, and tcp_udp_chksum * flags since the controller will replace the appropriate @@ -1743,19 +1761,19 @@ struct tx_bd_long_hi { #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80) /* * If set to '1', then the RoCE ICRC will be appended to the - * packet. Packet must be a valid RoCE format packet. + * packet. Packet must be a valid RoCE format packet. */ #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100) /* * If set to '1', then the FCoE CRC will be appended to the - * packet. Packet must be a valid FCoE format packet. + * packet. Packet must be a valid FCoE format packet. */ #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200) uint16_t hdr_size; /* * When LSO is '1', this field must contain the offset of the * TCP payload from the beginning of the packet in as - * 16b words. In case of encapsulated/tunneling packet, this field + * 16b words. In case of encapsulated/tunneling packet, this field * contains the offset of the inner TCP payload from beginning of the * packet as 16-bit words. * @@ -1862,7 +1880,7 @@ struct tx_bd_long_inline { #define TX_BD_LONG_INLINE_FLAGS_SFT 6 /* * If set to 1, the packet ends with the data in the buffer - * pointed to by this descriptor. This flag must be + * pointed to by this descriptor. This flag must be * valid on every BD. */ #define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40) @@ -1967,12 +1985,12 @@ struct tx_bd_long_inline { #define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80) /* * If set to '1', then the RoCE ICRC will be appended to the - * packet. Packet must be a valid RoCE format packet. + * packet. Packet must be a valid RoCE format packet. */ #define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100) /* * If set to '1', then the FCoE CRC will be appended to the - * packet. Packet must be a valid FCoE format packet. + * packet. Packet must be a valid FCoE format packet. */ #define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200) uint16_t unused2; @@ -2055,7 +2073,7 @@ struct tx_bd_empty { #define TX_BD_EMPTY_TYPE_SFT 0 /* * Indicates that this BD is 1BB long and is an empty - * TX BD. Not valid for use by the driver. + * TX BD. Not valid for use by the driver. */ #define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1) #define TX_BD_EMPTY_TYPE_LAST TX_BD_EMPTY_TYPE_TX_BD_EMPTY @@ -2074,7 +2092,7 @@ struct rx_prod_pkt_bd { #define RX_PROD_PKT_BD_TYPE_SFT 0 /* * Indicates that this BD is 16B long and is an RX Producer - * (ie. empty) buffer descriptor. + * (i.e. empty) buffer descriptor. */ #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4) #define RX_PROD_PKT_BD_TYPE_LAST \ @@ -2083,7 +2101,7 @@ struct rx_prod_pkt_bd { #define RX_PROD_PKT_BD_FLAGS_SFT 6 /* * If set to 1, the packet will be placed at the address plus - * 2B. The 2 Bytes of padding will be written as zero. + * 2B. The 2 Bytes of padding will be written as zero. */ #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40) /* @@ -2093,9 +2111,9 @@ struct rx_prod_pkt_bd { #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80) /* * This value is the number of additional buffers in the ring that - * describe the buffer space to be consumed for the this packet. + * describe the buffer space to be consumed for this packet. * If the value is zero, then the packet must fit within the - * space described by this BD. If this value is 1 or more, it + * space described by this BD. If this value is 1 or more, it * indicates how many additional "buffer" BDs are in the ring * immediately following this BD to be used for the same * network packet. @@ -2118,7 +2136,7 @@ struct rx_prod_pkt_bd { uint32_t opaque; /* * This is the host physical address where data for the packet may - * by placed in host memory. + * be placed in host memory. */ uint64_t address; } __attribute__((packed)); @@ -2147,7 +2165,7 @@ struct rx_prod_bfr_bd { uint32_t opaque; /* * This is the host physical address where data for the packet may - * by placed in host memory. + * be placed in host memory. */ uint64_t address; } __attribute__((packed)); @@ -2186,7 +2204,7 @@ struct rx_prod_agg_bd { uint32_t opaque; /* * This is the host physical address where data for the packet may - * by placed in host memory. + * be placed in host memory. */ uint64_t address; } __attribute__((packed)); @@ -2197,15 +2215,15 @@ struct cmpl_base { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f) #define CMPL_BASE_TYPE_SFT 0 /* * TX L2 completion: - * Completion of TX packet. Length = 16B + * Completion of TX packet. Length = 16B */ #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0) /* @@ -2216,7 +2234,7 @@ struct cmpl_base { /* * RX Aggregation Buffer completion : * Completion of an L2 aggregation buffer in support of - * TPA, HDS, or Jumbo packet completion. Length = 16B + * TPA, HDS, or Jumbo packet completion. Length = 16B */ #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12) /* @@ -2265,8 +2283,8 @@ struct cmpl_base { uint32_t info2; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ uint32_t info3_v; #define CMPL_BASE_V UINT32_C(0x1) @@ -2282,15 +2300,15 @@ struct tx_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define TX_CMPL_TYPE_MASK UINT32_C(0x3f) #define TX_CMPL_TYPE_SFT 0 /* * TX L2 completion: - * Completion of TX packet. Length = 16B + * Completion of TX packet. Length = 16B */ #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0) #define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2 @@ -2298,14 +2316,14 @@ struct tx_cmpl { #define TX_CMPL_FLAGS_SFT 6 /* * When this bit is '1', it indicates a packet that has an - * error of some type. Type of error is indicated in + * error of some type. Type of error is indicated in * error_flags. */ #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40) /* * When this bit is '1', it indicates that the packet completed * was transmitted using the push acceleration data provided - * by the driver. When this bit is '0', it indicates that the + * by the driver. When this bit is '0', it indicates that the * packet had not push acceleration data written or was executed * as a normal packet even though push data was provided. */ @@ -2320,8 +2338,8 @@ struct tx_cmpl { uint16_t errors_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define TX_CMPL_V UINT32_C(0x1) #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe) @@ -2343,7 +2361,7 @@ struct tx_cmpl { TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT /* * When this bit is '1', it indicates that the length of - * the packet was zero. No packet was transmitted. + * the packet was zero. No packet was transmitted. */ #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10) /* @@ -2360,7 +2378,7 @@ struct tx_cmpl { #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40) /* * When this bit is '1', it indicates that the packet was longer - * than indicated by the hint. No packet was transmitted. + * than indicated by the hint. No packet was transmitted. */ #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80) /* @@ -2381,8 +2399,8 @@ struct rx_pkt_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f) @@ -2397,7 +2415,7 @@ struct rx_pkt_cmpl { #define RX_PKT_CMPL_FLAGS_SFT 6 /* * When this bit is '1', it indicates a packet that has an - * error of some type. Type of error is indicated in + * error of some type. Type of error is indicated in * error_flags. */ #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40) @@ -2498,9 +2516,9 @@ struct rx_pkt_cmpl { RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP /* * This is the length of the data for the packet stored in the - * buffer(s) identified by the opaque value. This includes - * the packet BD and any associated buffer BDs. This does not include - * the the length of any data places in aggregation BDs. + * buffer(s) identified by the opaque value. This includes + * the packet BD and any associated buffer BDs. This does not include + * the length of any data places in aggregation BDs. */ uint16_t len; /* @@ -2511,8 +2529,8 @@ struct rx_pkt_cmpl { uint8_t agg_bufs_v1; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define RX_PKT_CMPL_V1 UINT32_C(0x1) /* @@ -2527,7 +2545,7 @@ struct rx_pkt_cmpl { #define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0) #define RX_PKT_CMPL_UNUSED1_SFT 6 /* - * This is the RSS hash type for the packet. The value is packed + * This is the RSS hash type for the packet. The value is packed * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. * * The value of tuple_extrac_op provides the information about @@ -2558,7 +2576,7 @@ struct rx_pkt_cmpl { uint8_t rss_hash_type; /* * This value indicates the offset in bytes from the beginning of the packet - * where the inner payload starts. This value is valid for TCP, UDP, + * where the inner payload starts. This value is valid for TCP, UDP, * FCoE, and RoCE packets. * * A value of zero indicates that header is 256B into the packet. @@ -2604,7 +2622,7 @@ struct rx_pkt_cmpl_hi { /* This value indicates what format the metadata field is. */ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0) #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4 - /* No metadata informtaion. Value is zero. */ + /* No metadata information. Value is zero. */ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \ (UINT32_C(0x0) << 4) /* @@ -2623,7 +2641,7 @@ struct rx_pkt_cmpl_hi { * - VXLAN = VNI[23:0] -> VXLAN Network ID * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier. * - NVGRE = TNI[23:0] -> Tenant Network ID - * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0 + * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0 * - IPV4 = 0 (not populated) * - IPV6 = Flow Label[19:0] * - PPPoE = sessionID[15:0] @@ -2653,7 +2671,7 @@ struct rx_pkt_cmpl_hi { RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET /* * This field indicates the IP type for the inner-most IP header. - * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + * A value of '0' indicates IPv4. A value of '1' indicates IPv6. * This value is only valid if itype indicates a packet * with an IP header. */ @@ -2697,8 +2715,8 @@ struct rx_pkt_cmpl_hi { uint16_t errors_v2; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define RX_PKT_CMPL_V2 \ UINT32_C(0x1) @@ -2708,7 +2726,7 @@ struct rx_pkt_cmpl_hi { /* * This error indicates that there was some sort of problem with * the BDs for the packet that was found after part of the - * packet was already placed. The packet should be treated as + * packet was already placed. The packet should be treated as * invalid. */ #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK \ @@ -2721,7 +2739,7 @@ struct rx_pkt_cmpl_hi { * Did Not Fit: * Packet did not fit into packet buffer provided. * For regular placement, this means the packet did not fit - * in the buffer provided. For HDS and jumbo placement, this + * in the buffer provided. For HDS and jumbo placement, this * means that the packet could not be placed into 7 physical * buffers or less. */ @@ -2774,7 +2792,7 @@ struct rx_pkt_cmpl_hi { UINT32_C(0x80) /* * This indicates that there was a CRC error on either an FCoE - * or RoCE packet. The itype indicates the packet type. + * or RoCE packet. The itype indicates the packet type. */ #define RX_PKT_CMPL_ERRORS_CRC_ERROR \ UINT32_C(0x100) @@ -2912,7 +2930,7 @@ struct rx_pkt_cmpl_hi { * This value holds the reordering sequence number for the packet. * If the reordering sequence is not valid, then this value is zero. * The reordering domain for the packet is in the bottom 8 to 10b of - * the rss_hash value. The bottom 20b of this value contain the + * the rss_hash value. The bottom 20b of this value contain the * ordering domain value for the packet. */ #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff) @@ -2929,8 +2947,8 @@ struct rx_tpa_start_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f) @@ -2952,9 +2970,9 @@ struct rx_tpa_start_cmpl { #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7 /* * Jumbo: - * TPA Packet was placed using jumbo algorithm. This means + * TPA Packet was placed using jumbo algorithm. This means * that the first buffer will be filled with data before - * moving to aggregation buffers. Each aggregation buffer + * moving to aggregation buffers. Each aggregation buffer * will be filled before moving to the next aggregation * buffer. */ @@ -3020,19 +3038,19 @@ struct rx_tpa_start_cmpl { uint32_t opaque; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ uint8_t v1; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define RX_TPA_START_CMPL_V1 UINT32_C(0x1) #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1 /* - * This is the RSS hash type for the packet. The value is packed + * This is the RSS hash type for the packet. The value is packed * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. * * The value of tuple_extrac_op provides the information about @@ -3063,7 +3081,7 @@ struct rx_tpa_start_cmpl { uint8_t rss_hash_type; /* * This is the aggregation ID that the completion is associated - * with. Use this number to correlate the TPA start completion + * with. Use this number to correlate the TPA start completion * with the TPA end completion. */ uint16_t agg_id; @@ -3072,7 +3090,7 @@ struct rx_tpa_start_cmpl { #define RX_TPA_START_CMPL_UNUSED2_SFT 0 /* * This is the aggregation ID that the completion is associated - * with. Use this number to correlate the TPA start completion + * with. Use this number to correlate the TPA start completion * with the TPA end completion. */ #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00) @@ -3120,7 +3138,7 @@ struct rx_tpa_start_cmpl_hi { /* This value indicates what format the metadata field is. */ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0) #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4 - /* No metadata information. Value is zero. */ + /* No metadata information. Value is zero. */ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \ (UINT32_C(0x0) << 4) /* @@ -3136,7 +3154,7 @@ struct rx_tpa_start_cmpl_hi { RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN /* * This field indicates the IP type for the inner-most IP header. - * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + * A value of '0' indicates IPv4. A value of '1' indicates IPv6. */ #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100) /* @@ -3158,8 +3176,8 @@ struct rx_tpa_start_cmpl_hi { uint16_t v2; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define RX_TPA_START_CMPL_V2 UINT32_C(0x1) /* @@ -3175,7 +3193,7 @@ struct rx_tpa_start_cmpl_hi { uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset; /* * This is the offset from the beginning of the packet in bytes for - * the outer L3 header. If there is no outer L3 header, then this + * the outer L3 header. If there is no outer L3 header, then this * value is zero. */ #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff) @@ -3211,8 +3229,8 @@ struct rx_tpa_end_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f) @@ -3229,7 +3247,7 @@ struct rx_tpa_end_cmpl { #define RX_TPA_END_CMPL_FLAGS_SFT 6 /* * When this bit is '1', it indicates a packet that has an - * error of some type. Type of error is indicated in + * error of some type. Type of error is indicated in * error_flags. */ #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40) @@ -3238,9 +3256,9 @@ struct rx_tpa_end_cmpl { #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7 /* * Jumbo: - * TPA Packet was placed using jumbo algorithm. This means + * TPA Packet was placed using jumbo algorithm. This means * that the first buffer will be filled with data before - * moving to aggregation buffers. Each aggregation buffer + * moving to aggregation buffers. Each aggregation buffer * will be filled before moving to the next aggregation * buffer. */ @@ -3283,7 +3301,7 @@ struct rx_tpa_end_cmpl { * This value indicates what the inner packet determined for the * packet was. * - 2 TCP Packet - * Indicates that the packet was IP and TCP. This indicates + * Indicates that the packet was IP and TCP. This indicates * that the ip_cs field is valid and that the tcp_udp_cs * field is valid and contains the TCP checksum. * This also indicates that the payload_offset field is valid. @@ -3303,14 +3321,14 @@ struct rx_tpa_end_cmpl { uint32_t opaque; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ uint8_t agg_bufs_v1; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define RX_TPA_END_CMPL_V1 UINT32_C(0x1) /* @@ -3326,7 +3344,7 @@ struct rx_tpa_end_cmpl { uint8_t tpa_segs; /* * This value indicates the offset in bytes from the beginning of the packet - * where the inner payload starts. This value is valid for TCP, UDP, + * where the inner payload starts. This value is valid for TCP, UDP, * FCoE, and RoCE packets. * * A value of zero indicates an offset of 256 bytes. @@ -3337,7 +3355,7 @@ struct rx_tpa_end_cmpl { #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1) /* * This is the aggregation ID that the completion is associated - * with. Use this number to correlate the TPA start completion + * with. Use this number to correlate the TPA start completion * with the TPA end completion. */ #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe) @@ -3351,8 +3369,8 @@ struct rx_tpa_end_cmpl { * For GRO packets, this field is zero except for the following * sub-fields. * - tsdelta[31] - * Timestamp present indication. When '0', no Timestamp - * option is in the packet. When '1', then a Timestamp + * Timestamp present indication. When '0', no Timestamp + * option is in the packet. When '1', then a Timestamp * option is present in the packet. */ uint32_t tsdelta; @@ -3374,13 +3392,13 @@ struct rx_tpa_end_cmpl_hi { #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf) #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0 /* - * This value is the valid when TPA completion is active. It + * This value is the valid when TPA completion is active. It * indicates the length of the longest segment of the TPA operation * for LRO mode and the length of the first segment in GRO mode. * * This value may be used by GRO software to re-construct the original - * packet stream from the TPA packet. This is the length of all - * but the last segment for GRO. In LRO mode this value may be used + * packet stream from the TPA packet. This is the length of all + * but the last segment for GRO. In LRO mode this value may be used * to indicate MSS size to the stack. */ uint16_t tpa_seg_len; @@ -3389,8 +3407,8 @@ struct rx_tpa_end_cmpl_hi { uint16_t errors_v2; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define RX_TPA_END_CMPL_V2 UINT32_C(0x1) #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe) @@ -3398,14 +3416,14 @@ struct rx_tpa_end_cmpl_hi { /* * This error indicates that there was some sort of problem with * the BDs for the packet that was found after part of the - * packet was already placed. The packet should be treated as + * packet was already placed. The packet should be treated as * invalid. */ #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1 /* * This error occurs when there is a fatal HW problem in - * the chip only. It indicates that there were not + * the chip only. It indicates that there were not * BDs on chip but that there was adequate reservation. * provided by the TPA block. */ @@ -3414,7 +3432,7 @@ struct rx_tpa_end_cmpl_hi { /* * This error occurs when TPA block was not configured to * reserve adequate BDs for TPA operations on this RX - * ring. All data for the TPA operation was not placed. + * ring. All data for the TPA operation was not placed. * * This error can also be generated when the number of * segments is not programmed correctly in TPA and the @@ -3444,8 +3462,8 @@ struct rx_tpa_v2_start_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define RX_TPA_V2_START_CMPL_TYPE_MASK \ @@ -3472,9 +3490,9 @@ struct rx_tpa_v2_start_cmpl { #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_SFT 7 /* * Jumbo: - * TPA Packet was placed using jumbo algorithm. This means + * TPA Packet was placed using jumbo algorithm. This means * that the first buffer will be filled with data before - * moving to aggregation buffers. Each aggregation buffer + * moving to aggregation buffers. Each aggregation buffer * will be filled before moving to the next aggregation * buffer. */ @@ -3551,19 +3569,19 @@ struct rx_tpa_v2_start_cmpl { uint32_t opaque; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ uint8_t v1; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define RX_TPA_V2_START_CMPL_V1 UINT32_C(0x1) #define RX_TPA_V2_START_CMPL_LAST RX_TPA_V2_START_CMPL_V1 /* - * This is the RSS hash type for the packet. The value is packed + * This is the RSS hash type for the packet. The value is packed * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. * * The value of tuple_extrac_op provides the information about @@ -3594,7 +3612,7 @@ struct rx_tpa_v2_start_cmpl { uint8_t rss_hash_type; /* * This is the aggregation ID that the completion is associated - * with. Use this number to correlate the TPA start completion + * with. Use this number to correlate the TPA start completion * with the TPA end completion. */ uint16_t agg_id; @@ -3646,7 +3664,7 @@ struct rx_tpa_v2_start_cmpl_hi { #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK \ UINT32_C(0xf0) #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_SFT 4 - /* No metadata informtaion. Value is zero. */ + /* No metadata informtaion. Value is zero. */ #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE \ (UINT32_C(0x0) << 4) /* @@ -3695,7 +3713,7 @@ struct rx_tpa_v2_start_cmpl_hi { RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET /* * This field indicates the IP type for the inner-most IP header. - * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + * A value of '0' indicates IPv4. A value of '1' indicates IPv6. */ #define RX_TPA_V2_START_CMPL_FLAGS2_IP_TYPE \ UINT32_C(0x100) @@ -3742,8 +3760,8 @@ struct rx_tpa_v2_start_cmpl_hi { uint16_t errors_v2; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define RX_TPA_V2_START_CMPL_V2 \ UINT32_C(0x1) @@ -3753,7 +3771,7 @@ struct rx_tpa_v2_start_cmpl_hi { /* * This error indicates that there was some sort of problem with * the BDs for the packet that was found after part of the - * packet was already placed. The packet should be treated as + * packet was already placed. The packet should be treated as * invalid. */ #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_MASK \ @@ -3794,7 +3812,7 @@ struct rx_tpa_v2_start_cmpl_hi { uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset; /* * This is the offset from the beginning of the packet in bytes for - * the outer L3 header. If there is no outer L3 header, then this + * the outer L3 header. If there is no outer L3 header, then this * value is zero. */ #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff) @@ -3830,8 +3848,8 @@ struct rx_tpa_v2_end_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define RX_TPA_V2_END_CMPL_TYPE_MASK UINT32_C(0x3f) @@ -3848,7 +3866,7 @@ struct rx_tpa_v2_end_cmpl { #define RX_TPA_V2_END_CMPL_FLAGS_SFT 6 /* * When this bit is '1', it indicates a packet that has an - * error of some type. Type of error is indicated in + * error of some type. Type of error is indicated in * error_flags. */ #define RX_TPA_V2_END_CMPL_FLAGS_ERROR UINT32_C(0x40) @@ -3857,9 +3875,9 @@ struct rx_tpa_v2_end_cmpl { #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT 7 /* * Jumbo: - * TPA Packet was placed using jumbo algorithm. This means + * TPA Packet was placed using jumbo algorithm. This means * that the first buffer will be filled with data before - * moving to aggregation buffers. Each aggregation buffer + * moving to aggregation buffers. Each aggregation buffer * will be filled before moving to the next aggregation * buffer. */ @@ -3902,7 +3920,7 @@ struct rx_tpa_v2_end_cmpl { * This value indicates what the inner packet determined for the * packet was. * - 2 TCP Packet - * Indicates that the packet was IP and TCP. This indicates + * Indicates that the packet was IP and TCP. This indicates * that the ip_cs field is valid and that the tcp_udp_cs * field is valid and contains the TCP checksum. * This also indicates that the payload_offset field is valid. @@ -3923,15 +3941,15 @@ struct rx_tpa_v2_end_cmpl { uint8_t v1; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define RX_TPA_V2_END_CMPL_V1 UINT32_C(0x1) /* This value is the number of segments in the TPA operation. */ uint8_t tpa_segs; /* * This is the aggregation ID that the completion is associated - * with. Use this number to correlate the TPA start completion + * with. Use this number to correlate the TPA start completion * with the TPA end completion. */ uint16_t agg_id; @@ -3944,8 +3962,8 @@ struct rx_tpa_v2_end_cmpl { * For GRO packets, this field is zero except for the following * sub-fields. * - tsdelta[31] - * Timestamp present indication. When '0', no Timestamp - * option is in the packet. When '1', then a Timestamp + * Timestamp present indication. When '0', no Timestamp + * option is in the packet. When '1', then a Timestamp * option is present in the packet. */ uint32_t tsdelta; @@ -3986,13 +4004,13 @@ struct rx_tpa_v2_end_cmpl_hi { */ uint8_t tpa_agg_bufs; /* - * This value is the valid when TPA completion is active. It + * This value is the valid when TPA completion is active. It * indicates the length of the longest segment of the TPA operation * for LRO mode and the length of the first segment in GRO mode. * * This value may be used by GRO software to re-construct the original - * packet stream from the TPA packet. This is the length of all - * but the last segment for GRO. In LRO mode this value may be used + * packet stream from the TPA packet. This is the length of all + * but the last segment for GRO. In LRO mode this value may be used * to indicate MSS size to the stack. */ uint16_t tpa_seg_len; @@ -4000,8 +4018,8 @@ struct rx_tpa_v2_end_cmpl_hi { uint16_t errors_v2; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define RX_TPA_V2_END_CMPL_V2 UINT32_C(0x1) #define RX_TPA_V2_END_CMPL_ERRORS_MASK \ @@ -4010,7 +4028,7 @@ struct rx_tpa_v2_end_cmpl_hi { /* * This error indicates that there was some sort of problem with * the BDs for the packet that was found after part of the - * packet was already placed. The packet should be treated as + * packet was already placed. The packet should be treated as * invalid. */ #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_MASK \ @@ -4021,7 +4039,7 @@ struct rx_tpa_v2_end_cmpl_hi { (UINT32_C(0x0) << 1) /* * This error occurs when there is a fatal HW problem in - * the chip only. It indicates that there were not + * the chip only. It indicates that there were not * BDs on chip but that there was adequate reservation. * provided by the TPA block. */ @@ -4036,7 +4054,7 @@ struct rx_tpa_v2_end_cmpl_hi { /* * This error occurs when TPA block was not configured to * reserve adequate BDs for TPA operations on this RX - * ring. All data for the TPA operation was not placed. + * ring. All data for the TPA operation was not placed. * * This error can also be generated when the number of * segments is not programmed correctly in TPA and the @@ -4071,8 +4089,8 @@ struct rx_tpa_v2_abuf_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define RX_TPA_V2_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f) @@ -4080,17 +4098,17 @@ struct rx_tpa_v2_abuf_cmpl { /* * RX TPA Aggregation Buffer completion : * Completion of an L2 aggregation buffer in support of - * TPA packet completion. Length = 16B + * TPA packet completion. Length = 16B */ #define RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG UINT32_C(0x16) #define RX_TPA_V2_ABUF_CMPL_TYPE_LAST \ RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG /* * This is the length of the data for the packet stored in this - * aggregation buffer identified by the opaque value. This does not + * aggregation buffer identified by the opaque value. This does not * include the length of any * data placed in other aggregation BDs or in the packet or buffer - * BDs. This length does not include any space added due to + * BDs. This length does not include any space added due to * hdr_offset register during HDS placement mode. */ uint16_t len; @@ -4102,8 +4120,8 @@ struct rx_tpa_v2_abuf_cmpl { uint16_t v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define RX_TPA_V2_ABUF_CMPL_V UINT32_C(0x1) /* @@ -4121,8 +4139,8 @@ struct rx_abuf_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f) @@ -4130,16 +4148,16 @@ struct rx_abuf_cmpl { /* * RX Aggregation Buffer completion : * Completion of an L2 aggregation buffer in support of - * TPA, HDS, or Jumbo packet completion. Length = 16B + * TPA, HDS, or Jumbo packet completion. Length = 16B */ #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12) #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG /* * This is the length of the data for the packet stored in this - * aggregation buffer identified by the opaque value. This does not + * aggregation buffer identified by the opaque value. This does not * include the length of any * data placed in other aggregation BDs or in the packet or buffer - * BDs. This length does not include any space added due to + * BDs. This length does not include any space added due to * hdr_offset register during HDS placement mode. */ uint16_t len; @@ -4151,8 +4169,8 @@ struct rx_abuf_cmpl { uint32_t v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define RX_ABUF_CMPL_V UINT32_C(0x1) /* unused3 is 32 b */ @@ -4165,8 +4183,8 @@ struct eject_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f) @@ -4182,7 +4200,7 @@ struct eject_cmpl { #define EJECT_CMPL_FLAGS_SFT 6 /* * When this bit is '1', it indicates a packet that has an - * error of some type. Type of error is indicated in + * error of some type. Type of error is indicated in * error_flags. */ #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40) @@ -4199,8 +4217,8 @@ struct eject_cmpl { uint16_t v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define EJECT_CMPL_V UINT32_C(0x1) #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe) @@ -4247,8 +4265,8 @@ struct hwrm_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f) @@ -4266,8 +4284,8 @@ struct hwrm_cmpl { uint32_t v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_CMPL_V UINT32_C(0x1) /* unused4 is 32 b */ @@ -4279,16 +4297,16 @@ struct hwrm_fwd_req_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ uint16_t req_len_type; /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f) @@ -4314,8 +4332,8 @@ struct hwrm_fwd_req_cmpl { uint32_t req_buf_addr_v[2]; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1) /* Address of forwarded request. */ @@ -4329,8 +4347,8 @@ struct hwrm_fwd_resp_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f) @@ -4355,8 +4373,8 @@ struct hwrm_fwd_resp_cmpl { uint32_t resp_buf_addr_v[2]; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1) /* Address of forwarded request. */ @@ -4370,8 +4388,8 @@ struct hwrm_async_event_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f) @@ -4497,6 +4515,12 @@ struct hwrm_async_event_cmpl { #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \ UINT32_C(0x3e) /* + * An event signifying completion for HWRM_FW_STATE_QUIESCE + * (completion, timeout, or error) + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE \ + UINT32_C(0x3f) + /* * A trace log message. This contains firmware trace logs string * embedded in the asynchronous message. This is an experimental * event, not meant for production use at this time. @@ -4513,8 +4537,8 @@ struct hwrm_async_event_cmpl { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1) /* opaque is 7 b */ @@ -4534,8 +4558,8 @@ struct hwrm_async_event_cmpl_link_status_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \ @@ -4558,8 +4582,8 @@ struct hwrm_async_event_cmpl_link_status_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \ UINT32_C(0x1) @@ -4613,8 +4637,8 @@ struct hwrm_async_event_cmpl_link_mtu_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \ @@ -4637,8 +4661,8 @@ struct hwrm_async_event_cmpl_link_mtu_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1) /* opaque is 7 b */ @@ -4663,8 +4687,8 @@ struct hwrm_async_event_cmpl_link_speed_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \ @@ -4687,8 +4711,8 @@ struct hwrm_async_event_cmpl_link_speed_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \ UINT32_C(0x1) @@ -4758,8 +4782,8 @@ struct hwrm_async_event_cmpl_dcb_config_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \ @@ -4791,8 +4815,8 @@ struct hwrm_async_event_cmpl_dcb_config_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \ UINT32_C(0x1) @@ -4839,8 +4863,8 @@ struct hwrm_async_event_cmpl_port_conn_not_allowed { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \ @@ -4864,8 +4888,8 @@ struct hwrm_async_event_cmpl_port_conn_not_allowed { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \ UINT32_C(0x1) @@ -4915,8 +4939,8 @@ struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \ @@ -4940,8 +4964,8 @@ struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \ UINT32_C(0x1) @@ -4968,8 +4992,8 @@ struct hwrm_async_event_cmpl_link_speed_cfg_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \ @@ -4993,8 +5017,8 @@ struct hwrm_async_event_cmpl_link_speed_cfg_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \ UINT32_C(0x1) @@ -5037,8 +5061,8 @@ struct hwrm_async_event_cmpl_port_phy_cfg_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \ @@ -5062,8 +5086,8 @@ struct hwrm_async_event_cmpl_port_phy_cfg_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \ UINT32_C(0x1) @@ -5113,8 +5137,8 @@ struct hwrm_async_event_cmpl_reset_notify { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \ @@ -5137,8 +5161,8 @@ struct hwrm_async_event_cmpl_reset_notify { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1) /* opaque is 7 b */ @@ -5213,8 +5237,8 @@ struct hwrm_async_event_cmpl_error_recovery { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \ @@ -5242,8 +5266,8 @@ struct hwrm_async_event_cmpl_error_recovery { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1) /* opaque is 7 b */ @@ -5282,8 +5306,8 @@ struct hwrm_async_event_cmpl_func_drvr_unload { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \ @@ -5306,8 +5330,8 @@ struct hwrm_async_event_cmpl_func_drvr_unload { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1) /* opaque is 7 b */ @@ -5333,8 +5357,8 @@ struct hwrm_async_event_cmpl_func_drvr_load { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \ @@ -5357,8 +5381,8 @@ struct hwrm_async_event_cmpl_func_drvr_load { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1) /* opaque is 7 b */ @@ -5382,8 +5406,8 @@ struct hwrm_async_event_cmpl_func_flr_proc_cmplt { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \ @@ -5407,8 +5431,8 @@ struct hwrm_async_event_cmpl_func_flr_proc_cmplt { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \ UINT32_C(0x1) @@ -5435,8 +5459,8 @@ struct hwrm_async_event_cmpl_pf_drvr_unload { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \ @@ -5459,8 +5483,8 @@ struct hwrm_async_event_cmpl_pf_drvr_unload { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1) /* opaque is 7 b */ @@ -5488,8 +5512,8 @@ struct hwrm_async_event_cmpl_pf_drvr_load { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \ @@ -5512,8 +5536,8 @@ struct hwrm_async_event_cmpl_pf_drvr_load { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1) /* opaque is 7 b */ @@ -5541,8 +5565,8 @@ struct hwrm_async_event_cmpl_vf_flr { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \ @@ -5564,8 +5588,8 @@ struct hwrm_async_event_cmpl_vf_flr { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1) /* opaque is 7 b */ @@ -5593,8 +5617,8 @@ struct hwrm_async_event_cmpl_vf_mac_addr_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \ @@ -5617,8 +5641,8 @@ struct hwrm_async_event_cmpl_vf_mac_addr_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \ UINT32_C(0x1) @@ -5645,8 +5669,8 @@ struct hwrm_async_event_cmpl_pf_vf_comm_status_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \ @@ -5670,8 +5694,8 @@ struct hwrm_async_event_cmpl_pf_vf_comm_status_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \ UINT32_C(0x1) @@ -5701,8 +5725,8 @@ struct hwrm_async_event_cmpl_vf_cfg_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \ @@ -5725,8 +5749,8 @@ struct hwrm_async_event_cmpl_vf_cfg_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1) /* opaque is 7 b */ @@ -5786,8 +5810,8 @@ struct hwrm_async_event_cmpl_llfc_pfc_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \ @@ -5814,8 +5838,8 @@ struct hwrm_async_event_cmpl_llfc_pfc_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1) /* opaque is 7 b */ @@ -5865,8 +5889,8 @@ struct hwrm_async_event_cmpl_default_vnic_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \ @@ -5885,7 +5909,7 @@ struct hwrm_async_event_cmpl_default_vnic_change { 6 /* Identifiers of events. */ uint16_t event_id; - /* Notification of a default vnic allocaiton or free */ + /* Notification of a default vnic allocation or free */ #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \ UINT32_C(0x35) #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \ @@ -5895,8 +5919,8 @@ struct hwrm_async_event_cmpl_default_vnic_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \ UINT32_C(0x1) @@ -5947,8 +5971,8 @@ struct hwrm_async_event_cmpl_hw_flow_aged { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \ @@ -5971,8 +5995,8 @@ struct hwrm_async_event_cmpl_hw_flow_aged { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1) /* opaque is 7 b */ @@ -6014,8 +6038,8 @@ struct hwrm_async_event_cmpl_eem_cache_flush_req { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \ @@ -6039,8 +6063,8 @@ struct hwrm_async_event_cmpl_eem_cache_flush_req { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \ UINT32_C(0x1) @@ -6062,8 +6086,8 @@ struct hwrm_async_event_cmpl_eem_cache_flush_done { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \ @@ -6090,8 +6114,8 @@ struct hwrm_async_event_cmpl_eem_cache_flush_done { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \ UINT32_C(0x1) @@ -6118,8 +6142,8 @@ struct hwrm_async_event_cmpl_tcp_flag_action_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \ @@ -6143,8 +6167,8 @@ struct hwrm_async_event_cmpl_tcp_flag_action_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \ UINT32_C(0x1) @@ -6166,8 +6190,8 @@ struct hwrm_async_event_cmpl_eem_flow_active { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \ @@ -6209,8 +6233,8 @@ struct hwrm_async_event_cmpl_eem_flow_active { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1) /* opaque is 7 b */ @@ -6266,8 +6290,8 @@ struct hwrm_async_event_cmpl_eem_cfg_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \ @@ -6290,8 +6314,8 @@ struct hwrm_async_event_cmpl_eem_cfg_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1) /* opaque is 7 b */ @@ -6317,14 +6341,87 @@ struct hwrm_async_event_cmpl_eem_cfg_change { UINT32_C(0x2) } __attribute__((packed)); +/* hwrm_async_event_cmpl_quiesce_done (size:128b/16B) */ +struct hwrm_async_event_cmpl_quiesce_done { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* An event signifying completion of HWRM_FW_STATE_QUIESCE */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE + /* Event specific data */ + uint32_t event_data2; + /* Status of HWRM_FW_STATE_QUIESCE completion */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SFT \ + 0 + /* + * The quiesce operation started by HWRM_FW_STATE_QUIESCE + * completed successfully. + */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SUCCESS \ + UINT32_C(0x0) + /* + * The quiesce operation started by HWRM_FW_STATE_QUIESCE timed + * out. + */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_TIMEOUT \ + UINT32_C(0x1) + /* + * The quiesce operation started by HWRM_FW_STATE_QUIESCE + * encountered an error. + */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR \ + UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_LAST \ + HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Time stamp for error event */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA1_TIMESTAMP \ + UINT32_C(0x1) +} __attribute__((packed)); + /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */ struct hwrm_async_event_cmpl_fw_trace_msg { uint16_t type; /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \ @@ -6363,8 +6460,8 @@ struct hwrm_async_event_cmpl_fw_trace_msg { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1) /* opaque is 7 b */ @@ -6430,8 +6527,8 @@ struct hwrm_async_event_cmpl_hwrm_error { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \ @@ -6469,8 +6566,8 @@ struct hwrm_async_event_cmpl_hwrm_error { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1) /* opaque is 7 b */ @@ -7336,6 +7433,15 @@ struct hwrm_func_qcaps_output { #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD \ UINT32_C(0x2000000) /* + * If the query is for a VF, then this flag (always set to 0) shall + * be ignored. If this query is for a PF and this flag is set to 1, + * host, when registered for the default vnic change async event, + * receives async notification whenever a default vnic state is + * changed for any of child or adopted VFs. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED \ + UINT32_C(0x4000000) + /* * This value is current MAC address configured for this * function. A value of 00-00-00-00-00-00 indicates no * MAC address is currently configured. @@ -7905,7 +8011,12 @@ struct hwrm_func_qcfg_output { * after receiving the RESET Notify event. */ uint32_t reset_addr_poll; - uint8_t unused_2[3]; + /* + * This field specifies legacy L2 doorbell size in KBytes. Drivers should use + * this value to find out the doorbell page offset from the BAR. + */ + uint16_t legacy_l2_db_size_kb; + uint8_t unused_2[1]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -8606,9 +8717,22 @@ struct hwrm_func_qstats_input { * Function ID of the function that is being queried. * 0xFF... (All Fs) if the query is for the requesting * function. + * A privileged PF can query for other function's statistics. */ uint16_t fid; - uint8_t unused_0[6]; + /* This flags indicates the type of statistics request. */ + uint8_t flags; + /* This value is not used to avoid backward compatibility issues. */ + #define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0) + /* + * flags should be set to 1 when request is for only RoCE statistics. + * This will be honored only if the caller_fid is a privileged PF. + * In all other cases FID and caller_fid should be the same. + */ + #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1) + #define HWRM_FUNC_QSTATS_INPUT_FLAGS_LAST \ + HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY + uint8_t unused_0[5]; } __attribute__((packed)); /* hwrm_func_qstats_output (size:1408b/176B) */ @@ -8928,12 +9052,11 @@ struct hwrm_func_drv_rgtr_input { UINT32_C(0x20) /* * When this bit is 1, the function is indicating the support of the - * Master capability. The Firmware will use this capability to select - * the Master function. The master function will be used to initiate - * designated functionality like error recovery etc. If none of the - * registered PFs or trusted VFs indicate this support, then - * firmware will select the 1st registered PF as Master capable - * instance. + * Master capability. The Firmware will use this capability to select the + * Master function. The master function will be used to initiate + * designated functionality like error recovery etc… If none of the + * registered PF’s or trusted VF’s indicate this support, then + * firmware will select the 1st registered PF as Master capable instance. */ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT \ UINT32_C(0x40) @@ -9621,7 +9744,7 @@ struct hwrm_func_backing_store_qcaps_input { uint64_t resp_addr; } __attribute__((packed)); -/* hwrm_func_backing_store_qcaps_output (size:576b/72B) */ +/* hwrm_func_backing_store_qcaps_output (size:640b/80B) */ struct hwrm_func_backing_store_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -9729,6 +9852,19 @@ struct hwrm_func_backing_store_qcaps_output { */ uint8_t tqm_entries_multiple; /* + * Initializer to be used by drivers + * to initialize context memory to ensure + * context subsystem flags an error for an attack + * before the first time context load. + */ + uint8_t ctx_kind_initializer; + /* Reserved for future. */ + uint32_t rsvd; + /* Reserved for future. */ + uint16_t rsvd1; + /* Reserved for future. */ + uint8_t rsvd2; + /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. @@ -13369,7 +13505,7 @@ struct hwrm_port_phy_cfg_input { #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2) /* * The HW will be configured with external loopback such that - * host data is sent on the trasmitter and based on the external + * host data is sent on the transmitter and based on the external * loopback connection the data will be received without modification. */ #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3) @@ -13431,7 +13567,7 @@ struct hwrm_port_phy_cfg_input { UINT32_C(0x40) uint8_t unused_2[2]; /* - * Reuested setting of TX LPI timer in microseconds. + * Requested setting of TX LPI timer in microseconds. * This field is valid only when EEE is enabled and TX LPI is * enabled. */ @@ -13861,7 +13997,7 @@ struct hwrm_port_phy_qcfg_output { #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2) /* * The HW will be configured with external loopback such that - * host data is sent on the trasmitter and based on the external + * host data is sent on the transmitter and based on the external * loopback connection the data will be received without modification. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3) @@ -14500,7 +14636,7 @@ struct hwrm_port_mac_cfg_input { #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \ UINT32_C(0x100) /* - * When this bit is '1', the the Out-Of-Box WoL is requested to + * When this bit is '1', the Out-Of-Box WoL is requested to * be disabled on this port. */ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \ @@ -14670,7 +14806,7 @@ struct hwrm_port_mac_cfg_input { * This field shall be ignored if the ptp_tx_ts_capture_enable * flag is not set in this command. * Otherwise, if bit 'i' is set, then the HWRM is being - * requested to configure the transmit sied of the port to + * requested to configure the transmit side of the port to * capture the time stamp of every transmitted PTP message * with messageType field value set to i. */ @@ -16169,12 +16305,27 @@ struct hwrm_port_phy_qcaps_output { #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \ UINT32_C(0x2) /* + * If set to 1, then this field indicates that the + * PHY is capable of supporting loopback in autoneg mode. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED \ + UINT32_C(0x4) + /* + * Indicates if the configuration of shared PHY settings is supported. + * In cases where a physical port is shared by multiple functions + * (e.g. NPAR, multihost, etc), the configuration of PHY + * settings may not be allowed. Callers to HWRM_PORT_PHY_CFG will + * get an HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED error in this case. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED \ + UINT32_C(0x8) + /* * Reserved field. The HWRM shall set this field to 0. * An HWRM client shall ignore this field. */ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \ - UINT32_C(0xfc) - #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 2 + UINT32_C(0xf0) + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 4 /* Number of front panel ports for this device. */ uint8_t port_cnt; /* Not supported or unknown */ @@ -17726,6 +17877,553 @@ struct hwrm_port_prbs_test_output { uint8_t valid; } __attribute__((packed)); +/********************** + * hwrm_port_dsc_dump * + **********************/ + + +/* hwrm_port_dsc_dump_input (size:320b/40B) */ +struct hwrm_port_dsc_dump_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Host address where response diagnostic data is returned. */ + uint64_t resp_data_addr; + /* + * Size of the buffer pointed to by resp_data_addr. The firmware + * may use this entire buffer or less than the entire buffer, but + * never more. + */ + uint16_t data_len; + uint16_t unused_0; + uint32_t unused_1; + /* Port ID of port where dsc dump to be collected. */ + uint16_t port_id; + /* Diag level specified by the user */ + uint16_t diag_level; + /* SRDS_DIAG_LANE */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE \ + UINT32_C(0x0) + /* SRDS_DIAG_CORE */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_CORE \ + UINT32_C(0x1) + /* SRDS_DIAG_EVENT */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT \ + UINT32_C(0x2) + /* SRDS_DIAG_EYE */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EYE \ + UINT32_C(0x3) + /* SRDS_DIAG_REG_CORE */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_CORE \ + UINT32_C(0x4) + /* SRDS_DIAG_REG_LANE */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_LANE \ + UINT32_C(0x5) + /* SRDS_DIAG_UC_CORE */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_CORE \ + UINT32_C(0x6) + /* SRDS_DIAG_UC_LANE */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_LANE \ + UINT32_C(0x7) + /* SRDS_DIAG_LANE_DEBUG */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE_DEBUG \ + UINT32_C(0x8) + /* SRDS_DIAG_BER_VERT */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_VERT \ + UINT32_C(0x9) + /* SRDS_DIAG_BER_HORZ */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_HORZ \ + UINT32_C(0xa) + /* SRDS_DIAG_EVENT_SAFE */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT_SAFE \ + UINT32_C(0xb) + /* SRDS_DIAG_TIMESTAMP */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP \ + UINT32_C(0xc) + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_LAST \ + HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP + /* + * This field is a lane number + * on which to collect the dsc dump + */ + uint16_t lane_number; + /* + * Configuration bits. + * Use enable bit to start dsc dump or retrieve dump + */ + uint16_t dsc_dump_config; + /* + * Set 0 to retrieve the dsc dump + * Set 1 to start the dsc dump + */ + #define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_START_RETRIEVE \ + UINT32_C(0x1) +} __attribute__((packed)); + +/* hwrm_port_dsc_dump_output (size:128b/16B) */ +struct hwrm_port_dsc_dump_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Total length of stored data. */ + uint16_t total_data_len; + uint16_t unused_0; + uint8_t unused_1[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/****************************** + * hwrm_port_sfp_sideband_cfg * + ******************************/ + + +/* hwrm_port_sfp_sideband_cfg_input (size:256b/32B) */ +struct hwrm_port_sfp_sideband_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Port ID of port that is to be queried. */ + uint16_t port_id; + uint8_t unused_0[6]; + /* + * This bitfield is used to specify which bits from the 'flags' + * fields are being configured by the caller. + */ + uint32_t enables; + /* This bit must be '1' for rs0 to be configured. */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS0 \ + UINT32_C(0x1) + /* This bit must be '1' for rs1 to be configured. */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS1 \ + UINT32_C(0x2) + /* This bit must be '1' for tx_disable to be configured. */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_TX_DIS \ + UINT32_C(0x4) + /* + * This bit must be '1' for mod_sel to be configured. + * Valid only on QSFP modules + */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_MOD_SEL \ + UINT32_C(0x8) + /* This bit must be '1' for reset_l to be configured. */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RESET_L \ + UINT32_C(0x10) + /* This bit must be '1' for lp_mode to be configured. */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_LP_MODE \ + UINT32_C(0x20) + /* This bit must be '1' for pwr_disable to be configured. */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_PWR_DIS \ + UINT32_C(0x40) + /* + * Only bits that have corresponding bits in the 'enables' + * bitfield are processed by the firmware, all other bits + * of 'flags' are ignored. + */ + uint32_t flags; + /* + * This bit along with rs1 configures the current speed of the dual + * rate module. If these pins are GNDed then the speed can be changed + * by driectly writing to EEPROM. + */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS0 \ + UINT32_C(0x1) + /* + * This bit along with rs0 configures the current speed of the dual + * rate module. If these pins are GNDed then the speed can be changed + * by driectly writing to EEPROM. + */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS1 \ + UINT32_C(0x2) + /* + * When this bit is set to '1', tx_disable is set. + * On a 1G BASE-T module, if this bit is set, + * module PHY registers will not be accessible. + */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_TX_DIS \ + UINT32_C(0x4) + /* + * When this bit is set to '1', this module is selected. + * Valid only on QSFP modules + */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_MOD_SEL \ + UINT32_C(0x8) + /* + * If reset_l is set to 0, Module will be taken out of reset + * and other signals will be set to their requested state once + * the module is out of reset. + * Valid only on QSFP modules + */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RESET_L \ + UINT32_C(0x10) + /* + * When this bit is set to '1', the module will be configured + * in low power mode. + * Valid only on QSFP modules + */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_LP_MODE \ + UINT32_C(0x20) + /* When this bit is set to '1', the module will be powered down. */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_PWR_DIS \ + UINT32_C(0x40) +} __attribute__((packed)); + +/* hwrm_port_sfp_sideband_cfg_output (size:128b/16B) */ +struct hwrm_port_sfp_sideband_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/******************************* + * hwrm_port_sfp_sideband_qcfg * + *******************************/ + + +/* hwrm_port_sfp_sideband_qcfg_input (size:192b/24B) */ +struct hwrm_port_sfp_sideband_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Port ID of port that is to be queried. */ + uint16_t port_id; + uint8_t unused_0[6]; +} __attribute__((packed)); + +/* hwrm_port_sfp_sideband_qcfg_output (size:192b/24B) */ +struct hwrm_port_sfp_sideband_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Bitmask indicating which sideband signals are valid. + * This is based on the board and nvm cfg that is present on the board. + */ + uint32_t supported_mask; + uint32_t sideband_signals; + /* When this bit is set to '1', the Module is absent. */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_ABS \ + UINT32_C(0x1) + /* + * When this bit is set to '1', there is no valid signal on RX. + * This signal is a filtered version of Signal Detect. + */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RX_LOS \ + UINT32_C(0x2) + /* + * This bit along with rs1 indiactes the current speed of the dual + * rate module.If these pins are grounded then the speed can be + * changed by driectky writing to EEPROM. + */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS0 \ + UINT32_C(0x4) + /* + * This bit along with rs0 indiactes the current speed of the dual + * rate module.If these pins are grounded then the speed can be + * changed by driectky writing to EEPROM. + */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS1 \ + UINT32_C(0x8) + /* + * When this bit is set to '1', tx_disable is set. + * On a 1G BASE-T module, if this bit is set, module PHY + * registers will not be accessible. + */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_DIS \ + UINT32_C(0x10) + /* When this bit is set to '1', tx_fault is set. */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_FAULT \ + UINT32_C(0x20) + /* + * When this bit is set to '1', module is selected. + * Valid only on QSFP modules + */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_SEL \ + UINT32_C(0x40) + /* + * When this bit is set to '0', the module is held in reset. + * if reset_l is set to 1,first module is taken out of reset + * and other signals will be set to their requested state. + * Valid only on QSFP modules. + */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RESET_L \ + UINT32_C(0x80) + /* + * When this bit is set to '1', the module is in low power mode. + * Valid only on QSFP modules + */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_LP_MODE \ + UINT32_C(0x100) + /* When this bit is set to '1', module is in power down state. */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_PWR_DIS \ + UINT32_C(0x200) + uint8_t unused[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/********************************** + * hwrm_port_phy_mdio_bus_acquire * + **********************************/ + + +/* hwrm_port_phy_mdio_bus_acquire_input (size:192b/24B) */ +struct hwrm_port_phy_mdio_bus_acquire_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Port ID of the port. */ + uint16_t port_id; + /* + * client_id of the client requesting BUS access. + * Any value from 0x10 to 0xFFFF can be used. + * Client should make sure that the returned client_id + * in response matches the client_id in request. + * 0-0xF are reserved for internal use. + */ + uint16_t client_id; + /* + * Timeout in milli seconds, MDIO BUS will be released automatically + * after this time, if another mdio acquire command is not received + * within the timeout window from the same client. + * A 0xFFFF will hold the bus untill this bus is released. + */ + uint16_t mdio_bus_timeout; + uint8_t unused_0[2]; +} __attribute__((packed)); + +/* hwrm_port_phy_mdio_bus_acquire_output (size:128b/16B) */ +struct hwrm_port_phy_mdio_bus_acquire_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint16_t unused_0; + /* + * client_id of the module holding the BUS. + * 0-0xF are reserved for internal use. + */ + uint16_t client_id; + uint8_t unused_1[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/********************************** + * hwrm_port_phy_mdio_bus_release * + **********************************/ + + +/* hwrm_port_phy_mdio_bus_release_input (size:192b/24B) */ +struct hwrm_port_phy_mdio_bus_release_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Port ID of the port. */ + uint16_t port_id; + /* + * client_id of the client requesting BUS release. + * A client should not release any other clients BUS. + */ + uint16_t client_id; + uint8_t unused_0[4]; +} __attribute__((packed)); + +/* hwrm_port_phy_mdio_bus_release_output (size:128b/16B) */ +struct hwrm_port_phy_mdio_bus_release_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint16_t unused_0; + /* The BUS is released if client_id matches the client_id in request. */ + uint16_t clients_id; + uint8_t unused_1[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + /*********************** * hwrm_queue_qportcfg * ***********************/ @@ -17776,7 +18474,7 @@ struct hwrm_queue_qportcfg_input { HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX /* * Port ID of port for which the queue configuration is being - * queried. This field is only required when sent by IPC. + * queried. This field is only required when sent by IPC. */ uint16_t port_id; /* @@ -18171,7 +18869,7 @@ struct hwrm_queue_qportcfg_output { HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -18242,7 +18940,7 @@ struct hwrm_queue_qcfg_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * This value is a the estimate packet length used in the + * This value is the estimate packet length used in the * TX arbiter. */ uint32_t queue_len; @@ -18269,7 +18967,7 @@ struct hwrm_queue_qcfg_output { uint8_t unused_0; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -18373,7 +19071,7 @@ struct hwrm_queue_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -18463,7 +19161,7 @@ struct hwrm_queue_pfcenable_qcfg_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -18513,22 +19211,22 @@ struct hwrm_queue_pfcenable_cfg_input { /* If set to 1, then PFC is requested to be enabled on PRI 1. */ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \ UINT32_C(0x2) - /* If set to 1, then PFC is requested to be enabled on PRI 2. */ + /* If set to 1, then PFC is requested to be enabled on PRI 2. */ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \ UINT32_C(0x4) - /* If set to 1, then PFC is requested to be enabled on PRI 3. */ + /* If set to 1, then PFC is requested to be enabled on PRI 3. */ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \ UINT32_C(0x8) - /* If set to 1, then PFC is requested to be enabled on PRI 4. */ + /* If set to 1, then PFC is requested to be enabled on PRI 4. */ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \ UINT32_C(0x10) - /* If set to 1, then PFC is requested to be enabled on PRI 5. */ + /* If set to 1, then PFC is requested to be enabled on PRI 5. */ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \ UINT32_C(0x20) - /* If set to 1, then PFC is requested to be enabled on PRI 6. */ + /* If set to 1, then PFC is requested to be enabled on PRI 6. */ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \ UINT32_C(0x40) - /* If set to 1, then PFC is requested to be enabled on PRI 7. */ + /* If set to 1, then PFC is requested to be enabled on PRI 7. */ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \ UINT32_C(0x80) /* @@ -18553,7 +19251,7 @@ struct hwrm_queue_pfcenable_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -18611,9 +19309,9 @@ struct hwrm_queue_pri2cos_qcfg_input { HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX /* * When this bit is set to '0', the query is - * for VLAN PRI field in tunnel headers. + * for PRI from tunnel headers. * When this bit is set to '1', the query is - * for VLAN PRI field in inner packet headers. + * for PRI from inner packet headers. */ #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2) /* @@ -18636,56 +19334,56 @@ struct hwrm_queue_pri2cos_qcfg_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * CoS Queue assigned to priority 0. This value can only + * CoS Queue assigned to priority 0. This value can only * be changed before traffic has started. * A value of 0xff indicates that no CoS queue is assigned to the * specified priority. */ uint8_t pri0_cos_queue_id; /* - * CoS Queue assigned to priority 1. This value can only + * CoS Queue assigned to priority 1. This value can only * be changed before traffic has started. * A value of 0xff indicates that no CoS queue is assigned to the * specified priority. */ uint8_t pri1_cos_queue_id; /* - * CoS Queue assigned to priority 2 This value can only + * CoS Queue assigned to priority 2. This value can only * be changed before traffic has started. * A value of 0xff indicates that no CoS queue is assigned to the * specified priority. */ uint8_t pri2_cos_queue_id; /* - * CoS Queue assigned to priority 3. This value can only + * CoS Queue assigned to priority 3. This value can only * be changed before traffic has started. * A value of 0xff indicates that no CoS queue is assigned to the * specified priority. */ uint8_t pri3_cos_queue_id; /* - * CoS Queue assigned to priority 4. This value can only + * CoS Queue assigned to priority 4. This value can only * be changed before traffic has started. * A value of 0xff indicates that no CoS queue is assigned to the * specified priority. */ uint8_t pri4_cos_queue_id; /* - * CoS Queue assigned to priority 5. This value can only + * CoS Queue assigned to priority 5. This value can only * be changed before traffic has started. * A value of 0xff indicates that no CoS queue is assigned to the * specified priority. */ uint8_t pri5_cos_queue_id; /* - * CoS Queue assigned to priority 6. This value can only + * CoS Queue assigned to priority 6. This value can only * be changed before traffic has started. * A value of 0xff indicates that no CoS queue is assigned to the * specified priority. */ uint8_t pri6_cos_queue_id; /* - * CoS Queue assigned to priority 7. This value can only + * CoS Queue assigned to priority 7. This value can only * be changed before traffic has started. * A value of 0xff indicates that no CoS queue is assigned to the * specified priority. @@ -18704,7 +19402,7 @@ struct hwrm_queue_pri2cos_qcfg_output { uint8_t unused_0[6]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -18765,9 +19463,9 @@ struct hwrm_queue_pri2cos_cfg_input { HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR /* * When this bit is set to '0', the mapping is requested - * for VLAN PRI field in tunnel headers. + * for PRI from tunnel headers. * When this bit is set to '1', the mapping is requested - * for VLAN PRI field in inner packet headers. + * for PRI from inner packet headers. */ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4) uint32_t enables; @@ -18826,12 +19524,12 @@ struct hwrm_queue_pri2cos_cfg_input { */ uint8_t port_id; /* - * CoS Queue assigned to priority 0. This value can only + * CoS Queue assigned to priority 0. This value can only * be changed before traffic has started. */ uint8_t pri0_cos_queue_id; /* - * CoS Queue assigned to priority 1. This value can only + * CoS Queue assigned to priority 1. This value can only * be changed before traffic has started. */ uint8_t pri1_cos_queue_id; @@ -18841,27 +19539,27 @@ struct hwrm_queue_pri2cos_cfg_input { */ uint8_t pri2_cos_queue_id; /* - * CoS Queue assigned to priority 3. This value can only + * CoS Queue assigned to priority 3. This value can only * be changed before traffic has started. */ uint8_t pri3_cos_queue_id; /* - * CoS Queue assigned to priority 4. This value can only + * CoS Queue assigned to priority 4. This value can only * be changed before traffic has started. */ uint8_t pri4_cos_queue_id; /* - * CoS Queue assigned to priority 5. This value can only + * CoS Queue assigned to priority 5. This value can only * be changed before traffic has started. */ uint8_t pri5_cos_queue_id; /* - * CoS Queue assigned to priority 6. This value can only + * CoS Queue assigned to priority 6. This value can only * be changed before traffic has started. */ uint8_t pri6_cos_queue_id; /* - * CoS Queue assigned to priority 7. This value can only + * CoS Queue assigned to priority 7. This value can only * be changed before traffic has started. */ uint8_t pri7_cos_queue_id; @@ -18881,7 +19579,7 @@ struct hwrm_queue_pri2cos_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -19924,7 +20622,7 @@ struct hwrm_queue_cos2bw_qcfg_output { uint8_t unused_2[4]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -21016,7 +21714,609 @@ struct hwrm_queue_cos2bw_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/************************* + * hwrm_queue_dscp_qcaps * + *************************/ + + +/* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ +struct hwrm_queue_dscp_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure pri2cos mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[7]; +} __attribute__((packed)); + +/* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ +struct hwrm_queue_dscp_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* The number of bits provided by the hardware for the DSCP value. */ + uint8_t num_dscp_bits; + uint8_t unused_0; + /* Max number of DSCP-MASK-PRI entries supported. */ + uint16_t max_entries; + uint8_t unused_1[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/**************************** + * hwrm_queue_dscp2pri_qcfg * + ****************************/ + + +/* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ +struct hwrm_queue_dscp2pri_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * This is the host address where the 24-bits DSCP-MASK-PRI + * tuple(s) will be copied to. + */ + uint64_t dest_data_addr; + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure pri2cos mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0; + /* Size of the buffer pointed to by dest_data_addr. */ + uint16_t dest_data_buffer_size; + uint8_t unused_1[4]; +} __attribute__((packed)); + +/* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ +struct hwrm_queue_dscp2pri_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * A count of the number of DSCP-MASK-PRI tuple(s) pointed to + * by the dest_data_addr. + */ + uint16_t entry_cnt; + /* + * This is the default PRI which un-initialized DSCP values are + * mapped to. + */ + uint8_t default_pri; + uint8_t unused_0[4]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/*************************** + * hwrm_queue_dscp2pri_cfg * + ***************************/ + + +/* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ +struct hwrm_queue_dscp2pri_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * This is the host address where the 24-bits DSCP-MASK-PRI tuple + * will be copied from. + */ + uint64_t src_data_addr; + uint32_t flags; + /* use_hw_default_pri is 1 b */ + #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \ + UINT32_C(0x1) + uint32_t enables; + /* + * This bit must be '1' for the default_pri field to be + * configured. + */ + #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \ + UINT32_C(0x1) + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure pri2cos mapping on this port. + */ + uint8_t port_id; + /* + * This is the default PRI which un-initialized DSCP values will be + * mapped to. + */ + uint8_t default_pri; + /* + * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed + * to by src_data_addr. + */ + uint16_t entry_cnt; + uint8_t unused_0[4]; +} __attribute__((packed)); + +/* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ +struct hwrm_queue_dscp2pri_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/************************* + * hwrm_queue_mpls_qcaps * + *************************/ + + +/* hwrm_queue_mpls_qcaps_input (size:192b/24B) */ +struct hwrm_queue_mpls_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure MPLS TC(EXP) to pri mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[7]; +} __attribute__((packed)); + +/* hwrm_queue_mpls_qcaps_output (size:128b/16B) */ +struct hwrm_queue_mpls_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Bitmask indicating which queues can be configured by the + * hwrm_queue_mplstc2pri_cfg command. + * + * Each bit represents a specific pri where bit 0 represents + * pri 0 and bit 7 represents pri 7. + * # A value of 0 indicates that the pri is not configurable + * by the hwrm_queue_mplstc2pri_cfg command. + * # A value of 1 indicates that the pri is configurable. + * # A hwrm_queue_mplstc2pri_cfg command shall return error when + * trying to configure a pri that is not configurable. + */ + uint8_t queue_mplstc2pri_cfg_allowed; + /* + * This is the default PRI which un-initialized MPLS values will be + * mapped to. + */ + uint8_t hw_default_pri; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/****************************** + * hwrm_queue_mplstc2pri_qcfg * + ******************************/ + + +/* hwrm_queue_mplstc2pri_qcfg_input (size:192b/24B) */ +struct hwrm_queue_mplstc2pri_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure MPLS TC(EXP) to pri mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[7]; +} __attribute__((packed)); + +/* hwrm_queue_mplstc2pri_qcfg_output (size:192b/24B) */ +struct hwrm_queue_mplstc2pri_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * pri assigned to MPLS TC(EXP) 0. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 0. + */ + uint8_t tc0_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 1. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 1. + */ + uint8_t tc1_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 2. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 2. + */ + uint8_t tc2_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 3. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 3. + */ + uint8_t tc3_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 4. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 4. + */ + uint8_t tc4_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 5. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 5. + */ + uint8_t tc5_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 6. This value can only + * be changed before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 6. + */ + uint8_t tc6_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 7. This value can only + * be changed before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 7. + */ + uint8_t tc7_pri_queue_id; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/***************************** + * hwrm_queue_mplstc2pri_cfg * + *****************************/ + + +/* hwrm_queue_mplstc2pri_cfg_input (size:256b/32B) */ +struct hwrm_queue_mplstc2pri_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the mplstc0_pri_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC0_PRI_QUEUE_ID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the mplstc1_pri_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC1_PRI_QUEUE_ID \ + UINT32_C(0x2) + /* + * This bit must be '1' for the mplstc2_pri_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC2_PRI_QUEUE_ID \ + UINT32_C(0x4) + /* + * This bit must be '1' for the mplstc3_pri_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC3_PRI_QUEUE_ID \ + UINT32_C(0x8) + /* + * This bit must be '1' for the mplstc4_pri_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC4_PRI_QUEUE_ID \ + UINT32_C(0x10) + /* + * This bit must be '1' for the mplstc5_pri_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC5_PRI_QUEUE_ID \ + UINT32_C(0x20) + /* + * This bit must be '1' for the mplstc6_pri_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC6_PRI_QUEUE_ID \ + UINT32_C(0x40) + /* + * This bit must be '1' for the mplstc7_pri_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC7_PRI_QUEUE_ID \ + UINT32_C(0x80) + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure MPLS TC(EXP)to pri mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[3]; + /* + * pri assigned to MPLS TC(EXP) 0. This value can only + * be changed before traffic has started. + */ + uint8_t tc0_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 1. This value can only + * be changed before traffic has started. + */ + uint8_t tc1_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 2 This value can only + * be changed before traffic has started. + */ + uint8_t tc2_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 3. This value can only + * be changed before traffic has started. + */ + uint8_t tc3_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 4. This value can only + * be changed before traffic has started. + */ + uint8_t tc4_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 5. This value can only + * be changed before traffic has started. + */ + uint8_t tc5_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 6. This value can only + * be changed before traffic has started. + */ + uint8_t tc6_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 7. This value can only + * be changed before traffic has started. + */ + uint8_t tc7_pri_queue_id; +} __attribute__((packed)); + +/* hwrm_queue_mplstc2pri_cfg_output (size:128b/16B) */ +struct hwrm_queue_mplstc2pri_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -21529,7 +22829,13 @@ struct hwrm_vnic_qcfg_output { */ #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \ UINT32_C(0x40) - uint8_t unused_1[7]; + /* + * When returned with a valid CoS Queue id, the CoS Queue/VNIC association + * is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS + * queue association. + */ + uint16_t queue_id; + uint8_t unused_1[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -22040,6 +23346,27 @@ struct hwrm_vnic_rss_cfg_output { uint8_t valid; } __attribute__((packed)); +/* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ +struct hwrm_vnic_rss_cfg_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) + /* + * Unable to change global RSS mode to outer due to all active + * interfaces are not ready to support outer RSS hashing. + */ + #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY \ + UINT32_C(0x1) + #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_LAST \ + HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY + uint8_t unused_0[7]; +} __attribute__((packed)); + /********************** * hwrm_vnic_rss_qcfg * **********************/ @@ -22308,7 +23635,7 @@ struct hwrm_vnic_plcmodes_cfg_input { /* * This value is used to determine the offset into * packet buffer where the split data (payload) will be - * placed according to one of of HDS placement algorithm. + * placed according to one of HDS placement algorithm. * * The lengths of packet buffers provided for split data * shall be larger than this value. @@ -22450,7 +23777,7 @@ struct hwrm_vnic_plcmodes_qcfg_output { /* * This value is used to determine the offset into * packet buffer where the split data (payload) will be - * placed according to one of of HDS placement algorithm. + * placed according to one of HDS placement algorithm. * * The lengths of packet buffers provided for split data * shall be larger than this value. @@ -23768,7 +25095,7 @@ struct hwrm_cfa_l2_filter_alloc_input { UINT32_C(0x40) /* * Setting this flag to 1 indicate the L2 fields in this command - * pertain to source fields. Setting this flag to 0 indicate the + * pertain to source fields. Setting this flag to 0 indicate the * L2 fields in this command pertain to the destination fields * and this is the default/legacy behavior. */ @@ -24010,7 +25337,7 @@ struct hwrm_cfa_l2_filter_alloc_input { /* Generic Network Virtualization Encapsulation (Geneve) */ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ + /* Multi-Protocol Label Switching (MPLS) */ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ UINT32_C(0x6) /* Stateless Transport Tunnel (STT) */ @@ -24142,7 +25469,7 @@ struct hwrm_cfa_l2_filter_alloc_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -24205,7 +25532,7 @@ struct hwrm_cfa_l2_filter_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -24333,7 +25660,7 @@ struct hwrm_cfa_l2_filter_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -24515,7 +25842,7 @@ struct hwrm_cfa_l2_set_rx_mask_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -24608,7 +25935,7 @@ struct hwrm_cfa_vlan_antispoof_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -24688,7 +26015,7 @@ struct hwrm_cfa_vlan_antispoof_qcfg_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -24863,7 +26190,7 @@ struct hwrm_cfa_tunnel_filter_alloc_input { /* Generic Network Virtualization Encapsulation (Geneve) */ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ + /* Multi-Protocol Label Switching (MPLS) */ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ UINT32_C(0x6) /* Stateless Transport Tunnel (STT) */ @@ -24998,7 +26325,7 @@ struct hwrm_cfa_tunnel_filter_alloc_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -25058,7 +26385,7 @@ struct hwrm_cfa_tunnel_filter_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -25123,7 +26450,7 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input { /* Generic Network Virtualization Encapsulation (Geneve) */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ + /* Multi-Protocol Label Switching (MPLS) */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ UINT32_C(0x6) /* Stateless Transport Tunnel (STT) */ @@ -25170,7 +26497,7 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -25235,7 +26562,7 @@ struct hwrm_cfa_redirect_tunnel_type_free_input { /* Generic Network Virtualization Encapsulation (Geneve) */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \ UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ + /* Multi-Protocol Label Switching (MPLS) */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \ UINT32_C(0x6) /* Stateless Transport Tunnel (STT) */ @@ -25277,7 +26604,7 @@ struct hwrm_cfa_redirect_tunnel_type_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -25342,7 +26669,7 @@ struct hwrm_cfa_redirect_tunnel_type_info_input { /* Generic Network Virtualization Encapsulation (Geneve) */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \ UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ + /* Multi-Protocol Label Switching (MPLS) */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \ UINT32_C(0x6) /* Stateless Transport Tunnel (STT) */ @@ -25386,7 +26713,7 @@ struct hwrm_cfa_redirect_tunnel_type_info_output { uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -25564,7 +26891,7 @@ struct hwrm_cfa_encap_record_alloc_input { /* Generic Network Virtualization Encapsulation (Geneve) */ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \ UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ + /* Multi-Protocol Label Switching (MPLS) */ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \ UINT32_C(0x6) /* VLAN */ @@ -25607,7 +26934,7 @@ struct hwrm_cfa_encap_record_alloc_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -25668,7 +26995,7 @@ struct hwrm_cfa_encap_record_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -25681,7 +27008,7 @@ struct hwrm_cfa_encap_record_free_output { ********************************/ -/* hwrm_cfa_ntuple_filter_alloc_input (size:1088b/136B) */ +/* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ struct hwrm_cfa_ntuple_filter_alloc_input { /* The HWRM command request type. */ uint16_t req_type; @@ -25729,11 +27056,25 @@ struct hwrm_cfa_ntuple_filter_alloc_input { #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \ UINT32_C(0x4) /* - * Setting of this flag indicates that the dest_id field contains function ID. + * Setting of this flag indicates that the dst_id field contains function ID. * If this is not set it indicates dest_id is VNIC or VPORT. */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \ UINT32_C(0x8) + /* + * Setting of this flag indicates match on arp reply when ethertype is 0x0806. + * If this is not set it indicates no specific arp opcode matching. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_ARP_REPLY \ + UINT32_C(0x10) + /* + * Setting of this flag indicates that the dst_id field contains RFS ring + * table index. If this is not set it indicates dst_id is VNIC or VPORT + * or function ID. Note dest_fid and dest_rfs_ring_idx can’t be set at + * the same time. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX \ + UINT32_C(0x20) uint32_t enables; /* * This bit must be '1' for the l2_filter_id field to be @@ -25849,10 +27190,7 @@ struct hwrm_cfa_ntuple_filter_alloc_input { */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \ UINT32_C(0x40000) - /* - * This bit must be '1' for the rfs_ring_tbl_idx field to be - * configured. - */ + /* This flag is deprecated. */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \ UINT32_C(0x80000) /* @@ -25942,7 +27280,7 @@ struct hwrm_cfa_ntuple_filter_alloc_input { /* Generic Network Virtualization Encapsulation (Geneve) */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ + /* Multi-Protocol Label Switching (MPLS) */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ UINT32_C(0x6) /* Stateless Transport Tunnel (STT) */ @@ -26038,13 +27376,6 @@ struct hwrm_cfa_ntuple_filter_alloc_input { * the pri_hint. */ uint64_t ntuple_filter_id_hint; - /* - * The value of rfs_ring_tbl_idx to be used for RFS for this filter. - * This index is used in lieu of the RSS hash when selecting the - * index into the RSS table to determine the rx ring. - */ - uint16_t rfs_ring_tbl_idx; - uint8_t unused_0[6]; } __attribute__((packed)); /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ @@ -26102,7 +27433,7 @@ struct hwrm_cfa_ntuple_filter_alloc_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -26180,7 +27511,7 @@ struct hwrm_cfa_ntuple_filter_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -26249,6 +27580,14 @@ struct hwrm_cfa_ntuple_filter_cfg_input { */ #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \ UINT32_C(0x1) + /* + * Setting of this flag indicates that the new_dst_id field contains + * RFS ring table index. If this is not set it indicates new_dst_id is + * VNIC or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx + * can’t be set at the same time. + */ + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX \ + UINT32_C(0x2) /* This value is an opaque id into CFA data structures. */ uint64_t ntuple_filter_id; /* @@ -26293,7 +27632,7 @@ struct hwrm_cfa_ntuple_filter_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -26508,7 +27847,7 @@ struct hwrm_cfa_em_flow_alloc_input { /* Generic Network Virtualization Encapsulation (Geneve) */ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ + /* Multi-Protocol Label Switching (MPLS) */ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ UINT32_C(0x6) /* Stateless Transport Tunnel (STT) */ @@ -26699,7 +28038,7 @@ struct hwrm_cfa_em_flow_alloc_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -26759,7 +28098,7 @@ struct hwrm_cfa_em_flow_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -26872,7 +28211,7 @@ struct hwrm_cfa_meter_qcaps_output { uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -27150,7 +28489,7 @@ struct hwrm_cfa_meter_profile_alloc_output { uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -27235,7 +28574,7 @@ struct hwrm_cfa_meter_profile_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -27506,7 +28845,7 @@ struct hwrm_cfa_meter_profile_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -27602,7 +28941,7 @@ struct hwrm_cfa_meter_instance_alloc_output { uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -27695,7 +29034,7 @@ struct hwrm_cfa_meter_instance_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -27780,7 +29119,7 @@ struct hwrm_cfa_meter_instance_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -27958,7 +29297,7 @@ struct hwrm_cfa_decap_filter_alloc_input { /* Generic Network Virtualization Encapsulation (Geneve) */ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ + /* Multi-Protocol Label Switching (MPLS) */ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ UINT32_C(0x6) /* Stateless Transport Tunnel (STT) */ @@ -28105,7 +29444,7 @@ struct hwrm_cfa_decap_filter_alloc_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -28166,7 +29505,7 @@ struct hwrm_cfa_decap_filter_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -28326,7 +29665,7 @@ struct hwrm_cfa_flow_alloc_input { UINT32_C(0x800) /* * If set to 1 an attempt will be made to try to offload this flow to the - * most optimal flow table resource. If set to 0, the flow will be + * most optimal flow table resource. If set to 0, the flow will be * placed to the default flow table resource. */ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \ @@ -28335,7 +29674,7 @@ struct hwrm_cfa_flow_alloc_input { * If set to 1 there will be no attempt to allocate an on-chip try to * offload this flow. If set to 0, which will keep compatibility with the * older drivers, will cause the FW to attempt to allocate an on-chip flow - * counter for the newly created flow. This will keep the existing behavior + * counter for the newly created flow. This will keep the existing behavior * with EM flows which always had an associated flow counter. */ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \ @@ -28428,7 +29767,7 @@ struct hwrm_cfa_flow_alloc_input { /* Generic Network Virtualization Encapsulation (Geneve) */ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ + /* Multi-Protocol Label Switching (MPLS) */ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ UINT32_C(0x6) /* Stateless Transport Tunnel (STT) */ @@ -28515,7 +29854,7 @@ struct hwrm_cfa_flow_alloc_output { uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -28612,7 +29951,7 @@ struct hwrm_cfa_flow_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -28651,10 +29990,10 @@ struct hwrm_cfa_flow_action_data { /* If set to 1, flow aging is enabled for this flow. */ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \ UINT32_C(0x80) - /* Setting of this flag indicates encap action.. */ + /* Setting of this flag indicates encap action. */ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \ UINT32_C(0x100) - /* Setting of this flag indicates decap action.. */ + /* Setting of this flag indicates decap action. */ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \ UINT32_C(0x200) /* Meter id. */ @@ -28680,7 +30019,7 @@ struct hwrm_cfa_flow_action_data { #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4) /* Generic Network Virtualization Encapsulation (Geneve) */ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ + /* Multi-Protocol Label Switching (MPLS) */ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6) /* VLAN */ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7) @@ -28723,7 +30062,7 @@ struct hwrm_cfa_flow_tunnel_hdr_data { /* Generic Network Virtualization Encapsulation (Geneve) */ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \ UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ + /* Multi-Protocol Label Switching (MPLS) */ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \ UINT32_C(0x6) /* Stateless Transport Tunnel (STT) */ @@ -28946,7 +30285,7 @@ struct hwrm_cfa_flow_info_output { uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -29001,7 +30340,7 @@ struct hwrm_cfa_flow_flush_input { UINT32_C(0x1) /* * Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA - * context memory tables..etc. This flag is set to 0 by older driver. For older firmware, + * context memory tables etc. This flag is set to 0 by older driver. For older firmware, * setting this flag has no effect. */ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \ @@ -29080,7 +30419,7 @@ struct hwrm_cfa_flow_flush_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -29221,7 +30560,7 @@ struct hwrm_cfa_flow_stats_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -29289,7 +30628,7 @@ struct hwrm_cfa_flow_aging_timer_reset_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -29414,7 +30753,7 @@ struct hwrm_cfa_flow_aging_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -29499,7 +30838,7 @@ struct hwrm_cfa_flow_aging_qcfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -29576,7 +30915,7 @@ struct hwrm_cfa_flow_aging_qcaps_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -29642,7 +30981,7 @@ struct hwrm_cfa_tcp_flag_process_qcfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -29763,7 +31102,7 @@ struct hwrm_cfa_pair_info_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -29841,7 +31180,7 @@ struct hwrm_cfa_redirect_query_tunnel_type_output { /* Generic Network Virtualization Encapsulation (Geneve) */ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \ UINT32_C(0x20) - /* Multi-Protocol Lable Switching (MPLS) */ + /* Multi-Protocol Label Switching (MPLS) */ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \ UINT32_C(0x40) /* Stateless Transport Tunnel (STT) */ @@ -29868,7 +31207,7 @@ struct hwrm_cfa_redirect_query_tunnel_type_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -29958,14 +31297,14 @@ struct hwrm_cfa_ctx_mem_rgtr_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * Id/Handle to the recently register context memory. This handle is passed + * Id/Handle to the recently register context memory. This handle is passed * to the CFA feature. */ uint16_t ctx_id; uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -30009,7 +31348,7 @@ struct hwrm_cfa_ctx_mem_unrgtr_input { */ uint64_t resp_addr; /* - * Id/Handle to the recently register context memory. This handle is passed + * Id/Handle to the recently register context memory. This handle is passed * to the CFA feature. */ uint16_t ctx_id; @@ -30029,7 +31368,7 @@ struct hwrm_cfa_ctx_mem_unrgtr_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -30073,7 +31412,7 @@ struct hwrm_cfa_ctx_mem_qctx_input { */ uint64_t resp_addr; /* - * Id/Handle to the recently register context memory. This handle is passed + * Id/Handle to the recently register context memory. This handle is passed * to the CFA feature. */ uint16_t ctx_id; @@ -30127,7 +31466,7 @@ struct hwrm_cfa_ctx_mem_qctx_output { uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -30187,7 +31526,7 @@ struct hwrm_cfa_ctx_mem_qcaps_output { uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -30278,15 +31617,15 @@ struct hwrm_cfa_eem_qcaps_output { UINT32_C(0x2) /* * When set to 1, indicates the the FW supports the Centralized - * Memory Model. The concept designates one entity for the + * Memory Model. The concept designates one entity for the * memory allocation while all others ‘subscribe’ to it. */ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \ UINT32_C(0x4) /* * When set to 1, indicates the the FW supports the Detached - * Centralized Memory Model. The memory is allocated and managed - * as a separate entity. All PFs and VFs will be granted direct + * Centralized Memory Model. The memory is allocated and managed + * as a separate entity. All PFs and VFs will be granted direct * or semi-direct access to the allocated memory while none of * which can interfere with the management of the memory. */ @@ -30326,7 +31665,7 @@ struct hwrm_cfa_eem_qcaps_output { #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \ UINT32_C(0x10) /* - * The maximum number of entries supported by EEM. When configuring the host memory + * The maximum number of entries supported by EEM. When configuring the host memory * the number of numbers of entries that can supported are - * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries. * Any value that are not these values, the FW will round down to the closest support @@ -30344,7 +31683,7 @@ struct hwrm_cfa_eem_qcaps_output { uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -30415,9 +31754,9 @@ struct hwrm_cfa_eem_cfg_input { uint16_t group_id; uint16_t unused_0; /* - * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1, + * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1, * RECORD, EFC all have the same number of entries and all tables will be configured - * using this value. Current minimum value is 32k. Current maximum value is 128M. + * using this value. Current minimum value is 32k. Current maximum value is 128M. */ uint32_t num_entries; uint32_t unused_1; @@ -30448,7 +31787,7 @@ struct hwrm_cfa_eem_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -30534,7 +31873,7 @@ struct hwrm_cfa_eem_qcfg_output { uint8_t unused_2[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -30597,7 +31936,7 @@ struct hwrm_cfa_eem_op_input { #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0) /* * To properly stop EEM and ensure there are no DMA's, the caller - * must disable EEM for the given PF, using this call. This will + * must disable EEM for the given PF, using this call. This will * safely disable EEM and ensure that all DMA'ed to the * keys/records/efc have been completed. */ @@ -30605,7 +31944,7 @@ struct hwrm_cfa_eem_op_input { /* * Once the EEM host memory has been configured, EEM options have * been configured. Then the caller should enable EEM for the given - * PF. Note once this call has been made, then the EEM mechanism + * PF. Note once this call has been made, then the EEM mechanism * will be active and DMA's will occur as packets are processed. */ #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2) @@ -30631,7 +31970,7 @@ struct hwrm_cfa_eem_op_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -30770,10 +32109,34 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output { */ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \ UINT32_C(0x800) + /* + * If set to 1, firmware is capable of supporting ARP ethertype as + * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the + * RX direction. By default, this flag should be 0 for older version + * of firmware. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \ + UINT32_C(0x1000) + /* + * Value of 1 to indicate that firmware supports setting of + * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC + * command. Value of 0 indicates firmware does not support + * rfs_ring_tbl_idx in dst_id field. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \ + UINT32_C(0x2000) + /* + * If set to 1, firmware is capable of supporting IPv4/IPv6 as + * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX + * direction. By default, this flag should be 0 for older version + * of firmware. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \ + UINT32_C(0x4000) uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -30848,7 +32211,7 @@ struct hwrm_cfa_tflib_output { uint8_t unused1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -31792,11 +33155,11 @@ struct pcie_ctx_hw_stats { uint64_t pcie_tl_signal_integrity; /* Number of times LTSSM entered Recovery state */ uint64_t pcie_link_integrity; - /* Number of TLP bytes that have been trasmitted */ + /* Number of TLP bytes that have been transmitted */ uint64_t pcie_tx_traffic_rate; /* Number of TLP bytes that have been received */ uint64_t pcie_rx_traffic_rate; - /* Number of DLLP bytes that have been trasmitted */ + /* Number of DLLP bytes that have been transmitted */ uint64_t pcie_tx_dllp_statistics; /* Number of DLLP bytes that have been received */ uint64_t pcie_rx_dllp_statistics; @@ -32158,7 +33521,7 @@ struct hwrm_nvm_raw_write_blk_input { uint64_t resp_addr; /* * 64-bit Host Source Address. - * This is the loation of the source data to be written. + * This is the location of the source data to be written. */ uint64_t host_src_addr; /* @@ -32523,7 +33886,7 @@ struct hwrm_nvm_write_input { * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length). * If this value is less than the specified data length, it will be ignored. * The response will contain the actual allocated item length, which may be greater than the requested item length. - * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accomodate + * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accommodate * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data). */ uint32_t dir_item_length; @@ -33105,7 +34468,7 @@ struct hwrm_nvm_install_update_input { #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \ UINT32_C(0x1) /* - * If set to 1, then unspecifed images, images not in the package file, will be safely deleted. + * If set to 1, then unspecified images, images not in the package file, will be safely deleted. * When combined with erase_unused_space then unspecified images will be securely erased. */ #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \ From patchwork Thu Oct 24 05:59:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 61808 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 9F4B11C1FC; Thu, 24 Oct 2019 08:07:21 +0200 (CEST) Received: from relay.smtp.broadcom.com (relay.smtp.broadcom.com [192.19.211.62]) by dpdk.org (Postfix) with ESMTP id 562951C190 for ; Thu, 24 Oct 2019 08:06:59 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (bgccx-dev-host-lnx35.bec.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id 3A0FD28FA85; Wed, 23 Oct 2019 23:06:58 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com 3A0FD28FA85 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1571897218; bh=q891UosWyEh8Nygxq2YmT+Ce9Ji3N4FpAGxPcWq+zjo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uiJRBFl+ikFcoV57r4TcJmNcQpNlqj+o0a0R7j9fge/TwU+wa7DsVvlTwWIV3pa92 vQLqtNrmRd1DxwnFiiPI4OqPLXWbB5oSnEshkPa5XLyzgb1Apd7yb6KZ0hruxEdsCs p1PmrG+lNzOboWID/b04v2Q7StKzddYQ01tDH1MY= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Thu, 24 Oct 2019 11:29:02 +0530 Message-Id: <20191024055913.28817-8-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20191024055913.28817-1-somnath.kotur@broadcom.com> References: <20191024055913.28817-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 07/16] net/bnxt: use mac index, while checking for default mac X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Venkat Duvvuru bnxt_set_hwrm_vnic_filters programs default mac addr and the same default mac is added by mac_add_addr_op routine as well. This redundant mac add is avoided by checking if the default mac is already added. However, that check is wrong. The check should consider the mac index as well to determine the default mac. This patch fixes it by using mac index to determine the default mac. Fixes: d42878f5fa17 ("net/bnxt: fix vlan filtering code path") Signed-off-by: Venkat Duvvuru Reviewed-by: Somnath Kotur Signed-off-by: Somnath Kotur --- drivers/net/bnxt/bnxt_ethdev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index ce3a03a..820005c 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -1023,7 +1023,7 @@ static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic, * hw-vlan-filter is turned OFF from ON, default * MAC filter should be restored */ - if (filter->dflt) + if (index == 0 && filter->dflt) return 0; filter = bnxt_alloc_filter(bp); From patchwork Thu Oct 24 05:59:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 61807 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2F7621C1E5; Thu, 24 Oct 2019 08:07:18 +0200 (CEST) Received: from relay.smtp.broadcom.com (unknown [192.19.211.62]) by dpdk.org (Postfix) with ESMTP id 20A891C18F for ; Thu, 24 Oct 2019 08:06:59 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (bgccx-dev-host-lnx35.bec.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id 9120E28FA8F; Wed, 23 Oct 2019 23:06:58 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com 9120E28FA8F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1571897218; bh=2tGul3N6VKnpTcx+peUw8FGU26gZ0uVlyTD3knIpQbE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vWUNIJmfH9DPYKYgpq1Jz3rhN8k0yPmHaYju4ydKSoXgNmoT5wGFp6i8qdBPHx8LO qxZE2+UlbgiLrJWd5uJDfNfcrkO16BAiISxZuWxOdaAbJ/czp79P1VPpOT1lnQIlyY QtX0gjN/6RulekWxVij/U8SbHWf7GDA4rBtI8e1s= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Thu, 24 Oct 2019 11:29:03 +0530 Message-Id: <20191024055913.28817-9-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20191024055913.28817-1-somnath.kotur@broadcom.com> References: <20191024055913.28817-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 08/16] net/bnxt: fix a possible race between start and interrupt handler X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kalesh AP During port start, driver enables interrupts. At the end of port start driver schedules the alarm for fw health check. This can cause race between interrupt handler and schedule fw health check alarm thread which falsely detects FW error. Fixes: 241f043a3c8f ("net/bnxt: handle firmware reset status during port start") Signed-off-by: Kalesh AP Reviewed-by: Somnath Kotur Reviewed-by: Ajit Kumar Khaparde Signed-off-by: Somnath Kotur --- drivers/net/bnxt/bnxt_ethdev.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 820005c..e24fd41 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -869,7 +869,9 @@ static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) bp->flags |= BNXT_FLAG_INIT_DONE; eth_dev->data->dev_started = 1; bp->dev_stopped = 0; + pthread_mutex_lock(&bp->def_cp_lock); bnxt_schedule_fw_health_check(bp); + pthread_mutex_unlock(&bp->def_cp_lock); return 0; error: From patchwork Thu Oct 24 05:59:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 61812 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 3D4C61C23B; Thu, 24 Oct 2019 08:07:41 +0200 (CEST) Received: from relay.smtp.broadcom.com (relay.smtp.broadcom.com [192.19.211.62]) by dpdk.org (Postfix) with ESMTP id 193351C190 for ; Thu, 24 Oct 2019 08:07:00 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (bgccx-dev-host-lnx35.bec.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id E7CB228FA9B; Wed, 23 Oct 2019 23:06:58 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com E7CB228FA9B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1571897219; bh=R6x7AvKyBc16RBz1IgSLBczKuBt/SU750+nDWoYkcb8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oGvct4xnfb0KMLr19LD/9CWspJGvhqejioFF3humXiGiNg/SCxOqrqgnTmWqa6ZzB FPD/Oo+f43g6mU1tBtO9zdRJMIcQVnqFbT8vmyzJkY3uYcZGZled9tANaRv5tpnQjK WDI/u6OyI3xNP4g2BDOAFioPE+eD9ZODZkHfavNA= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Thu, 24 Oct 2019 11:29:04 +0530 Message-Id: <20191024055913.28817-10-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20191024055913.28817-1-somnath.kotur@broadcom.com> References: <20191024055913.28817-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 09/16] net/bnxt: fix to use HWRM_CFA_L2_FILTER as the filter_type for non-ntuple flows X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Rahul Gupta Use HWRM_CFA_L2_FILTER filter_type, as its checked during SRC MAC filter creation in bnxt_create_l2_filter(). Fixes: f1a9687b7b352 ("net/bnxt: create SMAC filter only for L2 flows") Signed-off-by: Rahul Gupta Reviewed-by: Somnath Kotur Reviewed-by: Ajit Kumar Khaparde Signed-off-by: Somnath Kotur --- drivers/net/bnxt/bnxt_flow.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/bnxt/bnxt_flow.c b/drivers/net/bnxt/bnxt_flow.c index 85d2354..2bde6f7 100644 --- a/drivers/net/bnxt/bnxt_flow.c +++ b/drivers/net/bnxt/bnxt_flow.c @@ -161,7 +161,7 @@ PMD_DRV_LOG(DEBUG, "Use NTUPLE %d\n", use_ntuple); filter->filter_type = use_ntuple ? - HWRM_CFA_NTUPLE_FILTER : HWRM_CFA_EM_FILTER; + HWRM_CFA_NTUPLE_FILTER : HWRM_CFA_L2_FILTER; en_ethertype = use_ntuple ? NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE : EM_FLOW_ALLOC_INPUT_EN_ETHERTYPE; From patchwork Thu Oct 24 05:59:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 61809 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7F5AC1C219; Thu, 24 Oct 2019 08:07:27 +0200 (CEST) Received: from relay.smtp.broadcom.com (unknown [192.19.211.62]) by dpdk.org (Postfix) with ESMTP id DDC401C18F for ; Thu, 24 Oct 2019 08:06:59 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (bgccx-dev-host-lnx35.bec.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id 4A5E728FA8C; Wed, 23 Oct 2019 23:06:59 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com 4A5E728FA8C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1571897219; bh=RYF0Ob/QHydUAwowi5rhIE2xzz03IU+3YtzFjM9OILs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vzHpE0p1QeZexBzQrp/C0EYlwcDNxYqsSQXEQqmPjPAmgDPpihxkByo0Vnd5npNCR 3CEJinPrukmh+FNMdsEWAODWZ15lSvQfrz+EZJ6DdAxfhoafTi97sCLmQHQkz+dFIv HKItZPZh9sM4G3mZVsO0S/FiAtxa6oCZhR2bXs+o= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Thu, 24 Oct 2019 11:29:05 +0530 Message-Id: <20191024055913.28817-11-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20191024055913.28817-1-somnath.kotur@broadcom.com> References: <20191024055913.28817-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 10/16] net/bnxt: expose some missing counters in port statistics X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Rx/Tx Port statistics record PFC enabled frames for each priority. Modify the Rx/Tx port stats array to report these as well. Fixes: bfb9c226 ("net/bnxt: support xstats get/reset") Reviewed-by: Ajit Kumar Khaparde Signed-off-by: Somnath Kotur --- drivers/net/bnxt/bnxt_stats.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/net/bnxt/bnxt_stats.c b/drivers/net/bnxt/bnxt_stats.c index fa29f9d..40b496a 100644 --- a/drivers/net/bnxt/bnxt_stats.c +++ b/drivers/net/bnxt/bnxt_stats.c @@ -81,6 +81,22 @@ rx_runt_bytes)}, {"rx_runt_frames", offsetof(struct rx_port_stats, rx_runt_frames)}, + {"rx_pfc_ena_frames_pri0", offsetof(struct rx_port_stats, + rx_pfc_ena_frames_pri0)}, + {"rx_pfc_ena_frames_pri1", offsetof(struct rx_port_stats, + rx_pfc_ena_frames_pri1)}, + {"rx_pfc_ena_frames_pri2", offsetof(struct rx_port_stats, + rx_pfc_ena_frames_pri2)}, + {"rx_pfc_ena_frames_pri3", offsetof(struct rx_port_stats, + rx_pfc_ena_frames_pri3)}, + {"rx_pfc_ena_frames_pri4", offsetof(struct rx_port_stats, + rx_pfc_ena_frames_pri4)}, + {"rx_pfc_ena_frames_pri5", offsetof(struct rx_port_stats, + rx_pfc_ena_frames_pri5)}, + {"rx_pfc_ena_frames_pri6", offsetof(struct rx_port_stats, + rx_pfc_ena_frames_pri6)}, + {"rx_pfc_ena_frames_pri7", offsetof(struct rx_port_stats, + rx_pfc_ena_frames_pri7)}, }; static const struct bnxt_xstats_name_off bnxt_tx_stats_strings[] = { @@ -136,6 +152,22 @@ tx_total_collisions)}, {"tx_bytes", offsetof(struct tx_port_stats, tx_bytes)}, + {"tx_pfc_ena_frames_pri0", offsetof(struct tx_port_stats, + tx_pfc_ena_frames_pri0)}, + {"tx_pfc_ena_frames_pri1", offsetof(struct tx_port_stats, + tx_pfc_ena_frames_pri1)}, + {"tx_pfc_ena_frames_pri2", offsetof(struct tx_port_stats, + tx_pfc_ena_frames_pri2)}, + {"tx_pfc_ena_frames_pri3", offsetof(struct tx_port_stats, + tx_pfc_ena_frames_pri3)}, + {"tx_pfc_ena_frames_pri4", offsetof(struct tx_port_stats, + tx_pfc_ena_frames_pri4)}, + {"tx_pfc_ena_frames_pri5", offsetof(struct tx_port_stats, + tx_pfc_ena_frames_pri5)}, + {"tx_pfc_ena_frames_pri6", offsetof(struct tx_port_stats, + tx_pfc_ena_frames_pri6)}, + {"tx_pfc_ena_frames_pri7", offsetof(struct tx_port_stats, + tx_pfc_ena_frames_pri7)}, }; static const struct bnxt_xstats_name_off bnxt_func_stats_strings[] = { From patchwork Thu Oct 24 05:59:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 61811 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 9F1681C231; Thu, 24 Oct 2019 08:07:34 +0200 (CEST) Received: from relay.smtp.broadcom.com (relay.smtp.broadcom.com [192.19.211.62]) by dpdk.org (Postfix) with ESMTP id 246E61C195 for ; Thu, 24 Oct 2019 08:07:00 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (bgccx-dev-host-lnx35.bec.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id 982D328FA8D; Wed, 23 Oct 2019 23:06:59 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com 982D328FA8D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1571897219; bh=D0rIyCJhqgFP7qi2XI+iGznK+HOoZaIPoRY+aWhqong=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mtCPmqPpnSSz8E+zFRlCp14vjeFak+2PYv95BirTZ6xtNYphrdBOGdW+NR+y2twuo xP5WgtLbzeQUTSYAckSudmg3snLDU0S6kMi7aCNBZZR9RzTK4UlPuSBFdHNEET4nbv DkqFS3U17oYXjptRucQv8okHKI+y2X2Usis9OGQI= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Thu, 24 Oct 2019 11:29:06 +0530 Message-Id: <20191024055913.28817-12-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20191024055913.28817-1-somnath.kotur@broadcom.com> References: <20191024055913.28817-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 11/16] net/bnxt: fix to check for zero mac address while parsing flow arguments X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add another check to flag zero mac address while validating/parsing the flow arguments Fixes: 74defda79 ("net/bnxt: allow only unicast MAC address filter creation") Reviewed-by: Venkat Duvvuru Signed-off-by: Somnath Kotur --- drivers/net/bnxt/bnxt_flow.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/net/bnxt/bnxt_flow.c b/drivers/net/bnxt/bnxt_flow.c index 2bde6f7..cad232a 100644 --- a/drivers/net/bnxt/bnxt_flow.c +++ b/drivers/net/bnxt/bnxt_flow.c @@ -136,6 +136,7 @@ const struct rte_flow_item_tcp *tcp_spec, *tcp_mask; const struct rte_flow_item_udp *udp_spec, *udp_mask; const struct rte_flow_item_eth *eth_spec, *eth_mask; + const struct rte_ether_addr *dst, *src; const struct rte_flow_item_nvgre *nvgre_spec; const struct rte_flow_item_nvgre *nvgre_mask; const struct rte_flow_item_gre *gre_spec; @@ -226,12 +227,15 @@ } if (rte_is_broadcast_ether_addr(ð_mask->dst)) { - if (!rte_is_unicast_ether_addr(ð_spec->dst)) { + dst = ð_spec->dst; + if (!rte_is_valid_assigned_ether_addr(dst)) { rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, item, "DMAC is invalid"); + PMD_DRV_LOG(ERR, + "DMAC is invalid!\n"); return -rte_errno; } rte_memcpy(filter->dst_macaddr, @@ -246,14 +250,16 @@ PMD_DRV_LOG(DEBUG, "Creating a priority flow\n"); } - if (rte_is_broadcast_ether_addr(ð_mask->src)) { - if (!rte_is_unicast_ether_addr(ð_spec->src)) { + src = ð_spec->src; + if (!rte_is_valid_assigned_ether_addr(src)) { rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, item, "SMAC is invalid"); + PMD_DRV_LOG(ERR, + "SMAC is invalid!\n"); return -rte_errno; } rte_memcpy(filter->src_macaddr, From patchwork Thu Oct 24 05:59:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 61814 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 9753C1C2A2; Thu, 24 Oct 2019 08:07:54 +0200 (CEST) Received: from relay.smtp.broadcom.com (unknown [192.19.211.62]) by dpdk.org (Postfix) with ESMTP id 1981B1C198 for ; Thu, 24 Oct 2019 08:07:01 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (bgccx-dev-host-lnx35.bec.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id E68B628FAA4; Wed, 23 Oct 2019 23:06:59 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com E68B628FAA4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1571897220; bh=WoHluwaQDirwu6FSwr412XkYmB+ZhfiuXusetIyzTnc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BRYb0IFDMi8vsgwrBaROQ2wbDumzkGp1TSSZbV9QD+rLXzl5NLu3RyN83fyt9NDbR Je3r4+3AodXl6Z582rFfoCbmOUOpR7/n9GsQLL9iqgFeeYWAVxQOEepHJVsajBbL4o OBrbsNKJtCXYZ2CDNvOzpaXqR4eSmuD38uXhYAik= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Thu, 24 Oct 2019 11:29:07 +0530 Message-Id: <20191024055913.28817-13-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20191024055913.28817-1-somnath.kotur@broadcom.com> References: <20191024055913.28817-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 12/16] net/bnxt: fix segfault after removing and adding the slaves X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Santoshkumar Karanappa Rastapur On removing the slave interface, slave_remove in bonding module calls _rte_eth_dev_reset which in turn frees both Tx and Rx queues. 1. segfault is seen after removing/adding the slave interface and starting bond interface. In this below path, when mtu is set for the slave interface, queues are not created yet and driver reference to queue[0] causes the segfault. slave_configure: rte_eth_dev_set_mtu rte_eth_dev_configure rte_eth_rx_queue_setup 2. segfault is seen on starting the port after removing from bond device. This is a testpmd bug where in, on starting the port, testpmd is supposed to recreate the queues before starting the port. Fixed these by adding check for queues created before accessing them. Signed-off-by: Santoshkumar Karanappa Rastapur Reviewed-by: Somnath Kotur Signed-off-by: Somnath Kotur --- drivers/net/bnxt/bnxt.h | 1 + drivers/net/bnxt/bnxt_ethdev.c | 19 ++++++++++++++++--- drivers/net/bnxt/bnxt_rxq.c | 4 ++++ 3 files changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 975bcf9..ffc37ea 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -639,6 +639,7 @@ struct bnxt { struct bnxt_error_recovery_info *recovery_info; }; +int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu); int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete); int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg); int is_bnxt_in_error(struct bnxt *bp); diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index e24fd41..4187247 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -121,7 +121,6 @@ static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask); static void bnxt_print_link_info(struct rte_eth_dev *eth_dev); -static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu); static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev); static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev); static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev); @@ -831,6 +830,11 @@ static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) int vlan_mask = 0; int rc; + if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) { + PMD_DRV_LOG(ERR, "Queues are not configured yet!\n"); + return -EINVAL; + } + if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) { PMD_DRV_LOG(ERR, "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n", @@ -2126,7 +2130,7 @@ static int bnxt_del_dflt_mac_filter(struct bnxt *bp, qinfo->conf.tx_deferred_start = txq->tx_deferred_start; } -static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) +int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) { struct bnxt *bp = eth_dev->data->dev_private; uint32_t new_pkt_size; @@ -2137,6 +2141,10 @@ static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) if (rc) return rc; + /* Exit if receive queues are not configured yet */ + if (!eth_dev->data->nb_rx_queues) + return rc; + new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * BNXT_NUM_VLANS; @@ -2167,7 +2175,9 @@ static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) bp->flags &= ~BNXT_FLAG_JUMBO; } - eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size; + /* Is there a change in mtu setting? */ + if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size) + return rc; for (i = 0; i < bp->nr_vnics; i++) { struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; @@ -2188,6 +2198,9 @@ static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) } } + if (!rc) + eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size; + PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu); return rc; diff --git a/drivers/net/bnxt/bnxt_rxq.c b/drivers/net/bnxt/bnxt_rxq.c index e1ed360..d55adc3 100644 --- a/drivers/net/bnxt/bnxt_rxq.c +++ b/drivers/net/bnxt/bnxt_rxq.c @@ -366,6 +366,10 @@ int bnxt_rx_queue_setup_op(struct rte_eth_dev *eth_dev, eth_dev->data->rx_queue_state[queue_idx] = queue_state; rte_spinlock_init(&rxq->lock); + /* Configure mtu if it is different from what was configured before */ + if (!queue_idx) + bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu); + out: return rc; } From patchwork Thu Oct 24 05:59:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 61813 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 781631C29C; Thu, 24 Oct 2019 08:07:47 +0200 (CEST) Received: from relay.smtp.broadcom.com (unknown [192.19.211.62]) by dpdk.org (Postfix) with ESMTP id BA4031C033 for ; Thu, 24 Oct 2019 08:07:00 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (bgccx-dev-host-lnx35.bec.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id 3FC0E28FAAA; Wed, 23 Oct 2019 23:07:00 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com 3FC0E28FAAA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1571897220; bh=N3ywszljJEBCojBxwqQcOJPZYSn5nhMFi7svh/Tx+jM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FtVHQ7MUkydc861CcgsbeJKh4esq0p5q1EjnAauoChKKBsbJIudjrfKM/dt7X9qvT ZpgyA4sFVCNzDgKYjhvk/Jqpz7jjROmOXvUZzjPcRHlcff9j9QPng+A+mrRESlJGK1 00lUryVuMO4arTSWoBr4/174uxscrDXYC1bjTPWY= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Thu, 24 Oct 2019 11:29:08 +0530 Message-Id: <20191024055913.28817-14-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20191024055913.28817-1-somnath.kotur@broadcom.com> References: <20191024055913.28817-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 13/16] net/bnxt: add more checks for fw reset X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kalesh AP Added check for fw reset or fw errors in few more routines. While processing the events, if it is fw fatal or non-fatal event, there is no need to process the remaining events as driver triggers recovery mechanism. Also added a check for fw reset or fatal error in bnxt_disable_int() to avoid bar access in case of fatal error. Signed-off-by: Kalesh AP Reviewed-by: Rahul Gupta Reviewed-by: Somnath Kotur Reviewed-by: Ajit Kumar Khaparde Signed-off-by: Somnath Kotur --- drivers/net/bnxt/bnxt_irq.c | 8 ++++++++ drivers/net/bnxt/bnxt_rxr.c | 3 +++ 2 files changed, 11 insertions(+) diff --git a/drivers/net/bnxt/bnxt_irq.c b/drivers/net/bnxt/bnxt_irq.c index 4feb637..846325e 100644 --- a/drivers/net/bnxt/bnxt_irq.c +++ b/drivers/net/bnxt/bnxt_irq.c @@ -37,6 +37,11 @@ void bnxt_int_handler(void *param) return; } + if (is_bnxt_in_error(bp)) { + pthread_mutex_unlock(&bp->def_cp_lock); + return; + } + cons = RING_CMP(cpr->cp_ring_struct, raw_cons); cmp = &cpr->cp_desc_ring[cons]; @@ -104,6 +109,9 @@ void bnxt_disable_int(struct bnxt *bp) if (BNXT_NUM_ASYNC_CPR(bp) == 0) return; + if (is_bnxt_in_error(bp)) + return; + if (!cpr || !cpr->cp_db.doorbell) return; diff --git a/drivers/net/bnxt/bnxt_rxr.c b/drivers/net/bnxt/bnxt_rxr.c index 03dae57..ee1444c 100644 --- a/drivers/net/bnxt/bnxt_rxr.c +++ b/drivers/net/bnxt/bnxt_rxr.c @@ -639,6 +639,9 @@ uint16_t bnxt_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, evt = bnxt_event_hwrm_resp_handler(rxq->bp, (struct cmpl_base *)rxcmp); + /* If the async event is Fatal error, return */ + if (unlikely(is_bnxt_in_error(rxq->bp))) + goto done; } raw_cons = NEXT_RAW_CMP(raw_cons); From patchwork Thu Oct 24 05:59:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 61815 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D36141C2B9; Thu, 24 Oct 2019 08:08:01 +0200 (CEST) Received: from relay.smtp.broadcom.com (unknown [192.19.211.62]) by dpdk.org (Postfix) with ESMTP id 108DD1C196 for ; Thu, 24 Oct 2019 08:07:01 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (bgccx-dev-host-lnx35.bec.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id 8D44C28FAB4; Wed, 23 Oct 2019 23:07:00 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com 8D44C28FAB4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1571897220; bh=R1G/lC8aAAh6c4GRCN4R7REYs3lFD+8cJnqmOjROPRA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=G1AKNEna5hC03QZkaTQonZu1KNg5/vlBcINFeUe0rJu8LIYZcEd865EEyBe99e/PJ zke+xPZQOcr71iI5i2g4K+aXtxp+utjykjoBtRM7/y8y7vWOS5qRvwvIWQr7lYfCyz JR4KK8BEUldktQ69yEixGYhsW+MjQg/0GUG32Msw= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Thu, 24 Oct 2019 11:29:09 +0530 Message-Id: <20191024055913.28817-15-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20191024055913.28817-1-somnath.kotur@broadcom.com> References: <20191024055913.28817-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 14/16] net/bnxt: add PCI IDs for 57500 series NPAR devices X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kalesh AP Add PCI IDs for 57500 series NPAR devices Signed-off-by: Kalesh AP Reviewed-by: Somnath Kotur Signed-off-by: Somnath Kotur --- drivers/net/bnxt/bnxt.h | 6 ++++++ drivers/net/bnxt/bnxt_ethdev.c | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index ffc37ea..9901ba9 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -64,6 +64,12 @@ #define BROADCOM_DEV_ID_57508 0x1750 #define BROADCOM_DEV_ID_57504 0x1751 #define BROADCOM_DEV_ID_57502 0x1752 +#define BROADCOM_DEV_ID_57508_MF1 0x1800 +#define BROADCOM_DEV_ID_57504_MF1 0x1801 +#define BROADCOM_DEV_ID_57502_MF1 0x1802 +#define BROADCOM_DEV_ID_57508_MF2 0x1803 +#define BROADCOM_DEV_ID_57504_MF2 0x1804 +#define BROADCOM_DEV_ID_57502_MF2 0x1805 #define BROADCOM_DEV_ID_57500_VF1 0x1806 #define BROADCOM_DEV_ID_57500_VF2 0x1807 #define BROADCOM_DEV_ID_58802 0xd802 diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 4187247..0bed4a2 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -83,6 +83,12 @@ { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) }, { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) }, { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) }, { .vendor_id = 0, /* sentinel */ }, }; From patchwork Thu Oct 24 05:59:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 61816 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id F37751C2EF; Thu, 24 Oct 2019 08:08:08 +0200 (CEST) Received: from relay.smtp.broadcom.com (relay.smtp.broadcom.com [192.19.211.62]) by dpdk.org (Postfix) with ESMTP id 5DAD21C025 for ; Thu, 24 Oct 2019 08:07:01 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (bgccx-dev-host-lnx35.bec.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id DA64C28FABA; Wed, 23 Oct 2019 23:07:00 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com DA64C28FABA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1571897221; bh=pztY8kSJFsbt7x7T95KUBzY01kpsZkl77pmj1kaD01A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Z2koWRfCqAl2fbLeSQGSTWkb2QbgCJ3XnFqxgz6SLOoMyRaBF8IVG09y0xTIPVdRg kDmgxXzMC9fAJ7Exti0Ukz60ii9oslq87Fvtpcr2hru6PgJ2lvflVi3cLmIuuSUB3N Ok8BgA5DfsoskIOzbAOn3Nn7qaXIQFTrlXp/IR8I= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Thu, 24 Oct 2019 11:29:10 +0530 Message-Id: <20191024055913.28817-16-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20191024055913.28817-1-somnath.kotur@broadcom.com> References: <20191024055913.28817-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 15/16] net/bnxt: add a wrapper function for thor device check X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kalesh AP This patch adds a wrapper function bnxt_thor_device() which checks for the pci device is Thor family. Signed-off-by: Kalesh AP Reviewed-by: Somnath Kotur Reviewed-by: Santoshkumar Karanappa Rastapur Signed-off-by: Somnath Kotur --- drivers/net/bnxt/bnxt_ethdev.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 0bed4a2..013b968 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -4074,6 +4074,24 @@ static bool bnxt_vf_pciid(uint16_t id) return false; } +static bool bnxt_thor_device(uint16_t id) +{ + if (id == BROADCOM_DEV_ID_57508 || + id == BROADCOM_DEV_ID_57504 || + id == BROADCOM_DEV_ID_57502 || + id == BROADCOM_DEV_ID_57508_MF1 || + id == BROADCOM_DEV_ID_57504_MF1 || + id == BROADCOM_DEV_ID_57502_MF1 || + id == BROADCOM_DEV_ID_57508_MF2 || + id == BROADCOM_DEV_ID_57504_MF2 || + id == BROADCOM_DEV_ID_57502_MF2 || + id == BROADCOM_DEV_ID_57500_VF1 || + id == BROADCOM_DEV_ID_57500_VF2) + return true; + + return false; +} + bool bnxt_stratus_device(struct bnxt *bp) { uint16_t id = bp->pdev->id.device_id; @@ -4716,11 +4734,7 @@ static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev) if (bnxt_vf_pciid(pci_dev->id.device_id)) bp->flags |= BNXT_FLAG_VF; - if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 || - pci_dev->id.device_id == BROADCOM_DEV_ID_57504 || - pci_dev->id.device_id == BROADCOM_DEV_ID_57502 || - pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 || - pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2) + if (bnxt_thor_device(pci_dev->id.device_id)) bp->flags |= BNXT_FLAG_THOR_CHIP; if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 || From patchwork Thu Oct 24 05:59:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 61817 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 897621C2B5; Thu, 24 Oct 2019 08:08:15 +0200 (CEST) Received: from relay.smtp.broadcom.com (relay.smtp.broadcom.com [192.19.211.62]) by dpdk.org (Postfix) with ESMTP id A9F2A1C190 for ; Thu, 24 Oct 2019 08:07:01 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (bgccx-dev-host-lnx35.bec.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id 3300E28FAC5; Wed, 23 Oct 2019 23:07:01 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com 3300E28FAC5 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1571897221; bh=JvmRPx2aeQSY8jooCeBPKI++BsMEOzDm2GnMz3hdTf0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kN3r3ABGlH3J/fxk7sjv+X+NAX009N1gUhCM5uhWoJA0gXV0e9+lfYVWdZfVPLDEJ PMLEmkZd+21mzOHrlT/rLSR/2BtXq74ch6+ddkGqrVH5qAT73FDhtWzx4CJa3T2VOd DyR30VB+EHHDgPwBA8Ky3GpisYvOoRmPZZcsoGys= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Thu, 24 Oct 2019 11:29:11 +0530 Message-Id: <20191024055913.28817-17-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20191024055913.28817-1-somnath.kotur@broadcom.com> References: <20191024055913.28817-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 16/16] net/bnxt: fix a possible memory leak X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kalesh AP During hot fw upgrade or error recovery, driver does cleanup and reallocation of resources. But driver reallocates memory for ring group info table without freeing the allocated memory during device init. Fix this memory leak by moving the freeing of ring group info table to bnxt_free_mem() in bnxt_uninit_resources(). Fixes: 4617e2125c7f ("net/bnxt: refactor init and uninit functions") Signed-off-by: Kalesh AP Reviewed-by: Santoshkumar Karanappa Rastapur Signed-off-by: Somnath Kotur --- drivers/net/bnxt/bnxt_ethdev.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 013b968..9642796 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -183,6 +183,9 @@ static void bnxt_free_mem(struct bnxt *bp, bool reconfig) } bnxt_free_async_cp_ring(bp); bnxt_free_rxtx_nq_ring(bp); + + rte_free(bp->grp_info); + bp->grp_info = NULL; } static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig) @@ -4821,11 +4824,6 @@ static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev) rc = bnxt_uninit_resources(bp, false); - if (bp->grp_info != NULL) { - rte_free(bp->grp_info); - bp->grp_info = NULL; - } - if (bp->tx_mem_zone) { rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone); bp->tx_mem_zone = NULL; From patchwork Thu Oct 24 05:59:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 61818 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 948011C2EE; Thu, 24 Oct 2019 08:08:18 +0200 (CEST) Received: from relay.smtp.broadcom.com (unknown [192.19.211.62]) by dpdk.org (Postfix) with ESMTP id 0F1BF1C033 for ; Thu, 24 Oct 2019 08:07:02 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (bgccx-dev-host-lnx35.bec.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id 7F9F528FAD2; Wed, 23 Oct 2019 23:07:01 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com 7F9F528FAD2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1571897221; bh=zPbFlv2PAvKWn3BYenD5OoIxF138g4l4FNkenSz/QGA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=J/PGOe5TKN0DWhUtwM3pE/3mh6CAYT9pQsf8Z2xb0/JGpoUkw7rvq1rc8Bt0fS1zb 5atSffZspf68tvzvGKU3wJy2bb1JP4upLY14v1xvzSeVBwVGk8Le+8x2XmnigHMLz7 +gt37e6UgwgNn0Y27r89F27V7pPnPnwhq0GHTTxA= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Thu, 24 Oct 2019 11:29:12 +0530 Message-Id: <20191024055913.28817-18-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20191024055913.28817-1-somnath.kotur@broadcom.com> References: <20191024055913.28817-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 17/17] net/bnxt: fix mbuf free when clearing Tx queue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Lance Richardson When freeing pending transmit mbufs, use rte_pktmbuf_free_seg() instead of rte_pktmbuf_free(), otherwise linked mbufs may be freed more than once. Fixes: 6eb3cc2294fd ("net/bnxt: add initial Tx code") Reviewed-by: Ajit Kumar Khaparde Reviewed-by: Somnath Kotur Signed-off-by: Somnath Kotur --- drivers/net/bnxt/bnxt_txq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/bnxt/bnxt_txq.c b/drivers/net/bnxt/bnxt_txq.c index ebb9199..6b866d4 100644 --- a/drivers/net/bnxt/bnxt_txq.c +++ b/drivers/net/bnxt/bnxt_txq.c @@ -34,7 +34,7 @@ static void bnxt_tx_queue_release_mbufs(struct bnxt_tx_queue *txq) if (sw_ring) { for (i = 0; i < txq->tx_ring->tx_ring_struct->ring_size; i++) { if (sw_ring[i].mbuf) { - rte_pktmbuf_free(sw_ring[i].mbuf); + rte_pktmbuf_free_seg(sw_ring[i].mbuf); sw_ring[i].mbuf = NULL; } } From patchwork Thu Oct 24 05:59:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 61819 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 05FF31D127; Thu, 24 Oct 2019 08:08:21 +0200 (CEST) Received: from relay.smtp.broadcom.com (unknown [192.19.211.62]) by dpdk.org (Postfix) with ESMTP id 7118F1C025 for ; Thu, 24 Oct 2019 08:07:02 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (bgccx-dev-host-lnx35.bec.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id D5B5A28FAE3; Wed, 23 Oct 2019 23:07:01 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com D5B5A28FAE3 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1571897222; bh=TYQsLLZ1LJP8zEDbe3xInpicZ315cZbf/7EbzGNyW2s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tQg+x1xCCkbtloWYam5DMXfCW0fTIK1WIEOxS/4+qHZSpWpR0Qu5BfuBbpSfWqyCH yZhtNM/nYLvIpPqpnLZ9re9HJsN809bM/SHPql9eXomHlA+MT8PAaFodXE+xmKuxna 0z93rqSllrWwXj8d5tfsPKSJulDv7AQnXhmRFQCU= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Thu, 24 Oct 2019 11:29:13 +0530 Message-Id: <20191024055913.28817-19-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20191024055913.28817-1-somnath.kotur@broadcom.com> References: <20191024055913.28817-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 18/18] net/bnxt: call bnxt_uninit_locks from bnxt_uninit_resources X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Venkat Duvvuru Currently, bnxt_uninit_locks is called inside bnxt_dev_uninit. However, the more appropriate place to call it is inside bnxt_uninit_resources. This is more logical, as all the resources uninitialization is happening inside bnxt_uninit_resources. Signed-off-by: Venkat Duvvuru Signed-off-by: Somnath Kotur --- drivers/net/bnxt/bnxt_ethdev.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index e7ec99e..744f715 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -4772,6 +4772,7 @@ bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev) } } + bnxt_uninit_locks(bp); rte_free(bp->ptp_cfg); bp->ptp_cfg = NULL; return rc; @@ -4813,8 +4814,6 @@ bnxt_dev_uninit(struct rte_eth_dev *eth_dev) eth_dev->rx_pkt_burst = NULL; eth_dev->tx_pkt_burst = NULL; - bnxt_uninit_locks(bp); - return rc; }