From patchwork Fri Aug 30 06:28:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 58288 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 162DA1E570; Fri, 30 Aug 2019 08:31:55 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 649BB1BECA for ; Fri, 30 Aug 2019 08:31:54 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x7U6UO7W027743; Thu, 29 Aug 2019 23:31:52 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=WcDp0ILVcGPqiiIpPNNUtESSeTlcTgXPemgymQQEzj4=; b=lCzaSRqcOrolwGOBIejVBaNX/nyYc8bVSZqiEsk3gyRuSUU6NfgC4P0WatjHK8Vcbph5 DH6/cEKangKj5iPM7/jBt7VjMc2cMay1iYDa5rtEa103d/N5Uj109tXKCHAim3q7ZeNb M/iOywtQNIDKYR1wV0GhUAWVKkQ34UMyf2G3dn9MZvkgj1FCK0TMp+vJMmb48fP7Ngt3 bP1GAFUUgtUH2r2sk15OjESrmo8x48lBkVAA/oTln/ldwp+CNkGdaZDsrrzsf+lRnsQM jhHm4Yq4siQ2A9qwwQINmTqfgJ1s/yhbAMUABulVbskhzsyBZ5jUWpcmvZUsZYxc4emy cw== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0b-0016f401.pphosted.com with ESMTP id 2uk4rkyg1m-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2019 23:31:52 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Thu, 29 Aug 2019 23:31:50 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Thu, 29 Aug 2019 23:31:50 -0700 Received: from ajoseph83.caveonetworks.com.com (unknown [10.29.45.56]) by maili.marvell.com (Postfix) with ESMTP id 2B0563F703F; Thu, 29 Aug 2019 23:31:46 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Pablo de Lara , Thomas Monjalon CC: Ankur Dwivedi , Jerin Jacob , Narayana Prasad , Anoob Joseph , Tejasree Kondoj , Date: Fri, 30 Aug 2019 11:58:11 +0530 Message-ID: <1567146501-8224-2-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1567146501-8224-1-git-send-email-anoobj@marvell.com> References: <1567146501-8224-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.70,1.0.8 definitions=2019-08-30_02:2019-08-29,2019-08-30 signatures=0 Subject: [dpdk-dev] [PATCH 01/11] crypto/octeontx2: add PMD skeleton X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ankur Dwivedi Adding OCTEON TX2 crypto PMD skeleton. Enabling the driver by default in common_base. Signed-off-by: Ankur Dwivedi Signed-off-by: Anoob Joseph Signed-off-by: Tejasree Kondoj --- config/common_base | 5 + drivers/common/Makefile | 5 +- drivers/crypto/Makefile | 1 + drivers/crypto/meson.build | 4 +- drivers/crypto/octeontx2/Makefile | 37 +++++++ drivers/crypto/octeontx2/meson.build | 29 +++++ drivers/crypto/octeontx2/otx2_cryptodev.c | 118 +++++++++++++++++++++ drivers/crypto/octeontx2/otx2_cryptodev.h | 25 +++++ drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 27 +++++ drivers/crypto/octeontx2/otx2_cryptodev_ops.h | 12 +++ .../octeontx2/rte_pmd_octeontx2_crypto_version.map | 4 + mk/rte.app.mk | 6 +- 12 files changed, 269 insertions(+), 4 deletions(-) create mode 100644 drivers/crypto/octeontx2/Makefile create mode 100644 drivers/crypto/octeontx2/meson.build create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev.c create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev.h create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_ops.c create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_ops.h create mode 100644 drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map diff --git a/config/common_base b/config/common_base index 8ef75c2..b8143ea 100644 --- a/config/common_base +++ b/config/common_base @@ -593,6 +593,11 @@ CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4 CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y # +# Compile PMD for Marvell OCTEON TX2 crypto device +# +CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO=y + +# # Compile PMD for QuickAssist based devices - see docs for details # CONFIG_RTE_LIBRTE_PMD_QAT=y diff --git a/drivers/common/Makefile b/drivers/common/Makefile index bc6f972..1ff033b 100644 --- a/drivers/common/Makefile +++ b/drivers/common/Makefile @@ -4,7 +4,9 @@ include $(RTE_SDK)/mk/rte.vars.mk -ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO),y) +CPT-y := $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) +CPT-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) +ifneq (,$(findstring y,$(CPT-y))) DIRS-y += cpt endif @@ -12,6 +14,7 @@ ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF)$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOO DIRS-y += octeontx endif OCTEONTX2-y := $(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL) +OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) ifeq ($(findstring y,$(OCTEONTX2-y)),y) DIRS-y += octeontx2 endif diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index 009f844..0ac999c 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -8,6 +8,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_MB) += aesni_mb DIRS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO) += armv8 DIRS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += ccp DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += octeontx +DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += octeontx2 DIRS-$(CONFIG_RTE_LIBRTE_PMD_OPENSSL) += openssl DIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += scheduler DIRS-$(CONFIG_RTE_LIBRTE_PMD_SNOW3G) += snow3g diff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build index 83e7886..3c88f3c 100644 --- a/drivers/crypto/meson.build +++ b/drivers/crypto/meson.build @@ -2,8 +2,8 @@ # Copyright(c) 2017 Intel Corporation drivers = ['aesni_gcm', 'aesni_mb', 'caam_jr', 'ccp', 'dpaa_sec', 'dpaa2_sec', - 'kasumi', 'mvsam', 'null', 'octeontx', 'openssl', 'qat', 'scheduler', - 'snow3g', 'virtio', 'zuc'] + 'kasumi', 'mvsam', 'null', 'octeontx', 'octeontx2', 'openssl', 'qat', + 'scheduler', 'snow3g', 'virtio', 'zuc'] std_deps = ['cryptodev'] # cryptodev pulls in all other needed deps config_flag_fmt = 'RTE_LIBRTE_@0@_PMD' diff --git a/drivers/crypto/octeontx2/Makefile b/drivers/crypto/octeontx2/Makefile new file mode 100644 index 0000000..3273178 --- /dev/null +++ b/drivers/crypto/octeontx2/Makefile @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (C) 2019 Marvell International Ltd. +# + +include $(RTE_SDK)/mk/rte.vars.mk + +# library name +LIB = librte_pmd_octeontx2_crypto.a + +# library version +LIBABIVER := 1 + +# build flags +CFLAGS += $(WERROR_FLAGS) + +LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring +LDLIBS += -lrte_cryptodev +LDLIBS += -lrte_pci -lrte_bus_pci +LDLIBS += -lrte_common_cpt -lrte_common_octeontx2 + +VPATH += $(RTE_SDK)/drivers/crypto/octeontx2 + +CFLAGS += -O3 +CFLAGS += -I$(RTE_SDK)/drivers/common/cpt +CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2 + +# PMD code +SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_ops.c + +# export include files +SYMLINK-y-include += + +# versioning export map +EXPORT_MAP := rte_pmd_octeontx2_crypto_version.map + +include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build new file mode 100644 index 0000000..2b55d2a --- /dev/null +++ b/drivers/crypto/octeontx2/meson.build @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (C) 2019 Marvell International Ltd. + +if host_machine.system() != 'linux' + build = false +endif + +deps += ['bus_pci'] +deps += ['common_cpt'] +deps += ['common_octeontx2'] +name = 'octeontx2_crypto' + +sources = files('otx2_cryptodev.c', + 'otx2_cryptodev_ops.c') + +extra_flags = [] +# This integrated controller runs only on a arm64 machine, remove 32bit warnings +if not dpdk_conf.get('RTE_ARCH_64') + extra_flags += ['-Wno-int-to-pointer-cast', '-Wno-pointer-to-int-cast'] +endif + +foreach flag: extra_flags + if cc.has_argument(flag) + cflags += flag + endif +endforeach + +includes += include_directories('../../common/cpt') +includes += include_directories('../../common/octeontx2') diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.c b/drivers/crypto/octeontx2/otx2_cryptodev.c new file mode 100644 index 0000000..cf3a010 --- /dev/null +++ b/drivers/crypto/octeontx2/otx2_cryptodev.c @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C) 2019 Marvell International Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* CPT common headers */ +#include "cpt_common.h" +#include "cpt_pmd_logs.h" + +#include "otx2_common.h" +#include "otx2_cryptodev.h" +#include "otx2_cryptodev_ops.h" + +static int otx2_cryptodev_logtype; + +static struct rte_pci_id pci_id_cpt_table[] = { + { + RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, + PCI_DEVID_OCTEONTX2_RVU_CPT_VF) + }, + /* sentinel */ + { + .device_id = 0 + }, +}; + +static int +otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, + struct rte_pci_device *pci_dev) +{ + struct rte_cryptodev_pmd_init_params init_params = { + .name = "", + .socket_id = rte_socket_id(), + .private_data_size = sizeof(struct otx2_cpt_vf) + }; + char name[RTE_CRYPTODEV_NAME_MAX_LEN]; + struct rte_cryptodev *dev; + int ret; + + /* Initialize logtype used in common */ + cpt_logtype = otx2_cryptodev_logtype; + + rte_pci_device_name(&pci_dev->addr, name, sizeof(name)); + + dev = rte_cryptodev_pmd_create(name, &pci_dev->device, &init_params); + if (dev == NULL) { + ret = -ENODEV; + goto exit; + } + + dev->dev_ops = &otx2_cpt_ops; + + dev->driver_id = otx2_cryptodev_driver_id; + + dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | + RTE_CRYPTODEV_FF_HW_ACCELERATED | + RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING | + RTE_CRYPTODEV_FF_IN_PLACE_SGL | + RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT | + RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT; + + return 0; + +exit: + CPT_LOG_ERR("Could not create device (vendor_id: 0x%x device_id: 0x%x)", + pci_dev->id.vendor_id, pci_dev->id.device_id); + return ret; +} + +static int +otx2_cpt_pci_remove(struct rte_pci_device *pci_dev) +{ + char name[RTE_CRYPTODEV_NAME_MAX_LEN]; + struct rte_cryptodev *dev; + + if (pci_dev == NULL) + return -EINVAL; + + rte_pci_device_name(&pci_dev->addr, name, sizeof(name)); + + dev = rte_cryptodev_pmd_get_named_dev(name); + if (dev == NULL) + return -ENODEV; + + return rte_cryptodev_pmd_destroy(dev); +} + +static struct rte_pci_driver otx2_cryptodev_pmd = { + .id_table = pci_id_cpt_table, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING, + .probe = otx2_cpt_pci_probe, + .remove = otx2_cpt_pci_remove, +}; + +static struct cryptodev_driver otx2_cryptodev_drv; + +RTE_INIT(otx2_cpt_init_log); +RTE_PMD_REGISTER_PCI(CRYPTODEV_NAME_OCTEONTX2_PMD, otx2_cryptodev_pmd); +RTE_PMD_REGISTER_PCI_TABLE(CRYPTODEV_NAME_OCTEONTX2_PMD, pci_id_cpt_table); +RTE_PMD_REGISTER_CRYPTO_DRIVER(otx2_cryptodev_drv, otx2_cryptodev_pmd.driver, + otx2_cryptodev_driver_id); + +RTE_INIT(otx2_cpt_init_log) +{ + /* Bus level logs */ + otx2_cryptodev_logtype = rte_log_register("pmd.crypto.octeontx2"); + if (otx2_cryptodev_logtype >= 0) + rte_log_set_level(otx2_cryptodev_logtype, RTE_LOG_NOTICE); +} diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.h b/drivers/crypto/octeontx2/otx2_cryptodev.h new file mode 100644 index 0000000..da0f653 --- /dev/null +++ b/drivers/crypto/octeontx2/otx2_cryptodev.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C) 2019 Marvell International Ltd. + */ + +#ifndef _OTX2_CRYPTODEV_H_ +#define _OTX2_CRYPTODEV_H_ + +#include "cpt_common.h" + +/* Marvell OCTEON TX2 Crypto PMD device name */ +#define CRYPTODEV_NAME_OCTEONTX2_PMD crypto_octeontx2 + +/** + * Device private data + */ +struct otx2_cpt_vf { + /* To be populated */ +}; + +/* + * Crypto device driver ID + */ +uint8_t otx2_cryptodev_driver_id; + +#endif /* _OTX2_CRYPTODEV_H_ */ diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c new file mode 100644 index 0000000..18ad470 --- /dev/null +++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C) 2019 Marvell International Ltd. + */ + +#include + +#include "otx2_cryptodev_ops.h" + +struct rte_cryptodev_ops otx2_cpt_ops = { + /* Device control ops */ + .dev_configure = NULL, + .dev_start = NULL, + .dev_stop = NULL, + .dev_close = NULL, + .dev_infos_get = NULL, + + .stats_get = NULL, + .stats_reset = NULL, + .queue_pair_setup = NULL, + .queue_pair_release = NULL, + .queue_pair_count = NULL, + + /* Symmetric crypto ops */ + .sym_session_get_size = NULL, + .sym_session_configure = NULL, + .sym_session_clear = NULL, +}; diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h new file mode 100644 index 0000000..545614e --- /dev/null +++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C) 2019 Marvell International Ltd. + */ + +#ifndef _OTX2_CRYPTODEV_OPS_H_ +#define _OTX2_CRYPTODEV_OPS_H_ + +#include + +struct rte_cryptodev_ops otx2_cpt_ops; + +#endif /* _OTX2_CRYPTODEV_OPS_H_ */ diff --git a/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map new file mode 100644 index 0000000..9a61188 --- /dev/null +++ b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map @@ -0,0 +1,4 @@ +DPDK_19.08 { + + local: *; +}; diff --git a/mk/rte.app.mk b/mk/rte.app.mk index ba5c39e..f85e50e 100644 --- a/mk/rte.app.mk +++ b/mk/rte.app.mk @@ -101,7 +101,9 @@ ifeq ($(CONFIG_RTE_EXEC_ENV_LINUX),y) _LDLIBS-$(CONFIG_RTE_LIBRTE_KNI) += -lrte_kni endif -ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO),y) +OTX-CPT-y := $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) +OTX-CPT-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) +ifeq ($(findstring y,$(OTX-CPT-y)),y) _LDLIBS-y += -lrte_common_cpt endif @@ -109,6 +111,7 @@ ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF)$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOO _LDLIBS-y += -lrte_common_octeontx endif OCTEONTX2-y := $(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL) +OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV) OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD) @@ -268,6 +271,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO) += -lrte_pmd_armv8 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO) += -L$(ARMV8_CRYPTO_LIB_PATH) -larmv8_crypto _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO) += -L$(LIBMUSDK_PATH)/lib -lrte_pmd_mvsam_crypto -lmusdk _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += -lrte_pmd_octeontx_crypto +_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += -lrte_pmd_octeontx2_crypto _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += -lrte_pmd_crypto_scheduler ifeq ($(CONFIG_RTE_LIBRTE_SECURITY),y) ifeq ($(CONFIG_RTE_EAL_VFIO)$(CONFIG_RTE_LIBRTE_FSLMC_BUS),yy) From patchwork Fri Aug 30 06:28:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 58289 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 13BDA1E86F; Fri, 30 Aug 2019 08:31:59 +0200 (CEST) Received: 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([199.233.58.184]) by mx0b-0016f401.pphosted.com with ESMTP id 2uk4rkyg1u-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2019 23:31:57 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Thu, 29 Aug 2019 23:31:55 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Thu, 29 Aug 2019 23:31:55 -0700 Received: from ajoseph83.caveonetworks.com.com (unknown [10.29.45.56]) by maili.marvell.com (Postfix) with ESMTP id 9D2A83F703F; Thu, 29 Aug 2019 23:31:52 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Pablo de Lara , Thomas Monjalon CC: Anoob Joseph , Jerin Jacob , Narayana Prasad , Ankur Dwivedi , Tejasree Kondoj , Date: Fri, 30 Aug 2019 11:58:12 +0530 Message-ID: <1567146501-8224-3-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1567146501-8224-1-git-send-email-anoobj@marvell.com> References: <1567146501-8224-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.70,1.0.8 definitions=2019-08-30_02:2019-08-29,2019-08-30 signatures=0 Subject: [dpdk-dev] [PATCH 02/11] crypto/octeontx2: add device init sequence in probe X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds the device init sequence for OCTEON TX2 crypto device. Signed-off-by: Ankur Dwivedi Signed-off-by: Anoob Joseph Signed-off-by: Tejasree Kondoj --- drivers/crypto/octeontx2/Makefile | 10 +++++++ drivers/crypto/octeontx2/meson.build | 2 ++ drivers/crypto/octeontx2/otx2_cryptodev.c | 40 ++++++++++++++++++++++++++ drivers/crypto/octeontx2/otx2_cryptodev.h | 10 ++++++- drivers/crypto/octeontx2/otx2_cryptodev_mbox.c | 30 +++++++++++++++++++ drivers/crypto/octeontx2/otx2_cryptodev_mbox.h | 13 +++++++++ 6 files changed, 104 insertions(+), 1 deletion(-) create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_mbox.c create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_mbox.h diff --git a/drivers/crypto/octeontx2/Makefile b/drivers/crypto/octeontx2/Makefile index 3273178..10d8c39 100644 --- a/drivers/crypto/octeontx2/Makefile +++ b/drivers/crypto/octeontx2/Makefile @@ -23,9 +23,19 @@ VPATH += $(RTE_SDK)/drivers/crypto/octeontx2 CFLAGS += -O3 CFLAGS += -I$(RTE_SDK)/drivers/common/cpt CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2 +CFLAGS += -I$(RTE_SDK)/drivers/mempool/octeontx2 + +ifneq ($(CONFIG_RTE_ARCH_64),y) +CFLAGS += -Wno-int-to-pointer-cast +CFLAGS += -Wno-pointer-to-int-cast +ifeq ($(CONFIG_RTE_TOOLCHAIN_ICC),y) +CFLAGS += -diag-disable 2259 +endif +endif # PMD code SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_mbox.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_ops.c # export include files diff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build index 2b55d2a..845d50d 100644 --- a/drivers/crypto/octeontx2/meson.build +++ b/drivers/crypto/octeontx2/meson.build @@ -11,6 +11,7 @@ deps += ['common_octeontx2'] name = 'octeontx2_crypto' sources = files('otx2_cryptodev.c', + 'otx2_cryptodev_mbox.c', 'otx2_cryptodev_ops.c') extra_flags = [] @@ -27,3 +28,4 @@ endforeach includes += include_directories('../../common/cpt') includes += include_directories('../../common/octeontx2') +includes += include_directories('../../mempool/octeontx2') diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.c b/drivers/crypto/octeontx2/otx2_cryptodev.c index cf3a010..814b9ed 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev.c @@ -18,7 +18,9 @@ #include "otx2_common.h" #include "otx2_cryptodev.h" +#include "otx2_cryptodev_mbox.h" #include "otx2_cryptodev_ops.h" +#include "otx2_dev.h" static int otx2_cryptodev_logtype; @@ -44,6 +46,9 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, }; char name[RTE_CRYPTODEV_NAME_MAX_LEN]; struct rte_cryptodev *dev; + struct otx2_dev *otx2_dev; + struct otx2_cpt_vf *vf; + uint16_t nb_queues; int ret; /* Initialize logtype used in common */ @@ -61,6 +66,37 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, dev->driver_id = otx2_cryptodev_driver_id; + /* Get private data space allocated */ + vf = dev->data->dev_private; + + otx2_dev = &vf->otx2_dev; + + /* Initialize the base otx2_dev object */ + ret = otx2_dev_init(pci_dev, otx2_dev); + if (ret) { + CPT_LOG_ERR("Could not initialize otx2_dev"); + goto pmd_destroy; + } + + /* Get number of queues available on the device */ + ret = otx2_cpt_available_queues_get(dev, &nb_queues); + if (ret) { + CPT_LOG_ERR("Could not determine the number of queues available"); + goto otx2_dev_fini; + } + + /* Don't exceed the limits set per VF */ + nb_queues = RTE_MIN(nb_queues, OTX2_CPT_MAX_QUEUES_PER_VF); + + if (nb_queues == 0) { + CPT_LOG_ERR("No free queues available on the device"); + goto otx2_dev_fini; + } + + vf->max_queues = nb_queues; + + CPT_LOG_INFO("Max queues supported by device: %d", vf->max_queues); + dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | RTE_CRYPTODEV_FF_HW_ACCELERATED | RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING | @@ -70,6 +106,10 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, return 0; +otx2_dev_fini: + otx2_dev_fini(pci_dev, otx2_dev); +pmd_destroy: + rte_cryptodev_pmd_destroy(dev); exit: CPT_LOG_ERR("Could not create device (vendor_id: 0x%x device_id: 0x%x)", pci_dev->id.vendor_id, pci_dev->id.device_id); diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.h b/drivers/crypto/octeontx2/otx2_cryptodev.h index da0f653..531bd6d 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev.h +++ b/drivers/crypto/octeontx2/otx2_cryptodev.h @@ -7,14 +7,22 @@ #include "cpt_common.h" +#include "otx2_dev.h" + /* Marvell OCTEON TX2 Crypto PMD device name */ #define CRYPTODEV_NAME_OCTEONTX2_PMD crypto_octeontx2 +#define OTX2_CPT_MAX_LFS 64 +#define OTX2_CPT_MAX_QUEUES_PER_VF 64 + /** * Device private data */ struct otx2_cpt_vf { - /* To be populated */ + struct otx2_dev otx2_dev; + /**< Base class */ + uint16_t max_queues; + /**< Max queues supported */ }; /* diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c new file mode 100644 index 0000000..48d86ef --- /dev/null +++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C) 2019 Marvell International Ltd. + */ +#include + +#include "cpt_pmd_logs.h" + +#include "otx2_cryptodev.h" +#include "otx2_cryptodev_mbox.h" +#include "otx2_dev.h" +#include "otx2_mbox.h" + +int +otx2_cpt_available_queues_get(const struct rte_cryptodev *dev, + uint16_t *nb_queues) +{ + struct otx2_cpt_vf *vf = dev->data->dev_private; + struct otx2_dev *otx2_dev = &vf->otx2_dev; + struct free_rsrcs_rsp *rsp; + int ret; + + otx2_mbox_alloc_msg_free_rsrc_cnt(otx2_dev->mbox); + + ret = otx2_mbox_process_msg(otx2_dev->mbox, (void *)&rsp); + if (ret) + return -EIO; + + *nb_queues = rsp->cpt; + return 0; +} diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h new file mode 100644 index 0000000..648c009 --- /dev/null +++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C) 2019 Marvell International Ltd. + */ + +#ifndef _OTX2_CRYPTODEV_MBOX_H_ +#define _OTX2_CRYPTODEV_MBOX_H_ + +#include + +int otx2_cpt_available_queues_get(const struct rte_cryptodev *dev, + uint16_t *nb_queues); + +#endif /* _OTX2_CRYPTODEV_MBOX_H_ */ From patchwork Fri Aug 30 06:28:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 58290 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 3904C1E883; Fri, 30 Aug 2019 08:32:13 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id A46B51E87D for ; Fri, 30 Aug 2019 08:32:11 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x7U6ULDM027723; Thu, 29 Aug 2019 23:32:11 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; 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Thu, 29 Aug 2019 23:32:05 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Pablo de Lara , Thomas Monjalon CC: Ankur Dwivedi , Jerin Jacob , Narayana Prasad , Anoob Joseph , Tejasree Kondoj , Date: Fri, 30 Aug 2019 11:58:13 +0530 Message-ID: <1567146501-8224-4-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1567146501-8224-1-git-send-email-anoobj@marvell.com> References: <1567146501-8224-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.70,1.0.8 definitions=2019-08-30_02:2019-08-29,2019-08-30 signatures=0 Subject: [dpdk-dev] [PATCH 03/11] crypto/octeontx2: add device control ops X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ankur Dwivedi This patch adds the device control functions. Signed-off-by: Ankur Dwivedi Signed-off-by: Anoob Joseph Signed-off-by: Tejasree Kondoj --- drivers/crypto/octeontx2/Makefile | 1 + drivers/crypto/octeontx2/meson.build | 1 + drivers/crypto/octeontx2/otx2_cryptodev.h | 6 + .../crypto/octeontx2/otx2_cryptodev_hw_access.c | 126 +++++++++++++++++++++ .../crypto/octeontx2/otx2_cryptodev_hw_access.h | 27 +++++ drivers/crypto/octeontx2/otx2_cryptodev_mbox.c | 64 +++++++++++ drivers/crypto/octeontx2/otx2_cryptodev_mbox.h | 6 + drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 123 +++++++++++++++++++- drivers/crypto/octeontx2/otx2_cryptodev_ops.h | 3 + 9 files changed, 352 insertions(+), 5 deletions(-) create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h diff --git a/drivers/crypto/octeontx2/Makefile b/drivers/crypto/octeontx2/Makefile index 10d8c39..71bc4d1 100644 --- a/drivers/crypto/octeontx2/Makefile +++ b/drivers/crypto/octeontx2/Makefile @@ -35,6 +35,7 @@ endif # PMD code SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_hw_access.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_mbox.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_ops.c diff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build index 845d50d..944fa2c 100644 --- a/drivers/crypto/octeontx2/meson.build +++ b/drivers/crypto/octeontx2/meson.build @@ -11,6 +11,7 @@ deps += ['common_octeontx2'] name = 'octeontx2_crypto' sources = files('otx2_cryptodev.c', + 'otx2_cryptodev_hw_access.c', 'otx2_cryptodev_mbox.c', 'otx2_cryptodev_ops.c') diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.h b/drivers/crypto/octeontx2/otx2_cryptodev.h index 531bd6d..941bbc4 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev.h +++ b/drivers/crypto/octeontx2/otx2_cryptodev.h @@ -23,6 +23,12 @@ struct otx2_cpt_vf { /**< Base class */ uint16_t max_queues; /**< Max queues supported */ + uint8_t nb_queues; + /**< Number of crypto queues attached */ + uint16_t lf_msixoff[OTX2_CPT_MAX_LFS]; + /**< MSI-X offsets */ + uint8_t err_intr_registered:1; + /**< Are error interrupts registered? */ }; /* diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c new file mode 100644 index 0000000..88b5510 --- /dev/null +++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C) 2019 Marvell International Ltd. + */ + +#include "cpt_pmd_logs.h" + +#include "otx2_common.h" +#include "otx2_cryptodev.h" +#include "otx2_cryptodev_hw_access.h" + +static void +otx2_cpt_lf_err_intr_handler(void *param) +{ + uintptr_t base = (uintptr_t)param; + uint8_t lf_id; + uint64_t intr; + + lf_id = (base >> 12) & 0xFF; + + intr = otx2_read64(base + OTX2_CPT_LF_MISC_INT); + if (intr == 0) + return; + + CPT_LOG_ERR("LF %d MISC_INT: 0x%" PRIx64 "", lf_id, intr); + + /* Clear interrupt */ + otx2_write64(intr, base + OTX2_CPT_LF_MISC_INT); +} + +static void +otx2_cpt_lf_err_intr_unregister(const struct rte_cryptodev *dev, + uint16_t msix_off, uintptr_t base) +{ + struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); + struct rte_intr_handle *handle = &pci_dev->intr_handle; + + /* Disable error interrupts */ + otx2_write64(~0ull, base + OTX2_CPT_LF_MISC_INT_ENA_W1C); + + otx2_unregister_irq(handle, otx2_cpt_lf_err_intr_handler, (void *)base, + msix_off); +} + +void +otx2_cpt_err_intr_unregister(const struct rte_cryptodev *dev) +{ + struct otx2_cpt_vf *vf = dev->data->dev_private; + uintptr_t base; + uint32_t i; + + for (i = 0; i < vf->nb_queues; i++) { + base = OTX2_CPT_LF_BAR2(vf, i); + otx2_cpt_lf_err_intr_unregister(dev, vf->lf_msixoff[i], base); + } + + vf->err_intr_registered = 0; +} + +static int +otx2_cpt_lf_err_intr_register(const struct rte_cryptodev *dev, + uint16_t msix_off, uintptr_t base) +{ + struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); + struct rte_intr_handle *handle = &pci_dev->intr_handle; + int ret; + + /* Disable error interrupts */ + otx2_write64(~0ull, base + OTX2_CPT_LF_MISC_INT_ENA_W1C); + + /* Register error interrupt handler */ + ret = otx2_register_irq(handle, otx2_cpt_lf_err_intr_handler, + (void *)base, msix_off); + if (ret) + return ret; + + /* Enable error interrupts */ + otx2_write64(~0ull, base + OTX2_CPT_LF_MISC_INT_ENA_W1S); + + return 0; +} + +int +otx2_cpt_err_intr_register(const struct rte_cryptodev *dev) +{ + struct otx2_cpt_vf *vf = dev->data->dev_private; + uint32_t i, j, ret; + uintptr_t base; + + for (i = 0; i < vf->nb_queues; i++) { + if (vf->lf_msixoff[i] == MSIX_VECTOR_INVALID) { + CPT_LOG_ERR("Invalid CPT LF MSI-X offset: 0x%x", + vf->lf_msixoff[i]); + return -EINVAL; + } + } + + for (i = 0; i < vf->nb_queues; i++) { + base = OTX2_CPT_LF_BAR2(vf, i); + ret = otx2_cpt_lf_err_intr_register(dev, vf->lf_msixoff[i], + base); + if (ret) + goto intr_unregister; + } + + vf->err_intr_registered = 1; + return 0; + +intr_unregister: + /* Unregister the ones already registered */ + for (j = 0; j < i; j++) { + base = OTX2_CPT_LF_BAR2(vf, j); + otx2_cpt_lf_err_intr_unregister(dev, vf->lf_msixoff[j], base); + } + + /* + * Failed to register error interrupt. Not returning error as this would + * prevent application from enabling larger number of devs. + * + * This failure is a known issue because otx2_dev_init() initializes + * interrupts based on static values from ATF, and the actual number + * of interrupts needed (which is based on LFs) can be determined only + * after otx2_dev_init() sets up interrupts which includes mbox + * interrupts. + */ + return 0; +} diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h new file mode 100644 index 0000000..2af674d --- /dev/null +++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C) 2019 Marvell International Ltd. + */ + +#ifndef _OTX2_CRYPTODEV_HW_ACCESS_H_ +#define _OTX2_CRYPTODEV_HW_ACCESS_H_ + +#include + +#include "otx2_dev.h" + +/* Register offsets */ + +/* CPT LF registers */ +#define OTX2_CPT_LF_MISC_INT 0xb0ull +#define OTX2_CPT_LF_MISC_INT_ENA_W1S 0xd0ull +#define OTX2_CPT_LF_MISC_INT_ENA_W1C 0xe0ull + +#define OTX2_CPT_LF_BAR2(vf, q_id) \ + ((vf)->otx2_dev.bar2 + \ + ((RVU_BLOCK_ADDR_CPT0 << 20) | ((q_id) << 12))) + +void otx2_cpt_err_intr_unregister(const struct rte_cryptodev *dev); + +int otx2_cpt_err_intr_register(const struct rte_cryptodev *dev); + +#endif /* _OTX2_CRYPTODEV_HW_ACCESS_H_ */ diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c index 48d86ef..a11aef5 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c @@ -28,3 +28,67 @@ otx2_cpt_available_queues_get(const struct rte_cryptodev *dev, *nb_queues = rsp->cpt; return 0; } + +int +otx2_cpt_queues_attach(const struct rte_cryptodev *dev, uint8_t nb_queues) +{ + struct otx2_cpt_vf *vf = dev->data->dev_private; + struct otx2_mbox *mbox = vf->otx2_dev.mbox; + struct rsrc_attach_req *req; + + /* Ask AF to attach required LFs */ + + req = otx2_mbox_alloc_msg_attach_resources(mbox); + + /* 1 LF = 1 queue */ + req->cptlfs = nb_queues; + + if (otx2_mbox_process(mbox) < 0) + return -EIO; + + /* Update number of attached queues */ + vf->nb_queues = nb_queues; + + return 0; +} + +int +otx2_cpt_queues_detach(const struct rte_cryptodev *dev) +{ + struct otx2_cpt_vf *vf = dev->data->dev_private; + struct otx2_mbox *mbox = vf->otx2_dev.mbox; + struct rsrc_detach_req *req; + + req = otx2_mbox_alloc_msg_detach_resources(mbox); + req->cptlfs = true; + req->partial = true; + if (otx2_mbox_process(mbox) < 0) + return -EIO; + + /* Queues have been detached */ + vf->nb_queues = 0; + + return 0; +} + +int +otx2_cpt_msix_offsets_get(const struct rte_cryptodev *dev) +{ + struct otx2_cpt_vf *vf = dev->data->dev_private; + struct otx2_mbox *mbox = vf->otx2_dev.mbox; + struct msix_offset_rsp *rsp; + uint32_t i, ret; + + /* Get CPT MSI-X vector offsets */ + + otx2_mbox_alloc_msg_msix_offset(mbox); + + ret = otx2_mbox_process_msg(mbox, (void *)&rsp); + if (ret) + return ret; + + for (i = 0; i < vf->nb_queues; i++) + vf->lf_msixoff[i] = rsp->cptlf_msixoff[i]; + + return 0; +} diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h index 648c009..0a43061 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h +++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h @@ -10,4 +10,10 @@ int otx2_cpt_available_queues_get(const struct rte_cryptodev *dev, uint16_t *nb_queues); +int otx2_cpt_queues_attach(const struct rte_cryptodev *dev, uint8_t nb_queues); + +int otx2_cpt_queues_detach(const struct rte_cryptodev *dev); + +int otx2_cpt_msix_offsets_get(const struct rte_cryptodev *dev); + #endif /* _OTX2_CRYPTODEV_MBOX_H_ */ diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c index 18ad470..784fea6 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c @@ -4,15 +4,128 @@ #include +#include "cpt_hw_types.h" +#include "cpt_pmd_logs.h" + +#include "otx2_cryptodev.h" +#include "otx2_cryptodev_hw_access.h" +#include "otx2_cryptodev_mbox.h" #include "otx2_cryptodev_ops.h" +#include "otx2_mbox.h" + +/* PMD ops */ + +static int +otx2_cpt_dev_config(struct rte_cryptodev *dev, + struct rte_cryptodev_config *conf) +{ + struct otx2_cpt_vf *vf = dev->data->dev_private; + int ret; + + if (conf->nb_queue_pairs > vf->max_queues) { + CPT_LOG_ERR("Invalid number of queue pairs requested"); + return -EINVAL; + } + + dev->feature_flags &= ~conf->ff_disable; + + /* Unregister error interrupts */ + if (vf->err_intr_registered) + otx2_cpt_err_intr_unregister(dev); + + /* Detach queues */ + if (vf->nb_queues) { + ret = otx2_cpt_queues_detach(dev); + if (ret) { + CPT_LOG_ERR("Could not detach CPT queues"); + return ret; + } + } + + /* Attach queues */ + ret = otx2_cpt_queues_attach(dev, conf->nb_queue_pairs); + if (ret) { + CPT_LOG_ERR("Could not attach CPT queues"); + return -ENODEV; + } + + ret = otx2_cpt_msix_offsets_get(dev); + if (ret) { + CPT_LOG_ERR("Could not get MSI-X offsets"); + goto queues_detach; + } + + /* Register error interrupts */ + ret = otx2_cpt_err_intr_register(dev); + if (ret) { + CPT_LOG_ERR("Could not register error interrupts"); + goto queues_detach; + } + + rte_mb(); + return 0; + +queues_detach: + otx2_cpt_queues_detach(dev); + return ret; +} + +static int +otx2_cpt_dev_start(struct rte_cryptodev *dev) +{ + RTE_SET_USED(dev); + + CPT_PMD_INIT_FUNC_TRACE(); + + return 0; +} + +static void +otx2_cpt_dev_stop(struct rte_cryptodev *dev) +{ + RTE_SET_USED(dev); + + CPT_PMD_INIT_FUNC_TRACE(); +} + +static int +otx2_cpt_dev_close(struct rte_cryptodev *dev) +{ + int ret; + + otx2_cpt_err_intr_unregister(dev); + + ret = otx2_cpt_queues_detach(dev); + if (ret) + CPT_LOG_ERR("Could not detach CPT queues"); + + return ret; +} + +static void +otx2_cpt_dev_info_get(struct rte_cryptodev *dev, + struct rte_cryptodev_info *info) +{ + struct otx2_cpt_vf *vf = dev->data->dev_private; + + if (info != NULL) { + info->max_nb_queue_pairs = vf->max_queues; + info->feature_flags = dev->feature_flags; + info->capabilities = NULL; + info->sym.max_nb_sessions = 0; + info->driver_id = otx2_cryptodev_driver_id; + info->min_mbuf_headroom_req = OTX2_CPT_MIN_HEADROOM_REQ; + info->min_mbuf_tailroom_req = OTX2_CPT_MIN_TAILROOM_REQ; + } +} struct rte_cryptodev_ops otx2_cpt_ops = { /* Device control ops */ - .dev_configure = NULL, - .dev_start = NULL, - .dev_stop = NULL, - .dev_close = NULL, - .dev_infos_get = NULL, + .dev_configure = otx2_cpt_dev_config, + .dev_start = otx2_cpt_dev_start, + .dev_stop = otx2_cpt_dev_stop, + .dev_close = otx2_cpt_dev_close, + .dev_infos_get = otx2_cpt_dev_info_get, .stats_get = NULL, .stats_reset = NULL, diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h index 545614e..9bd24e7 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h +++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h @@ -7,6 +7,9 @@ #include +#define OTX2_CPT_MIN_HEADROOM_REQ 24 +#define OTX2_CPT_MIN_TAILROOM_REQ 8 + struct rte_cryptodev_ops otx2_cpt_ops; #endif /* _OTX2_CRYPTODEV_OPS_H_ */ From patchwork Fri Aug 30 06:28:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 58291 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 139091E892; Fri, 30 Aug 2019 08:32:17 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 555901E88E for ; Fri, 30 Aug 2019 08:32:16 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x7U6UcpM028191; Thu, 29 Aug 2019 23:32:15 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; 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Thu, 29 Aug 2019 23:32:10 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Pablo de Lara , Thomas Monjalon CC: Anoob Joseph , Jerin Jacob , Narayana Prasad , Ankur Dwivedi , Tejasree Kondoj , Date: Fri, 30 Aug 2019 11:58:14 +0530 Message-ID: <1567146501-8224-5-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1567146501-8224-1-git-send-email-anoobj@marvell.com> References: <1567146501-8224-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.70,1.0.8 definitions=2019-08-30_02:2019-08-29,2019-08-30 signatures=0 Subject: [dpdk-dev] [PATCH 04/11] crypto/octeontx2: add symmetric capabilities X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds the symmetric capabilities for OCTEON TX2 crypto PMD. Signed-off-by: Ankur Dwivedi Signed-off-by: Anoob Joseph Signed-off-by: Tejasree Kondoj --- drivers/crypto/octeontx2/Makefile | 1 + drivers/crypto/octeontx2/meson.build | 1 + .../crypto/octeontx2/otx2_cryptodev_capabilities.c | 604 +++++++++++++++++++++ .../crypto/octeontx2/otx2_cryptodev_capabilities.h | 16 + drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 3 +- 5 files changed, 624 insertions(+), 1 deletion(-) create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h diff --git a/drivers/crypto/octeontx2/Makefile b/drivers/crypto/octeontx2/Makefile index 71bc4d1..968efac 100644 --- a/drivers/crypto/octeontx2/Makefile +++ b/drivers/crypto/octeontx2/Makefile @@ -35,6 +35,7 @@ endif # PMD code SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_capabilities.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_hw_access.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_mbox.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_ops.c diff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build index 944fa2c..ee2e907 100644 --- a/drivers/crypto/octeontx2/meson.build +++ b/drivers/crypto/octeontx2/meson.build @@ -11,6 +11,7 @@ deps += ['common_octeontx2'] name = 'octeontx2_crypto' sources = files('otx2_cryptodev.c', + 'otx2_cryptodev_capabilities.c', 'otx2_cryptodev_hw_access.c', 'otx2_cryptodev_mbox.c', 'otx2_cryptodev_ops.c') diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c new file mode 100644 index 0000000..3a70470 --- /dev/null +++ b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c @@ -0,0 +1,604 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C) 2019 Marvell International Ltd. + */ + +#include + +#include "otx2_cryptodev_capabilities.h" + +static const struct rte_cryptodev_capabilities otx2_cpt_sym_capabilities[] = { + /* Symmetric capabilities */ + { /* NULL (AUTH) */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_NULL, + .block_size = 1, + .key_size = { + .min = 0, + .max = 0, + .increment = 0 + }, + .digest_size = { + .min = 0, + .max = 0, + .increment = 0 + }, + }, }, + }, }, + }, + { /* AES GMAC (AUTH) */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_AES_GMAC, + .block_size = 16, + .key_size = { + .min = 16, + .max = 32, + .increment = 8 + }, + .digest_size = { + .min = 8, + .max = 16, + .increment = 4 + }, + .iv_size = { + .min = 12, + .max = 12, + .increment = 0 + } + }, } + }, } + }, + { /* KASUMI (F9) */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_KASUMI_F9, + .block_size = 8, + .key_size = { + .min = 16, + .max = 16, + .increment = 0 + }, + .digest_size = { + .min = 4, + .max = 4, + .increment = 0 + }, + }, } + }, } + }, + { /* MD5 */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_MD5, + .block_size = 64, + .key_size = { + .min = 0, + .max = 0, + .increment = 0 + }, + .digest_size = { + .min = 16, + .max = 16, + .increment = 0 + }, + }, } + }, } + }, + { /* MD5 HMAC */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_MD5_HMAC, + .block_size = 64, + .key_size = { + .min = 8, + .max = 64, + .increment = 8 + }, + .digest_size = { + .min = 16, + .max = 16, + .increment = 0 + }, + }, } + }, } + }, + { /* SHA1 */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_SHA1, + .block_size = 64, + .key_size = { + .min = 0, + .max = 0, + .increment = 0 + }, + .digest_size = { + .min = 20, + .max = 20, + .increment = 0 + }, + }, } + }, } + }, + { /* SHA1 HMAC */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_SHA1_HMAC, + .block_size = 64, + .key_size = { + .min = 64, + .max = 64, + .increment = 0 + }, + .digest_size = { + .min = 20, + .max = 20, + .increment = 0 + }, + }, } + }, } + }, + { /* SHA224 */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_SHA224, + .block_size = 64, + .key_size = { + .min = 0, + .max = 0, + .increment = 0 + }, + .digest_size = { + .min = 28, + .max = 28, + .increment = 0 + }, + }, } + }, } + }, + { /* SHA224 HMAC */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_SHA224_HMAC, + .block_size = 64, + .key_size = { + .min = 64, + .max = 64, + .increment = 0 + }, + .digest_size = { + .min = 28, + .max = 28, + .increment = 0 + }, + }, } + }, } + }, + { /* SHA256 */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_SHA256, + .block_size = 64, + .key_size = { + .min = 0, + .max = 0, + .increment = 0 + }, + .digest_size = { + .min = 32, + .max = 32, + .increment = 0 + }, + }, } + }, } + }, + { /* SHA256 HMAC */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_SHA256_HMAC, + .block_size = 64, + .key_size = { + .min = 64, + .max = 64, + .increment = 0 + }, + .digest_size = { + .min = 32, + .max = 32, + .increment = 0 + }, + }, } + }, } + }, + { /* SHA384 */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_SHA384, + .block_size = 64, + .key_size = { + .min = 0, + .max = 0, + .increment = 0 + }, + .digest_size = { + .min = 48, + .max = 48, + .increment = 0 + }, + }, } + }, } + }, + { /* SHA384 HMAC */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_SHA384_HMAC, + .block_size = 64, + .key_size = { + .min = 64, + .max = 64, + .increment = 0 + }, + .digest_size = { + .min = 48, + .max = 48, + .increment = 0 + }, + }, } + }, } + }, + { /* SHA512 */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_SHA512, + .block_size = 128, + .key_size = { + .min = 0, + .max = 0, + .increment = 0 + }, + .digest_size = { + .min = 64, + .max = 64, + .increment = 0 + }, + }, } + }, } + }, + { /* SHA512 HMAC */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_SHA512_HMAC, + .block_size = 128, + .key_size = { + .min = 64, + .max = 64, + .increment = 0 + }, + .digest_size = { + .min = 64, + .max = 64, + .increment = 0 + }, + }, } + }, } + }, + { /* SNOW 3G (UIA2) */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2, + .block_size = 16, + .key_size = { + .min = 16, + .max = 16, + .increment = 0 + }, + .digest_size = { + .min = 4, + .max = 4, + .increment = 0 + }, + .iv_size = { + .min = 16, + .max = 16, + .increment = 0 + } + }, } + }, } + }, + { /* ZUC (EIA3) */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_ZUC_EIA3, + .block_size = 16, + .key_size = { + .min = 16, + .max = 16, + .increment = 0 + }, + .digest_size = { + .min = 4, + .max = 4, + .increment = 0 + }, + .iv_size = { + .min = 16, + .max = 16, + .increment = 0 + } + }, } + }, } + }, + { /* NULL (CIPHER) */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, + {.cipher = { + .algo = RTE_CRYPTO_CIPHER_NULL, + .block_size = 1, + .key_size = { + .min = 0, + .max = 0, + .increment = 0 + }, + .iv_size = { + .min = 0, + .max = 0, + .increment = 0 + } + }, }, + }, } + }, + { /* 3DES CBC */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, + {.cipher = { + .algo = RTE_CRYPTO_CIPHER_3DES_CBC, + .block_size = 8, + .key_size = { + .min = 24, + .max = 24, + .increment = 0 + }, + .iv_size = { + .min = 8, + .max = 16, + .increment = 8 + } + }, } + }, } + }, + { /* 3DES ECB */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, + {.cipher = { + .algo = RTE_CRYPTO_CIPHER_3DES_ECB, + .block_size = 8, + .key_size = { + .min = 24, + .max = 24, + .increment = 0 + }, + .iv_size = { + .min = 0, + .max = 0, + .increment = 0 + } + }, } + }, } + }, + { /* AES CBC */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, + {.cipher = { + .algo = RTE_CRYPTO_CIPHER_AES_CBC, + .block_size = 16, + .key_size = { + .min = 16, + .max = 32, + .increment = 8 + }, + .iv_size = { + .min = 16, + .max = 16, + .increment = 0 + } + }, } + }, } + }, + { /* AES CTR */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, + {.cipher = { + .algo = RTE_CRYPTO_CIPHER_AES_CTR, + .block_size = 16, + .key_size = { + .min = 16, + .max = 32, + .increment = 8 + }, + .iv_size = { + .min = 12, + .max = 16, + .increment = 4 + } + }, } + }, } + }, + { /* AES XTS */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, + {.cipher = { + .algo = RTE_CRYPTO_CIPHER_AES_XTS, + .block_size = 16, + .key_size = { + .min = 32, + .max = 64, + .increment = 0 + }, + .iv_size = { + .min = 16, + .max = 16, + .increment = 0 + } + }, } + }, } + }, + { /* DES CBC */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, + {.cipher = { + .algo = RTE_CRYPTO_CIPHER_DES_CBC, + .block_size = 8, + .key_size = { + .min = 8, + .max = 8, + .increment = 0 + }, + .iv_size = { + .min = 8, + .max = 8, + .increment = 0 + } + }, } + }, } + }, + { /* KASUMI (F8) */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, + {.cipher = { + .algo = RTE_CRYPTO_CIPHER_KASUMI_F8, + .block_size = 8, + .key_size = { + .min = 16, + .max = 16, + .increment = 0 + }, + .iv_size = { + .min = 8, + .max = 8, + .increment = 0 + } + }, } + }, } + }, + { /* SNOW 3G (UEA2) */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, + {.cipher = { + .algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2, + .block_size = 16, + .key_size = { + .min = 16, + .max = 16, + .increment = 0 + }, + .iv_size = { + .min = 16, + .max = 16, + .increment = 0 + } + }, } + }, } + }, + { /* ZUC (EEA3) */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, + {.cipher = { + .algo = RTE_CRYPTO_CIPHER_ZUC_EEA3, + .block_size = 16, + .key_size = { + .min = 16, + .max = 16, + .increment = 0 + }, + .iv_size = { + .min = 16, + .max = 16, + .increment = 0 + } + }, } + }, } + }, + { /* AES GCM */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AEAD, + {.aead = { + .algo = RTE_CRYPTO_AEAD_AES_GCM, + .block_size = 16, + .key_size = { + .min = 16, + .max = 32, + .increment = 8 + }, + .digest_size = { + .min = 8, + .max = 16, + .increment = 4 + }, + .aad_size = { + .min = 0, + .max = 1024, + .increment = 1 + }, + .iv_size = { + .min = 12, + .max = 12, + .increment = 0 + } + }, } + }, } + }, + /* End of symmetric capabilities */ + RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST() +}; + +const struct rte_cryptodev_capabilities * +otx2_cpt_capabilities_get(void) +{ + return otx2_cpt_sym_capabilities; +} diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h new file mode 100644 index 0000000..f103c32 --- /dev/null +++ b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C) 2019 Marvell International Ltd. + */ + +#ifndef _OTX2_CRYPTODEV_CAPABILITIES_H_ +#define _OTX2_CRYPTODEV_CAPABILITIES_H_ + +#include + +/* + * Get capabilities list for the device + * + */ +const struct rte_cryptodev_capabilities *otx2_cpt_capabilities_get(void); + +#endif /* _OTX2_CRYPTODEV_CAPABILITIES_H_ */ diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c index 784fea6..eafb2d3 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c @@ -8,6 +8,7 @@ #include "cpt_pmd_logs.h" #include "otx2_cryptodev.h" +#include "otx2_cryptodev_capabilities.h" #include "otx2_cryptodev_hw_access.h" #include "otx2_cryptodev_mbox.h" #include "otx2_cryptodev_ops.h" @@ -111,7 +112,7 @@ otx2_cpt_dev_info_get(struct rte_cryptodev *dev, if (info != NULL) { info->max_nb_queue_pairs = vf->max_queues; info->feature_flags = dev->feature_flags; - info->capabilities = NULL; + info->capabilities = otx2_cpt_capabilities_get(); info->sym.max_nb_sessions = 0; info->driver_id = otx2_cryptodev_driver_id; info->min_mbuf_headroom_req = OTX2_CPT_MIN_HEADROOM_REQ; From patchwork Fri Aug 30 06:28:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 58292 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5F18F1E88E; Fri, 30 Aug 2019 08:32:22 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id D6E3C1E886 for ; Fri, 30 Aug 2019 08:32:20 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x7U6UNd8027737; Thu, 29 Aug 2019 23:32:20 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=k1C0SmvVjMaqs0z5/3r1I0g3wVKR/tsLcqckgyJYvj4=; b=OTKVaGLs/PmvrOiKW/tUhf9mQHZZa8bQ8Gib7ZmbuhVOaBAP7bIcD+MPoRF02Z7K+NWf 3eFh9XeOGyZgJIznxh1FwBSImWbJEkTf+aS0BK9ZCykv7L2Vq4QV23g0oDUS4OSaorG6 68f1vN4Bo9m/AJXZ0JieNhlPwn1uUJp3E5swrqQ9XxZUabXDbmFHwl6V1960vOQBZNDs +7IV3jVDBjQaHZzuGYnAvsi+/y9Dhc+fmJmvRG1n5Y6PPNYjtGcCXmZQYMXyVg9us76T OyxHWyYUF95t8dQ0glFog6+I7Iu9ZFsPSsZTo9/OnreIMbVQ6jRq8ki7F6juNB+3qowk WA== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 2uk4rkyg34-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2019 23:32:20 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Thu, 29 Aug 2019 23:32:18 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Thu, 29 Aug 2019 23:32:18 -0700 Received: from ajoseph83.caveonetworks.com.com (unknown [10.29.45.56]) by maili.marvell.com (Postfix) with ESMTP id 250BD3F703F; Thu, 29 Aug 2019 23:32:14 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Pablo de Lara , Thomas Monjalon CC: Ankur Dwivedi , Jerin Jacob , Narayana Prasad , Anoob Joseph , Tejasree Kondoj , Date: Fri, 30 Aug 2019 11:58:15 +0530 Message-ID: <1567146501-8224-6-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1567146501-8224-1-git-send-email-anoobj@marvell.com> References: <1567146501-8224-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.70,1.0.8 definitions=2019-08-30_02:2019-08-29,2019-08-30 signatures=0 Subject: [dpdk-dev] [PATCH 05/11] crypto/octeontx2: add hardware definitions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ankur Dwivedi This patch adds the hardware definitions for OCTEON TX2 crypto hardware. Signed-off-by: Ankur Dwivedi Signed-off-by: Anoob Joseph Signed-off-by: Tejasree Kondoj --- .../crypto/octeontx2/otx2_cryptodev_hw_access.h | 117 +++++++++++++++++++++ 1 file changed, 117 insertions(+) diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h index 2af674d..441494e 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h +++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h @@ -11,15 +11,132 @@ /* Register offsets */ +/* LMT LF registers */ +#define OTX2_LMT_LF_LMTLINE(a) (0x0ull | (uint64_t)(a) << 3) + /* CPT LF registers */ +#define OTX2_CPT_LF_CTL 0x10ull +#define OTX2_CPT_LF_INPROG 0x40ull #define OTX2_CPT_LF_MISC_INT 0xb0ull #define OTX2_CPT_LF_MISC_INT_ENA_W1S 0xd0ull #define OTX2_CPT_LF_MISC_INT_ENA_W1C 0xe0ull +#define OTX2_CPT_LF_Q_BASE 0xf0ull +#define OTX2_CPT_LF_Q_SIZE 0x100ull +#define OTX2_CPT_LF_NQ(a) (0x400ull | (uint64_t)(a) << 3) + +#define OTX2_CPT_AF_LF_CTL(a) (0x27000ull | (uint64_t)(a) << 3) #define OTX2_CPT_LF_BAR2(vf, q_id) \ ((vf)->otx2_dev.bar2 + \ ((RVU_BLOCK_ADDR_CPT0 << 20) | ((q_id) << 12))) +union otx2_cpt_lf_ctl { + uint64_t u; + struct { +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ + uint64_t reserved_8_63 : 56; + uint64_t fc_hyst_bits : 4; + uint64_t reserved_3_3 : 1; + uint64_t fc_up_crossing : 1; + uint64_t fc_ena : 1; + uint64_t ena : 1; +#else /* Word 0 - Little Endian */ + uint64_t ena : 1; + uint64_t fc_ena : 1; + uint64_t fc_up_crossing : 1; + uint64_t reserved_3_3 : 1; + uint64_t fc_hyst_bits : 4; + uint64_t reserved_8_63 : 56; +#endif + } s; +}; + +union otx2_cpt_lf_inprog { + uint64_t u; + struct { +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ + uint64_t reserved_48_63 : 16; + uint64_t gwb_cnt : 8; + uint64_t grb_cnt : 8; + uint64_t grb_partial : 1; + uint64_t reserved_18_30 : 13; + uint64_t grp_drp : 1; + uint64_t eena : 1; + uint64_t reserved_9_15 : 7; + uint64_t inflight : 9; +#else /* Word 0 - Little Endian */ + uint64_t inflight : 9; + uint64_t reserved_9_15 : 7; + uint64_t eena : 1; + uint64_t grp_drp : 1; + uint64_t reserved_18_30 : 13; + uint64_t grb_partial : 1; + uint64_t grb_cnt : 8; + uint64_t gwb_cnt : 8; + uint64_t reserved_48_63 : 16; +#endif + } s; +}; + +union otx2_cpt_lf_q_base { + uint64_t u; + struct { +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ + uint64_t reserved_53_63 : 11; + uint64_t addr : 46; + uint64_t reserved_2_6 : 5; + uint64_t stopped : 1; + uint64_t fault : 1; +#else /* Word 0 - Little Endian */ + uint64_t fault : 1; + uint64_t stopped : 1; + uint64_t reserved_2_6 : 5; + uint64_t addr : 46; + uint64_t reserved_53_63 : 11; +#endif + } s; +}; + +union otx2_cpt_lf_q_size { + uint64_t u; + struct { +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ + uint64_t reserved_15_63 : 49; + uint64_t size_div40 : 15; +#else /* Word 0 - Little Endian */ + uint64_t size_div40 : 15; + uint64_t reserved_15_63 : 49; +#endif + } s; +}; + +union otx2_cpt_af_lf_ctl { + uint64_t u; + struct { +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ + uint64_t reserved_56_63 : 8; + uint64_t grp : 8; + uint64_t reserved_17_47 : 31; + uint64_t nixtx_en : 1; + uint64_t reserved_11_15 : 5; + uint64_t cont_err : 1; + uint64_t pf_func_inst : 1; + uint64_t reserved_1_8 : 8; + uint64_t pri : 1; +#else /* Word 0 - Little Endian */ + uint64_t pri : 1; + uint64_t reserved_1_8 : 8; + uint64_t pf_func_inst : 1; + uint64_t cont_err : 1; + uint64_t reserved_11_15 : 5; + uint64_t nixtx_en : 1; + uint64_t reserved_17_47 : 31; + uint64_t grp : 8; + uint64_t reserved_56_63 : 8; +#endif + } s; +}; + void otx2_cpt_err_intr_unregister(const struct rte_cryptodev *dev); int otx2_cpt_err_intr_register(const struct rte_cryptodev *dev); From patchwork Fri Aug 30 06:28:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 58293 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 79CA21E8B1; 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Thu, 29 Aug 2019 23:32:24 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Thu, 29 Aug 2019 23:32:23 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Thu, 29 Aug 2019 23:32:23 -0700 Received: from ajoseph83.caveonetworks.com.com (unknown [10.29.45.56]) by maili.marvell.com (Postfix) with ESMTP id EF61C3F703F; Thu, 29 Aug 2019 23:32:19 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Pablo de Lara , Thomas Monjalon CC: Anoob Joseph , Jerin Jacob , Narayana Prasad , Ankur Dwivedi , Tejasree Kondoj , Date: Fri, 30 Aug 2019 11:58:16 +0530 Message-ID: <1567146501-8224-7-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1567146501-8224-1-git-send-email-anoobj@marvell.com> References: <1567146501-8224-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.70,1.0.8 definitions=2019-08-30_02:2019-08-29,2019-08-30 signatures=0 Subject: [dpdk-dev] [PATCH 06/11] crypto/octeontx2: add queue pair functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds the queue pair setup and queue pair release functions for OCTEON TX2 crypto pmd. Signed-off-by: Ankur Dwivedi Signed-off-by: Anoob Joseph Signed-off-by: Tejasree Kondoj --- .../crypto/octeontx2/otx2_cryptodev_hw_access.c | 99 +++++++ .../crypto/octeontx2/otx2_cryptodev_hw_access.h | 63 +++++ drivers/crypto/octeontx2/otx2_cryptodev_mbox.c | 81 ++++++ drivers/crypto/octeontx2/otx2_cryptodev_mbox.h | 6 + drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 306 ++++++++++++++++++++- 5 files changed, 552 insertions(+), 3 deletions(-) diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c index 88b5510..20ec60e 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c @@ -1,12 +1,16 @@ /* SPDX-License-Identifier: BSD-3-Clause * Copyright (C) 2019 Marvell International Ltd. */ +#include #include "cpt_pmd_logs.h" #include "otx2_common.h" #include "otx2_cryptodev.h" #include "otx2_cryptodev_hw_access.h" +#include "otx2_cryptodev_mbox.h" +#include "otx2_cryptodev_ops.h" +#include "otx2_dev.h" static void otx2_cpt_lf_err_intr_handler(void *param) @@ -124,3 +128,98 @@ otx2_cpt_err_intr_register(const struct rte_cryptodev *dev) */ return 0; } + +int +otx2_cpt_iq_enable(const struct rte_cryptodev *dev, + const struct otx2_cpt_qp *qp, uint8_t grp_mask, uint8_t pri, + uint32_t size_div40) +{ + union otx2_cpt_af_lf_ctl af_lf_ctl; + union otx2_cpt_lf_inprog inprog; + union otx2_cpt_lf_q_base base; + union otx2_cpt_lf_q_size size; + union otx2_cpt_lf_ctl lf_ctl; + int ret; + + /* Set engine group mask and priority */ + + ret = otx2_cpt_af_reg_read(dev, OTX2_CPT_AF_LF_CTL(qp->id), + &af_lf_ctl.u); + if (ret) + return ret; + af_lf_ctl.s.grp = grp_mask; + af_lf_ctl.s.pri = pri ? 1 : 0; + ret = otx2_cpt_af_reg_write(dev, OTX2_CPT_AF_LF_CTL(qp->id), + af_lf_ctl.u); + if (ret) + return ret; + + /* Set instruction queue base address */ + + base.u = otx2_read64(qp->base + OTX2_CPT_LF_Q_BASE); + base.s.fault = 0; + base.s.stopped = 0; + base.s.addr = qp->iq_dma_addr >> 7; + otx2_write64(base.u, qp->base + OTX2_CPT_LF_Q_BASE); + + /* Set instruction queue size */ + + size.u = otx2_read64(qp->base + OTX2_CPT_LF_Q_SIZE); + size.s.size_div40 = size_div40; + otx2_write64(size.u, qp->base + OTX2_CPT_LF_Q_SIZE); + + /* Enable instruction queue */ + + lf_ctl.u = otx2_read64(qp->base + OTX2_CPT_LF_CTL); + lf_ctl.s.ena = 1; + otx2_write64(lf_ctl.u, qp->base + OTX2_CPT_LF_CTL); + + /* Start instruction execution */ + + inprog.u = otx2_read64(qp->base + OTX2_CPT_LF_INPROG); + inprog.s.eena = 1; + otx2_write64(inprog.u, qp->base + OTX2_CPT_LF_INPROG); + + return 0; +} + +void +otx2_cpt_iq_disable(struct otx2_cpt_qp *qp) +{ + union otx2_cpt_lf_q_grp_ptr grp_ptr; + union otx2_cpt_lf_inprog inprog; + union otx2_cpt_lf_ctl ctl; + int cnt; + + /* Stop instruction execution */ + inprog.u = otx2_read64(qp->base + OTX2_CPT_LF_INPROG); + inprog.s.eena = 0x0; + otx2_write64(inprog.u, qp->base + OTX2_CPT_LF_INPROG); + + /* Disable instructions enqueuing */ + ctl.u = otx2_read64(qp->base + OTX2_CPT_LF_CTL); + ctl.s.ena = 0; + otx2_write64(ctl.u, qp->base + OTX2_CPT_LF_CTL); + + /* Wait for instruction queue to become empty */ + cnt = 0; + do { + inprog.u = otx2_read64(qp->base + OTX2_CPT_LF_INPROG); + if (inprog.s.grb_partial) + cnt = 0; + else + cnt++; + grp_ptr.u = otx2_read64(qp->base + OTX2_CPT_LF_Q_GRP_PTR); + } while ((cnt < 10) && (grp_ptr.s.nq_ptr != grp_ptr.s.dq_ptr)); + + cnt = 0; + do { + inprog.u = otx2_read64(qp->base + OTX2_CPT_LF_INPROG); + if ((inprog.s.inflight == 0) && + (inprog.s.gwb_cnt < 40) && + ((inprog.s.grb_cnt == 0) || (inprog.s.grb_cnt == 40))) + cnt++; + else + cnt = 0; + } while (cnt < 10); +} diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h index 441494e..82718df 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h +++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h @@ -5,10 +5,24 @@ #ifndef _OTX2_CRYPTODEV_HW_ACCESS_H_ #define _OTX2_CRYPTODEV_HW_ACCESS_H_ +#include + #include +#include + +#include "cpt_common.h" +#include "cpt_hw_types.h" #include "otx2_dev.h" +/* CPT instruction queue length */ +#define OTX2_CPT_IQ_LEN 8200 + +#define OTX2_CPT_DEFAULT_CMD_QLEN OTX2_CPT_IQ_LEN + +/* Mask which selects all engine groups */ +#define OTX2_CPT_ENG_GRPS_MASK 0xFF + /* Register offsets */ /* LMT LF registers */ @@ -22,6 +36,7 @@ #define OTX2_CPT_LF_MISC_INT_ENA_W1C 0xe0ull #define OTX2_CPT_LF_Q_BASE 0xf0ull #define OTX2_CPT_LF_Q_SIZE 0x100ull +#define OTX2_CPT_LF_Q_GRP_PTR 0x120ull #define OTX2_CPT_LF_NQ(a) (0x400ull | (uint64_t)(a) << 3) #define OTX2_CPT_AF_LF_CTL(a) (0x27000ull | (uint64_t)(a) << 3) @@ -30,6 +45,8 @@ ((vf)->otx2_dev.bar2 + \ ((RVU_BLOCK_ADDR_CPT0 << 20) | ((q_id) << 12))) +#define OTX2_CPT_QUEUE_HI_PRIO 0x1 + union otx2_cpt_lf_ctl { uint64_t u; struct { @@ -137,8 +154,54 @@ union otx2_cpt_af_lf_ctl { } s; }; +union otx2_cpt_lf_q_grp_ptr { + uint64_t u; + struct { +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ + uint64_t xq_xor : 1; + uint64_t reserved_47_62 : 16; + uint64_t nq_ptr : 15; + uint64_t reserved_31_15 : 17; + uint64_t dq_ptr : 15; +#else /* Word 0 - Little Endian */ + uint64_t dq_ptr : 15; + uint64_t reserved_31_15 : 17; + uint64_t nq_ptr : 15; + uint64_t reserved_47_62 : 16; + uint64_t xq_xor : 1; +#endif + } s; +}; + +struct otx2_cpt_qp { + uint32_t id; + /**< Queue pair id */ + uintptr_t base; + /**< Base address where BAR is mapped */ + void *lmtline; + /**< Address of LMTLINE */ + rte_iova_t lf_nq_reg; + /**< LF enqueue register address */ + struct pending_queue pend_q; + /**< Pending queue */ + struct rte_mempool *sess_mp; + /**< Session mempool */ + struct rte_mempool *sess_mp_priv; + /**< Session private data mempool */ + struct cpt_qp_meta_info meta_info; + /**< Metabuf info required to support operations on the queue pair */ + rte_iova_t iq_dma_addr; + /**< Instruction queue address */ +}; + void otx2_cpt_err_intr_unregister(const struct rte_cryptodev *dev); int otx2_cpt_err_intr_register(const struct rte_cryptodev *dev); +int otx2_cpt_iq_enable(const struct rte_cryptodev *dev, + const struct otx2_cpt_qp *qp, uint8_t grp_mask, + uint8_t pri, uint32_t size_div40); + +void otx2_cpt_iq_disable(struct otx2_cpt_qp *qp); + #endif /* _OTX2_CRYPTODEV_HW_ACCESS_H_ */ diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c index a11aef5..7e7b2d9 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c @@ -92,3 +92,84 @@ otx2_cpt_msix_offsets_get(const struct rte_cryptodev *dev) return 0; } + +static int +otx2_cpt_send_mbox_msg(struct otx2_cpt_vf *vf) +{ + struct otx2_mbox *mbox = vf->otx2_dev.mbox; + int ret; + + otx2_mbox_msg_send(mbox, 0); + + ret = otx2_mbox_wait_for_rsp(mbox, 0); + if (ret < 0) { + CPT_LOG_ERR("Could not get mailbox response"); + return ret; + } + + return 0; +} + +int +otx2_cpt_af_reg_read(const struct rte_cryptodev *dev, uint64_t reg, + uint64_t *val) +{ + struct otx2_cpt_vf *vf = dev->data->dev_private; + struct otx2_mbox *mbox = vf->otx2_dev.mbox; + struct otx2_mbox_dev *mdev = &mbox->dev[0]; + struct cpt_rd_wr_reg_msg *msg; + int ret, off; + + msg = (struct cpt_rd_wr_reg_msg *) + otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*msg), + sizeof(*msg)); + if (msg == NULL) { + CPT_LOG_ERR("Could not allocate mailbox message"); + return -EFAULT; + } + + msg->hdr.id = MBOX_MSG_CPT_RD_WR_REGISTER; + msg->hdr.sig = OTX2_MBOX_REQ_SIG; + msg->hdr.pcifunc = vf->otx2_dev.pf_func; + msg->is_write = 0; + msg->reg_offset = reg; + msg->ret_val = val; + + ret = otx2_cpt_send_mbox_msg(vf); + if (ret < 0) + return ret; + + off = mbox->rx_start + + RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); + msg = (struct cpt_rd_wr_reg_msg *) ((uintptr_t)mdev->mbase + off); + + *val = msg->val; + + return 0; +} + +int +otx2_cpt_af_reg_write(const struct rte_cryptodev *dev, uint64_t reg, + uint64_t val) +{ + struct otx2_cpt_vf *vf = dev->data->dev_private; + struct otx2_mbox *mbox = vf->otx2_dev.mbox; + struct cpt_rd_wr_reg_msg *msg; + + msg = (struct cpt_rd_wr_reg_msg *) + otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*msg), + sizeof(*msg)); + if (msg == NULL) { + CPT_LOG_ERR("Could not allocate mailbox message"); + return -EFAULT; + } + + msg->hdr.id = MBOX_MSG_CPT_RD_WR_REGISTER; + msg->hdr.sig = OTX2_MBOX_REQ_SIG; + msg->hdr.pcifunc = vf->otx2_dev.pf_func; + msg->is_write = 1; + msg->reg_offset = reg; + msg->val = val; + + return otx2_cpt_send_mbox_msg(vf); +} diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h index 0a43061..a298718 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h +++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h @@ -16,4 +16,10 @@ int otx2_cpt_queues_detach(const struct rte_cryptodev *dev); int otx2_cpt_msix_offsets_get(const struct rte_cryptodev *dev); +int otx2_cpt_af_reg_read(const struct rte_cryptodev *dev, uint64_t reg, + uint64_t *val); + +int otx2_cpt_af_reg_write(const struct rte_cryptodev *dev, uint64_t reg, + uint64_t val); + #endif /* _OTX2_CRYPTODEV_MBOX_H_ */ diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c index eafb2d3..b2d459e 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c @@ -2,10 +2,14 @@ * Copyright (C) 2019 Marvell International Ltd. */ +#include + #include +#include #include "cpt_hw_types.h" #include "cpt_pmd_logs.h" +#include "cpt_pmd_ops_helper.h" #include "otx2_cryptodev.h" #include "otx2_cryptodev_capabilities.h" @@ -14,6 +18,232 @@ #include "otx2_cryptodev_ops.h" #include "otx2_mbox.h" +#define METABUF_POOL_CACHE_SIZE 512 + +/* Forward declarations */ + +static int +otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id); + +static void +qp_memzone_name_get(char *name, int size, int dev_id, int qp_id) +{ + snprintf(name, size, "otx2_cpt_lf_mem_%u:%u", dev_id, qp_id); +} + +static int +otx2_cpt_metabuf_mempool_create(const struct rte_cryptodev *dev, + struct otx2_cpt_qp *qp, uint8_t qp_id, + int nb_elements) +{ + char mempool_name[RTE_MEMPOOL_NAMESIZE]; + int sg_mlen, lb_mlen, max_mlen, ret; + struct cpt_qp_meta_info *meta_info; + struct rte_mempool *pool; + + /* Get meta len for scatter gather mode */ + sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode(); + + /* Extra 32B saved for future considerations */ + sg_mlen += 4 * sizeof(uint64_t); + + /* Get meta len for linear buffer (direct) mode */ + lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode(); + + /* Extra 32B saved for future considerations */ + lb_mlen += 4 * sizeof(uint64_t); + + /* Check max requirement for meta buffer */ + max_mlen = RTE_MAX(lb_mlen, sg_mlen); + + /* Allocate mempool */ + + snprintf(mempool_name, RTE_MEMPOOL_NAMESIZE, "otx2_cpt_mb_%u:%u", + dev->data->dev_id, qp_id); + + pool = rte_mempool_create_empty(mempool_name, nb_elements, max_mlen, + METABUF_POOL_CACHE_SIZE, 0, + rte_socket_id(), 0); + + if (pool == NULL) { + CPT_LOG_ERR("Could not create mempool for metabuf"); + return rte_errno; + } + + ret = rte_mempool_set_ops_byname(pool, RTE_MBUF_DEFAULT_MEMPOOL_OPS, + NULL); + if (ret) { + CPT_LOG_ERR("Could not set mempool ops"); + goto mempool_free; + } + + ret = rte_mempool_populate_default(pool); + if (ret <= 0) { + CPT_LOG_ERR("Could not populate metabuf pool"); + goto mempool_free; + } + + meta_info = &qp->meta_info; + + meta_info->pool = pool; + meta_info->lb_mlen = lb_mlen; + meta_info->sg_mlen = sg_mlen; + + return 0; + +mempool_free: + rte_mempool_free(pool); + return ret; +} + +static void +otx2_cpt_metabuf_mempool_destroy(struct otx2_cpt_qp *qp) +{ + struct cpt_qp_meta_info *meta_info = &qp->meta_info; + + rte_mempool_free(meta_info->pool); + + meta_info->pool = NULL; + meta_info->lb_mlen = 0; + meta_info->sg_mlen = 0; +} + +static struct otx2_cpt_qp * +otx2_cpt_qp_create(const struct rte_cryptodev *dev, uint16_t qp_id, + uint8_t group) +{ + struct otx2_cpt_vf *vf = dev->data->dev_private; + uint64_t pg_sz = sysconf(_SC_PAGESIZE); + const struct rte_memzone *lf_mem; + uint32_t len, iq_len, size_div40; + char name[RTE_MEMZONE_NAMESIZE]; + uint64_t used_len, iova; + struct otx2_cpt_qp *qp; + uint64_t lmtline; + uint8_t *va; + int ret; + + /* Allocate queue pair */ + qp = rte_zmalloc_socket("OCTEON TX2 Crypto PMD Queue Pair", sizeof(*qp), + OTX2_ALIGN, 0); + if (qp == NULL) { + CPT_LOG_ERR("Could not allocate queue pair"); + return NULL; + } + + iq_len = OTX2_CPT_IQ_LEN; + + /* + * Queue size must be a multiple of 40 and effective queue size to + * software is (size_div40 - 1) * 40 + */ + size_div40 = (iq_len + 40 - 1) / 40 + 1; + + /* For pending queue */ + len = iq_len * RTE_ALIGN(sizeof(struct rid), 8); + + /* Space for instruction group memory */ + len += size_div40 * 16; + + /* So that instruction queues start as pg size aligned */ + len = RTE_ALIGN(len, pg_sz); + + /* For instruction queues */ + len += OTX2_CPT_IQ_LEN * sizeof(union cpt_inst_s); + + /* Wastage after instruction queues */ + len = RTE_ALIGN(len, pg_sz); + + qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id, + qp_id); + + lf_mem = rte_memzone_reserve_aligned(name, len, vf->otx2_dev.node, + RTE_MEMZONE_SIZE_HINT_ONLY | RTE_MEMZONE_256MB, + RTE_CACHE_LINE_SIZE); + if (lf_mem == NULL) { + CPT_LOG_ERR("Could not allocate reserved memzone"); + goto qp_free; + } + + va = lf_mem->addr; + iova = lf_mem->iova; + + memset(va, 0, len); + + ret = otx2_cpt_metabuf_mempool_create(dev, qp, qp_id, iq_len); + if (ret) { + CPT_LOG_ERR("Could not create mempool for metabuf"); + goto lf_mem_free; + } + + /* Initialize pending queue */ + qp->pend_q.rid_queue = (struct rid *)va; + qp->pend_q.enq_tail = 0; + qp->pend_q.deq_head = 0; + qp->pend_q.pending_count = 0; + + used_len = iq_len * RTE_ALIGN(sizeof(struct rid), 8); + used_len += size_div40 * 16; + used_len = RTE_ALIGN(used_len, pg_sz); + iova += used_len; + + qp->iq_dma_addr = iova; + qp->id = qp_id; + qp->base = OTX2_CPT_LF_BAR2(vf, qp_id); + + lmtline = vf->otx2_dev.bar2 + + (RVU_BLOCK_ADDR_LMT << 20 | qp_id << 12) + + OTX2_LMT_LF_LMTLINE(0); + + qp->lmtline = (void *)lmtline; + + qp->lf_nq_reg = qp->base + OTX2_CPT_LF_NQ(0); + + otx2_cpt_iq_disable(qp); + + ret = otx2_cpt_iq_enable(dev, qp, group, OTX2_CPT_QUEUE_HI_PRIO, + size_div40); + if (ret) { + CPT_LOG_ERR("Could not enable instruction queue"); + goto mempool_destroy; + } + + return qp; + +mempool_destroy: + otx2_cpt_metabuf_mempool_destroy(qp); +lf_mem_free: + rte_memzone_free(lf_mem); +qp_free: + rte_free(qp); + return NULL; +} + +static int +otx2_cpt_qp_destroy(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp) +{ + const struct rte_memzone *lf_mem; + char name[RTE_MEMZONE_NAMESIZE]; + int ret; + + otx2_cpt_iq_disable(qp); + + otx2_cpt_metabuf_mempool_destroy(qp); + + qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id, + qp->id); + + lf_mem = rte_memzone_lookup(name); + + ret = rte_memzone_free(lf_mem); + if (ret) + return ret; + + rte_free(qp); + + return 0; +} + /* PMD ops */ static int @@ -92,7 +322,13 @@ otx2_cpt_dev_stop(struct rte_cryptodev *dev) static int otx2_cpt_dev_close(struct rte_cryptodev *dev) { - int ret; + int i, ret; + + for (i = 0; i < dev->data->nb_queue_pairs; i++) { + ret = otx2_cpt_queue_pair_release(dev, i); + if (ret) + return ret; + } otx2_cpt_err_intr_unregister(dev); @@ -120,6 +356,70 @@ otx2_cpt_dev_info_get(struct rte_cryptodev *dev, } } +static int +otx2_cpt_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id, + const struct rte_cryptodev_qp_conf *conf, + int socket_id __rte_unused) +{ + uint8_t grp_mask = OTX2_CPT_ENG_GRPS_MASK; + struct rte_pci_device *pci_dev; + struct otx2_cpt_qp *qp; + + CPT_PMD_INIT_FUNC_TRACE(); + + if (dev->data->queue_pairs[qp_id] != NULL) + otx2_cpt_queue_pair_release(dev, qp_id); + + if (conf->nb_descriptors > OTX2_CPT_DEFAULT_CMD_QLEN) { + CPT_LOG_ERR("Could not setup queue pair for %u descriptors", + conf->nb_descriptors); + return -EINVAL; + } + + pci_dev = RTE_DEV_TO_PCI(dev->device); + + if (pci_dev->mem_resource[2].addr == NULL) { + CPT_LOG_ERR("Invalid PCI mem address"); + return -EIO; + } + + qp = otx2_cpt_qp_create(dev, qp_id, grp_mask); + if (qp == NULL) { + CPT_LOG_ERR("Could not create queue pair %d", qp_id); + return -ENOMEM; + } + + qp->sess_mp = conf->mp_session; + qp->sess_mp_priv = conf->mp_session_private; + dev->data->queue_pairs[qp_id] = qp; + + return 0; +} + +static int +otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id) +{ + struct otx2_cpt_qp *qp = dev->data->queue_pairs[qp_id]; + int ret; + + CPT_PMD_INIT_FUNC_TRACE(); + + if (qp == NULL) + return -EINVAL; + + CPT_LOG_INFO("Releasing queue pair %d", qp_id); + + ret = otx2_cpt_qp_destroy(dev, qp); + if (ret) { + CPT_LOG_ERR("Could not destroy queue pair %d", qp_id); + return ret; + } + + dev->data->queue_pairs[qp_id] = NULL; + + return 0; +} + struct rte_cryptodev_ops otx2_cpt_ops = { /* Device control ops */ .dev_configure = otx2_cpt_dev_config, @@ -130,8 +430,8 @@ struct rte_cryptodev_ops otx2_cpt_ops = { .stats_get = NULL, .stats_reset = NULL, - .queue_pair_setup = NULL, - .queue_pair_release = NULL, + .queue_pair_setup = otx2_cpt_queue_pair_setup, + .queue_pair_release = otx2_cpt_queue_pair_release, .queue_pair_count = NULL, /* Symmetric crypto ops */ From patchwork Fri Aug 30 06:28:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 58294 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 792741E8C2; Fri, 30 Aug 2019 08:32:31 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id BF44A1E8BD for ; Fri, 30 Aug 2019 08:32:29 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x7U6TcTl024096; Thu, 29 Aug 2019 23:32:29 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=CCZI/aEVlnjo6X+ocIS7QmseGiczwNsOfFgjUmSqBIk=; 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Thu, 29 Aug 2019 23:32:24 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Pablo de Lara , Thomas Monjalon CC: Ankur Dwivedi , Jerin Jacob , Narayana Prasad , Anoob Joseph , Tejasree Kondoj , Date: Fri, 30 Aug 2019 11:58:17 +0530 Message-ID: <1567146501-8224-8-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1567146501-8224-1-git-send-email-anoobj@marvell.com> References: <1567146501-8224-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.70,1.0.8 definitions=2019-08-30_02:2019-08-29,2019-08-30 signatures=0 Subject: [dpdk-dev] [PATCH 07/11] crypto/octeontx2: add session related functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ankur Dwivedi This patch adds the symmetric session related callbacks. Signed-off-by: Ankur Dwivedi Signed-off-by: Anoob Joseph Signed-off-by: Tejasree Kondoj --- drivers/common/cpt/cpt_mcode_defines.h | 2 + drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 117 +++++++++++++++++++++++++- drivers/crypto/octeontx2/otx2_cryptodev_ops.h | 5 ++ 3 files changed, 121 insertions(+), 3 deletions(-) diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h index b7c3feb..c197c7b 100644 --- a/drivers/common/cpt/cpt_mcode_defines.h +++ b/drivers/common/cpt/cpt_mcode_defines.h @@ -213,6 +213,8 @@ struct cpt_sess_misc { uint16_t is_null:1; /** Flag for GMAC */ uint16_t is_gmac:1; + /** Engine group */ + uint16_t egrp:3; /** AAD length */ uint16_t aad_length; /** MAC len in bytes */ diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c index b2d459e..fcfcf1a 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c @@ -10,6 +10,7 @@ #include "cpt_hw_types.h" #include "cpt_pmd_logs.h" #include "cpt_pmd_ops_helper.h" +#include "cpt_ucode.h" #include "otx2_cryptodev.h" #include "otx2_cryptodev_capabilities.h" @@ -244,6 +245,90 @@ otx2_cpt_qp_destroy(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp) return 0; } +static int +sym_session_configure(int driver_id, struct rte_crypto_sym_xform *xform, + struct rte_cryptodev_sym_session *sess, + struct rte_mempool *pool) +{ + struct cpt_sess_misc *misc; + void *priv; + int ret; + + if (unlikely(cpt_is_algo_supported(xform))) { + CPT_LOG_ERR("Crypto xform not supported"); + return -ENOTSUP; + } + + if (unlikely(rte_mempool_get(pool, &priv))) { + CPT_LOG_ERR("Could not allocate session private data"); + return -ENOMEM; + } + + misc = priv; + + for ( ; xform != NULL; xform = xform->next) { + switch (xform->type) { + case RTE_CRYPTO_SYM_XFORM_AEAD: + ret = fill_sess_aead(xform, misc); + break; + case RTE_CRYPTO_SYM_XFORM_CIPHER: + ret = fill_sess_cipher(xform, misc); + break; + case RTE_CRYPTO_SYM_XFORM_AUTH: + if (xform->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC) + ret = fill_sess_gmac(xform, misc); + else + ret = fill_sess_auth(xform, misc); + break; + default: + ret = -1; + } + + if (ret) + goto priv_put; + } + + set_sym_session_private_data(sess, driver_id, misc); + + misc->ctx_dma_addr = rte_mempool_virt2iova(misc) + + sizeof(struct cpt_sess_misc); + + /* + * IE engines support IPsec operations + * SE engines support IPsec operations and Air-Crypto operations + */ + if (misc->zsk_flag) + misc->egrp = OTX2_CPT_EGRP_SE; + else + misc->egrp = OTX2_CPT_EGRP_SE_IE; + + return 0; + +priv_put: + rte_mempool_put(pool, priv); + + CPT_LOG_ERR("Crypto xform not supported"); + return -ENOTSUP; +} + +static void +sym_session_clear(int driver_id, struct rte_cryptodev_sym_session *sess) +{ + void *priv = get_sym_session_private_data(sess, driver_id); + struct rte_mempool *pool; + + if (priv == NULL) + return; + + memset(priv, 0, cpt_get_session_size()); + + pool = rte_mempool_from_obj(priv); + + set_sym_session_private_data(sess, driver_id, NULL); + + rte_mempool_put(pool, priv); +} + /* PMD ops */ static int @@ -420,6 +505,32 @@ otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id) return 0; } +static unsigned int +otx2_cpt_sym_session_get_size(struct rte_cryptodev *dev __rte_unused) +{ + return cpt_get_session_size(); +} + +static int +otx2_cpt_sym_session_configure(struct rte_cryptodev *dev, + struct rte_crypto_sym_xform *xform, + struct rte_cryptodev_sym_session *sess, + struct rte_mempool *pool) +{ + CPT_PMD_INIT_FUNC_TRACE(); + + return sym_session_configure(dev->driver_id, xform, sess, pool); +} + +static void +otx2_cpt_sym_session_clear(struct rte_cryptodev *dev, + struct rte_cryptodev_sym_session *sess) +{ + CPT_PMD_INIT_FUNC_TRACE(); + + return sym_session_clear(dev->driver_id, sess); +} + struct rte_cryptodev_ops otx2_cpt_ops = { /* Device control ops */ .dev_configure = otx2_cpt_dev_config, @@ -435,7 +546,7 @@ struct rte_cryptodev_ops otx2_cpt_ops = { .queue_pair_count = NULL, /* Symmetric crypto ops */ - .sym_session_get_size = NULL, - .sym_session_configure = NULL, - .sym_session_clear = NULL, + .sym_session_get_size = otx2_cpt_sym_session_get_size, + .sym_session_configure = otx2_cpt_sym_session_configure, + .sym_session_clear = otx2_cpt_sym_session_clear, }; diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h index 9bd24e7..ba93a66 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h +++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h @@ -10,6 +10,11 @@ #define OTX2_CPT_MIN_HEADROOM_REQ 24 #define OTX2_CPT_MIN_TAILROOM_REQ 8 +enum otx2_cpt_egrp { + OTX2_CPT_EGRP_SE = 0, + OTX2_CPT_EGRP_SE_IE = 1, +}; + struct rte_cryptodev_ops otx2_cpt_ops; #endif /* _OTX2_CRYPTODEV_OPS_H_ */ From patchwork Fri Aug 30 06:28:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 58295 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 658111E894; Fri, 30 Aug 2019 08:32:36 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id F23E41E894 for ; Fri, 30 Aug 2019 08:32:34 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x7U6TXx2023644; Thu, 29 Aug 2019 23:32:34 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; 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Thu, 29 Aug 2019 23:32:29 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Pablo de Lara , Thomas Monjalon CC: Anoob Joseph , Jerin Jacob , Narayana Prasad , Ankur Dwivedi , Tejasree Kondoj , Date: Fri, 30 Aug 2019 11:58:18 +0530 Message-ID: <1567146501-8224-9-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1567146501-8224-1-git-send-email-anoobj@marvell.com> References: <1567146501-8224-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.70,1.0.8 definitions=2019-08-30_02:2019-08-29,2019-08-30 signatures=0 Subject: [dpdk-dev] [PATCH 08/11] crypto/octeontx2: add enqueue burst X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds the enqueue burst callbacks for the OCTEON TX2 crypto driver. Other required functions and data structures which are used to enqueue the instruction to the hardware are also added. Signed-off-by: Ankur Dwivedi Signed-off-by: Anoob Joseph Signed-off-by: Tejasree Kondoj --- drivers/common/cpt/cpt_hw_types.h | 38 ++++++ drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 159 ++++++++++++++++++++++++++ 2 files changed, 197 insertions(+) diff --git a/drivers/common/cpt/cpt_hw_types.h b/drivers/common/cpt/cpt_hw_types.h index 4c2893b..4286512 100644 --- a/drivers/common/cpt/cpt_hw_types.h +++ b/drivers/common/cpt/cpt_hw_types.h @@ -197,6 +197,44 @@ typedef union cpt_inst_s { }; #endif /* Word 7 - End */ } s8x; + struct cpt_inst_s_9s { +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ + uint64_t nixtx_addr : 60; + uint64_t doneint : 1; + uint64_t nixtxl : 3; +#else /* Word 0 - Little Endian */ + uint64_t nixtxl : 3; + uint64_t doneint : 1; + uint64_t nixtx_addr : 60; +#endif /* Word 0 - End */ + uint64_t res_addr; +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 2 - Big Endian */ + uint64_t rvu_pf_func : 16; + uint64_t reserved_172_175 : 4; + uint64_t grp : 10; + uint64_t tt : 2; + uint64_t tag : 32; +#else /* Word 2 - Little Endian */ + uint64_t tag : 32; + uint64_t tt : 2; + uint64_t grp : 10; + uint64_t reserved_172_175 : 4; + uint64_t rvu_pf_func : 16; +#endif /* Word 2 - End */ +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 3 - Big Endian */ + uint64_t wq_ptr : 61; + uint64_t reserved_194_193 : 2; + uint64_t qord : 1; +#else /* Word 3 - Little Endian */ + uint64_t qord : 1; + uint64_t reserved_194_193 : 2; + uint64_t wq_ptr : 61; +#endif /* Word 3 - End */ + uint64_t ei0; + uint64_t ei1; + uint64_t ei2; + uint64_t ei3; + } s9x; } cpt_inst_s_t; /** diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c index fcfcf1a..74e6f1c 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c @@ -329,6 +329,163 @@ sym_session_clear(int driver_id, struct rte_cryptodev_sym_session *sess) rte_mempool_put(pool, priv); } +static __rte_always_inline int32_t __hot +otx2_cpt_enqueue_req(const struct otx2_cpt_qp *qp, + struct pending_queue *pend_q, + struct cpt_request_info *req) +{ + void *lmtline = qp->lmtline; + union cpt_inst_s inst; + uint64_t lmt_status; + + if (unlikely(pend_q->pending_count >= OTX2_CPT_DEFAULT_CMD_QLEN)) + return -EAGAIN; + + inst.u[0] = 0; + inst.s9x.res_addr = req->comp_baddr; + inst.u[2] = 0; + inst.u[3] = 0; + + inst.s9x.ei0 = req->ist.ei0; + inst.s9x.ei1 = req->ist.ei1; + inst.s9x.ei2 = req->ist.ei2; + inst.s9x.ei3 = req->ist.ei3; + + req->time_out = rte_get_timer_cycles() + + DEFAULT_COMMAND_TIMEOUT * rte_get_timer_hz(); + + do { + /* Copy CPT command to LMTLINE */ + memcpy(lmtline, &inst, sizeof(inst)); + + /* + * Make sure compiler does not reorder memcpy and ldeor. + * LMTST transactions are always flushed from the write + * buffer immediately, a DMB is not required to push out + * LMTSTs. + */ + rte_cio_wmb(); + lmt_status = otx2_lmt_submit(qp->lf_nq_reg); + } while (lmt_status == 0); + + pend_q->rid_queue[pend_q->enq_tail].rid = (uintptr_t)req; + + /* We will use soft queue length here to limit requests */ + MOD_INC(pend_q->enq_tail, OTX2_CPT_DEFAULT_CMD_QLEN); + pend_q->pending_count += 1; + + return 0; +} + +static __rte_always_inline int __hot +otx2_cpt_enqueue_sym(struct otx2_cpt_qp *qp, struct rte_crypto_op *op, + struct pending_queue *pend_q) +{ + struct rte_crypto_sym_op *sym_op = op->sym; + struct cpt_request_info *req; + struct cpt_sess_misc *sess; + vq_cmd_word3_t *w3; + uint64_t cpt_op; + void *mdata; + int ret; + + sess = get_sym_session_private_data(sym_op->session, + otx2_cryptodev_driver_id); + + cpt_op = sess->cpt_op; + + if (cpt_op & CPT_OP_CIPHER_MASK) + ret = fill_fc_params(op, sess, &qp->meta_info, &mdata, + (void **)&req); + else + ret = fill_digest_params(op, sess, &qp->meta_info, &mdata, + (void **)&req); + + if (unlikely(ret)) { + CPT_LOG_DP_ERR("Crypto req : op %p, cpt_op 0x%x ret 0x%x", + op, (unsigned int)cpt_op, ret); + return ret; + } + + w3 = ((vq_cmd_word3_t *)(&req->ist.ei3)); + w3->s.grp = sess->egrp; + + ret = otx2_cpt_enqueue_req(qp, pend_q, req); + + if (unlikely(ret)) { + /* Free buffer allocated by fill params routines */ + free_op_meta(mdata, qp->meta_info.pool); + } + + return ret; +} + +static __rte_always_inline int __hot +otx2_cpt_enqueue_sym_sessless(struct otx2_cpt_qp *qp, struct rte_crypto_op *op, + struct pending_queue *pend_q) +{ + const int driver_id = otx2_cryptodev_driver_id; + struct rte_crypto_sym_op *sym_op = op->sym; + struct rte_cryptodev_sym_session *sess; + int ret; + + /* Create temporary session */ + + if (rte_mempool_get(qp->sess_mp, (void **)&sess)) + return -ENOMEM; + + ret = sym_session_configure(driver_id, sym_op->xform, sess, + qp->sess_mp_priv); + if (ret) + goto sess_put; + + sym_op->session = sess; + + ret = otx2_cpt_enqueue_sym(qp, op, pend_q); + + if (unlikely(ret)) + goto priv_put; + + return 0; + +priv_put: + sym_session_clear(driver_id, sess); +sess_put: + rte_mempool_put(qp->sess_mp, sess); + return ret; +} + +static uint16_t +otx2_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops) +{ + uint16_t nb_allowed, count = 0; + struct otx2_cpt_qp *qp = qptr; + struct pending_queue *pend_q; + struct rte_crypto_op *op; + int ret; + + pend_q = &qp->pend_q; + + nb_allowed = OTX2_CPT_DEFAULT_CMD_QLEN - pend_q->pending_count; + if (nb_ops > nb_allowed) + nb_ops = nb_allowed; + + for (count = 0; count < nb_ops; count++) { + op = ops[count]; + if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) + ret = otx2_cpt_enqueue_sym(qp, op, pend_q); + else if (op->sess_type == RTE_CRYPTO_OP_SESSIONLESS) + ret = otx2_cpt_enqueue_sym_sessless(qp, op, pend_q); + else + break; + + if (unlikely(ret)) + break; + } + + return count; +} + /* PMD ops */ static int @@ -378,6 +535,8 @@ otx2_cpt_dev_config(struct rte_cryptodev *dev, goto queues_detach; } + dev->enqueue_burst = otx2_cpt_enqueue_burst; + rte_mb(); return 0; From patchwork Fri Aug 30 06:28:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 58296 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 87ADD1E86E; Fri, 30 Aug 2019 08:32:41 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 444F81E86E for ; Fri, 30 Aug 2019 08:32:40 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x7U6ULNB000551; Thu, 29 Aug 2019 23:32:39 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=eAbokfrPtazYTwUriGJQuy+sFzGrjfAv2ppkeaklWuw=; b=bSerM1C727tRVxgKwHELq0zJuKc9Rzx3S86/ljwh1bLoak3UdRoyu4GtnaPYdPIZnIgy cyC7M0oTZN4oGFxUEc9OQlXboTiZ0GSr0ePW0LAMNI7v10MgG02Wo0qDNt/KuQ+xAhmR 19LV6ShUWajbrN5aO+XHBEwQahsSDTmrDe4GKEt8NRBIpVCWZULpQ7BCx6Ih82jb9Baa FHm7r2lRcxy5sVReUG5HOxJX4pQHBtZeR+Az5fNfm1vcncAa8MzOeMya2d1LNIQd3p2J 2dzZP2lk3najNn2zg2mrN96513DzUU/RUBEGS7VjeaB+7BwlAhlQqLuGVDw9LqoQgTGe zw== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0a-0016f401.pphosted.com with ESMTP id 2upmepj41m-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2019 23:32:39 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Thu, 29 Aug 2019 23:32:38 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Thu, 29 Aug 2019 23:32:38 -0700 Received: from ajoseph83.caveonetworks.com.com (unknown [10.29.45.56]) by maili.marvell.com (Postfix) with ESMTP id EC3913F703F; Thu, 29 Aug 2019 23:32:34 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Pablo de Lara , Thomas Monjalon CC: Ankur Dwivedi , Jerin Jacob , Narayana Prasad , Anoob Joseph , Tejasree Kondoj , Date: Fri, 30 Aug 2019 11:58:19 +0530 Message-ID: <1567146501-8224-10-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1567146501-8224-1-git-send-email-anoobj@marvell.com> References: <1567146501-8224-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.70,1.0.8 definitions=2019-08-30_02:2019-08-29,2019-08-30 signatures=0 Subject: [dpdk-dev] [PATCH 09/11] crypto/octeontx2: add dequeue burst X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ankur Dwivedi This patch adds the dequeue burst callbacks for the OCTEON TX2 crypto driver. The completion code is checked during the dequeue and the respective status is set in the crypto operation. Signed-off-by: Ankur Dwivedi Signed-off-by: Anoob Joseph Signed-off-by: Tejasree Kondoj --- drivers/common/cpt/cpt_hw_types.h | 14 +++ drivers/crypto/octeontx2/Makefile | 1 + drivers/crypto/octeontx2/meson.build | 1 + .../crypto/octeontx2/otx2_cryptodev_hw_access.h | 16 +++ drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 128 +++++++++++++++++++++ 5 files changed, 160 insertions(+) diff --git a/drivers/common/cpt/cpt_hw_types.h b/drivers/common/cpt/cpt_hw_types.h index 4286512..e2b127d 100644 --- a/drivers/common/cpt/cpt_hw_types.h +++ b/drivers/common/cpt/cpt_hw_types.h @@ -281,6 +281,20 @@ typedef union cpt_res_s { uint64_t reserved_64_127 : 64; #endif /* Word 1 - End */ } s8x; + struct cpt_res_s_9s { +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */ + uint64_t reserved_17_63:47; + uint64_t doneint:1; + uint64_t uc_compcode:8; + uint64_t compcode:8; +#else /* Word 0 - Little Endian */ + uint64_t compcode:8; + uint64_t uc_compcode:8; + uint64_t doneint:1; + uint64_t reserved_17_63:47; +#endif /* Word 0 - End */ + uint64_t reserved_64_127; + } s9x; } cpt_res_s_t; /** diff --git a/drivers/crypto/octeontx2/Makefile b/drivers/crypto/octeontx2/Makefile index 968efac..ce116b8 100644 --- a/drivers/crypto/octeontx2/Makefile +++ b/drivers/crypto/octeontx2/Makefile @@ -24,6 +24,7 @@ CFLAGS += -O3 CFLAGS += -I$(RTE_SDK)/drivers/common/cpt CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2 CFLAGS += -I$(RTE_SDK)/drivers/mempool/octeontx2 +CFLAGS += -DALLOW_EXPERIMENTAL_API ifneq ($(CONFIG_RTE_ARCH_64),y) CFLAGS += -Wno-int-to-pointer-cast diff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build index ee2e907..b6e5b73 100644 --- a/drivers/crypto/octeontx2/meson.build +++ b/drivers/crypto/octeontx2/meson.build @@ -10,6 +10,7 @@ deps += ['common_cpt'] deps += ['common_octeontx2'] name = 'octeontx2_crypto' +allow_experimental_apis = true sources = files('otx2_cryptodev.c', 'otx2_cryptodev_capabilities.c', 'otx2_cryptodev_hw_access.c', diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h index 82718df..d787d74 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h +++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h @@ -12,6 +12,7 @@ #include "cpt_common.h" #include "cpt_hw_types.h" +#include "cpt_mcode_defines.h" #include "otx2_dev.h" @@ -173,6 +174,21 @@ union otx2_cpt_lf_q_grp_ptr { } s; }; +/* + * Enumeration cpt_9x_comp_e + * + * CPT 9X Completion Enumeration + * Enumerates the values of CPT_RES_S[COMPCODE]. + */ +enum cpt_9x_comp_e { + CPT_9X_COMP_E_NOTDONE = 0x00, + CPT_9X_COMP_E_GOOD = 0x01, + CPT_9X_COMP_E_FAULT = 0x02, + CPT_9X_COMP_E_HWERR = 0x04, + CPT_9X_COMP_E_INSTERR = 0x05, + CPT_9X_COMP_E_LAST_ENTRY = 0x06 +}; + struct otx2_cpt_qp { uint32_t id; /**< Queue pair id */ diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c index 74e6f1c..b21714c 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c @@ -486,6 +486,133 @@ otx2_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops) return count; } +static inline void +otx2_cpt_dequeue_post_process(struct otx2_cpt_qp *qp, struct rte_crypto_op *cop, + uintptr_t *rsp, uint8_t cc) +{ + if (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) { + if (likely(cc == NO_ERR)) { + /* Verify authentication data if required */ + if (unlikely(rsp[2])) + compl_auth_verify(cop, (uint8_t *)rsp[2], + rsp[3]); + else + cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS; + } else { + if (cc == ERR_GC_ICV_MISCOMPARE) + cop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED; + else + cop->status = RTE_CRYPTO_OP_STATUS_ERROR; + } + + if (unlikely(cop->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) { + sym_session_clear(otx2_cryptodev_driver_id, + cop->sym->session); + rte_mempool_put(qp->sess_mp, cop->sym->session); + cop->sym->session = NULL; + } + } +} + +static __rte_always_inline uint8_t +otx2_cpt_compcode_get(struct cpt_request_info *req) +{ + volatile struct cpt_res_s_9s *res; + uint8_t ret; + + res = (volatile struct cpt_res_s_9s *)req->completion_addr; + + if (unlikely(res->compcode == CPT_9X_COMP_E_NOTDONE)) { + if (rte_get_timer_cycles() < req->time_out) + return ERR_REQ_PENDING; + + CPT_LOG_DP_ERR("Request timed out"); + return ERR_REQ_TIMEOUT; + } + + if (likely(res->compcode == CPT_9X_COMP_E_GOOD)) { + ret = NO_ERR; + if (unlikely(res->uc_compcode)) { + ret = res->uc_compcode; + CPT_LOG_DP_DEBUG("Request failed with microcode error"); + CPT_LOG_DP_DEBUG("MC completion code 0x%x", + res->uc_compcode); + } + } else { + CPT_LOG_DP_DEBUG("HW completion code 0x%x", res->compcode); + + ret = res->compcode; + switch (res->compcode) { + case CPT_9X_COMP_E_INSTERR: + CPT_LOG_DP_ERR("Request failed with instruction error"); + break; + case CPT_9X_COMP_E_FAULT: + CPT_LOG_DP_ERR("Request failed with DMA fault"); + break; + case CPT_9X_COMP_E_HWERR: + CPT_LOG_DP_ERR("Request failed with hardware error"); + break; + default: + CPT_LOG_DP_ERR("Request failed with unknown completion code"); + } + } + + return ret; +} + +static uint16_t +otx2_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops) +{ + int i, nb_pending, nb_completed; + struct otx2_cpt_qp *qp = qptr; + struct pending_queue *pend_q; + struct cpt_request_info *req; + struct rte_crypto_op *cop; + uint8_t cc[nb_ops]; + struct rid *rid; + uintptr_t *rsp; + void *metabuf; + + pend_q = &qp->pend_q; + + nb_pending = pend_q->pending_count; + + if (nb_ops > nb_pending) + nb_ops = nb_pending; + + for (i = 0; i < nb_ops; i++) { + rid = &pend_q->rid_queue[pend_q->deq_head]; + req = (struct cpt_request_info *)(rid->rid); + + cc[i] = otx2_cpt_compcode_get(req); + + if (unlikely(cc[i] == ERR_REQ_PENDING)) + break; + + ops[i] = req->op; + + MOD_INC(pend_q->deq_head, OTX2_CPT_DEFAULT_CMD_QLEN); + pend_q->pending_count -= 1; + } + + nb_completed = i; + + for (i = 0; i < nb_completed; i++) { + rsp = (void *)ops[i]; + + metabuf = (void *)rsp[0]; + cop = (void *)rsp[1]; + + ops[i] = cop; + + otx2_cpt_dequeue_post_process(qp, cop, rsp, cc[i]); + + free_op_meta(metabuf, qp->meta_info.pool); + } + + return nb_completed; +} + /* PMD ops */ static int @@ -536,6 +663,7 @@ otx2_cpt_dev_config(struct rte_cryptodev *dev, } dev->enqueue_burst = otx2_cpt_enqueue_burst; + dev->dequeue_burst = otx2_cpt_dequeue_burst; rte_mb(); return 0; From patchwork Fri Aug 30 06:28:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 58297 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D29F21E8BF; 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Thu, 29 Aug 2019 23:32:45 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Thu, 29 Aug 2019 23:32:43 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Thu, 29 Aug 2019 23:32:43 -0700 Received: from ajoseph83.caveonetworks.com.com (unknown [10.29.45.56]) by maili.marvell.com (Postfix) with ESMTP id F13D73F7040; Thu, 29 Aug 2019 23:32:39 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Pablo de Lara , Thomas Monjalon CC: Anoob Joseph , Jerin Jacob , Narayana Prasad , Ankur Dwivedi , Tejasree Kondoj , Date: Fri, 30 Aug 2019 11:58:20 +0530 Message-ID: <1567146501-8224-11-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1567146501-8224-1-git-send-email-anoobj@marvell.com> References: <1567146501-8224-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.70,1.0.8 definitions=2019-08-30_02:2019-08-29,2019-08-30 signatures=0 Subject: [dpdk-dev] [PATCH 10/11] test: add OCTEON TX2 tests X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds the OCTEON TX2 crypto validation tests. Signed-off-by: Ankur Dwivedi Signed-off-by: Anoob Joseph Signed-off-by: Tejasree Kondoj --- app/test/meson.build | 1 + app/test/test_cryptodev.c | 323 ++++++++++++++++++++++++++++ app/test/test_cryptodev.h | 1 + app/test/test_cryptodev_aes_test_vectors.h | 112 ++++++---- app/test/test_cryptodev_blockcipher.c | 7 + app/test/test_cryptodev_blockcipher.h | 1 + app/test/test_cryptodev_des_test_vectors.h | 12 +- app/test/test_cryptodev_hash_test_vectors.h | 75 ++++--- 8 files changed, 466 insertions(+), 66 deletions(-) diff --git a/app/test/meson.build b/app/test/meson.build index ec40943..b40fe9d 100644 --- a/app/test/meson.build +++ b/app/test/meson.build @@ -270,6 +270,7 @@ driver_test_names = [ 'cryptodev_dpaa_sec_autotest', 'cryptodev_dpaa2_sec_autotest', 'cryptodev_null_autotest', + 'cryptodev_octeontx2_autotest', 'cryptodev_openssl_autotest', 'cryptodev_openssl_asym_autotest', 'cryptodev_qat_autotest', diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c index 4197feb..fe2322f 100644 --- a/app/test/test_cryptodev.c +++ b/app/test/test_cryptodev.c @@ -2368,6 +2368,101 @@ test_authonly_octeontx_all(void) return TEST_SUCCESS; } +static int +test_AES_chain_octeontx2_all(void) +{ + struct crypto_testsuite_params *ts_params = &testsuite_params; + int status; + + status = test_blockcipher_all_tests(ts_params->mbuf_pool, + ts_params->op_mpool, ts_params->session_mpool, + ts_params->session_priv_mpool, + ts_params->valid_devs[0], + rte_cryptodev_driver_id_get( + RTE_STR(CRYPTODEV_NAME_OCTEONTX2_PMD)), + BLKCIPHER_AES_CHAIN_TYPE); + + TEST_ASSERT_EQUAL(status, 0, "Test failed"); + + return TEST_SUCCESS; +} + +static int +test_AES_cipheronly_octeontx2_all(void) +{ + struct crypto_testsuite_params *ts_params = &testsuite_params; + int status; + + status = test_blockcipher_all_tests(ts_params->mbuf_pool, + ts_params->op_mpool, ts_params->session_mpool, + ts_params->session_priv_mpool, + ts_params->valid_devs[0], + rte_cryptodev_driver_id_get( + RTE_STR(CRYPTODEV_NAME_OCTEONTX2_PMD)), + BLKCIPHER_AES_CIPHERONLY_TYPE); + + TEST_ASSERT_EQUAL(status, 0, "Test failed"); + + return TEST_SUCCESS; +} + +static int +test_3DES_chain_octeontx2_all(void) +{ + struct crypto_testsuite_params *ts_params = &testsuite_params; + int status; + + status = test_blockcipher_all_tests(ts_params->mbuf_pool, + ts_params->op_mpool, ts_params->session_mpool, + ts_params->session_priv_mpool, + ts_params->valid_devs[0], + rte_cryptodev_driver_id_get( + RTE_STR(CRYPTODEV_NAME_OCTEONTX2_PMD)), + BLKCIPHER_3DES_CHAIN_TYPE); + + TEST_ASSERT_EQUAL(status, 0, "Test failed"); + + return TEST_SUCCESS; +} + +static int +test_3DES_cipheronly_octeontx2_all(void) +{ + struct crypto_testsuite_params *ts_params = &testsuite_params; + int status; + + status = test_blockcipher_all_tests(ts_params->mbuf_pool, + ts_params->op_mpool, ts_params->session_mpool, + ts_params->session_priv_mpool, + ts_params->valid_devs[0], + rte_cryptodev_driver_id_get( + RTE_STR(CRYPTODEV_NAME_OCTEONTX2_PMD)), + BLKCIPHER_3DES_CIPHERONLY_TYPE); + + TEST_ASSERT_EQUAL(status, 0, "Test failed"); + + return TEST_SUCCESS; +} + +static int +test_authonly_octeontx2_all(void) +{ + struct crypto_testsuite_params *ts_params = &testsuite_params; + int status; + + status = test_blockcipher_all_tests(ts_params->mbuf_pool, + ts_params->op_mpool, ts_params->session_mpool, + ts_params->session_priv_mpool, + ts_params->valid_devs[0], + rte_cryptodev_driver_id_get( + RTE_STR(CRYPTODEV_NAME_OCTEONTX2_PMD)), + BLKCIPHER_AUTHONLY_TYPE); + + TEST_ASSERT_EQUAL(status, 0, "Test failed"); + + return TEST_SUCCESS; +} + /* ***** SNOW 3G Tests ***** */ static int create_wireless_algo_hash_session(uint8_t dev_id, @@ -11969,6 +12064,218 @@ static struct unit_test_suite cryptodev_octeontx_testsuite = { } }; +static struct unit_test_suite cryptodev_octeontx2_testsuite = { + .suite_name = "Crypto Device OCTEON TX2 Unit Test Suite", + .setup = testsuite_setup, + .teardown = testsuite_teardown, + .unit_test_cases = { + TEST_CASE_ST(ut_setup, ut_teardown, + test_AES_chain_octeontx2_all), + TEST_CASE_ST(ut_setup, ut_teardown, + test_AES_cipheronly_octeontx2_all), + TEST_CASE_ST(ut_setup, ut_teardown, + test_3DES_chain_octeontx2_all), + TEST_CASE_ST(ut_setup, ut_teardown, + test_3DES_cipheronly_octeontx2_all), + TEST_CASE_ST(ut_setup, ut_teardown, + test_authonly_octeontx2_all), + + /** AES GCM Authenticated Encryption */ + TEST_CASE_ST(ut_setup, ut_teardown, + test_AES_GCM_authenticated_encryption_test_case_1), + TEST_CASE_ST(ut_setup, ut_teardown, + test_AES_GCM_authenticated_encryption_test_case_2), + TEST_CASE_ST(ut_setup, ut_teardown, + test_AES_GCM_authenticated_encryption_test_case_3), + TEST_CASE_ST(ut_setup, ut_teardown, + test_AES_GCM_authenticated_encryption_test_case_4), + TEST_CASE_ST(ut_setup, ut_teardown, + test_AES_GCM_authenticated_encryption_test_case_5), + TEST_CASE_ST(ut_setup, ut_teardown, + test_AES_GCM_authenticated_encryption_test_case_6), + TEST_CASE_ST(ut_setup, ut_teardown, + test_AES_GCM_authenticated_encryption_test_case_7), + + /** AES GCM Authenticated Decryption */ + TEST_CASE_ST(ut_setup, ut_teardown, + test_AES_GCM_authenticated_decryption_test_case_1), + TEST_CASE_ST(ut_setup, ut_teardown, + test_AES_GCM_authenticated_decryption_test_case_2), + TEST_CASE_ST(ut_setup, ut_teardown, + test_AES_GCM_authenticated_decryption_test_case_3), + TEST_CASE_ST(ut_setup, ut_teardown, + test_AES_GCM_authenticated_decryption_test_case_4), + TEST_CASE_ST(ut_setup, ut_teardown, + test_AES_GCM_authenticated_decryption_test_case_5), + TEST_CASE_ST(ut_setup, ut_teardown, + test_AES_GCM_authenticated_decryption_test_case_6), + TEST_CASE_ST(ut_setup, ut_teardown, + test_AES_GCM_authenticated_decryption_test_case_7), + /** AES GMAC Authentication */ + TEST_CASE_ST(ut_setup, ut_teardown, + test_AES_GMAC_authentication_test_case_1), + TEST_CASE_ST(ut_setup, ut_teardown, + test_AES_GMAC_authentication_verify_test_case_1), + TEST_CASE_ST(ut_setup, ut_teardown, + test_AES_GMAC_authentication_test_case_2), + TEST_CASE_ST(ut_setup, ut_teardown, + test_AES_GMAC_authentication_verify_test_case_2), + TEST_CASE_ST(ut_setup, ut_teardown, + test_AES_GMAC_authentication_test_case_3), + TEST_CASE_ST(ut_setup, ut_teardown, + test_AES_GMAC_authentication_verify_test_case_3), + + /** SNOW 3G encrypt only (UEA2) */ + TEST_CASE_ST(ut_setup, ut_teardown, + test_snow3g_encryption_test_case_1), + TEST_CASE_ST(ut_setup, ut_teardown, + test_snow3g_encryption_test_case_2), + TEST_CASE_ST(ut_setup, ut_teardown, + test_snow3g_encryption_test_case_3), + TEST_CASE_ST(ut_setup, ut_teardown, + test_snow3g_encryption_test_case_4), + TEST_CASE_ST(ut_setup, ut_teardown, + test_snow3g_encryption_test_case_5), + + TEST_CASE_ST(ut_setup, ut_teardown, + test_snow3g_encryption_test_case_1_oop), + TEST_CASE_ST(ut_setup, ut_teardown, + test_snow3g_decryption_test_case_1_oop), + TEST_CASE_ST(ut_setup, ut_teardown, + test_snow3g_encryption_test_case_1_oop_sgl), + + /** SNOW 3G decrypt only (UEA2) */ + TEST_CASE_ST(ut_setup, ut_teardown, + test_snow3g_decryption_test_case_1), + TEST_CASE_ST(ut_setup, ut_teardown, + test_snow3g_decryption_test_case_2), + TEST_CASE_ST(ut_setup, ut_teardown, + test_snow3g_decryption_test_case_3), + TEST_CASE_ST(ut_setup, ut_teardown, + test_snow3g_decryption_test_case_4), + TEST_CASE_ST(ut_setup, ut_teardown, + test_snow3g_decryption_test_case_5), + + TEST_CASE_ST(ut_setup, ut_teardown, + test_snow3g_hash_generate_test_case_1), + TEST_CASE_ST(ut_setup, ut_teardown, + test_snow3g_hash_generate_test_case_2), + TEST_CASE_ST(ut_setup, ut_teardown, + test_snow3g_hash_generate_test_case_3), + TEST_CASE_ST(ut_setup, ut_teardown, + test_snow3g_hash_verify_test_case_1), + TEST_CASE_ST(ut_setup, ut_teardown, + test_snow3g_hash_verify_test_case_2), + TEST_CASE_ST(ut_setup, ut_teardown, + test_snow3g_hash_verify_test_case_3), + + /** ZUC encrypt only (EEA3) */ + TEST_CASE_ST(ut_setup, ut_teardown, + test_zuc_encryption_test_case_1), + TEST_CASE_ST(ut_setup, ut_teardown, + test_zuc_encryption_test_case_2), + TEST_CASE_ST(ut_setup, ut_teardown, + test_zuc_encryption_test_case_3), + TEST_CASE_ST(ut_setup, ut_teardown, + test_zuc_encryption_test_case_4), + TEST_CASE_ST(ut_setup, ut_teardown, + test_zuc_encryption_test_case_5), + TEST_CASE_ST(ut_setup, ut_teardown, + test_zuc_hash_generate_test_case_1), + TEST_CASE_ST(ut_setup, ut_teardown, + test_zuc_hash_generate_test_case_2), + TEST_CASE_ST(ut_setup, ut_teardown, + test_zuc_hash_generate_test_case_3), + TEST_CASE_ST(ut_setup, ut_teardown, + test_zuc_hash_generate_test_case_4), + TEST_CASE_ST(ut_setup, ut_teardown, + test_zuc_hash_generate_test_case_5), + TEST_CASE_ST(ut_setup, ut_teardown, + test_zuc_encryption_test_case_6_sgl), + + /** KASUMI encrypt only (UEA1) */ + TEST_CASE_ST(ut_setup, ut_teardown, + test_kasumi_encryption_test_case_1), + TEST_CASE_ST(ut_setup, ut_teardown, + test_kasumi_encryption_test_case_2), + TEST_CASE_ST(ut_setup, ut_teardown, + test_kasumi_encryption_test_case_3), + TEST_CASE_ST(ut_setup, ut_teardown, + test_kasumi_encryption_test_case_4), + TEST_CASE_ST(ut_setup, ut_teardown, + test_kasumi_encryption_test_case_5), + TEST_CASE_ST(ut_setup, ut_teardown, + test_kasumi_encryption_test_case_1_sgl), + TEST_CASE_ST(ut_setup, ut_teardown, + test_kasumi_encryption_test_case_1_oop_sgl), + /** KASUMI decrypt only (UEA1) */ + TEST_CASE_ST(ut_setup, ut_teardown, + test_kasumi_decryption_test_case_1), + TEST_CASE_ST(ut_setup, ut_teardown, + test_kasumi_decryption_test_case_2), + TEST_CASE_ST(ut_setup, ut_teardown, + test_kasumi_decryption_test_case_3), + TEST_CASE_ST(ut_setup, ut_teardown, + test_kasumi_decryption_test_case_4), + TEST_CASE_ST(ut_setup, ut_teardown, + test_kasumi_decryption_test_case_5), + + TEST_CASE_ST(ut_setup, ut_teardown, + test_kasumi_encryption_test_case_1_oop), + TEST_CASE_ST(ut_setup, ut_teardown, + test_kasumi_decryption_test_case_1_oop), + + /** KASUMI hash only (UIA1) */ + TEST_CASE_ST(ut_setup, ut_teardown, + test_kasumi_hash_generate_test_case_1), + TEST_CASE_ST(ut_setup, ut_teardown, + test_kasumi_hash_generate_test_case_2), + TEST_CASE_ST(ut_setup, ut_teardown, + test_kasumi_hash_generate_test_case_3), + TEST_CASE_ST(ut_setup, ut_teardown, + test_kasumi_hash_generate_test_case_4), + TEST_CASE_ST(ut_setup, ut_teardown, + test_kasumi_hash_generate_test_case_5), + TEST_CASE_ST(ut_setup, ut_teardown, + test_kasumi_hash_generate_test_case_6), + TEST_CASE_ST(ut_setup, ut_teardown, + test_kasumi_hash_verify_test_case_1), + TEST_CASE_ST(ut_setup, ut_teardown, + test_kasumi_hash_verify_test_case_2), + TEST_CASE_ST(ut_setup, ut_teardown, + test_kasumi_hash_verify_test_case_3), + TEST_CASE_ST(ut_setup, ut_teardown, + test_kasumi_hash_verify_test_case_4), + TEST_CASE_ST(ut_setup, ut_teardown, + test_kasumi_hash_verify_test_case_5), + + /** NULL tests */ + TEST_CASE_ST(ut_setup, ut_teardown, + test_null_cipher_only_operation), + TEST_CASE_ST(ut_setup, ut_teardown, + test_null_auth_only_operation), + TEST_CASE_ST(ut_setup, ut_teardown, + test_null_cipher_auth_operation), + TEST_CASE_ST(ut_setup, ut_teardown, + test_null_auth_cipher_operation), + + /** Negative tests */ + TEST_CASE_ST(ut_setup, ut_teardown, + authentication_verify_HMAC_SHA1_fail_data_corrupt), + TEST_CASE_ST(ut_setup, ut_teardown, + authentication_verify_HMAC_SHA1_fail_tag_corrupt), + TEST_CASE_ST(ut_setup, ut_teardown, + authentication_verify_AES128_GMAC_fail_data_corrupt), + TEST_CASE_ST(ut_setup, ut_teardown, + authentication_verify_AES128_GMAC_fail_tag_corrupt), + TEST_CASE_ST(ut_setup, ut_teardown, + auth_decryption_AES128CBC_HMAC_SHA1_fail_data_corrupt), + TEST_CASE_ST(ut_setup, ut_teardown, + auth_decryption_AES128CBC_HMAC_SHA1_fail_tag_corrupt), + TEST_CASES_END() /**< NULL terminate unit test array */ + } +}; + static int test_cryptodev_qat(void /*argv __rte_unused, int argc __rte_unused*/) { @@ -12237,6 +12544,21 @@ test_cryptodev_octeontx(void) } static int +test_cryptodev_octeontx2(void) +{ + gbl_driver_id = rte_cryptodev_driver_id_get( + RTE_STR(CRYPTODEV_NAME_OCTEONTX2_PMD)); + if (gbl_driver_id == -1) { + RTE_LOG(ERR, USER1, "OCTEON TX2 PMD must be loaded. Check if " + "CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO is " + "enabled in config file to run this " + "testsuite.\n"); + return TEST_FAILED; + } + return unit_test_suite_runner(&cryptodev_octeontx2_testsuite); +} + +static int test_cryptodev_caam_jr(void /*argv __rte_unused, int argc __rte_unused*/) { gbl_driver_id = rte_cryptodev_driver_id_get( @@ -12267,4 +12589,5 @@ REGISTER_TEST_COMMAND(cryptodev_dpaa_sec_autotest, test_cryptodev_dpaa_sec); REGISTER_TEST_COMMAND(cryptodev_ccp_autotest, test_cryptodev_ccp); REGISTER_TEST_COMMAND(cryptodev_virtio_autotest, test_cryptodev_virtio); REGISTER_TEST_COMMAND(cryptodev_octeontx_autotest, test_cryptodev_octeontx); +REGISTER_TEST_COMMAND(cryptodev_octeontx2_autotest, test_cryptodev_octeontx2); REGISTER_TEST_COMMAND(cryptodev_caam_jr_autotest, test_cryptodev_caam_jr); diff --git a/app/test/test_cryptodev.h b/app/test/test_cryptodev.h index 14b54dc..241ed72 100644 --- a/app/test/test_cryptodev.h +++ b/app/test/test_cryptodev.h @@ -66,6 +66,7 @@ #define CRYPTODEV_NAME_CCP_PMD crypto_ccp #define CRYPTODEV_NAME_VIRTIO_PMD crypto_virtio #define CRYPTODEV_NAME_OCTEONTX_SYM_PMD crypto_octeontx +#define CRYPTODEV_NAME_OCTEONTX2_PMD crypto_octeontx2 #define CRYPTODEV_NAME_CAAM_JR_PMD crypto_caam_jr /** diff --git a/app/test/test_cryptodev_aes_test_vectors.h b/app/test/test_cryptodev_aes_test_vectors.h index ee4fdc9..986476d 100644 --- a/app/test/test_cryptodev_aes_test_vectors.h +++ b/app/test/test_cryptodev_aes_test_vectors.h @@ -1638,7 +1638,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | BLOCKCIPHER_TEST_TARGET_PMD_CCP | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-128-CBC HMAC-SHA1 Encryption Digest " @@ -1647,7 +1648,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = { .op_mask = BLOCKCIPHER_TEST_OP_ENC_AUTH_GEN, .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 | BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-128-CBC HMAC-SHA1 Encryption Digest " @@ -1663,7 +1665,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC | BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC | BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-128-CBC HMAC-SHA1 Decryption Digest " @@ -1680,7 +1683,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | BLOCKCIPHER_TEST_TARGET_PMD_CCP | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-128-CBC HMAC-SHA1 Decryption Digest " @@ -1691,7 +1695,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = { .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC | BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC | BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-128-CBC HMAC-SHA1 Decryption Digest " @@ -1700,7 +1705,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = { .op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY_DEC, .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 | BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-128-CBC HMAC-SHA256 Encryption Digest", @@ -1716,7 +1722,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | BLOCKCIPHER_TEST_TARGET_PMD_CCP | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-128-CBC HMAC-SHA256 Encryption Digest " @@ -1725,7 +1732,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = { .op_mask = BLOCKCIPHER_TEST_OP_ENC_AUTH_GEN, .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 | BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-128-CBC HMAC-SHA256 Decryption Digest " @@ -1741,7 +1749,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC | BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | BLOCKCIPHER_TEST_TARGET_PMD_CCP | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-128-CBC HMAC-SHA256 Decryption Digest " @@ -1750,7 +1759,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = { .op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY_DEC, .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 | BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-128-CBC HMAC-SHA512 Encryption Digest", @@ -1765,7 +1775,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | BLOCKCIPHER_TEST_TARGET_PMD_CCP | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-128-CBC HMAC-SHA512 Encryption Digest " @@ -1776,7 +1787,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = { .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB | BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL | BLOCKCIPHER_TEST_TARGET_PMD_CCP | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-128-CBC HMAC-SHA512 Encryption Digest " @@ -1788,7 +1800,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = { BLOCKCIPHER_TEST_FEATURE_OOP, .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-128-CBC HMAC-SHA512 Decryption Digest " @@ -1804,7 +1817,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | BLOCKCIPHER_TEST_TARGET_PMD_CCP | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-128-CBC HMAC-SHA512 Decryption Digest " @@ -1819,7 +1833,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC | BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC | BLOCKCIPHER_TEST_TARGET_PMD_SCHEDULER | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-128-CBC XCBC Encryption Digest", @@ -1850,7 +1865,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC | BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | BLOCKCIPHER_TEST_TARGET_PMD_MB | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-128-CBC HMAC-SHA1 Encryption Digest " @@ -1874,6 +1890,7 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC | BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 | BLOCKCIPHER_TEST_TARGET_PMD_MB }, { @@ -1888,7 +1905,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC | BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | BLOCKCIPHER_TEST_TARGET_PMD_CCP | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-128-CBC HMAC-SHA224 Decryption Digest " @@ -1903,7 +1921,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC | BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | BLOCKCIPHER_TEST_TARGET_PMD_CCP | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-128-CBC HMAC-SHA384 Encryption Digest", @@ -1943,7 +1962,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = { .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 | BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL | BLOCKCIPHER_TEST_TARGET_PMD_CCP | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = @@ -1955,7 +1975,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = { .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 | BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL | BLOCKCIPHER_TEST_TARGET_PMD_CCP | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "NULL-CIPHER-NULL-AUTH encrypt & gen x8byte", @@ -2058,7 +2079,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | BLOCKCIPHER_TEST_TARGET_PMD_CCP | BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-128-CBC Decryption", @@ -2074,7 +2096,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | BLOCKCIPHER_TEST_TARGET_PMD_CCP | BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-192-CBC Encryption", @@ -2089,7 +2112,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | BLOCKCIPHER_TEST_TARGET_PMD_CCP | BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-192-CBC Encryption Scater gather", @@ -2101,7 +2125,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC | BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC | BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-192-CBC Decryption", @@ -2116,7 +2141,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | BLOCKCIPHER_TEST_TARGET_PMD_CCP | BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-192-CBC Decryption Scatter Gather", @@ -2126,7 +2152,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = { .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC | BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC | BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-256-CBC Encryption", @@ -2142,7 +2169,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | BLOCKCIPHER_TEST_TARGET_PMD_CCP | BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-256-CBC Decryption", @@ -2158,7 +2186,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | BLOCKCIPHER_TEST_TARGET_PMD_CCP | BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-256-CBC OOP Encryption", @@ -2201,7 +2230,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | BLOCKCIPHER_TEST_TARGET_PMD_CCP | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-128-CTR Decryption", @@ -2216,7 +2246,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | BLOCKCIPHER_TEST_TARGET_PMD_CCP | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-192-CTR Encryption", @@ -2230,7 +2261,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC | BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | BLOCKCIPHER_TEST_TARGET_PMD_CCP | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-192-CTR Decryption", @@ -2244,7 +2276,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC | BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | BLOCKCIPHER_TEST_TARGET_PMD_CCP | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-256-CTR Encryption", @@ -2259,7 +2292,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | BLOCKCIPHER_TEST_TARGET_PMD_CCP | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-256-CTR Decryption", @@ -2274,28 +2308,32 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | BLOCKCIPHER_TEST_TARGET_PMD_CCP | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-128-CTR Encryption (12-byte IV)", .test_data = &aes_test_data_1_IV_12_bytes, .op_mask = BLOCKCIPHER_TEST_OP_ENCRYPT, .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-192-CTR Encryption (12-byte IV)", .test_data = &aes_test_data_2_IV_12_bytes, .op_mask = BLOCKCIPHER_TEST_OP_ENCRYPT, .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-256-CTR Encryption (12-byte IV)", .test_data = &aes_test_data_3_IV_12_bytes, .op_mask = BLOCKCIPHER_TEST_OP_ENCRYPT, .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "AES-128-XTS Encryption (16-byte plaintext)", diff --git a/app/test/test_cryptodev_blockcipher.c b/app/test/test_cryptodev_blockcipher.c index b8dcc39..4f0278c 100644 --- a/app/test/test_cryptodev_blockcipher.c +++ b/app/test/test_cryptodev_blockcipher.c @@ -77,6 +77,8 @@ test_blockcipher_one_case(const struct blockcipher_test_case *t, RTE_STR(CRYPTODEV_NAME_VIRTIO_PMD)); int octeontx_pmd = rte_cryptodev_driver_id_get( RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD)); + int octeontx2_pmd = rte_cryptodev_driver_id_get( + RTE_STR(CRYPTODEV_NAME_OCTEONTX2_PMD)); int null_pmd = rte_cryptodev_driver_id_get( RTE_STR(CRYPTODEV_NAME_NULL_PMD)); @@ -125,6 +127,7 @@ test_blockcipher_one_case(const struct blockcipher_test_case *t, driver_id == ccp_pmd || driver_id == virtio_pmd || driver_id == octeontx_pmd || + driver_id == octeontx2_pmd || driver_id == null_pmd) { /* Fall through */ digest_len = tdata->digest.len; } else if (driver_id == aesni_mb_pmd || @@ -715,6 +718,8 @@ test_blockcipher_all_tests(struct rte_mempool *mbuf_pool, RTE_STR(CRYPTODEV_NAME_VIRTIO_PMD)); int octeontx_pmd = rte_cryptodev_driver_id_get( RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD)); + int octeontx2_pmd = rte_cryptodev_driver_id_get( + RTE_STR(CRYPTODEV_NAME_OCTEONTX2_PMD)); int null_pmd = rte_cryptodev_driver_id_get( RTE_STR(CRYPTODEV_NAME_NULL_PMD)); @@ -787,6 +792,8 @@ test_blockcipher_all_tests(struct rte_mempool *mbuf_pool, target_pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO; else if (driver_id == octeontx_pmd) target_pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX; + else if (driver_id == octeontx2_pmd) + target_pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2; else if (driver_id == null_pmd) target_pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_NULL; else diff --git a/app/test/test_cryptodev_blockcipher.h b/app/test/test_cryptodev_blockcipher.h index 3d4b975..d5e0801 100644 --- a/app/test/test_cryptodev_blockcipher.h +++ b/app/test/test_cryptodev_blockcipher.h @@ -32,6 +32,7 @@ #define BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR 0x0400 /* CAAM_JR flag */ #define BLOCKCIPHER_TEST_TARGET_PMD_CCP 0x0800 /* CCP flag */ #define BLOCKCIPHER_TEST_TARGET_PMD_NULL 0x1000 /* NULL flag */ +#define BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 0x2000 /* OCTEON TX2 flag */ #define BLOCKCIPHER_TEST_OP_CIPHER (BLOCKCIPHER_TEST_OP_ENCRYPT | \ BLOCKCIPHER_TEST_OP_DECRYPT) diff --git a/app/test/test_cryptodev_des_test_vectors.h b/app/test/test_cryptodev_des_test_vectors.h index a71b0e9..9d2d0e7 100644 --- a/app/test/test_cryptodev_des_test_vectors.h +++ b/app/test/test_cryptodev_des_test_vectors.h @@ -1114,7 +1114,8 @@ static const struct blockcipher_test_case triple_des_chain_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | BLOCKCIPHER_TEST_TARGET_PMD_CCP | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "3DES-192-CBC HMAC-SHA1 Decryption Digest Verify", @@ -1127,7 +1128,8 @@ static const struct blockcipher_test_case triple_des_chain_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | BLOCKCIPHER_TEST_TARGET_PMD_CCP | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "3DES-192-CBC SHA1 Encryption Digest", @@ -1296,7 +1298,8 @@ static const struct blockcipher_test_case triple_des_cipheronly_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | BLOCKCIPHER_TEST_TARGET_PMD_CCP | BLOCKCIPHER_TEST_TARGET_PMD_MB | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "3DES-192-CBC Decryption", @@ -1310,7 +1313,8 @@ static const struct blockcipher_test_case triple_des_cipheronly_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | BLOCKCIPHER_TEST_TARGET_PMD_CCP | BLOCKCIPHER_TEST_TARGET_PMD_MB | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "3DES-128-CTR Encryption", diff --git a/app/test/test_cryptodev_hash_test_vectors.h b/app/test/test_cryptodev_hash_test_vectors.h index 6f201c0..cff2831 100644 --- a/app/test/test_cryptodev_hash_test_vectors.h +++ b/app/test/test_cryptodev_hash_test_vectors.h @@ -413,7 +413,8 @@ static const struct blockcipher_test_case hash_test_cases[] = { .op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN, .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL | BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "MD5 Digest Verify", @@ -421,7 +422,8 @@ static const struct blockcipher_test_case hash_test_cases[] = { .op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY, .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL | BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "HMAC-MD5 Digest", @@ -435,7 +437,8 @@ static const struct blockcipher_test_case hash_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | BLOCKCIPHER_TEST_TARGET_PMD_QAT | BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "HMAC-MD5 Digest Verify", @@ -449,7 +452,8 @@ static const struct blockcipher_test_case hash_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | BLOCKCIPHER_TEST_TARGET_PMD_QAT | BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "SHA1 Digest", @@ -461,7 +465,8 @@ static const struct blockcipher_test_case hash_test_cases[] = { #if IMB_VERSION_NUM >= IMB_VERSION(0, 52, 0) BLOCKCIPHER_TEST_TARGET_PMD_MB | #endif - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "SHA1 Digest Verify", @@ -473,7 +478,8 @@ static const struct blockcipher_test_case hash_test_cases[] = { #if IMB_VERSION_NUM >= IMB_VERSION(0, 52, 0) BLOCKCIPHER_TEST_TARGET_PMD_MB | #endif - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "HMAC-SHA1 Digest", @@ -488,7 +494,8 @@ static const struct blockcipher_test_case hash_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_QAT | BLOCKCIPHER_TEST_TARGET_PMD_CCP | BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "HMAC-SHA1 Digest Scatter Gather", @@ -498,7 +505,8 @@ static const struct blockcipher_test_case hash_test_cases[] = { .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC | BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC | BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "HMAC-SHA1 Digest Verify", @@ -513,7 +521,8 @@ static const struct blockcipher_test_case hash_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_QAT | BLOCKCIPHER_TEST_TARGET_PMD_CCP | BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "HMAC-SHA1 Digest Verify Scatter Gather", @@ -523,7 +532,8 @@ static const struct blockcipher_test_case hash_test_cases[] = { .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC | BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC | BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "SHA224 Digest", @@ -535,7 +545,8 @@ static const struct blockcipher_test_case hash_test_cases[] = { #if IMB_VERSION_NUM >= IMB_VERSION(0, 52, 0) BLOCKCIPHER_TEST_TARGET_PMD_MB | #endif - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "SHA224 Digest Verify", @@ -547,7 +558,8 @@ static const struct blockcipher_test_case hash_test_cases[] = { #if IMB_VERSION_NUM >= IMB_VERSION(0, 52, 0) BLOCKCIPHER_TEST_TARGET_PMD_MB | #endif - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "HMAC-SHA224 Digest", @@ -561,7 +573,8 @@ static const struct blockcipher_test_case hash_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | BLOCKCIPHER_TEST_TARGET_PMD_CCP | BLOCKCIPHER_TEST_TARGET_PMD_QAT | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "HMAC-SHA224 Digest Verify", @@ -575,7 +588,8 @@ static const struct blockcipher_test_case hash_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR | BLOCKCIPHER_TEST_TARGET_PMD_CCP | BLOCKCIPHER_TEST_TARGET_PMD_QAT | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "SHA256 Digest", @@ -587,7 +601,8 @@ static const struct blockcipher_test_case hash_test_cases[] = { #if IMB_VERSION_NUM >= IMB_VERSION(0, 52, 0) BLOCKCIPHER_TEST_TARGET_PMD_MB | #endif - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "SHA256 Digest Verify", @@ -599,7 +614,8 @@ static const struct blockcipher_test_case hash_test_cases[] = { #if IMB_VERSION_NUM >= IMB_VERSION(0, 52, 0) BLOCKCIPHER_TEST_TARGET_PMD_MB | #endif - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "HMAC-SHA256 Digest", @@ -614,7 +630,8 @@ static const struct blockcipher_test_case hash_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_QAT | BLOCKCIPHER_TEST_TARGET_PMD_CCP | BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "HMAC-SHA256 Digest Verify", @@ -629,7 +646,8 @@ static const struct blockcipher_test_case hash_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_QAT | BLOCKCIPHER_TEST_TARGET_PMD_CCP | BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "SHA384 Digest", @@ -641,7 +659,8 @@ static const struct blockcipher_test_case hash_test_cases[] = { #if IMB_VERSION_NUM >= IMB_VERSION(0, 52, 0) BLOCKCIPHER_TEST_TARGET_PMD_MB | #endif - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "SHA384 Digest Verify", @@ -653,7 +672,8 @@ static const struct blockcipher_test_case hash_test_cases[] = { #if IMB_VERSION_NUM >= IMB_VERSION(0, 52, 0) BLOCKCIPHER_TEST_TARGET_PMD_MB | #endif - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "HMAC-SHA384 Digest", @@ -668,7 +688,8 @@ static const struct blockcipher_test_case hash_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_QAT | BLOCKCIPHER_TEST_TARGET_PMD_CCP | BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "HMAC-SHA384 Digest Verify", @@ -683,7 +704,8 @@ static const struct blockcipher_test_case hash_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_QAT | BLOCKCIPHER_TEST_TARGET_PMD_CCP | BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "SHA512 Digest", @@ -707,7 +729,8 @@ static const struct blockcipher_test_case hash_test_cases[] = { #if IMB_VERSION_NUM >= IMB_VERSION(0, 52, 0) BLOCKCIPHER_TEST_TARGET_PMD_MB | #endif - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "HMAC-SHA512 Digest", @@ -722,7 +745,8 @@ static const struct blockcipher_test_case hash_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_QAT | BLOCKCIPHER_TEST_TARGET_PMD_CCP | BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "HMAC-SHA512 Digest Verify", @@ -737,7 +761,8 @@ static const struct blockcipher_test_case hash_test_cases[] = { BLOCKCIPHER_TEST_TARGET_PMD_QAT | BLOCKCIPHER_TEST_TARGET_PMD_CCP | BLOCKCIPHER_TEST_TARGET_PMD_MVSAM | - BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX | + BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 }, { .test_descr = "CMAC Digest 12B", From patchwork Fri Aug 30 06:28:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 58298 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A17591E8EC; Fri, 30 Aug 2019 08:32:52 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 031631E86B for ; Fri, 30 Aug 2019 08:32:50 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x7U6Thvq024118; Thu, 29 Aug 2019 23:32:50 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=pfpt0818; bh=xR7TLOMwcn1KDcAz0UgECkvM3AKhyXmEyT0QgYfu6FE=; b=XMljaks2+qNG4jLOVFWHV1FAxYH4OUElOp3JVEQO8pUs458iVpRQisJre+k59Fsldaru l/ifcj8OQk0XiBc+nxH4Yc2QYo6uSnO5ucOha4mPmNQTVbr8Fxaquh0aKoeSg+iG6yl0 kIjcolfTSFgOx4pMlT0GtQbyS+dcU4hFVR67LO1OK0OoXLohcc0HUm2U1yInw40dUGhl 2DBVEc+GFK1ZlN/nNjobrnsNJ2BLYt/61eAsZiWO+VtPEku3U0IKr7D+gF2ORFocBy1/ tVNNZghAhdsE7GI9iV9jKvjfJnGpqrhMX4ofWzgekOASKF0oMu9otEc5Y2s8GgSHPDd1 ag== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0a-0016f401.pphosted.com with ESMTP id 2upmepj422-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2019 23:32:50 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Thu, 29 Aug 2019 23:32:48 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Thu, 29 Aug 2019 23:32:48 -0700 Received: from ajoseph83.caveonetworks.com.com (unknown [10.29.45.56]) by maili.marvell.com (Postfix) with ESMTP id 5BBF43F703F; Thu, 29 Aug 2019 23:32:45 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Pablo de Lara , Thomas Monjalon CC: Anoob Joseph , Jerin Jacob , Narayana Prasad , Ankur Dwivedi , Tejasree Kondoj , Date: Fri, 30 Aug 2019 11:58:21 +0530 Message-ID: <1567146501-8224-12-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1567146501-8224-1-git-send-email-anoobj@marvell.com> References: <1567146501-8224-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.70,1.0.8 definitions=2019-08-30_02:2019-08-29,2019-08-30 signatures=0 Subject: [dpdk-dev] [PATCH 11/11] doc: add documentation for OCTEON TX2 crypto PMD X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Adding feature list and user guide for OCTEONTX2 crypto PMD. Signed-off-by: Ankur Dwivedi Signed-off-by: Anoob Joseph --- MAINTAINERS | 7 ++ doc/guides/cryptodevs/features/octeontx2.ini | 62 ++++++++++++ doc/guides/cryptodevs/index.rst | 1 + doc/guides/cryptodevs/octeontx2.rst | 142 +++++++++++++++++++++++++++ doc/guides/platform/octeontx2.rst | 3 + 5 files changed, 215 insertions(+) create mode 100644 doc/guides/cryptodevs/features/octeontx2.ini create mode 100644 doc/guides/cryptodevs/octeontx2.rst diff --git a/MAINTAINERS b/MAINTAINERS index 4100260..eef64f7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -965,6 +965,13 @@ F: drivers/crypto/mvsam/ F: doc/guides/cryptodevs/mvsam.rst F: doc/guides/cryptodevs/features/mvsam.ini +Marvell OCTEON TX2 crypto +M: Ankur Dwivedi +M: Anoob Joseph +F: drivers/crypto/octeontx2/ +F: doc/guides/cryptodevs/octeontx2.rst +F: doc/guides/cryptodevs/features/octeontx2.ini + Null Crypto M: Declan Doherty F: drivers/crypto/null/ diff --git a/doc/guides/cryptodevs/features/octeontx2.ini b/doc/guides/cryptodevs/features/octeontx2.ini new file mode 100644 index 0000000..ac76b11 --- /dev/null +++ b/doc/guides/cryptodevs/features/octeontx2.ini @@ -0,0 +1,62 @@ +; +; Supported features of the 'octeontx2' crypto driver. +; +; Refer to default.ini for the full list of available PMD features. +; +[Features] +Symmetric crypto = Y +Sym operation chaining = Y +HW Accelerated = Y +In Place SGL = Y +OOP SGL In LB Out = Y +OOP SGL In SGL Out = Y + +; +; Supported crypto algorithms of 'octeontx2' crypto driver. +; +[Cipher] +NULL = Y +3DES CBC = Y +3DES ECB = Y +AES CBC (128) = Y +AES CBC (192) = Y +AES CBC (256) = Y +AES CTR (128) = Y +AES CTR (192) = Y +AES CTR (256) = Y +AES XTS (128) = Y +AES XTS (256) = Y +DES CBC = Y +KASUMI F8 = Y +SNOW3G UEA2 = Y +ZUC EEA3 = Y + +; +; Supported authentication algorithms of 'octeontx2' crypto driver. +; +[Auth] +NULL = Y +AES GMAC = Y +KASUMI F9 = Y +MD5 = Y +MD5 HMAC = Y +SHA1 = Y +SHA1 HMAC = Y +SHA224 = Y +SHA224 HMAC = Y +SHA256 = Y +SHA256 HMAC = Y +SHA384 = Y +SHA384 HMAC = Y +SHA512 = Y +SHA512 HMAC = Y +SNOW3G UIA2 = Y +ZUC EIA3 = Y + +; +; Supported AEAD algorithms of 'octeontx2' crypto driver. +; +[AEAD] +AES GCM (128) = Y +AES GCM (192) = Y +AES GCM (256) = Y diff --git a/doc/guides/cryptodevs/index.rst b/doc/guides/cryptodevs/index.rst index 83610e6..1efb3fa 100644 --- a/doc/guides/cryptodevs/index.rst +++ b/doc/guides/cryptodevs/index.rst @@ -19,6 +19,7 @@ Crypto Device Drivers dpaa_sec kasumi octeontx + octeontx2 openssl mvsam null diff --git a/doc/guides/cryptodevs/octeontx2.rst b/doc/guides/cryptodevs/octeontx2.rst new file mode 100644 index 0000000..a2cbb50 --- /dev/null +++ b/doc/guides/cryptodevs/octeontx2.rst @@ -0,0 +1,142 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(c) 2019 Marvell International Ltd. + + +Marvell OCTEON TX2 Crypto Poll Mode Driver +========================================== + +The OCTEON TX2 crypto poll mode driver provides support for offloading +cryptographic operations to cryptographic accelerator units on the +**OCTEON TX2** :sup:`®` family of processors (CN9XXX). + +More information about OCTEON TX2 SoCs may be obtained from ``_ + +Features +-------- + +The OCTEON TX2 crypto PMD has support for: + +Cipher algorithms: + +* ``RTE_CRYPTO_CIPHER_NULL`` +* ``RTE_CRYPTO_CIPHER_3DES_CBC`` +* ``RTE_CRYPTO_CIPHER_3DES_ECB`` +* ``RTE_CRYPTO_CIPHER_AES_CBC`` +* ``RTE_CRYPTO_CIPHER_AES_CTR`` +* ``RTE_CRYPTO_CIPHER_AES_XTS`` +* ``RTE_CRYPTO_CIPHER_DES_CBC`` +* ``RTE_CRYPTO_CIPHER_KASUMI_F8`` +* ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2`` +* ``RTE_CRYPTO_CIPHER_ZUC_EEA3`` + +Hash algorithms: + +* ``RTE_CRYPTO_AUTH_NULL`` +* ``RTE_CRYPTO_AUTH_AES_GMAC`` +* ``RTE_CRYPTO_AUTH_KASUMI_F9`` +* ``RTE_CRYPTO_AUTH_MD5`` +* ``RTE_CRYPTO_AUTH_MD5_HMAC`` +* ``RTE_CRYPTO_AUTH_SHA1`` +* ``RTE_CRYPTO_AUTH_SHA1_HMAC`` +* ``RTE_CRYPTO_AUTH_SHA224`` +* ``RTE_CRYPTO_AUTH_SHA224_HMAC`` +* ``RTE_CRYPTO_AUTH_SHA256`` +* ``RTE_CRYPTO_AUTH_SHA256_HMAC`` +* ``RTE_CRYPTO_AUTH_SHA384`` +* ``RTE_CRYPTO_AUTH_SHA384_HMAC`` +* ``RTE_CRYPTO_AUTH_SHA512`` +* ``RTE_CRYPTO_AUTH_SHA512_HMAC`` +* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2`` +* ``RTE_CRYPTO_AUTH_ZUC_EIA3`` + +AEAD algorithms: + +* ``RTE_CRYPTO_AEAD_AES_GCM`` + + +Installation +------------ + +The OCTEON TX2 crypto PMD may be compiled natively on an OCTEON TX2 platform or +cross-compiled on an x86 platform. + +Enable OCTEON TX2 crypto PMD in your config file: + +* ``CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO=y`` + +Refer to :doc:`../platform/octeontx2` for instructions to build your DPDK +application. + +.. note:: + + The OCTEON TX2 crypto PMD uses services from the kernel mode OCTEON TX2 + crypto PF driver in linux. This driver is included in the OCTEON TX SDK. + +Initialization +-------------- + +List the CPT PF devices available on your OCTEON TX2 platform: + +.. code-block:: console + + lspci -d:a0fd + +``a0fd`` is the CPT PF device id. You should see output similar to: + +.. code-block:: console + + 0002:10:00.0 Class 1080: Device 177d:a0fd + +Set ``sriov_numvfs`` on the CPT PF device, to create a VF: + +.. code-block:: console + + echo 1 > /sys/bus/pci/drivers/octeontx2-cpt/0002:10:00.0/sriov_numvfs + +Bind the CPT VF device to the vfio_pci driver: + +.. code-block:: console + + echo '177d a0fe' > /sys/bus/pci/drivers/vfio-pci/new_id + echo 0002:10:00.1 > /sys/bus/pci/devices/0002:10:00.1/driver/unbind + echo 0002:10:00.1 > /sys/bus/pci/drivers/vfio-pci/bind + +Another way to bind the VF would be to use the ``dpdk-devbind.py`` script: + +.. code-block:: console + + cd + ./usertools/dpdk-devbind.py -u 0002:10:00.1 + ./usertools/dpdk-devbind.py -b vfio-pci 0002:10.00.1 + +.. note:: + + Ensure that sufficient huge pages are available for your application:: + + echo 8 > /sys/kernel/mm/hugepages/hugepages-524288kB/nr_hugepages + + Refer to :ref:`linux_gsg_hugepages` for more details. + +Debugging Options +----------------- + +.. _table_octeontx2_crypto_debug_options: + +.. table:: OCTEON TX2 crypto PMD debug options + + +---+------------+-------------------------------------------------------+ + | # | Component | EAL log command | + +===+============+=======================================================+ + | 1 | CPT | --log-level='pmd\.crypto\.octeontx2,8' | + +---+------------+-------------------------------------------------------+ + +Testing +------- + +The symmetric crypto operations on OCTEON TX2 crypto PMD may be verified by running the test +application: + +.. code-block:: console + + ./test + RTE>>cryptodev_octeontx2_autotest diff --git a/doc/guides/platform/octeontx2.rst b/doc/guides/platform/octeontx2.rst index 4194a43..f06dc68 100644 --- a/doc/guides/platform/octeontx2.rst +++ b/doc/guides/platform/octeontx2.rst @@ -132,6 +132,9 @@ This section lists dataplane H/W block(s) available in OCTEON TX2 SoC. #. **DMA Rawdev Driver** See :doc:`../rawdevs/octeontx2_dma` for DMA driver information. +#. **Crypto Device Driver** + See :doc:`../cryptodevs/octeontx2` for CPT crypto device driver information. + Procedure to Setup Platform ---------------------------