From patchwork Wed Aug 14 09:40:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 57679 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 110778F96; Wed, 14 Aug 2019 11:42:21 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 57687378B for ; Wed, 14 Aug 2019 11:42:19 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x7E9gIbL012751; Wed, 14 Aug 2019 02:42:18 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=Eq0Sh/8Vgya0nmr4ikaBL2XYY6m2Nbl4HuqyRSFnHsA=; b=JvcKUQZc7EWuT/8qkA4WNGiCMiiaiod6Zo7BBzvlYdzQAkpVschzVPqTmQdrI9n0DyEr pG3UXlC9v/in+wihQrRQBlgB0ej7JOUUbs17LQh1P0xaijtRtGiet8VEj0RmVUNmkeSx KF51gYI4/qqCYHTzkbY1XESLqsOzuzLCJLIrR/Ifiy2yyMGZILYy21Grlck35Zkh/Wq6 zDiRP1AKNL1YVTBz6gAvKtOC9qdFheBWY52u5nz8BiCUUdE7UhVPwLqhZI+6TKtVOI1z b6aSHAwWtXT05GwZ2GFySU0+UBaMfM3ycSBlY2zN3rPNEpZZkAR4Ix4au0bGr2pLLOLH GA== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0b-0016f401.pphosted.com with ESMTP id 2ubfabegcv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 14 Aug 2019 02:42:18 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Wed, 14 Aug 2019 02:42:16 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Wed, 14 Aug 2019 02:42:16 -0700 Received: from ajoseph83.caveonetworks.com.com (unknown [10.29.45.56]) by maili.marvell.com (Postfix) with ESMTP id 4136E3F704E; Wed, 14 Aug 2019 02:42:13 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Pablo de Lara CC: Ankur Dwivedi , Jerin Jacob , Narayana Prasad , , Anoob Joseph Date: Wed, 14 Aug 2019 15:10:31 +0530 Message-ID: <1565775631-20264-1-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:5.22.84,1.0.8 definitions=2019-08-14_03:2019-08-14,2019-08-14 signatures=0 Subject: [dpdk-dev] [PATCH] common/cpt: add support for new firmware X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ankur Dwivedi With the latest firmware, there are few changes for zuc and snow3g. 1. The iv_source is present in bitfield 7 of minor opcode. In the old firmware this was present in bitfield 6. 2. Algorithm type is a 2 bit field in new firmware. In the old firmware it was named as cipher type and it was a 1 bit field. Signed-off-by: Ankur Dwivedi Signed-off-by: Anoob Joseph --- drivers/common/cpt/cpt_mcode_defines.h | 4 ++-- drivers/common/cpt/cpt_ucode.h | 6 ++++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h index c0adbd5..b7c3feb 100644 --- a/drivers/common/cpt/cpt_mcode_defines.h +++ b/drivers/common/cpt/cpt_mcode_defines.h @@ -303,8 +303,8 @@ struct cpt_ctx { uint64_t hmac :1; uint64_t zsk_flags :3; uint64_t k_ecb :1; - uint64_t snow3g :1; - uint64_t rsvd :22; + uint64_t snow3g :2; + uint64_t rsvd :21; /* Below fields are accessed by hardware */ union { mc_fc_context_t fctx; diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h index 7d9c31e..0dac12e 100644 --- a/drivers/common/cpt/cpt_ucode.h +++ b/drivers/common/cpt/cpt_ucode.h @@ -1467,7 +1467,8 @@ cpt_zuc_snow3g_enc_prep(uint32_t req_flags, opcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G; /* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */ - opcode.s.minor = ((1 << 6) | (snow3g << 5) | (0 << 4) | + + opcode.s.minor = ((1 << 7) | (snow3g << 5) | (0 << 4) | (0 << 3) | (flags & 0x7)); if (flags == 0x1) { @@ -1791,7 +1792,8 @@ cpt_zuc_snow3g_dec_prep(uint32_t req_flags, opcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G; /* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */ - opcode.s.minor = ((1 << 6) | (snow3g << 5) | (0 << 4) | + + opcode.s.minor = ((1 << 7) | (snow3g << 5) | (0 << 4) | (0 << 3) | (flags & 0x7)); /* consider iv len */