From patchwork Wed Jul 31 14:37:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dekel Peled X-Patchwork-Id: 57325 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0C4DC1C06D; Wed, 31 Jul 2019 16:39:10 +0200 (CEST) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 84E271BF3F for ; Wed, 31 Jul 2019 16:39:08 +0200 (CEST) Received: from Internal Mail-Server by MTLPINE2 (envelope-from dekelp@mellanox.com) with ESMTPS (AES256-SHA encrypted); 31 Jul 2019 17:39:04 +0300 Received: from mtl-vdi-280.wap.labs.mlnx. (mtl-vdi-280.wap.labs.mlnx [10.128.130.87]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id x6VEd4nD009214; Wed, 31 Jul 2019 17:39:04 +0300 From: Dekel Peled To: yskoh@mellanox.com, viacheslavo@mellanox.com, shahafs@mellanox.com Cc: orika@mellanox.com, dev@dpdk.org, stable@dpdk.org Date: Wed, 31 Jul 2019 17:37:26 +0300 Message-Id: <3629a440b68b888ff45febdc1b8b111445904f48.1564583852.git.dekelp@mellanox.com> X-Mailer: git-send-email 1.7.1 Subject: [dpdk-dev] [PATCH] net/mlx5: fix limit on direct rules tables number X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" MLX5 PMD limits the number of SW steering tables to 32. This patch updates the limit to 65535, to allow wide range of values. Fixes: e2b4925ef7c1 ("net/mlx5: support Direct Rules E-Switch") Cc: stable@dpdk.org Signed-off-by: Dekel Peled --- drivers/net/mlx5/mlx5.h | 4 ++-- drivers/net/mlx5/mlx5_flow_dv.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index caf2491..f559f83 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -513,8 +513,8 @@ struct mlx5_flow_tbl_resource { rte_atomic32_t refcnt; /**< Reference counter. */ }; -#define MLX5_MAX_TABLES 1024 -#define MLX5_MAX_TABLES_FDB 32 +#define MLX5_MAX_TABLES 0xffff +#define MLX5_MAX_TABLES_FDB 0xffff #define MLX5_GROUP_FACTOR 1 #define MLX5_DBR_PAGE_SIZE 4096 /* Must be >= 512. */ diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 9c0a261..14e70ed 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -2817,7 +2817,7 @@ struct field_modify_info modify_tcp[] = { (error, EINVAL, RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, NULL, "group must be smaller than " - RTE_STR(MLX5_MAX_FDB_TABLES)); + RTE_STR(MLX5_MAX_TABLES_FDB)); } if (!(attributes->egress ^ attributes->ingress)) return rte_flow_error_set(error, ENOTSUP,