From patchwork Sat Jun 1 18:20:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerin Jacob Kollanukkaran X-Patchwork-Id: 54002 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 38A432F4F; Sat, 1 Jun 2019 20:20:24 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 296502F4F for ; Sat, 1 Jun 2019 20:20:23 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x51IKMvQ003601 for ; Sat, 1 Jun 2019 11:20:22 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=Izw2sFJHUQfyHxnCln2tXl1/BD78HYg1924M94+YNQA=; b=ARYyQP/ZjFJHPhjIVW8svfe67XdAP2aPAzrOd1MyjfzzRe2a5rRNimyYTw7Ob2RhenKw 5uI4p8AHOoSEzCxRQ6iK2V0LK7egYORhJ87Ey4pSHletGzMASgiJUFeQ5ibPZ0how+WX DWgPD828O1cCFzu0yxwSlvjKv76YgDayEJw+/Ute0SdjFegqXoxGO/rXrkE04OT+4iXF lHh2mOj918FsxPc81k+nmvp4oTeh9sCzFmvtaJ3xv2IwESCrViPLV2coddrymMZoCXu0 k4C/aOaCiJsxBdos5xQNiaSlYpqaOQOWfoJFcCbSmdPKdOPMaOx4/aFMK2Djs7/5EH5l hQ== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0b-0016f401.pphosted.com with ESMTP id 2survk1012-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 01 Jun 2019 11:20:22 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sat, 1 Jun 2019 11:20:20 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sat, 1 Jun 2019 11:20:20 -0700 Received: from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14]) by maili.marvell.com (Postfix) with ESMTP id 0B1E23F703F; Sat, 1 Jun 2019 11:20:19 -0700 (PDT) From: To: CC: , Vamsi Attunuru Date: Sat, 1 Jun 2019 23:50:22 +0530 Message-ID: <20190601182030.8282-2-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190601182030.8282-1-jerinj@marvell.com> References: <20190601182030.8282-1-jerinj@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-01_13:, , signatures=0 Subject: [dpdk-dev] [PATCH v1 1/9] raw/octeontx2_dma: add build infra and device probe X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Satha Rao Add the make and meson based build infrastructure along with the DMA device probe. Signed-off-by: Satha Rao Signed-off-by: Vamsi Attunuru --- config/common_base | 5 + drivers/raw/Makefile | 1 + drivers/raw/meson.build | 2 +- drivers/raw/octeontx2_dma/Makefile | 31 ++++++ drivers/raw/octeontx2_dma/meson.build | 18 ++++ drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c | 102 ++++++++++++++++++ .../rte_pmd_octeontx2_dma_version.map | 4 + mk/rte.app.mk | 1 + 8 files changed, 163 insertions(+), 1 deletion(-) create mode 100644 drivers/raw/octeontx2_dma/Makefile create mode 100644 drivers/raw/octeontx2_dma/meson.build create mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c create mode 100644 drivers/raw/octeontx2_dma/rte_pmd_octeontx2_dma_version.map diff --git a/config/common_base b/config/common_base index 4a3de0360..62e4cda01 100644 --- a/config/common_base +++ b/config/common_base @@ -741,6 +741,11 @@ CONFIG_RTE_LIBRTE_PMD_DPAA2_QDMA_RAWDEV=n # CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV=y +# +# Compile PMD for octeontx2 DMA device +# +CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV=y + # # Compile librte_ring # diff --git a/drivers/raw/Makefile b/drivers/raw/Makefile index 8e29b4a56..6af639ba2 100644 --- a/drivers/raw/Makefile +++ b/drivers/raw/Makefile @@ -10,5 +10,6 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_DPAA2_CMDIF_RAWDEV) += dpaa2_cmdif DIRS-$(CONFIG_RTE_LIBRTE_PMD_DPAA2_QDMA_RAWDEV) += dpaa2_qdma endif DIRS-$(CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV) += ifpga_rawdev +DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV) += octeontx2_dma include $(RTE_SDK)/mk/rte.subdir.mk diff --git a/drivers/raw/meson.build b/drivers/raw/meson.build index a61cdccef..00475d651 100644 --- a/drivers/raw/meson.build +++ b/drivers/raw/meson.build @@ -1,7 +1,7 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright 2018 NXP -drivers = ['skeleton_rawdev', 'dpaa2_cmdif', 'dpaa2_qdma', 'ifpga_rawdev'] +drivers = ['skeleton_rawdev', 'dpaa2_cmdif', 'dpaa2_qdma', 'ifpga_rawdev', 'octeontx2_dma'] std_deps = ['rawdev'] config_flag_fmt = 'RTE_LIBRTE_PMD_@0@_RAWDEV' driver_name_fmt = 'rte_pmd_@0@' diff --git a/drivers/raw/octeontx2_dma/Makefile b/drivers/raw/octeontx2_dma/Makefile new file mode 100644 index 000000000..7335d0ffa --- /dev/null +++ b/drivers/raw/octeontx2_dma/Makefile @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(C) 2019 Marvell International Ltd. +# + +include $(RTE_SDK)/mk/rte.vars.mk + +# library name +LIB = librte_pmd_octeontx2_dma.a + +CFLAGS += -DALLOW_EXPERIMENTAL_API -O3 $(WERROR_FLAGS) +CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2/ +CFLAGS += -I$(RTE_SDK)/drivers/mempool/octeontx2/ +CFLAGS += -I$(RTE_SDK)/drivers/raw/octeontx2_dma/ +LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring -lrte_rawdev +LDLIBS += -lrte_common_octeontx2 -lrte_kvargs -lrte_bus_pci + +ifneq ($(CONFIG_RTE_ARCH_64),y) +CFLAGS += -Wno-int-to-pointer-cast +CFLAGS += -Wno-pointer-to-int-cast +endif + +EXPORT_MAP := rte_pmd_octeontx2_dma_version.map + +LIBABIVER := 1 + +# +# all source are stored in SRCS-y +# +SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV) += otx2_dpi_rawdev.c + +include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/raw/octeontx2_dma/meson.build b/drivers/raw/octeontx2_dma/meson.build new file mode 100644 index 000000000..1281268aa --- /dev/null +++ b/drivers/raw/octeontx2_dma/meson.build @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(C) 2019 Marvell International Ltd. +# + +deps += ['rawdev', 'ring', 'kvargs', 'bus_pci', 'common_octeontx2', 'mempool_octeontx2'] +sources = files('otx2_dpi_rawdev.c') + +extra_flags = [] +# This integrated controller runs only on a arm64 machine, remove 32bit warnings +if not dpdk_conf.get('RTE_ARCH_64') + extra_flags += ['-Wno-int-to-pointer-cast', '-Wno-pointer-to-int-cast'] +endif + +foreach flag: extra_flags + if cc.has_argument(flag) + cflags += flag + endif +endforeach diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c new file mode 100644 index 000000000..01422c299 --- /dev/null +++ b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +static const struct rte_pci_id pci_dma_map[] = { + { + RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, + PCI_DEVID_OCTEONTX2_DPI_VF) + }, + { + .vendor_id = 0, + }, +}; + +static int +otx2_dpi_rawdev_probe(struct rte_pci_driver *pci_drv __rte_unused, + struct rte_pci_device *pci_dev) +{ + char name[RTE_RAWDEV_NAME_MAX_LEN]; + struct rte_rawdev *rawdev; + + /* For secondary processes, the primary has done all the work */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + if (pci_dev->mem_resource[0].addr == NULL) { + otx2_dpi_dbg("Empty bars %p %p", pci_dev->mem_resource[0].addr, + pci_dev->mem_resource[2].addr); + return -ENODEV; + } + + memset(name, 0, sizeof(name)); + snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "DPI:%x:%02x.%x", + pci_dev->addr.bus, pci_dev->addr.devid, + pci_dev->addr.function); + + /* Allocate device structure */ + rawdev = rte_rawdev_pmd_allocate(name, 0, rte_socket_id()); + if (rawdev == NULL) { + otx2_err("Rawdev allocation failed"); + return -EINVAL; + } + + rawdev->device = &pci_dev->device; + rawdev->driver_name = pci_dev->driver->driver.name; + + return 0; +} + +static int +otx2_dpi_rawdev_remove(struct rte_pci_device *pci_dev) +{ + char name[RTE_RAWDEV_NAME_MAX_LEN]; + struct rte_rawdev *rawdev; + + if (pci_dev == NULL) { + otx2_dpi_dbg("Invalid pci_dev of the device!"); + return -EINVAL; + } + + memset(name, 0, sizeof(name)); + snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "DPI:%x:%02x.%x", + pci_dev->addr.bus, pci_dev->addr.devid, + pci_dev->addr.function); + + rawdev = rte_rawdev_pmd_get_named_dev(name); + if (rawdev == NULL) { + otx2_dpi_dbg("Invalid device name (%s)", name); + return -EINVAL; + } + + /* rte_rawdev_close is called by pmd_release */ + return rte_rawdev_pmd_release(rawdev); +} + +static struct rte_pci_driver rte_dpi_rawdev_pmd = { + .id_table = pci_dma_map, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA, + .probe = otx2_dpi_rawdev_probe, + .remove = otx2_dpi_rawdev_remove, +}; + +RTE_PMD_REGISTER_PCI(dpi_rawdev_pci_driver, rte_dpi_rawdev_pmd); +RTE_PMD_REGISTER_PCI_TABLE(dpi_rawdev_pci_driver, pci_dma_map); +RTE_PMD_REGISTER_KMOD_DEP(dpi_rawdev_pci_driver, "vfio-pci"); diff --git a/drivers/raw/octeontx2_dma/rte_pmd_octeontx2_dma_version.map b/drivers/raw/octeontx2_dma/rte_pmd_octeontx2_dma_version.map new file mode 100644 index 000000000..fc8c95e91 --- /dev/null +++ b/drivers/raw/octeontx2_dma/rte_pmd_octeontx2_dma_version.map @@ -0,0 +1,4 @@ +DPDK_19.05 { + + local: *; +}; diff --git a/mk/rte.app.mk b/mk/rte.app.mk index cd89ccfd5..152bd8b14 100644 --- a/mk/rte.app.mk +++ b/mk/rte.app.mk @@ -309,6 +309,7 @@ ifeq ($(CONFIG_RTE_LIBRTE_IFPGA_BUS),y) _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV) += -lrte_pmd_ifpga_rawdev _LDLIBS-$(CONFIG_RTE_LIBRTE_IPN3KE_PMD) += -lrte_pmd_ipn3ke endif # CONFIG_RTE_LIBRTE_IFPGA_BUS +_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV) += -lrte_pmd_octeontx2_dma endif # CONFIG_RTE_LIBRTE_RAWDEV endif # !CONFIG_RTE_BUILD_SHARED_LIBS From patchwork Sat Jun 1 18:20:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerin Jacob Kollanukkaran X-Patchwork-Id: 54003 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E48D04F91; Sat, 1 Jun 2019 20:20:27 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id E2CF31C0B for ; Sat, 1 Jun 2019 20:20:26 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x51IKQiZ003606 for ; Sat, 1 Jun 2019 11:20:26 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=Ul+Uv8k5AB9KKJQhrw1XJlPjU1ZP5Bidwpd5jt1De90=; b=WOcGPMKEMrlbSXcpATZEC6fPnZhUcGn8q3KmJMUuQLb7HhDo1Jhc1eNS9T38kRADsyEW 6ThdJTvV5qW/b65/GkyMYECGA/jQf8ZwtPFsjF2S/duJ2v3M5Bt5NpnF5PIMvnHj6pNa 3P6unN4i3THjPP6/ocmL2GodbExjDPz+lmeTqfaFiwV87IataVMX1QwJTi9+/J2s05mT V4X2NQBnYOj2ZSI66OFUqS2rhcWOU+ihlw1gnk5eSIL/QisoIoIvuwadfWYM+EgBwOGD 1hGcQAB7TboQk2EIGeF/HKNVYJ+5amlkL8e5y9HD9XvvYn7K55ur01PyusDp/AVsSive 0g== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0b-0016f401.pphosted.com with ESMTP id 2survk1016-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 01 Jun 2019 11:20:26 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sat, 1 Jun 2019 11:20:25 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sat, 1 Jun 2019 11:20:25 -0700 Received: from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14]) by maili.marvell.com (Postfix) with ESMTP id 1CB353F703F; Sat, 1 Jun 2019 11:20:23 -0700 (PDT) From: To: CC: , Vamsi Attunuru Date: Sat, 1 Jun 2019 23:50:23 +0530 Message-ID: <20190601182030.8282-3-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190601182030.8282-1-jerinj@marvell.com> References: <20190601182030.8282-1-jerinj@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-01_13:, , signatures=0 Subject: [dpdk-dev] [PATCH v1 2/9] raw/octeontx2_dma: update probe function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Satha Rao Probe function enhanced to allocate and initialise PMD private data. Signed-off-by: Satha Rao Signed-off-by: Vamsi Attunuru --- drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c | 25 +++++++-- drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h | 59 +++++++++++++++++++++ 2 files changed, 80 insertions(+), 4 deletions(-) create mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c index 01422c299..f9560abcc 100644 --- a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c +++ b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c @@ -17,7 +17,7 @@ #include #include -#include +#include "otx2_dpi_rawdev.h" static const struct rte_pci_id pci_dma_map[] = { { @@ -34,11 +34,13 @@ otx2_dpi_rawdev_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_device *pci_dev) { char name[RTE_RAWDEV_NAME_MAX_LEN]; + struct dpi_vf_s *dpivf = NULL; struct rte_rawdev *rawdev; + uint16_t vf_id; /* For secondary processes, the primary has done all the work */ if (rte_eal_process_type() != RTE_PROC_PRIMARY) - return 0; + return DPI_DMA_QUEUE_SUCCESS; if (pci_dev->mem_resource[0].addr == NULL) { otx2_dpi_dbg("Empty bars %p %p", pci_dev->mem_resource[0].addr, @@ -52,7 +54,8 @@ otx2_dpi_rawdev_probe(struct rte_pci_driver *pci_drv __rte_unused, pci_dev->addr.function); /* Allocate device structure */ - rawdev = rte_rawdev_pmd_allocate(name, 0, rte_socket_id()); + rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct dpi_vf_s), + rte_socket_id()); if (rawdev == NULL) { otx2_err("Rawdev allocation failed"); return -EINVAL; @@ -61,7 +64,21 @@ otx2_dpi_rawdev_probe(struct rte_pci_driver *pci_drv __rte_unused, rawdev->device = &pci_dev->device; rawdev->driver_name = pci_dev->driver->driver.name; - return 0; + dpivf = rawdev->dev_private; + if (dpivf->state != DPI_QUEUE_STOP) { + otx2_dpi_dbg("Device already started!!!"); + return -ENODEV; + } + + vf_id = ((pci_dev->addr.devid & 0x1F) << 3) | + (pci_dev->addr.function & 0x7); + vf_id -= 1; + dpivf->state = DPI_QUEUE_START; + dpivf->vf_id = vf_id; + dpivf->vf_bar0 = (uintptr_t)pci_dev->mem_resource[0].addr; + dpivf->vf_bar2 = (uintptr_t)pci_dev->mem_resource[2].addr; + + return DPI_DMA_QUEUE_SUCCESS; } static int diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h new file mode 100644 index 000000000..33fd95c33 --- /dev/null +++ b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#ifndef _DPI_RAWDEV_H_ +#define _DPI_RAWDEV_H_ + +#include "otx2_common.h" +#include "otx2_mempool.h" + +#define DPI_QUEUE_OPEN 0x1 +#define DPI_QUEUE_CLOSE 0x2 + +/* DPI VF register offsets from VF_BAR0 */ +#define DPI_VDMA_EN (0x0) +#define DPI_VDMA_REQQ_CTL (0x8) +#define DPI_VDMA_DBELL (0x10) +#define DPI_VDMA_SADDR (0x18) +#define DPI_VDMA_COUNTS (0x20) +#define DPI_VDMA_NADDR (0x28) +#define DPI_VDMA_IWBUSY (0x30) +#define DPI_VDMA_CNT (0x38) +#define DPI_VF_INT (0x100) +#define DPI_VF_INT_W1S (0x108) +#define DPI_VF_INT_ENA_W1C (0x110) +#define DPI_VF_INT_ENA_W1S (0x118) + +#define DPI_MAX_VFS 8 +#define DPI_DMA_CMD_SIZE 64 +#define DPI_CHUNK_SIZE 1024 +#define DPI_QUEUE_STOP 0x0 +#define DPI_QUEUE_START 0x1 + +struct dpi_vf_s { + struct rte_pci_device *dev; + uint8_t state; + uint16_t vf_id; + uint8_t domain; + uintptr_t vf_bar0; + uintptr_t vf_bar2; + + uint16_t pool_size_m1; + uint16_t index; + uint64_t *base_ptr; + void *chunk_pool; + struct otx2_mbox *mbox; +}; + +struct dpi_rawdev_conf_s { + void *chunk_pool; +}; + +enum dpi_dma_queue_result_e { + DPI_DMA_QUEUE_SUCCESS = 0, + DPI_DMA_QUEUE_NO_MEMORY = -1, + DPI_DMA_QUEUE_INVALID_PARAM = -2, +}; + +#endif /* _DPI_RAWDEV_H_ */ From patchwork Sat Jun 1 18:20:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerin Jacob Kollanukkaran X-Patchwork-Id: 54004 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 490D91B955; Sat, 1 Jun 2019 20:20:31 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id EB1EB1B953 for ; Sat, 1 Jun 2019 20:20:29 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x51IKMvT003601 for ; Sat, 1 Jun 2019 11:20:29 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=uy1DtzbgOlskFQmJ6wG83dN4hhvE5znbkIfEbz6hij0=; b=xRFE/EoJKERAAk+9eo1A3GPQ7icxAtBM13sPIQG2mm218bo2AAyjDBXzpVZPqlyV8Rok g2Zn64Tg5Nza1zpiW7hZyAr/kVJX3qwhxq0sD12uTd+kobnKvsuNhcoklW6mFhITZpdJ GAYUVX18Rw8DaSd2vj846kQqp6FyHxPP6B9c5NqIMkgsBh4fAdUV8ecZRCvX0kjdJevv DeDZKOlJrYs+LTJGpAyR1fpNdE/uAXSNpgiytNlvNhb21QXQWrDZwRjwGPyXuUxisfVi aYfcRngrNGlDGTb4pWDHiHUUSf/S6MdnokVT3IpTjhty83UDy4JXxH5ybYcIg2G0RIHe Gg== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0b-0016f401.pphosted.com with ESMTP id 2survk1019-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 01 Jun 2019 11:20:29 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sat, 1 Jun 2019 11:20:27 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sat, 1 Jun 2019 11:20:27 -0700 Received: from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14]) by maili.marvell.com (Postfix) with ESMTP id C28103F7041; Sat, 1 Jun 2019 11:20:26 -0700 (PDT) From: To: CC: , Vamsi Attunuru Date: Sat, 1 Jun 2019 23:50:24 +0530 Message-ID: <20190601182030.8282-4-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190601182030.8282-1-jerinj@marvell.com> References: <20190601182030.8282-1-jerinj@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-01_13:, , signatures=0 Subject: [dpdk-dev] [PATCH v1 3/9] raw/octeontx2_dma: add device configuration X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Satha Rao Register dev_configure API to configure DPI PCI devices. After successful initialisation send message to PF to open corresponding DPI DMA queue. At present hardware doesn't support mail box for DPI, so PMD to PF communication uses prebuild kernel devfs. Signed-off-by: Satha Rao Signed-off-by: Vamsi Attunuru --- drivers/raw/octeontx2_dma/Makefile | 5 +- drivers/raw/octeontx2_dma/meson.build | 2 +- drivers/raw/octeontx2_dma/otx2_dpi_msg.c | 105 ++++++++++++++++++++ drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c | 54 ++++++++++ drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h | 3 + 5 files changed, 165 insertions(+), 4 deletions(-) create mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_msg.c diff --git a/drivers/raw/octeontx2_dma/Makefile b/drivers/raw/octeontx2_dma/Makefile index 7335d0ffa..6a9a380b1 100644 --- a/drivers/raw/octeontx2_dma/Makefile +++ b/drivers/raw/octeontx2_dma/Makefile @@ -7,10 +7,9 @@ include $(RTE_SDK)/mk/rte.vars.mk # library name LIB = librte_pmd_octeontx2_dma.a -CFLAGS += -DALLOW_EXPERIMENTAL_API -O3 $(WERROR_FLAGS) +CFLAGS += -O3 $(WERROR_FLAGS) CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2/ CFLAGS += -I$(RTE_SDK)/drivers/mempool/octeontx2/ -CFLAGS += -I$(RTE_SDK)/drivers/raw/octeontx2_dma/ LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring -lrte_rawdev LDLIBS += -lrte_common_octeontx2 -lrte_kvargs -lrte_bus_pci @@ -26,6 +25,6 @@ LIBABIVER := 1 # # all source are stored in SRCS-y # -SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV) += otx2_dpi_rawdev.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV) += otx2_dpi_rawdev.c otx2_dpi_msg.c include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/raw/octeontx2_dma/meson.build b/drivers/raw/octeontx2_dma/meson.build index 1281268aa..751d099d2 100644 --- a/drivers/raw/octeontx2_dma/meson.build +++ b/drivers/raw/octeontx2_dma/meson.build @@ -3,7 +3,7 @@ # deps += ['rawdev', 'ring', 'kvargs', 'bus_pci', 'common_octeontx2', 'mempool_octeontx2'] -sources = files('otx2_dpi_rawdev.c') +sources = files('otx2_dpi_rawdev.c', 'otx2_dpi_msg.c') extra_flags = [] # This integrated controller runs only on a arm64 machine, remove 32bit warnings diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_msg.c b/drivers/raw/octeontx2_dma/otx2_dpi_msg.c new file mode 100644 index 000000000..aa361cb8a --- /dev/null +++ b/drivers/raw/octeontx2_dma/otx2_dpi_msg.c @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#ifndef _DPI_MSG_H_ +#define _DPI_MSG_H_ + +#include +#include +#include +#include + +#include "otx2_dpi_rawdev.h" + +/* DPI PF DBDF information macro's */ +#define DPI_PF_DBDF_DOMAIN 0 +#define DPI_PF_DBDF_BUS 5 +#define DPI_PF_DBDF_DEVICE 0 +#define DPI_PF_DBDF_FUNCTION 0 + +#define DPI_PF_MBOX_SYSFS_ENTRY "dpi_device_config" + +union dpi_mbox_message_u { + uint64_t u[2]; + struct dpi_mbox_message_s { + /* VF ID to configure */ + uint64_t vfid :4; + /* Command code */ + uint64_t cmd :4; + /* Command buffer size in 8-byte words */ + uint64_t csize :14; + /* aura of the command buffer */ + uint64_t aura :20; + /* SSO PF function */ + uint64_t sso_pf_func :16; + /* NPA PF function */ + uint64_t npa_pf_func :16; + } s; +}; + +static inline int +send_msg_to_pf(const char *value, int size) +{ + char buff[255] = { 0 }; + int res, fd; + + res = snprintf(buff, sizeof(buff), "%s/" PCI_PRI_FMT "/%s", + rte_pci_get_sysfs_path(), DPI_PF_DBDF_DOMAIN, + DPI_PF_DBDF_BUS, DPI_PF_DBDF_DEVICE & 0x7, + DPI_PF_DBDF_FUNCTION & 0x7, DPI_PF_MBOX_SYSFS_ENTRY); + if ((res < 0) || ((size_t)res > sizeof(buff))) + return -ERANGE; + + fd = open(buff, O_WRONLY); + if (fd < 0) + return -EACCES; + res = write(fd, value, size); + close(fd); + if (res < 0) + return -EACCES; + + return 0; +} + +int +otx2_dpi_queue_open(uint16_t vf_id, uint32_t size, uint32_t gaura) +{ + union dpi_mbox_message_u mbox_msg; + int ret = 0; + + /* DPI PF driver expects vfid starts from index 0 */ + mbox_msg.s.vfid = vf_id; + mbox_msg.s.cmd = DPI_QUEUE_OPEN; + mbox_msg.s.csize = size; + mbox_msg.s.aura = gaura; + mbox_msg.s.sso_pf_func = otx2_sso_pf_func_get(); + mbox_msg.s.npa_pf_func = otx2_npa_pf_func_get(); + + ret = send_msg_to_pf((const char *)&mbox_msg, + sizeof(mbox_msg)); + if (ret < 0) + otx2_dpi_dbg("Failed to send mbox message to dpi pf"); + + return ret; +} + +int +otx2_dpi_queue_close(uint16_t vf_id) +{ + union dpi_mbox_message_u mbox_msg; + int ret = 0; + + /* DPI PF driver expects vfid starts from index 0 */ + mbox_msg.s.vfid = vf_id; + mbox_msg.s.cmd = DPI_QUEUE_CLOSE; + + ret = send_msg_to_pf((const char *)&mbox_msg, + sizeof(mbox_msg)); + if (ret < 0) + otx2_dpi_dbg("Failed to send mbox message to dpi pf"); + + return ret; +} + +#endif /* _DPI_MSG_H_ */ diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c index f9560abcc..b418dc5bb 100644 --- a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c +++ b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c @@ -29,6 +29,59 @@ static const struct rte_pci_id pci_dma_map[] = { }, }; +/* Enable/Disable DMA queue */ +static inline int +dma_engine_enb_dis(struct dpi_vf_s *dpivf, const bool enb) +{ + if (enb) + otx2_write64(0x1, dpivf->vf_bar0 + DPI_VDMA_EN); + else + otx2_write64(0x0, dpivf->vf_bar0 + DPI_VDMA_EN); + + return DPI_DMA_QUEUE_SUCCESS; +} + +static int +otx2_dpi_rawdev_configure(const struct rte_rawdev *dev, rte_rawdev_obj_t config) +{ + struct dpi_rawdev_conf_s *conf = config; + struct dpi_vf_s *dpivf = NULL; + void *buf = NULL; + uintptr_t pool; + uint32_t gaura; + + if (conf == NULL) { + otx2_dpi_dbg("NULL configuration"); + return -EINVAL; + } + dpivf = (struct dpi_vf_s *)dev->dev_private; + dpivf->chunk_pool = conf->chunk_pool; + if (rte_mempool_get(conf->chunk_pool, &buf) || (buf == NULL)) { + otx2_err("Unable allocate buffer"); + return -ENODEV; + } + dpivf->base_ptr = buf; + otx2_write64(0x0, dpivf->vf_bar0 + DPI_VDMA_EN); + dpivf->pool_size_m1 = (DPI_CHUNK_SIZE >> 3) - 2; + pool = (uintptr_t)((struct rte_mempool *)conf->chunk_pool)->pool_id; + gaura = npa_lf_aura_handle_to_aura(pool); + otx2_write64(0, dpivf->vf_bar0 + DPI_VDMA_REQQ_CTL); + otx2_write64(((uint64_t)buf >> 7) << 7, + dpivf->vf_bar0 + DPI_VDMA_SADDR); + if (otx2_dpi_queue_open(dpivf->vf_id, DPI_CHUNK_SIZE, gaura) < 0) { + otx2_err("Unable to open DPI VF %d", dpivf->vf_id); + rte_mempool_put(conf->chunk_pool, buf); + return -EACCES; + } + dma_engine_enb_dis(dpivf, true); + + return DPI_DMA_QUEUE_SUCCESS; +} + +static const struct rte_rawdev_ops dpi_rawdev_ops = { + .dev_configure = otx2_dpi_rawdev_configure, +}; + static int otx2_dpi_rawdev_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_device *pci_dev) @@ -61,6 +114,7 @@ otx2_dpi_rawdev_probe(struct rte_pci_driver *pci_drv __rte_unused, return -EINVAL; } + rawdev->dev_ops = &dpi_rawdev_ops; rawdev->device = &pci_dev->device; rawdev->driver_name = pci_dev->driver->driver.name; diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h index 33fd95c33..918ae725a 100644 --- a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h +++ b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h @@ -56,4 +56,7 @@ enum dpi_dma_queue_result_e { DPI_DMA_QUEUE_INVALID_PARAM = -2, }; +int otx2_dpi_queue_open(uint16_t vf_id, uint32_t size, uint32_t gaura); +int otx2_dpi_queue_close(uint16_t vf_id); + #endif /* _DPI_RAWDEV_H_ */ From patchwork Sat Jun 1 18:20:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerin Jacob Kollanukkaran X-Patchwork-Id: 54005 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id DCB431B95A; Sat, 1 Jun 2019 20:20:33 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 0A12E1B959 for ; Sat, 1 Jun 2019 20:20:31 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x51IKArr002841 for ; Sat, 1 Jun 2019 11:20:31 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=cN56tGQqZtqSBiHwB67xRDl0akepeHjywvwnxrdluTs=; b=rjBfivYleqoyHsFKYj3irNolSW5Z7FWTbMwjafm12MFUx6ExCae6Oj43D5lpK53K2P09 K1LlDfKTUW7H166S6ekqUa5uFzgpx3DoA+xvSDIbqQqHJiETKU1w4Mi4L0wZaIVcYB5e 86+AkxBTtXDe69yiSmBHpy855qtQNj6Y07dDn1iEtJ1gXWh+1zrAQIvA3YJZRslXxQjI kJbh66mCTAS8fzITDXEfEVSbpaKZmcrlQDcXysVtN2wwDTR2G77ZfZnbCuOL17558/Qt aCpd1TMbrka8yU7YjGgRG0S46hFQ1f6Ng8J5NpHFqcWih9KtquvrKtxjqOS1CjKlNSeQ kg== Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0a-0016f401.pphosted.com with ESMTP id 2supqksde6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 01 Jun 2019 11:20:31 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sat, 1 Jun 2019 11:20:30 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sat, 1 Jun 2019 11:20:30 -0700 Received: from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14]) by maili.marvell.com (Postfix) with ESMTP id 6EB8D3F703F; Sat, 1 Jun 2019 11:20:29 -0700 (PDT) From: To: CC: , Vamsi Attunuru Date: Sat, 1 Jun 2019 23:50:25 +0530 Message-ID: <20190601182030.8282-5-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190601182030.8282-1-jerinj@marvell.com> References: <20190601182030.8282-1-jerinj@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-01_13:, , signatures=0 Subject: [dpdk-dev] [PATCH v1 4/9] raw/octeontx2_dma: add device close operation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Satha Rao Send message to PF to stop DMA queue when device close is called from application. Defined the required data structures to support enqueue and dequeue APIs. Signed-off-by: Satha Rao Signed-off-by: Vamsi Attunuru --- drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c | 33 +++++ drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h | 133 ++++++++++++++++++++ 2 files changed, 166 insertions(+) diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c index b418dc5bb..e7e30825f 100644 --- a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c +++ b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c @@ -41,6 +41,34 @@ dma_engine_enb_dis(struct dpi_vf_s *dpivf, const bool enb) return DPI_DMA_QUEUE_SUCCESS; } +/* Free DMA Queue instruction buffers, and send close notification to PF */ +static inline int +dma_queue_finish(struct dpi_vf_s *dpivf) +{ + uint32_t timeout = 0, sleep = 1; + uint64_t reg = 0ULL; + + /* Wait for SADDR to become idle */ + reg = otx2_read64(dpivf->vf_bar0 + DPI_VDMA_SADDR); + while (!(reg & BIT_ULL(DPI_VDMA_SADDR_REQ_IDLE))) { + rte_delay_ms(sleep); + timeout++; + if (timeout >= DPI_QFINISH_TIMEOUT) { + otx2_dpi_dbg("Timeout!!! Closing Forcibly"); + break; + } + reg = otx2_read64(dpivf->vf_bar0 + DPI_VDMA_SADDR); + } + + if (otx2_dpi_queue_close(dpivf->vf_id) < 0) + return -EACCES; + + rte_mempool_put(dpivf->chunk_pool, dpivf->base_ptr); + dpivf->vf_bar0 = (uintptr_t)NULL; + + return DPI_DMA_QUEUE_SUCCESS; +} + static int otx2_dpi_rawdev_configure(const struct rte_rawdev *dev, rte_rawdev_obj_t config) { @@ -140,6 +168,7 @@ otx2_dpi_rawdev_remove(struct rte_pci_device *pci_dev) { char name[RTE_RAWDEV_NAME_MAX_LEN]; struct rte_rawdev *rawdev; + struct dpi_vf_s *dpivf; if (pci_dev == NULL) { otx2_dpi_dbg("Invalid pci_dev of the device!"); @@ -157,6 +186,10 @@ otx2_dpi_rawdev_remove(struct rte_pci_device *pci_dev) return -EINVAL; } + dpivf = (struct dpi_vf_s *)rawdev->dev_private; + dma_engine_enb_dis(dpivf, false); + dma_queue_finish(dpivf); + /* rte_rawdev_close is called by pmd_release */ return rte_rawdev_pmd_release(rawdev); } diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h index 918ae725a..f59bab97f 100644 --- a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h +++ b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h @@ -31,6 +31,32 @@ #define DPI_QUEUE_STOP 0x0 #define DPI_QUEUE_START 0x1 +#define DPI_VDMA_SADDR_REQ_IDLE 63 +#define DPI_MAX_POINTER 15 +#define STRM_INC(s) ((s)->tail = ((s)->tail + 1) % (s)->max_cnt) +#define DPI_QFINISH_TIMEOUT (10 * 1000) + +/* DPI Transfer Type, pointer type in DPI_DMA_INSTR_HDR_S[XTYPE] */ +#define DPI_XTYPE_OUTBOUND (0) +#define DPI_XTYPE_INBOUND (1) +#define DPI_XTYPE_INTERNAL_ONLY (2) +#define DPI_XTYPE_EXTERNAL_ONLY (3) +#define DPI_XTYPE_MASK 0x3 +#define DPI_HDR_PT_ZBW_CA 0x0 +#define DPI_HDR_PT_ZBW_NC 0x1 +#define DPI_HDR_PT_WQP 0x2 +#define DPI_HDR_PT_WQP_NOSTATUS 0x0 +#define DPI_HDR_PT_WQP_STATUSCA 0x1 +#define DPI_HDR_PT_WQP_STATUSNC 0x3 +#define DPI_HDR_PT_CNT 0x3 +#define DPI_HDR_PT_MASK 0x3 +#define DPI_W0_TT_MASK 0x3 +#define DPI_W0_GRP_MASK 0x3FF +/* Set Completion data to 0xFF when request submitted, + * upon successful request completion engine reset to completion status + */ +#define DPI_REQ_CDATA 0xFF + struct dpi_vf_s { struct rte_pci_device *dev; uint8_t state; @@ -56,6 +82,113 @@ enum dpi_dma_queue_result_e { DPI_DMA_QUEUE_INVALID_PARAM = -2, }; +struct dpi_dma_req_compl_s { + uint64_t cdata; + void (*compl_cb)(void *dev, void *arg); + void *cb_data; +}; + +union dpi_dma_ptr_u { + uint64_t u[2]; + struct dpi_dma_s { + uint64_t length:16; + uint64_t reserved:44; + uint64_t bed:1; /* Big-Endian */ + uint64_t alloc_l2:1; + uint64_t full_write:1; + uint64_t invert:1; + uint64_t ptr; + } s; +}; + +struct dpi_dma_buf_ptr_s { + union dpi_dma_ptr_u *rptr[DPI_MAX_POINTER]; /* Read From pointer list */ + union dpi_dma_ptr_u *wptr[DPI_MAX_POINTER]; /* Write to pointer list */ + uint8_t rptr_cnt; + uint8_t wptr_cnt; + struct dpi_dma_req_compl_s *comp_ptr; +}; + +struct dpi_cring_data_s { + struct dpi_dma_req_compl_s **compl_data; + uint16_t max_cnt; + uint16_t head; + uint16_t tail; +}; + +struct dpi_dma_queue_ctx_s { + uint16_t xtype:2; + + /* Completion pointer type */ + uint16_t pt:2; + + /* Completion updated using WQE */ + uint16_t tt:2; + uint16_t grp:10; + uint32_t tag; + + /* Valid only for Outbound only mode */ + uint16_t aura:12; + uint16_t csel:1; + uint16_t ca:1; + uint16_t fi:1; + uint16_t ii:1; + uint16_t fl:1; + + uint16_t pvfe:1; + uint16_t dealloce:1; + uint16_t req_type:2; + uint16_t use_lock:1; + uint16_t deallocv; + + struct dpi_cring_data_s *c_ring; +}; + +/* DPI DMA Instruction Header Format */ +union dpi_dma_instr_hdr_u { + uint64_t u[4]; + + struct dpi_dma_instr_hdr_s_s { + uint64_t tag:32; + uint64_t tt:2; + uint64_t grp:10; + uint64_t reserved_44_47:4; + uint64_t nfst:4; + uint64_t reserved_52_53:2; + uint64_t nlst:4; + uint64_t reserved_58_63:6; + /* Word 0 - End */ + + uint64_t aura:12; + uint64_t reserved_76_79:4; + uint64_t deallocv:16; + uint64_t dealloce:1; + uint64_t pvfe:1; + uint64_t reserved_98_99:2; + uint64_t pt:2; + uint64_t reserved_102_103:2; + uint64_t fl:1; + uint64_t ii:1; + uint64_t fi:1; + uint64_t ca:1; + uint64_t csel:1; + uint64_t reserved_109_111:3; + uint64_t xtype:2; + uint64_t reserved_114_119:6; + uint64_t fport:2; + uint64_t reserved_122_123:2; + uint64_t lport:2; + uint64_t reserved_126_127:2; + /* Word 1 - End */ + + uint64_t ptr:64; + /* Word 2 - End */ + + uint64_t reserved_192_255:64; + /* Word 3 - End */ + } s; +}; + int otx2_dpi_queue_open(uint16_t vf_id, uint32_t size, uint32_t gaura); int otx2_dpi_queue_close(uint16_t vf_id); From patchwork Sat Jun 1 18:20:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerin Jacob Kollanukkaran X-Patchwork-Id: 54006 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A7E991B964; Sat, 1 Jun 2019 20:20:36 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 1F8051B958 for ; Sat, 1 Jun 2019 20:20:35 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x51IK66m003558 for ; Sat, 1 Jun 2019 11:20:34 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=a2heIUAgyChiRNCoy/jtyFAmErq0NVQBt174ZNjyFnk=; b=It1zEGVqn1FOL0XaKsTaujtCqJl6ZKJNixNYzeMpj3kWjbfoFYbW93g0yf7KESQx006b hAaoYIw8vWl1WjswRAnQ5CSyjf1H0HYe0qrV7yfPb6QRqaRUjnTGNGXcdNd0NjXW/HqD +vRYbfjYMDA6DoyIxCs4v5T7RGKBUs8qQnK7rOBURuVvNmCHkEv8UE+Qav5N78MZDZZq CftxQ1pxqKcDGKnmoG0mWbU2ZljBW5OauXCy8Z9gjlwNgdQ8uHx++GEJm+KGYjMjj04T YMP1JzkhMBX0YRdpVGAcX3rC7SOeq4fewVPXKFKj9wMrSgAEwe2vq1Rw88csNgc3p5XX gw== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0b-0016f401.pphosted.com with ESMTP id 2survk101d-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 01 Jun 2019 11:20:34 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sat, 1 Jun 2019 11:20:33 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sat, 1 Jun 2019 11:20:33 -0700 Received: from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14]) by maili.marvell.com (Postfix) with ESMTP id 1E6813F703F; Sat, 1 Jun 2019 11:20:31 -0700 (PDT) From: To: CC: , Vamsi Attunuru Date: Sat, 1 Jun 2019 23:50:26 +0530 Message-ID: <20190601182030.8282-6-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190601182030.8282-1-jerinj@marvell.com> References: <20190601182030.8282-1-jerinj@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-01_13:, , signatures=0 Subject: [dpdk-dev] [PATCH v1 5/9] raw/octeontx2_dma: add enqueue operation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Satha Rao Add enqueue operation. Signed-off-by: Satha Rao Signed-off-by: Vamsi Attunuru --- drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c | 166 ++++++++++++++++++++ 1 file changed, 166 insertions(+) diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c index e7e30825f..bfc95657b 100644 --- a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c +++ b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c @@ -69,6 +69,171 @@ dma_queue_finish(struct dpi_vf_s *dpivf) return DPI_DMA_QUEUE_SUCCESS; } +/* Write an arbitrary number of command words to a command queue */ +static __rte_always_inline enum dpi_dma_queue_result_e +dma_queue_write(struct dpi_vf_s *dpi, uint16_t cmd_count, uint64_t *cmds) +{ + if ((cmd_count < 1) || (cmd_count > 64)) + return DPI_DMA_QUEUE_INVALID_PARAM; + + if (cmds == NULL) + return DPI_DMA_QUEUE_INVALID_PARAM; + + /* Room available in the current buffer for the command */ + if (dpi->index + cmd_count < dpi->pool_size_m1) { + uint64_t *ptr = dpi->base_ptr; + + ptr += dpi->index; + dpi->index += cmd_count; + while (cmd_count--) + *ptr++ = *cmds++; + } else { + void *new_buffer; + uint64_t *ptr; + int count; + + /* Allocate new command buffer, return if failed */ + if (rte_mempool_get(dpi->chunk_pool, &new_buffer) || + new_buffer == NULL) { + return DPI_DMA_QUEUE_NO_MEMORY; + } + ptr = dpi->base_ptr; + /* Figure out how many command words will fit in this buffer. + * One location will be needed for the next buffer pointer. + **/ + count = dpi->pool_size_m1 - dpi->index; + ptr += dpi->index; + cmd_count -= count; + while (count--) + *ptr++ = *cmds++; + /* Chunk next ptr is 2DWORDs, second DWORD is reserved. */ + *ptr++ = (uint64_t)new_buffer; + *ptr = 0; + /* The current buffer is full and has a link to the next buffer. + * Time to write the rest of the commands into the new buffer. + **/ + dpi->base_ptr = new_buffer; + dpi->index = cmd_count; + ptr = new_buffer; + while (cmd_count--) + *ptr++ = *cmds++; + /* queue index may greater than pool size */ + if (dpi->index >= dpi->pool_size_m1) { + if (rte_mempool_get(dpi->chunk_pool, &new_buffer) || + new_buffer == NULL) { + return DPI_DMA_QUEUE_NO_MEMORY; + } + /* Write next buffer address */ + *ptr = (uint64_t)new_buffer; + dpi->base_ptr = new_buffer; + dpi->index = 0; + } + } + return DPI_DMA_QUEUE_SUCCESS; +} + +/* Submit a DMA command to the DMA queues. */ +static __rte_always_inline int +dma_queue_submit(struct rte_rawdev *dev, uint16_t cmd_count, uint64_t *cmds) +{ + struct dpi_vf_s *dpivf = dev->dev_private; + enum dpi_dma_queue_result_e result; + + result = dma_queue_write(dpivf, cmd_count, cmds); + rte_wmb(); + if (likely(result == DPI_DMA_QUEUE_SUCCESS)) + otx2_write64((uint64_t)cmd_count, + dpivf->vf_bar0 + DPI_VDMA_DBELL); + + return result; +} + +/* Enqueue buffers to DMA queue + * returns number of buffers enqueued successfully + */ +static int +otx2_dpi_rawdev_enqueue_bufs(struct rte_rawdev *dev, + struct rte_rawdev_buf **buffers, + unsigned int count, rte_rawdev_obj_t context) +{ + struct dpi_dma_queue_ctx_s *ctx = (struct dpi_dma_queue_ctx_s *)context; + struct dpi_dma_buf_ptr_s *cmd; + uint32_t c = 0; + + for (c = 0; c < count; c++) { + uint64_t dpi_cmd[DPI_DMA_CMD_SIZE] = {0}; + union dpi_dma_instr_hdr_u *hdr; + uint16_t index = 0, i; + + hdr = (union dpi_dma_instr_hdr_u *)&dpi_cmd[0]; + cmd = (struct dpi_dma_buf_ptr_s *)buffers[c]->buf_addr; + + hdr->s.xtype = ctx->xtype & DPI_XTYPE_MASK; + hdr->s.pt = ctx->pt & DPI_HDR_PT_MASK; + /* Request initiated with byte write completion, but completion + * pointer not provided + */ + if ((hdr->s.pt == DPI_HDR_PT_ZBW_CA || + hdr->s.pt == DPI_HDR_PT_ZBW_NC) && cmd->comp_ptr == NULL) + return c; + + cmd->comp_ptr->cdata = DPI_REQ_CDATA; + hdr->s.ptr = (uint64_t)cmd->comp_ptr; + hdr->s.deallocv = ctx->deallocv; + hdr->s.tt = ctx->tt & DPI_W0_TT_MASK; + hdr->s.grp = ctx->grp & DPI_W0_GRP_MASK; + + /* If caller provides completion ring details, then only queue + * completion address for later polling. + */ + if (ctx->c_ring) { + ctx->c_ring->compl_data[ctx->c_ring->tail] = + cmd->comp_ptr; + STRM_INC(ctx->c_ring); + } + + if (hdr->s.deallocv) + hdr->s.pvfe = 1; + + if (hdr->s.pt == DPI_HDR_PT_WQP) + hdr->s.ptr = hdr->s.ptr | DPI_HDR_PT_WQP_STATUSNC; + + index += 4; + hdr->s.fport = 0; + hdr->s.lport = 0; + + /* For inbound case, src pointers are last pointers. + * For all other cases, src pointers are first pointers. + */ + if (ctx->xtype == DPI_XTYPE_INBOUND) { + hdr->s.nfst = cmd->wptr_cnt & DPI_MAX_POINTER; + hdr->s.nlst = cmd->rptr_cnt & DPI_MAX_POINTER; + for (i = 0; i < hdr->s.nfst; i++) { + dpi_cmd[index++] = cmd->wptr[i]->u[0]; + dpi_cmd[index++] = cmd->wptr[i]->u[1]; + } + for (i = 0; i < hdr->s.nlst; i++) { + dpi_cmd[index++] = cmd->rptr[i]->u[0]; + dpi_cmd[index++] = cmd->rptr[i]->u[1]; + } + } else { + hdr->s.nfst = cmd->rptr_cnt & DPI_MAX_POINTER; + hdr->s.nlst = cmd->wptr_cnt & DPI_MAX_POINTER; + for (i = 0; i < hdr->s.nfst; i++) { + dpi_cmd[index++] = cmd->rptr[i]->u[0]; + dpi_cmd[index++] = cmd->rptr[i]->u[1]; + } + for (i = 0; i < hdr->s.nlst; i++) { + dpi_cmd[index++] = cmd->wptr[i]->u[0]; + dpi_cmd[index++] = cmd->wptr[i]->u[1]; + } + } + if (dma_queue_submit(dev, index, dpi_cmd)) + return c; + } + return c; +} + static int otx2_dpi_rawdev_configure(const struct rte_rawdev *dev, rte_rawdev_obj_t config) { @@ -108,6 +273,7 @@ otx2_dpi_rawdev_configure(const struct rte_rawdev *dev, rte_rawdev_obj_t config) static const struct rte_rawdev_ops dpi_rawdev_ops = { .dev_configure = otx2_dpi_rawdev_configure, + .enqueue_bufs = otx2_dpi_rawdev_enqueue_bufs, }; static int From patchwork Sat Jun 1 18:20:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerin Jacob Kollanukkaran X-Patchwork-Id: 54007 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 72A281B995; Sat, 1 Jun 2019 20:20:38 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id DFB0A1B96B for ; Sat, 1 Jun 2019 20:20:36 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x51IKOkf002871 for ; Sat, 1 Jun 2019 11:20:36 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=UZEfG35S/g7NS6KwElIfxjc7uD72MoEb4PVxVvabya4=; b=HfIevaZSod2iWcrbDJdkPFy11/vnQUioQ6QrQrYzu+xc17Yf+1BVE5KzCvXYzD+a2OWz ZLRIgi316FJWY3VcYFprAv7ufosQNo9UJrw0/fEocC+cM84+yKlHtCy02oSa6YmMot9I QKElSAsJa+3Au1NM8mY4grXYP/R9i/KMulX5XuLe+k6qHXYUteJLPpofEZBGY5JDHjum 61tesAvmGKyHVnRnfenTI4AE02DT/9TM8O95RithqwRnCj5T94u1KIOoH5cIpNFpZcLz KIdrjh9U2xoWVdyQGK2mYI9hbbWnxw3qekX7tgbi08+z9UI5bSLN53eE7CeCV1swZoyQ ig== Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0a-0016f401.pphosted.com with ESMTP id 2supqksdem-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 01 Jun 2019 11:20:36 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sat, 1 Jun 2019 11:20:35 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sat, 1 Jun 2019 11:20:35 -0700 Received: from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14]) by maili.marvell.com (Postfix) with ESMTP id 787993F703F; Sat, 1 Jun 2019 11:20:34 -0700 (PDT) From: To: CC: , Vamsi Attunuru Date: Sat, 1 Jun 2019 23:50:27 +0530 Message-ID: <20190601182030.8282-7-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190601182030.8282-1-jerinj@marvell.com> References: <20190601182030.8282-1-jerinj@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-01_13:, , signatures=0 Subject: [dpdk-dev] [PATCH v1 6/9] raw/octeontx2_dma: add dequeue and device control operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Satha Rao Add dequeue, device start, stop, close and reset operations. Signed-off-by: Satha Rao Signed-off-by: Vamsi Attunuru --- drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c | 64 +++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c index bfc95657b..f8f0c4af6 100644 --- a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c +++ b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c @@ -234,6 +234,65 @@ otx2_dpi_rawdev_enqueue_bufs(struct rte_rawdev *dev, return c; } +/* Check for command completion, returns number of commands completed */ +static int +otx2_dpi_rawdev_dequeue_bufs(struct rte_rawdev *dev __rte_unused, + struct rte_rawdev_buf **buffers, + unsigned int count, rte_rawdev_obj_t context) +{ + struct dpi_dma_queue_ctx_s *ctx = (struct dpi_dma_queue_ctx_s *)context; + unsigned int i = 0, headp; + + /* No completion ring to poll */ + if (ctx->c_ring == NULL) + return 0; + + headp = ctx->c_ring->head; + for (i = 0; i < count && (headp != ctx->c_ring->tail); i++) { + struct dpi_dma_req_compl_s *comp_ptr = + ctx->c_ring->compl_data[headp]; + + if (comp_ptr->cdata) + break; + + /* Request Completed */ + buffers[i] = (void *)comp_ptr; + headp = (headp + 1) % ctx->c_ring->max_cnt; + } + ctx->c_ring->head = headp; + + return i; +} + +static int +otx2_dpi_rawdev_start(struct rte_rawdev *dev) +{ + dev->started = DPI_QUEUE_START; + + return DPI_DMA_QUEUE_SUCCESS; +} + +static void +otx2_dpi_rawdev_stop(struct rte_rawdev *dev) +{ + dev->started = DPI_QUEUE_STOP; +} + +static int +otx2_dpi_rawdev_close(struct rte_rawdev *dev) +{ + dma_engine_enb_dis(dev->dev_private, false); + dma_queue_finish(dev->dev_private); + + return DPI_DMA_QUEUE_SUCCESS; +} + +static int +otx2_dpi_rawdev_reset(struct rte_rawdev *dev) +{ + return dev ? DPI_QUEUE_STOP : DPI_QUEUE_START; +} + static int otx2_dpi_rawdev_configure(const struct rte_rawdev *dev, rte_rawdev_obj_t config) { @@ -273,7 +332,12 @@ otx2_dpi_rawdev_configure(const struct rte_rawdev *dev, rte_rawdev_obj_t config) static const struct rte_rawdev_ops dpi_rawdev_ops = { .dev_configure = otx2_dpi_rawdev_configure, + .dev_start = otx2_dpi_rawdev_start, + .dev_stop = otx2_dpi_rawdev_stop, + .dev_close = otx2_dpi_rawdev_close, + .dev_reset = otx2_dpi_rawdev_reset, .enqueue_bufs = otx2_dpi_rawdev_enqueue_bufs, + .dequeue_bufs = otx2_dpi_rawdev_dequeue_bufs, }; static int From patchwork Sat Jun 1 18:20:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerin Jacob Kollanukkaran X-Patchwork-Id: 54008 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 83E221B99F; Sat, 1 Jun 2019 20:20:41 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id B5CE71B998 for ; Sat, 1 Jun 2019 20:20:39 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x51IKQia003606 for ; Sat, 1 Jun 2019 11:20:39 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=2t1p7/R5b1lTHBst8PmKcwiXp6z9l5abDdWz+5nhvVo=; b=bSqqj8+z4ZEZz8PsNBnD26M5xuQ7Cuk8y9mU/XUHudCUFaO0ub7716Qt+cDr1BKq/WLc 0fTy5m2Pu7szfB5wrSkE4u9GjP3OCMNt2R3/cDSuRyxoxrRQ9A+mE2PpM6nSLzeZEb6g BvpdI+OP0Y/8hDV2ARSzhyggAgmPo6XE1lmfZaRy5ywN1sEF/mye2YBCkw4zS1qaornY YFrRIOqEfxWW+PbVNPwAGVIZq3NbatqWfSRXbyt4JyZklF4u1j/+C87wNUVmnO9wlBxQ QfJtS481iIvkX2yd2HKPcu7oXWqEM42NsKjX0SyKbzjTZ4Ft95nvSxYFbNF8Lg2Qpm1e Gw== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0b-0016f401.pphosted.com with ESMTP id 2survk101h-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 01 Jun 2019 11:20:39 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sat, 1 Jun 2019 11:20:37 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sat, 1 Jun 2019 11:20:37 -0700 Received: from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14]) by maili.marvell.com (Postfix) with ESMTP id D45083F703F; Sat, 1 Jun 2019 11:20:36 -0700 (PDT) From: To: CC: , Vamsi Attunuru Date: Sat, 1 Jun 2019 23:50:28 +0530 Message-ID: <20190601182030.8282-8-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190601182030.8282-1-jerinj@marvell.com> References: <20190601182030.8282-1-jerinj@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-01_13:, , signatures=0 Subject: [dpdk-dev] [PATCH v1 7/9] raw/octeontx2_dma: add driver self test X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Satha Rao Sample test to verify DMA functionality, this test covers internal transfer mode. Signed-off-by: Satha Rao Signed-off-by: Vamsi Attunuru --- drivers/raw/octeontx2_dma/Makefile | 2 +- drivers/raw/octeontx2_dma/meson.build | 2 +- drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c | 2 + drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h | 1 + drivers/raw/octeontx2_dma/otx2_dpi_test.c | 216 ++++++++++++++++++++ 5 files changed, 221 insertions(+), 2 deletions(-) create mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_test.c diff --git a/drivers/raw/octeontx2_dma/Makefile b/drivers/raw/octeontx2_dma/Makefile index 6a9a380b1..8135fba6a 100644 --- a/drivers/raw/octeontx2_dma/Makefile +++ b/drivers/raw/octeontx2_dma/Makefile @@ -25,6 +25,6 @@ LIBABIVER := 1 # # all source are stored in SRCS-y # -SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV) += otx2_dpi_rawdev.c otx2_dpi_msg.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV) += otx2_dpi_rawdev.c otx2_dpi_msg.c otx2_dpi_test.c include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/raw/octeontx2_dma/meson.build b/drivers/raw/octeontx2_dma/meson.build index 751d099d2..f1afff2a9 100644 --- a/drivers/raw/octeontx2_dma/meson.build +++ b/drivers/raw/octeontx2_dma/meson.build @@ -3,7 +3,7 @@ # deps += ['rawdev', 'ring', 'kvargs', 'bus_pci', 'common_octeontx2', 'mempool_octeontx2'] -sources = files('otx2_dpi_rawdev.c', 'otx2_dpi_msg.c') +sources = files('otx2_dpi_rawdev.c', 'otx2_dpi_msg.c', 'otx2_dpi_test.c') extra_flags = [] # This integrated controller runs only on a arm64 machine, remove 32bit warnings diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c index f8f0c4af6..0922555bc 100644 --- a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c +++ b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c @@ -338,6 +338,8 @@ static const struct rte_rawdev_ops dpi_rawdev_ops = { .dev_reset = otx2_dpi_rawdev_reset, .enqueue_bufs = otx2_dpi_rawdev_enqueue_bufs, .dequeue_bufs = otx2_dpi_rawdev_dequeue_bufs, + + .dev_selftest = test_otx2_dma_rawdev, }; static int diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h index f59bab97f..ff03431d0 100644 --- a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h +++ b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h @@ -191,5 +191,6 @@ union dpi_dma_instr_hdr_u { int otx2_dpi_queue_open(uint16_t vf_id, uint32_t size, uint32_t gaura); int otx2_dpi_queue_close(uint16_t vf_id); +int test_otx2_dma_rawdev(void); #endif /* _DPI_RAWDEV_H_ */ diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_test.c b/drivers/raw/octeontx2_dma/otx2_dpi_test.c new file mode 100644 index 000000000..571136bf5 --- /dev/null +++ b/drivers/raw/octeontx2_dma/otx2_dpi_test.c @@ -0,0 +1,216 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "otx2_dpi_rawdev.h" + +static struct dpi_cring_data_s cring; + +static uint8_t +buffer_fill(uint8_t *addr, int len, uint8_t val) +{ + int j = 0; + + memset(addr, 0, len); + for (j = 0; j < len; j++) + *(addr + j) = val++; + + return val; +} + +static int +validate_buffer(uint8_t *saddr, uint8_t *daddr, int len) +{ + int j = 0, ret = 0; + + for (j = 0; j < len; j++) { + if (*(saddr + j) != *(daddr + j)) { + otx2_dpi_dbg("FAIL: Data Integrity failed"); + otx2_dpi_dbg("index: %d, Expected: 0x%x, Actual: 0x%x", + j, *(saddr + j), *(daddr + j)); + ret = -1; + break; + } + } + + return ret; +} + +static inline int +dma_test_internal(int dma_port, int buf_size) +{ + struct dpi_dma_req_compl_s *comp_data; + struct dpi_dma_queue_ctx_s ctx = {0}; + struct rte_rawdev_buf buf = {0}; + struct rte_rawdev_buf *d_buf[1]; + struct rte_rawdev_buf *bufp[1]; + struct dpi_dma_buf_ptr_s cmd; + union dpi_dma_ptr_u rptr = { {0} }; + union dpi_dma_ptr_u wptr = { {0} }; + uint8_t *fptr, *lptr; + int ret; + + fptr = (uint8_t *)rte_malloc("dummy", buf_size, 128); + lptr = (uint8_t *)rte_malloc("dummy", buf_size, 128); + comp_data = rte_malloc("dummy", buf_size, 128); + if (fptr == NULL || lptr == NULL || comp_data == NULL) { + otx2_dpi_dbg("Unable to allocate internal memory"); + return -ENOMEM; + } + + buffer_fill(fptr, buf_size, 0); + memset(&cmd, 0, sizeof(struct dpi_dma_buf_ptr_s)); + memset(lptr, 0, buf_size); + memset(comp_data, 0, buf_size); + rptr.s.ptr = (uint64_t)fptr; + rptr.s.length = buf_size; + wptr.s.ptr = (uint64_t)lptr; + wptr.s.length = buf_size; + cmd.rptr[0] = &rptr; + cmd.wptr[0] = &wptr; + cmd.rptr_cnt = 1; + cmd.wptr_cnt = 1; + cmd.comp_ptr = comp_data; + buf.buf_addr = (void *)&cmd; + bufp[0] = &buf; + + ctx.xtype = DPI_XTYPE_INTERNAL_ONLY; + ctx.pt = 0; + ctx.c_ring = &cring; + + ret = rte_rawdev_enqueue_buffers(dma_port, + (struct rte_rawdev_buf **)bufp, 1, + &ctx); + if (ret < 0) { + otx2_dpi_dbg("Enqueue request failed"); + return 0; + } + + /* Wait and dequeue completion */ + do { + sleep(1); + ret = rte_rawdev_dequeue_buffers(dma_port, &d_buf[0], 1, &ctx); + if (ret) + break; + + otx2_dpi_dbg("Dequeue request not completed"); + } while (1); + + if (validate_buffer(fptr, lptr, buf_size)) { + otx2_dpi_dbg("DMA transfer failed\n"); + return -EAGAIN; + } + otx2_dpi_dbg("Internal Only DMA transfer successfully completed"); + + if (lptr) + rte_free(lptr); + if (fptr) + rte_free(fptr); + if (comp_data) + rte_free(comp_data); + + return 0; +} + +static void * +dpi_create_mempool(void) +{ + void *chunk_pool = NULL; + char pool_name[25]; + int ret; + + snprintf(pool_name, sizeof(pool_name), "dpi_chunk_pool"); + + chunk_pool = (void *)rte_mempool_create_empty(pool_name, 1024, 1024, + 0, 0, rte_socket_id(), 0); + if (chunk_pool == NULL) { + otx2_dpi_dbg("Unable to create memory pool."); + return NULL; + } + + ret = rte_mempool_set_ops_byname(chunk_pool, + rte_mbuf_platform_mempool_ops(), NULL); + if (ret < 0) { + otx2_dpi_dbg("Unable to set pool ops"); + rte_mempool_free(chunk_pool); + return NULL; + } + + ret = rte_mempool_populate_default(chunk_pool); + if (ret < 0) { + otx2_dpi_dbg("Unable to populate pool"); + return NULL; + } + + return chunk_pool; +} + +int +test_otx2_dma_rawdev(void) +{ + struct rte_rawdev_info rdev_info = {0}; + struct dpi_rawdev_conf_s conf = {0}; + int ret, i, size = 1024; + int nb_ports; + + nb_ports = rte_rawdev_count(); + if (nb_ports == 0) { + otx2_dpi_dbg("No Rawdev ports - bye"); + return -ENODEV; + } + + i = rte_rawdev_get_dev_id("DPI:5:00.1"); + /* Configure rawdev ports */ + conf.chunk_pool = dpi_create_mempool(); + rdev_info.dev_private = &conf; + ret = rte_rawdev_configure(i, (rte_rawdev_obj_t)&rdev_info); + if (ret) { + otx2_dpi_dbg("Unable to configure DPIVF %d", i); + return -ENODEV; + } + otx2_dpi_dbg("rawdev %d configured successfully", i); + + /* Each stream allocate its own completion ring data, store it in + * application context. Each stream needs to use same application + * context for enqueue/dequeue. + */ + cring.compl_data = rte_malloc("dummy", sizeof(void *) * 1024, 128); + if (!cring.compl_data) { + otx2_dpi_dbg("Completion allocation failed"); + return -ENOMEM; + } + + cring.max_cnt = 1024; + cring.head = 0; + cring.tail = 0; + + ret = dma_test_internal(i, size); + if (ret) + otx2_dpi_dbg("DMA transfer failed for queue %d", i); + + if (rte_rawdev_close(i)) + otx2_dpi_dbg("Dev close failed for port %d", i); + + if (conf.chunk_pool) + rte_mempool_free(conf.chunk_pool); + + return ret; +} From patchwork Sat Jun 1 18:20:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerin Jacob Kollanukkaran X-Patchwork-Id: 54009 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2F7E31B9A3; Sat, 1 Jun 2019 20:20:43 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 6899B1B99E for ; Sat, 1 Jun 2019 20:20:42 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x51IK66n003558 for ; Sat, 1 Jun 2019 11:20:41 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=UhhyrhBZUbhDnUnwfk5UJbSbYdp9I2ZJN3hWks9mJok=; b=vyPSKiEHiibK/fSVnsd78XYz5u9uMZv3A7pf3OkZMfrH2X4B6185Kn0mm3Q5lsGfvn0m 8CkmGqDohpKePpmYvniV9nElGLSxO9uHSdVYe/J+rYFudrkYRhAidMQ8tBnh99s9HM/o AsUaGfrfk+VwPzEwS1jF+uXjFgfZ4vDjOre9T9l6Rgz+mX81KUqpIGfHGTi7yzqducyN fkEbKg5aeUVBT5g4JTLqTIhnN1s+9o4efjNUmefB5T0sQM/hVMj/j2dz6rplyeXvVBCY 81UwnVlWpPuxIC+BwuOL93pjyc/OmIaovxpoQH26scmd82frTrlP7HrBSrmjqA6s7ExG PQ== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0b-0016f401.pphosted.com with ESMTP id 2survk101m-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 01 Jun 2019 11:20:41 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sat, 1 Jun 2019 11:20:40 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sat, 1 Jun 2019 11:20:40 -0700 Received: from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14]) by maili.marvell.com (Postfix) with ESMTP id BA6E63F703F; Sat, 1 Jun 2019 11:20:39 -0700 (PDT) From: To: CC: , Vamsi Attunuru Date: Sat, 1 Jun 2019 23:50:29 +0530 Message-ID: <20190601182030.8282-9-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190601182030.8282-1-jerinj@marvell.com> References: <20190601182030.8282-1-jerinj@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-01_13:, , signatures=0 Subject: [dpdk-dev] [PATCH v1 8/9] usertools: add octeontx2 DMA device X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Satha Rao Update the devbind script with new section of DMA devices, also added OCTEONTX2 DMA device ID to DMA device list Signed-off-by: Satha Rao Signed-off-by: Vamsi Attunuru --- usertools/dpdk-devbind.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/usertools/dpdk-devbind.py b/usertools/dpdk-devbind.py index 9e79f0d28..99bbfc5d3 100755 --- a/usertools/dpdk-devbind.py +++ b/usertools/dpdk-devbind.py @@ -35,12 +35,15 @@ 'SVendor': None, 'SDevice': None} octeontx2_npa = {'Class': '08', 'Vendor': '177d', 'Device': 'a0fb,a0fc', 'SVendor': None, 'SDevice': None} +octeontx2_dma = {'Class': '08', 'Vendor': '177d', 'Device': 'a081', + 'SVendor': None, 'SDevice': None} network_devices = [network_class, cavium_pkx, avp_vnic, ifpga_class] crypto_devices = [encryption_class, intel_processor_class] eventdev_devices = [cavium_sso, cavium_tim, octeontx2_sso] mempool_devices = [cavium_fpa, octeontx2_npa] compress_devices = [cavium_zip] +dma_devices = [octeontx2_dma] # global dict ethernet devices present. Dictionary indexed by PCI address. # Each device within this is itself a dictionary of device properties @@ -595,6 +598,9 @@ def show_status(): if status_dev == "compress" or status_dev == "all": show_device_status(compress_devices , "Compress") + if status_dev == "dma" or status_dev == "all": + show_device_status(dma_devices , "DMA") + def parse_args(): '''Parses the command-line arguments given by the user and takes the @@ -670,6 +676,7 @@ def do_arg_actions(): get_device_details(eventdev_devices) get_device_details(mempool_devices) get_device_details(compress_devices) + get_device_details(dma_devices) show_status() @@ -690,6 +697,7 @@ def main(): get_device_details(eventdev_devices) get_device_details(mempool_devices) get_device_details(compress_devices) + get_device_details(dma_devices) do_arg_actions() if __name__ == "__main__": From patchwork Sat Jun 1 18:20:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerin Jacob Kollanukkaran X-Patchwork-Id: 54010 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0EBC61B99B; Sat, 1 Jun 2019 20:20:48 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 0EC231B994 for ; Sat, 1 Jun 2019 20:20:45 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x51IKGVa003587; Sat, 1 Jun 2019 11:20:45 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=xiurMNlbmxsIlneCwfXIN+U9SgHE2XgKEJpaOUxnqPk=; b=sbhVGoB9a0AgKUemzH1R0S6umGbZQPdog7XLL7OPMi5DoyB/mL9+o6GgCOZp+s2RCbS0 FjaIqUuV0OZ16ra42ZE2iHt8j8dmE1LRsEhGQ10bdeeAoGx3aD6O+oPuXmBVIXruC/KZ fGahjvlTqOb7ve1vyRmULi9MxlAvaG2PeuBFZ7wZ2mf0kZ71tRJZOvqjpD3PzlHKqxEf htGlfRJgqDZPwL4vIGh8WSvu4Rv4Tu5zrlF1fPEuesvgUZIZRtxhqgMZoyiphhHTB3HA MnuQ0npvM+9lKTLNsKfNXYsgqOeTKW6vRBI6CRSnKzJ6WyoxDpqkq48bJWq+RRg7b4iW Gg== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 2survk101y-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sat, 01 Jun 2019 11:20:45 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sat, 1 Jun 2019 11:20:43 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sat, 1 Jun 2019 11:20:43 -0700 Received: from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14]) by maili.marvell.com (Postfix) with ESMTP id 6B1A03F703F; Sat, 1 Jun 2019 11:20:42 -0700 (PDT) From: To: CC: , John McNamara , "Thomas Monjalon" , Vamsi Attunuru , "Jerin Jacob" Date: Sat, 1 Jun 2019 23:50:30 +0530 Message-ID: <20190601182030.8282-10-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190601182030.8282-1-jerinj@marvell.com> References: <20190601182030.8282-1-jerinj@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-01_13:, , signatures=0 Subject: [dpdk-dev] [PATCH v1 9/9] raw/octeontx2_dma: add documentation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Satha Rao Add documentation and update MAINTAINERS file. Cc: John McNamara Cc: Thomas Monjalon Signed-off-by: Satha Rao Signed-off-by: Vamsi Attunuru Signed-off-by: Jerin Jacob --- MAINTAINERS | 6 ++ doc/guides/platform/octeontx2.rst | 5 ++ doc/guides/rawdevs/index.rst | 1 + doc/guides/rawdevs/octeontx2_dma.rst | 114 +++++++++++++++++++++++++++ 4 files changed, 126 insertions(+) create mode 100644 doc/guides/rawdevs/octeontx2_dma.rst diff --git a/MAINTAINERS b/MAINTAINERS index 74ac6d41f..2434fc18c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1062,6 +1062,12 @@ M: Nipun Gupta F: drivers/raw/dpaa2_cmdif/ F: doc/guides/rawdevs/dpaa2_cmdif.rst +Marvell OCTEON TX2 DMA +M: Satha Rao +M: Vamsi Attunuru +F: drivers/raw/octeontx2_dma/ +F: doc/guides/rawdevs/octeontx2_dma.rst + Packet processing ----------------- diff --git a/doc/guides/platform/octeontx2.rst b/doc/guides/platform/octeontx2.rst index c9ea45647..e6bfa2052 100644 --- a/doc/guides/platform/octeontx2.rst +++ b/doc/guides/platform/octeontx2.rst @@ -101,6 +101,9 @@ This section lists dataplane H/W block(s) available in OCTEON TX2 SoC. #. **Mempool Driver** See :doc:`../mempool/octeontx2` for NPA mempool driver information. +#. **DMA Rawdev Driver** + See :doc:`../rawdevs/octeontx2_dma` for DMA driver information. + Procedure to Setup Platform --------------------------- @@ -143,6 +146,8 @@ compatible board: # Enable if netdev VF driver required CONFIG_OCTEONTX2_VF=y CONFIG_CRYPTO_DEV_OCTEONTX2_CPT=y + # Enable if OCTEONTX2 DMA PF driver required + CONFIG_OCTEONTX2_DPI_PF=n 2. **ARM64 Linux Tool Chain** diff --git a/doc/guides/rawdevs/index.rst b/doc/guides/rawdevs/index.rst index 7c3bd9586..1351d14e4 100644 --- a/doc/guides/rawdevs/index.rst +++ b/doc/guides/rawdevs/index.rst @@ -14,3 +14,4 @@ application through rawdev API. dpaa2_cmdif dpaa2_qdma ifpga_rawdev + octeontx2_dma diff --git a/doc/guides/rawdevs/octeontx2_dma.rst b/doc/guides/rawdevs/octeontx2_dma.rst new file mode 100644 index 000000000..7409c17ab --- /dev/null +++ b/doc/guides/rawdevs/octeontx2_dma.rst @@ -0,0 +1,114 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(c) 2019 Marvell International Ltd. + +OCTEON TX2 DMA Driver +===================== + +OCTEON TX2 has an internal DMA unit which can be used by applications to initiate +DMA transaction internally, from/to host when OCTEON TX2 operates in PCIe End +Point mode. The DMA PF function supports 8 VFs corresponding to 8 DMA queues. +Each DMA queue was exposed as a VF function when SRIOV enabled. + +Features +-------- + +This DMA PMD supports below 3 modes of memory transfers + +#. Internal - OCTEON TX2 DRAM to DRAM without core intervention + +#. Inbound - Host DRAM to OCTEON TX2 DRAM without host/OCTEON TX2 cores involvement + +#. Outbound - OCTEON TX2 DRAM to Host DRAM without host/OCTEON TX2 cores involvement + +Prerequisites and Compilation procedure +--------------------------------------- + + See :doc:`../platform/octeontx2` for setup information. + + +Pre-Installation Configuration +------------------------------ + +Config File Options +~~~~~~~~~~~~~~~~~~~ + +The following options can be modified in the ``config`` file. + +- ``CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV`` (default ``y``) + + Toggle compilation of the ``lrte_pmd_octeontx2_dma`` driver. + +Enabling logs +------------- + +For enabling logs, use the following EAL parameter: + +.. code-block:: console + + ./your_dma_application --log-level=pmd.raw.octeontx2.dpi, + +Using ``pmd.raw.octeontx2.dpi`` as log matching criteria, all Event PMD logs +can be enabled which are lower than logging ``level``. + +Initialization +-------------- + +The number of DMA VFs (queues) enabled can be controlled by setting sysfs +entry, `sriov_numvfs` for the corresponding PF driver. + +.. code-block:: console + + echo > /sys/bus/pci/drivers/octeontx2-dpi/0000\:05\:00.0/sriov_numvfs + +Once the required VFs are enabled, to be accessible from DPDK, VFs need to be +bound to vfio-pci driver. + +Device Setup +------------- + +The DPI DMA HW device will need to be bound to a user-space IO driver for use. +The script ``dpdk-devbind.py`` script included with DPDK can be used to view the +state of the devices and to bind them to a suitable DPDK-supported kernel driver. +When querying the status of the devices, they will appear under the category of +"dma devices", i.e. the command ``dpdk-devbind.py --status-dev dma`` can be used +to see the state of those devices alone. + +Device Configuration +-------------------- + +Configuring DMA rawdev device is done using the ``rte_rawdev_configure()`` +API, which takes the mempool as parameter. PMD uses this pool to submit DMA +commands to HW. + +The following code shows how the device is configured + +.. code-block:: c + + struct dpi_rawdev_conf_s conf = {0}; + struct rte_rawdev_info rdev_info = {.dev_private = &conf}; + + conf.chunk_pool = (void *)rte_mempool_create_empty(...); + rte_mempool_set_ops_byname(conf.chunk_pool, rte_mbuf_platform_mempool_ops(), NULL); + rte_mempool_populate_default(conf.chunk_pool); + + rte_rawdev_configure(dev_id, (rte_rawdev_obj_t)&rdev_info); + +Performing Data Transfer +------------------------ + +To perform data transfer using OCTEON TX2 DMA rawdev devices use standard +``rte_rawdev_enqueue_buffers()`` and ``rte_rawdev_dequeue_buffers()`` APIs. + +Self test +--------- + +On EAL initialization, dma devices will be probed and populated into the +raw devices. The rawdev ID of the device can be obtained using + +* Invoke ``rte_rawdev_get_dev_id("DPI:x")`` from the application + where x is the VF device's bus id specified in "bus:device.func" format. Use this + index for further rawdev function calls. + +* This PMD supports driver self test, to test DMA internal mode from test + application one can directly calls + ``rte_rawdev_selftest(rte_rawdev_get_dev_id("DPI:x"))``