From patchwork Tue May 21 08:23:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ziyang Xuan X-Patchwork-Id: 53566 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E2B524CA7; Tue, 21 May 2019 10:12:51 +0200 (CEST) Received: from huawei.com (szxga06-in.huawei.com [45.249.212.32]) by dpdk.org (Postfix) with ESMTP id 6FCCE14EC for ; Tue, 21 May 2019 10:12:49 +0200 (CEST) Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id A032A844EE1DE6B4037F for ; Tue, 21 May 2019 16:12:47 +0800 (CST) Received: from tester_149.localdomain (10.175.119.39) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.439.0; Tue, 21 May 2019 16:12:38 +0800 From: Ziyang Xuan To: CC: , , , , Ziyang Xuan Date: Tue, 21 May 2019 16:23:17 +0800 Message-ID: <1558426997-187282-1-git-send-email-xuanziyang2@huawei.com> X-Mailer: git-send-email 1.8.3.1 MIME-Version: 1.0 X-Originating-IP: [10.175.119.39] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 08/11] net/hinic: add hinic PMD build and doc files X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add build and doc files, and common code files. Signed-off-by: Ziyang Xuan --- MAINTAINERS | 9 + config/common_base | 5 + doc/guides/nics/features/hinic.ini | 32 ++ drivers/net/Makefile | 1 + drivers/net/hinic/Makefile | 91 +++++ drivers/net/hinic/base/hinic_logs.c | 16 + drivers/net/hinic/base/hinic_logs.h | 31 ++ drivers/net/hinic/base/meson.build | 61 +++ drivers/net/hinic/hinic_pmd_dpdev.c | 720 ++++++++++++++++++++++++++++++++++++ drivers/net/hinic/meson.build | 18 + mk/rte.app.mk | 1 + 11 files changed, 985 insertions(+) create mode 100644 doc/guides/nics/features/hinic.ini create mode 100644 drivers/net/hinic/Makefile create mode 100644 drivers/net/hinic/base/hinic_logs.c create mode 100644 drivers/net/hinic/base/hinic_logs.h create mode 100644 drivers/net/hinic/base/meson.build create mode 100644 drivers/net/hinic/hinic_pmd_dpdev.c create mode 100644 drivers/net/hinic/meson.build diff --git a/MAINTAINERS b/MAINTAINERS index 15d0829..b76340c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -577,6 +577,15 @@ F: drivers/net/enic/ F: doc/guides/nics/enic.rst F: doc/guides/nics/features/enic.ini +Huawei hinic +M: Xiaoyun Wang +M: Ziyang Xuan +M: Guoyang Zhou +M: Rami Rosen +F: drivers/net/hinic/ +F: doc/guides/nics/hinic.rst +F: doc/guides/nics/features/hinic.ini + Intel e1000 M: Wenzhuo Lu T: git://dpdk.org/next/dpdk-next-net-intel diff --git a/config/common_base b/config/common_base index 6b96e0e..8d8ba10 100644 --- a/config/common_base +++ b/config/common_base @@ -277,6 +277,11 @@ CONFIG_RTE_LIBRTE_E1000_DEBUG_TX_FREE=n CONFIG_RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC=n # +# Compile burst-oriented HINIC PMD driver +# +CONFIG_RTE_LIBRTE_HINIC_PMD=y + +# # Compile burst-oriented IXGBE PMD driver # CONFIG_RTE_LIBRTE_IXGBE_PMD=y diff --git a/doc/guides/nics/features/hinic.ini b/doc/guides/nics/features/hinic.ini new file mode 100644 index 0000000..d3b9e35 --- /dev/null +++ b/doc/guides/nics/features/hinic.ini @@ -0,0 +1,32 @@ +; +; Supported features of the 'hinic' network poll mode driver. +; +; Refer to default.ini for the full list of available PMD features. +; +[Features] +Speed capabilities = Y +Link status = Y +Link status event = Y +Free Tx mbuf on demand = Y +Queue start/stop = Y +Jumbo frame = N +Scattered Rx = Y +TSO = Y +Promiscuous mode = Y +Unicast MAC filter = Y +Multicast MAC filter = Y +RSS hash = Y +RSS key update = Y +RSS reta update = Y +Inner RSS = Y +CRC offload = Y +L3 checksum offload = Y +L4 checksum offload = Y +Inner L3 checksum = Y +Inner L4 checksum = Y +Basic stats = Y +Extended stats = Y +Stats per queue = Y +BSD nic_uio = Y +Linux UIO = Y +x86-64 = Y diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 3a72cf3..606b274 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -29,6 +29,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_ENETC_PMD) += enetc DIRS-$(CONFIG_RTE_LIBRTE_ENIC_PMD) += enic DIRS-$(CONFIG_RTE_LIBRTE_PMD_FAILSAFE) += failsafe DIRS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k +DIRS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic DIRS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e DIRS-$(CONFIG_RTE_LIBRTE_IAVF_PMD) += iavf DIRS-$(CONFIG_RTE_LIBRTE_ICE_PMD) += ice diff --git a/drivers/net/hinic/Makefile b/drivers/net/hinic/Makefile new file mode 100644 index 0000000..9fe4946 --- /dev/null +++ b/drivers/net/hinic/Makefile @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2017 Huawei Technologies Co., Ltd + +include $(RTE_SDK)/mk/rte.vars.mk + +# +# library name +# +LIB = librte_pmd_hinic.a + +CFLAGS += -O3 +CFLAGS += $(WERROR_FLAGS) + +EXPORT_MAP := rte_pmd_hinic_version.map + +LIBABIVER := 1 + +# +# Add extra flags for base driver files (also known as shared code) +# to disable warnings +# +ifeq ($(CONFIG_RTE_TOOLCHAIN_ICC),y) +CFLAGS_BASE_DRIVER = -wd593 -wd188 +else ifeq ($(CONFIG_RTE_TOOLCHAIN_CLANG),y) +CFLAGS_BASE_DRIVER += -Wno-sign-compare +CFLAGS_BASE_DRIVER += -Wno-unused-value +CFLAGS_BASE_DRIVER += -Wno-unused-parameter +CFLAGS_BASE_DRIVER += -Wno-strict-aliasing +CFLAGS_BASE_DRIVER += -Wno-format +CFLAGS_BASE_DRIVER += -Wno-missing-field-initializers +CFLAGS_BASE_DRIVER += -Wno-pointer-to-int-cast +CFLAGS_BASE_DRIVER += -Wno-format-nonliteral +CFLAGS_BASE_DRIVER += -Wno-unused-variable +else +CFLAGS_BASE_DRIVER = -Wno-sign-compare +CFLAGS_BASE_DRIVER += -Wno-unused-value +CFLAGS_BASE_DRIVER += -Wno-unused-parameter +CFLAGS_BASE_DRIVER += -Wno-strict-aliasing +CFLAGS_BASE_DRIVER += -Wno-format +CFLAGS_BASE_DRIVER += -Wno-missing-field-initializers +CFLAGS_BASE_DRIVER += -Wno-pointer-to-int-cast +CFLAGS_BASE_DRIVER += -Wno-format-nonliteral +CFLAGS_BASE_DRIVER += -Wno-format-security +CFLAGS_BASE_DRIVER += -Wno-unused-variable + +ifeq ($(shell test $(GCC_VERSION) -ge 44 && echo 1), 1) +CFLAGS_BASE_DRIVER += -Wno-unused-but-set-variable +endif + +endif + +OBJS_BASE_DRIVER=$(patsubst %.c,%.o,$(notdir $(wildcard $(SRCDIR)/base/*.c))) +$(foreach obj, $(OBJS_BASE_DRIVER), $(eval CFLAGS_$(obj)+=$(CFLAGS_BASE_DRIVER))) + +VPATH += $(SRCDIR)/base + +# +# all source are stored in SRCS-y +# + +SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_logs.c + +SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_api_cmd.c +SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_cfg.c +SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_cmdq.c +SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_eqs.c +SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_hwdev.c +SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_hwif.c +SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_mgmt.c +SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_niccfg.c +SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_nicio.c +SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_qp.c +SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_wq.c + +SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_dpdev.c +#SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_ethdev.c +#SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_rx.c +#SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_tx.c +# this lib depends upon: +DEPDIRS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += lib/librte_eal lib/librte_ether +DEPDIRS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += lib/librte_mempool lib/librte_mbuf +DEPDIRS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += lib/librte_net lib/librte_hash +DEPDIRS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += lib/librte_kvargs +DEPDIRS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += lib/librte_net +DEPDIRS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += lib/librte_ring + +LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring +LDLIBS += -lrte_ethdev -lrte_net -lrte_kvargs -lrte_hash +LDLIBS += -lrte_bus_pci + +include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/net/hinic/base/hinic_logs.c b/drivers/net/hinic/base/hinic_logs.c new file mode 100644 index 0000000..1e9b5ad --- /dev/null +++ b/drivers/net/hinic/base/hinic_logs.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Huawei Technologies Co., Ltd + */ + + +#include "hinic_logs.h" + +int hinic_logtype; + +RTE_INIT(hinic_init_log) +{ + hinic_logtype = rte_log_register("pmd.net.hinic"); + if (hinic_logtype >= 0) + rte_log_set_level(hinic_logtype, RTE_LOG_INFO); +} + diff --git a/drivers/net/hinic/base/hinic_logs.h b/drivers/net/hinic/base/hinic_logs.h new file mode 100644 index 0000000..ca815ed --- /dev/null +++ b/drivers/net/hinic/base/hinic_logs.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Huawei Technologies Co., Ltd + */ + +#ifndef _HINIC_LOGS_H_ +#define _HINIC_LOGS_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C"{ +#endif +#endif /* __cplusplus */ +#include + +/* Reported driver name. */ +#define HINIC_DRIVER_NAME "net_hinic" + +extern int hinic_logtype; + +#define PMD_DRV_LOG(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, hinic_logtype, \ + HINIC_DRIVER_NAME": " fmt "\n", ##args) + + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + +#endif /* _HINIC_LOGS_H_ */ diff --git a/drivers/net/hinic/base/meson.build b/drivers/net/hinic/base/meson.build new file mode 100644 index 0000000..5b62254 --- /dev/null +++ b/drivers/net/hinic/base/meson.build @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2017 Huawei Technologies Co., Ltd + +sources = [ + 'hinic_pmd_api_cmd.c', + 'hinic_pmd_cfg.c', + 'hinic_pmd_cmdq.c', + 'hinic_pmd_eqs.c', + 'hinic_pmd_hwdev.c', + 'hinic_pmd_hwif.c', + 'hinic_pmd_mgmt.c', + 'hinic_pmd_niccfg.c', + 'hinic_pmd_nicio.c', + 'hinic_pmd_qp.c', + 'hinic_pmd_wq.c' +] + +headers = [ + 'hinic_compat.h', + 'hinic_csr.h', + 'hinic_ctx_def.h', + 'hinic_pmd_api_cmd.h', + 'hinic_pmd_cfg.h', + 'hinic_pmd_cmdq.h', + 'hinic_pmd_dpdev.h', + 'hinic_pmd_eqs.h', + 'hinic_pmd_hwdev.h', + 'hinic_pmd_hw.h', + 'hinic_pmd_hwif.h', + 'hinic_pmd_hw_mgmt.h', + 'hinic_pmd_mgmt.h', + 'hinic_pmd_mgmt_interface.h', + 'hinic_pmd_niccfg.h', + 'hinic_pmd_nic.h', + 'hinic_pmd_nicio.h', + 'hinic_pmd_qp.h', + 'hinic_pmd_wq.h', + 'hinic_port_cmd.h', + 'hinic_qe_def.h' +] + + +deps += 'ethdev' +deps += 'pci' + +error_cflags = ['-Wno-unused-value', + '-Wno-unused-but-set-variable', + '-Wno-unused-variable', +] +c_args = cflags + +foreach flag: error_cflags + if cc.has_argument(flag) + c_args += flag + endif +endforeach + +base_lib = static_library('hinic_base', sources, + dependencies: static_rte_eal, + c_args: c_args) +base_objs = base_lib.extract_all_objects() diff --git a/drivers/net/hinic/hinic_pmd_dpdev.c b/drivers/net/hinic/hinic_pmd_dpdev.c new file mode 100644 index 0000000..bf72ef1 --- /dev/null +++ b/drivers/net/hinic/hinic_pmd_dpdev.c @@ -0,0 +1,720 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Huawei Technologies Co., Ltd + */ + +#include +#include +#include +#include + +#include "base/hinic_pmd_dpdev.h" +#include "hinic_pmd_ethdev.h" + +#define DEFAULT_BASE_COS (4) +#define NR_MAX_COS (8) +#define HINIC_HASH_FUNC rte_jhash +#define HINIC_HASH_KEY_LEN (sizeof(dma_addr_t)) +#define HINIC_HASH_FUNC_INIT_VAL (0) +#define HINIC_SERVICE_MODE_OVS (0) + +/* dma pool */ +struct dma_pool { + u32 inuse; + size_t elem_size; + size_t align; + size_t boundary; + void *nic_dev; + + char name[32]; +}; + +static int hinic_osdep_init(hinic_nic_dev *nic_dev) +{ + struct rte_hash_parameters dh_params = { 0 }; + struct rte_hash *paddr_hash = NULL; + + nic_dev->os_dep = &nic_dev->dumb_os_dep; + + rte_atomic32_set(&nic_dev->os_dep->dma_alloc_cnt, 0); + rte_spinlock_init(&nic_dev->os_dep->dma_hash_lock); + + dh_params.name = nic_dev->proc_dev_name; + dh_params.entries = HINIC_MAX_DMA_ENTRIES; + dh_params.key_len = HINIC_HASH_KEY_LEN; + dh_params.hash_func = HINIC_HASH_FUNC; + dh_params.hash_func_init_val = HINIC_HASH_FUNC_INIT_VAL; + dh_params.socket_id = SOCKET_ID_ANY; + + paddr_hash = rte_hash_find_existing(dh_params.name); + if (paddr_hash == NULL) { + paddr_hash = rte_hash_create(&dh_params); + if (paddr_hash == NULL) { + PMD_DRV_LOG(ERR, "Create nic_dev phys_addr hash table failed"); + return -ENOMEM; + } + } else { + PMD_DRV_LOG(INFO, "Using existing dma hash table %s", + dh_params.name); + } + nic_dev->os_dep->dma_addr_hash = paddr_hash; + + return 0; +} + +static void hinic_osdep_deinit(hinic_nic_dev *nic_dev) +{ + uint32_t iter = 0; + dma_addr_t key_pa; + struct rte_memzone *data_mz = NULL; + struct rte_hash *paddr_hash = nic_dev->os_dep->dma_addr_hash; + + if (paddr_hash) { + /* iterate through the hash table */ + while (rte_hash_iterate(paddr_hash, (const void **)&key_pa, + (void **)&data_mz, &iter) >= 0) { + if (data_mz) { + PMD_DRV_LOG(WARNING, "Free leaked dma_addr: 0x%lx, mz: %s", + key_pa, data_mz->name); + (void)rte_memzone_free(data_mz); + } + } + + /* free phys_addr hash table */ + rte_hash_free(paddr_hash); + } + + nic_dev->os_dep = NULL; +} + +void *hinic_dma_mem_zalloc(void *dev, size_t size, dma_addr_t *dma_handle, + unsigned int flag, unsigned int align) +{ + int rc, alloc_cnt; + const struct rte_memzone *mz; + char z_name[RTE_MEMZONE_NAMESIZE]; + hinic_nic_dev *nic_dev = (hinic_nic_dev *)dev; + hash_sig_t sig; + rte_iova_t iova; + + HINIC_ASSERT((nic_dev != NULL) && + (nic_dev->os_dep->dma_addr_hash != NULL)); + + if (dma_handle == NULL || 0 == size) + return NULL; + + alloc_cnt = rte_atomic32_add_return(&nic_dev->os_dep->dma_alloc_cnt, 1); + snprintf(z_name, sizeof(z_name), "%s_%d", + nic_dev->proc_dev_name, alloc_cnt); + + mz = rte_memzone_reserve_aligned(z_name, size, SOCKET_ID_ANY, + flag, align); + if (!mz) { + PMD_DRV_LOG(ERR, "Alloc dma able memory failed, errno: %d, ma_name: %s, size: 0x%zx", + rte_errno, z_name, size); + return NULL; + } + + iova = mz->iova; + + /* check if phys_addr already exist */ + sig = HINIC_HASH_FUNC(&iova, HINIC_HASH_KEY_LEN, + HINIC_HASH_FUNC_INIT_VAL); + rc = rte_hash_lookup_with_hash(nic_dev->os_dep->dma_addr_hash, + &iova, sig); + if (rc >= 0) { + PMD_DRV_LOG(ERR, "Dma addr: 0x%lx already in hash table, error: %d, mz_name: %s", + iova, rc, z_name); + goto phys_addr_hash_err; + } + + /* record paddr in hash table */ + rte_spinlock_lock(&nic_dev->os_dep->dma_hash_lock); + rc = rte_hash_add_key_with_hash_data(nic_dev->os_dep->dma_addr_hash, + &iova, sig, + (void *)(u64)mz); + rte_spinlock_unlock(&nic_dev->os_dep->dma_hash_lock); + if (rc) { + PMD_DRV_LOG(ERR, "Insert dma addr: 0x%lx hash failed, error: %d, mz_name: %s", + iova, rc, z_name); + goto phys_addr_hash_err; + } + *dma_handle = iova; + memset(mz->addr, 0, size); + + return mz->addr; + +phys_addr_hash_err: + (void)rte_memzone_free(mz); + + return NULL; +} + +void hinic_dma_mem_free(void *dev, size_t size, void *virt, dma_addr_t phys) +{ + int rc; + struct rte_memzone *mz = NULL; + hinic_nic_dev *nic_dev = (hinic_nic_dev *)dev; + struct rte_hash *hash; + hash_sig_t sig; + + HINIC_ASSERT((nic_dev != NULL) && + (nic_dev->os_dep->dma_addr_hash != NULL)); + + if (virt == NULL || phys == 0) + return; + + hash = nic_dev->os_dep->dma_addr_hash; + sig = HINIC_HASH_FUNC(&phys, HINIC_HASH_KEY_LEN, + HINIC_HASH_FUNC_INIT_VAL); + rc = rte_hash_lookup_with_hash_data(hash, &phys, sig, (void **)&mz); + if (rc < 0) { + PMD_DRV_LOG(ERR, "Can not find phys_addr: 0x%lx, error: %d", + phys, rc); + return; + } + + HINIC_ASSERT(mz != NULL); + if (virt != mz->addr || + (size > RTE_CACHE_LINE_SIZE && size != mz->len)) { + PMD_DRV_LOG(ERR, "Match mz_info failed: " + "mz.name: %s, mz.phys: 0x%lx, mz.virt: %p, mz.len: 0x%lx, " + "phys: 0x%lx, virt: %p, size: 0x%lx", + mz->name, mz->phys_addr, mz->addr, mz->len, + phys, virt, size); + } + + rte_spinlock_lock(&nic_dev->os_dep->dma_hash_lock); + (void)rte_hash_del_key_with_hash(hash, &phys, sig); + rte_spinlock_unlock(&nic_dev->os_dep->dma_hash_lock); + + (void)rte_memzone_free(mz); +} + +void *dma_zalloc_coherent(void *dev, size_t size, + dma_addr_t *dma_handle, gfp_t flag) +{ + return hinic_dma_mem_zalloc(dev, size, dma_handle, flag, + RTE_CACHE_LINE_SIZE); +} + +void *dma_zalloc_coherent_aligned(void *dev, size_t size, + dma_addr_t *dma_handle, gfp_t flag) +{ + return hinic_dma_mem_zalloc(dev, size, dma_handle, flag, PAGE_SIZE); +} + +void *dma_zalloc_coherent_aligned256k(void *dev, size_t size, + dma_addr_t *dma_handle, gfp_t flag) +{ + return hinic_dma_mem_zalloc(dev, size, dma_handle, + flag, PAGE_SIZE * 64); +} + +void dma_free_coherent(void *dev, size_t size, void *virt, dma_addr_t phys) +{ + hinic_dma_mem_free(dev, size, virt, phys); +} + +void dma_free_coherent_volatile(void *dev, size_t size, + volatile void *virt, dma_addr_t phys) +{ + int rc; + struct rte_memzone *mz = NULL; + hinic_nic_dev *nic_dev = (hinic_nic_dev *)dev; + struct rte_hash *hash; + hash_sig_t sig; + + HINIC_ASSERT((nic_dev != NULL) && + (nic_dev->os_dep->dma_addr_hash != NULL)); + + if (virt == NULL || phys == 0) + return; + + hash = nic_dev->os_dep->dma_addr_hash; + sig = HINIC_HASH_FUNC(&phys, HINIC_HASH_KEY_LEN, + HINIC_HASH_FUNC_INIT_VAL); + rc = rte_hash_lookup_with_hash_data(hash, &phys, sig, (void **)&mz); + if (rc < 0) { + PMD_DRV_LOG(ERR, "Can not find phys_addr:0x%lx, error:%d", + phys, rc); + return; + } + + HINIC_ASSERT(mz != NULL); + if (virt != mz->addr || + (size > RTE_CACHE_LINE_SIZE && size != mz->len)) { + PMD_DRV_LOG(ERR, "Match mz_info failed: " + "mz.name:%s, mz.phys:0x%lx, mz.virt:%p, mz.len:0x%lx, " + "phys:0x%lx, virt:%p, size:0x%lx", + mz->name, mz->phys_addr, mz->addr, mz->len, + phys, virt, size); + } + + rte_spinlock_lock(&nic_dev->os_dep->dma_hash_lock); + (void)rte_hash_del_key_with_hash(hash, &phys, sig); + rte_spinlock_unlock(&nic_dev->os_dep->dma_hash_lock); + + (void)rte_memzone_free(mz); +} + +struct dma_pool *dma_pool_create(const char *name, void *dev, + size_t size, size_t align, size_t boundary) +{ + struct pci_pool *pool; + + pool = (struct pci_pool *)rte_zmalloc(NULL, sizeof(*pool), + HINIC_MEM_ALLOC_ALIGNE_MIN); + if (!pool) + return NULL; + + pool->inuse = 0; + pool->elem_size = size; + pool->align = align; + pool->boundary = boundary; + pool->nic_dev = dev; + strncpy(pool->name, name, (sizeof(pool->name) - 1)); + + return pool; +} + +void dma_pool_destroy(struct dma_pool *pool) +{ + if (!pool) + return; + + if (pool->inuse != 0) { + PMD_DRV_LOG(ERR, "Leak memory, dma_pool:%s, inuse_count:%u", + pool->name, pool->inuse); + } + + rte_free(pool); +} + +void *dma_pool_alloc(struct pci_pool *pool, int flags, dma_addr_t *dma_addr) +{ + void *buf; + + buf = hinic_dma_mem_zalloc(pool->nic_dev, pool->elem_size, + dma_addr, flags, (u32)pool->align); + if (buf) + pool->inuse++; + + return buf; +} + +void dma_pool_free(struct pci_pool *pool, void *vaddr, dma_addr_t dma) +{ + pool->inuse--; + hinic_dma_mem_free(pool->nic_dev, pool->elem_size, vaddr, dma); +} + +/** + * Atomically writes the link status information into global + * struct rte_eth_dev. + */ +int hinic_dev_atomic_write_link_status(struct rte_eth_dev *dev, + struct rte_eth_link *link) +{ + struct rte_eth_link *dst = &dev->data->dev_link; + struct rte_eth_link *src = link; + + if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, + *(uint64_t *)src) == 0) + return HINIC_ERROR; + + return HINIC_OK; +} + +int hinic_link_event_process(struct rte_eth_dev *dev, u8 status) +{ + hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + uint32_t port_speed[LINK_SPEED_MAX] = {ETH_SPEED_NUM_10M, + ETH_SPEED_NUM_100M, ETH_SPEED_NUM_1G, + ETH_SPEED_NUM_10G, ETH_SPEED_NUM_25G, + ETH_SPEED_NUM_40G, ETH_SPEED_NUM_100G}; + struct nic_port_info port_info; + struct rte_eth_link link; + int rc = HINIC_OK; + + nic_dev->link_status = status; + if (!status) { + link.link_status = ETH_LINK_DOWN; + link.link_speed = 0; + link.link_duplex = ETH_LINK_HALF_DUPLEX; + link.link_autoneg = ETH_LINK_FIXED; + } else { + link.link_status = ETH_LINK_UP; + + memset(&port_info, 0, sizeof(port_info)); + rc = hinic_get_port_info(nic_dev->hwdev, &port_info); + if (rc) { + link.link_speed = ETH_SPEED_NUM_NONE; + link.link_duplex = ETH_LINK_FULL_DUPLEX; + link.link_autoneg = ETH_LINK_FIXED; + } else { + link.link_speed = port_speed[port_info.speed % + LINK_SPEED_MAX]; + link.link_duplex = port_info.duplex; + link.link_autoneg = port_info.autoneg_state; + } + } + + (void)hinic_dev_atomic_write_link_status(dev, &link); + + return rc; +} + +void hinic_lsc_process(struct rte_eth_dev *rte_dev, u8 status) +{ + int ret; + + ret = hinic_link_event_process(rte_dev, status); + /* check if link has changed, notify callback */ + if (ret == 0) + _rte_eth_dev_callback_process(rte_dev, + RTE_ETH_EVENT_INTR_LSC, + NULL); +} + +static int hinic_set_default_pause_feature(hinic_nic_dev *nic_dev) +{ + struct nic_pause_config pause_config = {0}; + + pause_config.auto_neg = 0; + pause_config.rx_pause = HINIC_DEFAUT_PAUSE_CONFIG; + pause_config.tx_pause = HINIC_DEFAUT_PAUSE_CONFIG; + + return hinic_set_pause_config(nic_dev->hwdev, pause_config); +} + +static int hinic_set_default_dcb_feature(hinic_nic_dev *nic_dev) +{ + u8 up_tc[HINIC_DCB_UP_MAX] = {0}; + u8 up_pgid[HINIC_DCB_UP_MAX] = {0}; + u8 up_bw[HINIC_DCB_UP_MAX] = {0}; + u8 pg_bw[HINIC_DCB_UP_MAX] = {0}; + u8 up_strict[HINIC_DCB_UP_MAX] = {0}; + int i = 0; + + pg_bw[0] = 100; + for (i = 0; i < HINIC_DCB_UP_MAX; i++) + up_bw[i] = 100; + + return hinic_dcb_set_ets(nic_dev->hwdev, up_tc, pg_bw, + up_pgid, up_bw, up_strict); +} + +static void hinic_init_default_cos(hinic_nic_dev *nic_dev) +{ + nic_dev->default_cos = + (hinic_global_func_id(nic_dev->hwdev) + + DEFAULT_BASE_COS) % NR_MAX_COS; +} + +static int hinic_set_default_hw_feature(hinic_nic_dev *nic_dev) +{ + int err; + + hinic_init_default_cos(nic_dev); + + /* Restore DCB configure to default status */ + err = hinic_set_default_dcb_feature(nic_dev); + if (err) + return err; + + /* disable LRO */ + err = hinic_set_rx_lro(nic_dev->hwdev, 0, 0, (u8)0); + if (err) + return err; + + /* Set pause enable, and up will disable pfc. */ + err = hinic_set_default_pause_feature(nic_dev); + if (err) + return err; + + err = hinic_reset_port_link_cfg(nic_dev->hwdev); + if (err) + return err; + + err = hinic_set_link_status_follow(nic_dev->hwdev, + HINIC_LINK_FOLLOW_PORT); + if (err == HINIC_MGMT_CMD_UNSUPPORTED) + PMD_DRV_LOG(WARNING, "Don't support to set link status follow phy port status"); + else if (err) + return err; + + return hinic_set_anti_attack(nic_dev->hwdev, true); +} + +static int32_t hinic_card_workmode_check(hinic_nic_dev *nic_dev) +{ + struct hinic_board_info info = { 0 }; + int rc; + + rc = hinic_get_board_info(nic_dev->hwdev, &info); + if (rc) + return rc; + + /*pf can not run dpdk in ovs mode*/ + return (info.service_mode != HINIC_SERVICE_MODE_OVS ? HINIC_OK : + HINIC_ERROR); +} + +static int hinic_copy_mempool_init(hinic_nic_dev *nic_dev) +{ + nic_dev->cpy_mpool = rte_mempool_lookup(nic_dev->proc_dev_name); + if (nic_dev->cpy_mpool == NULL) { + nic_dev->cpy_mpool = + rte_pktmbuf_pool_create(nic_dev->proc_dev_name, + HINIC_COPY_MEMPOOL_DEPTH, + RTE_CACHE_LINE_SIZE, 0, + HINIC_COPY_MBUF_SIZE, + rte_socket_id()); + if (!nic_dev->cpy_mpool) { + PMD_DRV_LOG(ERR, "Create copy mempool failed, errno: %d, dev_name: %s", + rte_errno, nic_dev->proc_dev_name); + return -ENOMEM; + } + } + + return 0; +} + +static void hinic_copy_mempool_uninit(hinic_nic_dev *nic_dev) +{ + if (nic_dev->cpy_mpool != NULL) + rte_mempool_free(nic_dev->cpy_mpool); +} + +int hinic_init_sw_rxtxqs(hinic_nic_dev *nic_dev) +{ + u32 txq_size; + u32 rxq_size; + + /* allocate software txq array */ + txq_size = nic_dev->nic_cap.max_sqs * sizeof(*nic_dev->txqs); + nic_dev->txqs = kzalloc_aligned(txq_size, GFP_KERNEL); + if (!nic_dev->txqs) { + PMD_DRV_LOG(ERR, "Allocate txqs failed"); + return -ENOMEM; + } + + /* allocate software rxq array */ + rxq_size = nic_dev->nic_cap.max_rqs * sizeof(*nic_dev->rxqs); + nic_dev->rxqs = kzalloc_aligned(rxq_size, GFP_KERNEL); + if (!nic_dev->rxqs) { + /* free txqs */ + kfree(nic_dev->txqs); + nic_dev->txqs = NULL; + + PMD_DRV_LOG(ERR, "Allocate rxqs failed"); + return -ENOMEM; + } + + return HINIC_OK; +} + +void hinic_deinit_sw_rxtxqs(hinic_nic_dev *nic_dev) +{ + kfree(nic_dev->txqs); + nic_dev->txqs = NULL; + + kfree(nic_dev->rxqs); + nic_dev->rxqs = NULL; +} + +int32_t hinic_nic_dev_create(struct rte_eth_dev *eth_dev) +{ + hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev); + int rc; + + nic_dev->hwdev = + (struct hinic_hwdev *)rte_zmalloc("hinic_hwdev", + sizeof(*nic_dev->hwdev), + RTE_CACHE_LINE_SIZE); + if (!nic_dev->hwdev) { + PMD_DRV_LOG(ERR, "Allocate hinic hwdev memory failed, dev_name: %s", + eth_dev->data->name); + return -ENOMEM; + } + + nic_dev->hwdev->pcidev_hdl = + (struct rte_pci_device *)RTE_ETH_DEV_TO_PCI(eth_dev); + nic_dev->hwdev->dev_hdl = nic_dev; + + /* init osdep*/ + rc = hinic_osdep_init(nic_dev); + if (rc) { + PMD_DRV_LOG(ERR, "Initialize os_dep failed, dev_name: %s", + eth_dev->data->name); + goto init_osdep_fail; + } + + /* init_hwif */ + rc = hinic_hwif_res_init(nic_dev); + if (rc) { + PMD_DRV_LOG(ERR, "Initialize hwif failed, dev_name: %s", + eth_dev->data->name); + goto init_hwif_fail; + } + + /* init_cfg_mgmt */ + rc = init_cfg_mgmt(nic_dev->hwdev); + if (rc) { + PMD_DRV_LOG(ERR, "Initialize cfg_mgmt failed, dev_name: %s", + eth_dev->data->name); + goto init_cfgmgnt_fail; + } + + /* init_aeqs */ + rc = hinic_comm_aeqs_init(nic_dev); + if (rc) { + PMD_DRV_LOG(ERR, "Initialize aeqs failed, dev_name: %s", + eth_dev->data->name); + goto init_aeqs_fail; + } + + /* init_pf_to_mgnt */ + rc = hinic_comm_pf_to_mgmt_init(nic_dev); + if (rc) { + PMD_DRV_LOG(ERR, "Initialize pf_to_mgmt failed, dev_name: %s", + eth_dev->data->name); + goto init_pf_to_mgmt_fail; + } + + rc = hinic_card_workmode_check(nic_dev); + if (rc) { + PMD_DRV_LOG(ERR, "Check card workmode failed, dev_name: %s", + eth_dev->data->name); + goto workmode_check_fail; + } + + /* do l2nic reset to make chip clear */ + rc = hinic_l2nic_reset(nic_dev->hwdev); + if (rc) { + PMD_DRV_LOG(ERR, "Do l2nic reset failed, dev_name: %s", + eth_dev->data->name); + goto l2nic_reset_fail; + } + + /* init dma and aeq msix attribute table */ + (void)hinic_init_attr_table(nic_dev->hwdev); + + /* init_cmdqs */ + rc = hinic_comm_cmdqs_init(nic_dev->hwdev); + if (rc) { + PMD_DRV_LOG(ERR, "Initialize cmdq failed, dev_name: %s", + eth_dev->data->name); + goto init_cmdq_fail; + } + + /* set hardware state active */ + rc = hinic_activate_hwdev_state(nic_dev->hwdev); + if (rc) { + PMD_DRV_LOG(ERR, "Initialize resources state failed, dev_name: %s", + eth_dev->data->name); + goto init_resources_state_fail; + } + + /* init_capability */ + rc = hinic_init_capability(nic_dev); + if (rc) { + PMD_DRV_LOG(ERR, "Initialize capability failed, dev_name: %s", + eth_dev->data->name); + goto init_cap_fail; + } + + /* init root cla and function table */ + rc = hinic_init_nicio(nic_dev); + if (rc) { + PMD_DRV_LOG(ERR, "Initialize nic_io failed, dev_name: %s", + eth_dev->data->name); + goto init_nicio_fail; + } + + /* init_software_txrxq */ + rc = hinic_init_sw_rxtxqs(nic_dev); + if (rc) { + PMD_DRV_LOG(ERR, "Initialize sw_rxtxqs failed, dev_name: %s", + eth_dev->data->name); + goto init_sw_rxtxqs_fail; + } + + rc = hinic_copy_mempool_init(nic_dev); + if (rc) { + PMD_DRV_LOG(ERR, "Create copy mempool failed, dev_name: %s", + eth_dev->data->name); + goto init_mpool_fail; + } + + /* set hardware feature to default status */ + rc = hinic_set_default_hw_feature(nic_dev); + if (rc) { + PMD_DRV_LOG(ERR, "Initialize hardware default features failed, dev_name: %s", + eth_dev->data->name); + goto set_default_hw_feature_fail; + } + + return 0; + +set_default_hw_feature_fail: + hinic_copy_mempool_uninit(nic_dev); + +init_mpool_fail: + hinic_deinit_sw_rxtxqs(nic_dev); + +init_sw_rxtxqs_fail: + hinic_deinit_nicio(nic_dev); + +init_nicio_fail: +init_cap_fail: + hinic_deactivate_hwdev_state(nic_dev->hwdev); + +init_resources_state_fail: + hinic_comm_cmdqs_free(nic_dev->hwdev); + +init_cmdq_fail: +l2nic_reset_fail: +workmode_check_fail: + hinic_comm_pf_to_mgmt_free(nic_dev); + +init_pf_to_mgmt_fail: + hinic_comm_aeqs_free(nic_dev); + +init_aeqs_fail: + free_cfg_mgmt(nic_dev->hwdev); + +init_cfgmgnt_fail: + hinic_hwif_res_free(nic_dev); + +init_hwif_fail: + hinic_osdep_deinit(nic_dev); + +init_osdep_fail: + rte_free(nic_dev->hwdev); + nic_dev->hwdev = NULL; + + return rc; +} + +void hinic_nic_dev_destroy(struct rte_eth_dev *rte_dev) +{ + hinic_nic_dev *nic_dev = + HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(rte_dev); + + (void)hinic_set_link_status_follow(nic_dev->hwdev, + HINIC_LINK_FOLLOW_DEFAULT); + hinic_copy_mempool_uninit(nic_dev); + hinic_deinit_sw_rxtxqs(nic_dev); + hinic_deinit_nicio(nic_dev); + hinic_deactivate_hwdev_state(nic_dev->hwdev); + hinic_comm_cmdqs_free(nic_dev->hwdev); + hinic_comm_pf_to_mgmt_free(nic_dev); + hinic_comm_aeqs_free(nic_dev); + free_cfg_mgmt(nic_dev->hwdev); + hinic_hwif_res_free(nic_dev); + hinic_osdep_deinit(nic_dev); + + rte_free(nic_dev->hwdev); + nic_dev->hwdev = NULL; +} diff --git a/drivers/net/hinic/meson.build b/drivers/net/hinic/meson.build new file mode 100644 index 0000000..b054f6b --- /dev/null +++ b/drivers/net/hinic/meson.build @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2017 Huawei Technologies Co., Ltd + +subdir('base') +objs = [base_objs] + +sources = files( + 'hinic_pmd_dpdev.c', + 'hinic_pmd_ethdev.c', + 'hinic_pmd_rx.c', + 'hinic_pmd_tx.c' + ) + +deps += 'ethdev' +deps += 'pci' +deps += 'hash' + +includes += include_directories('base') diff --git a/mk/rte.app.mk b/mk/rte.app.mk index 7c9b4b5..6f189ce 100644 --- a/mk/rte.app.mk +++ b/mk/rte.app.mk @@ -166,6 +166,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_ENETC_PMD) += -lrte_pmd_enetc _LDLIBS-$(CONFIG_RTE_LIBRTE_ENIC_PMD) += -lrte_pmd_enic _LDLIBS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += -lrte_pmd_fm10k _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_FAILSAFE) += -lrte_pmd_failsafe +_LDLIBS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += -lrte_pmd_hinic _LDLIBS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += -lrte_pmd_i40e _LDLIBS-$(CONFIG_RTE_LIBRTE_IAVF_PMD) += -lrte_pmd_iavf _LDLIBS-$(CONFIG_RTE_LIBRTE_ICE_PMD) += -lrte_pmd_ice From patchwork Tue May 21 08:23:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ziyang Xuan X-Patchwork-Id: 53567 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id EC57A5A44; Tue, 21 May 2019 10:13:14 +0200 (CEST) Received: from huawei.com (szxga05-in.huawei.com [45.249.212.191]) by dpdk.org (Postfix) with ESMTP id 8CBA45942 for ; Tue, 21 May 2019 10:13:12 +0200 (CEST) Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id EA92646C94C83B306C93 for ; Tue, 21 May 2019 16:13:10 +0800 (CST) Received: from tester_149.localdomain (10.175.119.39) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.439.0; Tue, 21 May 2019 16:13:02 +0800 From: Ziyang Xuan To: CC: , , , , Ziyang Xuan Date: Tue, 21 May 2019 16:23:49 +0800 Message-ID: <1558427029-187334-1-git-send-email-xuanziyang2@huawei.com> X-Mailer: git-send-email 1.8.3.1 MIME-Version: 1.0 X-Originating-IP: [10.175.119.39] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 09/11] net/hinic: add RX module X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add code for RX module. Signed-off-by: Ziyang Xuan --- drivers/net/hinic/Makefile | 2 +- drivers/net/hinic/hinic_pmd_rx.c | 906 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 907 insertions(+), 1 deletion(-) create mode 100644 drivers/net/hinic/hinic_pmd_rx.c diff --git a/drivers/net/hinic/Makefile b/drivers/net/hinic/Makefile index 9fe4946..50095ac 100644 --- a/drivers/net/hinic/Makefile +++ b/drivers/net/hinic/Makefile @@ -74,7 +74,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_wq.c SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_dpdev.c #SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_ethdev.c -#SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_rx.c +SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_rx.c #SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_tx.c # this lib depends upon: DEPDIRS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += lib/librte_eal lib/librte_ether diff --git a/drivers/net/hinic/hinic_pmd_rx.c b/drivers/net/hinic/hinic_pmd_rx.c new file mode 100644 index 0000000..f03148e --- /dev/null +++ b/drivers/net/hinic/hinic_pmd_rx.c @@ -0,0 +1,906 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Huawei Technologies Co., Ltd + */ + +#include +#include +#include + +#include "hinic_pmd_ethdev.h" +#include "hinic_pmd_rx.h" + +#ifdef HINIC_XSTAT_RXBUF_INFO +static void hinic_rxq_buffer_done_count(struct hinic_rxq *rxq) +{ + u16 sw_ci, avail_pkts = 0, hit_done = 0, cqe_hole = 0; + u32 status; + volatile struct hinic_rq_cqe *rx_cqe; + + for (sw_ci = 0; sw_ci < rxq->q_depth; sw_ci++) { + rx_cqe = &rxq->rx_cqe[sw_ci]; + + /* test current ci is done */ + status = rx_cqe->status; + if (!HINIC_GET_RX_DONE_BE(status)) { + if (hit_done) { + cqe_hole++; + hit_done = 0; + } + continue; + } + + avail_pkts++; + hit_done = 1; + } + + rxq->rxq_stats.rx_avail = avail_pkts; + rxq->rxq_stats.rx_hole = cqe_hole; +} +#endif + +void hinic_rxq_get_stats(struct hinic_rxq *rxq, struct hinic_rxq_stats *stats) +{ + if (!rxq || !stats) + return; + +#ifdef HINIC_XSTAT_RXBUF_INFO + rxq->rxq_stats.rx_mbuf = (rxq->q_depth) + - HINIC_GET_RQ_FREE_WQEBBS(rxq); + + hinic_rxq_buffer_done_count(rxq); +#endif +#ifdef HINIC_XSTAT_MBUF_USE + rxq->rxq_stats.left_mbuf = rxq->rxq_stats.alloc_mbuf + - rxq->rxq_stats.free_mbuf; +#endif + memcpy(stats, &rxq->rxq_stats, sizeof(rxq->rxq_stats)); +} + +void hinic_rxq_stats_reset(struct hinic_rxq *rxq) +{ + struct hinic_rxq_stats *rxq_stats; + + if (rxq == NULL) + return; + + rxq_stats = &rxq->rxq_stats; + memset(rxq_stats, 0, sizeof(*rxq_stats)); +} + +/* mbuf alloc and free */ +static inline struct rte_mbuf *hinic_rte_rxmbuf_alloc(struct rte_mempool *mp) +{ + struct rte_mbuf *m; + + m = rte_mbuf_raw_alloc(mp); + return m; +} + +static int hinic_rx_alloc_cqe(struct hinic_rxq *rxq) +{ + size_t cqe_mem_size; + + /* allocate continuous cqe memory for saving number of memory zone */ + cqe_mem_size = sizeof(struct hinic_rq_cqe) * rxq->q_depth; + rxq->cqe_start_vaddr = dma_zalloc_coherent(rxq->nic_dev, cqe_mem_size, + &rxq->cqe_start_paddr, + GFP_KERNEL); + if (!rxq->cqe_start_vaddr) { + PMD_DRV_LOG(ERR, "Allocate cqe dma memory failed"); + return -ENOMEM; + } + + rxq->rx_cqe = (struct hinic_rq_cqe *)rxq->cqe_start_vaddr; + + return HINIC_OK; +} + +static void hinic_rx_free_cqe(struct hinic_rxq *rxq) +{ + size_t cqe_mem_size; + + cqe_mem_size = sizeof(struct hinic_rq_cqe) * rxq->q_depth; + dma_free_coherent(rxq->nic_dev, cqe_mem_size, + rxq->cqe_start_vaddr, + rxq->cqe_start_paddr); + rxq->cqe_start_vaddr = NULL; +} + +static int hinic_rx_fill_wqe(struct hinic_rxq *rxq) +{ + hinic_nic_dev *nic_dev = rxq->nic_dev; + struct hinic_rq_wqe *rq_wqe; + dma_addr_t buf_dma_addr, cqe_dma_addr; + u16 pi = 0; + int rq_wqe_len; + int i; + + buf_dma_addr = 0; + cqe_dma_addr = rxq->cqe_start_paddr; + for (i = 0; i < rxq->q_depth; i++) { + rq_wqe = (struct hinic_rq_wqe *) + hinic_get_rq_wqe(nic_dev->hwdev, rxq->q_id, &pi); + if (!rq_wqe) { + PMD_DRV_LOG(ERR, "Get rq wqe failed"); + break; + } + + hinic_prepare_rq_wqe(rq_wqe, pi, buf_dma_addr, cqe_dma_addr); + cqe_dma_addr += sizeof(struct hinic_rq_cqe); + + rq_wqe_len = sizeof(struct hinic_rq_wqe); + hinic_cpu_to_be32(rq_wqe, rq_wqe_len); + } + + hinic_return_rq_wqe(nic_dev->hwdev, rxq->q_id, i); + + return i; +} + +/* alloc cqe and prepare rqe */ +int hinic_setup_rx_resources(struct hinic_rxq *rxq) +{ + u64 rx_info_sz; + int err, pkts; + + rx_info_sz = rxq->q_depth * sizeof(*rxq->rx_info); + rxq->rx_info = kzalloc_aligned(rx_info_sz, GFP_KERNEL); + if (!rxq->rx_info) + return -ENOMEM; + + err = hinic_rx_alloc_cqe(rxq); + if (err) { + PMD_DRV_LOG(ERR, "Allocate rx cqe failed"); + goto rx_cqe_err; + } + + pkts = hinic_rx_fill_wqe(rxq); + if (pkts != rxq->q_depth) { + PMD_DRV_LOG(ERR, "Fill rx wqe failed"); + err = -ENOMEM; + goto rx_fill_err; + } + + return 0; + +rx_fill_err: + hinic_rx_free_cqe(rxq); + +rx_cqe_err: + kfree(rxq->rx_info); + rxq->rx_info = NULL; + + return err; +} + +void hinic_free_rx_resources(struct hinic_rxq *rxq) +{ + if (rxq->rx_info == NULL) + return; + + hinic_rx_free_cqe(rxq); + kfree(rxq->rx_info); + rxq->rx_info = NULL; +} + +void hinic_free_all_rx_resources(struct rte_eth_dev *eth_dev) +{ + u16 q_id; + hinic_nic_dev *nic_dev = + (hinic_nic_dev *)HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev); + + for (q_id = 0; q_id < nic_dev->num_rq; q_id++) { + eth_dev->data->rx_queues[q_id] = NULL; + + if (nic_dev->rxqs[q_id] == NULL) + continue; + + hinic_free_all_rx_skbs(nic_dev->rxqs[q_id]); + hinic_free_rx_resources(nic_dev->rxqs[q_id]); + kfree(nic_dev->rxqs[q_id]); + nic_dev->rxqs[q_id] = NULL; + } +} + +void hinic_free_all_rx_mbuf(struct rte_eth_dev *eth_dev) +{ + u16 q_id; + hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev); + + for (q_id = 0; q_id < nic_dev->num_rq; q_id++) + hinic_free_all_rx_skbs(nic_dev->rxqs[q_id]); +} + +static void hinic_recv_jumbo_pkt(struct hinic_rxq *rxq, + struct rte_mbuf *head_skb, + u32 remain_pkt_len) +{ + hinic_nic_dev *nic_dev = rxq->nic_dev; + struct rte_mbuf *cur_mbuf, *rxm = NULL; + struct hinic_rx_info *rx_info; + u16 sw_ci, rx_buf_len = rxq->buf_len; + u32 pkt_len; + + while (remain_pkt_len > 0) { + sw_ci = hinic_get_rq_local_ci(nic_dev->hwdev, rxq->q_id); + rx_info = &rxq->rx_info[sw_ci]; + + hinic_update_rq_local_ci(nic_dev->hwdev, rxq->q_id, 1); + + pkt_len = remain_pkt_len > rx_buf_len ? + rx_buf_len : remain_pkt_len; + remain_pkt_len -= pkt_len; + + cur_mbuf = rx_info->mbuf; + cur_mbuf->data_len = (u16)pkt_len; + cur_mbuf->next = NULL; + + head_skb->pkt_len += cur_mbuf->data_len; + head_skb->nb_segs++; +#ifdef HINIC_XSTAT_MBUF_USE + rxq->rxq_stats.free_mbuf++; +#endif + + if (!rxm) + head_skb->next = cur_mbuf; + else + rxm->next = cur_mbuf; + + rxm = cur_mbuf; + } +} + +static void hinic_rss_deinit(hinic_nic_dev *nic_dev) +{ + u8 prio_tc[HINIC_DCB_UP_MAX] = {0}; + (void)hinic_rss_cfg(nic_dev->hwdev, 0, + nic_dev->rss_tmpl_idx, 0, prio_tc); +} + +static int hinic_rss_key_init(hinic_nic_dev *nic_dev, + struct rte_eth_rss_conf *rss_conf) +{ + u8 default_rss_key[HINIC_RSS_KEY_SIZE] = { + 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, + 0x41, 0x67, 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, + 0xd0, 0xca, 0x2b, 0xcb, 0xae, 0x7b, 0x30, 0xb4, + 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30, 0xf2, 0x0c, + 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa}; + u8 hashkey[HINIC_RSS_KEY_SIZE] = {0}; + u8 tmpl_idx = nic_dev->rss_tmpl_idx; + + if (rss_conf->rss_key == NULL) + memcpy(hashkey, default_rss_key, HINIC_RSS_KEY_SIZE); + else + memcpy(hashkey, rss_conf->rss_key, rss_conf->rss_key_len); + + return hinic_rss_set_template_tbl(nic_dev->hwdev, tmpl_idx, hashkey); +} + +static void hinic_fill_rss_type(struct nic_rss_type *rss_type, + struct rte_eth_rss_conf *rss_conf) +{ + u64 rss_hf = rss_conf->rss_hf; + + rss_type->ipv4 = (rss_hf & (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4)) ? 1 : 0; + rss_type->tcp_ipv4 = (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) ? 1 : 0; + rss_type->ipv6 = (rss_hf & (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6)) ? 1 : 0; + rss_type->ipv6_ext = (rss_hf & ETH_RSS_IPV6_EX) ? 1 : 0; + rss_type->tcp_ipv6 = (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) ? 1 : 0; + rss_type->tcp_ipv6_ext = (rss_hf & ETH_RSS_IPV6_TCP_EX) ? 1 : 0; + rss_type->udp_ipv4 = (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) ? 1 : 0; + rss_type->udp_ipv6 = (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) ? 1 : 0; +} + +static void hinic_fillout_indir_tbl(hinic_nic_dev *nic_dev, u32 *indir) +{ + u8 rss_queue_count = nic_dev->num_rss; + int i = 0, j; + + if (rss_queue_count == 0) { + /* delete q_id from indir tbl */ + for (i = 0; i < HINIC_RSS_INDIR_SIZE; i++) + indir[i] = 0xFF; /* Invalid value in indir tbl */ + } else { + while (i < HINIC_RSS_INDIR_SIZE) + for (j = 0; (j < rss_queue_count) && + (i < HINIC_RSS_INDIR_SIZE); j++) + indir[i++] = nic_dev->rx_queue_list[j]; + } +} + +static int hinic_rss_init(hinic_nic_dev *nic_dev, + __attribute__((unused)) u8 *rq2iq_map, + struct rte_eth_rss_conf *rss_conf) +{ + u32 indir_tbl[HINIC_RSS_INDIR_SIZE] = {0}; + struct nic_rss_type rss_type = {0}; + u8 prio_tc[HINIC_DCB_UP_MAX] = {0}; + u8 tmpl_idx = 0xFF, num_tc = 0; + int err; + + tmpl_idx = nic_dev->rss_tmpl_idx; + + err = hinic_rss_key_init(nic_dev, rss_conf); + if (err) + return err; + + if (!nic_dev->rss_indir_flag) { + hinic_fillout_indir_tbl(nic_dev, indir_tbl); + err = hinic_rss_set_indir_tbl(nic_dev->hwdev, tmpl_idx, + indir_tbl); + if (err) + return err; + } + + hinic_fill_rss_type(&rss_type, rss_conf); + err = hinic_set_rss_type(nic_dev->hwdev, tmpl_idx, rss_type); + if (err) + return err; + + err = hinic_rss_set_hash_engine(nic_dev->hwdev, tmpl_idx, + HINIC_RSS_HASH_ENGINE_TYPE_TOEP); + if (err) + return err; + + return hinic_rss_cfg(nic_dev->hwdev, 1, tmpl_idx, num_tc, prio_tc); +} + +static void hinic_add_rq_to_rx_queue_list(hinic_nic_dev *nic_dev, u16 queue_id) +{ + u8 rss_queue_count = nic_dev->num_rss; + + RTE_ASSERT(rss_queue_count <= (RTE_DIM(nic_dev->rx_queue_list) - 1)); + + nic_dev->rx_queue_list[rss_queue_count] = queue_id; + nic_dev->num_rss++; +} + +/** + * hinic_setup_num_qps - determine num_qps from rss_tmpl_id + * @nic_dev: pointer to the private ethernet device + * Return: 0 on Success, error code otherwise. + **/ +static int hinic_setup_num_qps(hinic_nic_dev *nic_dev) +{ + int err, i; + + if (!(nic_dev->flags & ETH_MQ_RX_RSS_FLAG)) { + nic_dev->flags &= ~ETH_MQ_RX_RSS_FLAG; + nic_dev->num_rss = 0; + if (nic_dev->num_rq > 1) { + /* get rss template id */ + err = hinic_rss_template_alloc(nic_dev->hwdev, + &nic_dev->rss_tmpl_idx); + if (err) { + PMD_DRV_LOG(WARNING, "Alloc rss template failed"); + return err; + } + nic_dev->flags |= ETH_MQ_RX_RSS_FLAG; + for (i = 0; i < nic_dev->num_rq; i++) + hinic_add_rq_to_rx_queue_list(nic_dev, i); + } + } + + return 0; +} + +static void hinic_destroy_num_qps(hinic_nic_dev *nic_dev) +{ + if (nic_dev->flags & ETH_MQ_RX_RSS_FLAG) { + if (hinic_rss_template_free(nic_dev->hwdev, + nic_dev->rss_tmpl_idx)) + PMD_DRV_LOG(WARNING, "Free rss template failed"); + + nic_dev->flags &= ~ETH_MQ_RX_RSS_FLAG; + } +} + +static int hinic_config_mq_rx_rss(hinic_nic_dev *nic_dev, bool on) +{ + int ret = 0; + + if (on) { + ret = hinic_setup_num_qps(nic_dev); + if (ret) + PMD_DRV_LOG(ERR, "Setup num_qps failed"); + } else { + hinic_destroy_num_qps(nic_dev); + } + + return ret; +} + +int hinic_config_mq_mode(struct rte_eth_dev *dev, bool on) +{ + hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + struct rte_eth_conf *dev_conf = &dev->data->dev_conf; + int ret = 0; + + switch (dev_conf->rxmode.mq_mode) { + case ETH_MQ_RX_RSS: + ret = hinic_config_mq_rx_rss(nic_dev, on); + break; + default: + break; + } + + return ret; +} + +int hinic_rx_configure(struct rte_eth_dev *dev) +{ + hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + struct rte_eth_rss_conf rss_conf = + dev->data->dev_conf.rx_adv_conf.rss_conf; + u32 csum_en = 0; + int err; + + if (nic_dev->flags & ETH_MQ_RX_RSS_FLAG) { + if (rss_conf.rss_hf == 0) { + rss_conf.rss_hf = HINIC_RSS_OFFLOAD_ALL; + } else if ((rss_conf.rss_hf & HINIC_RSS_OFFLOAD_ALL) == 0) { + PMD_DRV_LOG(ERR, "Do not support rss offload all"); + goto rss_config_err; + } + + err = hinic_rss_init(nic_dev, NULL, &rss_conf); + if (err) { + PMD_DRV_LOG(ERR, "Init rss failed"); + goto rss_config_err; + } + } + + /* Enable both L3/L4 rx checksum offload */ + if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_CHECKSUM) + csum_en = HINIC_RX_CSUM_OFFLOAD_EN; + + err = hinic_set_rx_csum_offload(nic_dev->hwdev, csum_en); + if (err) + goto rx_csum_ofl_err; + + return 0; + +rx_csum_ofl_err: +rss_config_err: + hinic_destroy_num_qps(nic_dev); + + return HINIC_ERROR; +} + +void hinic_rx_remove_configure(struct rte_eth_dev *dev) +{ + hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + + if (nic_dev->flags & ETH_MQ_RX_RSS_FLAG) { + hinic_rss_deinit(nic_dev); + hinic_destroy_num_qps(nic_dev); + } +} + +void hinic_free_all_rx_skbs(struct hinic_rxq *rxq) +{ + hinic_nic_dev *nic_dev = (hinic_nic_dev *)rxq->nic_dev; + struct hinic_rx_info *rx_info; + int free_wqebbs = + hinic_get_rq_free_wqebbs(nic_dev->hwdev, rxq->q_id) + 1; + volatile struct hinic_rq_cqe *rx_cqe; + u16 ci; + + while (free_wqebbs++ < rxq->q_depth) { + ci = hinic_get_rq_local_ci(nic_dev->hwdev, rxq->q_id); + + rx_cqe = &rxq->rx_cqe[ci]; + + /* clear done bit */ + rx_cqe->status = 0; + + rx_info = &rxq->rx_info[ci]; +#ifdef HINIC_XSTAT_MBUF_USE + hinic_rx_free_mbuf(rxq, rx_info->mbuf); +#else + hinic_rx_free_mbuf(rx_info->mbuf); +#endif + rx_info->mbuf = NULL; + + hinic_update_rq_local_ci(nic_dev->hwdev, rxq->q_id, 1); + } +} + +static inline struct hinic_rq_wqe *hinic_get_rearm_rq_wqe(struct hinic_rxq *rxq, + u16 *prod_idx) +{ + u32 cur_pi; + struct hinic_wq *wq = rxq->wq; + + /* record current pi */ + cur_pi = MASKED_WQE_IDX(wq, wq->prod_idx); + + /* update next pi and delta */ + wq->prod_idx += 1; + wq->delta -= 1; + + /* return current pi */ + *prod_idx = cur_pi; + return (struct hinic_rq_wqe *)WQ_WQE_ADDR(wq, cur_pi); +} + +/* performance: byteorder swap m128i */ +static inline void hinic_rq_cqe_be_to_cpu32(void *dst_le32, + volatile void *src_be32) +{ + volatile __m128i *wqe_be = (volatile __m128i *)src_be32; + __m128i *wqe_le = (__m128i *)dst_le32; + __m128i shuf_mask = _mm_set_epi8(12, 13, 14, 15, 8, 9, 10, + 11, 4, 5, 6, 7, 0, 1, 2, 3); + + /* swap 32B CQE using 2 128 bits instructions */ + wqe_le[0] = _mm_shuffle_epi8(wqe_be[0], shuf_mask); +} + +static inline uint64_t hinic_rx_rss_hash(uint32_t offload_type, + uint32_t cqe_hass_val, + uint32_t *rss_hash) +{ + uint32_t rss_type; + + rss_type = HINIC_GET_RSS_TYPES(offload_type); + if (likely(rss_type != 0)) { + *rss_hash = cqe_hass_val; + return PKT_RX_RSS_HASH; + } + + return 0; +} + +static inline uint64_t hinic_rx_csum(uint32_t status, struct hinic_rxq *rxq) +{ + uint32_t checksum_err; + uint64_t flags; + + /* most case checksum is ok */ + checksum_err = HINIC_GET_RX_CSUM_ERR(status); + if (likely(checksum_err == 0)) + return (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD); + + /* If BYPASS bit set, all other status indications should be ignored */ + if (unlikely(HINIC_CSUM_ERR_BYPASSED(checksum_err))) + return PKT_RX_IP_CKSUM_UNKNOWN; + + flags = 0; + + /* IP checksum error */ + if (HINIC_CSUM_ERR_IP(checksum_err)) + flags |= PKT_RX_IP_CKSUM_BAD; + else + flags |= PKT_RX_IP_CKSUM_GOOD; + + /* L4 checksum error */ + if (HINIC_CSUM_ERR_L4(checksum_err)) + flags |= PKT_RX_L4_CKSUM_BAD; + else + flags |= PKT_RX_L4_CKSUM_GOOD; + + if (unlikely(HINIC_CSUM_ERR_OTHER(checksum_err))) + flags = PKT_RX_L4_CKSUM_NONE; + + rxq->rxq_stats.errors++; + + return flags; +} + +static inline uint64_t hinic_rx_vlan(uint32_t offload_type, uint32_t vlan_len, + uint16_t *vlan_tci) +{ + uint16_t vlan_tag; + + vlan_tag = HINIC_GET_RX_VLAN_TAG(vlan_len); + if (!HINIC_GET_RX_VLAN_OFFLOAD_EN(offload_type) || 0 == vlan_tag) { + *vlan_tci = 0; + return 0; + } + + *vlan_tci = vlan_tag; + + return PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED; +} + +static inline uint64_t hinic_rx_pkt_type(uint32_t offload_type) +{ + uint32_t pkt_type, pkt_idx; + static const uint32_t pkt_type_table[RQ_CQE_PKT_TYPES_L2_MASK + 1] + __rte_cache_aligned = { + [3] = RTE_PTYPE_L3_IPV4, + [4] = RTE_PTYPE_L3_IPV4_EXT, + [5] = RTE_PTYPE_L4_FRAG, + [7] = RTE_PTYPE_L3_IPV6, + [9] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_SCTP, + [10] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP, + [11] = RTE_PTYPE_TUNNEL_VXLAN, + [13] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP, + [14] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP, + [15] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP, + [16] = RTE_PTYPE_TUNNEL_NVGRE, + [65] = RTE_PTYPE_L4_ICMP, + [66] = RTE_PTYPE_L4_ICMP, + [76] = RTE_PTYPE_L2_ETHER_LLDP, + [81] = RTE_PTYPE_L2_ETHER_ARP, + /* All others reserved */ + }; + pkt_idx = HINIC_GET_PKT_TYPES(offload_type); + + /* Unknown type */ + if (unlikely(pkt_idx == 0)) + return RTE_PTYPE_UNKNOWN; + + /* if hardware report index not correct set l2 ether as default */ + pkt_type = RTE_PTYPE_L2_ETHER; + pkt_type |= pkt_type_table[HINIC_PKT_TYPES_L2(pkt_idx)]; + + return pkt_type; +} + +static inline u32 hinic_rx_alloc_mbuf_bulk(struct hinic_rxq *rxq, + struct rte_mbuf **mbufs, + u32 exp_mbuf_cnt) +{ + int rc; + u32 avail_cnt; + + rc = rte_pktmbuf_alloc_bulk(rxq->mb_pool, mbufs, exp_mbuf_cnt); + if (likely(rc == HINIC_OK)) { + avail_cnt = exp_mbuf_cnt; + } else { + avail_cnt = 0; + rxq->rxq_stats.rx_nombuf += exp_mbuf_cnt; + } +#ifdef HINIC_XSTAT_MBUF_USE + rxq->rxq_stats.alloc_mbuf += avail_cnt; +#endif + return avail_cnt; +} + +#ifdef HINIC_XSTAT_MBUF_USE +void hinic_rx_free_mbuf(struct hinic_rxq *rxq, struct rte_mbuf *m) +{ + rte_pktmbuf_free(m); + rxq->rxq_stats.free_mbuf++; +} +#else +void hinic_rx_free_mbuf(struct rte_mbuf *m) +{ + rte_pktmbuf_free(m); +} +#endif + +static struct rte_mbuf *hinic_rx_alloc_mbuf(struct hinic_rxq *rxq, + dma_addr_t *dma_addr) +{ + struct rte_mbuf *mbuf; + + mbuf = hinic_rte_rxmbuf_alloc(rxq->mb_pool); + if (unlikely(!mbuf)) + return NULL; + + *dma_addr = rte_mbuf_data_iova_default(mbuf); + +#ifdef HINIC_XSTAT_MBUF_USE + rxq->rxq_stats.alloc_mbuf++; +#endif + + return mbuf; +} + +static inline void hinic_rearm_rxq_mbuf(struct hinic_rxq *rxq) +{ + u16 pi; + u32 i, free_wqebbs, rearm_wqebbs, exp_wqebbs; + dma_addr_t dma_addr; + struct hinic_rq_wqe *rq_wqe; + struct rte_mbuf **rearm_mbufs; + + /* check free wqebb fo rearm */ + free_wqebbs = HINIC_GET_RQ_FREE_WQEBBS(rxq); + if (unlikely(free_wqebbs < rxq->rx_free_thresh)) + return; + + /* get rearm mbuf array */ + pi = HINIC_GET_RQ_LOCAL_PI(rxq); + rearm_mbufs = (struct rte_mbuf **)(&rxq->rx_info[pi]); + + /* check rxq free wqebbs turn around */ + if (unlikely(pi > rxq->rxinfo_align_end)) + exp_wqebbs = rxq->q_depth - pi; + else + exp_wqebbs = rxq->rx_free_thresh; + + /* alloc mbuf in bulk */ + rearm_wqebbs = hinic_rx_alloc_mbuf_bulk(rxq, rearm_mbufs, exp_wqebbs); + if (unlikely(rearm_wqebbs == 0)) + return; + + /* rearm rx mbuf */ + rq_wqe = (struct hinic_rq_wqe *)WQ_WQE_ADDR(rxq->wq, (u32)pi); + for (i = 0; i < rearm_wqebbs; i++) { + dma_addr = rte_mbuf_data_iova_default(rearm_mbufs[i]); + rq_wqe->buf_desc.addr_high = + cpu_to_be32(upper_32_bits(dma_addr)); + rq_wqe->buf_desc.addr_low = + cpu_to_be32(lower_32_bits(dma_addr)); + rq_wqe++; + } + rxq->wq->prod_idx += rearm_wqebbs; + rxq->wq->delta -= rearm_wqebbs; + + /* update rq hw_pi */ + rte_wmb(); + HINIC_UPDATE_RQ_HW_PI(rxq, pi + rearm_wqebbs); +} + +void hinic_rx_alloc_pkts(struct hinic_rxq *rxq) +{ + hinic_nic_dev *nic_dev = rxq->nic_dev; + struct hinic_rq_wqe *rq_wqe; + struct hinic_rx_info *rx_info; + struct rte_mbuf *mb; + dma_addr_t dma_addr; + u16 pi = 0; + int i, free_wqebbs; + + free_wqebbs = HINIC_GET_RQ_FREE_WQEBBS(rxq); + for (i = 0; i < free_wqebbs; i++) { + mb = hinic_rx_alloc_mbuf(rxq, &dma_addr); + if (unlikely(!mb)) { + rxq->rxq_stats.rx_nombuf++; + break; + } + + rq_wqe = (struct hinic_rq_wqe *) + hinic_get_rq_wqe(nic_dev->hwdev, rxq->q_id, &pi); + if (unlikely(!rq_wqe)) { +#ifdef HINIC_XSTAT_MBUF_USE + hinic_rx_free_mbuf(rxq, mb); +#else + hinic_rx_free_mbuf(mb); +#endif + break; + } + + /* fill buffer address only */ + rq_wqe->buf_desc.addr_high = + cpu_to_be32(upper_32_bits(dma_addr)); + rq_wqe->buf_desc.addr_low = + cpu_to_be32(lower_32_bits(dma_addr)); + + rx_info = &rxq->rx_info[pi]; + rx_info->mbuf = mb; + } + + if (likely(i > 0)) { + rte_wmb(); + HINIC_UPDATE_RQ_HW_PI(rxq, pi + 1); + } +} + +u16 hinic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, u16 nb_pkts) +{ + struct rte_mbuf *rxm; + struct hinic_rxq *rxq = (struct hinic_rxq *)rx_queue; + struct hinic_rx_info *rx_info; + volatile struct hinic_rq_cqe *rx_cqe; + u16 rx_buf_len, pkts = 0; + u16 sw_ci, ci_mask, wqebb_cnt = 0; + u32 pkt_len, status, vlan_len; + u64 rx_bytes = 0; +#ifdef HINIC_XSTAT_PROF_RX + uint64_t t1 = rte_get_tsc_cycles(); + uint64_t t2; +#endif + struct hinic_rq_cqe cqe; + u32 offload_type, rss_hash; + + rx_buf_len = rxq->buf_len; + + /* 1. get polling start ci */ + ci_mask = HINIC_GET_RQ_WQE_MASK(rxq); + sw_ci = HINIC_GET_RQ_LOCAL_CI(rxq); + + while (pkts < nb_pkts) { + /* 2. current ci is done */ + rx_cqe = &rxq->rx_cqe[sw_ci]; + status = rx_cqe->status; + if (!HINIC_GET_RX_DONE_BE(status)) + break; + + /* read other cqe member after status */ + rte_rmb(); + + /* convert cqe and get packet length */ + hinic_rq_cqe_be_to_cpu32(&cqe, (volatile void *)rx_cqe); + vlan_len = cqe.vlan_len; + + rx_info = &rxq->rx_info[sw_ci]; + rxm = rx_info->mbuf; + + /* 3. next ci point and prefetch */ + sw_ci++; + sw_ci &= ci_mask; + + /* prefetch next mbuf first 64B */ + rte_prefetch0(rxq->rx_info[sw_ci].mbuf); + + /* 4. jumbo frame process */ + pkt_len = HINIC_GET_RX_PKT_LEN(vlan_len); + if (likely(pkt_len <= rx_buf_len)) { + rxm->data_len = pkt_len; + rxm->pkt_len = pkt_len; + wqebb_cnt++; + } else { + rxm->data_len = rx_buf_len; + rxm->pkt_len = rx_buf_len; + + /* if jumbo use multi-wqebb update ci, + * recv_jumbo_pkt will also update ci + */ + HINIC_UPDATE_RQ_LOCAL_CI(rxq, wqebb_cnt + 1); + wqebb_cnt = 0; + hinic_recv_jumbo_pkt(rxq, rxm, pkt_len - rx_buf_len); + sw_ci = HINIC_GET_RQ_LOCAL_CI(rxq); + } + + /* 5. vlan/checksum/rss/pkt_type/gro offload */ + rxm->data_off = RTE_PKTMBUF_HEADROOM; + rxm->port = rxq->port_id; + offload_type = cqe.offload_type; + + /* vlan offload */ + rxm->ol_flags |= hinic_rx_vlan(offload_type, vlan_len, + &rxm->vlan_tci); + + /* checksum offload */ + rxm->ol_flags |= hinic_rx_csum(cqe.status, rxq); + + /* rss hash offload */ + rss_hash = cqe.rss_hash; + rxm->ol_flags |= hinic_rx_rss_hash(offload_type, rss_hash, + &rxm->hash.rss); + + /* packet type parser offload */ + rxm->packet_type = hinic_rx_pkt_type(offload_type); + + /* 6. clear done bit */ + rx_cqe->status = 0; + + rx_bytes += pkt_len; + rx_pkts[pkts++] = rxm; + } + + if (pkts) { + /* 7. update ci */ + HINIC_UPDATE_RQ_LOCAL_CI(rxq, wqebb_cnt); + + /* do packet stats */ + rxq->rxq_stats.packets += pkts; + rxq->rxq_stats.bytes += rx_bytes; +#ifdef HINIC_XSTAT_MBUF_USE + rxq->rxq_stats.free_mbuf += pkts; +#endif + } + +#ifdef HINIC_XSTAT_RXBUF_INFO + rxq->rxq_stats.burst_pkts = pkts; +#endif + + /* 8. rearm mbuf to rxq */ + hinic_rearm_rxq_mbuf(rxq); + +#ifdef HINIC_XSTAT_PROF_RX + /* do profiling stats */ + t2 = rte_get_tsc_cycles(); + rxq->rxq_stats.app_tsc = t1 - rxq->prof_rx_end_tsc; + rxq->prof_rx_end_tsc = t2; + rxq->rxq_stats.pmd_tsc = t2 - t1; +#endif + + return pkts; +} From patchwork Tue May 21 08:24:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ziyang Xuan X-Patchwork-Id: 53568 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 977F458EC; Tue, 21 May 2019 10:13:39 +0200 (CEST) Received: from huawei.com (szxga07-in.huawei.com [45.249.212.35]) by dpdk.org (Postfix) with ESMTP id 8433A4CA7 for ; Tue, 21 May 2019 10:13:37 +0200 (CEST) Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 38F51F286D68D48AC205 for ; Tue, 21 May 2019 16:13:36 +0800 (CST) Received: from tester_149.localdomain (10.175.119.39) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.439.0; Tue, 21 May 2019 16:13:28 +0800 From: Ziyang Xuan To: CC: , , , , Ziyang Xuan Date: Tue, 21 May 2019 16:24:14 +0800 Message-ID: <1558427054-187378-1-git-send-email-xuanziyang2@huawei.com> X-Mailer: git-send-email 1.8.3.1 MIME-Version: 1.0 X-Originating-IP: [10.175.119.39] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 10/11] net/hinic: add TX module X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add code for TX module Signed-off-by: Ziyang Xuan --- drivers/net/hinic/Makefile | 2 +- drivers/net/hinic/hinic_pmd_tx.c | 1036 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 1037 insertions(+), 1 deletion(-) create mode 100644 drivers/net/hinic/hinic_pmd_tx.c diff --git a/drivers/net/hinic/Makefile b/drivers/net/hinic/Makefile index 50095ac..6fabf5e 100644 --- a/drivers/net/hinic/Makefile +++ b/drivers/net/hinic/Makefile @@ -75,7 +75,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_wq.c SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_dpdev.c #SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_ethdev.c SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_rx.c -#SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_tx.c +SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_tx.c # this lib depends upon: DEPDIRS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += lib/librte_eal lib/librte_ether DEPDIRS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += lib/librte_mempool lib/librte_mbuf diff --git a/drivers/net/hinic/hinic_pmd_tx.c b/drivers/net/hinic/hinic_pmd_tx.c new file mode 100644 index 0000000..1f1659f --- /dev/null +++ b/drivers/net/hinic/hinic_pmd_tx.c @@ -0,0 +1,1036 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Huawei Technologies Co., Ltd + */ + +#include +#include +#include +#include +#include + +#include "hinic_pmd_ethdev.h" +#include "hinic_pmd_tx.h" + +/* packet header and tx offload info */ +#define VXLANLEN (8) +#define MAX_PLD_OFFSET (221) +#define MAX_SINGLE_SGE_SIZE (65536) +#define TSO_ENABLE (1) + +#define HINIC_NONTSO_PKT_MAX_SGE (17) /* non-tso max sge 17 */ +#define HINIC_NONTSO_SEG_NUM_INVALID(num) ((num) > HINIC_NONTSO_PKT_MAX_SGE) + +#define HINIC_TSO_PKT_MAX_SGE (127) /* tso max sge 127 */ +#define HINIC_TSO_SEG_NUM_INVALID(num) ((num) > HINIC_TSO_PKT_MAX_SGE) + +#define HINIC_TX_CKSUM_OFFLOAD_MASK ( \ + PKT_TX_IP_CKSUM | \ + PKT_TX_TCP_CKSUM | \ + PKT_TX_UDP_CKSUM | \ + PKT_TX_SCTP_CKSUM | \ + PKT_TX_OUTER_IP_CKSUM | \ + PKT_TX_TCP_SEG) + +/* sizeof(struct hinic_sq_bufdesc) == 16, shift 4 */ +#define HINIC_BUF_DESC_SIZE(nr_descs) \ + (SIZE_8BYTES(((u32)nr_descs) << 4)) + +/* tx offload info */ +struct hinic_tx_offload_info { + u8 outer_l2_len; + u8 outer_l3_type; + u8 outer_l3_len; + + u8 inner_l2_len; + u8 inner_l3_type; + u8 inner_l3_len; + + u8 tunnel_length; + u8 tunnel_type; + u8 inner_l4_type; + u8 inner_l4_len; + + u8 payload_offset; + u8 inner_l4_tcp_udp; +}; + +/* tx sge info */ +struct hinic_wqe_info { + u16 pi; + u16 owner; + u16 around; + u16 seq_wqebbs; + u16 sge_cnt; + u16 cpy_mbuf_cnt; +}; + +/* performance: byteorder swap m128i */ +static inline void hinic_sq_wqe_cpu_to_be32(void *data, int nr_wqebb) +{ + int i; + __m128i *wqe_line = (__m128i *)data; + __m128i shuf_mask = _mm_set_epi8(12, 13, 14, 15, 8, 9, 10, + 11, 4, 5, 6, 7, 0, 1, 2, 3); + + for (i = 0; i < nr_wqebb; i++) { + /* convert 64B wqebb using 4 SSE instructions */ + wqe_line[0] = _mm_shuffle_epi8(wqe_line[0], shuf_mask); + wqe_line[1] = _mm_shuffle_epi8(wqe_line[1], shuf_mask); + wqe_line[2] = _mm_shuffle_epi8(wqe_line[2], shuf_mask); + wqe_line[3] = _mm_shuffle_epi8(wqe_line[3], shuf_mask); + wqe_line += 4; + } +} + +static inline void hinic_sge_cpu_to_be32(void *data, int nr_sge) +{ + int i; + __m128i *sge_line = (__m128i *)data; + __m128i shuf_mask = _mm_set_epi8(12, 13, 14, 15, 8, 9, 10, + 11, 4, 5, 6, 7, 0, 1, 2, 3); + + for (i = 0; i < nr_sge; i++) { + /* convert 16B sge using 1 SSE instructions */ + *sge_line = _mm_shuffle_epi8(*sge_line, shuf_mask); + sge_line++; + } +} + +void hinic_txq_get_stats(struct hinic_txq *txq, struct hinic_txq_stats *stats) +{ + if (!txq || !stats) { + PMD_DRV_LOG(ERR, "Txq or stats is NULL"); + return; + } + + memcpy(stats, &txq->txq_stats, sizeof(txq->txq_stats)); +} + +void hinic_txq_stats_reset(struct hinic_txq *txq) +{ + struct hinic_txq_stats *txq_stats; + + if (txq == NULL) + return; + + txq_stats = &txq->txq_stats; + memset(txq_stats, 0, sizeof(*txq_stats)); +} + +static inline struct rte_mbuf *hinic_copy_tx_mbuf(hinic_nic_dev *nic_dev, + struct rte_mbuf *mbuf, + u16 sge_cnt) +{ + struct rte_mbuf *dst_mbuf; + u32 offset = 0; + u16 i; + + if (unlikely(!nic_dev->cpy_mpool)) + return NULL; + + dst_mbuf = rte_pktmbuf_alloc(nic_dev->cpy_mpool); + if (unlikely(!dst_mbuf)) + return NULL; + + dst_mbuf->data_off = 0; + for (i = 0; i < sge_cnt; i++) { + rte_memcpy((char *)dst_mbuf->buf_addr + offset, + (char *)mbuf->buf_addr + mbuf->data_off, + mbuf->data_len); + dst_mbuf->data_len += mbuf->data_len; + offset += mbuf->data_len; + mbuf = mbuf->next; + } + + return dst_mbuf; +} + +static inline bool hinic_mbuf_dma_map_sge(struct hinic_txq *txq, + struct rte_mbuf *mbuf, + struct hinic_sq_bufdesc *sges, + struct hinic_wqe_info *sqe_info) +{ + dma_addr_t dma_addr; + u16 i, around_sges; + u16 nb_segs = sqe_info->sge_cnt - sqe_info->cpy_mbuf_cnt; + u16 real_nb_segs = mbuf->nb_segs; + struct hinic_sq_bufdesc *sge_idx = sges; + + if (unlikely(sqe_info->around)) { + /* parts of wqe is in sq bottom while parts + * of wqe is in sq head + */ + i = 0; + for (sge_idx = sges; (u64)sge_idx <= txq->sq_bot_sge_addr; + sge_idx++) { + dma_addr = rte_mbuf_data_iova(mbuf); + hinic_set_sge((struct hinic_sge *)sge_idx, dma_addr, + mbuf->data_len); + mbuf = mbuf->next; + i++; + } + + around_sges = nb_segs - i; + sge_idx = (struct hinic_sq_bufdesc *) + ((void *)txq->sq_head_addr); + for (; i < nb_segs; i++) { + dma_addr = rte_mbuf_data_iova(mbuf); + hinic_set_sge((struct hinic_sge *)sge_idx, dma_addr, + mbuf->data_len); + mbuf = mbuf->next; + sge_idx++; + } + + /* covert sges at head to big endian */ + hinic_sge_cpu_to_be32((void *)txq->sq_head_addr, around_sges); + } else { + /* wqe is in continuous space */ + for (i = 0; i < nb_segs; i++) { + dma_addr = rte_mbuf_data_iova(mbuf); + hinic_set_sge((struct hinic_sge *)sge_idx, dma_addr, + mbuf->data_len); + mbuf = mbuf->next; + sge_idx++; + } + } + + /* for now: support non-tso over 17 sge, copy the last 2 mbuf */ + if (unlikely(sqe_info->cpy_mbuf_cnt != 0)) { + /* copy invalid mbuf segs to a valid buffer, lost performance */ + txq->txq_stats.cpy_pkts += 1; + mbuf = hinic_copy_tx_mbuf(txq->nic_dev, mbuf, + real_nb_segs - nb_segs); + if (unlikely(!mbuf)) + return false; + + txq->tx_info[sqe_info->pi].cpy_mbuf = mbuf; + + /* deal with the last mbuf */ + dma_addr = rte_mbuf_data_iova(mbuf); + hinic_set_sge((struct hinic_sge *)sge_idx, dma_addr, + mbuf->data_len); + if (unlikely(sqe_info->around)) + hinic_sge_cpu_to_be32((void *)sge_idx, 1); + } + + return true; +} + +static inline void hinic_fill_sq_wqe_header(struct hinic_sq_ctrl *ctrl, + u32 queue_info, int nr_descs, + u8 owner) +{ + u32 ctrl_size, task_size, bufdesc_size; + + ctrl_size = SIZE_8BYTES(sizeof(struct hinic_sq_ctrl)); + task_size = SIZE_8BYTES(sizeof(struct hinic_sq_task)); + bufdesc_size = HINIC_BUF_DESC_SIZE(nr_descs); + + ctrl->ctrl_fmt = SQ_CTRL_SET(bufdesc_size, BUFDESC_SECT_LEN) | + SQ_CTRL_SET(task_size, TASKSECT_LEN) | + SQ_CTRL_SET(SQ_NORMAL_WQE, DATA_FORMAT) | + SQ_CTRL_SET(ctrl_size, LEN) | + SQ_CTRL_SET(owner, OWNER); + + ctrl->queue_info = queue_info; + ctrl->queue_info |= SQ_CTRL_QUEUE_INFO_SET(1U, UC); + + if (!SQ_CTRL_QUEUE_INFO_GET(ctrl->queue_info, MSS)) { + ctrl->queue_info |= + SQ_CTRL_QUEUE_INFO_SET(TX_MSS_DEFAULT, MSS); + } else if (SQ_CTRL_QUEUE_INFO_GET(ctrl->queue_info, MSS) < TX_MSS_MIN) { + /* mss should not be less than 80 */ + ctrl->queue_info = + SQ_CTRL_QUEUE_INFO_CLEAR(ctrl->queue_info, MSS); + ctrl->queue_info |= SQ_CTRL_QUEUE_INFO_SET(TX_MSS_MIN, MSS); + } +} + +static inline bool hinic_is_tso_sge_valid(struct rte_mbuf *mbuf, + struct hinic_tx_offload_info + *poff_info, + struct hinic_wqe_info *sqe_info) +{ + u32 total_len, limit_len, checked_len, left_len; + u32 i, first_mss_sges, left_sges; + struct rte_mbuf *mbuf_head, *mbuf_pre; + + left_sges = mbuf->nb_segs; + mbuf_head = mbuf; + + /* tso sge number validation */ + if (unlikely(left_sges >= HINIC_NONTSO_PKT_MAX_SGE)) { + checked_len = 0; + limit_len = mbuf->tso_segsz + poff_info->payload_offset; + first_mss_sges = HINIC_NONTSO_PKT_MAX_SGE; + + /* each continues 17 mbufs segmust do one check */ + while (left_sges >= HINIC_NONTSO_PKT_MAX_SGE) { + /* total len of first 16 mbufs must equal + * or more than limit_len + */ + total_len = 0; + for (i = 0; i < first_mss_sges; i++) { + total_len += mbuf->data_len; + mbuf_pre = mbuf; + mbuf = mbuf->next; + if (total_len >= limit_len) { + limit_len = mbuf_head->tso_segsz; + break; + } + } + + checked_len += total_len; + + /* try to copy if not valid */ + if (unlikely(first_mss_sges == i)) { + left_sges -= first_mss_sges; + checked_len -= mbuf_pre->data_len; + + left_len = mbuf_head->pkt_len - checked_len; + if (left_len > HINIC_COPY_MBUF_SIZE) + return false; + + sqe_info->sge_cnt = mbuf_head->nb_segs - + left_sges; + sqe_info->cpy_mbuf_cnt = 1; + + return true; + } + first_mss_sges = (HINIC_NONTSO_PKT_MAX_SGE - 1); + + /* continue next 16 mbufs */ + left_sges -= (i + 1); + } /* end of while */ + } + + sqe_info->sge_cnt = mbuf_head->nb_segs; + return true; +} + +static inline void +hinic_set_l4_csum_info(struct hinic_sq_task *task, + u32 *queue_info, struct hinic_tx_offload_info *poff_info) +{ + u32 tcp_udp_cs, sctp; + u16 l2hdr_len; + + sctp = 0; + if (unlikely(poff_info->inner_l4_type == SCTP_OFFLOAD_ENABLE)) + sctp = 1; + + tcp_udp_cs = poff_info->inner_l4_tcp_udp; + + if (poff_info->tunnel_type == TUNNEL_UDP_NO_CSUM) { + l2hdr_len = poff_info->outer_l2_len; + + task->pkt_info2 |= + SQ_TASK_INFO2_SET(poff_info->outer_l3_type, OUTER_L3TYPE) | + SQ_TASK_INFO2_SET(poff_info->outer_l3_len, OUTER_L3LEN); + task->pkt_info2 |= + SQ_TASK_INFO2_SET(poff_info->tunnel_type, TUNNEL_L4TYPE) | + SQ_TASK_INFO2_SET(poff_info->tunnel_length, TUNNEL_L4LEN); + } else { + l2hdr_len = poff_info->inner_l2_len; + } + + task->pkt_info0 |= SQ_TASK_INFO0_SET(l2hdr_len, L2HDR_LEN); + task->pkt_info1 |= + SQ_TASK_INFO1_SET(poff_info->inner_l3_len, INNER_L3LEN); + task->pkt_info0 |= + SQ_TASK_INFO0_SET(poff_info->inner_l3_type, INNER_L3TYPE); + task->pkt_info1 |= + SQ_TASK_INFO1_SET(poff_info->inner_l4_len, INNER_L4LEN); + task->pkt_info0 |= + SQ_TASK_INFO0_SET(poff_info->inner_l4_type, L4OFFLOAD); + *queue_info |= + SQ_CTRL_QUEUE_INFO_SET(poff_info->payload_offset, PLDOFF) | + SQ_CTRL_QUEUE_INFO_SET(tcp_udp_cs, TCPUDP_CS) | + SQ_CTRL_QUEUE_INFO_SET(sctp, SCTP); +} + +static inline void +hinic_set_tso_info(struct hinic_sq_task *task, + u32 *queue_info, struct rte_mbuf *mbuf, + struct hinic_tx_offload_info *poff_info) +{ + hinic_set_l4_csum_info(task, queue_info, poff_info); + + /* wqe for tso */ + task->pkt_info0 |= + SQ_TASK_INFO0_SET(poff_info->inner_l3_type, INNER_L3TYPE); + task->pkt_info0 |= SQ_TASK_INFO0_SET(TSO_ENABLE, TSO_UFO); + *queue_info |= SQ_CTRL_QUEUE_INFO_SET(TSO_ENABLE, TSO); + /* qsf was initialized in prepare_sq_wqe */ + *queue_info = SQ_CTRL_QUEUE_INFO_CLEAR(*queue_info, MSS); + *queue_info |= SQ_CTRL_QUEUE_INFO_SET(mbuf->tso_segsz, MSS); +} + +static inline void +hinic_set_vlan_tx_offload(struct hinic_sq_task *task, + u32 *queue_info, u16 vlan_tag, u16 vlan_pri) +{ + task->pkt_info0 |= SQ_TASK_INFO0_SET(vlan_tag, VLAN_TAG) | + SQ_TASK_INFO0_SET(1U, VLAN_OFFLOAD); + + *queue_info |= SQ_CTRL_QUEUE_INFO_SET(vlan_pri, PRI); +} + +static inline void +hinic_fill_tx_offload_info(struct rte_mbuf *mbuf, + struct hinic_sq_task *task, u32 *queue_info, + struct hinic_tx_offload_info *tx_off_info) +{ + u16 vlan_tag; + uint64_t ol_flags = mbuf->ol_flags; + + /* clear DW0~2 of task section for offload */ + task->pkt_info0 = 0; + task->pkt_info1 = 0; + task->pkt_info2 = 0; + + /* Base VLAN */ + if (unlikely(ol_flags & PKT_TX_VLAN_PKT)) { + vlan_tag = mbuf->vlan_tci; + hinic_set_vlan_tx_offload(task, queue_info, vlan_tag, + vlan_tag >> VLAN_PRIO_SHIFT); + } + + /* non checksum or tso */ + if (unlikely(!(ol_flags & HINIC_TX_CKSUM_OFFLOAD_MASK))) + return; + + if ((ol_flags & PKT_TX_TCP_SEG)) + /* set tso info for task and qsf */ + hinic_set_tso_info(task, queue_info, mbuf, tx_off_info); + else /* just support l4 checksum offload */ + hinic_set_l4_csum_info(task, queue_info, tx_off_info); +} + +static inline void hinic_xmit_mbuf_cleanup(struct hinic_txq *txq) +{ + struct hinic_tx_info *tx_info; + struct rte_mbuf *mbuf, *m, *mbuf_free[HINIC_MAX_TX_FREE_BULK]; + int i, nb_free = 0; + u16 hw_ci, sw_ci, sq_mask; + int wqebb_cnt = 0; + + hw_ci = HINIC_GET_SQ_HW_CI(txq); + sw_ci = HINIC_GET_SQ_LOCAL_CI(txq); + sq_mask = HINIC_GET_SQ_WQE_MASK(txq); + + for (i = 0; i < txq->tx_free_thresh; ++i) { + tx_info = &txq->tx_info[sw_ci]; + if ((hw_ci == sw_ci) || + (((hw_ci - sw_ci) & sq_mask) < tx_info->wqebb_cnt)) + break; + + sw_ci = (sw_ci + tx_info->wqebb_cnt) & sq_mask; + + if (unlikely(tx_info->cpy_mbuf != NULL)) { + rte_pktmbuf_free(tx_info->cpy_mbuf); + tx_info->cpy_mbuf = NULL; + } + + wqebb_cnt += tx_info->wqebb_cnt; + mbuf = tx_info->mbuf; + + if (likely(mbuf->nb_segs == 1)) { + m = rte_pktmbuf_prefree_seg(mbuf); + tx_info->mbuf = NULL; + + if (unlikely(m == NULL)) + continue; + + mbuf_free[nb_free++] = m; + if (unlikely((m->pool != mbuf_free[0]->pool) || + (nb_free >= HINIC_MAX_TX_FREE_BULK))) { + rte_mempool_put_bulk(mbuf_free[0]->pool, + (void **)mbuf_free, (nb_free - 1)); + nb_free = 0; + mbuf_free[nb_free++] = m; + } + } else { + rte_pktmbuf_free(mbuf); + tx_info->mbuf = NULL; + } + } + + if (nb_free > 0) + rte_mempool_put_bulk(mbuf_free[0]->pool, (void **)mbuf_free, + nb_free); + + HINIC_UPDATE_SQ_LOCAL_CI(txq, wqebb_cnt); +} + +static inline struct hinic_sq_wqe * +hinic_get_sq_wqe(struct hinic_txq *txq, int wqebb_cnt, + struct hinic_wqe_info *wqe_info) +{ + u32 cur_pi, end_pi; + u16 remain_wqebbs; + struct hinic_sq *sq = txq->sq; + struct hinic_wq *wq = txq->wq; + + /* record current pi */ + cur_pi = MASKED_WQE_IDX(wq, wq->prod_idx); + end_pi = cur_pi + wqebb_cnt; + + /* update next pi and delta */ + wq->prod_idx += wqebb_cnt; + wq->delta -= wqebb_cnt; + + /* return current pi and owner */ + wqe_info->pi = cur_pi; + wqe_info->owner = sq->owner; + wqe_info->around = 0; + wqe_info->seq_wqebbs = wqebb_cnt; + + if (unlikely(end_pi >= txq->q_depth)) { + /* update owner of next prod_idx */ + sq->owner = !sq->owner; + + /* turn around to head */ + if (unlikely(end_pi > txq->q_depth)) { + wqe_info->around = 1; + remain_wqebbs = txq->q_depth - cur_pi; + wqe_info->seq_wqebbs = remain_wqebbs; + } + } + + return (struct hinic_sq_wqe *)WQ_WQE_ADDR(wq, cur_pi); +} + +static inline int +hinic_validate_tx_offload(const struct rte_mbuf *m) +{ + uint64_t ol_flags = m->ol_flags; + uint64_t inner_l3_offset = m->l2_len; + + /* just support vxlan offload */ + if ((ol_flags & PKT_TX_TUNNEL_MASK) && + !(ol_flags & PKT_TX_TUNNEL_VXLAN)) + return -ENOTSUP; + + if (ol_flags & PKT_TX_OUTER_IP_CKSUM) + inner_l3_offset += m->outer_l2_len + m->outer_l3_len; + + /* Headers are fragmented */ + if (rte_pktmbuf_data_len(m) < inner_l3_offset + m->l3_len + m->l4_len) + return -ENOTSUP; + + /* IP checksum can be counted only for IPv4 packet */ + if ((ol_flags & PKT_TX_IP_CKSUM) && (ol_flags & PKT_TX_IPV6)) + return -EINVAL; + + /* IP type not set when required */ + if (ol_flags & (PKT_TX_L4_MASK | PKT_TX_TCP_SEG)) { + if (!(ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6))) + return -EINVAL; + } + + /* Check requirements for TSO packet */ + if (ol_flags & PKT_TX_TCP_SEG) { + if ((m->tso_segsz == 0) || + ((ol_flags & PKT_TX_IPV4) && + !(ol_flags & PKT_TX_IP_CKSUM))) + return -EINVAL; + } + + /* PKT_TX_OUTER_IP_CKSUM set for non outer IPv4 packet. */ + if ((ol_flags & PKT_TX_OUTER_IP_CKSUM) && + !(ol_flags & PKT_TX_OUTER_IPV4)) + return -EINVAL; + + return 0; +} + +static inline uint16_t +hinic_ipv4_phdr_cksum(const struct ipv4_hdr *ipv4_hdr, uint64_t ol_flags) +{ + struct ipv4_psd_header { + uint32_t src_addr; /* IP address of source host. */ + uint32_t dst_addr; /* IP address of destination host. */ + uint8_t zero; /* zero. */ + uint8_t proto; /* L4 protocol type. */ + uint16_t len; /* L4 length. */ + } psd_hdr; + uint8_t ihl; + + psd_hdr.src_addr = ipv4_hdr->src_addr; + psd_hdr.dst_addr = ipv4_hdr->dst_addr; + psd_hdr.zero = 0; + psd_hdr.proto = ipv4_hdr->next_proto_id; + if (ol_flags & PKT_TX_TCP_SEG) { + psd_hdr.len = 0; + } else { + /* ipv4_hdr->version_ihl is uint8_t big endian, ihl locates + * lower 4 bits and unit is 4 bytes + */ + ihl = (ipv4_hdr->version_ihl & 0xF) << 2; + psd_hdr.len = + rte_cpu_to_be_16( + rte_be_to_cpu_16(ipv4_hdr->total_length) - ihl); + } + return rte_raw_cksum(&psd_hdr, sizeof(psd_hdr)); +} + +static inline uint16_t +hinic_ipv6_phdr_cksum(const struct ipv6_hdr *ipv6_hdr, uint64_t ol_flags) +{ + uint32_t sum; + struct { + uint32_t len; /* L4 length. */ + uint32_t proto; /* L4 protocol - top 3 bytes must be zero */ + } psd_hdr; + + psd_hdr.proto = (ipv6_hdr->proto << 24); + if (ol_flags & PKT_TX_TCP_SEG) + psd_hdr.len = 0; + else + psd_hdr.len = ipv6_hdr->payload_len; + + sum = __rte_raw_cksum(ipv6_hdr->src_addr, + sizeof(ipv6_hdr->src_addr) + sizeof(ipv6_hdr->dst_addr), 0); + sum = __rte_raw_cksum(&psd_hdr, sizeof(psd_hdr), sum); + return __rte_raw_cksum_reduce(sum); +} + +static inline int +hinic_tx_offload_pkt_prepare(struct rte_mbuf *m, + struct hinic_tx_offload_info *off_info) +{ + struct ipv4_hdr *ipv4_hdr; + struct ipv6_hdr *ipv6_hdr; + struct tcp_hdr *tcp_hdr; + struct udp_hdr *udp_hdr; + struct ether_hdr *eth_hdr; + struct vlan_hdr *vlan_hdr; + u16 eth_type = 0; + uint64_t inner_l3_offset = m->l2_len; + uint64_t ol_flags = m->ol_flags; + + /* Does packet set any of available offloads */ + if (!(ol_flags & HINIC_TX_CKSUM_OFFLOAD_MASK)) + return 0; + + if (unlikely(hinic_validate_tx_offload(m))) + return -EINVAL; + + if ((ol_flags & PKT_TX_OUTER_IP_CKSUM) || + (ol_flags & PKT_TX_OUTER_IPV6) || + (ol_flags & PKT_TX_TUNNEL_VXLAN)) { + inner_l3_offset += m->outer_l2_len + m->outer_l3_len; + off_info->outer_l2_len = m->outer_l2_len; + off_info->outer_l3_len = m->outer_l3_len; + /* just support vxlan tunneling pkt */ + off_info->inner_l2_len = m->l2_len - VXLANLEN - + sizeof(struct udp_hdr); + off_info->inner_l3_len = m->l3_len; + off_info->inner_l4_len = m->l4_len; + off_info->tunnel_length = m->l2_len; + off_info->payload_offset = m->outer_l2_len + + m->outer_l3_len + m->l2_len + m->l3_len; + off_info->tunnel_type = TUNNEL_UDP_NO_CSUM; + } else { + off_info->inner_l2_len = m->l2_len; + off_info->inner_l3_len = m->l3_len; + off_info->inner_l4_len = m->l4_len; + off_info->tunnel_type = NOT_TUNNEL; + off_info->payload_offset = m->l2_len + m->l3_len; + } + + if (((ol_flags & PKT_TX_L4_MASK) != PKT_TX_SCTP_CKSUM) && + ((ol_flags & PKT_TX_L4_MASK) != PKT_TX_UDP_CKSUM)) + off_info->payload_offset += m->l4_len; + + /* invalid udp or tcp header */ + if (unlikely(off_info->payload_offset > MAX_PLD_OFFSET)) + return -EINVAL; + + /* Process outter udp pseudo-header checksum */ + if ((ol_flags & PKT_TX_TUNNEL_VXLAN) && ((ol_flags & PKT_TX_TCP_SEG) || + (ol_flags & PKT_TX_OUTER_IP_CKSUM) || + (ol_flags & PKT_TX_OUTER_IPV6))) { + off_info->tunnel_type = TUNNEL_UDP_CSUM; + + /* inner_l4_tcp_udp csum should be setted to calculate outter + * udp checksum when vxlan packets without inner l3 and l4 + */ + off_info->inner_l4_tcp_udp = 1; + + eth_hdr = rte_pktmbuf_mtod(m, struct ether_hdr *); + eth_type = rte_be_to_cpu_16(eth_hdr->ether_type); + + if (eth_type == ETHER_TYPE_VLAN) { + vlan_hdr = (struct vlan_hdr *)(eth_hdr + 1); + eth_type = rte_be_to_cpu_16(vlan_hdr->eth_proto); + } + + if (eth_type == ETHER_TYPE_IPv4) { + ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *, + m->outer_l2_len); + off_info->outer_l3_type = IPV4_PKT_WITH_CHKSUM_OFFLOAD; + ipv4_hdr->hdr_checksum = 0; + + udp_hdr = (struct udp_hdr *)((char *)ipv4_hdr + + m->outer_l3_len); + udp_hdr->dgram_cksum = hinic_ipv4_phdr_cksum(ipv4_hdr, + ol_flags); + } else if (eth_type == ETHER_TYPE_IPv6) { + off_info->outer_l3_type = IPV6_PKT; + ipv6_hdr = rte_pktmbuf_mtod_offset(m, struct ipv6_hdr *, + m->outer_l2_len); + + udp_hdr = rte_pktmbuf_mtod_offset(m, struct udp_hdr *, + m->outer_l2_len + + m->outer_l3_len); + udp_hdr->dgram_cksum = + hinic_ipv6_phdr_cksum(ipv6_hdr, ol_flags); + } + } + + if (ol_flags & PKT_TX_IPV4) + off_info->inner_l3_type = (ol_flags & PKT_TX_IP_CKSUM) ? + IPV4_PKT_WITH_CHKSUM_OFFLOAD : + IPV4_PKT_NO_CHKSUM_OFFLOAD; + else if (ol_flags & PKT_TX_IPV6) + off_info->inner_l3_type = IPV6_PKT; + + /* Process the pseudo-header checksum */ + if ((ol_flags & PKT_TX_L4_MASK) == PKT_TX_UDP_CKSUM) { + if (ol_flags & PKT_TX_IPV4) { + ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *, + inner_l3_offset); + + if (ol_flags & PKT_TX_IP_CKSUM) + ipv4_hdr->hdr_checksum = 0; + + udp_hdr = (struct udp_hdr *)((char *)ipv4_hdr + + m->l3_len); + udp_hdr->dgram_cksum = hinic_ipv4_phdr_cksum(ipv4_hdr, + ol_flags); + } else { + ipv6_hdr = rte_pktmbuf_mtod_offset(m, struct ipv6_hdr *, + inner_l3_offset); + + udp_hdr = rte_pktmbuf_mtod_offset(m, struct udp_hdr *, + inner_l3_offset + + m->l3_len); + udp_hdr->dgram_cksum = + hinic_ipv6_phdr_cksum(ipv6_hdr, ol_flags); + } + + off_info->inner_l4_type = UDP_OFFLOAD_ENABLE; + off_info->inner_l4_tcp_udp = 1; + off_info->inner_l4_len = sizeof(struct udp_hdr); + } else if (((ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) || + (ol_flags & PKT_TX_TCP_SEG)) { + if (ol_flags & PKT_TX_IPV4) { + ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *, + inner_l3_offset); + + if (ol_flags & PKT_TX_IP_CKSUM) + ipv4_hdr->hdr_checksum = 0; + + /* non-TSO tcp */ + tcp_hdr = (struct tcp_hdr *)((char *)ipv4_hdr + + m->l3_len); + tcp_hdr->cksum = + hinic_ipv4_phdr_cksum(ipv4_hdr, ol_flags); + } else { + ipv6_hdr = rte_pktmbuf_mtod_offset(m, struct ipv6_hdr *, + inner_l3_offset); + /* non-TSO tcp */ + tcp_hdr = rte_pktmbuf_mtod_offset(m, struct tcp_hdr *, + inner_l3_offset + + m->l3_len); + tcp_hdr->cksum = + hinic_ipv6_phdr_cksum(ipv6_hdr, ol_flags); + } + + off_info->inner_l4_type = TCP_OFFLOAD_ENABLE; + off_info->inner_l4_tcp_udp = 1; + } else if ((ol_flags & PKT_TX_L4_MASK) == PKT_TX_SCTP_CKSUM) { + off_info->inner_l4_type = SCTP_OFFLOAD_ENABLE; + off_info->inner_l4_tcp_udp = 0; + off_info->inner_l4_len = sizeof(struct sctp_hdr); + } + + return 0; +} + +static inline bool hinic_get_sge_txoff_info(struct rte_mbuf *mbuf_pkt, + struct hinic_wqe_info *sqe_info, + struct hinic_tx_offload_info + *off_info) +{ + u16 i, total_len, sge_cnt = mbuf_pkt->nb_segs; + struct rte_mbuf *mbuf; + int ret; + + memset(off_info, 0, sizeof(*off_info)); + + ret = hinic_tx_offload_pkt_prepare(mbuf_pkt, off_info); + if (unlikely(ret)) + return false; + + sqe_info->cpy_mbuf_cnt = 0; + + /* non tso mbuf */ + if (likely(!(mbuf_pkt->ol_flags & PKT_TX_TCP_SEG))) { + if (unlikely(mbuf_pkt->pkt_len > MAX_SINGLE_SGE_SIZE)) { + /* non tso packet len must less than 64KB */ + return false; + } else if (unlikely(HINIC_NONTSO_SEG_NUM_INVALID(sge_cnt))) { + /* non tso packet buffer number must less than 17 + * the mbuf segs more than 17 must copy to one buffer + */ + total_len = 0; + mbuf = mbuf_pkt; + for (i = 0; i < (HINIC_NONTSO_PKT_MAX_SGE - 1) ; i++) { + total_len += mbuf->data_len; + mbuf = mbuf->next; + } + + /* default support copy total 4k mbuf segs */ + if ((u32)(total_len + (u16)HINIC_COPY_MBUF_SIZE) < + mbuf_pkt->pkt_len) + return false; + + sqe_info->sge_cnt = HINIC_NONTSO_PKT_MAX_SGE; + sqe_info->cpy_mbuf_cnt = 1; + return true; + } + + /* valid non tso mbuf */ + sqe_info->sge_cnt = sge_cnt; + } else { + /* tso mbuf */ + if (unlikely(HINIC_TSO_SEG_NUM_INVALID(sge_cnt))) + /* too many mbuf segs */ + return false; + + /* check tso mbuf segs are valid or not */ + if (unlikely(!hinic_is_tso_sge_valid(mbuf_pkt, + off_info, sqe_info))) + return false; + } + + return true; +} + +static inline void hinic_sq_write_db(struct hinic_sq *sq, int cos) +{ + u16 prod_idx; + u32 hi_prod_idx; + struct hinic_sq_db sq_db; + + prod_idx = MASKED_SQ_IDX(sq, sq->wq->prod_idx); + hi_prod_idx = SQ_DB_PI_HIGH(prod_idx); + + sq_db.db_info = SQ_DB_INFO_SET(hi_prod_idx, HI_PI) | + SQ_DB_INFO_SET(SQ_DB, TYPE) | + SQ_DB_INFO_SET(SQ_CFLAG_DP, CFLAG) | + SQ_DB_INFO_SET(cos, COS) | + SQ_DB_INFO_SET(sq->q_id, QID); + + /* Data should be written to HW in Big Endian Format */ + sq_db.db_info = cpu_to_be32(sq_db.db_info); + + /* Write all before the doorbell */ + rte_wmb(); + writel(sq_db.db_info, SQ_DB_ADDR(sq, prod_idx)); +} + +u16 hinic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, u16 nb_pkts) +{ + int free_wqebb_cnt, wqe_wqebb_cnt; + u32 queue_info, tx_bytes = 0; + u16 nb_tx; + struct hinic_wqe_info sqe_info; + struct hinic_tx_offload_info off_info; + struct rte_mbuf *mbuf_pkt; + struct hinic_txq *txq; + struct hinic_tx_info *tx_info; + struct hinic_sq_wqe *sq_wqe; + struct hinic_sq_task *task; +#ifdef HINIC_XSTAT_PROF_TX + uint64_t t1, t2; + + t1 = rte_get_tsc_cycles(); +#endif + + txq = (struct hinic_txq *)tx_queue; + + if (unlikely(!txq->nic_dev->link_status)) + return 0; + + /* reclaim tx mbuf before xmit new packet */ + if (HINIC_GET_SQ_FREE_WQEBBS(txq) < txq->tx_free_thresh) + hinic_xmit_mbuf_cleanup(txq); + + /* tx loop routine */ + for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) { + mbuf_pkt = *tx_pkts++; + queue_info = 0; + + /* 1. parse sge and tx offlod info from mbuf */ + if (unlikely(!hinic_get_sge_txoff_info(mbuf_pkt, + &sqe_info, &off_info))) { + txq->txq_stats.off_errs++; + break; + } + + /* 2. try to get enough wqebb */ + wqe_wqebb_cnt = HINIC_SQ_WQEBB_CNT(sqe_info.sge_cnt); + free_wqebb_cnt = HINIC_GET_SQ_FREE_WQEBBS(txq); + if (unlikely(wqe_wqebb_cnt > free_wqebb_cnt)) { + /* reclaim again */ + hinic_xmit_mbuf_cleanup(txq); + free_wqebb_cnt = HINIC_GET_SQ_FREE_WQEBBS(txq); + if (unlikely(wqe_wqebb_cnt > free_wqebb_cnt)) { + txq->txq_stats.tx_busy += (nb_pkts - nb_tx); + break; + } + } + + /* 3. get sq tail wqe address from wqe_page, + * sq have enough wqebb for this packet + */ + sq_wqe = hinic_get_sq_wqe(txq, wqe_wqebb_cnt, &sqe_info); + + /* 4. fill sq wqe sge section */ + if (unlikely(!hinic_mbuf_dma_map_sge(txq, mbuf_pkt, + sq_wqe->buf_descs, + &sqe_info))) { + hinic_return_sq_wqe(txq->nic_dev->hwdev, txq->q_id, + wqe_wqebb_cnt, sqe_info.owner); + txq->txq_stats.off_errs++; + break; + } + + /* 5. fill sq wqe task section and queue info */ + task = &sq_wqe->task; + + /* tx packet offload configure */ + hinic_fill_tx_offload_info(mbuf_pkt, task, &queue_info, + &off_info); + + /* 6. record tx info */ + tx_info = &txq->tx_info[sqe_info.pi]; + tx_info->mbuf = mbuf_pkt; + tx_info->wqebb_cnt = wqe_wqebb_cnt; + + /* 7. fill sq wqe header section */ + hinic_fill_sq_wqe_header(&sq_wqe->ctrl, queue_info, + sqe_info.sge_cnt, sqe_info.owner); + + /* 8.convert continue or bottom wqe byteorder to big endian */ + hinic_sq_wqe_cpu_to_be32(sq_wqe, sqe_info.seq_wqebbs); + + tx_bytes += mbuf_pkt->pkt_len; + } + + /* 9. write sq doorbell in burst mode */ + if (nb_tx) { + hinic_sq_write_db(txq->sq, txq->cos); + + txq->txq_stats.packets += nb_tx; + txq->txq_stats.bytes += tx_bytes; + } + +#ifdef HINIC_XSTAT_PROF_TX + /* do profiling stats */ + t2 = rte_get_tsc_cycles(); + txq->txq_stats.app_tsc = t1 - txq->prof_tx_end_tsc; + txq->prof_tx_end_tsc = t2; + txq->txq_stats.pmd_tsc = t2 - t1; + txq->txq_stats.burst_pkts = nb_tx; +#endif + + return nb_tx; +} + +void hinic_free_all_tx_skbs(struct hinic_txq *txq) +{ + u16 ci; + hinic_nic_dev *nic_dev = txq->nic_dev; + struct hinic_tx_info *tx_info; + int free_wqebbs = hinic_get_sq_free_wqebbs(nic_dev->hwdev, + txq->q_id) + 1; + + while (free_wqebbs < txq->q_depth) { + ci = hinic_get_sq_local_ci(nic_dev->hwdev, txq->q_id); + + tx_info = &txq->tx_info[ci]; + + if (unlikely(tx_info->cpy_mbuf != NULL)) { + rte_pktmbuf_free(tx_info->cpy_mbuf); + tx_info->cpy_mbuf = NULL; + } + + rte_pktmbuf_free(tx_info->mbuf); + hinic_update_sq_local_ci(nic_dev->hwdev, txq->q_id, + tx_info->wqebb_cnt); + + free_wqebbs += tx_info->wqebb_cnt; + tx_info->mbuf = NULL; + } +} + +void hinic_free_all_tx_resources(struct rte_eth_dev *eth_dev) +{ + u16 q_id; + hinic_nic_dev *nic_dev = + (hinic_nic_dev *)HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev); + + for (q_id = 0; q_id < nic_dev->num_sq; q_id++) { + eth_dev->data->tx_queues[q_id] = NULL; + + if (nic_dev->txqs[q_id] == NULL) + continue; + + /* stop tx queue free tx mbuf */ + hinic_free_all_tx_skbs(nic_dev->txqs[q_id]); + hinic_free_tx_resources(nic_dev->txqs[q_id]); + + /* free txq */ + kfree(nic_dev->txqs[q_id]); + nic_dev->txqs[q_id] = NULL; + } +} + +void hinic_free_all_tx_mbuf(struct rte_eth_dev *eth_dev) +{ + u16 q_id; + hinic_nic_dev *nic_dev = + (hinic_nic_dev *)HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev); + + for (q_id = 0; q_id < nic_dev->num_sq; q_id++) + /* stop tx queue free tx mbuf */ + hinic_free_all_tx_skbs(nic_dev->txqs[q_id]); +} + +int hinic_setup_tx_resources(struct hinic_txq *txq) +{ + u64 tx_info_sz; + + tx_info_sz = txq->q_depth * sizeof(*txq->tx_info); + txq->tx_info = kzalloc_aligned(tx_info_sz, GFP_KERNEL); + if (!txq->tx_info) { + PMD_DRV_LOG(ERR, "Allocate tx info failed"); + return -ENOMEM; + } + + return HINIC_OK; +} + +void hinic_free_tx_resources(struct hinic_txq *txq) +{ + if (txq->tx_info == NULL) + return; + + kfree(txq->tx_info); + txq->tx_info = NULL; +} From patchwork Tue May 21 08:24:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ziyang Xuan X-Patchwork-Id: 53569 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 215964CAB; Tue, 21 May 2019 10:14:18 +0200 (CEST) Received: from huawei.com (szxga04-in.huawei.com [45.249.212.190]) by dpdk.org (Postfix) with ESMTP id 188DA4CA6 for ; Tue, 21 May 2019 10:14:16 +0200 (CEST) Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id A82FE887991821DC8A28 for ; Tue, 21 May 2019 16:14:14 +0800 (CST) Received: from tester_149.localdomain (10.175.119.39) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.439.0; Tue, 21 May 2019 16:14:05 +0800 From: Ziyang Xuan To: CC: , , , , Ziyang Xuan Date: Tue, 21 May 2019 16:24:52 +0800 Message-ID: <1558427092-187430-1-git-send-email-xuanziyang2@huawei.com> X-Mailer: git-send-email 1.8.3.1 MIME-Version: 1.0 X-Originating-IP: [10.175.119.39] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 11/11] net/hinic: add support for basic device operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add hinic PMD initialization and ethernet operatioins code. Signed-off-by: Ziyang Xuan --- drivers/net/hinic/Makefile | 2 +- drivers/net/hinic/hinic_pmd_ethdev.c | 2157 +++++++++++++++++++++++++++ drivers/net/hinic/rte_pmd_hinic_version.map | 4 + 3 files changed, 2162 insertions(+), 1 deletion(-) create mode 100644 drivers/net/hinic/hinic_pmd_ethdev.c create mode 100644 drivers/net/hinic/rte_pmd_hinic_version.map diff --git a/drivers/net/hinic/Makefile b/drivers/net/hinic/Makefile index 6fabf5e..06f49c4 100644 --- a/drivers/net/hinic/Makefile +++ b/drivers/net/hinic/Makefile @@ -73,7 +73,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_qp.c SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_wq.c SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_dpdev.c -#SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_ethdev.c +SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_ethdev.c SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_rx.c SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_tx.c # this lib depends upon: diff --git a/drivers/net/hinic/hinic_pmd_ethdev.c b/drivers/net/hinic/hinic_pmd_ethdev.c new file mode 100644 index 0000000..cd41e80 --- /dev/null +++ b/drivers/net/hinic/hinic_pmd_ethdev.c @@ -0,0 +1,2157 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Huawei Technologies Co., Ltd + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "hinic_pmd_ethdev.h" +#include "hinic_pmd_tx.h" +#include "hinic_pmd_rx.h" + +#define HINIC_MIN_RX_BUF_SIZE 1024 + +#define HINIC_MAX_MAC_ADDRS 1 +#define EQ_MSIX_RESEND_TIMER_CLEAR 1 + +/* Hinic PMD parameters */ +#define ETH_HINIC_FW_VER "check_fw_version" + +static const char *const valid_params[] = { + ETH_HINIC_FW_VER, + NULL}; + + +/** Driver-specific log messages type. */ +int hinic_logtype; + +static int check_fw_ver = 1; + +static int hinic_dev_init(struct rte_eth_dev *eth_dev); +static int hinic_dev_uninit(struct rte_eth_dev *dev); +static int hinic_init_mac_addr(struct rte_eth_dev *eth_dev); +static void hinic_deinit_mac_addr(struct rte_eth_dev *eth_dev); +static int hinic_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, + uint16_t nb_desc, unsigned int socket_id, + __rte_unused const struct rte_eth_rxconf *rx_conf, + struct rte_mempool *mp); +static int hinic_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, + uint16_t nb_desc, unsigned int socket_id, + __rte_unused const struct rte_eth_txconf *tx_conf); + +static const struct eth_dev_ops hinic_pmd_ops = { + .dev_configure = hinic_dev_configure, + .dev_infos_get = hinic_dev_infos_get, + .rx_queue_setup = hinic_rx_queue_setup, + .tx_queue_setup = hinic_tx_queue_setup, + .dev_start = hinic_dev_start, + .link_update = hinic_link_update, + .rx_queue_release = hinic_rx_queue_release, + .tx_queue_release = hinic_tx_queue_release, + .dev_stop = hinic_dev_stop, + .dev_close = hinic_dev_close, + .promiscuous_enable = hinic_dev_promiscuous_enable, + .promiscuous_disable = hinic_dev_promiscuous_disable, + .rss_hash_update = hinic_rss_hash_update, + .rss_hash_conf_get = hinic_rss_conf_get, + .reta_update = hinic_rss_indirtbl_update, + .reta_query = hinic_rss_indirtbl_query, + .stats_get = hinic_dev_stats_get, + .stats_reset = hinic_dev_stats_reset, + .xstats_get = hinic_dev_xstats_get, + .xstats_reset = hinic_dev_xstats_reset, + .xstats_get_names = hinic_dev_xstats_get_names, + .fw_version_get = hinic_fw_version_get, +}; + +static int hinic_check_fw_ver_param(__rte_unused const char *key, + const char *value, + __rte_unused void *opaque) +{ + int num = -1; + char *end = NULL; + + while (isblank(*value)) + value++; + + num = strtoul(value, &end, 10); + if ((*end == '-') || errno) + return -1; + check_fw_ver = num; + + return 0; +} + +static int +hinic_pci_verify_fw_ver(struct rte_eth_dev *eth_dev, + struct rte_devargs *devargs) +{ + struct rte_kvargs *kvlist; + const char *hinic_fw_ver_arg = ETH_HINIC_FW_VER; + int ret = HINIC_OK; + char ver_str[64] = {0}; + + if (hinic_fw_version_get(eth_dev, ver_str, 64) != HINIC_OK) + PMD_DRV_LOG(ERR, "Failed to get FW version"); + + PMD_DRV_LOG(INFO, "FW version = %s\n", ver_str); + + if (!devargs) + return ret; + + kvlist = rte_kvargs_parse(devargs->args, valid_params); + if (kvlist == NULL) + return ret; + + if (!rte_kvargs_count(kvlist, hinic_fw_ver_arg)) { + rte_kvargs_free(kvlist); + return ret; + } + + if (!rte_kvargs_process(kvlist, hinic_fw_ver_arg, + hinic_check_fw_ver_param, NULL) && check_fw_ver > 0) { + /* TODO: Verify version compatibility + * and update ret accordingly + */ + } + rte_kvargs_free(kvlist); + + return ret; +} + +RTE_PMD_REGISTER_PARAM_STRING(net_hinic, + ETH_HINIC_FW_VER "="); + +static struct rte_pci_id pci_id_hinic_map[] = { + { RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_PRD) }, + { RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_MEZZ_25GE) }, + { RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_MEZZ_40GE) }, + { RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_MEZZ_100GE) }, + {.vendor_id = 0}, +}; + +static int hinic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, + struct rte_pci_device *pci_dev) +{ + return rte_eth_dev_pci_generic_probe(pci_dev, + sizeof(hinic_nic_dev), hinic_dev_init); +} + +static int hinic_pci_remove(struct rte_pci_device *pci_dev) +{ + return rte_eth_dev_pci_generic_remove(pci_dev, hinic_dev_uninit); +} + +static struct rte_pci_driver rte_hinic_pmd = { + .id_table = pci_id_hinic_map, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, + .probe = hinic_pci_probe, + .remove = hinic_pci_remove, +}; + +RTE_PMD_REGISTER_PCI(net_hinic, rte_hinic_pmd); +RTE_PMD_REGISTER_PCI_TABLE(net_hinic, pci_id_hinic_map); + +struct hinic_xstats_name_off { + char name[RTE_ETH_XSTATS_NAME_SIZE]; + u32 offset; +}; + +#define HINIC_FUNC_STAT(_stat_item) { \ + .name = #_stat_item, \ + .offset = offsetof(struct hinic_vport_stats, _stat_item) \ +} + +static const struct hinic_xstats_name_off hinic_vport_stats_strings[] = { + HINIC_FUNC_STAT(tx_unicast_pkts_vport), + HINIC_FUNC_STAT(tx_unicast_bytes_vport), + HINIC_FUNC_STAT(tx_multicast_pkts_vport), + HINIC_FUNC_STAT(tx_multicast_bytes_vport), + HINIC_FUNC_STAT(tx_broadcast_pkts_vport), + HINIC_FUNC_STAT(tx_broadcast_bytes_vport), + + HINIC_FUNC_STAT(rx_unicast_pkts_vport), + HINIC_FUNC_STAT(rx_unicast_bytes_vport), + HINIC_FUNC_STAT(rx_multicast_pkts_vport), + HINIC_FUNC_STAT(rx_multicast_bytes_vport), + HINIC_FUNC_STAT(rx_broadcast_pkts_vport), + HINIC_FUNC_STAT(rx_broadcast_bytes_vport), + + HINIC_FUNC_STAT(tx_discard_vport), + HINIC_FUNC_STAT(rx_discard_vport), + HINIC_FUNC_STAT(tx_err_vport), + HINIC_FUNC_STAT(rx_err_vport), +}; + +#define HINIC_VPORT_XSTATS_NUM (sizeof(hinic_vport_stats_strings) / \ + sizeof(hinic_vport_stats_strings[0])) + +#define HINIC_PORT_STAT(_stat_item) { \ + .name = #_stat_item, \ + .offset = offsetof(struct hinic_phy_port_stats, _stat_item) \ +} + +static const struct hinic_xstats_name_off hinic_phyport_stats_strings[] = { + HINIC_PORT_STAT(mac_rx_total_pkt_num), + HINIC_PORT_STAT(mac_rx_total_oct_num), + HINIC_PORT_STAT(mac_rx_bad_pkt_num), + HINIC_PORT_STAT(mac_rx_bad_oct_num), + HINIC_PORT_STAT(mac_rx_good_pkt_num), + HINIC_PORT_STAT(mac_rx_good_oct_num), + HINIC_PORT_STAT(mac_rx_uni_pkt_num), + HINIC_PORT_STAT(mac_rx_multi_pkt_num), + HINIC_PORT_STAT(mac_rx_broad_pkt_num), + HINIC_PORT_STAT(mac_tx_total_pkt_num), + HINIC_PORT_STAT(mac_tx_total_oct_num), + HINIC_PORT_STAT(mac_tx_bad_pkt_num), + HINIC_PORT_STAT(mac_tx_bad_oct_num), + HINIC_PORT_STAT(mac_tx_good_pkt_num), + HINIC_PORT_STAT(mac_tx_good_oct_num), + HINIC_PORT_STAT(mac_tx_uni_pkt_num), + HINIC_PORT_STAT(mac_tx_multi_pkt_num), + HINIC_PORT_STAT(mac_tx_broad_pkt_num), + HINIC_PORT_STAT(mac_rx_fragment_pkt_num), + HINIC_PORT_STAT(mac_rx_undersize_pkt_num), + HINIC_PORT_STAT(mac_rx_undermin_pkt_num), + HINIC_PORT_STAT(mac_rx_64_oct_pkt_num), + HINIC_PORT_STAT(mac_rx_65_127_oct_pkt_num), + HINIC_PORT_STAT(mac_rx_128_255_oct_pkt_num), + HINIC_PORT_STAT(mac_rx_256_511_oct_pkt_num), + HINIC_PORT_STAT(mac_rx_512_1023_oct_pkt_num), + HINIC_PORT_STAT(mac_rx_1024_1518_oct_pkt_num), + HINIC_PORT_STAT(mac_rx_1519_2047_oct_pkt_num), + HINIC_PORT_STAT(mac_rx_2048_4095_oct_pkt_num), + HINIC_PORT_STAT(mac_rx_4096_8191_oct_pkt_num), + HINIC_PORT_STAT(mac_rx_8192_9216_oct_pkt_num), + HINIC_PORT_STAT(mac_rx_9217_12287_oct_pkt_num), + HINIC_PORT_STAT(mac_rx_12288_16383_oct_pkt_num), + HINIC_PORT_STAT(mac_rx_1519_max_bad_pkt_num), + HINIC_PORT_STAT(mac_rx_1519_max_good_pkt_num), + HINIC_PORT_STAT(mac_rx_oversize_pkt_num), + HINIC_PORT_STAT(mac_rx_jabber_pkt_num), + HINIC_PORT_STAT(mac_rx_mac_pause_num), + HINIC_PORT_STAT(mac_rx_pfc_pkt_num), + HINIC_PORT_STAT(mac_rx_pfc_pri0_pkt_num), + HINIC_PORT_STAT(mac_rx_pfc_pri1_pkt_num), + HINIC_PORT_STAT(mac_rx_pfc_pri2_pkt_num), + HINIC_PORT_STAT(mac_rx_pfc_pri3_pkt_num), + HINIC_PORT_STAT(mac_rx_pfc_pri4_pkt_num), + HINIC_PORT_STAT(mac_rx_pfc_pri5_pkt_num), + HINIC_PORT_STAT(mac_rx_pfc_pri6_pkt_num), + HINIC_PORT_STAT(mac_rx_pfc_pri7_pkt_num), + HINIC_PORT_STAT(mac_rx_mac_control_pkt_num), + HINIC_PORT_STAT(mac_rx_sym_err_pkt_num), + HINIC_PORT_STAT(mac_rx_fcs_err_pkt_num), + HINIC_PORT_STAT(mac_rx_send_app_good_pkt_num), + HINIC_PORT_STAT(mac_rx_send_app_bad_pkt_num), + HINIC_PORT_STAT(mac_tx_fragment_pkt_num), + HINIC_PORT_STAT(mac_tx_undersize_pkt_num), + HINIC_PORT_STAT(mac_tx_undermin_pkt_num), + HINIC_PORT_STAT(mac_tx_64_oct_pkt_num), + HINIC_PORT_STAT(mac_tx_65_127_oct_pkt_num), + HINIC_PORT_STAT(mac_tx_128_255_oct_pkt_num), + HINIC_PORT_STAT(mac_tx_256_511_oct_pkt_num), + HINIC_PORT_STAT(mac_tx_512_1023_oct_pkt_num), + HINIC_PORT_STAT(mac_tx_1024_1518_oct_pkt_num), + HINIC_PORT_STAT(mac_tx_1519_2047_oct_pkt_num), + HINIC_PORT_STAT(mac_tx_2048_4095_oct_pkt_num), + HINIC_PORT_STAT(mac_tx_4096_8191_oct_pkt_num), + HINIC_PORT_STAT(mac_tx_8192_9216_oct_pkt_num), + HINIC_PORT_STAT(mac_tx_9217_12287_oct_pkt_num), + HINIC_PORT_STAT(mac_tx_12288_16383_oct_pkt_num), + HINIC_PORT_STAT(mac_tx_1519_max_bad_pkt_num), + HINIC_PORT_STAT(mac_tx_1519_max_good_pkt_num), + HINIC_PORT_STAT(mac_tx_oversize_pkt_num), + HINIC_PORT_STAT(mac_trans_jabber_pkt_num), + HINIC_PORT_STAT(mac_tx_mac_pause_num), + HINIC_PORT_STAT(mac_tx_pfc_pkt_num), + HINIC_PORT_STAT(mac_tx_pfc_pri0_pkt_num), + HINIC_PORT_STAT(mac_tx_pfc_pri1_pkt_num), + HINIC_PORT_STAT(mac_tx_pfc_pri2_pkt_num), + HINIC_PORT_STAT(mac_tx_pfc_pri3_pkt_num), + HINIC_PORT_STAT(mac_tx_pfc_pri4_pkt_num), + HINIC_PORT_STAT(mac_tx_pfc_pri5_pkt_num), + HINIC_PORT_STAT(mac_tx_pfc_pri6_pkt_num), + HINIC_PORT_STAT(mac_tx_pfc_pri7_pkt_num), + HINIC_PORT_STAT(mac_tx_mac_control_pkt_num), + HINIC_PORT_STAT(mac_tx_err_all_pkt_num), + HINIC_PORT_STAT(mac_tx_from_app_good_pkt_num), + HINIC_PORT_STAT(mac_tx_from_app_bad_pkt_num), +}; + +#define HINIC_PHYPORT_XSTATS_NUM (sizeof(hinic_phyport_stats_strings) / \ + sizeof(hinic_phyport_stats_strings[0])) + +static const struct hinic_xstats_name_off hinic_rxq_stats_strings[] = { + {"rx_nombuf", offsetof(struct hinic_rxq_stats, rx_nombuf)}, + +#ifdef HINIC_XSTAT_RXBUF_INFO + {"rxmbuf", offsetof(struct hinic_rxq_stats, rx_mbuf)}, + {"avail", offsetof(struct hinic_rxq_stats, rx_avail)}, + {"hole", offsetof(struct hinic_rxq_stats, rx_hole)}, + {"burst_pkt", offsetof(struct hinic_rxq_stats, burst_pkts)}, +#endif + +#ifdef HINIC_XSTAT_PROF_RX + {"app_tsc", offsetof(struct hinic_rxq_stats, app_tsc)}, + {"pmd_tsc", offsetof(struct hinic_rxq_stats, pmd_tsc)}, +#endif + +#ifdef HINIC_XSTAT_MBUF_USE + {"rx_alloc_mbuf", offsetof(struct hinic_rxq_stats, alloc_mbuf)}, + {"rx_free_mbuf", offsetof(struct hinic_rxq_stats, free_mbuf)}, + {"rx_left_mbuf", offsetof(struct hinic_rxq_stats, left_mbuf)}, +#endif +}; + +#define HINIC_RXQ_XSTATS_NUM (sizeof(hinic_rxq_stats_strings) / \ + sizeof(hinic_rxq_stats_strings[0])) + +static const struct hinic_xstats_name_off hinic_txq_stats_strings[] = { + {"tx_busy", offsetof(struct hinic_txq_stats, tx_busy)}, + {"offload_errors", offsetof(struct hinic_txq_stats, off_errs)}, + {"copy_pkts", offsetof(struct hinic_txq_stats, cpy_pkts)}, + {"rl_drop", offsetof(struct hinic_txq_stats, rl_drop)}, + +#ifdef HINIC_XSTAT_PROF_TX + {"app_tsc", offsetof(struct hinic_txq_stats, app_tsc)}, + {"pmd_tsc", offsetof(struct hinic_txq_stats, pmd_tsc)}, + {"burst_pkts", offsetof(struct hinic_txq_stats, burst_pkts)}, +#endif +}; + +#define HINIC_TXQ_XSTATS_NUM (sizeof(hinic_txq_stats_strings) / \ + sizeof(hinic_txq_stats_strings[0])) + +static const struct rte_eth_desc_lim hinic_rx_desc_lim = { + .nb_max = HINIC_MAX_QUEUE_DEPTH, + .nb_min = HINIC_MIN_QUEUE_DEPTH, + .nb_align = HINIC_RXD_ALIGN, +}; + +static const struct rte_eth_desc_lim hinic_tx_desc_lim = { + .nb_max = HINIC_MAX_QUEUE_DEPTH, + .nb_min = HINIC_MIN_QUEUE_DEPTH, + .nb_align = HINIC_TXD_ALIGN, +}; + +static int hinic_xstats_calc_num(hinic_nic_dev *nic_dev) +{ + return (HINIC_VPORT_XSTATS_NUM + + HINIC_PHYPORT_XSTATS_NUM + + HINIC_RXQ_XSTATS_NUM * nic_dev->num_rq + + HINIC_TXQ_XSTATS_NUM * nic_dev->num_sq); +} + +static void hinic_dev_handle_aeq_event(hinic_nic_dev *nic_dev, void *param) +{ + struct hinic_hwdev *hwdev = nic_dev->hwdev; + struct hinic_eq *aeq = &hwdev->aeqs->aeq[0]; + + /* clear resend timer cnt register */ + hinic_misx_intr_clear_resend_bit(hwdev, aeq->eq_irq.msix_entry_idx, + EQ_MSIX_RESEND_TIMER_CLEAR); + (void)hinic_aeq_poll_msg(aeq, 0, param); +} + +/** + * Interrupt handler triggered by NIC for handling + * specific event. + * + * @param: The address of parameter (struct rte_eth_dev *) regsitered before. + **/ +static void hinic_dev_interrupt_handler(void *param) +{ + struct rte_eth_dev *dev = (struct rte_eth_dev *)param; + hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + + if (!hinic_test_bit(HINIC_DEV_INTR_EN, &nic_dev->dev_status)) { + PMD_DRV_LOG(INFO, "Device's interrupt is disabled, ignore interrupt event, dev_name: %s, port_id: %d", + nic_dev->proc_dev_name, dev->data->port_id); + return; + } + + /* aeq0 msg handler */ + hinic_dev_handle_aeq_event(nic_dev, param); +} + +static int hinic_func_init(struct rte_eth_dev *eth_dev) +{ + struct rte_pci_device *pci_dev; + struct ether_addr *eth_addr; + hinic_nic_dev *nic_dev; + int rc; + + pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); + + /* EAL is SECONDARY and eth_dev is already created */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) { + rc = rte_intr_callback_register(&pci_dev->intr_handle, + hinic_dev_interrupt_handler, + (void *)eth_dev); + if (rc) + PMD_DRV_LOG(ERR, "Initialize %s failed in secondary process", + eth_dev->data->name); + + return rc; + } + + nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev); + memset(nic_dev, 0, sizeof(*nic_dev)); + + snprintf(nic_dev->proc_dev_name, + sizeof(nic_dev->proc_dev_name), + "hinic-%.4x:%.2x:%.2x.%x", + pci_dev->addr.domain, pci_dev->addr.bus, + pci_dev->addr.devid, pci_dev->addr.function); + + rte_eth_copy_pci_info(eth_dev, pci_dev); + + /* clear RX ring mbuf allocated failed */ + eth_dev->data->rx_mbuf_alloc_failed = 0; + + /* alloc mac_addrs */ + eth_addr = (struct ether_addr *)rte_zmalloc("hinic_mac", + sizeof(*eth_addr), 0); + if (!eth_addr) { + PMD_DRV_LOG(ERR, "Allocate ethernet addresses' memory failed, dev_name: %s", + eth_dev->data->name); + rc = -ENOMEM; + goto eth_addr_fail; + } + eth_dev->data->mac_addrs = eth_addr; + + /* create hardware nic_device */ + rc = hinic_nic_dev_create(eth_dev); + if (rc) { + PMD_DRV_LOG(ERR, "Create nic device failed, dev_name: %s", + eth_dev->data->name); + goto create_nic_dev_fail; + } + + rc = hinic_init_mac_addr(eth_dev); + if (rc) { + PMD_DRV_LOG(ERR, "Initialize mac table failed, dev_name: %s", + eth_dev->data->name); + goto init_mac_fail; + } + + /* register callback func to eal lib */ + rc = rte_intr_callback_register(&pci_dev->intr_handle, + hinic_dev_interrupt_handler, + (void *)eth_dev); + if (rc) { + PMD_DRV_LOG(ERR, "Register rte interrupt callback failed, dev_name: %s", + eth_dev->data->name); + goto reg_intr_cb_fail; + } + + /* Verify fw-driver version compatibility */ + rc = hinic_pci_verify_fw_ver(eth_dev, pci_dev->device.devargs); + if (rc != HINIC_OK) + goto enable_intr_fail; + + /* enable uio/vfio intr/eventfd mapping */ + rc = rte_intr_enable(&pci_dev->intr_handle); + if (rc) { + PMD_DRV_LOG(ERR, "Enable rte interrupt failed, dev_name: %s", + eth_dev->data->name); + goto enable_intr_fail; + } + hinic_set_bit(HINIC_DEV_INTR_EN, &nic_dev->dev_status); + + hinic_set_bit(HINIC_DEV_INIT, &nic_dev->dev_status); + PMD_DRV_LOG(INFO, "Initialize %s in primary successfully", + eth_dev->data->name); + + return 0; + +enable_intr_fail: + (void)rte_intr_callback_unregister(&pci_dev->intr_handle, + hinic_dev_interrupt_handler, + (void *)eth_dev); + +reg_intr_cb_fail: + hinic_deinit_mac_addr(eth_dev); + +init_mac_fail: + hinic_nic_dev_destroy(eth_dev); + +create_nic_dev_fail: + rte_free(eth_addr); + eth_dev->data->mac_addrs = NULL; + +eth_addr_fail: + PMD_DRV_LOG(INFO, "Initialize %s in primary failed", + eth_dev->data->name); + return rc; +} + +static int hinic_dev_init(struct rte_eth_dev *eth_dev) +{ + struct rte_pci_device *pci_dev; + + pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); + + PMD_DRV_LOG(INFO, "Initializing pf hinic-%.4x:%.2x:%.2x.%x in %s process", + pci_dev->addr.domain, pci_dev->addr.bus, + pci_dev->addr.devid, pci_dev->addr.function, + (rte_eal_process_type() == RTE_PROC_PRIMARY) ? + "primary" : "secondary"); + + /* rte_eth_dev ops, rx_burst and tx_burst */ + eth_dev->dev_ops = &hinic_pmd_ops; + eth_dev->rx_pkt_burst = hinic_recv_pkts; + eth_dev->tx_pkt_burst = hinic_xmit_pkts; + + return hinic_func_init(eth_dev); +} + +/** + * PF Function device uninit. + */ +static int hinic_dev_uninit(struct rte_eth_dev *dev) +{ + hinic_nic_dev *nic_dev; + + nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + hinic_clear_bit(HINIC_DEV_INIT, &nic_dev->dev_status); + + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + hinic_dev_close(dev); + + dev->dev_ops = NULL; + dev->rx_pkt_burst = NULL; + dev->tx_pkt_burst = NULL; + + rte_free(dev->data->mac_addrs); + dev->data->mac_addrs = NULL; + + return HINIC_OK; +} + +/** + * Ethernet device configuration. + * + * Prepare the driver for a given number of TX and RX queues, mtu size + * and configure RSS. + * + * @param dev + * Pointer to Ethernet device structure. + * + * @return + * 0 on success, negative error value otherwise. + */ +int hinic_dev_configure(struct rte_eth_dev *dev) +{ + hinic_nic_dev *nic_dev; + struct hinic_nic_io *nic_io; + int err; + + nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + nic_io = nic_dev->hwdev->nic_io; + + nic_dev->num_sq = dev->data->nb_tx_queues; + nic_dev->num_rq = dev->data->nb_rx_queues; + + nic_io->num_sqs = dev->data->nb_tx_queues; + nic_io->num_rqs = dev->data->nb_rx_queues; + + /* queue pair is max_num(sq, rq) */ + nic_dev->num_qps = (nic_dev->num_sq > nic_dev->num_rq) ? + nic_dev->num_sq : nic_dev->num_rq; + nic_io->num_qps = nic_dev->num_qps; + + if (nic_dev->num_qps > nic_io->max_qps) { + PMD_DRV_LOG(ERR, + "Queue number out of range, get queue_num:%d, max_queue_num:%d", + nic_dev->num_qps, nic_io->max_qps); + return -EINVAL; + } + + /* mtu size is 256~9600 */ + if (dev->data->dev_conf.rxmode.max_rx_pkt_len < HINIC_MIN_FRAME_SIZE || + dev->data->dev_conf.rxmode.max_rx_pkt_len > + HINIC_MAX_JUMBO_FRAME_SIZE) { + PMD_DRV_LOG(ERR, + "Max rx pkt len out of range, get max_rx_pkt_len:%d, " + "expect between %d and %d", + dev->data->dev_conf.rxmode.max_rx_pkt_len, + HINIC_MIN_FRAME_SIZE, HINIC_MAX_JUMBO_FRAME_SIZE); + return -EINVAL; + } + + nic_dev->mtu_size = + HINIC_PKTLEN_TO_MTU(dev->data->dev_conf.rxmode.max_rx_pkt_len); + + /* rss template */ + err = hinic_config_mq_mode(dev, TRUE); + if (err) { + PMD_DRV_LOG(ERR, "Config multi-queue failed"); + return err; + } + + return HINIC_OK; +} + +/** + * DPDK callback to create the receive queue. + * + * @param dev + * Pointer to Ethernet device structure. + * @param queue_idx + * RX queue index. + * @param nb_desc + * Number of descriptors for receive queue. + * @param socket_id + * NUMA socket on which memory must be allocated. + * @param rx_conf + * Thresholds parameters (unused_). + * @param mp + * Memory pool for buffer allocations. + * + * @return + * 0 on success, negative error value otherwise. + */ +static int hinic_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, + uint16_t nb_desc, unsigned int socket_id, + __rte_unused const struct rte_eth_rxconf *rx_conf, + struct rte_mempool *mp) +{ + int rc; + hinic_nic_dev *nic_dev; + struct hinic_rxq *rxq; + u16 rq_depth, rx_free_thresh; + u32 buf_size; + + nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + + /* queue depth must be power of 2, otherwise will be aligned up */ + rq_depth = (nb_desc & (nb_desc - 1)) ? + ((u16)(1U << (ilog2(nb_desc) + 1))) : nb_desc; + + /* + * Validate number of receive descriptors. + * It must not exceed hardware maximum and minimum. + */ + if ((rq_depth > HINIC_MAX_QUEUE_DEPTH) || + (rq_depth < HINIC_MIN_QUEUE_DEPTH)) { + PMD_DRV_LOG(ERR, "RX queue depth is out of range from %d to %d, (nb_desc=%d, q_depth=%d, port=%d queue=%d)", + HINIC_MIN_QUEUE_DEPTH, HINIC_MAX_QUEUE_DEPTH, + (int)nb_desc, (int)rq_depth, + (int)dev->data->port_id, (int)queue_idx); + return -EINVAL; + } + + /* + * The RX descriptor ring will be cleaned after rxq->rx_free_thresh + * descriptors are used or if the number of descriptors required + * to transmit a packet is greater than the number of free RX + * descriptors. + * The following constraints must be satisfied: + * rx_free_thresh must be greater than 0. + * rx_free_thresh must be less than the size of the ring minus 1. + * When set to zero use default values. + */ + rx_free_thresh = (u16)((rx_conf->rx_free_thresh) ? + rx_conf->rx_free_thresh : HINIC_DEFAULT_RX_FREE_THRESH); + if (rx_free_thresh >= (rq_depth - 1)) { + PMD_DRV_LOG(ERR, "rx_free_thresh must be less than the number of RX descriptors minus 1. (rx_free_thresh=%u port=%d queue=%d)", + (unsigned int)rx_free_thresh, + (int)dev->data->port_id, + (int)queue_idx); + return -EINVAL; + } + + rxq = (struct hinic_rxq *)rte_zmalloc_socket("hinic_rx_queue", + sizeof(struct hinic_rxq), + RTE_CACHE_LINE_SIZE, + socket_id); + if (!rxq) { + PMD_DRV_LOG(ERR, "Allocate rxq[%d] failed, dev_name: %s", + queue_idx, dev->data->name); + return -ENOMEM; + } + nic_dev->rxqs[queue_idx] = rxq; + + /* alloc rx sq hw wqepage*/ + rc = hinic_create_rq(nic_dev, queue_idx, rq_depth); + if (rc) { + PMD_DRV_LOG(ERR, "Create rxq[%d] failed, dev_name: %s, rq_depth: %d", + queue_idx, dev->data->name, rq_depth); + goto ceate_rq_fail; + } + + /* mbuf pool must be assigned before setup rx resources */ + rxq->mb_pool = mp; + + rc = + hinic_convert_rx_buf_size(rte_pktmbuf_data_room_size(rxq->mb_pool) - + RTE_PKTMBUF_HEADROOM, &buf_size); + if (rc) { + PMD_DRV_LOG(ERR, "Adjust buf size failed, dev_name: %s", + dev->data->name); + goto adjust_bufsize_fail; + } + + /* rx queue info, rearm control */ + rxq->wq = &nic_dev->nic_io->rq_wq[queue_idx]; + rxq->pi_virt_addr = nic_dev->nic_io->qps[queue_idx].rq.pi_virt_addr; + rxq->nic_dev = nic_dev; + rxq->q_id = queue_idx; + rxq->q_depth = rq_depth; + rxq->buf_len = (u16)buf_size; + rxq->rx_free_thresh = rx_free_thresh; + + /* the last point cant do mbuf rearm in bulk */ + rxq->rxinfo_align_end = rxq->q_depth - rxq->rx_free_thresh; + + /* device port identifier */ + rxq->port_id = dev->data->port_id; + + /* alloc rx_cqe and prepare rq_wqe */ + rc = hinic_setup_rx_resources(rxq); + if (rc) { + PMD_DRV_LOG(ERR, "Setup rxq[%d] rx_resources failed, dev_name:%s", + queue_idx, dev->data->name); + goto setup_rx_res_err; + } + + /* record nic_dev rxq in rte_eth rx_queues */ + dev->data->rx_queues[queue_idx] = rxq; + + PMD_DRV_LOG(INFO, "Setup rxq[%d] successfully, dev_name: %s, rq_depth: %d", + queue_idx, dev->data->name, rq_depth); + return 0; + +setup_rx_res_err: +adjust_bufsize_fail: + hinic_destroy_rq(nic_dev, queue_idx); + +ceate_rq_fail: + rte_free(rxq); + + return rc; +} + +static void hinic_reset_rx_queue(struct rte_eth_dev *dev) +{ + struct hinic_rxq *rxq; + hinic_nic_dev *nic_dev; + int q_id = 0; + + nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + + for (q_id = 0; q_id < nic_dev->num_rq; q_id++) { + rxq = (struct hinic_rxq *)dev->data->rx_queues[q_id]; + + rxq->wq->cons_idx = 0; + rxq->wq->prod_idx = 0; + rxq->wq->delta = rxq->q_depth; + rxq->wq->mask = rxq->q_depth - 1; + + /* alloc mbuf to rq */ + hinic_rx_alloc_pkts(rxq); + } +} + +/** + * DPDK callback to configure the transmit queue. + * + * @param dev + * Pointer to Ethernet device structure. + * @param queue_idx + * Transmit queue index. + * @param nb_desc + * Number of descriptors for transmit queue. + * @param socket_id + * NUMA socket on which memory must be allocated. + * @param tx_conf + * Tx queue configuration parameters. + * + * @return + * 0 on success, negative error value otherwise. + */ +static int hinic_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, + uint16_t nb_desc, unsigned int socket_id, + __rte_unused const struct rte_eth_txconf *tx_conf) +{ + int rc; + hinic_nic_dev *nic_dev; + struct hinic_txq *txq; + u16 sq_depth, tx_free_thresh; + + nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + + /* queue depth must be power of 2, otherwise will be aligned up */ + sq_depth = (nb_desc & (nb_desc - 1)) ? + ((u16)(1U << (ilog2(nb_desc) + 1))) : nb_desc; + + /* + * Validate number of transmit descriptors. + * It must not exceed hardware maximum and minimum. + */ + if ((sq_depth > HINIC_MAX_QUEUE_DEPTH) || + (sq_depth < HINIC_MIN_QUEUE_DEPTH)) { + PMD_DRV_LOG(ERR, "TX queue depth is out of range from %d to %d, (nb_desc=%d, q_depth=%d, port=%d queue=%d)", + HINIC_MIN_QUEUE_DEPTH, HINIC_MAX_QUEUE_DEPTH, + (int)nb_desc, (int)sq_depth, + (int)dev->data->port_id, (int)queue_idx); + return -EINVAL; + } + + /* + * The TX descriptor ring will be cleaned after txq->tx_free_thresh + * descriptors are used or if the number of descriptors required + * to transmit a packet is greater than the number of free TX + * descriptors. + * The following constraints must be satisfied: + * tx_free_thresh must be greater than 0. + * tx_free_thresh must be less than the size of the ring minus 1. + * When set to zero use default values. + */ + tx_free_thresh = (u16)((tx_conf->tx_free_thresh) ? + tx_conf->tx_free_thresh : HINIC_DEFAULT_TX_FREE_THRESH); + if (tx_free_thresh >= (sq_depth - 1)) { + PMD_DRV_LOG(ERR, "tx_free_thresh must be less than the number of TX descriptors minus 1. (tx_free_thresh=%u port=%d queue=%d)", + (unsigned int)tx_free_thresh, (int)dev->data->port_id, + (int)queue_idx); + return -EINVAL; + } + + txq = (struct hinic_txq *)rte_zmalloc_socket("hinic_tx_queue", + sizeof(struct hinic_txq), RTE_CACHE_LINE_SIZE, socket_id); + if (!txq) { + PMD_DRV_LOG(ERR, "Allocate txq[%d] failed, dev_name: %s", + queue_idx, dev->data->name); + return -ENOMEM; + } + nic_dev->txqs[queue_idx] = txq; + + /* alloc tx sq hw wqepage */ + rc = hinic_create_sq(nic_dev, queue_idx, sq_depth); + if (rc) { + PMD_DRV_LOG(ERR, "Create txq[%d] failed, dev_name: %s, sq_depth: %d", + queue_idx, dev->data->name, sq_depth); + goto create_sq_fail; + } + + txq->q_id = queue_idx; + txq->q_depth = sq_depth; + txq->port_id = dev->data->port_id; + txq->tx_free_thresh = tx_free_thresh; + txq->nic_dev = nic_dev; + txq->wq = &nic_dev->nic_io->sq_wq[queue_idx]; + txq->sq = &nic_dev->nic_io->qps[queue_idx].sq; + txq->cons_idx_addr = nic_dev->nic_io->qps[queue_idx].sq.cons_idx_addr; + txq->sq_head_addr = HINIC_GET_WQ_HEAD(txq); + txq->sq_bot_sge_addr = HINIC_GET_WQ_TAIL(txq) - + sizeof(struct hinic_sq_bufdesc); + txq->cos = nic_dev->default_cos; + + /* alloc software txinfo */ + rc = hinic_setup_tx_resources(txq); + if (rc) { + PMD_DRV_LOG(ERR, "Setup txq[%d] tx_resources failed, dev_name: %s", + queue_idx, dev->data->name); + goto setup_tx_res_fail; + } + + /* record nic_dev txq in rte_eth tx_queues */ + dev->data->tx_queues[queue_idx] = txq; + + return HINIC_OK; + +setup_tx_res_fail: + hinic_destroy_sq(nic_dev, queue_idx); + +create_sq_fail: + rte_free(txq); + + return rc; +} + +static void hinic_reset_tx_queue(struct rte_eth_dev *dev) +{ + hinic_nic_dev *nic_dev; + struct hinic_txq *txq; + struct hinic_nic_io *nic_io; + struct hinic_hwdev *hwdev; + volatile u32 *ci_addr; + int q_id = 0; + + nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + hwdev = nic_dev->hwdev; + nic_io = hwdev->nic_io; + + for (q_id = 0; q_id < nic_dev->num_sq; q_id++) { + txq = (struct hinic_txq *)dev->data->tx_queues[q_id]; + + txq->wq->cons_idx = 0; + txq->wq->prod_idx = 0; + txq->wq->delta = txq->q_depth; + txq->wq->mask = txq->q_depth - 1; + + /*clear hardware ci*/ + ci_addr = (volatile u32 *)HINIC_CI_VADDR(nic_io->ci_vaddr_base, + q_id); + *ci_addr = 0; + } +} + +/** + * Get link speed from NIC. + * + * @param dev + * Pointer to Ethernet device structure. + * @param speed_capa + * Pointer to link speed structure. + */ +static void hinic_get_speed_capa(struct rte_eth_dev *dev, uint32_t *speed_capa) +{ + hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + u32 supported_link, advertised_link; + int err; + +#define HINIC_LINK_MODE_SUPPORT_1G (1U << HINIC_GE_BASE_KX) + +#define HINIC_LINK_MODE_SUPPORT_10G (1U << HINIC_10GE_BASE_KR) + +#define HINIC_LINK_MODE_SUPPORT_25G ((1U << HINIC_25GE_BASE_KR_S) | \ + (1U << HINIC_25GE_BASE_CR_S) | \ + (1U << HINIC_25GE_BASE_KR) | \ + (1U << HINIC_25GE_BASE_CR)) + +#define HINIC_LINK_MODE_SUPPORT_40G ((1U << HINIC_40GE_BASE_KR4) | \ + (1U << HINIC_40GE_BASE_CR4)) + +#define HINIC_LINK_MODE_SUPPORT_100G ((1U << HINIC_100GE_BASE_KR4) | \ + (1U << HINIC_100GE_BASE_CR4)) + + err = hinic_get_link_mode(nic_dev->hwdev, + &supported_link, &advertised_link); + if (err || supported_link == HINIC_SUPPORTED_UNKNOWN || + advertised_link == HINIC_SUPPORTED_UNKNOWN) { + PMD_DRV_LOG(WARNING, "Get speed capability info failed, device: %s, port_id: %u", + nic_dev->proc_dev_name, dev->data->port_id); + } else { + *speed_capa = 0; + if (!!(supported_link & HINIC_LINK_MODE_SUPPORT_1G)) + *speed_capa |= ETH_LINK_SPEED_1G; + if (!!(supported_link & HINIC_LINK_MODE_SUPPORT_10G)) + *speed_capa |= ETH_LINK_SPEED_10G; + if (!!(supported_link & HINIC_LINK_MODE_SUPPORT_25G)) + *speed_capa |= ETH_LINK_SPEED_25G; + if (!!(supported_link & HINIC_LINK_MODE_SUPPORT_40G)) + *speed_capa |= ETH_LINK_SPEED_40G; + if (!!(supported_link & HINIC_LINK_MODE_SUPPORT_100G)) + *speed_capa |= ETH_LINK_SPEED_100G; + } +} + +/** + * DPDK callback to get information about the device. + * + * @param dev + * Pointer to Ethernet device structure. + * @param info + * Pointer to Info structure output buffer. + */ +void hinic_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) +{ + hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + + info->max_rx_queues = nic_dev->nic_cap.max_rqs; + info->max_tx_queues = nic_dev->nic_cap.max_sqs; + info->min_rx_bufsize = HINIC_MIN_RX_BUF_SIZE; + info->max_rx_pktlen = HINIC_MAX_JUMBO_FRAME_SIZE; + info->max_mac_addrs = HINIC_MAX_MAC_ADDRS; + + hinic_get_speed_capa(dev, &info->speed_capa); + info->rx_queue_offload_capa = 0; + info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP | + DEV_RX_OFFLOAD_IPV4_CKSUM | + DEV_RX_OFFLOAD_UDP_CKSUM | + DEV_RX_OFFLOAD_TCP_CKSUM | + DEV_RX_OFFLOAD_VLAN_FILTER | + DEV_RX_OFFLOAD_JUMBO_FRAME; + + info->tx_queue_offload_capa = 0; + info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT | + DEV_TX_OFFLOAD_IPV4_CKSUM | + DEV_TX_OFFLOAD_UDP_CKSUM | + DEV_TX_OFFLOAD_TCP_CKSUM | + DEV_TX_OFFLOAD_SCTP_CKSUM | + DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | + DEV_TX_OFFLOAD_TCP_TSO | + DEV_TX_OFFLOAD_MULTI_SEGS; + + info->hash_key_size = HINIC_RSS_KEY_SIZE; + info->reta_size = HINIC_RSS_INDIR_SIZE; + info->flow_type_rss_offloads = HINIC_RSS_OFFLOAD_ALL; + info->rx_desc_lim = hinic_rx_desc_lim; + info->tx_desc_lim = hinic_tx_desc_lim; +} + +int hinic_rxtx_configure(struct rte_eth_dev *dev) +{ + int err; + hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + + /* rx configure, if rss enable, need to init default configuration */ + err = hinic_rx_configure(dev); + if (err) { + PMD_DRV_LOG(ERR, "Configure rss failed"); + return err; + } + + /* rx mode init */ + err = hinic_config_rx_mode(nic_dev, HINIC_DEFAULT_RX_MODE); + if (err) { + PMD_DRV_LOG(ERR, "Configure rx_mode:0x%x failed", + HINIC_DEFAULT_RX_MODE); + goto set_rx_mode_fail; + } + + return HINIC_OK; + +set_rx_mode_fail: + hinic_rx_remove_configure(dev); + + return err; +} + +static void hinic_remove_rxtx_configure(struct rte_eth_dev *dev) +{ + hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + + (void)hinic_config_rx_mode(nic_dev, 0); + hinic_rx_remove_configure(dev); +} + +/** + * DPDK callback to start the device. + * + * @param dev + * Pointer to Ethernet device structure. + * + * @return + * 0 on success, negative errno value on failure. + */ +int hinic_dev_start(struct rte_eth_dev *dev) +{ + int rc; + char *name; + hinic_nic_dev *nic_dev; + + nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + name = dev->data->name; + + /* reset rx and tx queue */ + hinic_reset_rx_queue(dev); + hinic_reset_tx_queue(dev); + + /* init txq and rxq context */ + rc = hinic_init_qp_ctxts(nic_dev->hwdev); + if (rc) { + PMD_DRV_LOG(ERR, "Initialize qp context failed, dev_name:%s", + name); + goto init_qp_fail; + } + + /* rss template */ + rc = hinic_config_mq_mode(dev, TRUE); + if (rc) { + PMD_DRV_LOG(ERR, "Configure mq mode failed, dev_name: %s", + name); + goto cfg_mq_mode_fail; + } + + /* set default mtu */ + rc = hinic_set_port_mtu(nic_dev->hwdev, nic_dev->mtu_size); + if (rc) { + PMD_DRV_LOG(ERR, "Set mtu_size[%d] failed, dev_name: %s", + nic_dev->mtu_size, name); + goto set_mtu_fail; + } + + /* configure rss rx_mode and other rx or tx default feature */ + rc = hinic_rxtx_configure(dev); + if (rc) { + PMD_DRV_LOG(ERR, "Configure tx and rx failed, dev_name: %s", + name); + goto cfg_rxtx_fail; + } + + /* open virtual port and ready to start packet receiving */ + rc = hinic_set_vport_enable(nic_dev->hwdev, true); + if (rc) { + PMD_DRV_LOG(ERR, "Enable vport failed, dev_name:%s", name); + goto en_vport_fail; + } + + /* open physical port and start packet receiving */ + rc = hinic_set_port_enable(nic_dev->hwdev, true); + if (rc) { + PMD_DRV_LOG(ERR, "Enable physical port failed, dev_name:%s", + name); + goto en_port_fail; + } + + /* update eth_dev link status */ + if (dev->data->dev_conf.intr_conf.lsc != 0) + (void)hinic_link_update(dev, 0); + + hinic_set_bit(HINIC_DEV_START, &nic_dev->dev_status); + + PMD_DRV_LOG(INFO, "Device %s started", name); + + return 0; + +en_port_fail: + (void)hinic_set_vport_enable(nic_dev->hwdev, false); + +en_vport_fail: + /* Flush tx && rx chip resources in case of set vport fake fail */ + (void)hinic_flush_qp_res(nic_dev->hwdev); + rte_delay_ms(100); + + hinic_remove_rxtx_configure(dev); + +cfg_rxtx_fail: +set_mtu_fail: +cfg_mq_mode_fail: + hinic_free_qp_ctxts(nic_dev->hwdev); + +init_qp_fail: + hinic_free_all_rx_mbuf(dev); + hinic_free_all_tx_mbuf(dev); + + return rc; +} + +/** + * DPDK callback to release the receive queue. + * + * @param queue + * Generic receive queue pointer. + */ +void hinic_rx_queue_release(void *queue) +{ + struct hinic_rxq *rxq = (struct hinic_rxq *)queue; + hinic_nic_dev *nic_dev; + + if (!rxq) { + PMD_DRV_LOG(WARNING, "Rxq is null when release"); + return; + } + nic_dev = (hinic_nic_dev *)rxq->nic_dev; + + /* free rxq_pkt mbuf */ + hinic_free_all_rx_skbs(rxq); + + /* free rxq_cqe, rxq_info */ + hinic_free_rx_resources(rxq); + + /* free root rq wq */ + hinic_destroy_rq(nic_dev, rxq->q_id); + + nic_dev->rxqs[rxq->q_id] = NULL; + + /* free rxq */ + rte_free(rxq); +} + +/** + * DPDK callback to release the transmit queue. + * + * @param queue + * Generic transmit queue pointer. + */ +void hinic_tx_queue_release(void *queue) +{ + struct hinic_txq *txq = (struct hinic_txq *)queue; + hinic_nic_dev *nic_dev; + + if (!txq) { + PMD_DRV_LOG(WARNING, "Txq is null when release"); + return; + } + nic_dev = (hinic_nic_dev *)txq->nic_dev; + + /* free txq_pkt mbuf */ + hinic_free_all_tx_skbs(txq); + + /* free txq_info */ + hinic_free_tx_resources(txq); + + /* free root sq wq */ + hinic_destroy_sq(nic_dev, txq->q_id); + nic_dev->txqs[txq->q_id] = NULL; + + /* free txq */ + rte_free(txq); +} + +/** + * Atomically reads the link status information from global + * structure rte_eth_dev. + */ +int hinic_dev_atomic_read_link_status(struct rte_eth_dev *dev, + struct rte_eth_link *link) +{ + struct rte_eth_link *dst = link; + struct rte_eth_link *src = &dev->data->dev_link; + + if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, + *(uint64_t *)src) == 0) + return HINIC_ERROR; + + return HINIC_OK; +} + +void hinic_free_all_rq(hinic_nic_dev *nic_dev) +{ + u16 q_id; + + for (q_id = 0; q_id < nic_dev->num_rq; q_id++) + hinic_destroy_rq(nic_dev, q_id); +} + +void hinic_free_all_sq(hinic_nic_dev *nic_dev) +{ + u16 q_id; + + for (q_id = 0; q_id < nic_dev->num_sq; q_id++) + hinic_destroy_sq(nic_dev, q_id); +} + +/** + * DPDK callback to stop the device. + * + * @param dev + * Pointer to Ethernet device structure. + */ +void hinic_dev_stop(struct rte_eth_dev *dev) +{ + int rc; + char *name; + uint16_t port_id; + hinic_nic_dev *nic_dev; + struct rte_eth_link link; + + nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + name = dev->data->name; + port_id = dev->data->port_id; + + if (!hinic_test_and_clear_bit(HINIC_DEV_START, &nic_dev->dev_status)) { + PMD_DRV_LOG(INFO, "Device %s already stopped", name); + return; + } + + /* just stop phy port and vport */ + rc = hinic_set_port_enable(nic_dev->hwdev, false); + if (rc) + PMD_DRV_LOG(WARNING, "Disable phy port failed, error: %d, dev_name:%s, port_id:%d", + rc, name, port_id); + + rc = hinic_set_vport_enable(nic_dev->hwdev, false); + if (rc) + PMD_DRV_LOG(WARNING, "Disable vport failed, error: %d, dev_name:%s, port_id:%d", + rc, name, port_id); + + /* Clear recorded link status */ + memset(&link, 0, sizeof(link)); + (void)hinic_dev_atomic_write_link_status(dev, &link); + + /* flush pending io request */ + rc = hinic_rx_tx_flush(nic_dev->hwdev); + if (rc) + PMD_DRV_LOG(WARNING, "Flush pending io failed, error: %d, dev_name: %s, port_id: %d", + rc, name, port_id); + + /* clean rss table and rx_mode */ + hinic_remove_rxtx_configure(dev); + + /* clean root context */ + hinic_free_qp_ctxts(nic_dev->hwdev); + + /* free mbuf */ + hinic_free_all_rx_mbuf(dev); + hinic_free_all_tx_mbuf(dev); + + PMD_DRV_LOG(INFO, "Device %s stopped", name); +} + +void hinic_disable_interrupt(struct rte_eth_dev *dev) +{ + hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); + int ret, retries = 0; + + hinic_clear_bit(HINIC_DEV_INTR_EN, &nic_dev->dev_status); + + /* disable msix interrupt in hardware */ + hinic_set_msix_state(nic_dev->hwdev, 0, HINIC_MSIX_DISABLE); + + /* disable rte interrupt */ + ret = rte_intr_disable(&pci_dev->intr_handle); + if (ret) + PMD_DRV_LOG(ERR, "Disable intr failed: %d", ret); + + do { + ret = + rte_intr_callback_unregister(&pci_dev->intr_handle, + hinic_dev_interrupt_handler, dev); + if (ret >= 0) { + break; + } else if (ret == -EAGAIN) { + rte_delay_ms(100); + retries++; + } else { + PMD_DRV_LOG(ERR, "intr callback unregister failed: %d", + ret); + break; + } + } while (retries < HINIC_INTR_CB_UNREG_MAX_RETRIES); + + if (retries == HINIC_INTR_CB_UNREG_MAX_RETRIES) + PMD_DRV_LOG(ERR, "Unregister intr callback failed after %d retries", + retries); +} + +/** + * DPDK callback to close the device. + * + * @param dev + * Pointer to Ethernet device structure. + */ +void hinic_dev_close(struct rte_eth_dev *dev) +{ + char *name; + hinic_nic_dev *nic_dev; + + nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + name = dev->data->name; + + if (hinic_test_and_set_bit(HINIC_DEV_CLOSE, &nic_dev->dev_status)) { + PMD_DRV_LOG(INFO, "Device %s already closed", name); + return; + } + + /* stop device first */ + hinic_dev_stop(dev); + + /* rx_cqe, rx_info */ + hinic_free_all_rx_resources(dev); + + /* tx_info */ + hinic_free_all_tx_resources(dev); + + /* free wq, pi_dma_addr */ + hinic_free_all_rq(nic_dev); + + /* free wq, db_addr */ + hinic_free_all_sq(nic_dev); + + /* deinit mac vlan tbl */ + hinic_deinit_mac_addr(dev); + + /* disable hardware and uio interrupt */ + hinic_disable_interrupt(dev); + + /* deinit nic hardware device */ + hinic_nic_dev_destroy(dev); + + PMD_DRV_LOG(INFO, "Device %s closed", name); +} + +static int hinic_priv_get_dev_link_status(hinic_nic_dev *nic_dev, + struct rte_eth_link *link) +{ + int rc = HINIC_OK; + u8 port_link_status = 0; + struct nic_port_info port_link_info; + struct hinic_hwdev *nic_hwdev = nic_dev->hwdev; + uint32_t port_speed[LINK_SPEED_MAX] = {ETH_SPEED_NUM_10M, + ETH_SPEED_NUM_100M, ETH_SPEED_NUM_1G, + ETH_SPEED_NUM_10G, ETH_SPEED_NUM_25G, + ETH_SPEED_NUM_40G, ETH_SPEED_NUM_100G}; + + memset(link, 0, sizeof(*link)); + rc = hinic_get_link_status(nic_hwdev, &port_link_status); + if (rc) + return rc; + + nic_dev->link_status = port_link_status; + if (!port_link_status) { + link->link_status = ETH_LINK_DOWN; + link->link_speed = 0; + link->link_duplex = ETH_LINK_HALF_DUPLEX; + link->link_autoneg = ETH_LINK_FIXED; + return rc; + } + + memset(&port_link_info, 0, sizeof(port_link_info)); + rc = hinic_get_port_info(nic_hwdev, &port_link_info); + if (rc) + return rc; + + link->link_speed = port_speed[port_link_info.speed % LINK_SPEED_MAX]; + link->link_duplex = port_link_info.duplex; + link->link_autoneg = port_link_info.autoneg_state; + link->link_status = port_link_status; + + return rc; +} + +static int hinic_priv_set_dev_promiscuous(hinic_nic_dev *nic_dev, bool enable) +{ + u32 rx_mode_ctrl = nic_dev->rx_mode_status; + + if (enable) + rx_mode_ctrl |= HINIC_RX_MODE_PROMISC; + else + rx_mode_ctrl &= (~HINIC_RX_MODE_PROMISC); + + return hinic_config_rx_mode(nic_dev, rx_mode_ctrl); +} + +/** + * DPDK callback to get device statistics. + * + * @param dev + * Pointer to Ethernet device structure. + * @param stats + * Stats structure output buffer. + * + * @return + * 0 on success and stats is filled, + * negative error value otherwise. + */ +int hinic_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) +{ + int i, err, q_num; + u64 rx_discards_pmd = 0; + hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + struct hinic_vport_stats vport_stats; + struct hinic_rxq *rxq = NULL; + struct hinic_rxq_stats rxq_stats; + struct hinic_txq *txq = NULL; + struct hinic_txq_stats txq_stats; + + err = hinic_get_vport_stats(nic_dev->hwdev, &vport_stats); + if (err) { + PMD_DRV_LOG(ERR, "Get vport stats from fw failed, nic_dev: %s", + nic_dev->proc_dev_name); + return err; + } + + dev->data->rx_mbuf_alloc_failed = 0; + + /* rx queue stats */ + q_num = (nic_dev->num_rq < RTE_ETHDEV_QUEUE_STAT_CNTRS) ? + nic_dev->num_rq : RTE_ETHDEV_QUEUE_STAT_CNTRS; + for (i = 0; i < q_num; i++) { + rxq = nic_dev->rxqs[i]; + hinic_rxq_get_stats(rxq, &rxq_stats); + stats->q_ipackets[i] = rxq_stats.packets; + stats->q_ibytes[i] = rxq_stats.bytes; + stats->q_errors[i] = rxq_stats.rx_discards; + + stats->ierrors += rxq_stats.errors; + rx_discards_pmd += rxq_stats.rx_discards; + dev->data->rx_mbuf_alloc_failed += rxq_stats.rx_nombuf; + } + + /* tx queue stats */ + q_num = (nic_dev->num_sq < RTE_ETHDEV_QUEUE_STAT_CNTRS) ? + nic_dev->num_sq : RTE_ETHDEV_QUEUE_STAT_CNTRS; + for (i = 0; i < q_num; i++) { + txq = nic_dev->txqs[i]; + hinic_txq_get_stats(txq, &txq_stats); + stats->q_opackets[i] = txq_stats.packets; + stats->q_obytes[i] = txq_stats.bytes; + stats->oerrors += (txq_stats.tx_busy + txq_stats.off_errs); + } + + /* vport stats */ + stats->oerrors += vport_stats.tx_discard_vport; + + stats->imissed = vport_stats.rx_discard_vport + rx_discards_pmd; + + stats->ipackets = (vport_stats.rx_unicast_pkts_vport + + vport_stats.rx_multicast_pkts_vport + + vport_stats.rx_broadcast_pkts_vport - + rx_discards_pmd); + + stats->opackets = (vport_stats.tx_unicast_pkts_vport + + vport_stats.tx_multicast_pkts_vport + + vport_stats.tx_broadcast_pkts_vport); + + stats->ibytes = (vport_stats.rx_unicast_bytes_vport + + vport_stats.rx_multicast_bytes_vport + + vport_stats.rx_broadcast_bytes_vport); + + stats->obytes = (vport_stats.tx_unicast_bytes_vport + + vport_stats.tx_multicast_bytes_vport + + vport_stats.tx_broadcast_bytes_vport); + return 0; +} + +/** + * DPDK callback to clear device statistics. + * + * @param dev + * Pointer to Ethernet device structure. + */ +void hinic_dev_stats_reset(struct rte_eth_dev *dev) +{ + int qid; + struct hinic_rxq *rxq = NULL; + struct hinic_txq *txq = NULL; + hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + + hinic_clear_vport_stats(nic_dev->hwdev); + + for (qid = 0; qid < nic_dev->num_rq; qid++) { + rxq = nic_dev->rxqs[qid]; + hinic_rxq_stats_reset(rxq); + } + + for (qid = 0; qid < nic_dev->num_sq; qid++) { + txq = nic_dev->txqs[qid]; + hinic_txq_stats_reset(txq); + } +} + +/** + * DPDK callback to clear device extended statistics. + * + * @param dev + * Pointer to Ethernet device structure. + **/ +void hinic_dev_xstats_reset(struct rte_eth_dev *dev) +{ + hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + + hinic_dev_stats_reset(dev); + + if (hinic_func_type(nic_dev->hwdev) != TYPE_VF) + hinic_clear_phy_port_stats(nic_dev->hwdev); +} + +static void hinic_gen_random_mac_addr(struct ether_addr *mac_addr) +{ + uint64_t random_value; + + /* Set Organizationally Unique Identifier (OUI) prefix */ + mac_addr->addr_bytes[0] = 0x00; + mac_addr->addr_bytes[1] = 0x09; + mac_addr->addr_bytes[2] = 0xC0; + /* Force indication of locally assigned MAC address. */ + mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR; + /* Generate the last 3 bytes of the MAC address with a random number. */ + random_value = rte_rand(); + memcpy(&mac_addr->addr_bytes[3], &random_value, 3); +} + +/** + * Init mac_vlan table in NIC. + * + * @param dev + * Pointer to Ethernet device structure. + * + * @return + * 0 on success and stats is filled, + * negative error value otherwise. + */ +static int hinic_init_mac_addr(struct rte_eth_dev *eth_dev) +{ + int rc = 0; + hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev); + uint8_t addr_bytes[ETHER_ADDR_LEN]; + u16 func_id = 0; + + rc = hinic_get_default_mac(nic_dev->hwdev, addr_bytes); + if (rc) + return rc; + + ether_addr_copy((struct ether_addr *)addr_bytes, + eth_dev->data->mac_addrs); + + if (is_zero_ether_addr(eth_dev->data->mac_addrs)) + hinic_gen_random_mac_addr(eth_dev->data->mac_addrs); + + func_id = hinic_global_func_id(nic_dev->hwdev); + rc = hinic_set_mac(nic_dev->hwdev, eth_dev->data->mac_addrs->addr_bytes, + 0, func_id); + if (rc && rc != HINIC_PF_SET_VF_ALREADY) + return rc; + + return 0; +} + +/** + * Deinit mac_vlan table in NIC. + * + * @param dev + * Pointer to Ethernet device structure. + * + * @return + * 0 on success and stats is filled, + * negative error value otherwise. + */ +static void hinic_deinit_mac_addr(struct rte_eth_dev *eth_dev) +{ + hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev); + int rc; + u16 func_id = 0; + + if (is_zero_ether_addr(eth_dev->data->mac_addrs)) + return; + + func_id = hinic_global_func_id(nic_dev->hwdev); + rc = hinic_del_mac(nic_dev->hwdev, + eth_dev->data->mac_addrs->addr_bytes, + 0, func_id); + if (rc && rc != HINIC_PF_SET_VF_ALREADY) + PMD_DRV_LOG(ERR, "Delete mac table failed, dev_name: %s", + eth_dev->data->name); +} + +/** + * DPDK callback to retrieve physical link information. + * + * @param dev + * Pointer to Ethernet device structure. + * @param wait_to_complete + * Wait for request completion. + * + * @return + * 0 link status changed, -1 link status not changed + */ +int hinic_link_update(struct rte_eth_dev *dev, int wait_to_complete) +{ +#define CHECK_INTERVAL 10 /* 10ms */ +#define MAX_REPEAT_TIME 100 /* 1s (100 * 10ms) in total */ + int rc = HINIC_OK; + struct rte_eth_link new_link, old_link; + hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + unsigned int rep_cnt = MAX_REPEAT_TIME; + + memset(&old_link, 0, sizeof(old_link)); + memset(&new_link, 0, sizeof(new_link)); + (void)hinic_dev_atomic_read_link_status(dev, &old_link); + + do { + /* Get link status information from hardware */ + rc = hinic_priv_get_dev_link_status(nic_dev, &new_link); + if (rc != HINIC_OK) { + new_link.link_speed = ETH_SPEED_NUM_NONE; + new_link.link_duplex = ETH_LINK_FULL_DUPLEX; + PMD_DRV_LOG(ERR, "Get link status failed"); + goto out; + } + + if (!wait_to_complete) + break; + + rte_delay_ms(CHECK_INTERVAL); + } while (!new_link.link_status && rep_cnt--); + +out: + (void)hinic_dev_atomic_write_link_status(dev, &new_link); + + if (old_link.link_status == new_link.link_status) + return HINIC_ERROR; + + PMD_DRV_LOG(INFO, "Device %s link status change from %s to %s", + nic_dev->proc_dev_name, + (old_link.link_status ? "UP" : "DOWN"), + (new_link.link_status ? "UP" : "DOWN")); + + return HINIC_OK; +} + +/** + * DPDK callback to enable promiscuous mode. + * + * @param dev + * Pointer to Ethernet device structure. + */ +void hinic_dev_promiscuous_enable(struct rte_eth_dev *dev) +{ + int rc = HINIC_OK; + hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + + PMD_DRV_LOG(INFO, "Enable promiscuous, nic_dev: %s, port_id: %d, promisc: %d", + nic_dev->proc_dev_name, dev->data->port_id, + dev->data->promiscuous); + + rc = hinic_priv_set_dev_promiscuous(nic_dev, true); + if (rc) + PMD_DRV_LOG(ERR, "Enable promiscuous failed"); +} + +/** + * DPDK callback to disable promiscuous mode. + * + * @param dev + * Pointer to Ethernet device structure. + */ +void hinic_dev_promiscuous_disable(struct rte_eth_dev *dev) +{ + int rc = HINIC_OK; + hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + + PMD_DRV_LOG(INFO, "Disable promiscuous, nic_dev: %s, port_id: %d, promisc: %d", + nic_dev->proc_dev_name, dev->data->port_id, + dev->data->promiscuous); + + rc = hinic_priv_set_dev_promiscuous(nic_dev, false); + if (rc) + PMD_DRV_LOG(ERR, "Disable promiscuous failed"); +} + +/** + * DPDK callback to update the RSS hash key and RSS hash type. + * + * @param dev + * Pointer to Ethernet device structure. + * @param rss_conf + * RSS configuration data. + * + * @return + * 0 on success, negative error value otherwise. + */ +int hinic_rss_hash_update(struct rte_eth_dev *dev, + struct rte_eth_rss_conf *rss_conf) +{ + hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + u8 tmpl_idx = nic_dev->rss_tmpl_idx; + u8 hashkey[HINIC_RSS_KEY_SIZE] = {0}; + u8 prio_tc[HINIC_DCB_UP_MAX] = {0}; + u64 rss_hf = rss_conf->rss_hf; + struct nic_rss_type rss_type = {0}; + int err = 0; + + PMD_DRV_LOG(INFO, "rss info, rss_flag:0x%x, rss_key_len:%d, rss_hf:%lu, tmpl_idx:%d", + nic_dev->flags, rss_conf->rss_key_len, rss_hf, tmpl_idx); + + if (!(nic_dev->flags & ETH_MQ_RX_RSS_FLAG)) { + PMD_DRV_LOG(INFO, "RSS is not enabled"); + return HINIC_OK; + } + + if (rss_conf->rss_key_len > HINIC_RSS_KEY_SIZE) { + PMD_DRV_LOG(ERR, "Invalid rss key, rss_key_len:%d", + rss_conf->rss_key_len); + return HINIC_ERROR; + } + + if (rss_conf->rss_key) { + memcpy(hashkey, rss_conf->rss_key, rss_conf->rss_key_len); + err = hinic_rss_set_template_tbl(nic_dev->hwdev, tmpl_idx, + hashkey); + if (err) { + PMD_DRV_LOG(ERR, "Set rss template table failed"); + goto disable_rss; + } + } + + rss_type.ipv4 = (rss_hf & (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4)) ? 1 : 0; + rss_type.tcp_ipv4 = (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) ? 1 : 0; + rss_type.ipv6 = (rss_hf & (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6)) ? 1 : 0; + rss_type.ipv6_ext = (rss_hf & ETH_RSS_IPV6_EX) ? 1 : 0; + rss_type.tcp_ipv6 = (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) ? 1 : 0; + rss_type.tcp_ipv6_ext = (rss_hf & ETH_RSS_IPV6_TCP_EX) ? 1 : 0; + rss_type.udp_ipv4 = (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) ? 1 : 0; + rss_type.udp_ipv6 = (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) ? 1 : 0; + + err = hinic_set_rss_type(nic_dev->hwdev, tmpl_idx, rss_type); + if (err) { + PMD_DRV_LOG(ERR, "Set rss type table failed"); + goto disable_rss; + } + + return 0; + +disable_rss: + memset(prio_tc, 0, sizeof(prio_tc)); + (void)hinic_rss_cfg(nic_dev->hwdev, 0, tmpl_idx, 0, prio_tc); + return err; +} + +/** + * DPDK callback to get the RSS hash configuration. + * + * @param dev + * Pointer to Ethernet device structure. + * @param rss_conf + * RSS configuration data. + * + * @return + * 0 on success, negative error value otherwise. + */ +int hinic_rss_conf_get(struct rte_eth_dev *dev, + struct rte_eth_rss_conf *rss_conf) +{ + hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + u8 tmpl_idx = nic_dev->rss_tmpl_idx; + u8 hashkey[HINIC_RSS_KEY_SIZE] = {0}; + struct nic_rss_type rss_type = {0}; + int err; + + if (!(nic_dev->flags & ETH_MQ_RX_RSS_FLAG)) { + PMD_DRV_LOG(INFO, "RSS is not enabled"); + return HINIC_ERROR; + } + + err = hinic_rss_get_template_tbl(nic_dev->hwdev, tmpl_idx, hashkey); + if (err) + return err; + + if (rss_conf->rss_key && + rss_conf->rss_key_len >= HINIC_RSS_KEY_SIZE) { + memcpy(rss_conf->rss_key, hashkey, sizeof(hashkey)); + rss_conf->rss_key_len = sizeof(hashkey); + } + + err = hinic_get_rss_type(nic_dev->hwdev, tmpl_idx, &rss_type); + if (err) + return err; + + rss_conf->rss_hf = 0; + rss_conf->rss_hf |= rss_type.ipv4 ? + (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4) : 0; + rss_conf->rss_hf |= rss_type.tcp_ipv4 ? ETH_RSS_NONFRAG_IPV4_TCP : 0; + rss_conf->rss_hf |= rss_type.ipv6 ? + (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6) : 0; + rss_conf->rss_hf |= rss_type.ipv6_ext ? ETH_RSS_IPV6_EX : 0; + rss_conf->rss_hf |= rss_type.tcp_ipv6 ? ETH_RSS_NONFRAG_IPV6_TCP : 0; + rss_conf->rss_hf |= rss_type.tcp_ipv6_ext ? ETH_RSS_IPV6_TCP_EX : 0; + rss_conf->rss_hf |= rss_type.udp_ipv4 ? ETH_RSS_NONFRAG_IPV4_UDP : 0; + rss_conf->rss_hf |= rss_type.udp_ipv6 ? ETH_RSS_NONFRAG_IPV6_UDP : 0; + + return HINIC_OK; +} + +/** + * DPDK callback to update the RETA indirection table. + * + * @param dev + * Pointer to Ethernet device structure. + * @param reta_conf + * Pointer to RETA configuration structure array. + * @param reta_size + * Size of the RETA table. + * + * @return + * 0 on success, negative error value otherwise. + */ +int hinic_rss_indirtbl_update(struct rte_eth_dev *dev, + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size) +{ + hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + u8 tmpl_idx = nic_dev->rss_tmpl_idx; + u8 prio_tc[HINIC_DCB_UP_MAX] = {0}; + u32 indirtbl[NIC_RSS_INDIR_SIZE] = {0}; + int err = 0; + u16 i = 0; + u16 idx, shift; + + PMD_DRV_LOG(INFO, "Update indirect table, rss_flag:0x%x, reta_size:%d, tmpl_idx:%d", + nic_dev->flags, reta_size, tmpl_idx); + + if (!(nic_dev->flags & ETH_MQ_RX_RSS_FLAG)) + return HINIC_OK; + + if (reta_size != NIC_RSS_INDIR_SIZE) { + PMD_DRV_LOG(ERR, "Invalid reta size, reta_size:%d", reta_size); + return HINIC_ERROR; + } + + err = hinic_rss_get_indir_tbl(nic_dev->hwdev, tmpl_idx, indirtbl); + if (err) + return err; + + /* update rss indir_tbl */ + for (i = 0; i < reta_size; i++) { + idx = i / RTE_RETA_GROUP_SIZE; + shift = i % RTE_RETA_GROUP_SIZE; + if (reta_conf[idx].mask & (1ULL << shift)) + indirtbl[i] = reta_conf[idx].reta[shift]; + } + + for (i = 0 ; i < reta_size; i++) { + if (indirtbl[i] >= nic_dev->num_rq) { + PMD_DRV_LOG(ERR, "Invalid reta entry, index:%d, num_rq:%d", + i, nic_dev->num_rq); + goto disable_rss; + } + } + + err = hinic_rss_set_indir_tbl(nic_dev->hwdev, tmpl_idx, indirtbl); + if (err) + goto disable_rss; + + nic_dev->rss_indir_flag = true; + + return 0; + +disable_rss: + memset(prio_tc, 0, sizeof(prio_tc)); + (void)hinic_rss_cfg(nic_dev->hwdev, 0, tmpl_idx, 0, prio_tc); + + return HINIC_ERROR; +} + + +/** + * DPDK callback to get the RETA indirection table. + * + * @param dev + * Pointer to Ethernet device structure. + * @param reta_conf + * Pointer to RETA configuration structure array. + * @param reta_size + * Size of the RETA table. + * + * @return + * 0 on success, negative error value otherwise. + */ +int hinic_rss_indirtbl_query(struct rte_eth_dev *dev, + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size) +{ + hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + u8 tmpl_idx = nic_dev->rss_tmpl_idx; + int err = 0; + u32 indirtbl[NIC_RSS_INDIR_SIZE] = {0}; + u16 idx, shift; + u16 i = 0; + + if (reta_size != NIC_RSS_INDIR_SIZE) { + PMD_DRV_LOG(ERR, "Invalid reta size, reta_size:%d", reta_size); + return HINIC_ERROR; + } + + err = hinic_rss_get_indir_tbl(nic_dev->hwdev, tmpl_idx, indirtbl); + if (err) { + PMD_DRV_LOG(ERR, "Get rss indirect table failed, error:%d", + err); + return err; + } + + for (i = 0; i < reta_size; i++) { + idx = i / RTE_RETA_GROUP_SIZE; + shift = i % RTE_RETA_GROUP_SIZE; + if (reta_conf[idx].mask & (1ULL << shift)) + reta_conf[idx].reta[shift] = (uint16_t)indirtbl[i]; + } + + return HINIC_OK; +} + +/** + * DPDK callback to get extended device statistics. + * + * @param dev + * Pointer to Ethernet device. + * @param xstats + * Pointer to rte extended stats table. + * @param n + * The size of the stats table. + * + * @return + * Number of extended stats on success and stats is filled, + * negative error value otherwise. + */ +int hinic_dev_xstats_get(struct rte_eth_dev *dev, + struct rte_eth_xstat *xstats, + unsigned int n) +{ + u16 qid = 0; + u32 i; + int err, count; + hinic_nic_dev *nic_dev; + struct hinic_phy_port_stats port_stats; + struct hinic_vport_stats vport_stats; + struct hinic_rxq *rxq = NULL; + struct hinic_rxq_stats rxq_stats; + struct hinic_txq *txq = NULL; + struct hinic_txq_stats txq_stats; + + nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + count = hinic_xstats_calc_num(nic_dev); + if ((int)n < count) + return count; + + count = 0; + + /* Get stats from hinic_rxq_stats */ + for (qid = 0; qid < nic_dev->num_rq; qid++) { + rxq = nic_dev->rxqs[qid]; + hinic_rxq_get_stats(rxq, &rxq_stats); + + for (i = 0; i < HINIC_RXQ_XSTATS_NUM; i++) { + xstats[count].value = + *(uint64_t *)(((char *)&rxq_stats) + + hinic_rxq_stats_strings[i].offset); + xstats[count].id = count; + count++; + } + } + + /* Get stats from hinic_txq_stats */ + for (qid = 0; qid < nic_dev->num_sq; qid++) { + txq = nic_dev->txqs[qid]; + hinic_txq_get_stats(txq, &txq_stats); + + for (i = 0; i < HINIC_TXQ_XSTATS_NUM; i++) { + xstats[count].value = + *(uint64_t *)(((char *)&txq_stats) + + hinic_txq_stats_strings[i].offset); + xstats[count].id = count; + count++; + } + } + + /* Get stats from hinic_vport_stats */ + err = hinic_get_vport_stats(nic_dev->hwdev, &vport_stats); + if (err) + return err; + + for (i = 0; i < HINIC_VPORT_XSTATS_NUM; i++) { + xstats[count].value = + *(uint64_t *)(((char *)&vport_stats) + + hinic_vport_stats_strings[i].offset); + xstats[count].id = count; + count++; + } + + /* Get stats from hinic_phy_port_stats */ + err = hinic_get_phy_port_stats(nic_dev->hwdev, &port_stats); + if (err) + return err; + + for (i = 0; i < HINIC_PHYPORT_XSTATS_NUM; i++) { + xstats[count].value = *(uint64_t *)(((char *)&port_stats) + + hinic_phyport_stats_strings[i].offset); + xstats[count].id = count; + count++; + } + + return count; +} + +/** + * DPDK callback to retrieve names of extended device statistics + * + * @param dev + * Pointer to Ethernet device structure. + * @param xstats_names + * Buffer to insert names into. + * + * @return + * Number of xstats names. + */ +int hinic_dev_xstats_get_names(struct rte_eth_dev *dev, + struct rte_eth_xstat_name *xstats_names, + __rte_unused unsigned int limit) +{ + hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + int count = 0; + u16 i = 0, q_num; + + if (xstats_names == NULL) + return hinic_xstats_calc_num(nic_dev); + + /* get pmd rxq stats */ + for (q_num = 0; q_num < nic_dev->num_rq; q_num++) { + for (i = 0; i < HINIC_RXQ_XSTATS_NUM; i++) { + snprintf(xstats_names[count].name, + sizeof(xstats_names[count].name), + "rxq%d_%s_pmd", + q_num, hinic_rxq_stats_strings[i].name); + count++; + } + } + + /* get pmd txq stats */ + for (q_num = 0; q_num < nic_dev->num_sq; q_num++) { + for (i = 0; i < HINIC_TXQ_XSTATS_NUM; i++) { + snprintf(xstats_names[count].name, + sizeof(xstats_names[count].name), + "txq%d_%s_pmd", + q_num, hinic_txq_stats_strings[i].name); + count++; + } + } + + /* get vport stats */ + for (i = 0; i < HINIC_VPORT_XSTATS_NUM; i++) { + snprintf(xstats_names[count].name, + sizeof(xstats_names[count].name), + "%s", + hinic_vport_stats_strings[i].name); + count++; + } + + /* get phy port stats */ + for (i = 0; i < HINIC_PHYPORT_XSTATS_NUM; i++) { + snprintf(xstats_names[count].name, + sizeof(xstats_names[count].name), + "%s", + hinic_phyport_stats_strings[i].name); + count++; + } + + return count; +} + +/** + * DPDK callback to get fw version + * + * @param dev + * Pointer to Ethernet device structure. + * @param fw_version + * Pointer to fw version structure. + * @param fw_size + * Size of fw version. + * + * @return + * Number of xstats names. + */ +int +hinic_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) +{ + hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); + struct hinic_fw_version fw_ver; + int ret; + + memset(&fw_ver, 0, sizeof(fw_ver)); + ret = hinic_get_fw_version(nic_dev->hwdev, &fw_ver); + if (ret) + return ret; + + ret = snprintf(fw_version, fw_size, "%s", fw_ver.microcode_ver); + ret += 1; /* add the size of '\0' */ + if (fw_size < (u32)ret) + return ret; + else + return 0; +} diff --git a/drivers/net/hinic/rte_pmd_hinic_version.map b/drivers/net/hinic/rte_pmd_hinic_version.map new file mode 100644 index 0000000..9a61188 --- /dev/null +++ b/drivers/net/hinic/rte_pmd_hinic_version.map @@ -0,0 +1,4 @@ +DPDK_19.08 { + + local: *; +};