From patchwork Tue Sep 30 09:59:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zaiyu Wang X-Patchwork-Id: 157114 X-Patchwork-Delegate: stephen@networkplumber.org Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2F4C94886F; Tue, 30 Sep 2025 12:00:23 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1D9F740695; Tue, 30 Sep 2025 12:00:23 +0200 (CEST) Received: from smtpbgsg2.qq.com (smtpbgsg2.qq.com [54.254.200.128]) by mails.dpdk.org (Postfix) with ESMTP id E070E400EF for ; Tue, 30 Sep 2025 12:00:21 +0200 (CEST) X-QQ-mid: esmtpgz13t1759226417t49405b59 X-QQ-Originating-IP: 59FyPKFMmYnqhPu2V+9YeKWDKDOHfBgIe6gqSpzDxKo= Received: from DSK-zaiyuwang.trustnetic.com ( [115.220.225.164]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 30 Sep 2025 18:00:02 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 8381111083825882056 EX-QQ-RecipientCnt: 4 From: Zaiyu Wang To: dev@dpdk.org Cc: Zaiyu Wang , Jiawen Wu , Jian Wang Subject: [PATCH v4 01/20] net/txgbe: add basic information for Amber-Lite 25G/40G NICs Date: Tue, 30 Sep 2025 17:59:33 +0800 Message-Id: <20250930095953.18508-2-zaiyuwang@trustnetic.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20250930095953.18508-1-zaiyuwang@trustnetic.com> References: <20250418094131.24136-1-zaiyuwang@trustnetic.com> <20250930095953.18508-1-zaiyuwang@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:trustnetic.com:qybglogicsvrgz:qybglogicsvrgz5a-1 X-QQ-XMAILINFO: MMz/ZfIG29K6zLYyVVc3u8O8XgSLBf/oFaG+n6qgajeN34Uk1w5b6W70 ULQdPtj2Itg86UFKnmBKTgLDti501t6WLpRUPzxE+EGTbHqlFn6cDdeUZqPmS863YyeQ0oj q3o0hgxRs3/iTl/PlEOPhK5O2Koc3jf1Mq+6+5QlTEVT4I5hn1RiQeKFkNiY0br3Tke8Mmo YTaFks8HldqNZx5bY3U9RduUKbUt6D8fhJqqNQhLOWyDB1Tz1shC55VHsAqDW7bKGQWYmx/ UGGzCbUKuFiYRlY++cw68rd6t+KuZDJKfaCieM/sObNS9m4ZtylD1s3g3sCfQsiZoJ+Kwtj qlJvhEEpgXianr3/dQ2jFK8AiQmrynea60UoUHRmlOUGRVBGPfH+KHHWuos3hlUH1JGf3Eu 2zt5J/dngzFwb47WLA/hHjcdf69loUQXN7DQkwO8N1sSobl6+b/wUviyXswvuTq2WKZyX26 fX9KeXpP0d836piWac1foQNuZfzAD4lkaOvhPMO0Kj1bVYjPK43Hr3mrH2VR0rUZyUa2vnS 3t5W2xOM/ZtezeDr+FZWYSZNPe6wldx8MrIpeXFnBq3F2C9/mD3kwXvnklnC1cmN0UxPU5A tI7LC6FUuWSygaMKakR1G7SyFMuhQVGsU2H60x0otyNH/NvL4zADHGAKIDXcy22/LOpLqB6 wE+yGZaTRxDq0k/tqdvSx0RO4LQxGGoDmZfoE2NVg9fTGDQXniJyk/rfI0q3y/NtYtYZKL0 RyJ0VXVNg4ojNXEmcU1e0+FtQxH2Kl+HcEn0vFWcPLOWDuLTi11h1JLGxFFamEn4ahGdoOV e+95MpYugNS51cDWi6yqu9VLlkmR2nWUSQyr114qSAW1e9lbKw/XF/n6LTxqSaVP+vIJGKO Vg6Q8Q7tIYjWnqyQLH9MF4ewW8LiorXRbHhKbIZ3zjQsMwAAILqcp4C7aHErgB2PN9A0YQ2 tIk/ALlYfYSJeTOsUZfKW98kGM1HJ1JVmSNdv4aWbilrsGefUTRxmjHtIF2ya+8Br0yQLtD HVZnhf03NBhmIoLFxQKn4IR4Jri5UvMMVlG/KF1YwMKD+qWVvbnaha6JesSmXIgoBbSC+v2 TZRU6ybspr1 X-QQ-XMRINFO: NI4Ajvh11aEj8Xl/2s1/T8w= X-QQ-RECHKSPAM: 0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add device IDs, speed and other basic information for Wangxun's new Amber-Lite NICs: aml (10G/25G) and aml40 (40G). Signed-off-by: Zaiyu Wang --- drivers/net/txgbe/base/txgbe_devids.h | 9 +++++++ drivers/net/txgbe/base/txgbe_hw.c | 17 +++++++++++++ drivers/net/txgbe/base/txgbe_regs.h | 4 ++- drivers/net/txgbe/base/txgbe_type.h | 3 +++ drivers/net/txgbe/txgbe_ethdev.c | 35 ++++++++++++++++++++------- 5 files changed, 58 insertions(+), 10 deletions(-) diff --git a/drivers/net/txgbe/base/txgbe_devids.h b/drivers/net/txgbe/base/txgbe_devids.h index a3f26eabf6..b7133c7d54 100644 --- a/drivers/net/txgbe/base/txgbe_devids.h +++ b/drivers/net/txgbe/base/txgbe_devids.h @@ -19,6 +19,15 @@ #define TXGBE_DEV_ID_WX1820 0x2001 #define TXGBE_DEV_ID_SP1000_VF 0x1000 #define TXGBE_DEV_ID_WX1820_VF 0x2000 +#define TXGBE_DEV_ID_AML 0x5000 +#define TXGBE_DEV_ID_AML5025 0x5025 +#define TXGBE_DEV_ID_AML5125 0x5125 +#define TXGBE_DEV_ID_AML5040 0x5040 +#define TXGBE_DEV_ID_AML5140 0x5140 + +#define TXGBE_DEV_ID_AML_VF 0x5001 +#define TXGBE_DEV_ID_AML5024_VF 0x5024 +#define TXGBE_DEV_ID_AML5124_VF 0x5124 /* * Subsystem IDs diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c index 42cd0e0e2c..76f8ecf62e 100644 --- a/drivers/net/txgbe/base/txgbe_hw.c +++ b/drivers/net/txgbe/base/txgbe_hw.c @@ -2476,6 +2476,8 @@ s32 txgbe_init_shared_code(struct txgbe_hw *hw) txgbe_init_ops_dummy(hw); switch (hw->mac.type) { case txgbe_mac_raptor: + case txgbe_mac_aml: + case txgbe_mac_aml40: status = txgbe_init_ops_pf(hw); break; case txgbe_mac_raptor_vf: @@ -2523,11 +2525,26 @@ s32 txgbe_set_mac_type(struct txgbe_hw *hw) case TXGBE_DEV_ID_WX1820: hw->mac.type = txgbe_mac_raptor; break; + case TXGBE_DEV_ID_AML: + case TXGBE_DEV_ID_AML5025: + case TXGBE_DEV_ID_AML5125: + hw->mac.type = txgbe_mac_aml; + break; + case TXGBE_DEV_ID_AML5040: + case TXGBE_DEV_ID_AML5140: + hw->mac.type = txgbe_mac_aml40; + break; case TXGBE_DEV_ID_SP1000_VF: case TXGBE_DEV_ID_WX1820_VF: hw->phy.media_type = txgbe_media_type_virtual; hw->mac.type = txgbe_mac_raptor_vf; break; + case TXGBE_DEV_ID_AML_VF: + case TXGBE_DEV_ID_AML5024_VF: + case TXGBE_DEV_ID_AML5124_VF: + hw->phy.media_type = txgbe_media_type_virtual; + hw->mac.type = txgbe_mac_aml_vf; + break; default: err = TXGBE_ERR_DEVICE_NOT_SUPPORTED; DEBUGOUT("Unsupported device id: %x", hw->device_id); diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h index 346c23b5da..8da976dcc4 100644 --- a/drivers/net/txgbe/base/txgbe_regs.h +++ b/drivers/net/txgbe/base/txgbe_regs.h @@ -97,7 +97,9 @@ #define TXGBE_LINK_SPEED_2_5GB_FULL 0x0400 #define TXGBE_LINK_SPEED_5GB_FULL 0x0800 #define TXGBE_LINK_SPEED_10GB_FULL 0x0080 -#define TXGBE_LINK_SPEED_40GB_FULL 0x0100 +#define TXGBE_LINK_SPEED_25GB_FULL 0x0100 +#define TXGBE_LINK_SPEED_40GB_FULL 0x0040 +#define TXGBE_LINK_SPEED_50GB_FULL 0x0200 #define TXGBE_AUTOC_AUTONEG MS64(63, 0x1) diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h index 65527a22e7..731a7b4373 100644 --- a/drivers/net/txgbe/base/txgbe_type.h +++ b/drivers/net/txgbe/base/txgbe_type.h @@ -140,7 +140,10 @@ enum txgbe_eeprom_type { enum txgbe_mac_type { txgbe_mac_unknown = 0, txgbe_mac_raptor, + txgbe_mac_aml, + txgbe_mac_aml40, txgbe_mac_raptor_vf, + txgbe_mac_aml_vf, txgbe_num_macs }; diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c index 580579094b..d49030357d 100644 --- a/drivers/net/txgbe/txgbe_ethdev.c +++ b/drivers/net/txgbe/txgbe_ethdev.c @@ -145,6 +145,11 @@ static void txgbe_l2_tunnel_conf(struct rte_eth_dev *dev); static const struct rte_pci_id pci_id_txgbe_map[] = { { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_SP1000) }, { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_AML) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_AML5025) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_AML5125) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_AML5040) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_AML5140) }, { .vendor_id = 0, /* sentinel */ }, }; @@ -1829,8 +1834,13 @@ txgbe_dev_start(struct rte_eth_dev *dev) if (err) goto error; - allowed_speeds = RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_1G | - RTE_ETH_LINK_SPEED_10G; + if (hw->mac.type == txgbe_mac_aml40) + allowed_speeds = RTE_ETH_LINK_SPEED_40G; + else if (hw->mac.type == txgbe_mac_aml) + allowed_speeds = RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_25G; + else + allowed_speeds = RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_1G | + RTE_ETH_LINK_SPEED_10G; link_speeds = &dev->data->dev_conf.link_speeds; if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) { @@ -1840,17 +1850,24 @@ txgbe_dev_start(struct rte_eth_dev *dev) speed = 0x0; if (*link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) { - speed = (TXGBE_LINK_SPEED_100M_FULL | - TXGBE_LINK_SPEED_1GB_FULL | - TXGBE_LINK_SPEED_10GB_FULL); + if (hw->mac.type == txgbe_mac_aml40) { + speed = TXGBE_LINK_SPEED_40GB_FULL; + } else if (hw->mac.type == txgbe_mac_aml) { + speed = (TXGBE_LINK_SPEED_10GB_FULL | + TXGBE_LINK_SPEED_25GB_FULL); + } else { + speed = (TXGBE_LINK_SPEED_100M_FULL | + TXGBE_LINK_SPEED_1GB_FULL | + TXGBE_LINK_SPEED_10GB_FULL); + } hw->autoneg = true; } else { + if (*link_speeds & RTE_ETH_LINK_SPEED_40G) + speed |= TXGBE_LINK_SPEED_40GB_FULL; + if (*link_speeds & RTE_ETH_LINK_SPEED_25G) + speed |= TXGBE_LINK_SPEED_25GB_FULL; if (*link_speeds & RTE_ETH_LINK_SPEED_10G) speed |= TXGBE_LINK_SPEED_10GB_FULL; - if (*link_speeds & RTE_ETH_LINK_SPEED_5G) - speed |= TXGBE_LINK_SPEED_5GB_FULL; - if (*link_speeds & RTE_ETH_LINK_SPEED_2_5G) - speed |= TXGBE_LINK_SPEED_2_5GB_FULL; if (*link_speeds & RTE_ETH_LINK_SPEED_1G) speed |= TXGBE_LINK_SPEED_1GB_FULL; if (*link_speeds & RTE_ETH_LINK_SPEED_100M) From patchwork Tue Sep 30 09:59:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zaiyu Wang X-Patchwork-Id: 157115 X-Patchwork-Delegate: stephen@networkplumber.org Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 26EC04886F; Tue, 30 Sep 2025 12:00:28 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1309440A67; Tue, 30 Sep 2025 12:00:27 +0200 (CEST) Received: from smtpbg154.qq.com (smtpbg154.qq.com [15.184.224.54]) by mails.dpdk.org (Postfix) with ESMTP id 0BFFA40150 for ; Tue, 30 Sep 2025 12:00:24 +0200 (CEST) X-QQ-mid: esmtpgz13t1759226419tb3a18220 X-QQ-Originating-IP: oIBqtwcRoMImKmWaHAMJyu7BNAIfYNc16hEJMsrZUH8= Received: from DSK-zaiyuwang.trustnetic.com ( [115.220.225.164]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 30 Sep 2025 18:00:18 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 9564367347419751474 EX-QQ-RecipientCnt: 4 From: Zaiyu Wang To: dev@dpdk.org Cc: Zaiyu Wang , Jiawen Wu , Jian Wang Subject: [PATCH v4 02/20] net/txgbe: add new SW-FW mailbox interface Date: Tue, 30 Sep 2025 17:59:34 +0800 Message-Id: <20250930095953.18508-3-zaiyuwang@trustnetic.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20250930095953.18508-1-zaiyuwang@trustnetic.com> References: <20250418094131.24136-1-zaiyuwang@trustnetic.com> <20250930095953.18508-1-zaiyuwang@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:trustnetic.com:qybglogicsvrgz:qybglogicsvrgz5a-1 X-QQ-XMAILINFO: N4WhQbLQyIqSIp83KxsxUFBxgME1huD3JVUJtEK+QF3c7Eeso1kkYDYE ZdoYYLw69aTBdr7Q/fQr/TdB154GqbPymdCHNXHerI8RKZ3I+OJ/IzISBc1sdQT521JwcDc JIAV7zTasmTIn+i0IDy1RILe4ONxVw2280AO7bNDvrSFpxakP72PAvg2YipAG7NCG4bgH5J s4zN7lTGzh7DO48s8RLWxER4wD3ljQjJa3C+WoPWhqM927G5fg3AsO5utRsFZ5rUBJkAnQ8 3gmO6pdxyK87k8ZSk7djJkv2/d3Ea4ageZys5dRqCIC/pMPGyx/IAcnKD6bcfbvWbmB3/3z QNhyBLOUJUMg+nbaH7jY6B0RFm8lDt04ikKksxpJvTFd9hwULjN0G5+EEhbfAiEXCPCYg33 ueEFttSW5KROz1KDn0pt0/bGwx7K7CBcnRfh6RAWdylFD1v00j3AVBc3SLMlm6XltLYADvk AyKRhPN2fN4oeh4uvL/jnM2pDmsNvOG3fpYpfeMWF12yp44GgqX9ZznbtgyNGedd8K9SokS OOYqMgmCAK9ZhFVxDd9hZDNYkZEjo7fUsAFUpjgAIvb2WcTHU5st2ge7C3dKk9Sw5/BeCu7 IBMB++axuAn1OMuSli8Equ3bbkM/9xnOkpsMkE2l59zuC/CU1lMfJgYgzdfwrLsSdnqdKUA tA5HbOa2mu/9EkJTIL7aAeMvrpUK/PVvdtz33Fr0ua+dymyafeDw7BPcTdnEdUhi+pcDhTa mKPgQu4AkUA2rx7vJsui1v9an5uv8MKME3AvDD5yvNqjMfdJDQPMZePku/kklN9/PgHaq8z UeyiSg+CKwXYg1P1j8y09QulTp9HmcaQOdbqfDGoeq9S5zb1Q7T480tmvw4+6D4Iq5Lmk/r 7jGcCH6ZD+/Yjg+wk3DsuCedtRbNIX5UxQe1nm7YiF8XOUAqPyuCODvsBaAwEyRYbWhemT8 eWmFC/uW70as0P3lLPgwUvZUd/nDBB5F/9C3A9rris6ADElUyU4U557NrAn6cVJSl1OYoFm wmXjuPVDAkyawVIEYtNUJnslh7NXiHS1WGNrRi+bY3V2lUUi2s X-QQ-XMRINFO: NyFYKkN4Ny6FSmKK/uo/jdU= X-QQ-RECHKSPAM: 0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Amber-Lite NICs adopt new mailbox interface for software-firmware interaion to enable enhanced functionality. Signed-off-by: Zaiyu Wang --- drivers/net/txgbe/base/txgbe_eeprom.c | 7 +- drivers/net/txgbe/base/txgbe_eeprom.h | 2 + drivers/net/txgbe/base/txgbe_mng.c | 148 +++++++++++++++++++++++--- drivers/net/txgbe/base/txgbe_mng.h | 17 ++- drivers/net/txgbe/base/txgbe_regs.h | 7 ++ drivers/net/txgbe/base/txgbe_type.h | 4 + 6 files changed, 165 insertions(+), 20 deletions(-) diff --git a/drivers/net/txgbe/base/txgbe_eeprom.c b/drivers/net/txgbe/base/txgbe_eeprom.c index aeeae06dfc..eb53b35a19 100644 --- a/drivers/net/txgbe/base/txgbe_eeprom.c +++ b/drivers/net/txgbe/base/txgbe_eeprom.c @@ -366,8 +366,13 @@ s32 txgbe_calc_eeprom_checksum(struct txgbe_hw *hw) err = hw->rom.readw_buffer(hw, i, seg, buffer); if (err) return err; - for (j = 0; j < seg; j++) + for (j = 0; j < seg; j++) { + if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) + if (((i + j) >= (TXGBE_SHOWROM_I2C_PTR / 2)) && + ((i + j) < (TXGBE_SHOWROM_I2C_END / 2))) + buffer[j] = 0xffff; checksum += buffer[j]; + } } checksum = (u16)TXGBE_EEPROM_SUM - checksum + read_checksum; diff --git a/drivers/net/txgbe/base/txgbe_eeprom.h b/drivers/net/txgbe/base/txgbe_eeprom.h index c10ad45ec8..26cc53ab42 100644 --- a/drivers/net/txgbe/base/txgbe_eeprom.h +++ b/drivers/net/txgbe/base/txgbe_eeprom.h @@ -20,6 +20,8 @@ #define TXGBE_PBANUM0_PTR 0x05 #define TXGBE_PBANUM1_PTR 0x06 #define TXGBE_SW_REGION_PTR 0x1C +#define TXGBE_SHOWROM_I2C_PTR 0xB00 +#define TXGBE_SHOWROM_I2C_END 0xF00 #define TXGBE_EE_CSUM_MAX 0x800 #define TXGBE_EEPROM_CHECKSUM 0x2F diff --git a/drivers/net/txgbe/base/txgbe_mng.c b/drivers/net/txgbe/base/txgbe_mng.c index 7dc8f21183..8839450b44 100644 --- a/drivers/net/txgbe/base/txgbe_mng.c +++ b/drivers/net/txgbe/base/txgbe_mng.c @@ -45,17 +45,6 @@ txgbe_hic_unlocked(struct txgbe_hw *hw, u32 *buffer, u32 length, u32 timeout) u32 value, loop; u16 i, dword_len; - if (!length || length > TXGBE_PMMBX_BSIZE) { - DEBUGOUT("Buffer length failure buffersize=%d.", length); - return TXGBE_ERR_HOST_INTERFACE_COMMAND; - } - - /* Calculate length in DWORDs. We must be DWORD aligned */ - if (length % sizeof(u32)) { - DEBUGOUT("Buffer length failure, not aligned to dword"); - return TXGBE_ERR_INVALID_ARGUMENT; - } - dword_len = length >> 2; txgbe_flush(hw); @@ -114,7 +103,7 @@ txgbe_host_interface_command(struct txgbe_hw *hw, u32 *buffer, u32 hdr_size = sizeof(struct txgbe_hic_hdr); struct txgbe_hic_hdr *resp = (struct txgbe_hic_hdr *)buffer; u16 buf_len; - s32 err; + s32 err = 0; u32 bi; u32 dword_len; @@ -123,6 +112,12 @@ txgbe_host_interface_command(struct txgbe_hw *hw, u32 *buffer, return TXGBE_ERR_HOST_INTERFACE_COMMAND; } + /* Calculate length in DWORDs. We must be DWORD aligned */ + if (length % sizeof(u32)) { + DEBUGOUT("Buffer length failure, not aligned to dword"); + return TXGBE_ERR_INVALID_ARGUMENT; + } + /* Take management host interface semaphore */ err = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWMBX); if (err) @@ -165,6 +160,117 @@ txgbe_host_interface_command(struct txgbe_hw *hw, u32 *buffer, return err; } +static s32 +txgbe_host_interface_command_aml(struct txgbe_hw *hw, u32 *buffer, + u32 length, u32 timeout, bool return_data) +{ + u32 hdr_size = sizeof(struct txgbe_hic_hdr); + struct txgbe_hic_hdr *resp = (struct txgbe_hic_hdr *)buffer; + struct txgbe_hic_hdr *recv_hdr; + u16 buf_len; + s32 err = 0; + u32 bi, i; + u32 dword_len; + u8 send_cmd; + + if (length == 0 || length > TXGBE_PMMBX_BSIZE) { + DEBUGOUT("Buffer length failure buffersize=%d.", length); + return TXGBE_ERR_HOST_INTERFACE_COMMAND; + } + + /* Calculate length in DWORDs. We must be DWORD aligned */ + if (length % sizeof(u32)) { + DEBUGOUT("Buffer length failure, not aligned to dword"); + return TXGBE_ERR_INVALID_ARGUMENT; + } + + /* try to get lock */ + while (rte_atomic32_test_and_set(&hw->swfw_busy)) { + timeout--; + if (!timeout) + return TXGBE_ERR_TIMEOUT; + usec_delay(1000); + } + + /* index to unique seq id for each mbox message */ + resp->index = hw->swfw_index; + send_cmd = resp->cmd; + + /* Calculate length in DWORDs */ + dword_len = length >> 2; + + /* write data to SW-FW mbox array */ + for (i = 0; i < dword_len; i++) { + wr32a(hw, TXGBE_AML_MNG_MBOX_SW2FW, + i, rte_cpu_to_le_32(buffer[i])); + /* write flush */ + rd32a(hw, TXGBE_AML_MNG_MBOX_SW2FW, i); + } + + /* amlite: generate interrupt to notify FW */ + wr32m(hw, TXGBE_AML_MNG_MBOX_CTL_SW2FW, + TXGBE_AML_MNG_MBOX_NOTIFY, 0); + wr32m(hw, TXGBE_AML_MNG_MBOX_CTL_SW2FW, + TXGBE_AML_MNG_MBOX_NOTIFY, TXGBE_AML_MNG_MBOX_NOTIFY); + + /* Calculate length in DWORDs */ + dword_len = hdr_size >> 2; + + /* polling reply from FW */ + timeout = 50; + do { + timeout--; + usec_delay(1000); + + /* read hdr */ + for (bi = 0; bi < dword_len; bi++) + buffer[bi] = rd32a(hw, TXGBE_AML_MNG_MBOX_FW2SW, bi); + + /* check hdr */ + recv_hdr = (struct txgbe_hic_hdr *)buffer; + + if (recv_hdr->cmd == send_cmd && + recv_hdr->index == hw->swfw_index) + break; + } while (timeout); + + if (!timeout) { + PMD_DRV_LOG(ERR, "Polling from FW messages timeout, cmd is 0x%x, index is %d", + send_cmd, hw->swfw_index); + err = TXGBE_ERR_TIMEOUT; + goto rel_out; + } + + /* expect no reply from FW then return */ + /* release lock if return */ + if (!return_data) + goto rel_out; + + /* If there is any thing in data position pull it in */ + buf_len = recv_hdr->buf_len; + if (buf_len == 0) + goto rel_out; + + if (length < buf_len + hdr_size) { + DEBUGOUT("Buffer not large enough for reply message."); + err = TXGBE_ERR_HOST_INTERFACE_COMMAND; + goto rel_out; + } + + /* Calculate length in DWORDs, add 3 for odd lengths */ + dword_len = (buf_len + 3) >> 2; + for (; bi <= dword_len; bi++) + buffer[bi] = rd32a(hw, TXGBE_AML_MNG_MBOX_FW2SW, bi); + +rel_out: + /* index++, index replace txgbe_hic_hdr.checksum */ + hw->swfw_index = resp->index == TXGBE_HIC_HDR_INDEX_MAX ? + 0 : resp->index + 1; + rte_atomic32_clear(&hw->swfw_busy); + + return err; +} + /** * txgbe_hic_sr_read - Read EEPROM word using a host interface cmd * assuming that the semaphore is already obtained. @@ -179,6 +285,12 @@ s32 txgbe_hic_sr_read(struct txgbe_hw *hw, u32 addr, u8 *buf, int len) struct txgbe_hic_read_shadow_ram command; u32 value; int err, i = 0, j = 0; + u32 mngmbx_addr; + + if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) + mngmbx_addr = TXGBE_AML_MNG_MBOX_FW2SW; + else + mngmbx_addr = TXGBE_MNGMBX; if (len > TXGBE_PMMBX_DATA_SIZE) return TXGBE_ERR_HOST_INTERFACE_COMMAND; @@ -191,18 +303,22 @@ s32 txgbe_hic_sr_read(struct txgbe_hw *hw, u32 addr, u8 *buf, int len) command.address = cpu_to_be32(addr); command.length = cpu_to_be16(len); - err = txgbe_hic_unlocked(hw, (u32 *)&command, - sizeof(command), TXGBE_HI_COMMAND_TIMEOUT); + if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) + err = txgbe_host_interface_command_aml(hw, (u32 *)&command, + sizeof(command), TXGBE_HI_COMMAND_TIMEOUT, false); + else + err = txgbe_hic_unlocked(hw, (u32 *)&command, + sizeof(command), TXGBE_HI_COMMAND_TIMEOUT); if (err) return err; while (i < (len >> 2)) { - value = rd32a(hw, TXGBE_MNGMBX, FW_NVM_DATA_OFFSET + i); + value = rd32a(hw, mngmbx_addr, FW_NVM_DATA_OFFSET + i); ((u32 *)buf)[i] = value; i++; } - value = rd32a(hw, TXGBE_MNGMBX, FW_NVM_DATA_OFFSET + i); + value = rd32a(hw, mngmbx_addr, FW_NVM_DATA_OFFSET + i); for (i <<= 2; i < len; i++) ((u8 *)buf)[i] = ((u8 *)&value)[j++]; diff --git a/drivers/net/txgbe/base/txgbe_mng.h b/drivers/net/txgbe/base/txgbe_mng.h index 16775862d6..613aa7b88a 100644 --- a/drivers/net/txgbe/base/txgbe_mng.h +++ b/drivers/net/txgbe/base/txgbe_mng.h @@ -60,6 +60,8 @@ #define TXGBE_CHECKSUM_CAP_ST_PASS 0x80658383 #define TXGBE_CHECKSUM_CAP_ST_FAIL 0x70657376 +#define TXGBE_HIC_HDR_INDEX_MAX 255 + /* Host Interface Command Structures */ struct txgbe_hic_hdr { u8 cmd; @@ -68,21 +70,30 @@ struct txgbe_hic_hdr { u8 cmd_resv; u8 ret_status; } cmd_or_resp; - u8 checksum; + union { + u8 checksum; + u8 index; + }; }; struct txgbe_hic_hdr2_req { u8 cmd; u8 buf_lenh; u8 buf_lenl; - u8 checksum; + union { + u8 checksum; + u8 index; + }; }; struct txgbe_hic_hdr2_rsp { u8 cmd; u8 buf_lenl; u8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */ - u8 checksum; + union { + u8 checksum; + u8 index; + }; }; union txgbe_hic_hdr2 { diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h index 8da976dcc4..3b0bf08ea2 100644 --- a/drivers/net/txgbe/base/txgbe_regs.h +++ b/drivers/net/txgbe/base/txgbe_regs.h @@ -263,6 +263,13 @@ #define TXGBE_MNGMBXCTL_FWACK MS(3, 0x1) #define TXGBE_MNGMBX 0x01E100 +/* amlite: swfw mailbox changes */ +#define TXGBE_AML_MNG_MBOX_CTL_SW2FW 0x01E0A0 +#define TXGBE_AML_MNG_MBOX_SW2FW 0x01E200 +#define TXGBE_AML_MNG_MBOX_CTL_FW2SW 0x01E0A4 +#define TXGBE_AML_MNG_MBOX_FW2SW 0x01E300 +#define TXGBE_AML_MNG_MBOX_NOTIFY MS(31, 0x1) + /****************************************************************************** * Port Registers ******************************************************************************/ diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h index 731a7b4373..a34c782ec8 100644 --- a/drivers/net/txgbe/base/txgbe_type.h +++ b/drivers/net/txgbe/base/txgbe_type.h @@ -814,6 +814,10 @@ struct txgbe_hw { u64 tx_qp_bytes; u64 rx_qp_mc_packets; } qp_last[TXGBE_MAX_QP]; + + /*amlite: new SW-FW mbox */ + u8 swfw_index; + rte_atomic32_t swfw_busy; }; struct txgbe_backplane_ability { From patchwork Tue Sep 30 09:59:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zaiyu Wang X-Patchwork-Id: 157116 X-Patchwork-Delegate: stephen@networkplumber.org Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3B8E54886F; Tue, 30 Sep 2025 12:00:35 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2CDC240A7F; Tue, 30 Sep 2025 12:00:30 +0200 (CEST) Received: from smtpbgsg2.qq.com (smtpbgsg2.qq.com [54.254.200.128]) by mails.dpdk.org (Postfix) with ESMTP id 2E77140A7F for ; Tue, 30 Sep 2025 12:00:27 +0200 (CEST) X-QQ-mid: esmtpgz13t1759226422t5f9d5c43 X-QQ-Originating-IP: jvjvvr3T8Xv/+QIvZqFPfndzTBpuMHliLEZiwG+Sx8Y= Received: from DSK-zaiyuwang.trustnetic.com ( [115.220.225.164]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 30 Sep 2025 18:00:21 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 11329806905909766861 EX-QQ-RecipientCnt: 4 From: Zaiyu Wang To: dev@dpdk.org Cc: Zaiyu Wang , Jiawen Wu , Jian Wang Subject: [PATCH v4 03/20] net/txgbe: add identification support for new SFP/QSFP modules Date: Tue, 30 Sep 2025 17:59:35 +0800 Message-Id: <20250930095953.18508-4-zaiyuwang@trustnetic.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20250930095953.18508-1-zaiyuwang@trustnetic.com> References: <20250418094131.24136-1-zaiyuwang@trustnetic.com> <20250930095953.18508-1-zaiyuwang@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:trustnetic.com:qybglogicsvrgz:qybglogicsvrgz5a-1 X-QQ-XMAILINFO: MzUsEJ4eXJ2k7McbtbrBlR59vzecZPf3e43UEolJ9UrJxxE+p2HwrAe7 746ibpc7ATpVCSYlbkt1p8adcRaUrN/unjKjK8WaN+PxeC9Y+jki6hpYuda4rK68NaBIw21 41mbZvDtOxp/bN17BW6EkT8AzygCm7TB2kpnorAQDoWyiP14CJI3OhSuyLXk0h6GTK0kHYq 2vE+eWjNiEtgark97InlZCHB3CsPgfTnfQU+HywrJ0XR9jiUwEGdcefQro4CcMIXnnGlsc5 41Wby633b0j7aXGPD2tUs2Ld78RI0AGA+WYGcE29aF5PYkv+G6oscOVgrK6QYxlOBgzI+qJ 2op0TC0pdb3pN3BmJ1G3jeXAUQXJOBSpj1jqLI3nAVqddkOHzejewZMODySCZiaeHJojZlI 4IErr9D5gYKlmtDU0Z9WcYQmta4O2mnI0NXSGuPDkAk+tTn5j6FQn5jm+/muN9KPrpDvwYi rBcqBmgBQZjDPpihZWcdJ9iM3RWiVB4FS7zQeNuCWo8k2p9CR4tCve2idEGxeFwDvFvPDHR c/K8OfEqtfzYiDzxH9+mdy3YyzRHeeEUDMmUy0WcwzrQ+hBPQRux5iIu/ofmxR+GJriiTn5 79iBquYws5KdP4zPFSTZnP/soyJU5R7x1WGouSntnCLWpjJRBwN4ydqMi+hXNLkgsy1/K97 qzsZJ5bGXGIU+SWwZDMzyE1DvgIKW4ybHPC6H044fONzfGpmMxhkRr79ytFYitHWHBsu3pf jZIf9vsTNenD2hrx3gsBTylS0ptY9LLv1xSXWgPRtBC4QpyAN9nRi/UPDYn/p3plNAbVaU6 WtlHnrM+ZTGmw/vD2twg1MCmINgVTB9Hh/N8TvBOrFaHHZbItzdy/5RctaJdx4228NPBeW+ 68mVnYcm3576J3zsLJ9vG3NBWQR2K2+B1n4gszIJ/nMmnKuKsEL0KnRVtpNPwuQ8HwTjUG+ cOcFZ4wVe7q9kibr8l4sYH7gLIK/RkaQ8O7D4wTMoAdpjgfVVSTHVK/zbKGluxJT/S8Uk/b H0yqqiGcEADtcfLrvZ2LtnsC5XTeB0ABQOWGkm49ovtR3kCzGhCM+B7H17E48onZ5X9FzGZ A== X-QQ-XMRINFO: NS+P29fieYNw95Bth2bWPxk= X-QQ-RECHKSPAM: 0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add identification support for new SFP/QSFP module types (e.g., 25G SR/CR) in the Amber-Lite NIC configuration flow. Signed-off-by: Zaiyu Wang --- drivers/net/txgbe/base/txgbe_phy.c | 92 ++++++++++++++++++++++++----- drivers/net/txgbe/base/txgbe_phy.h | 23 ++++++++ drivers/net/txgbe/base/txgbe_regs.h | 5 +- drivers/net/txgbe/base/txgbe_type.h | 12 ++++ 4 files changed, 117 insertions(+), 15 deletions(-) diff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c index ce6882e262..81e9aee295 100644 --- a/drivers/net/txgbe/base/txgbe_phy.c +++ b/drivers/net/txgbe/base/txgbe_phy.c @@ -774,10 +774,21 @@ s32 txgbe_identify_sfp_module(struct txgbe_hw *hw) u8 identifier = 0; u8 comp_codes_1g = 0; u8 comp_codes_10g = 0; + u8 comp_codes_25g = 0; + u8 comp_copper_len = 0; u8 oui_bytes[3] = {0, 0, 0}; u8 cable_tech = 0; u8 cable_spec = 0; u16 enforce_sfp = 0; + u32 value; + + if (hw->mac.type == txgbe_mac_aml) { + value = rd32(hw, TXGBE_GPIOEXT); + if (value & TXGBE_SFP1_MOD_ABS_LS) { + hw->phy.sfp_type = txgbe_sfp_type_not_present; + return TXGBE_ERR_SFP_NOT_PRESENT; + } + } if (hw->phy.media_type != txgbe_media_type_fiber) { hw->phy.sfp_type = txgbe_sfp_type_not_present; @@ -811,6 +822,16 @@ s32 txgbe_identify_sfp_module(struct txgbe_hw *hw) if (err != 0) goto ERR_I2C; + err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_25GBE_COMP_CODES, + &comp_codes_25g); + if (err != 0) + goto ERR_I2C; + + err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_COPPER_LENGTH, + &comp_copper_len); + if (err != 0) + goto ERR_I2C; + err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_CABLE_TECHNOLOGY, &cable_tech); if (err != 0) @@ -832,12 +853,7 @@ s32 txgbe_identify_sfp_module(struct txgbe_hw *hw) * 11 SFP_1g_sx_CORE0 - chip-specific * 12 SFP_1g_sx_CORE1 - chip-specific */ - if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE) { - if (hw->bus.lan_id == 0) - hw->phy.sfp_type = txgbe_sfp_type_da_cu_core0; - else - hw->phy.sfp_type = txgbe_sfp_type_da_cu_core1; - } else if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE) { + if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE) { err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_CABLE_SPEC_COMP, &cable_spec); if (err != 0) @@ -849,6 +865,17 @@ s32 txgbe_identify_sfp_module(struct txgbe_hw *hw) } else { hw->phy.sfp_type = txgbe_sfp_type_unknown; } + } else if (comp_codes_25g == TXGBE_SFF_25GBASESR_CAPABLE || + comp_codes_25g == TXGBE_SFF_25GBASEER_CAPABLE) { + if (hw->bus.lan_id == 0) + hw->phy.sfp_type = txgbe_sfp_type_25g_sr_core0; + else + hw->phy.sfp_type = txgbe_sfp_type_25g_sr_core1; + } else if (comp_codes_25g == TXGBE_SFF_25GBASELR_CAPABLE) { + if (hw->bus.lan_id == 0) + hw->phy.sfp_type = txgbe_sfp_type_25g_lr_core0; + else + hw->phy.sfp_type = txgbe_sfp_type_25g_lr_core1; } else if (comp_codes_10g & (TXGBE_SFF_10GBASESR_CAPABLE | TXGBE_SFF_10GBASELR_CAPABLE)) { @@ -876,11 +903,20 @@ s32 txgbe_identify_sfp_module(struct txgbe_hw *hw) /* Determine if the SFP+ PHY is dual speed or not. */ hw->phy.multispeed_fiber = false; - if (((comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) && - (comp_codes_10g & TXGBE_SFF_10GBASESR_CAPABLE)) || - ((comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) && - (comp_codes_10g & TXGBE_SFF_10GBASELR_CAPABLE))) - hw->phy.multispeed_fiber = true; + if (hw->mac.type == txgbe_mac_aml) { + if ((comp_codes_25g == TXGBE_SFF_25GBASESR_CAPABLE || + comp_codes_25g == TXGBE_SFF_25GBASELR_CAPABLE || + comp_codes_25g == TXGBE_SFF_25GBASEER_CAPABLE) && + ((comp_codes_10g & TXGBE_SFF_10GBASESR_CAPABLE) || + (comp_codes_10g & TXGBE_SFF_10GBASELR_CAPABLE))) + hw->phy.multispeed_fiber = true; + } else { + if (((comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) && + (comp_codes_10g & TXGBE_SFF_10GBASESR_CAPABLE)) || + ((comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) && + (comp_codes_10g & TXGBE_SFF_10GBASELR_CAPABLE))) + hw->phy.multispeed_fiber = true; + } /* Determine PHY vendor */ if (hw->phy.type != txgbe_phy_nl) { @@ -938,7 +974,7 @@ s32 txgbe_identify_sfp_module(struct txgbe_hw *hw) } /* Verify supported 1G SFP modules */ - if (comp_codes_10g == 0 && + if (comp_codes_10g == 0 && comp_codes_25g == 0 && !(hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 || hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 || hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 || @@ -986,6 +1022,7 @@ s32 txgbe_identify_qsfp_module(struct txgbe_hw *hw) u8 cable_length = 0; u8 device_tech = 0; bool active_cable = false; + u32 value; if (hw->phy.media_type != txgbe_media_type_fiber_qsfp) { hw->phy.sfp_type = txgbe_sfp_type_not_present; @@ -993,6 +1030,16 @@ s32 txgbe_identify_qsfp_module(struct txgbe_hw *hw) goto out; } + if (hw->mac.type == txgbe_mac_aml40) { + /* config GPIO before read i2c */ + wr32(hw, TXGBE_GPIODATA, TXGBE_GPIOBIT_1); + value = rd32(hw, TXGBE_GPIOEXT); + if (value & TXGBE_SFP1_MOD_PRST_LS) { + hw->phy.sfp_type = txgbe_sfp_type_not_present; + return TXGBE_ERR_SFP_NOT_PRESENT; + } + } + err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_IDENTIFIER, &identifier); ERR_I2C: @@ -1024,10 +1071,27 @@ s32 txgbe_identify_qsfp_module(struct txgbe_hw *hw) if (comp_codes_10g & TXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { hw->phy.type = txgbe_phy_qsfp_unknown_passive; + if (hw->mac.type == txgbe_mac_aml40) { + if (hw->bus.lan_id == 0) + hw->phy.sfp_type = txgbe_qsfp_type_40g_cu_core0; + else + hw->phy.sfp_type = txgbe_qsfp_type_40g_cu_core1; + } else { + if (hw->bus.lan_id == 0) + hw->phy.sfp_type = txgbe_sfp_type_da_cu_core0; + else + hw->phy.sfp_type = txgbe_sfp_type_da_cu_core1; + } + } else if (comp_codes_10g & TXGBE_SFF_40GBASE_SR4) { + if (hw->bus.lan_id == 0) + hw->phy.sfp_type = txgbe_qsfp_type_40g_sr_core0; + else + hw->phy.sfp_type = txgbe_qsfp_type_40g_sr_core1; + } else if (comp_codes_10g & TXGBE_SFF_40GBASE_LR4) { if (hw->bus.lan_id == 0) - hw->phy.sfp_type = txgbe_sfp_type_da_cu_core0; + hw->phy.sfp_type = txgbe_qsfp_type_40g_lr_core0; else - hw->phy.sfp_type = txgbe_sfp_type_da_cu_core1; + hw->phy.sfp_type = txgbe_qsfp_type_40g_lr_core1; } else if (comp_codes_10g & (TXGBE_SFF_10GBASESR_CAPABLE | TXGBE_SFF_10GBASELR_CAPABLE)) { if (hw->bus.lan_id == 0) diff --git a/drivers/net/txgbe/base/txgbe_phy.h b/drivers/net/txgbe/base/txgbe_phy.h index 4dfe18930c..c02be3cc34 100644 --- a/drivers/net/txgbe/base/txgbe_phy.h +++ b/drivers/net/txgbe/base/txgbe_phy.h @@ -249,6 +249,8 @@ #define TXGBE_SFF_VENDOR_OUI_BYTE2 0x27 #define TXGBE_SFF_1GBE_COMP_CODES 0x06 #define TXGBE_SFF_10GBE_COMP_CODES 0x03 +#define TXGBE_SFF_25GBE_COMP_CODES 0x24 +#define TXGBE_SFF_COPPER_LENGTH 0x12 #define TXGBE_SFF_CABLE_TECHNOLOGY 0x08 #define TXGBE_SFF_CABLE_DA_PASSIVE 0x4 #define TXGBE_SFF_CABLE_DA_ACTIVE 0x8 @@ -275,6 +277,23 @@ #define TXGBE_SFF_1GBASET_CAPABLE 0x8 #define TXGBE_SFF_10GBASESR_CAPABLE 0x10 #define TXGBE_SFF_10GBASELR_CAPABLE 0x20 +#define TXGBE_SFF_25GBASESR_CAPABLE 0x2 +#define TXGBE_SFF_25GBASELR_CAPABLE 0x3 +#define TXGBE_SFF_25GBASEER_CAPABLE 0x4 +#define TXGBE_SFF_25GBASECR_91FEC 0xB +#define TXGBE_SFF_25GBASECR_74FEC 0xC +#define TXGBE_SFF_25GBASECR_NOFEC 0xD +#define TXGBE_SFF_40GBASE_SR_CAPABLE 0x10 +#define TXGBE_SFF_4x10GBASESR_CAP 0x11 +#define TXGBE_SFF_40GBASEPSM4_PARALLEL 0x12 +#define TXGBE_SFF_40GBASE_SWMD4_CAP 0x1f + +#define TXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4 +#define TXGBE_SFF_25GAUI_C2M_AOC_BER_5 0x1 +#define TXGBE_SFF_25GAUI_C2M_ACC_BER_5 0x8 +#define TXGBE_SFF_25GAUI_C2M_AOC_BER_12 0x18 +#define TXGBE_SFF_25GAUI_C2M_ACC_BER_12 0x19 + #define TXGBE_SFF_SOFT_RS_SELECT_MASK 0x8 #define TXGBE_SFF_SOFT_RS_SELECT_10G 0x8 #define TXGBE_SFF_SOFT_RS_SELECT_1G 0x0 @@ -290,6 +309,10 @@ #define TXGBE_I2C_EEPROM_STATUS_FAIL 0x2 #define TXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3 +#define TXGBE_SFF_40GBASE_CR4 0x8 +#define TXGBE_SFF_40GBASE_SR4 0x4 +#define TXGBE_SFF_40GBASE_LR4 0x2 + /* EEPROM for SFF-8472 (dev_addr = 0xA2) */ #define TXGBE_I2C_EEPROM_DEV_ADDR2 0xA2 diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h index 3b0bf08ea2..e75597591f 100644 --- a/drivers/net/txgbe/base/txgbe_regs.h +++ b/drivers/net/txgbe/base/txgbe_regs.h @@ -1605,7 +1605,10 @@ enum txgbe_5tuple_protocol { #define TXGBE_GPIOINTSTAT 0x014840 #define TXGBE_GPIORAWINTSTAT 0x014844 #define TXGBE_GPIOEOI 0x01484C - +#define TXGBE_GPIOEXT 0x014850 +#define TXGBE_SFP1_MOD_ABS_LS MS(2, 0x1) /* GPIO_EXT SFP ABSENT*/ +#define TXGBE_SFP1_RX_LOS_LS MS(3, 0x1) /* GPIO_EXT RX LOSS */ +#define TXGBE_SFP1_MOD_PRST_LS MS(4, 0x1) /* GPIO_EXT SFP ABSENT*/ #define TXGBE_ARBPOOLIDX 0x01820C #define TXGBE_ARBTXRATE 0x018404 diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h index a34c782ec8..2d13539f87 100644 --- a/drivers/net/txgbe/base/txgbe_type.h +++ b/drivers/net/txgbe/base/txgbe_type.h @@ -206,6 +206,18 @@ enum txgbe_sfp_type { txgbe_sfp_type_1g_sx_core1, txgbe_sfp_type_1g_lx_core0, txgbe_sfp_type_1g_lx_core1, + txgbe_sfp_type_25g_sr_core0, + txgbe_sfp_type_25g_sr_core1, + txgbe_sfp_type_25g_lr_core0, + txgbe_sfp_type_25g_lr_core1, + txgbe_sfp_type_25g_aoc_core0, + txgbe_sfp_type_25g_aoc_core1, + txgbe_qsfp_type_40g_cu_core0, + txgbe_qsfp_type_40g_cu_core1, + txgbe_qsfp_type_40g_sr_core0, + txgbe_qsfp_type_40g_sr_core1, + txgbe_qsfp_type_40g_lr_core0, + txgbe_qsfp_type_40g_lr_core1, txgbe_sfp_type_not_present = 0xFFFE, txgbe_sfp_type_not_known = 0xFFFF }; From patchwork Tue Sep 30 09:59:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zaiyu Wang X-Patchwork-Id: 157117 X-Patchwork-Delegate: stephen@networkplumber.org Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6CBAF4886F; Tue, 30 Sep 2025 12:00:44 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8896740B9C; Tue, 30 Sep 2025 12:00:32 +0200 (CEST) Received: from smtpbgau2.qq.com (smtpbgau2.qq.com [54.206.34.216]) by mails.dpdk.org (Postfix) with ESMTP id EC24F40A6D for ; Tue, 30 Sep 2025 12:00:29 +0200 (CEST) X-QQ-mid: esmtpgz13t1759226424t7f5f3652 X-QQ-Originating-IP: pjGDPNKURuUdTIDf0BQPXZUA/LmsfVddIaZlH4P4H6I= Received: from DSK-zaiyuwang.trustnetic.com ( [115.220.225.164]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 30 Sep 2025 18:00:23 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 1178880294213098784 EX-QQ-RecipientCnt: 4 From: Zaiyu Wang To: dev@dpdk.org Cc: Zaiyu Wang , Jiawen Wu , Jian Wang Subject: [PATCH v4 04/20] net/txgbe: rename raptor to sp for Sapphire-specific code Date: Tue, 30 Sep 2025 17:59:36 +0800 Message-Id: <20250930095953.18508-5-zaiyuwang@trustnetic.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20250930095953.18508-1-zaiyuwang@trustnetic.com> References: <20250418094131.24136-1-zaiyuwang@trustnetic.com> <20250930095953.18508-1-zaiyuwang@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:trustnetic.com:qybglogicsvrgz:qybglogicsvrgz5a-1 X-QQ-XMAILINFO: OQEfmBmUqqJ6triph1LVPyLavF6y9qHnU2LuGJfXTW9HKKrhmQyevr2T NuPN4//ypSrO+FDjz7O0ZaHb/j8Fp0Zzpcq/SY4yECSJQt07Y+qvHi/+S2VhewJTYmL0ZDZ j5IaFu0BqFGs8dm2EKZau5bVPHIKYJG/oE8rfbkQyTnLhzfWPrnCZzSoYfsHsWoHhSqt9KV 6wkJzOSqI5D3gIm6wMF4DoHc8XuBcsvuQWwKKzj7g0v8mYWtcE9diAJVAxO5PcHM15B556M SsAsJQ6n7bJycgFhws/mdPKLm7qusl+fKXiIARXwteRbecPYZ2G2cTEjPaKoJVzb+m4Ei3i oe4l3BJoOKB7xj/Vf5Bge9Q/rco0RM88yQ+dwh/6Hm+RKbhP00IwUnUNvPsptC4J6KHCZWM nWu/cOys54Tp4akV2h4ITx4HJ201XzfwPiyJzoMKcTeIbOzdayWjjgKRYVLkjDjYRuNZMhM zgqdhvXuOG7bgeqEmILOsOcTvyn2ilMJJVxJ8OdtUhZGM7yySi3Xy0uaAnmZpA2Vgq9EXv9 xmfOARCxS87Nfn+pYhSblXu7RbyLgl1QO9oxne64Z7v7ZLypKUVrcTU1ba9Z2KFNZmWyh6i TfZt74gnlbZ601QrU2DEVwcMz4DKuPcY0LwsVGwcxbzWofGwveYl0NkoEs7urDdFzHo3Wdu sPxusMdHB57APiyasM+7ZcIfzlkglLySYP2c/Z4zxqN6I3Xjjba4jTPmWNGfgoIYzTdBZpt mXujUVryyrR2Bogz3ASByR8r9yrwGbG2uu7+iq1vv76i+hs4EaRT49CPjNV59PCjBCrCq9E Wex9I494joWMTTOx0omHkgomwtQdWBAaP4JvGQ5l9Iu6cjDUTHcLWPT/GsrpUdcuVEFGxUV McGGmV/26Wfq82zWHSz7KjkXfMdquBekzo1OTfCM3LA8eDsu0UpBkCp1GVq5yg3Vze3MROk rawIEF+ekzXqULrvNbIk1QScb7HiSEWG4Z8GUh3U/u6UcbHazzOdMzohZmU76BIicaiYc8O y18pP+d9PrJ/4iIw+49FydlvdwO0HH8ROuSefHKACj087K9/0P X-QQ-XMRINFO: Mp0Kj//9VHAxr69bL5MkOOs= X-QQ-RECHKSPAM: 0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The term "raptor" was originally used as a general designation for NICs when only Sapphire series existed. With the addition of Amber-Lite series NICs, we now use "sp" to replace "raptor" for driver components that are specific to Sapphire NICs, while retaining the "raptor" name for common flows applicable to all NICs. Signed-off-by: Zaiyu Wang --- drivers/net/txgbe/base/txgbe_hw.c | 62 +++++++++++++++++++---------- drivers/net/txgbe/base/txgbe_hw.h | 11 ++--- drivers/net/txgbe/base/txgbe_regs.h | 8 ++-- drivers/net/txgbe/base/txgbe_type.h | 5 ++- drivers/net/txgbe/base/txgbe_vf.c | 2 +- drivers/net/txgbe/txgbe_ethdev.c | 14 +++---- drivers/net/txgbe/txgbe_ethdev_vf.c | 2 +- drivers/net/txgbe/txgbe_flow.c | 2 +- drivers/net/txgbe/txgbe_rxtx.c | 24 +++++------ 9 files changed, 76 insertions(+), 54 deletions(-) diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c index 76f8ecf62e..81e686fdf1 100644 --- a/drivers/net/txgbe/base/txgbe_hw.c +++ b/drivers/net/txgbe/base/txgbe_hw.c @@ -272,7 +272,7 @@ s32 txgbe_start_hw(struct txgbe_hw *hw) /* Cache bit indicating need for crosstalk fix */ switch (hw->mac.type) { - case txgbe_mac_raptor: + case txgbe_mac_sp: hw->mac.get_device_caps(hw, &device_caps); if (device_caps & TXGBE_DEVICE_CAPS_NO_CROSSTALK_WR) hw->need_crosstalk_fix = false; @@ -1915,7 +1915,7 @@ static bool txgbe_need_crosstalk_fix(struct txgbe_hw *hw) * * Reads the links register to determine if link is up and the current speed **/ -s32 txgbe_check_mac_link(struct txgbe_hw *hw, u32 *speed, +s32 txgbe_check_mac_link_sp(struct txgbe_hw *hw, u32 *speed, bool *link_up, bool link_up_wait_to_complete) { u32 links_reg, links_orig; @@ -1928,7 +1928,7 @@ s32 txgbe_check_mac_link(struct txgbe_hw *hw, u32 *speed, u32 sfp_cage_full; switch (hw->mac.type) { - case txgbe_mac_raptor: + case txgbe_mac_sp: sfp_cage_full = !rd32m(hw, TXGBE_GPIODATA, TXGBE_GPIOBIT_2); break; @@ -2475,12 +2475,13 @@ s32 txgbe_init_shared_code(struct txgbe_hw *hw) txgbe_init_ops_dummy(hw); switch (hw->mac.type) { - case txgbe_mac_raptor: + case txgbe_mac_sp: + txgbe_init_ops_sp(hw); + break; case txgbe_mac_aml: case txgbe_mac_aml40: - status = txgbe_init_ops_pf(hw); break; - case txgbe_mac_raptor_vf: + case txgbe_mac_sp_vf: status = txgbe_init_ops_vf(hw); break; default: @@ -2497,7 +2498,7 @@ s32 txgbe_init_shared_code(struct txgbe_hw *hw) bool txgbe_is_pf(struct txgbe_hw *hw) { switch (hw->mac.type) { - case txgbe_mac_raptor: + case txgbe_mac_sp: return true; default: return false; @@ -2523,7 +2524,7 @@ s32 txgbe_set_mac_type(struct txgbe_hw *hw) switch (hw->device_id) { case TXGBE_DEV_ID_SP1000: case TXGBE_DEV_ID_WX1820: - hw->mac.type = txgbe_mac_raptor; + hw->mac.type = txgbe_mac_sp; break; case TXGBE_DEV_ID_AML: case TXGBE_DEV_ID_AML5025: @@ -2537,7 +2538,7 @@ s32 txgbe_set_mac_type(struct txgbe_hw *hw) case TXGBE_DEV_ID_SP1000_VF: case TXGBE_DEV_ID_WX1820_VF: hw->phy.media_type = txgbe_media_type_virtual; - hw->mac.type = txgbe_mac_raptor_vf; + hw->mac.type = txgbe_mac_sp_vf; break; case TXGBE_DEV_ID_AML_VF: case TXGBE_DEV_ID_AML5024_VF: @@ -2556,7 +2557,7 @@ s32 txgbe_set_mac_type(struct txgbe_hw *hw) return err; } -void txgbe_init_mac_link_ops(struct txgbe_hw *hw) +void txgbe_init_mac_link_ops_sp(struct txgbe_hw *hw) { struct txgbe_mac_info *mac = &hw->mac; @@ -2616,7 +2617,7 @@ s32 txgbe_init_phy_raptor(struct txgbe_hw *hw) goto init_phy_ops_out; /* Setup function pointers based on detected SFP module and speeds */ - txgbe_init_mac_link_ops(hw); + txgbe_init_mac_link_ops_sp(hw); /* If copper media, overwrite with copper function pointers */ if (phy->media_type == txgbe_media_type_copper) { @@ -2651,7 +2652,7 @@ s32 txgbe_setup_sfp_modules(struct txgbe_hw *hw) if (hw->phy.sfp_type == txgbe_sfp_type_unknown) return 0; - txgbe_init_mac_link_ops(hw); + txgbe_init_mac_link_ops_sp(hw); /* PHY config will finish before releasing the semaphore */ err = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY); @@ -2792,13 +2793,13 @@ s32 txgbe_flash_read_dword(struct txgbe_hw *hw, u32 addr, u32 *data) } /** - * txgbe_init_ops_pf - Inits func ptrs and MAC type + * txgbe_init_ops_generic - Inits func ptrs and MAC type * @hw: pointer to hardware structure * * Initialize the function pointers and assign the MAC type. * Does not touch the hardware. **/ -s32 txgbe_init_ops_pf(struct txgbe_hw *hw) +s32 txgbe_init_ops_generic(struct txgbe_hw *hw) { struct txgbe_bus_info *bus = &hw->bus; struct txgbe_mac_info *mac = &hw->mac; @@ -2918,15 +2919,31 @@ s32 txgbe_init_ops_pf(struct txgbe_hw *hw) return 0; } +void txgbe_init_ops_sp(struct txgbe_hw *hw) +{ + struct txgbe_mac_info *mac = &hw->mac; + struct txgbe_phy_info *phy = &hw->phy; + + txgbe_init_ops_generic(hw); + + /* PHY */ + phy->get_media_type = txgbe_get_media_type_sp; + + /* LINK */ + mac->init_mac_link_ops = txgbe_init_mac_link_ops_sp; + mac->get_link_capabilities = txgbe_get_link_capabilities_sp; + mac->check_link = txgbe_check_mac_link_sp; +} + /** - * txgbe_get_link_capabilities_raptor - Determines link capabilities + * txgbe_get_link_capabilities_sp - Determines link capabilities * @hw: pointer to hardware structure * @speed: pointer to link speed * @autoneg: true when autoneg or autotry is enabled * * Determines the link capabilities by reading the AUTOC register. **/ -s32 txgbe_get_link_capabilities_raptor(struct txgbe_hw *hw, +s32 txgbe_get_link_capabilities_sp(struct txgbe_hw *hw, u32 *speed, bool *autoneg) { @@ -3027,12 +3044,12 @@ s32 txgbe_get_link_capabilities_raptor(struct txgbe_hw *hw, } /** - * txgbe_get_media_type_raptor - Get media type + * txgbe_get_media_type_sp - Get media type * @hw: pointer to hardware structure * * Returns the media type (fiber, copper, backplane) **/ -u32 txgbe_get_media_type_raptor(struct txgbe_hw *hw) +u32 txgbe_get_media_type_sp(struct txgbe_hw *hw) { u32 media_type; @@ -3565,8 +3582,10 @@ s32 txgbe_reset_hw(struct txgbe_hw *hw) if (!hw->phy.reset_disable) hw->phy.reset(hw); - /* remember AUTOC from before we reset */ - autoc = hw->mac.autoc_read(hw); + if (hw->mac.type == txgbe_mac_sp) { + /* remember AUTOC from before we reset */ + autoc = hw->mac.autoc_read(hw); + } mac_reset_top: /* Do LAN reset, the MNG domain will not be reset. */ @@ -3615,7 +3634,8 @@ s32 txgbe_reset_hw(struct txgbe_hw *hw) msec_delay(50); /* A temporary solution to set phy */ - txgbe_set_phy_temp(hw); + if (hw->mac.type == txgbe_mac_sp) + txgbe_set_phy_temp(hw); } /* Store the permanent mac address */ diff --git a/drivers/net/txgbe/base/txgbe_hw.h b/drivers/net/txgbe/base/txgbe_hw.h index 7a45020824..62c027c850 100644 --- a/drivers/net/txgbe/base/txgbe_hw.h +++ b/drivers/net/txgbe/base/txgbe_hw.h @@ -56,7 +56,7 @@ s32 txgbe_set_vlvf(struct txgbe_hw *hw, u32 vlan, u32 vind, s32 txgbe_clear_vfta(struct txgbe_hw *hw); s32 txgbe_find_vlvf_slot(struct txgbe_hw *hw, u32 vlan, bool vlvf_bypass); -s32 txgbe_check_mac_link(struct txgbe_hw *hw, +s32 txgbe_check_mac_link_sp(struct txgbe_hw *hw, u32 *speed, bool *link_up, bool link_up_wait_to_complete); @@ -87,10 +87,11 @@ s32 txgbe_negotiate_fc(struct txgbe_hw *hw, u32 adv_reg, u32 lp_reg, s32 txgbe_init_shared_code(struct txgbe_hw *hw); bool txgbe_is_pf(struct txgbe_hw *hw); s32 txgbe_set_mac_type(struct txgbe_hw *hw); -s32 txgbe_init_ops_pf(struct txgbe_hw *hw); -s32 txgbe_get_link_capabilities_raptor(struct txgbe_hw *hw, +s32 txgbe_init_ops_generic(struct txgbe_hw *hw); +void txgbe_init_ops_sp(struct txgbe_hw *hw); +s32 txgbe_get_link_capabilities_sp(struct txgbe_hw *hw, u32 *speed, bool *autoneg); -u32 txgbe_get_media_type_raptor(struct txgbe_hw *hw); +u32 txgbe_get_media_type_sp(struct txgbe_hw *hw); void txgbe_disable_tx_laser_multispeed_fiber(struct txgbe_hw *hw); void txgbe_enable_tx_laser_multispeed_fiber(struct txgbe_hw *hw); void txgbe_flap_tx_laser_multispeed_fiber(struct txgbe_hw *hw); @@ -104,7 +105,7 @@ s32 txgbe_start_mac_link_raptor(struct txgbe_hw *hw, s32 txgbe_setup_mac_link(struct txgbe_hw *hw, u32 speed, bool autoneg_wait_to_complete); s32 txgbe_setup_sfp_modules(struct txgbe_hw *hw); -void txgbe_init_mac_link_ops(struct txgbe_hw *hw); +void txgbe_init_mac_link_ops_sp(struct txgbe_hw *hw); s32 txgbe_reset_hw(struct txgbe_hw *hw); s32 txgbe_start_hw_raptor(struct txgbe_hw *hw); s32 txgbe_init_phy_raptor(struct txgbe_hw *hw); diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h index e75597591f..ab1a11230c 100644 --- a/drivers/net/txgbe/base/txgbe_regs.h +++ b/drivers/net/txgbe/base/txgbe_regs.h @@ -1737,11 +1737,11 @@ txgbe_map_reg(struct txgbe_hw *hw, u32 reg) { switch (reg) { case TXGBE_REG_RSSTBL: - if (hw->mac.type == txgbe_mac_raptor_vf) + if (hw->mac.type == txgbe_mac_sp_vf) reg = TXGBE_VFRSSTBL(0); break; case TXGBE_REG_RSSKEY: - if (hw->mac.type == txgbe_mac_raptor_vf) + if (hw->mac.type == txgbe_mac_sp_vf) reg = TXGBE_VFRSSKEY(0); break; default: @@ -1917,10 +1917,10 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual, static inline void txgbe_flush(struct txgbe_hw *hw) { switch (hw->mac.type) { - case txgbe_mac_raptor: + case txgbe_mac_sp: rd32(hw, TXGBE_PWR); break; - case txgbe_mac_raptor_vf: + case txgbe_mac_sp_vf: rd32(hw, TXGBE_VFSTATUS); break; default: diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h index 2d13539f87..4d825bec44 100644 --- a/drivers/net/txgbe/base/txgbe_type.h +++ b/drivers/net/txgbe/base/txgbe_type.h @@ -139,10 +139,10 @@ enum txgbe_eeprom_type { enum txgbe_mac_type { txgbe_mac_unknown = 0, - txgbe_mac_raptor, + txgbe_mac_sp, txgbe_mac_aml, txgbe_mac_aml40, - txgbe_mac_raptor_vf, + txgbe_mac_sp_vf, txgbe_mac_aml_vf, txgbe_num_macs }; @@ -544,6 +544,7 @@ struct txgbe_mac_info { s32 (*prot_autoc_read)(struct txgbe_hw *hw, bool *locked, u64 *value); s32 (*prot_autoc_write)(struct txgbe_hw *hw, bool locked, u64 value); s32 (*negotiate_api_version)(struct txgbe_hw *hw, int api); + void (*init_mac_link_ops)(struct txgbe_hw *hw); /* Link */ void (*disable_tx_laser)(struct txgbe_hw *hw); diff --git a/drivers/net/txgbe/base/txgbe_vf.c b/drivers/net/txgbe/base/txgbe_vf.c index 8c731b4776..5e41ba1a3e 100644 --- a/drivers/net/txgbe/base/txgbe_vf.c +++ b/drivers/net/txgbe/base/txgbe_vf.c @@ -488,7 +488,7 @@ s32 txgbe_check_mac_link_vf(struct txgbe_hw *hw, u32 *speed, /* for SFP+ modules and DA cables it can take up to 500usecs * before the link status is correct */ - if (mac->type == txgbe_mac_raptor_vf && wait_to_complete) { + if (mac->type == txgbe_mac_sp_vf && wait_to_complete) { if (po32m(hw, TXGBE_VFSTATUS, TXGBE_VFSTATUS_UP, 0, NULL, 5, 100)) goto out; diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c index d49030357d..82cec488f4 100644 --- a/drivers/net/txgbe/txgbe_ethdev.c +++ b/drivers/net/txgbe/txgbe_ethdev.c @@ -385,7 +385,7 @@ txgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, uint32_t q_map; uint8_t n, offset; - if (hw->mac.type != txgbe_mac_raptor) + if (hw->mac.type != txgbe_mac_sp) return -ENOSYS; if (stat_idx & ~QMAP_FIELD_RESERVED_BITS_MASK) @@ -1806,7 +1806,7 @@ txgbe_dev_start(struct rte_eth_dev *dev) } /* Skip link setup if loopback mode is enabled. */ - if (hw->mac.type == txgbe_mac_raptor && + if (hw->mac.type == txgbe_mac_sp && dev->data->dev_conf.lpbk_mode) goto skip_link_setup; @@ -3072,7 +3072,7 @@ txgbe_dev_link_update_share(struct rte_eth_dev *dev, } /* Re configure MAC RX */ - if (hw->mac.type == txgbe_mac_raptor) { + if (hw->mac.type == txgbe_mac_sp) { reg = rd32(hw, TXGBE_MACRXCFG); wr32(hw, TXGBE_MACRXCFG, reg); wr32m(hw, TXGBE_MACRXFLT, TXGBE_MACRXFLT_PROMISC, @@ -3858,7 +3858,7 @@ txgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev); /* The UTA table only exists on pf hardware */ - if (hw->mac.type < txgbe_mac_raptor) + if (hw->mac.type < txgbe_mac_sp) return -ENOTSUP; vector = txgbe_uta_vector(hw, mac_addr); @@ -3903,7 +3903,7 @@ txgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on) int i; /* The UTA table only exists on pf hardware */ - if (hw->mac.type < txgbe_mac_raptor) + if (hw->mac.type < txgbe_mac_sp) return -ENOTSUP; if (on) { @@ -4969,8 +4969,8 @@ bool txgbe_rss_update_sp(enum txgbe_mac_type mac_type) { switch (mac_type) { - case txgbe_mac_raptor: - case txgbe_mac_raptor_vf: + case txgbe_mac_sp: + case txgbe_mac_sp_vf: return 1; default: return 0; diff --git a/drivers/net/txgbe/txgbe_ethdev_vf.c b/drivers/net/txgbe/txgbe_ethdev_vf.c index 847febf8c3..6505c5848c 100644 --- a/drivers/net/txgbe/txgbe_ethdev_vf.c +++ b/drivers/net/txgbe/txgbe_ethdev_vf.c @@ -375,7 +375,7 @@ eth_txgbevf_dev_init(struct rte_eth_dev *eth_dev) PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s", eth_dev->data->port_id, pci_dev->id.vendor_id, - pci_dev->id.device_id, "txgbe_mac_raptor_vf"); + pci_dev->id.device_id, "txgbe_mac_sp_vf"); return 0; } diff --git a/drivers/net/txgbe/txgbe_flow.c b/drivers/net/txgbe/txgbe_flow.c index 99a76daca0..31af3593ed 100644 --- a/drivers/net/txgbe/txgbe_flow.c +++ b/drivers/net/txgbe/txgbe_flow.c @@ -2854,7 +2854,7 @@ txgbe_parse_fdir_filter(struct rte_eth_dev *dev, step_next: - if (hw->mac.type == txgbe_mac_raptor && + if (hw->mac.type == txgbe_mac_sp && rule->fdirflags == TXGBE_FDIRPICMD_DROP && (rule->input.src_port != 0 || rule->input.dst_port != 0)) return -ENOTSUP; diff --git a/drivers/net/txgbe/txgbe_rxtx.c b/drivers/net/txgbe/txgbe_rxtx.c index e6f33739c4..5c05dfd90a 100644 --- a/drivers/net/txgbe/txgbe_rxtx.c +++ b/drivers/net/txgbe/txgbe_rxtx.c @@ -80,7 +80,7 @@ txgbe_is_vf(struct rte_eth_dev *dev) struct txgbe_hw *hw = TXGBE_DEV_HW(dev); switch (hw->mac.type) { - case txgbe_mac_raptor_vf: + case txgbe_mac_sp_vf: return 1; default: return 0; @@ -2121,10 +2121,10 @@ txgbe_get_rx_port_offloads(struct rte_eth_dev *dev) * RSC is only supported by PF devices in a non-SR-IOV * mode. */ - if (hw->mac.type == txgbe_mac_raptor && !sriov->active) + if (hw->mac.type == txgbe_mac_sp && !sriov->active) offloads |= RTE_ETH_RX_OFFLOAD_TCP_LRO; - if (hw->mac.type == txgbe_mac_raptor) + if (hw->mac.type == txgbe_mac_sp) offloads |= RTE_ETH_RX_OFFLOAD_MACSEC_STRIP; offloads |= RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM; @@ -2498,7 +2498,7 @@ txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, /* Modification to set tail pointer for virtual function * if vf is detected. */ - if (hw->mac.type == txgbe_mac_raptor_vf) { + if (hw->mac.type == txgbe_mac_sp_vf) { txq->tdt_reg_addr = TXGBE_REG_ADDR(hw, TXGBE_TXWP(queue_idx)); txq->tdc_reg_addr = TXGBE_REG_ADDR(hw, TXGBE_TXCFG(queue_idx)); } else { @@ -2791,7 +2791,7 @@ txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, /* * Modified to setup VFRDT for Virtual Function */ - if (hw->mac.type == txgbe_mac_raptor_vf) { + if (hw->mac.type == txgbe_mac_sp_vf) { rxq->rdt_reg_addr = TXGBE_REG_ADDR(hw, TXGBE_RXWP(queue_idx)); rxq->rdh_reg_addr = @@ -3037,7 +3037,7 @@ txgbe_rss_disable(struct rte_eth_dev *dev) struct txgbe_hw *hw; hw = TXGBE_DEV_HW(dev); - if (hw->mac.type == txgbe_mac_raptor_vf) + if (hw->mac.type == txgbe_mac_sp_vf) wr32m(hw, TXGBE_VFPLCFG, TXGBE_VFPLCFG_RSSENA, 0); else wr32m(hw, TXGBE_RACTL, TXGBE_RACTL_RSSENA, 0); @@ -3074,7 +3074,7 @@ txgbe_dev_rss_hash_update(struct rte_eth_dev *dev, /* Set configured hashing protocols */ rss_hf = rss_conf->rss_hf & TXGBE_RSS_OFFLOAD_ALL; - if (hw->mac.type == txgbe_mac_raptor_vf) { + if (hw->mac.type == txgbe_mac_sp_vf) { mrqc = rd32(hw, TXGBE_VFPLCFG); mrqc &= ~TXGBE_VFPLCFG_RSSMASK; if (rss_hf & RTE_ETH_RSS_IPV4) @@ -3166,7 +3166,7 @@ txgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, } rss_hf = 0; - if (hw->mac.type == txgbe_mac_raptor_vf) { + if (hw->mac.type == txgbe_mac_sp_vf) { mrqc = rd32(hw, TXGBE_VFPLCFG); if (mrqc & TXGBE_VFPLCFG_RSSIPV4) rss_hf |= RTE_ETH_RSS_IPV4; @@ -3627,7 +3627,7 @@ txgbe_dcb_hw_arbite_tx_config(struct txgbe_hw *hw, uint16_t *refill, uint16_t *max, uint8_t *bwg_id, uint8_t *tsa, uint8_t *map) { switch (hw->mac.type) { - case txgbe_mac_raptor: + case txgbe_mac_sp: txgbe_dcb_config_tx_desc_arbiter_raptor(hw, refill, max, bwg_id, tsa); txgbe_dcb_config_tx_data_arbiter_raptor(hw, refill, @@ -4555,7 +4555,7 @@ txgbe_dev_rx_init(struct rte_eth_dev *dev) * If loopback mode is configured, set LPBK bit. */ hlreg0 = rd32(hw, TXGBE_PSRCTL); - if (hw->mac.type == txgbe_mac_raptor && + if (hw->mac.type == txgbe_mac_sp && dev->data->dev_conf.lpbk_mode) hlreg0 |= TXGBE_PSRCTL_LBENA; else @@ -4640,7 +4640,7 @@ txgbe_dev_rx_init(struct rte_eth_dev *dev) wr32(hw, TXGBE_PSRCTL, rxcsum); - if (hw->mac.type == txgbe_mac_raptor) { + if (hw->mac.type == txgbe_mac_sp) { rdrxctl = rd32(hw, TXGBE_SECRXCTL); if (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC) rdrxctl &= ~TXGBE_SECRXCTL_CRCSTRIP; @@ -4765,7 +4765,7 @@ txgbe_dev_rxtx_start(struct rte_eth_dev *dev) hw->mac.enable_rx_dma(hw, rxctrl); /* If loopback mode is enabled, set up the link accordingly */ - if (hw->mac.type == txgbe_mac_raptor && + if (hw->mac.type == txgbe_mac_sp && dev->data->dev_conf.lpbk_mode) txgbe_setup_loopback_link_raptor(hw); From patchwork Tue Sep 30 09:59:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zaiyu Wang X-Patchwork-Id: 157118 X-Patchwork-Delegate: stephen@networkplumber.org Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 19ECE4886F; Tue, 30 Sep 2025 12:00:52 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8F7D340BA6; Tue, 30 Sep 2025 12:00:33 +0200 (CEST) Received: from smtpbg151.qq.com (smtpbg151.qq.com [18.169.211.239]) by mails.dpdk.org (Postfix) with ESMTP id E6DF8406B8 for ; Tue, 30 Sep 2025 12:00:31 +0200 (CEST) X-QQ-mid: esmtpgz13t1759226428t40bf64e2 X-QQ-Originating-IP: q4OxtwBWU+amVE8QMRZ1oiyFhCmV6Kf962UeYM4B7+U= Received: from DSK-zaiyuwang.trustnetic.com ( [115.220.225.164]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 30 Sep 2025 18:00:26 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 3895156737126014456 EX-QQ-RecipientCnt: 4 From: Zaiyu Wang To: dev@dpdk.org Cc: Zaiyu Wang , Jiawen Wu , Jian Wang Subject: [PATCH v4 05/20] net/txgbe: add basic link configuration for Amber-Lite NICs Date: Tue, 30 Sep 2025 17:59:37 +0800 Message-Id: <20250930095953.18508-6-zaiyuwang@trustnetic.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20250930095953.18508-1-zaiyuwang@trustnetic.com> References: <20250418094131.24136-1-zaiyuwang@trustnetic.com> <20250930095953.18508-1-zaiyuwang@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:trustnetic.com:qybglogicsvrgz:qybglogicsvrgz5a-1 X-QQ-XMAILINFO: NGHdgOcrWZQ9LlMyySY/GRzIIIEKkD7jDV3TPnt6B0rYCmDZQ8Rd6Dkn tU6WJHRKR/jmMd0jTxDXKHTk7cvdVs5/l4MiuMgOjaUnSBrjyWEvryFmSF0GFYXRXBDdl9L 4zK0H9+Dhe3BocypGA35AvR8hzqwUXZUfV/PH76sI62dl4Vw60Qp2w2QEZzTai+TEt6g4yO RLCK/9tsUjS+MuUIr9XQaeK3MP46rO5Z/y62A/C5FeTcDpU8DYBYj5Ij6gB1OQk8G0+SRUs +NV45ImHO33zwNIVBAo8/R2I3MeJGO3kOe2UXhM2AmkiLLC3ThmDwOg5gTPKfR7yf/h1bNj KaigO95sXP0EmUM7KDlKTiMQrs8I/qQE4k5X14cdbYRLgZG60gASOoyZDHQE0Jw+5M07Zeu mfzED6c+iRQ3Bcrf9DkEibZcNanv2jQDhb9xBESp4ykgH7ZNHLIIllaXYGPiNUpivU0XZFT UMn9y0lmdS5lkoJvvuvBpzdzEJka1jf4xCAiOUpmcbtBJzp955EOk1b/PXfDc7kX/gZkIHR CB+yQXEQ4XHW0G+8xGISnUAGlbU6lyCVYklWzjw05GGyq8b6H52N/nZM0MtPs7Tmdzoa2Rt myc+IPSIj/IGykrkajhf2GnE4C0cBiW/e2p/LG5MKZ6Z6tkfbNXrOH4NFUmGtkmFrt4WPU9 6e75HI/OGcmgH0Mdn4pN/k0adNTp79l5DgGvxZuAniXTzwipdJmM5IUVHayTUbWcYKLygRL ERdiO8g/T651RHFszUO89UZ3ofviGlhGWgfLdf0tE1EYt8p36VPOXMncWqJB9N5OpnSHEZI aF0yV5G29JemD9UCN7h9fGUVL4swzqxAAjUlQyE87Wg4WD130DycnuGyQYGviwitScSYwEG vQeg3t2KF3kI+wqpdvqq//ITgggTpv5KbtuQR8NX6ocskthZ/c/sEWFajVpDd+43YEWG7ra zhiiVeVq0YCaB2nZZnMjHrVAwpYNIuwE3uYtUmP8hOTZAaCMqf8Alo+cl87NLvIIOmmxSQt w+MrOdL8hSQisMmG4AGdnDNDkt6yDPpG1SAtRnUvJ7UDVlVB3ZwPhcr+unPWgKB442Ysl5+ i25Mpqk2YXBv53ZmN+ak8w= X-QQ-XMRINFO: NI4Ajvh11aEj8Xl/2s1/T8w= X-QQ-RECHKSPAM: 0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Due to Amber-Lite's significant differences from our 10G NICs, we split link configuration components (setup_link, check_link, etc.) into new files. Signed-off-by: Zaiyu Wang --- drivers/net/txgbe/base/meson.build | 2 + drivers/net/txgbe/base/txgbe_aml.c | 296 +++++++++++++++++++++++++++ drivers/net/txgbe/base/txgbe_aml.h | 21 ++ drivers/net/txgbe/base/txgbe_aml40.c | 126 ++++++++++++ drivers/net/txgbe/base/txgbe_aml40.h | 20 ++ drivers/net/txgbe/base/txgbe_hw.c | 49 ++++- drivers/net/txgbe/base/txgbe_hw.h | 2 + drivers/net/txgbe/base/txgbe_regs.h | 9 + drivers/net/txgbe/base/txgbe_type.h | 1 + drivers/net/txgbe/txgbe_ethdev.c | 8 + 10 files changed, 528 insertions(+), 6 deletions(-) create mode 100644 drivers/net/txgbe/base/txgbe_aml.c create mode 100644 drivers/net/txgbe/base/txgbe_aml.h create mode 100644 drivers/net/txgbe/base/txgbe_aml40.c create mode 100644 drivers/net/txgbe/base/txgbe_aml40.h diff --git a/drivers/net/txgbe/base/meson.build b/drivers/net/txgbe/base/meson.build index 0bb0782c92..ac4a05005e 100644 --- a/drivers/net/txgbe/base/meson.build +++ b/drivers/net/txgbe/base/meson.build @@ -6,6 +6,8 @@ base_sources = files( 'txgbe_dcb.c', 'txgbe_eeprom.c', 'txgbe_hw.c', + 'txgbe_aml.c', + 'txgbe_aml40.c', 'txgbe_mbx.c', 'txgbe_mng.c', 'txgbe_phy.c', diff --git a/drivers/net/txgbe/base/txgbe_aml.c b/drivers/net/txgbe/base/txgbe_aml.c new file mode 100644 index 0000000000..b172622ac7 --- /dev/null +++ b/drivers/net/txgbe/base/txgbe_aml.c @@ -0,0 +1,296 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2015-2025 Beijing WangXun Technology Co., Ltd. + * Copyright(c) 2010-2017 Intel Corporation + */ + +#include "txgbe_type.h" +#include "txgbe_mbx.h" +#include "txgbe_phy.h" +#include "txgbe_dcb.h" +#include "txgbe_vf.h" +#include "txgbe_eeprom.h" +#include "txgbe_mng.h" +#include "txgbe_hw.h" +#include "txgbe_aml.h" + +void txgbe_init_ops_aml(struct txgbe_hw *hw) +{ + struct txgbe_mac_info *mac = &hw->mac; + struct txgbe_phy_info *phy = &hw->phy; + + txgbe_init_ops_generic(hw); + + /* PHY */ + phy->get_media_type = txgbe_get_media_type_aml; + + /* LINK */ + mac->init_mac_link_ops = txgbe_init_mac_link_ops_aml; + mac->get_link_capabilities = txgbe_get_link_capabilities_aml; + mac->check_link = txgbe_check_mac_link_aml; +} + +s32 txgbe_check_mac_link_aml(struct txgbe_hw *hw, u32 *speed, + bool *link_up, bool link_up_wait_to_complete) +{ + u32 links_reg, links_orig; + u32 i; + + /* clear the old state */ + links_orig = rd32(hw, TXGBE_PORTSTAT); + + links_reg = rd32(hw, TXGBE_PORTSTAT); + + if (links_orig != links_reg) { + DEBUGOUT("LINKS changed from %08X to %08X", + links_orig, links_reg); + } + + if (link_up_wait_to_complete) { + for (i = 0; i < hw->mac.max_link_up_time; i++) { + if (!(links_reg & TXGBE_PORTSTAT_UP)) { + *link_up = false; + } else { + *link_up = true; + break; + } + msec_delay(100); + links_reg = rd32(hw, TXGBE_PORTSTAT); + } + } else { + if (links_reg & TXGBE_PORTSTAT_UP) + *link_up = true; + else + *link_up = false; + } + + if (link_up) { + switch (links_reg & TXGBE_CFG_PORT_ST_AML_LINK_MASK) { + case TXGBE_CFG_PORT_ST_AML_LINK_25G: + *speed = TXGBE_LINK_SPEED_25GB_FULL; + break; + case TXGBE_CFG_PORT_ST_AML_LINK_10G: + *speed = TXGBE_LINK_SPEED_10GB_FULL; + break; + default: + *speed = TXGBE_LINK_SPEED_UNKNOWN; + } + } else { + *speed = TXGBE_LINK_SPEED_UNKNOWN; + } + + return 0; +} + +s32 txgbe_get_link_capabilities_aml(struct txgbe_hw *hw, + u32 *speed, + bool *autoneg) +{ + if (hw->phy.multispeed_fiber) { + *speed = TXGBE_LINK_SPEED_10GB_FULL | + TXGBE_LINK_SPEED_25GB_FULL; + *autoneg = true; + } else if (hw->phy.sfp_type == txgbe_sfp_type_25g_sr_core0 || + hw->phy.sfp_type == txgbe_sfp_type_25g_sr_core1 || + hw->phy.sfp_type == txgbe_sfp_type_25g_lr_core0 || + hw->phy.sfp_type == txgbe_sfp_type_25g_lr_core1) { + *speed = TXGBE_LINK_SPEED_25GB_FULL; + *autoneg = false; + } else if (hw->phy.sfp_type == txgbe_sfp_type_25g_aoc_core0 || + hw->phy.sfp_type == txgbe_sfp_type_25g_aoc_core1) { + *speed = TXGBE_LINK_SPEED_25GB_FULL; + *autoneg = false; + } else { + /* SFP */ + if (hw->phy.sfp_type == txgbe_sfp_type_not_present) + *speed = TXGBE_LINK_SPEED_25GB_FULL; + else + *speed = TXGBE_LINK_SPEED_10GB_FULL; + *autoneg = true; + } + + return 0; +} + +u32 txgbe_get_media_type_aml(struct txgbe_hw *hw) +{ + u8 device_type = hw->subsystem_device_id & 0xF0; + enum txgbe_media_type media_type; + + switch (device_type) { + case TXGBE_DEV_ID_KR_KX_KX4: + media_type = txgbe_media_type_backplane; + break; + case TXGBE_DEV_ID_SFP: + media_type = txgbe_media_type_fiber; + break; + default: + media_type = txgbe_media_type_unknown; + break; + } + + return media_type; +} + +s32 txgbe_setup_mac_link_aml(struct txgbe_hw *hw, + u32 speed, + bool autoneg_wait_to_complete) +{ + bool autoneg = false; + s32 status = 0; + u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN; + bool link_up = false; + u32 link_capabilities = TXGBE_LINK_SPEED_UNKNOWN; + u32 value = 0; + + UNREFERENCED_PARAMETER(autoneg_wait_to_complete); + + if (hw->phy.sfp_type == txgbe_sfp_type_not_present) { + DEBUGOUT("SFP not detected, skip setup mac link"); + return 0; + } + + /* Check to see if speed passed in is supported. */ + status = hw->mac.get_link_capabilities(hw, + &link_capabilities, &autoneg); + if (status) + return status; + + speed &= link_capabilities; + if (speed == TXGBE_LINK_SPEED_UNKNOWN) + return TXGBE_ERR_LINK_SETUP; + + value = rd32(hw, TXGBE_GPIOEXT); + if (value & (TXGBE_SFP1_MOD_ABS_LS | TXGBE_SFP1_RX_LOS_LS)) + return status; + + return status; +} + +/** + * txgbe_setup_mac_link_multispeed_fiber_aml - Set MAC link speed + * @hw: pointer to hardware structure + * @speed: new link speed + * @autoneg_wait_to_complete: true when waiting for completion is needed + * + * Set the link speed in the MAC and/or PHY register and restarts link. + **/ +static s32 txgbe_setup_mac_link_multispeed_fiber_aml(struct txgbe_hw *hw, + u32 speed, + bool autoneg_wait_to_complete) +{ + u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN; + u32 highest_link_speed = TXGBE_LINK_SPEED_UNKNOWN; + s32 status = 0; + u32 speedcnt = 0; + bool autoneg, link_up = false; + + /* Mask off requested but non-supported speeds */ + status = hw->mac.get_link_capabilities(hw, &link_speed, &autoneg); + if (status != 0) + return status; + + speed &= link_speed; + + /* Try each speed one by one, highest priority first. We do this in + * software because 25Gb fiber doesn't support speed autonegotiation. + */ + if (speed & TXGBE_LINK_SPEED_25GB_FULL) { + speedcnt++; + highest_link_speed = TXGBE_LINK_SPEED_25GB_FULL; + + /* If we already have link at this speed, just jump out */ + txgbe_e56_check_phy_link(hw, &link_speed, &link_up); + + if (link_speed == TXGBE_LINK_SPEED_25GB_FULL && link_up) + goto out; + + /* Allow module to change analog characteristics (10G -> 25G) */ + msec_delay(40); + + status = hw->mac.setup_mac_link(hw, + TXGBE_LINK_SPEED_25GB_FULL, + autoneg_wait_to_complete); + if (status != 0) + return status; + + /* Aml wait link in setup, no need to repeatedly wait */ + /* If we have link, just jump out */ + txgbe_e56_check_phy_link(hw, &link_speed, &link_up); + + if (link_up) + goto out; + } + + if (speed & TXGBE_LINK_SPEED_10GB_FULL) { + speedcnt++; + if (highest_link_speed == TXGBE_LINK_SPEED_UNKNOWN) + highest_link_speed = TXGBE_LINK_SPEED_10GB_FULL; + + /* If we already have link at this speed, just jump out */ + txgbe_e56_check_phy_link(hw, &link_speed, &link_up); + + if (link_speed == TXGBE_LINK_SPEED_10GB_FULL && link_up) + goto out; + + /* Allow module to change analog characteristics (25G->10G) */ + msec_delay(40); + + status = hw->mac.setup_mac_link(hw, TXGBE_LINK_SPEED_10GB_FULL, + autoneg_wait_to_complete); + if (status != 0) + return status; + + /* Aml wait link in setup, no need to repeatedly wait */ + /* If we have link, just jump out */ + txgbe_e56_check_phy_link(hw, &link_speed, &link_up); + + if (link_up) + goto out; + } + + /* We didn't get link. Configure back to the highest speed we tried, + * (if there was more than one). We call ourselves back with just the + * single highest speed that the user requested. + */ + if (speedcnt > 1) + status = txgbe_setup_mac_link_multispeed_fiber_aml(hw, + highest_link_speed, + autoneg_wait_to_complete); + +out: + /* Set autoneg_advertised value based on input link speed */ + hw->phy.autoneg_advertised = 0; + + if (speed & TXGBE_LINK_SPEED_25GB_FULL) + hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_25GB_FULL; + + if (speed & TXGBE_LINK_SPEED_10GB_FULL) + hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL; + + return status; +} + +void txgbe_init_mac_link_ops_aml(struct txgbe_hw *hw) +{ + struct txgbe_mac_info *mac = &hw->mac; + + if (hw->phy.media_type == txgbe_media_type_fiber || + hw->phy.media_type == txgbe_media_type_fiber_qsfp) { + mac->disable_tx_laser = + txgbe_disable_tx_laser_multispeed_fiber; + mac->enable_tx_laser = + txgbe_enable_tx_laser_multispeed_fiber; + mac->flap_tx_laser = + txgbe_flap_tx_laser_multispeed_fiber; + + if (hw->phy.multispeed_fiber) { + /* Set up dual speed SFP+ support */ + mac->setup_link = txgbe_setup_mac_link_multispeed_fiber_aml; + mac->setup_mac_link = txgbe_setup_mac_link_aml; + mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed; + } else { + mac->setup_link = txgbe_setup_mac_link_aml; + mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed; + } + } +} diff --git a/drivers/net/txgbe/base/txgbe_aml.h b/drivers/net/txgbe/base/txgbe_aml.h new file mode 100644 index 0000000000..18f683a746 --- /dev/null +++ b/drivers/net/txgbe/base/txgbe_aml.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2015-2025 Beijing WangXun Technology Co., Ltd. + * Copyright(c) 2010-2017 Intel Corporation + */ + +#ifndef _TXGBE_AML_H_ +#define _TXGBE_AML_H_ + +#include "txgbe_type.h" + +void txgbe_init_ops_aml(struct txgbe_hw *hw); +s32 txgbe_check_mac_link_aml(struct txgbe_hw *hw, + u32 *speed, + bool *link_up, bool link_up_wait_to_complete); +s32 txgbe_get_link_capabilities_aml(struct txgbe_hw *hw, + u32 *speed, bool *autoneg); +u32 txgbe_get_media_type_aml(struct txgbe_hw *hw); +s32 txgbe_setup_mac_link_aml(struct txgbe_hw *hw, u32 speed, + bool autoneg_wait_to_complete); +void txgbe_init_mac_link_ops_aml(struct txgbe_hw *hw); +#endif /* _TXGBE_AML_H_ */ diff --git a/drivers/net/txgbe/base/txgbe_aml40.c b/drivers/net/txgbe/base/txgbe_aml40.c new file mode 100644 index 0000000000..d11773916b --- /dev/null +++ b/drivers/net/txgbe/base/txgbe_aml40.c @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2015-2025 Beijing WangXun Technology Co., Ltd. + * Copyright(c) 2010-2017 Intel Corporation + */ + +#include "txgbe_type.h" +#include "txgbe_mbx.h" +#include "txgbe_phy.h" +#include "txgbe_dcb.h" +#include "txgbe_vf.h" +#include "txgbe_eeprom.h" +#include "txgbe_mng.h" +#include "txgbe_hw.h" +#include "txgbe_aml.h" +#include "txgbe_aml40.h" + +void txgbe_init_ops_aml40(struct txgbe_hw *hw) +{ + struct txgbe_mac_info *mac = &hw->mac; + struct txgbe_phy_info *phy = &hw->phy; + + txgbe_init_ops_generic(hw); + + /* PHY */ + phy->get_media_type = txgbe_get_media_type_aml40; + + /* LINK */ + mac->init_mac_link_ops = txgbe_init_mac_link_ops_aml40; + mac->get_link_capabilities = txgbe_get_link_capabilities_aml40; + mac->check_link = txgbe_check_mac_link_aml40; +} + +s32 txgbe_check_mac_link_aml40(struct txgbe_hw *hw, u32 *speed, + bool *link_up, bool link_up_wait_to_complete) +{ + u32 links_reg, links_orig; + u32 i; + + /* clear the old state */ + links_orig = rd32(hw, TXGBE_PORTSTAT); + + links_reg = rd32(hw, TXGBE_PORTSTAT); + + if (links_orig != links_reg) { + DEBUGOUT("LINKS changed from %08X to %08X", + links_orig, links_reg); + } + + if (link_up_wait_to_complete) { + for (i = 0; i < hw->mac.max_link_up_time; i++) { + if (!(links_reg & TXGBE_PORTSTAT_UP)) { + *link_up = false; + } else { + *link_up = true; + break; + } + msec_delay(100); + links_reg = rd32(hw, TXGBE_PORTSTAT); + } + } else { + if (links_reg & TXGBE_PORTSTAT_UP) + *link_up = true; + else + *link_up = false; + } + + if (link_up) { + if ((links_reg & TXGBE_CFG_PORT_ST_AML_LINK_40G) == + TXGBE_CFG_PORT_ST_AML_LINK_40G) + *speed = TXGBE_LINK_SPEED_40GB_FULL; + } else { + *speed = TXGBE_LINK_SPEED_UNKNOWN; + } + + return 0; +} + +s32 txgbe_get_link_capabilities_aml40(struct txgbe_hw *hw, + u32 *speed, + bool *autoneg) +{ + if (hw->phy.sfp_type == txgbe_qsfp_type_40g_cu_core0 || + hw->phy.sfp_type == txgbe_qsfp_type_40g_cu_core1) { + *speed = TXGBE_LINK_SPEED_40GB_FULL; + *autoneg = false; + } else { + /* + * Temporary workaround: set speed to 40G even if sfp not present + * to avoid TXGBE_ERR_LINK_SETUP returned by setup_mac_link, but + * a more reasonable solution is don't execute setup_mac_link when + * sfp module not present. + */ + *speed = TXGBE_LINK_SPEED_40GB_FULL; + *autoneg = true; + } + + return 0; +} + +u32 txgbe_get_media_type_aml40(struct txgbe_hw *hw) +{ + UNREFERENCED_PARAMETER(hw); + return txgbe_media_type_fiber_qsfp; +} + +s32 txgbe_setup_mac_link_aml40(struct txgbe_hw *hw, + u32 speed, + bool autoneg_wait_to_complete) +{ + return 0; +} + +void txgbe_init_mac_link_ops_aml40(struct txgbe_hw *hw) +{ + struct txgbe_mac_info *mac = &hw->mac; + + mac->disable_tx_laser = + txgbe_disable_tx_laser_multispeed_fiber; + mac->enable_tx_laser = + txgbe_enable_tx_laser_multispeed_fiber; + mac->flap_tx_laser = + txgbe_flap_tx_laser_multispeed_fiber; + + mac->setup_link = txgbe_setup_mac_link_aml40; + mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed; +} diff --git a/drivers/net/txgbe/base/txgbe_aml40.h b/drivers/net/txgbe/base/txgbe_aml40.h new file mode 100644 index 0000000000..f31360c899 --- /dev/null +++ b/drivers/net/txgbe/base/txgbe_aml40.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2015-2025 Beijing WangXun Technology Co., Ltd. + * Copyright(c) 2010-2017 Intel Corporation + */ + +#ifndef _TXGBE_AML40_H_ +#define _TXGBE_AML40_H_ + +#include "txgbe_type.h" + +void txgbe_init_ops_aml40(struct txgbe_hw *hw); +s32 txgbe_check_mac_link_aml40(struct txgbe_hw *hw, + u32 *speed, bool *link_up, bool link_up_wait_to_complete); +s32 txgbe_get_link_capabilities_aml40(struct txgbe_hw *hw, + u32 *speed, bool *autoneg); +u32 txgbe_get_media_type_aml40(struct txgbe_hw *hw); +s32 txgbe_setup_mac_link_aml40(struct txgbe_hw *hw, u32 speed, + bool autoneg_wait_to_complete); +void txgbe_init_mac_link_ops_aml40(struct txgbe_hw *hw); +#endif /* _TXGBE_AML40_H_ */ diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c index 81e686fdf1..1bfc07d930 100644 --- a/drivers/net/txgbe/base/txgbe_hw.c +++ b/drivers/net/txgbe/base/txgbe_hw.c @@ -11,6 +11,8 @@ #include "txgbe_eeprom.h" #include "txgbe_mng.h" #include "txgbe_hw.h" +#include "txgbe_aml.h" +#include "txgbe_aml40.h" #define TXGBE_RAPTOR_MAX_TX_QUEUES 128 #define TXGBE_RAPTOR_MAX_RX_QUEUES 128 @@ -2466,7 +2468,7 @@ s32 txgbe_setup_mac_link_multispeed_fiber(struct txgbe_hw *hw, **/ s32 txgbe_init_shared_code(struct txgbe_hw *hw) { - s32 status; + s32 status = 0; /* * Set the mac type @@ -2479,9 +2481,13 @@ s32 txgbe_init_shared_code(struct txgbe_hw *hw) txgbe_init_ops_sp(hw); break; case txgbe_mac_aml: + txgbe_init_ops_aml(hw); + break; case txgbe_mac_aml40: + txgbe_init_ops_aml40(hw); break; case txgbe_mac_sp_vf: + case txgbe_mac_aml_vf: status = txgbe_init_ops_vf(hw); break; default: @@ -2617,7 +2623,7 @@ s32 txgbe_init_phy_raptor(struct txgbe_hw *hw) goto init_phy_ops_out; /* Setup function pointers based on detected SFP module and speeds */ - txgbe_init_mac_link_ops_sp(hw); + hw->mac.init_mac_link_ops(hw); /* If copper media, overwrite with copper function pointers */ if (phy->media_type == txgbe_media_type_copper) { @@ -2652,7 +2658,7 @@ s32 txgbe_setup_sfp_modules(struct txgbe_hw *hw) if (hw->phy.sfp_type == txgbe_sfp_type_unknown) return 0; - txgbe_init_mac_link_ops_sp(hw); + hw->mac.init_mac_link_ops(hw); /* PHY config will finish before releasing the semaphore */ err = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY); @@ -2811,7 +2817,6 @@ s32 txgbe_init_ops_generic(struct txgbe_hw *hw) bus->set_lan_id = txgbe_set_lan_id_multi_port; /* PHY */ - phy->get_media_type = txgbe_get_media_type_raptor; phy->identify = txgbe_identify_phy; phy->init = txgbe_init_phy_raptor; phy->read_reg = txgbe_read_phy_reg; @@ -2879,8 +2884,6 @@ s32 txgbe_init_ops_generic(struct txgbe_hw *hw) mac->fc_autoneg = txgbe_fc_autoneg; /* Link */ - mac->get_link_capabilities = txgbe_get_link_capabilities_raptor; - mac->check_link = txgbe_check_mac_link; mac->setup_pba = txgbe_set_pba; /* Manageability interface */ @@ -3886,3 +3889,37 @@ s32 txgbe_reset_pipeline_raptor(struct txgbe_hw *hw) return err; } +s32 txgbe_e56_check_phy_link(struct txgbe_hw *hw, u32 *speed, + bool *link_up) +{ + u32 rdata = 0; + u32 links_reg = 0; + + /* must read it twice because the state may + * not be correct the first time you read it + */ + rdata = rd32_epcs(hw, 0x30001); + rdata = rd32_epcs(hw, 0x30001); + + if (rdata & TXGBE_AML_PHY_LINK_UP) + *link_up = true; + else + *link_up = false; + + links_reg = rd32(hw, TXGBE_PORTSTAT); + if (*link_up) { + if ((links_reg & TXGBE_CFG_PORT_ST_AML_LINK_40G) == + TXGBE_CFG_PORT_ST_AML_LINK_40G) + *speed = TXGBE_LINK_SPEED_40GB_FULL; + else if ((links_reg & TXGBE_CFG_PORT_ST_AML_LINK_25G) == + TXGBE_CFG_PORT_ST_AML_LINK_25G) + *speed = TXGBE_LINK_SPEED_25GB_FULL; + else if ((links_reg & TXGBE_CFG_PORT_ST_AML_LINK_10G) == + TXGBE_CFG_PORT_ST_AML_LINK_10G) + *speed = TXGBE_LINK_SPEED_10GB_FULL; + } else { + *speed = TXGBE_LINK_SPEED_UNKNOWN; + } + + return 0; +} diff --git a/drivers/net/txgbe/base/txgbe_hw.h b/drivers/net/txgbe/base/txgbe_hw.h index 62c027c850..7afc800f8d 100644 --- a/drivers/net/txgbe/base/txgbe_hw.h +++ b/drivers/net/txgbe/base/txgbe_hw.h @@ -116,4 +116,6 @@ s32 txgbe_reinit_fdir_tables(struct txgbe_hw *hw); bool txgbe_verify_lesm_fw_enabled_raptor(struct txgbe_hw *hw); s32 txgbe_fmgr_cmd_op(struct txgbe_hw *hw, u32 cmd, u32 cmd_addr); s32 txgbe_flash_read_dword(struct txgbe_hw *hw, u32 addr, u32 *data); +s32 txgbe_e56_check_phy_link(struct txgbe_hw *hw, u32 *speed, + bool *link_up); #endif /* _TXGBE_HW_H_ */ diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h index ab1a11230c..5709245068 100644 --- a/drivers/net/txgbe/base/txgbe_regs.h +++ b/drivers/net/txgbe/base/txgbe_regs.h @@ -1581,6 +1581,15 @@ enum txgbe_5tuple_protocol { #define TXGBE_PORTSTAT_BW_100M MS(3, 0x1) #define TXGBE_PORTSTAT_ID(r) RS(r, 8, 0x1) +/* amlite: diff from sapphire */ +#define TXGBE_CFG_PORT_ST_AML_LINK_MASK MS(1, 0xF) +#define TXGBE_CFG_PORT_ST_AML_LINK_10G MS(4, 0x1) +#define TXGBE_CFG_PORT_ST_AML_LINK_25G MS(3, 0x1) +#define TXGBE_CFG_PORT_ST_AML_LINK_40G MS(2, 0x1) +#define TXGBE_CFG_PORT_ST_AML_LINK_50G MS(1, 0x1) + +#define TXGBE_AML_PHY_LINK_UP MS(2, 0x1) + #define TXGBE_VXLAN 0x014410 #define TXGBE_VXLAN_GPE 0x014414 #define TXGBE_GENEVE 0x014418 diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h index 4d825bec44..8be0c6cd57 100644 --- a/drivers/net/txgbe/base/txgbe_type.h +++ b/drivers/net/txgbe/base/txgbe_type.h @@ -828,6 +828,7 @@ struct txgbe_hw { u64 rx_qp_mc_packets; } qp_last[TXGBE_MAX_QP]; + rte_spinlock_t phy_lock; /*amlite: new SW-FW mbox */ u8 swfw_index; rte_atomic32_t swfw_busy; diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c index 82cec488f4..0e2f25ad76 100644 --- a/drivers/net/txgbe/txgbe_ethdev.c +++ b/drivers/net/txgbe/txgbe_ethdev.c @@ -3069,6 +3069,14 @@ txgbe_dev_link_update_share(struct rte_eth_dev *dev, case TXGBE_LINK_SPEED_10GB_FULL: link.link_speed = RTE_ETH_SPEED_NUM_10G; break; + + case TXGBE_LINK_SPEED_25GB_FULL: + link.link_speed = RTE_ETH_SPEED_NUM_25G; + break; + + case TXGBE_LINK_SPEED_40GB_FULL: + link.link_speed = RTE_ETH_SPEED_NUM_40G; + break; } /* Re configure MAC RX */ From patchwork Tue Sep 30 09:59:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zaiyu Wang X-Patchwork-Id: 157119 X-Patchwork-Delegate: stephen@networkplumber.org Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 08BFE4886F; Tue, 30 Sep 2025 12:01:02 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0C2FD40A84; Tue, 30 Sep 2025 12:00:39 +0200 (CEST) Received: from smtpbgbr2.qq.com (smtpbgbr2.qq.com [54.207.22.56]) by mails.dpdk.org (Postfix) with ESMTP id 4751F40A75 for ; Tue, 30 Sep 2025 12:00:35 +0200 (CEST) X-QQ-mid: esmtpgz13t1759226430t1ab6a14f X-QQ-Originating-IP: NDRFMYRO6Vuydm3pWrw+mG4RmcyfSTSDTaHVb+zg1oc= Received: from DSK-zaiyuwang.trustnetic.com ( [115.220.225.164]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 30 Sep 2025 18:00:29 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 16241656349860973096 EX-QQ-RecipientCnt: 4 From: Zaiyu Wang To: dev@dpdk.org Cc: Zaiyu Wang , Jiawen Wu , Jian Wang Subject: [PATCH v4 06/20] net/txgbe: add support for PHY configuration via SW-FW mailbox Date: Tue, 30 Sep 2025 17:59:38 +0800 Message-Id: <20250930095953.18508-7-zaiyuwang@trustnetic.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20250930095953.18508-1-zaiyuwang@trustnetic.com> References: <20250418094131.24136-1-zaiyuwang@trustnetic.com> <20250930095953.18508-1-zaiyuwang@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:trustnetic.com:qybglogicsvrgz:qybglogicsvrgz5a-1 X-QQ-XMAILINFO: NOIkHYnr7VzdF5DodGZMKE1vAG+f1ugkoJDcD2MUXk8c848iGJiWDwE2 SCsRpLfOzdd6J5ycg1U+uJzPOiN9FgJy19IJEPTKlVBU+O4Y3At9OXvIP2b50/Pc2V5w9dM ONe3P98ahofWGhWaA7EaQCnLywMYDXdI1COQGkbqUyT9Mnz+kcgJz4SCrFLgN5dvuOYoaB1 KqTzcBgncY3BtamUuL5IlrZQkiD5+iBXjVD0zZFMvNUKUYnX0OCgeaCtXCtv36ohZFN/4xe fYBdnQyg6UJcwahz9K2qSdF5Dbhn4jW2ABj7H3TcMmH6TBTAw6NPkI3nNgoeU0V0kdgsAvw YVuCf1wkPPZ/YQvp0uDwST/z1EJE33gsdw/hN73IqKsFxV4muh1TdpO2SGKS6MLGl7B7bkx NNsZVkpUImR3J/GY1tAnbE2IXwB347maM7QChck1hvrMh2sZV6MhoD+SCMBiDtN7ct2toSh pHinK6Tqtr69/tFvQHU2dhVxUxzqakGS6vKLieVzORk9++yneQbF74SsB0YvfDp7OfoiWWd TqG+YP3bdFd4lnPxTquSu7a2K17tTy3GZPJoIBjHXWQdVcYq+wIONwfJxb8DMM2tOpCkaou oJ9nl2mJEsl6+NlnHFaSbVTUStpcb7DFwgV9XsPkP5a6oWCDrvSBkEoNvEvYDZ2l0hMVLVg opCyjpV5JKL7sJMNfLkZ7VXpUVluHrn6Z90AwqiGneJQzx0noitBkJ63ptKSNv818BRzis5 kQUEaJ3BoqfGIERNuAsD2Tn77WwQ3AYsUSynhjhFlPNw82eBLhvHyoVJ5hk38fFc2jZfOHH f0xm6xsm7c4odr7O8+Si010GX9vmFQoSatLWUq7RFj5aaW482NsAnDDbQqfXCitsYLtsGOd Ti7nLsKXUSQVaEGab/88nZCgdKzcinIJIZOqtmhazsuFmEdhPSo8CbM8VwOTEWPyACQBzvN enmU+MW8/jNnlKfVDoIC7/mPwNlDBKeiyWR7Pm53hBBrsr4zlqOn2xoXdOcX3/UnaScbwpA FGfacu++iATI2ndxlea6BIaZmBwn6EZG6y4cLvbeRwemaHn5C//ZAjeLM89uY= X-QQ-XMRINFO: OWPUhxQsoeAVDbp3OJHYyFg= X-QQ-RECHKSPAM: 0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Migrate Amber-Lite PHY configuration to firmware due to complexity. Driver now sends mailbox commands for link state changes, handled by firmware’s intricate PHY setup process Signed-off-by: Zaiyu Wang --- drivers/net/txgbe/base/txgbe_aml.c | 37 ++++++++++++++++++++++++++-- drivers/net/txgbe/base/txgbe_aml40.c | 37 +++++++++++++++++++++++++++- drivers/net/txgbe/base/txgbe_hw.c | 1 + drivers/net/txgbe/base/txgbe_mng.c | 36 +++++++++++++++++++++++++++ drivers/net/txgbe/base/txgbe_mng.h | 17 +++++++++++++ drivers/net/txgbe/base/txgbe_type.h | 7 ++++++ 6 files changed, 132 insertions(+), 3 deletions(-) diff --git a/drivers/net/txgbe/base/txgbe_aml.c b/drivers/net/txgbe/base/txgbe_aml.c index b172622ac7..bf63975a15 100644 --- a/drivers/net/txgbe/base/txgbe_aml.c +++ b/drivers/net/txgbe/base/txgbe_aml.c @@ -131,6 +131,26 @@ u32 txgbe_get_media_type_aml(struct txgbe_hw *hw) return media_type; } +static void txgbe_wait_for_link_up_aml(struct txgbe_hw *hw, u32 speed) +{ + u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN; + bool link_up = false; + int cnt = 0; + int i; + + if (speed == TXGBE_LINK_SPEED_25GB_FULL) + cnt = 4; + else + cnt = 1; + + for (i = 0; i < (4 * cnt); i++) { + hw->mac.check_link(hw, &link_speed, &link_up, false); + if (link_up) + break; + msleep(250); + } +} + s32 txgbe_setup_mac_link_aml(struct txgbe_hw *hw, u32 speed, bool autoneg_wait_to_complete) @@ -142,8 +162,6 @@ s32 txgbe_setup_mac_link_aml(struct txgbe_hw *hw, u32 link_capabilities = TXGBE_LINK_SPEED_UNKNOWN; u32 value = 0; - UNREFERENCED_PARAMETER(autoneg_wait_to_complete); - if (hw->phy.sfp_type == txgbe_sfp_type_not_present) { DEBUGOUT("SFP not detected, skip setup mac link"); return 0; @@ -163,6 +181,21 @@ s32 txgbe_setup_mac_link_aml(struct txgbe_hw *hw, if (value & (TXGBE_SFP1_MOD_ABS_LS | TXGBE_SFP1_RX_LOS_LS)) return status; + status = hw->mac.check_link(hw, &link_speed, &link_up, + autoneg_wait_to_complete); + + if (link_speed == speed && link_up) + return status; + + if (speed & TXGBE_LINK_SPEED_25GB_FULL) + speed = 0x10; + else if (speed & TXGBE_LINK_SPEED_10GB_FULL) + speed = 0x08; + + status = hw->phy.set_link_hostif(hw, (u8)speed, autoneg, true); + + txgbe_wait_for_link_up_aml(hw, speed); + return status; } diff --git a/drivers/net/txgbe/base/txgbe_aml40.c b/drivers/net/txgbe/base/txgbe_aml40.c index d11773916b..597b42951e 100644 --- a/drivers/net/txgbe/base/txgbe_aml40.c +++ b/drivers/net/txgbe/base/txgbe_aml40.c @@ -107,7 +107,42 @@ s32 txgbe_setup_mac_link_aml40(struct txgbe_hw *hw, u32 speed, bool autoneg_wait_to_complete) { - return 0; + bool autoneg = false; + s32 status = 0; + u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN; + bool link_up = false; + u32 link_capabilities = TXGBE_LINK_SPEED_UNKNOWN; + u32 value = 0; + + if (hw->phy.sfp_type == txgbe_sfp_type_not_present) { + DEBUGOUT("SFP not detected, skip setup mac link"); + return 0; + } + + /* Check to see if speed passed in is supported. */ + status = hw->mac.get_link_capabilities(hw, + &link_capabilities, &autoneg); + if (status) + return status; + + speed &= link_capabilities; + if (speed == TXGBE_LINK_SPEED_UNKNOWN) + return TXGBE_ERR_LINK_SETUP; + + status = hw->mac.check_link(hw, &link_speed, &link_up, + autoneg_wait_to_complete); + + if (link_speed == speed && link_up) + return status; + + if (speed & TXGBE_LINK_SPEED_40GB_FULL) + speed = 0x20; + + status = hw->phy.set_link_hostif(hw, (u8)speed, autoneg, true); + + txgbe_wait_for_link_up_aml(hw, speed); + + return status; } void txgbe_init_mac_link_ops_aml40(struct txgbe_hw *hw) diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c index 1bfc07d930..ef1c3c06ea 100644 --- a/drivers/net/txgbe/base/txgbe_hw.c +++ b/drivers/net/txgbe/base/txgbe_hw.c @@ -2836,6 +2836,7 @@ s32 txgbe_init_ops_generic(struct txgbe_hw *hw) phy->write_i2c_byte_unlocked = txgbe_write_i2c_byte_unlocked; phy->check_overtemp = txgbe_check_overtemp; phy->reset = txgbe_reset_phy; + phy->set_link_hostif = txgbe_hic_ephy_set_link; /* MAC */ mac->init_hw = txgbe_init_hw; diff --git a/drivers/net/txgbe/base/txgbe_mng.c b/drivers/net/txgbe/base/txgbe_mng.c index 8839450b44..782e86e1fa 100644 --- a/drivers/net/txgbe/base/txgbe_mng.c +++ b/drivers/net/txgbe/base/txgbe_mng.c @@ -602,3 +602,39 @@ s32 txgbe_hic_set_lldp(struct txgbe_hw *hw, bool on) return txgbe_host_interface_command(hw, (u32 *)&buffer, sizeof(buffer), TXGBE_HI_COMMAND_TIMEOUT, false); } + +s32 txgbe_hic_ephy_set_link(struct txgbe_hw *hw, u8 speed, u8 autoneg, u8 duplex) +{ + struct txgbe_hic_ephy_setlink buffer; + s32 status; + int i; + + buffer.hdr.cmd = FW_PHY_CONFIG_LINK_CMD; + buffer.hdr.buf_len = sizeof(struct txgbe_hic_ephy_setlink) - sizeof(struct txgbe_hic_hdr); + buffer.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; + + buffer.fec_mode = TXGBE_PHY_FEC_AUTO; + buffer.speed = speed; + buffer.autoneg = autoneg; + buffer.duplex = duplex; + + for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { + status = txgbe_host_interface_command(hw, (u32 *)&buffer, + sizeof(buffer), + TXGBE_HI_COMMAND_TIMEOUT_SHORT, true); + if (status != 0) { + msleep(1); + continue; + } + + if (buffer.hdr.cmd_or_resp.ret_status == + FW_CEM_RESP_STATUS_SUCCESS) + status = 0; + else + status = TXGBE_ERR_HOST_INTERFACE_COMMAND; + + break; + } + + return status; +} diff --git a/drivers/net/txgbe/base/txgbe_mng.h b/drivers/net/txgbe/base/txgbe_mng.h index 613aa7b88a..53c5cd5487 100644 --- a/drivers/net/txgbe/base/txgbe_mng.h +++ b/drivers/net/txgbe/base/txgbe_mng.h @@ -13,6 +13,7 @@ #define TXGBE_PMMBX_BSIZE (TXGBE_PMMBX_QSIZE * 4) #define TXGBE_PMMBX_DATA_SIZE (TXGBE_PMMBX_BSIZE - FW_NVM_DATA_OFFSET * 4) #define TXGBE_HI_COMMAND_TIMEOUT 5000 /* Process HI command limit */ +#define TXGBE_HI_COMMAND_TIMEOUT_SHORT 500 /* Process HI command limit */ #define TXGBE_HI_FLASH_ERASE_TIMEOUT 5000 /* Process Erase command limit */ #define TXGBE_HI_FLASH_UPDATE_TIMEOUT 5000 /* Process Update command limit */ #define TXGBE_HI_FLASH_VERIFY_TIMEOUT 60000 /* Process Apply command limit */ @@ -56,6 +57,12 @@ #define FW_LLDP_GET_CMD 0xF2 #define FW_LLDP_SET_CMD_OFF 0xF1 #define FW_LLDP_SET_CMD_ON 0xF0 +#define FW_PHY_CONFIG_READ_CMD 0xc0 +#define FW_PHY_CONFIG_LINK_CMD 0xc1 +#define FW_PHY_CONFIG_FC_CMD 0xc2 +#define FW_PHY_CONFIG_POWER_CMD 0xc3 +#define FW_PHY_CONFIG_RESET_CMD 0xc4 +#define FW_READ_SFP_INFO_CMD 0xc5 #define TXGBE_CHECKSUM_CAP_ST_PASS 0x80658383 #define TXGBE_CHECKSUM_CAP_ST_FAIL 0x70657376 @@ -101,6 +108,15 @@ union txgbe_hic_hdr2 { struct txgbe_hic_hdr2_rsp rsp; }; +struct txgbe_hic_ephy_setlink { + struct txgbe_hic_hdr hdr; + u8 speed; + u8 duplex; + u8 autoneg; + u8 fec_mode; + u8 resv[4]; +}; + struct txgbe_hic_drv_info { struct txgbe_hic_hdr hdr; u8 port_num; @@ -204,5 +220,6 @@ bool txgbe_mng_present(struct txgbe_hw *hw); bool txgbe_mng_enabled(struct txgbe_hw *hw); s32 txgbe_hic_get_lldp(struct txgbe_hw *hw); s32 txgbe_hic_set_lldp(struct txgbe_hw *hw, bool on); +s32 txgbe_hic_ephy_set_link(struct txgbe_hw *hw, u8 speed, u8 autoneg, u8 duplex); #endif /* _TXGBE_MNG_H_ */ diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h index 8be0c6cd57..55123d0b6c 100644 --- a/drivers/net/txgbe/base/txgbe_type.h +++ b/drivers/net/txgbe/base/txgbe_type.h @@ -681,6 +681,7 @@ struct txgbe_phy_info { u8 *value); s32 (*write_i2c_byte_unlocked)(struct txgbe_hw *hw, u8 offset, u8 addr, u8 value); + s32 (*set_link_hostif)(struct txgbe_hw *hw, u8 speed, u8 autoneg, u8 duplex); enum txgbe_phy_type type; u32 addr; @@ -764,6 +765,12 @@ enum txgbe_isb_idx { TXGBE_ISB_MAX }; +#define TXGBE_PHY_FEC_RS MS(0, 0x1) +#define TXGBE_PHY_FEC_BASER MS(1, 0x1) +#define TXGBE_PHY_FEC_OFF MS(2, 0x1) +#define TXGBE_PHY_FEC_AUTO (TXGBE_PHY_FEC_OFF | TXGBE_PHY_FEC_BASER |\ + TXGBE_PHY_FEC_RS) + struct txgbe_devargs { u16 auto_neg; u16 poll; From patchwork Tue Sep 30 09:59:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zaiyu Wang X-Patchwork-Id: 157120 X-Patchwork-Delegate: stephen@networkplumber.org Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5C77B4886F; Tue, 30 Sep 2025 12:01:09 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 14D9840DCB; Tue, 30 Sep 2025 12:00:42 +0200 (CEST) Received: from smtpbguseast1.qq.com (smtpbguseast1.qq.com [54.204.34.129]) by mails.dpdk.org (Postfix) with ESMTP id 354D140695 for ; Tue, 30 Sep 2025 12:00:38 +0200 (CEST) X-QQ-mid: esmtpgz13t1759226435t7859a387 X-QQ-Originating-IP: M7jH+/cn6MapuA0BwJdqQEX2HyJhLnynA1gHGzKX3nI= Received: from DSK-zaiyuwang.trustnetic.com ( [115.220.225.164]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 30 Sep 2025 18:00:31 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 3925479006266721470 EX-QQ-RecipientCnt: 4 From: Zaiyu Wang To: dev@dpdk.org Cc: Zaiyu Wang , Jiawen Wu , Jian Wang Subject: [PATCH v4 07/20] net/txgbe: add RX&TX support for Amber-Lite NICs Date: Tue, 30 Sep 2025 17:59:39 +0800 Message-Id: <20250930095953.18508-8-zaiyuwang@trustnetic.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20250930095953.18508-1-zaiyuwang@trustnetic.com> References: <20250418094131.24136-1-zaiyuwang@trustnetic.com> <20250930095953.18508-1-zaiyuwang@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:trustnetic.com:qybglogicsvrgz:qybglogicsvrgz5a-1 X-QQ-XMAILINFO: OKpEC/bXOl3KA+2rTGTj6zIDLCXOXdm1yIm730NfnhyTzAGdRCYl+9Dn 38qbpey7RNCkfiSGQn+csH/F2V2RhJPl/KJhPs6tQN0aI8HwxkjIw/sB09fPi5KFJ8OL7nt 4AHNPDkbmLbwBVzD3aLQFwyV9VuEOJ4XHYvLNqT6gy4awBlop7svRPuGZIIY50vURSCVr4P 9qHwxDDtXA5BihOlfX2M04MsGf1Z7pnKF2gFyGP6oNfuVIGjnIH+HqIX0MIKFFmTSKTFpvJ QUiW1d4OgoxtxJBnNvcwV7+TI3EPoC8zWhBeMUOAytaMgWDcmDDQuHAjvaeAfhJIWlWyyJJ qGBJAgszQJjItdh0Y1VFD9EqBxjiwB3Fr/78q6a2WDBl04zz6trn8GNHXTOy0dbCT4CrDG6 iptSnf5jBY855Q+fG3IPijuGFMBx69g/tyuhOFl9vtHbVEFHaA0L/OlGVSGfqkrj/IkrlIm kERaGFNxtkDWfAQB0zVosJUXErrufokN5LIOgEuzliysEvHzP/5a44ltmvUdfkjLKXN/bEb IyFUOdi6dFTWp3IrchP/ePsIaj01hnYJJtyZO1yE4sB0ZnG/eyFo9cISEDMqaTsy41Au8VH hrfVUFFyuzbX65XZ6vcT5VHk6sRgs0yStzq+H4LDXnsklCISQrdMWuWN22WmNkJpEvMB5/G L76ZMIQAkpNz7M5Gs3eOXPk+Mo6fWzw4RnG6J8ngOq+grxHRIECx3xgW2rlw19/9G9QquzW 0rQeyYIerOXqj9rSU6/SbpRU0ZdqySYFrHSeKsnjKXYMqMhiMzy1+ulqb+e6RXFZ7ThS10G +Z0Typq6F1bKssTB3L2pDqafF9zSqdLV+48f7UbwU1E3MZn0K0/ZoUJsPq+wG4vS+IhX4cu InGCAQH95MN4x5de1TkOhW5ukAuA3GZHT8plUEzCA4eFZEk9mUYpmG9zAifoNb9mK6dyau1 HtXfZ8n4YTJPIR+VPqxUIpiBE72x0CNAHo7Iqqdac6ORi451OPpGkeaUO+diuSzqxVcncr6 XRG3R6BDJw4uPWtQ2lzabP/4aZ/KMKZnoVSQEUZbEjDJ2dE6y0Y3+dz+MP6UWX7yX5FBq4K cdUDs2LT74gsd7dfAiuB+c= X-QQ-XMRINFO: OD9hHCdaPRBwq3WW+NvGbIU= X-QQ-RECHKSPAM: 0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The packet handling workflow largely reuses the existing 10G NIC’s process, so we adjusted driver conditional checks rather than making major changes to the overall flow. Signed-off-by: Zaiyu Wang --- drivers/net/txgbe/base/txgbe_aml.c | 2 +- drivers/net/txgbe/base/txgbe_aml.h | 1 + drivers/net/txgbe/base/txgbe_aml40.c | 1 - drivers/net/txgbe/base/txgbe_hw.c | 17 ++++++++ drivers/net/txgbe/base/txgbe_hw.h | 1 + drivers/net/txgbe/base/txgbe_regs.h | 31 ++++++++++++++ drivers/net/txgbe/txgbe_ethdev.c | 12 ++++-- drivers/net/txgbe/txgbe_rxtx.c | 64 +++++++++++++++------------- 8 files changed, 94 insertions(+), 35 deletions(-) diff --git a/drivers/net/txgbe/base/txgbe_aml.c b/drivers/net/txgbe/base/txgbe_aml.c index bf63975a15..3283d3f56c 100644 --- a/drivers/net/txgbe/base/txgbe_aml.c +++ b/drivers/net/txgbe/base/txgbe_aml.c @@ -131,7 +131,7 @@ u32 txgbe_get_media_type_aml(struct txgbe_hw *hw) return media_type; } -static void txgbe_wait_for_link_up_aml(struct txgbe_hw *hw, u32 speed) +void txgbe_wait_for_link_up_aml(struct txgbe_hw *hw, u32 speed) { u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN; bool link_up = false; diff --git a/drivers/net/txgbe/base/txgbe_aml.h b/drivers/net/txgbe/base/txgbe_aml.h index 18f683a746..e98c952787 100644 --- a/drivers/net/txgbe/base/txgbe_aml.h +++ b/drivers/net/txgbe/base/txgbe_aml.h @@ -15,6 +15,7 @@ s32 txgbe_check_mac_link_aml(struct txgbe_hw *hw, s32 txgbe_get_link_capabilities_aml(struct txgbe_hw *hw, u32 *speed, bool *autoneg); u32 txgbe_get_media_type_aml(struct txgbe_hw *hw); +void txgbe_wait_for_link_up_aml(struct txgbe_hw *hw, u32 speed); s32 txgbe_setup_mac_link_aml(struct txgbe_hw *hw, u32 speed, bool autoneg_wait_to_complete); void txgbe_init_mac_link_ops_aml(struct txgbe_hw *hw); diff --git a/drivers/net/txgbe/base/txgbe_aml40.c b/drivers/net/txgbe/base/txgbe_aml40.c index 597b42951e..c7d64cade6 100644 --- a/drivers/net/txgbe/base/txgbe_aml40.c +++ b/drivers/net/txgbe/base/txgbe_aml40.c @@ -112,7 +112,6 @@ s32 txgbe_setup_mac_link_aml40(struct txgbe_hw *hw, u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN; bool link_up = false; u32 link_capabilities = TXGBE_LINK_SPEED_UNKNOWN; - u32 value = 0; if (hw->phy.sfp_type == txgbe_sfp_type_not_present) { DEBUGOUT("SFP not detected, skip setup mac link"); diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c index ef1c3c06ea..be8409c28e 100644 --- a/drivers/net/txgbe/base/txgbe_hw.c +++ b/drivers/net/txgbe/base/txgbe_hw.c @@ -20,6 +20,7 @@ #define TXGBE_RAPTOR_MC_TBL_SIZE 128 #define TXGBE_RAPTOR_VFT_TBL_SIZE 128 #define TXGBE_RAPTOR_RX_PB_SIZE 512 /*KB*/ +#define TXGBE_AML_RX_PB_SIZE 768 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw, u32 speed, @@ -2505,6 +2506,19 @@ bool txgbe_is_pf(struct txgbe_hw *hw) { switch (hw->mac.type) { case txgbe_mac_sp: + case txgbe_mac_aml: + case txgbe_mac_aml40: + return true; + default: + return false; + } +} + +bool txgbe_is_vf(struct txgbe_hw *hw) +{ + switch (hw->mac.type) { + case txgbe_mac_sp_vf: + case txgbe_mac_aml_vf: return true; default: return false; @@ -2920,6 +2934,9 @@ s32 txgbe_init_ops_generic(struct txgbe_hw *hw) mac->max_rx_queues = TXGBE_RAPTOR_MAX_RX_QUEUES; mac->max_tx_queues = TXGBE_RAPTOR_MAX_TX_QUEUES; + if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) + mac->rx_pb_size = TXGBE_AML_RX_PB_SIZE; + return 0; } diff --git a/drivers/net/txgbe/base/txgbe_hw.h b/drivers/net/txgbe/base/txgbe_hw.h index 7afc800f8d..ab33d01966 100644 --- a/drivers/net/txgbe/base/txgbe_hw.h +++ b/drivers/net/txgbe/base/txgbe_hw.h @@ -86,6 +86,7 @@ s32 txgbe_negotiate_fc(struct txgbe_hw *hw, u32 adv_reg, u32 lp_reg, u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm); s32 txgbe_init_shared_code(struct txgbe_hw *hw); bool txgbe_is_pf(struct txgbe_hw *hw); +bool txgbe_is_vf(struct txgbe_hw *hw); s32 txgbe_set_mac_type(struct txgbe_hw *hw); s32 txgbe_init_ops_generic(struct txgbe_hw *hw); void txgbe_init_ops_sp(struct txgbe_hw *hw); diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h index 5709245068..93cc222339 100644 --- a/drivers/net/txgbe/base/txgbe_regs.h +++ b/drivers/net/txgbe/base/txgbe_regs.h @@ -318,12 +318,18 @@ #define TXGBE_LEDCTL_1G MS(2, 0x1) #define TXGBE_LEDCTL_100M MS(3, 0x1) #define TXGBE_LEDCTL_ACTIVE MS(4, 0x1) +#define TXGBE_LINKUP_FILTER 0x014428 #define TXGBE_TAGTPID(i) (0x014430 + (i) * 4) /* 0-3 */ #define TXGBE_TAGTPID_LSB_MASK MS(0, 0xFFFF) #define TXGBE_TAGTPID_LSB(v) LS(v, 0, 0xFFFF) #define TXGBE_TAGTPID_MSB_MASK MS(16, 0xFFFF) #define TXGBE_TAGTPID_MSB(v) LS(v, 16, 0xFFFF) +/*AML LINK STATUS OVERWRITE*/ +#define TXGBE_AML_EPCS_MISC_CTL 0x13240 +#define TXGBE_AML_LINK_STATUS_OVRD_EN MS(5, 0x1) +#define TXGBE_AML_LINK_STATUS_OVRD_VAL MS(4, 0x1) + /** * GPIO Control * P0: link speed change @@ -1393,7 +1399,9 @@ enum txgbe_5tuple_protocol { #define TXGBE_TXCFG_HTHRESH_MASK MS(8, 0xF) #define TXGBE_TXCFG_HTHRESH(v) LS(v, 8, 0xF) #define TXGBE_TXCFG_WTHRESH_MASK MS(16, 0x7F) +#define TXGBE_TXCFG_WTHRESH_MASK_AML MS(16, 0x1FF) #define TXGBE_TXCFG_WTHRESH(v) LS(v, 16, 0x7F) +#define TXGBE_TXCFG_WTHRESH_AML(v) LS(v, 16, 0x1FF) #define TXGBE_TXCFG_FLUSH MS(26, 0x1) #define TXGBE_TDM_DESC_CHK(i) (0x0180B0 + (i) * 4) /*0-3*/ @@ -1638,6 +1646,16 @@ enum txgbe_5tuple_protocol { #define TXGBE_ARBRXCTL_WSP MS(2, 0x1) #define TXGBE_ARBRXCTL_DIA MS(6, 0x1) +#define TXGBE_RDM_VF_RE(_i) (0x12004 + ((_i) * 4)) +#define TXGBE_RDM_VFRE_CLR(_i) (0x120A0 + ((_i) * 4)) +#define TXGBE_RDM_RSC_CTL 0x1200C +/* amlite: rdm_rsc_ctl_free_ctl */ +#define TXGBE_RDM_RSC_CTL_FREE_CTL MS(7, 0x1) +#define TXGBE_RDM_RSC_CTL_FREE_CNT_DIS MS(8, 0x1) +#define TXGBE_RDM_ARB_CFG(_i) (0x12040 + ((_i) * 4)) /* 8 of these (0-7) */ +#define TXGBE_RDM_PF_QDE(_i) (0x12080 + ((_i) * 4)) +#define TXGBE_RDM_PF_HIDE(_i) (0x12090 + ((_i) * 4)) + #define TXGBE_RPUP2TC 0x019008 #define TXGBE_RPUP2TC_UP_SHIFT 3 #define TXGBE_RPUP2TC_UP_MASK 0x7 @@ -1712,6 +1730,19 @@ enum txgbe_5tuple_protocol { #define TXGBE_MACTXCFG_SPEED_10G LS(0, 29, 0x3) #define TXGBE_MACTXCFG_SPEED_1G LS(3, 29, 0x3) +#define TXGBE_MAC_TX_CFG_AML_SPEED_MASK MS(28, 0x7) +#define TXGBE_MAC_TX_CFG_AML_SPEED_50G LS(2, 28, 0x7) +#define TXGBE_MAC_TX_CFG_AML_SPEED_40G LS(0, 28, 0x7) +#define TXGBE_MAC_TX_CFG_AML_SPEED_25G LS(1, 28, 0x7) +#define TXGBE_MAC_TX_CFG_AML_SPEED_10G LS(4, 28, 0x7) +#define TXGBE_MAC_TX_CFG_AML_SPEED_1G LS(7, 28, 0x7) + +#define TXGBE_MAC_MISC_CTL 0x11f00 +#define TXGBE_MAC_MISC_LINK_STS_MOD MS(0, 0x1) +#define TXGBE_LINK_BOTH_PCS_MAC MS(0, 0x1) + +#define TXGBE_EPHY_STAT 0x13404 +#define TXGBE_EPHY_STAT_PPL_LOCK 0x3 #define TXGBE_ISBADDRL 0x000160 #define TXGBE_ISBADDRH 0x000164 diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c index 0e2f25ad76..30c11b8743 100644 --- a/drivers/net/txgbe/txgbe_ethdev.c +++ b/drivers/net/txgbe/txgbe_ethdev.c @@ -385,7 +385,7 @@ txgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, uint32_t q_map; uint8_t n, offset; - if (hw->mac.type != txgbe_mac_sp) + if (!txgbe_is_pf(hw)) return -ENOSYS; if (stat_idx & ~QMAP_FIELD_RESERVED_BITS_MASK) @@ -1806,7 +1806,7 @@ txgbe_dev_start(struct rte_eth_dev *dev) } /* Skip link setup if loopback mode is enabled. */ - if (hw->mac.type == txgbe_mac_sp && + if (txgbe_is_pf(hw) && dev->data->dev_conf.lpbk_mode) goto skip_link_setup; @@ -2817,6 +2817,7 @@ txgbe_dev_sfp_event(struct rte_eth_dev *dev) wr32(hw, TXGBE_GPIOINTMASK, 0xFF); reg = rd32(hw, TXGBE_GPIORAWINTSTAT); + if (reg & TXGBE_GPIOBIT_0) wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_0); if (reg & TXGBE_GPIOBIT_2) { @@ -3079,8 +3080,13 @@ txgbe_dev_link_update_share(struct rte_eth_dev *dev, break; } + /* enable mac receiver */ + if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) { + wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, TXGBE_MACRXCFG_ENA); + } + /* Re configure MAC RX */ - if (hw->mac.type == txgbe_mac_sp) { + if (txgbe_is_pf(hw)) { reg = rd32(hw, TXGBE_MACRXCFG); wr32(hw, TXGBE_MACRXCFG, reg); wr32m(hw, TXGBE_MACRXFLT, TXGBE_MACRXFLT_PROMISC, diff --git a/drivers/net/txgbe/txgbe_rxtx.c b/drivers/net/txgbe/txgbe_rxtx.c index 5c05dfd90a..3f157527c6 100644 --- a/drivers/net/txgbe/txgbe_rxtx.c +++ b/drivers/net/txgbe/txgbe_rxtx.c @@ -74,19 +74,6 @@ static const u64 TXGBE_TX_OFFLOAD_MASK = (RTE_MBUF_F_TX_IP_CKSUM | */ #define rte_txgbe_prefetch(p) rte_prefetch0(p) -static int -txgbe_is_vf(struct rte_eth_dev *dev) -{ - struct txgbe_hw *hw = TXGBE_DEV_HW(dev); - - switch (hw->mac.type) { - case txgbe_mac_sp_vf: - return 1; - default: - return 0; - } -} - /********************************************************************* * * TX functions @@ -2112,7 +2099,7 @@ txgbe_get_rx_port_offloads(struct rte_eth_dev *dev) RTE_ETH_RX_OFFLOAD_RSS_HASH | RTE_ETH_RX_OFFLOAD_SCATTER; - if (!txgbe_is_vf(dev)) + if (!txgbe_is_vf(hw)) offloads |= (RTE_ETH_RX_OFFLOAD_VLAN_FILTER | RTE_ETH_RX_OFFLOAD_QINQ_STRIP | RTE_ETH_RX_OFFLOAD_VLAN_EXTEND); @@ -2121,10 +2108,10 @@ txgbe_get_rx_port_offloads(struct rte_eth_dev *dev) * RSC is only supported by PF devices in a non-SR-IOV * mode. */ - if (hw->mac.type == txgbe_mac_sp && !sriov->active) + if (txgbe_is_pf(hw) && !sriov->active) offloads |= RTE_ETH_RX_OFFLOAD_TCP_LRO; - if (hw->mac.type == txgbe_mac_sp) + if (txgbe_is_pf(hw)) offloads |= RTE_ETH_RX_OFFLOAD_MACSEC_STRIP; offloads |= RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM; @@ -2363,6 +2350,7 @@ uint64_t txgbe_get_tx_port_offloads(struct rte_eth_dev *dev) { uint64_t tx_offload_capa; + struct txgbe_hw *hw = TXGBE_DEV_HW(dev); tx_offload_capa = RTE_ETH_TX_OFFLOAD_VLAN_INSERT | @@ -2380,7 +2368,7 @@ txgbe_get_tx_port_offloads(struct rte_eth_dev *dev) RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO | RTE_ETH_TX_OFFLOAD_MULTI_SEGS; - if (!txgbe_is_vf(dev)) + if (!txgbe_is_vf(hw)) tx_offload_capa |= RTE_ETH_TX_OFFLOAD_QINQ_INSERT; tx_offload_capa |= RTE_ETH_TX_OFFLOAD_MACSEC_INSERT; @@ -2498,7 +2486,7 @@ txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, /* Modification to set tail pointer for virtual function * if vf is detected. */ - if (hw->mac.type == txgbe_mac_sp_vf) { + if (txgbe_is_vf(hw)) { txq->tdt_reg_addr = TXGBE_REG_ADDR(hw, TXGBE_TXWP(queue_idx)); txq->tdc_reg_addr = TXGBE_REG_ADDR(hw, TXGBE_TXCFG(queue_idx)); } else { @@ -2791,7 +2779,7 @@ txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, /* * Modified to setup VFRDT for Virtual Function */ - if (hw->mac.type == txgbe_mac_sp_vf) { + if (txgbe_is_vf(hw)) { rxq->rdt_reg_addr = TXGBE_REG_ADDR(hw, TXGBE_RXWP(queue_idx)); rxq->rdh_reg_addr = @@ -3037,7 +3025,7 @@ txgbe_rss_disable(struct rte_eth_dev *dev) struct txgbe_hw *hw; hw = TXGBE_DEV_HW(dev); - if (hw->mac.type == txgbe_mac_sp_vf) + if (txgbe_is_vf(hw)) wr32m(hw, TXGBE_VFPLCFG, TXGBE_VFPLCFG_RSSENA, 0); else wr32m(hw, TXGBE_RACTL, TXGBE_RACTL_RSSENA, 0); @@ -3074,7 +3062,7 @@ txgbe_dev_rss_hash_update(struct rte_eth_dev *dev, /* Set configured hashing protocols */ rss_hf = rss_conf->rss_hf & TXGBE_RSS_OFFLOAD_ALL; - if (hw->mac.type == txgbe_mac_sp_vf) { + if (txgbe_is_vf(hw)) { mrqc = rd32(hw, TXGBE_VFPLCFG); mrqc &= ~TXGBE_VFPLCFG_RSSMASK; if (rss_hf & RTE_ETH_RSS_IPV4) @@ -3166,7 +3154,7 @@ txgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, } rss_hf = 0; - if (hw->mac.type == txgbe_mac_sp_vf) { + if (txgbe_is_vf(hw)) { mrqc = rd32(hw, TXGBE_VFPLCFG); if (mrqc & TXGBE_VFPLCFG_RSSIPV4) rss_hf |= RTE_ETH_RSS_IPV4; @@ -3628,6 +3616,8 @@ txgbe_dcb_hw_arbite_tx_config(struct txgbe_hw *hw, uint16_t *refill, { switch (hw->mac.type) { case txgbe_mac_sp: + case txgbe_mac_aml: + case txgbe_mac_aml40: txgbe_dcb_config_tx_desc_arbiter_raptor(hw, refill, max, bwg_id, tsa); txgbe_dcb_config_tx_data_arbiter_raptor(hw, refill, @@ -4555,7 +4545,7 @@ txgbe_dev_rx_init(struct rte_eth_dev *dev) * If loopback mode is configured, set LPBK bit. */ hlreg0 = rd32(hw, TXGBE_PSRCTL); - if (hw->mac.type == txgbe_mac_sp && + if (txgbe_is_pf(hw) && dev->data->dev_conf.lpbk_mode) hlreg0 |= TXGBE_PSRCTL_LBENA; else @@ -4640,7 +4630,7 @@ txgbe_dev_rx_init(struct rte_eth_dev *dev) wr32(hw, TXGBE_PSRCTL, rxcsum); - if (hw->mac.type == txgbe_mac_sp) { + if (txgbe_is_pf(hw)) { rdrxctl = rd32(hw, TXGBE_SECRXCTL); if (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC) rdrxctl &= ~TXGBE_SECRXCTL_CRCSTRIP; @@ -4730,11 +4720,18 @@ txgbe_dev_rxtx_start(struct rte_eth_dev *dev) for (i = 0; i < dev->data->nb_tx_queues; i++) { txq = dev->data->tx_queues[i]; /* Setup Transmit Threshold Registers */ - wr32m(hw, TXGBE_TXCFG(txq->reg_idx), - TXGBE_TXCFG_HTHRESH_MASK | - TXGBE_TXCFG_WTHRESH_MASK, - TXGBE_TXCFG_HTHRESH(txq->hthresh) | - TXGBE_TXCFG_WTHRESH(txq->wthresh)); + if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) + wr32m(hw, TXGBE_TXCFG(txq->reg_idx), + TXGBE_TXCFG_HTHRESH_MASK | + TXGBE_TXCFG_WTHRESH_MASK_AML, + TXGBE_TXCFG_HTHRESH(txq->hthresh) | + TXGBE_TXCFG_WTHRESH_AML(txq->wthresh)); + else + wr32m(hw, TXGBE_TXCFG(txq->reg_idx), + TXGBE_TXCFG_HTHRESH_MASK | + TXGBE_TXCFG_WTHRESH_MASK, + TXGBE_TXCFG_HTHRESH(txq->hthresh) | + TXGBE_TXCFG_WTHRESH(txq->wthresh)); } dmatxctl = rd32(hw, TXGBE_DMATXCTRL); @@ -4759,13 +4756,20 @@ txgbe_dev_rxtx_start(struct rte_eth_dev *dev) } } + /* enable mac transmitter */ + if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) { + wr32(hw, TXGBE_SECTXCTL, 0); + wr32m(hw, TXGBE_MACTXCFG, + TXGBE_MACTXCFG_TXE, TXGBE_MACTXCFG_TXE); + } + /* Enable Receive engine */ rxctrl = rd32(hw, TXGBE_PBRXCTL); rxctrl |= TXGBE_PBRXCTL_ENA; hw->mac.enable_rx_dma(hw, rxctrl); /* If loopback mode is enabled, set up the link accordingly */ - if (hw->mac.type == txgbe_mac_sp && + if (txgbe_is_pf(hw) && dev->data->dev_conf.lpbk_mode) txgbe_setup_loopback_link_raptor(hw); From patchwork Tue Sep 30 09:59:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zaiyu Wang X-Patchwork-Id: 157121 X-Patchwork-Delegate: stephen@networkplumber.org Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B90144886F; Tue, 30 Sep 2025 12:01:16 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id ECB5140DD3; Tue, 30 Sep 2025 12:00:44 +0200 (CEST) Received: from smtpbg154.qq.com (smtpbg154.qq.com [15.184.224.54]) by mails.dpdk.org (Postfix) with ESMTP id 403CA40DD3 for ; Tue, 30 Sep 2025 12:00:41 +0200 (CEST) X-QQ-mid: esmtpgz13t1759226437t1a969970 X-QQ-Originating-IP: 0j2NDZLTRfII6q+OmScSFVSPgbLSbwUHviBbWCTF8jc= Received: from DSK-zaiyuwang.trustnetic.com ( [115.220.225.164]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 30 Sep 2025 18:00:36 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 6084070779899740307 EX-QQ-RecipientCnt: 4 From: Zaiyu Wang To: dev@dpdk.org Cc: Zaiyu Wang , Jiawen Wu , Jian Wang Subject: [PATCH v4 08/20] net/txgbe: add hardware reset change for Amber-Lite NICs Date: Tue, 30 Sep 2025 17:59:40 +0800 Message-Id: <20250930095953.18508-9-zaiyuwang@trustnetic.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20250930095953.18508-1-zaiyuwang@trustnetic.com> References: <20250418094131.24136-1-zaiyuwang@trustnetic.com> <20250930095953.18508-1-zaiyuwang@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:trustnetic.com:qybglogicsvrgz:qybglogicsvrgz5a-1 X-QQ-XMAILINFO: NAEPl/HULyKMXKW4cX3KWwsnY4MFGYa83pdzVXl3G9uWE16pPsmpTuT7 3DL8YBj7NG26ADGByy0o68qPXhJiiljl9Gn/MIajq5fJUlmUo6KGLf/u8UIU6GE1va/mAfS RukruLfiaKZsBFyMOC+/ae/qXGto5PPysoIzoBaAtSMrJJceg4LpSBInSOrhHci0Nl6nJi4 QXPcOW0flkYRzOqQ5AUmwRzQMJ07ikvQDtQOg5KYL/2bz6LvNxi7tNNfWiLX3DurOAhLm9X eg81YFpnL+aUevtaMpR0U035xNqqb/bF0JcNYgST1oCM7IN/2pYHe2BXYh679zKn3KpvdGC Zy5XPxvHq1fS/TgsxFg9kKmmUxgcD6y0/lPSbDI6Qug7OOB3zBC7fkdjIwAHjFZERyd7H8i RGMyHGvY1Yjuvz1GBVtYiLriJydIVMsOgd4dwe2ayTgRqS9CbxxA9MYrsI9MYhJkppsh/WD S3olLwCJtnFGUmIGHuRi/42bblKuZNX601ZpZn7apIwIwgHWnbyv+arzhKoD1jbacUm+J5X /rPtrKt/Zynei/DgurNC9sikNmA7K6WC9rZb4zNyDZ5NJU1KQli36Dm/q1jStO21ySCGWQU 13EJvZeB1kVKA5B8pNUdzSMxVOcO8rI/aGRVCWqt6Bt9gNGzx0htlfQmJpR5bGa2tJwbhWx qV7VyaBHSf8LN6hIqZZWKWYQT5eX/k/KrxtlIhqay59XKJMfc9jutUb0H+GiCYbu04KOWxr jhcCcz7R7UHbZ+7cxymYQKjlf9PSrcU3umVF1EG3AqcxiZNVQiQHrw8PcQ3Fj0GS2+ZaaAw 079Vg+cnCAC4RNDBbo8B7PrLJ0BdRQZ4s6nP1c2kQa5fJzkIGt5oXlC3yek+ks9xXuVCaZw mFzHnecMsZGJgrlV+0oGozHTJg/hDSFOA612AN0AMv4CRqzrY2bsQ1hpCGnXnwY/2kPK51+ dmFUFYSvbjufz64M1Sc5nSSEVSG44nYyNhJWIgCP/QPzXKNhny0TnjbQitBek61VvqBZ4wV 9SsE5r4kwmSfrmDxiAUXjqQO3o6uv8T4Siu15jqKje27IwOGGsv6LCceuEPhFOwzAGByNk8 wP28IvMpMQZYzwN2s+MJIIVzGaekZeRWA== X-QQ-XMRINFO: MSVp+SPm3vtS1Vd6Y4Mggwc= X-QQ-RECHKSPAM: 0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add necessary configurations for Amber-Lite's hardware reset process, which differs from the 10G NIC's. These configurations may be modified in future to accommodate further changes. Signed-off-by: Zaiyu Wang --- drivers/net/txgbe/base/txgbe_hw.c | 64 +++++++++++++++++++++++------ drivers/net/txgbe/base/txgbe_regs.h | 2 + 2 files changed, 53 insertions(+), 13 deletions(-) diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c index be8409c28e..1fcc2feb98 100644 --- a/drivers/net/txgbe/base/txgbe_hw.c +++ b/drivers/net/txgbe/base/txgbe_hw.c @@ -276,6 +276,8 @@ s32 txgbe_start_hw(struct txgbe_hw *hw) /* Cache bit indicating need for crosstalk fix */ switch (hw->mac.type) { case txgbe_mac_sp: + case txgbe_mac_aml: + case txgbe_mac_aml40: hw->mac.get_device_caps(hw, &device_caps); if (device_caps & TXGBE_DEVICE_CAPS_NO_CROSSTALK_WR) hw->need_crosstalk_fix = false; @@ -3507,13 +3509,37 @@ txgbe_reset_misc(struct txgbe_hw *hw) { int i; u32 value; + int err = 0; + u32 speed; wr32(hw, TXGBE_ISBADDRL, hw->isb_dma & 0x00000000FFFFFFFF); wr32(hw, TXGBE_ISBADDRH, hw->isb_dma >> 32); - value = rd32_epcs(hw, SR_XS_PCS_CTRL2); - if ((value & 0x3) != SR_PCS_CTRL2_TYPE_SEL_X) - hw->link_status = TXGBE_LINK_STATUS_NONE; + if (hw->mac.type == txgbe_mac_aml) { + if ((rd32(hw, TXGBE_EPHY_STAT) & TXGBE_EPHY_STAT_PPL_LOCK) + != TXGBE_EPHY_STAT_PPL_LOCK) { + speed = TXGBE_LINK_SPEED_25GB_FULL + | TXGBE_LINK_SPEED_10GB_FULL; + err = hw->mac.setup_link(hw, speed, false); + if (err) { + DEBUGOUT("setup phy failed"); + return; + } + } + } else if (hw->mac.type == txgbe_mac_aml40) { + if (!(rd32(hw, TXGBE_EPHY_STAT) & TXGBE_EPHY_STAT_PPL_LOCK)) { + speed = TXGBE_LINK_SPEED_40GB_FULL; + err = hw->mac.setup_link(hw, speed, false); + if (err) { + DEBUGOUT("setup phy failed"); + return; + } + } + } else { + value = rd32_epcs(hw, SR_XS_PCS_CTRL2); + if ((value & 0x3) != SR_PCS_CTRL2_TYPE_SEL_X) + hw->link_status = TXGBE_LINK_STATUS_NONE; + } /* receive packets that size > 2048 */ wr32m(hw, TXGBE_MACRXCFG, @@ -3576,7 +3602,7 @@ txgbe_reset_misc(struct txgbe_hw *hw) s32 txgbe_reset_hw(struct txgbe_hw *hw) { s32 status; - u32 autoc; + u32 autoc = 0; /* Call adapter stop to disable tx/rx and clear interrupts */ status = hw->mac.stop_hw(hw); @@ -3638,16 +3664,28 @@ s32 txgbe_reset_hw(struct txgbe_hw *hw) goto mac_reset_top; } - /* - * Store the original AUTOC/AUTOC2 values if they have not been - * stored off yet. Otherwise restore the stored original - * values since the reset operation sets back to defaults. - */ - if (!hw->mac.orig_link_settings_stored) { - hw->mac.orig_autoc = hw->mac.autoc_read(hw); - hw->mac.orig_link_settings_stored = true; + /* amlite TODO*/ + if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) { + wr32(hw, TXGBE_LINKUP_FILTER, 30); + wr32m(hw, TXGBE_MAC_MISC_CTL, TXGBE_MAC_MISC_LINK_STS_MOD, + TXGBE_LINK_BOTH_PCS_MAC); + /* amlite: bme */ + wr32(hw, TXGBE_PX_PF_BME, TXGBE_PX_PF_BME_EN); + /* amlite: rdm_rsc_ctl_free_ctl set to 1 */ + wr32m(hw, TXGBE_RDM_RSC_CTL, TXGBE_RDM_RSC_CTL_FREE_CTL, + TXGBE_RDM_RSC_CTL_FREE_CTL); } else { - hw->mac.orig_autoc = autoc; + /* + * Store the original AUTOC/AUTOC2 values if they have not been + * stored off yet. Otherwise restore the stored original + * values since the reset operation sets back to defaults. + */ + if (!hw->mac.orig_link_settings_stored) { + hw->mac.orig_autoc = hw->mac.autoc_read(hw); + hw->mac.orig_link_settings_stored = true; + } else { + hw->mac.orig_autoc = autoc; + } } if (hw->phy.ffe_set) { diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h index 93cc222339..5b730bf749 100644 --- a/drivers/net/txgbe/base/txgbe_regs.h +++ b/drivers/net/txgbe/base/txgbe_regs.h @@ -1238,6 +1238,8 @@ enum txgbe_5tuple_protocol { TXGBE_ICRMISC_LNKUP) #define TXGBE_ICSMISC 0x000104 #define TXGBE_IENMISC 0x000108 +#define TXGBE_PX_PF_BME 0x0004B8 +#define TXGBE_PX_PF_BME_EN MS(0, 0x1) #define TXGBE_IVARMISC 0x0004FC #define TXGBE_IVARMISC_VEC(v) LS(v, 0, 0x7) #define TXGBE_IVARMISC_VLD MS(7, 0x1) From patchwork Tue Sep 30 09:59:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zaiyu Wang X-Patchwork-Id: 157122 X-Patchwork-Delegate: stephen@networkplumber.org Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DE8384886F; Tue, 30 Sep 2025 12:01:25 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 839F540DD8; Tue, 30 Sep 2025 12:00:48 +0200 (CEST) Received: from smtpbgbr2.qq.com (smtpbgbr2.qq.com [54.207.22.56]) by mails.dpdk.org (Postfix) with ESMTP id 6BD5D40E17 for ; Tue, 30 Sep 2025 12:00:45 +0200 (CEST) X-QQ-mid: esmtpgz13t1759226439t5384a980 X-QQ-Originating-IP: IVGRkMqNuIZSIW5tzi+Erw57e7OlnDpb/3JIDypuLFg= Received: from DSK-zaiyuwang.trustnetic.com ( [115.220.225.164]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 30 Sep 2025 18:00:38 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 11078994436134679667 EX-QQ-RecipientCnt: 4 From: Zaiyu Wang To: dev@dpdk.org Cc: Zaiyu Wang , Jiawen Wu , Jian Wang Subject: [PATCH v4 09/20] net/txgbe: add MAC reconfiguration to avoid packet loss Date: Tue, 30 Sep 2025 17:59:41 +0800 Message-Id: <20250930095953.18508-10-zaiyuwang@trustnetic.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20250930095953.18508-1-zaiyuwang@trustnetic.com> References: <20250418094131.24136-1-zaiyuwang@trustnetic.com> <20250930095953.18508-1-zaiyuwang@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:trustnetic.com:qybglogicsvrgz:qybglogicsvrgz5a-1 X-QQ-XMAILINFO: OeFOmPvKThpBdXqavVjzFL3ZB28qLHl+A08VJTxMfem/UtDuwkcr5eW8 MvLAAgABQSdXhAVU4vhH44UaWBXIxp+GUKRkXtwr5NiFOzEXDMyQdzA8xvkoJBZkzu4v5Hy CqcbItrDu2Ak01YzBblPxUSkHURZTxvJvzqIBHMfXE+8IOqnASpFdw02nr7Ygy3MNtrqxa2 RTSOnkm6KFknkn7eZRHb9iGrt8Rv7NjyFNdKHKTLnPR5E09JCaqjkz0lopXRkqfCyL4ysCY inNNiyuNPlhg4BHMRiecDqrTYuBTNJBPzNWlcETT/Wby1RrGZmngDxpF9Ms74oFXvgRuoPH ZV91xmUcRkpGSFIEM0LvHjNrf/pnpfdwP7UtJJXGYKgxUMcqdaP+0oJFE0ejefh9qnZohJv +FGwS2w8qCCwl47AE4yiH2WbdXU0yWAKrihmwpwIjxlIldMVLVLnr8HZGgx9Jmpj1hRffVt u+qPcbwoBCccOP0bYj2hqPDY3wO/Lein223k2bMhQxOZFdrtEZUZycZ3wLcxmCQ+zgY5FXO o4Up3qhHYC1wJ/THD2rRt1DPMKFps/PrvQxvjLiVolSarVE3NJ0qgQfAYpgUfeMscjVzlZj nCJqguAkx+RuStH4QL6D2Wuf5KUkMb+LQcEUTTORc775KuyIiRHY0pApDutoFA24cyGUWOG s1dSNZ1XC5iIlvhRyQhVeXwZjbwpZKIj69kN8kHg4zvwmp2Fa6Vd7KI7sRPPtjl58DOHf1O MCrHyWcWiIjP38miZXeJOqhTg/q/aeEkHUU5+eHl47hUz21o7vmql80B5aUX1bjCgAoS6i3 62eqx57zQ6Vp/uixtwAkgztpBxwt3GZ74ZBbWEW381KsouG0DQKopG3e32sm+dVkR1lQSz7 NOWmZ9s4xdB5oh5t+HDa9aZQ3hIGZHKwJhGPXD7u0Uh9LyrTjiB3Q4OldRMeh+nIp6LXz8R HyNRAzvVQ7IxUIEbon8mHlvh8YVkFe8hsSVIVWaYpRRnSjLQbasvchVWZTRVIGQLsqRRPl/ pu4+jrPtq/x0kQyj5/XL1s3SVT/pVPo/P9nyPhHvOUWx0V7YpnjWNgI2OmgQFuuQsye0k+B AZ9OA8K+cBf X-QQ-XMRINFO: MPJ6Tf5t3I/ycC2BItcBVIA= X-QQ-RECHKSPAM: 0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org There was a bug that RX will lose the first packet when down/up port. When PHY is configured, mac error code is reported to the MAC layer, and MAC locked this status without unlocking. As a result, when the first packet is reveived, MAC reports this error code and RDB dismissed this packet. Do MAC reset can clean MAC error code so we can fix this bug. Signed-off-by: Zaiyu Wang --- drivers/net/txgbe/base/txgbe_hw.c | 37 +++++++++++++++++++++++++++++ drivers/net/txgbe/base/txgbe_hw.h | 1 + drivers/net/txgbe/base/txgbe_regs.h | 2 ++ drivers/net/txgbe/txgbe_ethdev.c | 1 + 4 files changed, 41 insertions(+) diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c index 1fcc2feb98..6d3b917bbf 100644 --- a/drivers/net/txgbe/base/txgbe_hw.c +++ b/drivers/net/txgbe/base/txgbe_hw.c @@ -3504,6 +3504,43 @@ txgbe_check_flash_load(struct txgbe_hw *hw, u32 check_bit) return err; } +int txgbe_reconfig_mac(struct txgbe_hw *hw) +{ + u32 mac_wdg_timeout; + u32 mac_flow_ctrl; + + mac_wdg_timeout = rd32(hw, TXGBE_MAC_WDG_TIMEOUT); + mac_flow_ctrl = rd32(hw, TXGBE_RXFCCFG); + + if (hw->bus.lan_id == 0) + wr32(hw, TXGBE_RST, TXGBE_RST_MAC_LAN_0); + else if (hw->bus.lan_id == 1) + wr32(hw, TXGBE_RST, TXGBE_RST_MAC_LAN_1); + + /* wait for mac reset complete */ + usec_delay(1500); + wr32m(hw, TXGBE_MAC_MISC_CTL, TXGBE_MAC_MISC_LINK_STS_MOD, + TXGBE_LINK_BOTH_PCS_MAC); + + /* receive packets that size > 2048 */ + wr32m(hw, TXGBE_MACRXCFG, + TXGBE_MACRXCFG_JUMBO, TXGBE_MACRXCFG_JUMBO); + + /* clear counters on read */ + wr32m(hw, TXGBE_MACCNTCTL, + TXGBE_MACCNTCTL_RC, TXGBE_MACCNTCTL_RC); + + wr32m(hw, TXGBE_RXFCCFG, + TXGBE_RXFCCFG_FC, TXGBE_RXFCCFG_FC); + + wr32(hw, TXGBE_MACRXFLT, TXGBE_MACRXFLT_PROMISC); + + wr32(hw, TXGBE_MAC_WDG_TIMEOUT, mac_wdg_timeout); + wr32(hw, TXGBE_RXFCCFG, mac_flow_ctrl); + + return 0; +} + static void txgbe_reset_misc(struct txgbe_hw *hw) { diff --git a/drivers/net/txgbe/base/txgbe_hw.h b/drivers/net/txgbe/base/txgbe_hw.h index ab33d01966..bc34d639eb 100644 --- a/drivers/net/txgbe/base/txgbe_hw.h +++ b/drivers/net/txgbe/base/txgbe_hw.h @@ -107,6 +107,7 @@ s32 txgbe_setup_mac_link(struct txgbe_hw *hw, u32 speed, bool autoneg_wait_to_complete); s32 txgbe_setup_sfp_modules(struct txgbe_hw *hw); void txgbe_init_mac_link_ops_sp(struct txgbe_hw *hw); +int txgbe_reconfig_mac(struct txgbe_hw *hw); s32 txgbe_reset_hw(struct txgbe_hw *hw); s32 txgbe_start_hw_raptor(struct txgbe_hw *hw); s32 txgbe_init_phy_raptor(struct txgbe_hw *hw); diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h index 5b730bf749..23d39857de 100644 --- a/drivers/net/txgbe/base/txgbe_regs.h +++ b/drivers/net/txgbe/base/txgbe_regs.h @@ -158,6 +158,8 @@ #define TXGBE_RST_SW MS(0, 0x1) #define TXGBE_RST_LAN(i) MS(((i) + 1), 0x1) #define TXGBE_RST_FW MS(3, 0x1) +#define TXGBE_RST_MAC_LAN_1 MS(17, 0x1) +#define TXGBE_RST_MAC_LAN_0 MS(20, 0x1) #define TXGBE_RST_ETH(i) MS(((i) + 29), 0x1) #define TXGBE_RST_GLB MS(31, 0x1) #define TXGBE_RST_DEFAULT (TXGBE_RST_SW | \ diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c index 30c11b8743..10e088ee95 100644 --- a/drivers/net/txgbe/txgbe_ethdev.c +++ b/drivers/net/txgbe/txgbe_ethdev.c @@ -3082,6 +3082,7 @@ txgbe_dev_link_update_share(struct rte_eth_dev *dev, /* enable mac receiver */ if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) { + txgbe_reconfig_mac(hw); wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, TXGBE_MACRXCFG_ENA); } From patchwork Tue Sep 30 09:59:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zaiyu Wang X-Patchwork-Id: 157123 X-Patchwork-Delegate: stephen@networkplumber.org Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DA8DE4886F; Tue, 30 Sep 2025 12:01:32 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A354D40E1E; Tue, 30 Sep 2025 12:00:49 +0200 (CEST) Received: from smtpbgau2.qq.com (smtpbgau2.qq.com [54.206.34.216]) by mails.dpdk.org (Postfix) with ESMTP id DA48840A79 for ; Tue, 30 Sep 2025 12:00:47 +0200 (CEST) X-QQ-mid: esmtpgz13t1759226442t4091c2b7 X-QQ-Originating-IP: ywn53P/0Fk2zJ0KOSu2ARDFluyv50oV0h+6/T5A9Lqg= Received: from DSK-zaiyuwang.trustnetic.com ( [115.220.225.164]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 30 Sep 2025 18:00:41 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 16171448251923589421 EX-QQ-RecipientCnt: 4 From: Zaiyu Wang To: dev@dpdk.org Cc: Zaiyu Wang , Jiawen Wu , Jian Wang Subject: [PATCH v4 10/20] net/txgbe: add TX head Write-Back mode for Amber-Lite NICs Date: Tue, 30 Sep 2025 17:59:42 +0800 Message-Id: <20250930095953.18508-11-zaiyuwang@trustnetic.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20250930095953.18508-1-zaiyuwang@trustnetic.com> References: <20250418094131.24136-1-zaiyuwang@trustnetic.com> <20250930095953.18508-1-zaiyuwang@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:trustnetic.com:qybglogicsvrgz:qybglogicsvrgz5a-1 X-QQ-XMAILINFO: NoaupJ8ahyDyD9tuI22GVQdIJNylObIWsoyzRMRJf7kHOu/F0Nc1UbTW F3qPxjvDBamHG0ua0ll01N3Y9Q7K2FzRRJrQtc47LNLtMrPRpqi3AjTYKnfvw0SaaQK834m ixzjaB1ljt8vaqjqkn3ULDaeqQb+VbkKetIa5k0rbNC7oO1v2oAM5N0cmLLMCCIgKtd53pI vXTiV6HRgltMfNQxwnm1lTfnOU0rD3SsmTZUROVR5uII8VBmnauxkldq4w5SP5x56J2kTTu bbRm6mmxn+yJpZ9fdT54jLI9oAa4rpw2/FjsbbMLPjVnx0dI9d1Ad0zMe1Bn0fwKdbaA624 ug/Z1qYV5OHh2RN3Mel3OdLOTNZNKldf7TDEEEEJ1o8f29Q9KEX1ilXv+Sb1cIlkfK6w69f 1wvTYtJCtYsscT4uYRW6hLVC/Oq51WKq4GaBX9JmL7GUjN+N1IGsnnKxL7ovaL0v1ucemUu KhT9ltdP4YSeDbqszUuMHlFaQBTcAV+hm71m0cpn1THyt7qmqFBNLbBaXNCwaaZRzR/0rtw NaG9ryuzrOD2C4rMd8ErQmCb3CZidMUd1j9CA4rQ4rjiukMALrOf7Xkb2K++q+dViTEgXRz yzzlKvB/lykQOlQNrRdTnYF7HGhz7EObbUDuJYA81lnHHFTp59hPybGQpDYCICf73FAFBbs Js0VNE5x4EbofRft/d+P4ZpfVs2pBoMKsaOdCS3FD74AReRitJrhLVdU6MFeo42ek5z699N 8b0ZJWwTahd7I1PaoreiMNnZz1J8ecPEeZOga6ZDxryxEnWAg0VTx9poM5h9PeDDFROqC50 dJiSX5PYptmAfTXRf/St7FLIRSQY/dSXpWsAzKUoKEaAiCLO4R4bgSsz6tujo1rfZ0ruKmV qxkJ/s+g6/sUgxjzO3A6vs8s2VQWOdqaud9jUhQrbw4BGjyMsaUBP05WpGRl0wuPAyctoT4 oMpJYA8WYrIItLU+pR5PlmdgL0hoZhf8d2CJnkABir7askmRaP7wIRQ27Q8rtPZcbIXzSch Jyl7RSdHK5+f07f69WFOh8ZGqhexn8GCqUhbUbZiHTeYntjXtcamWfR8cxJFK2bftwDJWk+ q23W19nZs4q X-QQ-XMRINFO: NyFYKkN4Ny6FSmKK/uo/jdU= X-QQ-RECHKSPAM: 0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add TX head Write-Back mode for Amber-Lite NICs. When enabled, the hardware no longer individually rewrites descriptors but intermittently notifies the driver of processed descriptor indices. This feature significantly improves performance and is enabled by default in the driver. Users can configure it via tx_headwb and tx_headwb_size in devargs. Signed-off-by: Zaiyu Wang --- drivers/net/txgbe/base/txgbe_regs.h | 7 ++ drivers/net/txgbe/base/txgbe_type.h | 6 ++ drivers/net/txgbe/txgbe_ethdev.c | 13 ++- drivers/net/txgbe/txgbe_rxtx.c | 124 ++++++++++++++++++---- drivers/net/txgbe/txgbe_rxtx.h | 3 + drivers/net/txgbe/txgbe_rxtx_vec_common.h | 27 +++-- 6 files changed, 153 insertions(+), 27 deletions(-) diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h index 23d39857de..1a544bcd57 100644 --- a/drivers/net/txgbe/base/txgbe_regs.h +++ b/drivers/net/txgbe/base/txgbe_regs.h @@ -1407,6 +1407,13 @@ enum txgbe_5tuple_protocol { #define TXGBE_TXCFG_WTHRESH(v) LS(v, 16, 0x7F) #define TXGBE_TXCFG_WTHRESH_AML(v) LS(v, 16, 0x1FF) #define TXGBE_TXCFG_FLUSH MS(26, 0x1) +#define TXGBE_PX_TR_CFG_HEAD_WB MS(27, 0x1) /* amlite head wb */ +#define TXGBE_PX_TR_CFG_HEAD_WB_64BYTE MS(28, 0x1) /* amlite head wb 64byte */ +#define TXGBE_PX_TR_CFG_HEAD_WB_MASK MS(27, 0x3) + +/* amlite: tx head wb */ +#define TXGBE_PX_TR_HEAD_ADDRL(_i) (0x03028 + ((_i) * 0x40)) +#define TXGBE_PX_TR_HEAD_ADDRH(_i) (0x0302C + ((_i) * 0x40)) #define TXGBE_TDM_DESC_CHK(i) (0x0180B0 + (i) * 4) /*0-3*/ #define TXGBE_TDM_DESC_NONFATAL(i) (0x0180C0 + (i) * 4) /*0-3*/ diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h index 55123d0b6c..844a2827bc 100644 --- a/drivers/net/txgbe/base/txgbe_type.h +++ b/drivers/net/txgbe/base/txgbe_type.h @@ -716,6 +716,8 @@ struct txgbe_phy_info { #define TXGBE_DEVARG_FFE_MAIN "ffe_main" #define TXGBE_DEVARG_FFE_PRE "ffe_pre" #define TXGBE_DEVARG_FFE_POST "ffe_post" +#define TXGBE_DEVARG_TX_HEAD_WB "tx_headwb" +#define TXGBE_DEVARG_TX_HEAD_WB_SIZE "tx_headwb_size" static const char * const txgbe_valid_arguments[] = { TXGBE_DEVARG_BP_AUTO, @@ -726,6 +728,8 @@ static const char * const txgbe_valid_arguments[] = { TXGBE_DEVARG_FFE_MAIN, TXGBE_DEVARG_FFE_PRE, TXGBE_DEVARG_FFE_POST, + TXGBE_DEVARG_TX_HEAD_WB, + TXGBE_DEVARG_TX_HEAD_WB_SIZE, NULL }; @@ -776,6 +780,8 @@ struct txgbe_devargs { u16 poll; u16 present; u16 sgmii; + u16 tx_headwb; + u16 tx_headwb_size; }; struct txgbe_hw { diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c index 10e088ee95..9c14e4b8ed 100644 --- a/drivers/net/txgbe/txgbe_ethdev.c +++ b/drivers/net/txgbe/txgbe_ethdev.c @@ -513,6 +513,9 @@ txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs) u16 ffe_main = 27; u16 ffe_pre = 8; u16 ffe_post = 44; + /* New devargs for amberlite config */ + u16 tx_headwb = 1; + u16 tx_headwb_size = 16; if (devargs == NULL) goto null; @@ -537,6 +540,10 @@ txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs) &txgbe_handle_devarg, &ffe_pre); rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_POST, &txgbe_handle_devarg, &ffe_post); + rte_kvargs_process(kvlist, TXGBE_DEVARG_TX_HEAD_WB, + &txgbe_handle_devarg, &tx_headwb); + rte_kvargs_process(kvlist, TXGBE_DEVARG_TX_HEAD_WB_SIZE, + &txgbe_handle_devarg, &tx_headwb_size); rte_kvargs_free(kvlist); null: @@ -544,6 +551,8 @@ txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs) hw->devarg.poll = poll; hw->devarg.present = present; hw->devarg.sgmii = sgmii; + hw->devarg.tx_headwb = tx_headwb; + hw->devarg.tx_headwb_size = tx_headwb_size; hw->phy.ffe_set = ffe_set; hw->phy.ffe_main = ffe_main; hw->phy.ffe_pre = ffe_pre; @@ -5718,7 +5727,9 @@ RTE_PMD_REGISTER_PARAM_STRING(net_txgbe, TXGBE_DEVARG_FFE_SET "=<0-4>" TXGBE_DEVARG_FFE_MAIN "=" TXGBE_DEVARG_FFE_PRE "=" - TXGBE_DEVARG_FFE_POST "="); + TXGBE_DEVARG_FFE_POST "=" + TXGBE_DEVARG_TX_HEAD_WB "=<0|1>" + TXGBE_DEVARG_TX_HEAD_WB_SIZE "=<1|16>"); RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_init, init, NOTICE); RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_driver, driver, NOTICE); diff --git a/drivers/net/txgbe/txgbe_rxtx.c b/drivers/net/txgbe/txgbe_rxtx.c index 3f157527c6..b15b6788e6 100644 --- a/drivers/net/txgbe/txgbe_rxtx.c +++ b/drivers/net/txgbe/txgbe_rxtx.c @@ -92,14 +92,29 @@ txgbe_tx_free_bufs(struct txgbe_tx_queue *txq) int i, nb_free = 0; struct rte_mbuf *m, *free[RTE_TXGBE_TX_MAX_FREE_BUF_SZ]; - /* check DD bit on threshold descriptor */ - status = txq->tx_ring[txq->tx_next_dd].dw3; - if (!(status & rte_cpu_to_le_32(TXGBE_TXD_DD))) { - if (txq->nb_tx_free >> 1 < txq->tx_free_thresh) - txgbe_set32_masked(txq->tdc_reg_addr, - TXGBE_TXCFG_FLUSH, TXGBE_TXCFG_FLUSH); - return 0; + if (txq->headwb_mem) { + uint16_t tx_last_dd = txq->nb_tx_desc + + txq->tx_next_dd - txq->tx_free_thresh; + if (tx_last_dd >= txq->nb_tx_desc) + tx_last_dd -= txq->nb_tx_desc; + + volatile uint16_t head = (uint16_t)*txq->headwb_mem; + + if (txq->tx_next_dd > head && head > tx_last_dd) + return 0; + else if (tx_last_dd > txq->tx_next_dd && + (head > tx_last_dd || head < txq->tx_next_dd)) + return 0; + } else { + /* check DD bit on threshold descriptor */ + status = txq->tx_ring[txq->tx_next_dd].dw3; + if (!(status & rte_cpu_to_le_32(TXGBE_TXD_DD))) { + if (txq->nb_tx_free >> 1 < txq->tx_free_thresh) + txgbe_set32_masked(txq->tdc_reg_addr, + TXGBE_TXCFG_FLUSH, TXGBE_TXCFG_FLUSH); + return 0; } +} /* * first buffer to free from S/W ring is at index @@ -628,17 +643,28 @@ txgbe_xmit_cleanup(struct txgbe_tx_queue *txq) /* Check to make sure the last descriptor to clean is done */ desc_to_clean_to = sw_ring[desc_to_clean_to].last_id; status = txr[desc_to_clean_to].dw3; - if (!(status & rte_cpu_to_le_32(TXGBE_TXD_DD))) { - PMD_TX_FREE_LOG(DEBUG, - "TX descriptor %4u is not done" - "(port=%d queue=%d)", - desc_to_clean_to, - txq->port_id, txq->queue_id); - if (txq->nb_tx_free >> 1 < txq->tx_free_thresh) - txgbe_set32_masked(txq->tdc_reg_addr, - TXGBE_TXCFG_FLUSH, TXGBE_TXCFG_FLUSH); - /* Failed to clean any descriptors, better luck next time */ - return -(1); + + if (txq->headwb_mem) { + u32 head = *txq->headwb_mem; + + PMD_TX_FREE_LOG(DEBUG, "queue[%02d]: headwb_mem = %03d, desc_to_clean_to = %03d", + txq->reg_idx, head, desc_to_clean_to); + /* we have caught up to head, no work left to do */ + if (desc_to_clean_to == head) + return -(1); + } else { + if (!(status & rte_cpu_to_le_32(TXGBE_TXD_DD))) { + PMD_TX_FREE_LOG(DEBUG, + "TX descriptor %4u is not done" + "(port=%d queue=%d)", + desc_to_clean_to, + txq->port_id, txq->queue_id); + if (txq->nb_tx_free >> 1 < txq->tx_free_thresh) + txgbe_set32_masked(txq->tdc_reg_addr, + TXGBE_TXCFG_FLUSH, TXGBE_TXCFG_FLUSH); + /* Failed to clean any descriptors, better luck next time */ + return -(1); + } } /* Figure out how many descriptors will be cleaned */ @@ -2246,6 +2272,8 @@ txgbe_tx_queue_release(struct txgbe_tx_queue *txq) txq->ops->release_mbufs(txq); txq->ops->free_swring(txq); rte_memzone_free(txq->mz); + if (txq->headwb_mem) + rte_memzone_free(txq->headwb); rte_free(txq); } } @@ -2382,6 +2410,43 @@ txgbe_get_tx_port_offloads(struct rte_eth_dev *dev) return tx_offload_capa; } +static int +txgbe_setup_headwb_resources(struct rte_eth_dev *dev, + void *tx_queue, + unsigned int socket_id) +{ + struct txgbe_hw *hw = TXGBE_DEV_HW(dev); + const struct rte_memzone *headwb; + struct txgbe_tx_queue *txq = tx_queue; + u8 i, headwb_size = 0; + + if (hw->mac.type != txgbe_mac_aml && hw->mac.type != txgbe_mac_aml40) { + txq->headwb_mem = NULL; + return 0; + } + + headwb_size = hw->devarg.tx_headwb_size; + headwb = rte_eth_dma_zone_reserve(dev, "tx_headwb_mem", txq->queue_id, + sizeof(u32) * headwb_size, + TXGBE_ALIGN, socket_id); + + if (headwb == NULL) { + DEBUGOUT("Fail to setup headwb resources: no mem"); + txgbe_tx_queue_release(txq); + return -ENOMEM; + } + + txq->headwb = headwb; + txq->headwb_dma = TMZ_PADDR(headwb); + txq->headwb_mem = (uint32_t *)TMZ_VADDR(headwb); + + /* Zero out headwb_mem memory */ + for (i = 0; i < headwb_size; i++) + txq->headwb_mem[i] = 0; + + return 0; +} + int __rte_cold txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, @@ -2394,6 +2459,7 @@ txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, struct txgbe_hw *hw; uint16_t tx_free_thresh; uint64_t offloads; + s32 err = 0; PMD_INIT_FUNC_TRACE(); hw = TXGBE_DEV_HW(dev); @@ -2513,12 +2579,15 @@ txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, /* set up scalar TX function as appropriate */ txgbe_set_tx_function(dev, txq); + if (hw->devarg.tx_headwb) + err = txgbe_setup_headwb_resources(dev, txq, socket_id); + txq->ops->reset(txq); txq->desc_error = 0; dev->data->tx_queues[queue_idx] = txq; - return 0; + return err; } /** @@ -4676,6 +4745,23 @@ txgbe_dev_tx_init(struct rte_eth_dev *dev) /* Setup the HW Tx Head and TX Tail descriptor pointers */ wr32(hw, TXGBE_TXRP(txq->reg_idx), 0); wr32(hw, TXGBE_TXWP(txq->reg_idx), 0); + + if ((hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) && + hw->devarg.tx_headwb) { + uint32_t txdctl; + + wr32(hw, TXGBE_PX_TR_HEAD_ADDRL(txq->reg_idx), + (uint32_t)(txq->headwb_dma & BIT_MASK32)); + wr32(hw, TXGBE_PX_TR_HEAD_ADDRH(txq->reg_idx), + (uint32_t)(txq->headwb_dma >> 32)); + if (hw->devarg.tx_headwb_size == 16) + txdctl = TXGBE_PX_TR_CFG_HEAD_WB | + TXGBE_PX_TR_CFG_HEAD_WB_64BYTE; + else + txdctl = TXGBE_PX_TR_CFG_HEAD_WB; + wr32m(hw, TXGBE_TXCFG(txq->reg_idx), + TXGBE_PX_TR_CFG_HEAD_WB_MASK, txdctl); + } } #ifndef RTE_LIB_SECURITY diff --git a/drivers/net/txgbe/txgbe_rxtx.h b/drivers/net/txgbe/txgbe_rxtx.h index 622a0d3981..b1ac03576f 100644 --- a/drivers/net/txgbe/txgbe_rxtx.h +++ b/drivers/net/txgbe/txgbe_rxtx.h @@ -414,6 +414,9 @@ struct txgbe_tx_queue { const struct rte_memzone *mz; uint64_t desc_error; bool resetting; + const struct rte_memzone *headwb; + uint64_t headwb_dma; + volatile uint32_t *headwb_mem; }; struct txgbe_txq_ops { diff --git a/drivers/net/txgbe/txgbe_rxtx_vec_common.h b/drivers/net/txgbe/txgbe_rxtx_vec_common.h index cf67df66d8..00847d087b 100644 --- a/drivers/net/txgbe/txgbe_rxtx_vec_common.h +++ b/drivers/net/txgbe/txgbe_rxtx_vec_common.h @@ -89,13 +89,26 @@ txgbe_tx_free_bufs(struct txgbe_tx_queue *txq) int nb_free = 0; struct rte_mbuf *m, *free[RTE_TXGBE_TX_MAX_FREE_BUF_SZ]; - /* check DD bit on threshold descriptor */ - status = txq->tx_ring[txq->tx_next_dd].dw3; - if (!(status & TXGBE_TXD_DD)) { - if (txq->nb_tx_free >> 1 < txq->tx_free_thresh) - txgbe_set32_masked(txq->tdc_reg_addr, - TXGBE_TXCFG_FLUSH, TXGBE_TXCFG_FLUSH); - return 0; + if (txq->headwb_mem) { + uint16_t tx_last_dd = txq->nb_tx_desc + + txq->tx_next_dd - txq->tx_free_thresh; + if (tx_last_dd >= txq->nb_tx_desc) + tx_last_dd -= txq->nb_tx_desc; + volatile uint16_t head = (uint16_t)*txq->headwb_mem; + if (txq->tx_next_dd > head && head > tx_last_dd) + return 0; + else if (tx_last_dd > txq->tx_next_dd && + (head > tx_last_dd || head < txq->tx_next_dd)) + return 0; + } else { + /* check DD bit on threshold descriptor */ + status = txq->tx_ring[txq->tx_next_dd].dw3; + if (!(status & TXGBE_TXD_DD)) { + if (txq->nb_tx_free >> 1 < txq->tx_free_thresh) + txgbe_set32_masked(txq->tdc_reg_addr, + TXGBE_TXCFG_FLUSH, TXGBE_TXCFG_FLUSH); + return 0; + } } n = txq->tx_free_thresh; From patchwork Tue Sep 30 09:59:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zaiyu Wang X-Patchwork-Id: 157124 X-Patchwork-Delegate: stephen@networkplumber.org Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5D4C74886F; Tue, 30 Sep 2025 12:01:39 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DA95940E0B; Tue, 30 Sep 2025 12:00:50 +0200 (CEST) Received: from smtpbg151.qq.com (smtpbg151.qq.com [18.169.211.239]) by mails.dpdk.org (Postfix) with ESMTP id A233240E0A for ; Tue, 30 Sep 2025 12:00:48 +0200 (CEST) X-QQ-mid: esmtpgz13t1759226444tf0d8775f X-QQ-Originating-IP: dRlAi0/vUYMEC4itQhlLblP8W3SDRayNriSmBqEBw1g= Received: from DSK-zaiyuwang.trustnetic.com ( [115.220.225.164]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 30 Sep 2025 18:00:43 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 14889170040542431108 EX-QQ-RecipientCnt: 4 From: Zaiyu Wang To: dev@dpdk.org Cc: Zaiyu Wang , Jiawen Wu , Jian Wang Subject: [PATCH v4 11/20] net/txgbe: add RX desc merge mode for Amber-Lite NICs Date: Tue, 30 Sep 2025 17:59:43 +0800 Message-Id: <20250930095953.18508-12-zaiyuwang@trustnetic.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20250930095953.18508-1-zaiyuwang@trustnetic.com> References: <20250418094131.24136-1-zaiyuwang@trustnetic.com> <20250930095953.18508-1-zaiyuwang@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:trustnetic.com:qybglogicsvrgz:qybglogicsvrgz5a-1 X-QQ-XMAILINFO: MgOpuW05bt0i/o808YtqM3nHdXzvrp0L2Kyd8nzcxEgjIeDDx9dlOxYo +jj8P8MK1/ap6pv0C9ZCJi+1rlm3g3htPfLOGKvRmsrUbbNzhv32Eq1D+6IJGoKQKyd39ZF Xi/nWGpueFUeQQTS3fPTcisRPDrr2n6H/C3Lyopr4tU+lQ4ps8LM+Hsjn6PyNpkD89OMz0G y1p1cvDLE3TemRzlmsEdRlF6IIfUT0kKL11s1rZL9VlGrG1vMKUiV4JugRuHiTCdsARilFk iWEP+ri4oxLyhGPPOLjvWapTkMeiOYhs9un9LC/JnW2PABBYjuRW6NDcErHLAGbR1R755bx muGLF6DRZKXWuCVg1dOm8fyRpKXFHmyOPUP0qco9V1BHIGD5IyO6yrL9SLlIKNKJjsK1cwL aMVXGonXE0TDmSVHfSzGCW//h3Eg9K5d0Pa6Fs/6jNlTdj2Q/xIG35bnbpC0jbNa7tbVpol K2af7QgsLLLraFThZWMgAMZyhjbg+w8FEoVw+1vlumETffjUAiPQKFMP6oNOo4jqj+Samsk aq/xJxBxYBPk/1BsXXHY2lR4WwgL5hJAeAUWnVTiZKi4Yr7VejhQRuxmgnkgqjVHtIbHdjr rAnjqh0LGcsQqSwp2MD5XIsqd+TlCqGOxMMMw/qCECWqVW2RrMQZgvApG+kHbKNXZBk0OQ2 azhmZVr8gj93GRoUplsqFWQAxyahrkhyogLJX//BdTMzoGxTLcT+X6hHODYKq2jRo9KMfeu AXrzAsoGKus1GvaA3RRXRIqgiz9VkhJFnisOr60UueGL5zML7SJyF2LiktKs++38lxMBiSn KbKxRIRwVOvtAuz6UYesawrAmq/1iZpmPO8iWTgEu1mGrQwUQQ2Osx3wHMoUQ1WBKXnH2i2 n60lp1XY05ouTwJ9F3GVwgk9fhgklhvYoum37HptNBm73iAOm82H/HdnKz5XOBUhSgbt19E egNKjXjiuZ8vk5dM2d+M3TIioEghCt62kLUW5OGONwx/YjRKKdp8JK+eHQmnEIUY6MNqPOy 5MMVE0p05f80B7+nMtrYKTwRfIeSlN+3Ruji8YQxZomznd5WlzkaoaDBwFPELoJW1mdm4fN w== X-QQ-XMRINFO: MSVp+SPm3vtS1Vd6Y4Mggwc= X-QQ-RECHKSPAM: 0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add RX desc merge mode for Amber-Lite NICs. When enabled, the hardware batch-processes RX packets, significantly enhancing performance. This feature is enabled by default in the driver and can be configured via the rx_desc_merge parameter in devargs. Signed-off-by: Zaiyu Wang --- drivers/net/txgbe/base/txgbe_regs.h | 4 ++++ drivers/net/txgbe/base/txgbe_type.h | 3 +++ drivers/net/txgbe/txgbe_ethdev.c | 7 ++++++- drivers/net/txgbe/txgbe_rxtx.c | 11 +++++++++++ 4 files changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h index 1a544bcd57..e050941992 100644 --- a/drivers/net/txgbe/base/txgbe_regs.h +++ b/drivers/net/txgbe/base/txgbe_regs.h @@ -1377,6 +1377,7 @@ enum txgbe_5tuple_protocol { #define TXGBE_RXCFG_HDRLEN(v) LS(HDRLEN(v), 12, 0xF) #define TXGBE_RXCFG_HDRLEN_MASK MS(12, 0xF) #define TXGBE_RXCFG_WTHRESH(v) LS(v, 16, 0x7) +#define TXGBE_RXCFG_DESC_MERGE MS(19, 0x1) #define TXGBE_RXCFG_ETAG MS(22, 0x1) #define TXGBE_RXCFG_RSCMAX_MASK MS(23, 0x3) #define TXGBE_RXCFG_RSCMAX_1 LS(0, 23, 0x3) @@ -1671,6 +1672,9 @@ enum txgbe_5tuple_protocol { #define TXGBE_RPUP2TC_UP_SHIFT 3 #define TXGBE_RPUP2TC_UP_MASK 0x7 +#define TXGBE_RDM_DCACHE_CTL 0x0120A8 +#define TXGBE_RDM_DCACHE_CTL_EN MS(0, 0x1) + /* mac switcher */ #define TXGBE_ETHADDRL 0x016200 #define TXGBE_ETHADDRL_AD0(v) LS(v, 0, 0xFF) diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h index 844a2827bc..03e5bd489d 100644 --- a/drivers/net/txgbe/base/txgbe_type.h +++ b/drivers/net/txgbe/base/txgbe_type.h @@ -718,6 +718,7 @@ struct txgbe_phy_info { #define TXGBE_DEVARG_FFE_POST "ffe_post" #define TXGBE_DEVARG_TX_HEAD_WB "tx_headwb" #define TXGBE_DEVARG_TX_HEAD_WB_SIZE "tx_headwb_size" +#define TXGBE_DEVARG_RX_DESC_MERGE "rx_desc_merge" static const char * const txgbe_valid_arguments[] = { TXGBE_DEVARG_BP_AUTO, @@ -730,6 +731,7 @@ static const char * const txgbe_valid_arguments[] = { TXGBE_DEVARG_FFE_POST, TXGBE_DEVARG_TX_HEAD_WB, TXGBE_DEVARG_TX_HEAD_WB_SIZE, + TXGBE_DEVARG_RX_DESC_MERGE, NULL }; @@ -782,6 +784,7 @@ struct txgbe_devargs { u16 sgmii; u16 tx_headwb; u16 tx_headwb_size; + u16 rx_desc_merge; }; struct txgbe_hw { diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c index 9c14e4b8ed..13d1d6924d 100644 --- a/drivers/net/txgbe/txgbe_ethdev.c +++ b/drivers/net/txgbe/txgbe_ethdev.c @@ -516,6 +516,7 @@ txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs) /* New devargs for amberlite config */ u16 tx_headwb = 1; u16 tx_headwb_size = 16; + u16 rx_desc_merge = 1; if (devargs == NULL) goto null; @@ -544,6 +545,8 @@ txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs) &txgbe_handle_devarg, &tx_headwb); rte_kvargs_process(kvlist, TXGBE_DEVARG_TX_HEAD_WB_SIZE, &txgbe_handle_devarg, &tx_headwb_size); + rte_kvargs_process(kvlist, TXGBE_DEVARG_RX_DESC_MERGE, + &txgbe_handle_devarg, &rx_desc_merge); rte_kvargs_free(kvlist); null: @@ -553,6 +556,7 @@ txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs) hw->devarg.sgmii = sgmii; hw->devarg.tx_headwb = tx_headwb; hw->devarg.tx_headwb_size = tx_headwb_size; + hw->devarg.rx_desc_merge = rx_desc_merge; hw->phy.ffe_set = ffe_set; hw->phy.ffe_main = ffe_main; hw->phy.ffe_pre = ffe_pre; @@ -5729,7 +5733,8 @@ RTE_PMD_REGISTER_PARAM_STRING(net_txgbe, TXGBE_DEVARG_FFE_PRE "=" TXGBE_DEVARG_FFE_POST "=" TXGBE_DEVARG_TX_HEAD_WB "=<0|1>" - TXGBE_DEVARG_TX_HEAD_WB_SIZE "=<1|16>"); + TXGBE_DEVARG_TX_HEAD_WB_SIZE "=<1|16>" + TXGBE_DEVARG_RX_DESC_MERGE "=<0|1>"); RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_init, init, NOTICE); RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_driver, driver, NOTICE); diff --git a/drivers/net/txgbe/txgbe_rxtx.c b/drivers/net/txgbe/txgbe_rxtx.c index b15b6788e6..957aa5c6eb 100644 --- a/drivers/net/txgbe/txgbe_rxtx.c +++ b/drivers/net/txgbe/txgbe_rxtx.c @@ -4667,6 +4667,17 @@ txgbe_dev_rx_init(struct rte_eth_dev *dev) buf_size = ROUND_DOWN(buf_size, 0x1 << 10); srrctl |= TXGBE_RXCFG_PKTLEN(buf_size); + if ((hw->mac.type == txgbe_mac_aml || + hw->mac.type == txgbe_mac_aml40) && hw->devarg.rx_desc_merge == 1) { + srrctl |= TXGBE_RXCFG_DESC_MERGE; + + wr32(hw, TXGBE_RDM_DCACHE_CTL, TXGBE_RDM_DCACHE_CTL_EN); + wr32m(hw, TXGBE_RDM_RSC_CTL, TXGBE_RDM_RSC_CTL_FREE_CTL, + TXGBE_RDM_RSC_CTL_FREE_CTL); + wr32m(hw, TXGBE_RDM_RSC_CTL, TXGBE_RDM_RSC_CTL_FREE_CNT_DIS, + ~TXGBE_RDM_RSC_CTL_FREE_CNT_DIS); + } + wr32(hw, TXGBE_RXCFG(rxq->reg_idx), srrctl); /* It adds dual VLAN length for supporting dual VLAN */ From patchwork Tue Sep 30 09:59:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zaiyu Wang X-Patchwork-Id: 157125 X-Patchwork-Delegate: stephen@networkplumber.org Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 951914886F; Tue, 30 Sep 2025 12:01:45 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EDD3740DD1; Tue, 30 Sep 2025 12:00:56 +0200 (CEST) Received: from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166]) by mails.dpdk.org (Postfix) with ESMTP id 6EE7C40E1F for ; Tue, 30 Sep 2025 12:00:52 +0200 (CEST) X-QQ-mid: esmtpgz13t1759226447tb069bd16 X-QQ-Originating-IP: dVtHmBlkMXjbKyqMZ12STPBWo/iTm39e8A89WocjRvI= Received: from DSK-zaiyuwang.trustnetic.com ( [115.220.225.164]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 30 Sep 2025 18:00:46 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 13236182368315923075 EX-QQ-RecipientCnt: 4 From: Zaiyu Wang To: dev@dpdk.org Cc: Zaiyu Wang , Jiawen Wu , Jian Wang Subject: [PATCH v4 12/20] net/txgbe: add FEC support for Amber-Lite 25G NICs Date: Tue, 30 Sep 2025 17:59:44 +0800 Message-Id: <20250930095953.18508-13-zaiyuwang@trustnetic.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20250930095953.18508-1-zaiyuwang@trustnetic.com> References: <20250418094131.24136-1-zaiyuwang@trustnetic.com> <20250930095953.18508-1-zaiyuwang@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:trustnetic.com:qybglogicsvrgz:qybglogicsvrgz5a-1 X-QQ-XMAILINFO: NSahpW5IwUZOh6hQfTRv2Zb+bg4EpsjsiklnDCJ5BbZHwlKUqbJJ8cfa jxymBV2WGOly80O4FGPO6BSTe2K/V+sy1QVh9zgoxxVf8+HLRh2wA7NTzqfWC9Yxb1kQpCo UNwQU194UcQVCryBYf3QisXgK+uRs61EgO6ZTwQh7kP1VPSs9gzG8AIiiEWlRLixDTQo/se Y7Zx0tl4Z9kn1fVlO2PDCRDfX+X3Y6JMp6Y4Mk+oPJz7Z1TzShBd4ohhi8+8E4aeP+gihRd 8vSQNsK3fJ3d586jHGGynHFo8HMq8EuRkQ7QcXostcAvTZbI4bhX2RlBAr0HH3hnb8A6JSf oph5DIUYkrFZUhT3weUVo48nybnuxBtpm8i/t4W8LdrbXkwSSiHtTekzQkzTx1yYQuiEWvW OGXJ7jZ+iRbc9cQZqiV2mNkJTasDci+5FjFXAyy/9TaqLLu+gu9NAgBUF7e/CXvbJt0xn2t 2wlZZgciJd1sVtr66gfnY8oTnPTzG9FGWw081CQlP/Ngkzt+G2RW1v/oL1iR4Rp6iYBBFVN mJqPBTx8Bm/VerkhJp+N04gw0ME7+5NSXOiUiVaSKMmEvZX0ph5wPQ1afKqU5Zy1ZUs8E3w a+/b4I1gWP4uo01IRIQCKMT7fE/4r/0FZXVP8y/9oKMidiyi0GPzAQCZtsrdzJjfqIsXY75 9vUMdLFk1fQmwkHaprwdjXEYiZ2VsKqC7rgUCbMAfBnLNVb4MPGzOYurQEKZZQq72v7lfQs dPfMYqDlNfdf24F4oS1fKDkaj54xyXdj26nbTfuAkgg2RQjK0noJwV/J7KooS6jP2QaYonD BNgsVMc+AIGJ+Twng9U0O7DfD1n8Gkv5b+Qfi1n/kHd3bzFMI9kY3f5+qn2sH88CvEiQz2f oAUo0/wxW+vWlI2fFYB606ayiNiHy0aV5IFAlhNCDi6jqzieCIlvCQuoyR+bH+knTnUy+5q Ujq2MW5Vj06bG6j9gO1mqd0w53MiIjhUDXO0zcJCdx5iR4T8R4Fof1ZwKoYBYvPEpdmMzir eAEVT1Z24sQwx5NGgfmDckvck+E+Ssyjf/i42yoCiIdo/WjFwsTbZI6+kpcVzehJFEYwP76 w== X-QQ-XMRINFO: NyFYKkN4Ny6FSmKK/uo/jdU= X-QQ-RECHKSPAM: 0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Amber-Lite 25G NICs support four FEC modes (off, baser, rs, auto). The driver implements standard interfaces (fec_get_capability, fec_get, fec_set) to allow manual configuration. The default FEC mode is set to 'auto'. Signed-off-by: Zaiyu Wang --- drivers/net/txgbe/base/txgbe_aml.c | 27 ++++++- drivers/net/txgbe/base/txgbe_hw.c | 3 + drivers/net/txgbe/base/txgbe_mng.c | 2 +- drivers/net/txgbe/base/txgbe_phy.h | 1 + drivers/net/txgbe/base/txgbe_type.h | 2 + drivers/net/txgbe/txgbe_ethdev.c | 121 ++++++++++++++++++++++++++++ 6 files changed, 154 insertions(+), 2 deletions(-) diff --git a/drivers/net/txgbe/base/txgbe_aml.c b/drivers/net/txgbe/base/txgbe_aml.c index 3283d3f56c..867cf4c2d3 100644 --- a/drivers/net/txgbe/base/txgbe_aml.c +++ b/drivers/net/txgbe/base/txgbe_aml.c @@ -131,6 +131,26 @@ u32 txgbe_get_media_type_aml(struct txgbe_hw *hw) return media_type; } +static int +txgbe_phy_fec_get(struct txgbe_hw *hw) +{ + int value = 0; + + rte_spinlock_lock(&hw->phy_lock); + value = rd32_epcs(hw, SR_PMA_RS_FEC_CTRL); + rte_spinlock_unlock(&hw->phy_lock); + if (value & 0x4) + return TXGBE_PHY_FEC_RS; + + rte_spinlock_lock(&hw->phy_lock); + value = rd32_epcs(hw, SR_PMA_KR_FEC_CTRL); + rte_spinlock_unlock(&hw->phy_lock); + if (value & 0x1) + return TXGBE_PHY_FEC_BASER; + + return TXGBE_PHY_FEC_OFF; +} + void txgbe_wait_for_link_up_aml(struct txgbe_hw *hw, u32 speed) { u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN; @@ -184,7 +204,12 @@ s32 txgbe_setup_mac_link_aml(struct txgbe_hw *hw, status = hw->mac.check_link(hw, &link_speed, &link_up, autoneg_wait_to_complete); - if (link_speed == speed && link_up) + if (link_up && speed == TXGBE_LINK_SPEED_25GB_FULL) + hw->cur_fec_link = txgbe_phy_fec_get(hw); + + if (link_speed == speed && link_up && + !(speed == TXGBE_LINK_SPEED_25GB_FULL && + !(hw->fec_mode & hw->cur_fec_link))) return status; if (speed & TXGBE_LINK_SPEED_25GB_FULL) diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c index 6d3b917bbf..cbf7aafe7f 100644 --- a/drivers/net/txgbe/base/txgbe_hw.c +++ b/drivers/net/txgbe/base/txgbe_hw.c @@ -338,6 +338,9 @@ s32 txgbe_init_hw(struct txgbe_hw *hw) txgbe_disable_lldp(hw); + /* Init fec mode to 'AUTO' */ + hw->fec_mode = TXGBE_PHY_FEC_AUTO; + /* Reset the hardware */ status = hw->mac.reset_hw(hw); if (status == 0 || status == TXGBE_ERR_SFP_NOT_PRESENT) { diff --git a/drivers/net/txgbe/base/txgbe_mng.c b/drivers/net/txgbe/base/txgbe_mng.c index 782e86e1fa..05eb07c0e2 100644 --- a/drivers/net/txgbe/base/txgbe_mng.c +++ b/drivers/net/txgbe/base/txgbe_mng.c @@ -613,7 +613,7 @@ s32 txgbe_hic_ephy_set_link(struct txgbe_hw *hw, u8 speed, u8 autoneg, u8 duplex buffer.hdr.buf_len = sizeof(struct txgbe_hic_ephy_setlink) - sizeof(struct txgbe_hic_hdr); buffer.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; - buffer.fec_mode = TXGBE_PHY_FEC_AUTO; + buffer.fec_mode = hw->fec_mode; buffer.speed = speed; buffer.autoneg = autoneg; buffer.duplex = duplex; diff --git a/drivers/net/txgbe/base/txgbe_phy.h b/drivers/net/txgbe/base/txgbe_phy.h index c02be3cc34..f1849c8400 100644 --- a/drivers/net/txgbe/base/txgbe_phy.h +++ b/drivers/net/txgbe/base/txgbe_phy.h @@ -40,6 +40,7 @@ #define SR_PMA_KR_LD_CESTS_RR MS16(15, 0x1) #define SR_PMA_KR_FEC_CTRL 0x0100AB #define SR_PMA_KR_FEC_CTRL_EN MS16(0, 0x1) +#define SR_PMA_RS_FEC_CTRL 0x0100C8 #define SR_MII_MMD_CTL 0x1F0000 #define SR_MII_MMD_CTL_AN_EN 0x1000 #define SR_MII_MMD_CTL_RESTART_AN 0x0200 diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h index 03e5bd489d..c5f51b3ade 100644 --- a/drivers/net/txgbe/base/txgbe_type.h +++ b/drivers/net/txgbe/base/txgbe_type.h @@ -848,6 +848,8 @@ struct txgbe_hw { /*amlite: new SW-FW mbox */ u8 swfw_index; rte_atomic32_t swfw_busy; + u32 fec_mode; + u32 cur_fec_link; }; struct txgbe_backplane_ability { diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c index 13d1d6924d..dc190fbc1a 100644 --- a/drivers/net/txgbe/txgbe_ethdev.c +++ b/drivers/net/txgbe/txgbe_ethdev.c @@ -2806,9 +2806,31 @@ txgbe_dev_detect_sfp(void *param) { struct rte_eth_dev *dev = (struct rte_eth_dev *)param; struct txgbe_hw *hw = TXGBE_DEV_HW(dev); + u32 value = 0; s32 err; + if (hw->mac.type == txgbe_mac_aml40) { + value = rd32(hw, TXGBE_GPIOEXT); + if (value & TXGBE_SFP1_MOD_PRST_LS) { + err = TXGBE_ERR_SFP_NOT_PRESENT; + goto out; + } + } + + if (hw->mac.type == txgbe_mac_aml) { + value = rd32(hw, TXGBE_GPIOEXT); + if (value & TXGBE_SFP1_MOD_ABS_LS) { + err = TXGBE_ERR_SFP_NOT_PRESENT; + goto out; + } + } + + /* wait for sfp module ready*/ + if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) + msec_delay(200); + err = hw->phy.identify_sfp(hw); +out: if (err == TXGBE_ERR_SFP_NOT_SUPPORTED) { PMD_DRV_LOG(ERR, "Unsupported SFP+ module type was detected."); } else if (err == TXGBE_ERR_SFP_NOT_PRESENT) { @@ -5642,6 +5664,102 @@ txgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev) return 0; } +static int txgbe_fec_get_capa_speed_to_fec(struct rte_eth_fec_capa *speed_fec_capa) +{ + int num = 2; + + if (speed_fec_capa) { + speed_fec_capa[0].speed = RTE_ETH_SPEED_NUM_10G; + speed_fec_capa[0].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC); + speed_fec_capa[1].speed = RTE_ETH_SPEED_NUM_25G; + speed_fec_capa[1].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | + RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | + RTE_ETH_FEC_MODE_CAPA_MASK(BASER) | + RTE_ETH_FEC_MODE_CAPA_MASK(RS); + } + + return num; +} + +static int txgbe_fec_get_capability(struct rte_eth_dev *dev, + struct rte_eth_fec_capa *speed_fec_capa, + unsigned int num) +{ + struct txgbe_hw *hw = TXGBE_DEV_HW(dev); + u8 num_entries; + + if (hw->mac.type != txgbe_mac_aml) + return -EOPNOTSUPP; + + num_entries = txgbe_fec_get_capa_speed_to_fec(NULL); + if (!speed_fec_capa || num < num_entries) + return num_entries; + + return txgbe_fec_get_capa_speed_to_fec(speed_fec_capa); +} + +static int txgbe_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa) +{ + struct txgbe_hw *hw = TXGBE_DEV_HW(dev); + u32 speed = 0; + bool negotiate = false; + u32 curr_fec_mode; + + hw->mac.get_link_capabilities(hw, &speed, &negotiate); + + if (hw->mac.type != txgbe_mac_aml || + !(speed & TXGBE_LINK_SPEED_25GB_FULL)) + return -EOPNOTSUPP; + + if (hw->fec_mode == TXGBE_PHY_FEC_AUTO) + curr_fec_mode = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO); + else if (hw->fec_mode == TXGBE_PHY_FEC_RS) + curr_fec_mode = RTE_ETH_FEC_MODE_CAPA_MASK(RS); + else if (hw->fec_mode == TXGBE_PHY_FEC_BASER) + curr_fec_mode = RTE_ETH_FEC_MODE_CAPA_MASK(BASER); + else + curr_fec_mode = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC); + + *fec_capa = curr_fec_mode; + return 0; +} + +static int txgbe_fec_set(struct rte_eth_dev *dev, u32 fec_capa) +{ + struct txgbe_hw *hw = TXGBE_DEV_HW(dev); + u32 orig_fec_mode = hw->fec_mode; + bool negotiate = false; + u32 speed = 0; + + hw->mac.get_link_capabilities(hw, &speed, &negotiate); + + if (hw->mac.type != txgbe_mac_aml || + !(speed & TXGBE_LINK_SPEED_25GB_FULL)) + return -EOPNOTSUPP; + + if (!fec_capa) + return -EINVAL; + + if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(AUTO)) + hw->fec_mode = TXGBE_PHY_FEC_AUTO; + + if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC)) + hw->fec_mode = TXGBE_PHY_FEC_OFF; + + if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(BASER)) + hw->fec_mode = TXGBE_PHY_FEC_BASER; + + if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(RS)) + hw->fec_mode = TXGBE_PHY_FEC_RS; + + if (hw->fec_mode != orig_fec_mode) { + txgbe_dev_setup_link_alarm_handler(dev); + txgbe_dev_link_update(dev, 0); + } + + return 0; +} + static const struct eth_dev_ops txgbe_eth_dev_ops = { .dev_configure = txgbe_dev_configure, .dev_infos_get = txgbe_dev_info_get, @@ -5718,6 +5836,9 @@ static const struct eth_dev_ops txgbe_eth_dev_ops = { .udp_tunnel_port_del = txgbe_dev_udp_tunnel_port_del, .tm_ops_get = txgbe_tm_ops_get, .tx_done_cleanup = txgbe_dev_tx_done_cleanup, + .fec_get_capability = txgbe_fec_get_capability, + .fec_get = txgbe_fec_get, + .fec_set = txgbe_fec_set, }; RTE_PMD_REGISTER_PCI(net_txgbe, rte_txgbe_pmd); From patchwork Tue Sep 30 09:59:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zaiyu Wang X-Patchwork-Id: 157126 X-Patchwork-Delegate: stephen@networkplumber.org Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3E1064886F; Tue, 30 Sep 2025 12:01:52 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EC36740E25; Tue, 30 Sep 2025 12:00:57 +0200 (CEST) Received: from smtpbgsg2.qq.com (smtpbgsg2.qq.com [54.254.200.128]) by mails.dpdk.org (Postfix) with ESMTP id 8D15340DDB for ; Tue, 30 Sep 2025 12:00:53 +0200 (CEST) X-QQ-mid: esmtpgz13t1759226450t58455813 X-QQ-Originating-IP: /m314BnB1V4OKYqW3opHHlnMuAG6rQE/O4sfaRAf94U= Received: from DSK-zaiyuwang.trustnetic.com ( [115.220.225.164]) by bizesmtp.qq.com (ESMTP) with id ; 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Signed-off-by: Zaiyu Wang --- drivers/net/txgbe/base/txgbe_regs.h | 2 + drivers/net/txgbe/txgbe_ethdev.c | 111 ++++++++++++++++++++++++++++ 2 files changed, 113 insertions(+) diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h index e050941992..00c41a5b86 100644 --- a/drivers/net/txgbe/base/txgbe_regs.h +++ b/drivers/net/txgbe/base/txgbe_regs.h @@ -1631,6 +1631,8 @@ enum txgbe_5tuple_protocol { #define TXGBE_GPIOINTEN 0x014830 #define TXGBE_GPIOINTMASK 0x014834 #define TXGBE_GPIOINTTYPE 0x014838 +#define TXGBE_GPIO_INT_POLARITY 0x01483C +#define TXGBE_GPIO_INT_POLARITY_3 MS(3, 0x1) #define TXGBE_GPIOINTSTAT 0x014840 #define TXGBE_GPIORAWINTSTAT 0x014844 #define TXGBE_GPIOEOI 0x01484C diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c index dc190fbc1a..e6694f7fc2 100644 --- a/drivers/net/txgbe/txgbe_ethdev.c +++ b/drivers/net/txgbe/txgbe_ethdev.c @@ -353,11 +353,33 @@ txgbe_enable_intr(struct rte_eth_dev *dev) { struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); struct txgbe_hw *hw = TXGBE_DEV_HW(dev); + uint32_t gpie; wr32(hw, TXGBE_IENMISC, intr->mask_misc); wr32(hw, TXGBE_IMC(0), TXGBE_IMC_MASK); wr32(hw, TXGBE_IMC(1), TXGBE_IMC_MASK); txgbe_flush(hw); + + /* To avoid gpio intr lost, enable pcie intr first. Then enable gpio intr. */ + if (hw->mac.type == txgbe_mac_aml) { + gpie = rd32(hw, TXGBE_GPIOINTEN); + gpie |= TXGBE_GPIOBIT_2 | TXGBE_GPIOBIT_3 | TXGBE_GPIOBIT_6; + wr32(hw, TXGBE_GPIOINTEN, gpie); + + gpie = rd32(hw, TXGBE_GPIOINTTYPE); + gpie |= TXGBE_GPIOBIT_2 | TXGBE_GPIOBIT_3 | TXGBE_GPIOBIT_6; + wr32(hw, TXGBE_GPIOINTTYPE, gpie); + } + + if (hw->mac.type == txgbe_mac_aml40) { + gpie = rd32(hw, TXGBE_GPIOINTEN); + gpie |= TXGBE_GPIOBIT_4; + wr32(hw, TXGBE_GPIOINTEN, gpie); + + gpie = rd32(hw, TXGBE_GPIOINTTYPE); + gpie |= TXGBE_GPIOBIT_4; + wr32(hw, TXGBE_GPIOINTTYPE, gpie); + } } static void @@ -1711,6 +1733,7 @@ txgbe_dev_start(struct rte_eth_dev *dev) uint16_t vf, idx; uint32_t *link_speeds; struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev); + u32 links_reg; PMD_INIT_FUNC_TRACE(); @@ -1892,6 +1915,44 @@ txgbe_dev_start(struct rte_eth_dev *dev) if (err) goto error; + if (hw->mac.type == txgbe_mac_aml) { + links_reg = rd32(hw, TXGBE_PORT); + if (links_reg & TXGBE_PORT_LINKUP) { + if (links_reg & TXGBE_CFG_PORT_ST_AML_LINK_25G) { + wr32(hw, TXGBE_MACTXCFG, + (rd32(hw, TXGBE_MACTXCFG) & + ~TXGBE_MAC_TX_CFG_AML_SPEED_MASK) | + TXGBE_MAC_TX_CFG_AML_SPEED_25G); + } else if (links_reg & TXGBE_CFG_PORT_ST_AML_LINK_10G) { + wr32(hw, TXGBE_MACTXCFG, + (rd32(hw, TXGBE_MACTXCFG) & + ~TXGBE_MAC_TX_CFG_AML_SPEED_MASK) | + TXGBE_MAC_TX_CFG_AML_SPEED_10G); + } + } + + /* amlite: restart gpio */ + wr32(hw, TXGBE_GPIODIR, TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1 | + TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5); + wr32(hw, TXGBE_GPIODATA, TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5); + msleep(10); + wr32(hw, TXGBE_GPIODATA, TXGBE_GPIOBIT_0); + wr32m(hw, TXGBE_GPIO_INT_POLARITY, TXGBE_GPIO_INT_POLARITY_3, 0x0); + } else if (hw->mac.type == txgbe_mac_aml40) { + links_reg = rd32(hw, TXGBE_PORT); + if (links_reg & TXGBE_PORT_LINKUP) { + if (links_reg & TXGBE_CFG_PORT_ST_AML_LINK_40G) { + wr32(hw, TXGBE_MACTXCFG, + (rd32(hw, TXGBE_MACTXCFG) & + ~TXGBE_MAC_TX_CFG_AML_SPEED_MASK) | + TXGBE_MAC_TX_CFG_AML_SPEED_40G); + } + } + + wr32(hw, TXGBE_GPIODIR, TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1 + | TXGBE_GPIOBIT_3); + wr32(hw, TXGBE_GPIODATA, TXGBE_GPIOBIT_1); + } skip_link_setup: if (rte_intr_allow_others(intr_handle)) { @@ -1989,6 +2050,10 @@ txgbe_dev_stop(struct rte_eth_dev *dev) for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++) vfinfo[vf].clear_to_send = false; + if (hw->mac.type == txgbe_mac_aml) + wr32m(hw, TXGBE_AML_EPCS_MISC_CTL, + TXGBE_AML_LINK_STATUS_OVRD_EN, 0x0); + txgbe_dev_clear_queues(dev); /* Clear stored conf */ @@ -2868,6 +2933,27 @@ txgbe_dev_sfp_event(struct rte_eth_dev *dev) intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE; } + if (hw->mac.type == txgbe_mac_aml40) { + if (reg & TXGBE_GPIOBIT_4) { + wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_4); + rte_eal_alarm_set(1000 * 100, txgbe_dev_detect_sfp, dev); + } + } else if (hw->mac.type == txgbe_mac_sp || hw->mac.type == txgbe_mac_aml) { + if (reg & TXGBE_GPIOBIT_0) + wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_0); + if (reg & TXGBE_GPIOBIT_2) { + wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_2); + rte_eal_alarm_set(1000 * 100, txgbe_dev_detect_sfp, dev); + } + if (reg & TXGBE_GPIOBIT_3) { + wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_3); + intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE; + } + if (reg & TXGBE_GPIOBIT_6) { + wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_6); + intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE; + } + } wr32(hw, TXGBE_GPIOINTMASK, 0); } @@ -3045,6 +3131,9 @@ txgbe_dev_link_update_share(struct rte_eth_dev *dev, } if (link_up == 0) { + if (hw->mac.type == txgbe_mac_aml) + wr32m(hw, TXGBE_GPIO_INT_POLARITY, + TXGBE_GPIO_INT_POLARITY_3, 0x0); if ((hw->subsystem_device_id & 0xFF) == TXGBE_DEV_ID_KR_KX_KX4) { hw->mac.bp_down_event(hw); @@ -3131,6 +3220,28 @@ txgbe_dev_link_update_share(struct rte_eth_dev *dev, wr32(hw, TXGBE_MAC_WDG_TIMEOUT, reg); } + if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) { + reg = rd32(hw, TXGBE_PORT); + if (reg & TXGBE_PORT_LINKUP) { + if (reg & TXGBE_CFG_PORT_ST_AML_LINK_40G) { + wr32(hw, TXGBE_MACTXCFG, + (rd32(hw, TXGBE_MACTXCFG) & + ~TXGBE_MAC_TX_CFG_AML_SPEED_MASK) | TXGBE_MACTXCFG_TXE | + TXGBE_MAC_TX_CFG_AML_SPEED_40G); + } else if (reg & TXGBE_CFG_PORT_ST_AML_LINK_25G) { + wr32(hw, TXGBE_MACTXCFG, + (rd32(hw, TXGBE_MACTXCFG) & + ~TXGBE_MAC_TX_CFG_AML_SPEED_MASK) | TXGBE_MACTXCFG_TXE | + TXGBE_MAC_TX_CFG_AML_SPEED_25G); + } else if (reg & TXGBE_CFG_PORT_ST_AML_LINK_10G) { + wr32(hw, TXGBE_MACTXCFG, + (rd32(hw, TXGBE_MACTXCFG) & + ~TXGBE_MAC_TX_CFG_AML_SPEED_MASK) | TXGBE_MACTXCFG_TXE | + TXGBE_MAC_TX_CFG_AML_SPEED_10G); + } + } + } + return rte_eth_linkstatus_set(dev, &link); } From patchwork Tue Sep 30 09:59:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zaiyu Wang X-Patchwork-Id: 157127 X-Patchwork-Delegate: stephen@networkplumber.org Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4EB644886F; Tue, 30 Sep 2025 12:02:00 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 879FC40DCD; Tue, 30 Sep 2025 12:01:00 +0200 (CEST) Received: from smtpbgbr2.qq.com (smtpbgbr2.qq.com [54.207.22.56]) by mails.dpdk.org (Postfix) with ESMTP id C8BFE40E1F for ; Tue, 30 Sep 2025 12:00:57 +0200 (CEST) X-QQ-mid: esmtpgz13t1759226452t26773769 X-QQ-Originating-IP: LdZmLwo+x940J4kAIxgUwVJ02BnZwNPUvBF62PRpkvo= Received: from DSK-zaiyuwang.trustnetic.com ( [115.220.225.164]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 30 Sep 2025 18:00:51 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 3282865521064815579 EX-QQ-RecipientCnt: 4 From: Zaiyu Wang To: dev@dpdk.org Cc: Zaiyu Wang , Jiawen Wu , Jian Wang Subject: [PATCH v4 14/20] net/txgbe: disable unstable features Date: Tue, 30 Sep 2025 17:59:46 +0800 Message-Id: <20250930095953.18508-15-zaiyuwang@trustnetic.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20250930095953.18508-1-zaiyuwang@trustnetic.com> References: <20250418094131.24136-1-zaiyuwang@trustnetic.com> <20250930095953.18508-1-zaiyuwang@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:trustnetic.com:qybglogicsvrgz:qybglogicsvrgz5a-1 X-QQ-XMAILINFO: NLzRLBwQcCCDJ9cC9dTwEHL4oaJ881OZNwCId6Cl0ECR1mUliW90iwJF 3dIvetFRovRvUw1qUilUy0mF/HB/W6YMsNWpXpRlImys5gycg7SMcQBWQNAG9ocnr8Q4VvD SpxFe5NLqv4yO4rc70/PMQ4qL3LJ0qpwmupHqLRVoVNbgpvSaoi4jd3sLJj1pb4v3ki28mC A9ijoOc2RZQa+Zkhub5DBZBOIVNt8PzWg4AaAf0iqCpZGFW/wItPTnc6Nf81pfAkbdhts6V goRjdADHdzOpKwZBBg8ds2HooL+9lWTBSMcSihM+1hugNzbaYgRco4urj8hvwNWSqea9xm7 au3PiRDVcgFi9nx1z3JYPslt0D5EC5IbolOD+RXqW1nG++g6rTPO0owPobnbSe9HXzqwMnl MOlq6v3USPPluWmM/V1Cy3WvdyIeSrzRU+CcdMoLO2Y55EgSjiExGcJLI2H181Oq4lLHoCg tb0ktEazPT/XeGUd7sd6UlpS6l/nlcvgPFXo/ip/HVAodhRSEt0MYsi3aCX22SYyoHp2Tye YyRzfXZBPQEDepaYkUc2VkDBSOcDvwlu8uE4JWHsF4SaxDTClPUYdjRb+LZnhMityMW30Zi eOWFFJUWeXn8448iM75OWUmjGwNwoWwUCatqlQZof0qKCss/riq+iigO84CCDzI7+ohsjTt fezTHCsOQoCRac+s5uxAXR/A0rrCWkwg/7LIdsf8Aoa9y+EpkQckZ7oZOCAc443+oBQyLXh 4uhBlLIhuheoY3XyMb8YuUhTzN6CxCAomuhxtSuSQ6uiPulgE/PdbEiXDqIdDDyMnu9efQV rT9TBlzSkSM0rbE4IBxuEVfPHkPdHVumvDCXkU7z2wLDPrAo3ttew/JIkpIgerEEueFhYPp 8GODTFg/VOHUOGUO5WlhO82e5Oml9UZrkJtOG/MaFIqIY7+p9faZtKqJYfQ/Z/SkRRra5OZ 98JQGIa4EjrFOsrh7il487AuTyBfD1HZMZOj9BjKppu4v9eAHk8b7pr9wdWZpnk1tshuRoe Ffki1zB0aSUzTBbnwlwKhP0PswLwSTlIGH2wEhM0z30LzgWamc8qHcV9/hCOUCvWEpR4kFL YY7Q188R/GK X-QQ-XMRINFO: MPJ6Tf5t3I/ycC2BItcBVIA= X-QQ-RECHKSPAM: 0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Temporarily disabled unstable features on Amber-Lite NICs (e.g., flow control). These incomplete features will be gradually completed in future driver updates. Signed-off-by: Zaiyu Wang --- drivers/net/txgbe/base/txgbe_hw.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c index cbf7aafe7f..d845fd0a69 100644 --- a/drivers/net/txgbe/base/txgbe_hw.c +++ b/drivers/net/txgbe/base/txgbe_hw.c @@ -144,6 +144,10 @@ s32 txgbe_setup_fc(struct txgbe_hw *hw) u32 value = 0; u64 reg_bp = 0; + /* amlite-to-do */ + if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) + return 0; + /* Validate the requested mode */ if (hw->fc.strict_ieee && hw->fc.requested_mode == txgbe_fc_rx_pause) { DEBUGOUT("txgbe_fc_rx_pause not valid in strict IEEE mode"); @@ -3242,6 +3246,9 @@ void txgbe_set_hard_rate_select_speed(struct txgbe_hw *hw, u32 esdp_reg = rd32(hw, TXGBE_GPIODATA); switch (speed) { + case TXGBE_LINK_SPEED_25GB_FULL: + /* amlite-to-do */ + break; case TXGBE_LINK_SPEED_10GB_FULL: esdp_reg |= (TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5); break; From patchwork Tue Sep 30 09:59:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zaiyu Wang X-Patchwork-Id: 157128 X-Patchwork-Delegate: stephen@networkplumber.org Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 66CCD4886F; Tue, 30 Sep 2025 12:02:06 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A2EF540E16; Tue, 30 Sep 2025 12:01:02 +0200 (CEST) Received: from smtpbguseast1.qq.com (smtpbguseast1.qq.com [54.204.34.129]) by mails.dpdk.org (Postfix) with ESMTP id 698A040DDD for ; Tue, 30 Sep 2025 12:01:00 +0200 (CEST) X-QQ-mid: esmtpgz13t1759226454t45342c0e X-QQ-Originating-IP: YARfIMQFnQuWZOILwSn4yay2gzB9V7jqeZmnFlYilDk= Received: from DSK-zaiyuwang.trustnetic.com ( [115.220.225.164]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 30 Sep 2025 18:00:53 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 12604399481257037751 EX-QQ-RecipientCnt: 4 From: Zaiyu Wang To: dev@dpdk.org Cc: Zaiyu Wang , Jiawen Wu , Jian Wang Subject: [PATCH v4 15/20] net/txgbe: add support for TX laser enable/disable Date: Tue, 30 Sep 2025 17:59:47 +0800 Message-Id: <20250930095953.18508-16-zaiyuwang@trustnetic.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20250930095953.18508-1-zaiyuwang@trustnetic.com> References: <20250418094131.24136-1-zaiyuwang@trustnetic.com> <20250930095953.18508-1-zaiyuwang@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:trustnetic.com:qybglogicsvrgz:qybglogicsvrgz5a-1 X-QQ-XMAILINFO: M7uElAZZZMmFLEvVcHfAKDYJFa8GJ9Xg40j+HCJClCSfsZb2VIlyJA3B I1Tp2eIknqaOBkn/HAnd0z6MHKomC0QFh7FKEc/jgFU7W3vLy+bbDgPSL9K5hmZBrhnlhl+ 5DGpJ3nBb+dc8Eu5ZC/1qSNUiayGUC3OcRvdbHViPnshkzdiPHfZmd3cYdyzoYjl83lcR/X v/bE0/3Kf4ElalNkbTXUwAqBoWgyyGtQg87xuTD0LHgEx607MAdsarWT8kGolYg8YdQ3hUo MAqAJZCcO9ywJv9qUjkMhqrKJShGpvEtL5/VE5xVcjbJoHLGEJVGM7h9NxAPzkYGSNnMkC6 vYDNd2bwcSBUHgy/Y/XR24WAbawMwNcN65FrwpFaD+/xB9Ersa7uornKn6cZRS0AgGTxWzw Lh8QsEqPPWVWxFp6l/OPssCu6W7saP3r8ZhNxYvohKxuR09NmE0TvmjCIeV8coTIHAr53wm glkz5CzrbgYe7c0KFx8jLJMGHEzhbDc/XsqhZxTp4iBcSToppv3hHJDS23ELu7A3aMve7FR vDQ1+u6gMOSEk2vLNe6CvgWsw9UlkM3CvuCBGcG8kfvqoRt0SV5y1na1JSJgecAR9eQHQBb eorknKQWD9LWXXPBAtgERYDimGISbLva2uEMrqG1Ew+RCeOb6+Di8ANmr2EiikTuerGQflT UsZ6SZEmPidlNMxC1LdUc2IovfQbHmwAmAxQV3N3qPpkvcRy9Imw6822JpO/KK12pf8Ruzx YGW91zN/IiAoydaZqWy8sA7pEX06/kvCfdrjLJl7+PIacFXs2jQnIn6w/tlON0lyk0cCTcR z7Koy9Geq2gOf+zviSEaY5xH0+KqXpdyF3w82JkLVSoWgEtioCX8IkYy+KUgeR30WjtzSQr 5XIC/SeUnaRQGA3BNlV7w9CUkKa0Q4+tdkONIgure3mKQ9ujDwAxLVQ00OYJFxWxw14BnsC 6BxVF2qq1S/gDtlIsVs8zYU/Mdl9xXS25rNbe6MqMClSrqfb7SHzKuFWerwTwkADsYIbN0m 4YDPz+X6BPF5DpqQiEMFyaeF9f99bKvOQo7+/Xqty9xRnl2GsdOMbsYm8QbbFu5L2VdRkLD Q== X-QQ-XMRINFO: MSVp+SPm3vtS1Vd6Y4Mggwc= X-QQ-RECHKSPAM: 0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add enable/disable TX laser configuration code for Amber-Lite NICs. Due to hardware design differences, the GPIO controlling the TX laser on Amber-Lite NICs differs from Sapphire NICs, requiring corresponding configuration changes. Signed-off-by: Zaiyu Wang --- drivers/net/txgbe/base/txgbe_hw.c | 31 ++++++++++++++++++++++++----- drivers/net/txgbe/base/txgbe_regs.h | 10 ++++++++++ 2 files changed, 36 insertions(+), 5 deletions(-) diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c index d845fd0a69..3cbb21a686 100644 --- a/drivers/net/txgbe/base/txgbe_hw.c +++ b/drivers/net/txgbe/base/txgbe_hw.c @@ -3179,12 +3179,28 @@ void txgbe_disable_tx_laser_multispeed_fiber(struct txgbe_hw *hw) { u32 esdp_reg = rd32(hw, TXGBE_GPIODATA); - if (txgbe_close_notify(hw)) - txgbe_led_off(hw, TXGBE_LEDCTL_UP | TXGBE_LEDCTL_10G | - TXGBE_LEDCTL_1G | TXGBE_LEDCTL_ACTIVE); + if (txgbe_close_notify(hw)) { + /* over write led when ifconfig down */ + if (hw->mac.type == txgbe_mac_aml40) { + txgbe_led_off(hw, TXGBE_LEDCTL_UP | TXGBE_AMLITE_LED_LINK_40G | + TXGBE_AMLITE_LED_LINK_ACTIVE); + } else if (hw->mac.type == txgbe_mac_aml) + txgbe_led_off(hw, TXGBE_LEDCTL_UP | TXGBE_AMLITE_LED_LINK_25G | + TXGBE_AMLITE_LED_LINK_10G | TXGBE_AMLITE_LED_LINK_ACTIVE); + else + txgbe_led_off(hw, TXGBE_LEDCTL_UP | TXGBE_LEDCTL_10G | + TXGBE_LEDCTL_1G | TXGBE_LEDCTL_ACTIVE); + } /* Disable Tx laser; allow 100us to go dark per spec */ - esdp_reg |= (TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1); + if (hw->mac.type == txgbe_mac_aml40) { + wr32m(hw, TXGBE_GPIODIR, TXGBE_GPIOBIT_1, TXGBE_GPIOBIT_1); + esdp_reg &= ~TXGBE_GPIOBIT_1; + } else if (hw->mac.type == txgbe_mac_aml) { + esdp_reg |= TXGBE_GPIOBIT_1; + } else { + esdp_reg |= (TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1); + } wr32(hw, TXGBE_GPIODATA, esdp_reg); txgbe_flush(hw); usec_delay(100); @@ -3206,7 +3222,12 @@ void txgbe_enable_tx_laser_multispeed_fiber(struct txgbe_hw *hw) wr32(hw, TXGBE_LEDCTL, 0); /* Enable Tx laser; allow 100ms to light up */ - esdp_reg &= ~(TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1); + if (hw->mac.type == txgbe_mac_aml40) { + wr32m(hw, TXGBE_GPIODIR, TXGBE_GPIOBIT_1, TXGBE_GPIOBIT_1); + esdp_reg |= TXGBE_GPIOBIT_1; + } else { + esdp_reg &= ~(TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1); + } wr32(hw, TXGBE_GPIODATA, esdp_reg); txgbe_flush(hw); msec_delay(100); diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h index 00c41a5b86..2e0ac9c742 100644 --- a/drivers/net/txgbe/base/txgbe_regs.h +++ b/drivers/net/txgbe/base/txgbe_regs.h @@ -302,6 +302,16 @@ #define TXGBE_PORT_LINK1000M MS(2, 0x1) #define TXGBE_PORT_LINK100M MS(3, 0x1) #define TXGBE_PORT_LANID(r) RS(r, 8, 0x1) +#define TXGBE_AMLITE_CFG_LED_CTL_LINK_BSY_SEL MS(5, 0x1) +#define TXGBE_AMLITE_CFG_LED_CTL_LINK_10G_SEL MS(4, 0x1) +#define TXGBE_AMLITE_CFG_LED_CTL_LINK_25G_SEL MS(3, 0x1) +#define TXGBE_AMLITE_CFG_LED_CTL_LINK_40G_SEL MS(2, 0x1) +#define TXGBE_AMLITE_CFG_LED_CTL_LINK_50G_SEL MS(1, 0x1) +#define TXGBE_AMLITE_LED_LINK_ACTIVE TXGBE_AMLITE_CFG_LED_CTL_LINK_BSY_SEL +#define TXGBE_AMLITE_LED_LINK_10G TXGBE_AMLITE_CFG_LED_CTL_LINK_10G_SEL +#define TXGBE_AMLITE_LED_LINK_25G TXGBE_AMLITE_CFG_LED_CTL_LINK_25G_SEL +#define TXGBE_AMLITE_LED_LINK_40G TXGBE_AMLITE_CFG_LED_CTL_LINK_40G_SEL +#define TXGBE_AMLITE_LED_LINK_50G TXGBE_AMLITE_CFG_LED_CTL_LINK_50G_SEL #define TXGBE_EXTAG 0x014408 #define TXGBE_EXTAG_ETAG_MASK MS(0, 0xFFFF) #define TXGBE_EXTAG_ETAG(v) LS(v, 0, 0xFFFF) From patchwork Tue Sep 30 09:59:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zaiyu Wang X-Patchwork-Id: 157129 X-Patchwork-Delegate: stephen@networkplumber.org Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C03A04886F; Tue, 30 Sep 2025 12:02:12 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D922340E37; Tue, 30 Sep 2025 12:01:05 +0200 (CEST) Received: from smtpbguseast3.qq.com (smtpbguseast3.qq.com [54.243.244.52]) by mails.dpdk.org (Postfix) with ESMTP id BEB1B40DDD for ; Tue, 30 Sep 2025 12:01:01 +0200 (CEST) X-QQ-mid: esmtpgz13t1759226457te634bb54 X-QQ-Originating-IP: bdr1u/el9YPtD4u0sjO44T0pGfNkYO8OAzsCa/kspT0= Received: from DSK-zaiyuwang.trustnetic.com ( [115.220.225.164]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 30 Sep 2025 18:00:56 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 16320697659879495577 EX-QQ-RecipientCnt: 4 From: Zaiyu Wang To: dev@dpdk.org Cc: Zaiyu Wang , Jiawen Wu , Jian Wang Subject: [PATCH v4 16/20] net/txgbe: add support for TX queue rate limiting Date: Tue, 30 Sep 2025 17:59:48 +0800 Message-Id: <20250930095953.18508-17-zaiyuwang@trustnetic.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20250930095953.18508-1-zaiyuwang@trustnetic.com> References: <20250418094131.24136-1-zaiyuwang@trustnetic.com> <20250930095953.18508-1-zaiyuwang@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:trustnetic.com:qybglogicsvrgz:qybglogicsvrgz5a-1 X-QQ-XMAILINFO: Nc7l3rjNm00Az1B8X9lnZ3Lrm8KSyv0wdQYgfOplW7xgxq4nyEVt1Kks O4uA9nS17OqL1zgsfz5cgXP617/6TC7kKowpIu8YtyYzm15JbSX1HPepWQgvBV30KWRMgqP oVc+9yxbP/WYJ1Ply6CY/r2rhj3fE5NghgKLCQMiqYCybvHNiwKPdHp9m94eTYqbBkR2gzP wjLW10o40ChbesztpqZCgCcPqYyOQd5Hg71rFpQEVq76KbPlDCXXIp30dU/26YrUvEZfuly Dg7MyCIglZxFgByzmJ75maKQe/wY42OQWtEZSrHeAM+uglB0cO4EVhy+5+K2qbzHfdceDbV XruWKodt9eBnASRa35tBBu5q4v4ATvTyeYWrLyHiP+62ExLG0Hxbc/WuQzoD3yqE6dCskar 28x+PFFG4WPjTheTCcDDGmxHMctVv5nCIywn92TLKn8K2nOss2kKlWzrp2xVtaJk4AS8eeB rwelSqfnlHfRk5do4Q5j6hKhpG0CCd+cNo+vW7z4aygaD+Z/PkZ1EaVlI90zslHc4ikB8U3 ZgjRM4dRf0lFmQq0sw9BgTp2+U+sJfW3fqlwMv255rJQh2+x8Bwk8PV1nIfc5o/60yHu/+X D31Y8I5j4oc9aRu1O57uxeSbaHqc4QQ6rCijF8fCJD8HedSoQtlAtqq4VGcpRZx1IfoqhGT nTFD44Zjb8GHbFShWOR43kAGRupoQeiOxMq0brFQ+QwkuG1R/qO2F3GBmabWlGGCHPq00nO b9n4vYtiLK0BeS/RKMNb38rjQED0vK+Co6i3YzFsIIttBQhkwN3wXwUkVuS4tsx0YmBCLt5 Y5ARN7Vgzbweyznqir1LewgCyCB9fThe3PbJeAExcLfXkj2gdtYmqXR1ZAL9Oah0Cjufaex EKzCLKkiryO1JvdgXr35w3RRS6YmiXgU0tr/SvOI2htgCQzv6Q73hfD6AtJGLtl6f84iNBS oArGF4JA7nwXTXKgYMI4fuKCJTfdloCcmLECoz9UzF9GT9jyNzir2PnabCAyOddQtyZy/xe 4pC+Msyv7eU46KJLKXLxDuQsim8HsWDE2hm2+RMHv0UJ5rxpdrNAnr0qtpGlg= X-QQ-XMRINFO: MSVp+SPm3vtS1Vd6Y4Mggwc= X-QQ-RECHKSPAM: 0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add TX queue rate limiting functionality for Amber-Lite NICs. Due to hardware design differences, the TX queue rate limiting configuration for Amber-Lite NICs requires updates compared to Sapphire NICs. Signed-off-by: Zaiyu Wang --- drivers/net/txgbe/base/txgbe_osdep.h | 2 + drivers/net/txgbe/base/txgbe_regs.h | 12 +++++ drivers/net/txgbe/txgbe_ethdev.c | 69 +++++++++++++++++++++++----- 3 files changed, 72 insertions(+), 11 deletions(-) diff --git a/drivers/net/txgbe/base/txgbe_osdep.h b/drivers/net/txgbe/base/txgbe_osdep.h index a1477653e2..f4282b3241 100644 --- a/drivers/net/txgbe/base/txgbe_osdep.h +++ b/drivers/net/txgbe/base/txgbe_osdep.h @@ -164,6 +164,8 @@ static inline u64 REVERT_BIT_MASK64(u64 mask) #define IOMEM +#define BIT(nr) (1UL << (nr)) + #define prefetch(x) rte_prefetch0(x) #define ARRAY_SIZE(x) ((int32_t)RTE_DIM(x)) diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h index 2e0ac9c742..f2e4994863 100644 --- a/drivers/net/txgbe/base/txgbe_regs.h +++ b/drivers/net/txgbe/base/txgbe_regs.h @@ -1656,6 +1656,18 @@ enum txgbe_5tuple_protocol { #define TXGBE_ARBTXRATE_MIN(v) LS(v, 0, 0x3FFF) #define TXGBE_ARBTXRATE_MAX(v) LS(v, 16, 0x3FFF) +#define TXGBE_TDM_RL_QUEUE_IDX 0x018210 +#define TXGBE_TDM_RL_QUEUE_CFG 0x018214 +#define TXGBE_TDM_FACTOR_INT_MASK MS(16, 0xFFFF) +#define TXGBE_TDM_FACTOR_FRA_MASK MS(0, 0xFFFC) +#define TXGBE_TDM_FACTOR_INT_SHIFT 16 +#define TXGBE_TDM_FACTOR_FRA_SHIFT 2 + +#define TXGBE_TDM_RL_VM_IDX 0x018218 +#define TXGBE_TDM_RL_VM_CFG 0x01821C +#define TXGBE_TDM_RL_CFG 0x018400 +#define TXGBE_TDM_RL_EN MS(0, 0x1) + /* qos */ #define TXGBE_ARBTXCTL 0x018200 #define TXGBE_ARBTXCTL_RRM MS(1, 0x1) diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c index e6694f7fc2..c7c3668066 100644 --- a/drivers/net/txgbe/txgbe_ethdev.c +++ b/drivers/net/txgbe/txgbe_ethdev.c @@ -4245,33 +4245,80 @@ txgbe_configure_msix(struct rte_eth_dev *dev) | TXGBE_ITR_WRDSA); } +static u16 txgbe_frac_to_bi(u16 frac, u16 denom, int max_bits) +{ + u16 value = 0; + + while (frac > 0 && max_bits > 0) { + max_bits -= 1; + frac *= 2; + if (frac >= denom) { + value |= BIT(max_bits); + frac -= denom; + } + } + + return value; +} + int txgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx, uint32_t tx_rate) { struct txgbe_hw *hw = TXGBE_DEV_HW(dev); uint32_t bcnrc_val; + int factor_int, factor_fra; + uint32_t link_speed; if (queue_idx >= hw->mac.max_tx_queues) return -EINVAL; - if (tx_rate != 0) { - bcnrc_val = TXGBE_ARBTXRATE_MAX(tx_rate); - bcnrc_val |= TXGBE_ARBTXRATE_MIN(tx_rate / 2); - } else { - bcnrc_val = 0; - } - /* * Set global transmit compensation time to the MMW_SIZE in ARBTXMMW * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. */ wr32(hw, TXGBE_ARBTXMMW, 0x14); - /* Set ARBTXRATE of queue X */ - wr32(hw, TXGBE_ARBPOOLIDX, queue_idx); - wr32(hw, TXGBE_ARBTXRATE, bcnrc_val); - txgbe_flush(hw); + if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) { + if (tx_rate) { + u16 frac; + + link_speed = dev->data->dev_link.link_speed; + tx_rate = tx_rate * 105 / 100; + /* Calculate the rate factor values to set */ + factor_int = link_speed / tx_rate; + frac = (link_speed % tx_rate) * 10000 / tx_rate; + factor_fra = txgbe_frac_to_bi(frac, 10000, 14); + if (tx_rate > link_speed) { + factor_int = 1; + factor_fra = 0; + } + + wr32(hw, TXGBE_TDM_RL_QUEUE_IDX, queue_idx); + wr32m(hw, TXGBE_TDM_RL_QUEUE_CFG, + TXGBE_TDM_FACTOR_INT_MASK, factor_int << TXGBE_TDM_FACTOR_INT_SHIFT); + wr32m(hw, TXGBE_TDM_RL_QUEUE_CFG, + TXGBE_TDM_FACTOR_FRA_MASK, factor_fra << TXGBE_TDM_FACTOR_FRA_SHIFT); + wr32m(hw, TXGBE_TDM_RL_QUEUE_CFG, + TXGBE_TDM_RL_EN, TXGBE_TDM_RL_EN); + } else { + wr32(hw, TXGBE_TDM_RL_QUEUE_IDX, queue_idx); + wr32m(hw, TXGBE_TDM_RL_QUEUE_CFG, + TXGBE_TDM_RL_EN, 0); + } + } else { + if (tx_rate != 0) { + bcnrc_val = TXGBE_ARBTXRATE_MAX(tx_rate); + bcnrc_val |= TXGBE_ARBTXRATE_MIN(tx_rate / 2); + } else { + bcnrc_val = 0; + } + + /* Set ARBTXRATE of queue X */ + wr32(hw, TXGBE_ARBPOOLIDX, queue_idx); + wr32(hw, TXGBE_ARBTXRATE, bcnrc_val); + txgbe_flush(hw); + } return 0; } From patchwork Tue Sep 30 09:59:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zaiyu Wang X-Patchwork-Id: 157130 X-Patchwork-Delegate: stephen@networkplumber.org Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 76AA54886F; Tue, 30 Sep 2025 12:02:19 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 25CA540E4F; Tue, 30 Sep 2025 12:01:07 +0200 (CEST) Received: from smtpbg150.qq.com (smtpbg150.qq.com [18.132.163.193]) by mails.dpdk.org (Postfix) with ESMTP id 39C3540E49 for ; Tue, 30 Sep 2025 12:01:04 +0200 (CEST) X-QQ-mid: esmtpgz13t1759226459tf17ea2af X-QQ-Originating-IP: /ofTs+cv0DGSbM5zUpoNQ4ryM6WaQwD8S6gDd8IIV3c= Received: from DSK-zaiyuwang.trustnetic.com ( [115.220.225.164]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 30 Sep 2025 18:00:58 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 14217161575231773427 EX-QQ-RecipientCnt: 4 From: Zaiyu Wang To: dev@dpdk.org Cc: Zaiyu Wang , Jiawen Wu , Jian Wang Subject: [PATCH v4 17/20] net/txgbe: add support for getting PHY ID Date: Tue, 30 Sep 2025 17:59:49 +0800 Message-Id: <20250930095953.18508-18-zaiyuwang@trustnetic.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20250930095953.18508-1-zaiyuwang@trustnetic.com> References: <20250418094131.24136-1-zaiyuwang@trustnetic.com> <20250930095953.18508-1-zaiyuwang@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:trustnetic.com:qybglogicsvrgz:qybglogicsvrgz5a-1 X-QQ-XMAILINFO: NgzJQeCZ3xJjFw/B/6LhnQPfRPgaZla4vKjMUq12KE9WqFRkqj1ZvQdu r+arbMjXuwsDfEhgQUb0VdkZA+4Bk9wu92kSzM3PFsoSvt8jBcXUQX7C3jZS4XgVHM36bg7 oesVgWlFJcY4Kp7EBxC+iicrnp1vfv7GlchjwtwSp07ut2QyNInXrpQYEbuyMpqPfzE8twP oFaq8z6W3ZivH2ZhM3aXNureRHy0RilVbwv9j29il9IDCybuPl+lMzM2A6HGZSuwkqyRoom 1Z3WZHyxNHIOSUex8MI8b34TI8sWzYfVrjUCE700t7akQ6Ej4XOoqFgPzjN336M83966oxH zEEYYbLYokuBqVjfHH1nMf7bXxJD61+8GFVyNh7lCKG5CGWa5aVVuKU1oqST0AVkjRV2epI 36FPep4o6ZwFEVzFHZKfyhVxrQPGw2Ju7tyTEo2pD7uuPy72BbRFKx5W1RSxspVf+njiDgS 6JKJRu9VvLJ8eHJ35qAeatA8exyZEbWKAWyDccEiTN1WyJsmh3utMP9WqP1m9WuXm8RSbgn afQuQfi1WDaZKhUu2D0KTpCOIpvNdXaNi8wEi7SFlk19i9Mx1rM/cH8X7oky47mjCNqEDw4 bIMDZuTsuhDSurgPCdeynftTKkbER3z/4BWMH8qo3eNYQjGd1poiBIluKctJvvmitePtjFK F7NTZ+IybfgncZ+nlPMfHwfiW5Qgc89ip86K9qXYPZwdxVw9rIC+p2By/ZHfJlu1vn7pI2/ aN8BEgIbfWjT12LjwXdwcnOJZTwxiGnKSCruYR8rCtMAz8LThyrqnayMvyfko9Ihk6hnBsu EqXInZ23VRbLJ9nqQgTHw8K1Y6ybCxZ3W21+QiOM4ZgUBdNsh2hN6DBSXNoOJkAStsv785m RNMQy5hTBYaJgIK9qddrRTvsCdzJZkGS4vb/A6R+Z7mWwKl8sDoyGZbNB7z1TLB2XV9l8Kb xwMLa2CGdL0yednGGHL3ZN3uUQsaqtwHUuI/CwTsN4wBLNxUqhs8WSG31Lxjz1FKxG2kHGQ v7Sy640MFHKvGkwiJG9Gz5N3rmXYbrhaOnKr6+Jcr9/D4Xf9u2crkdO2tXKs/DT36TWbhsH 37ncNdN+rrE X-QQ-XMRINFO: OD9hHCdaPRBwq3WW+NvGbIU= X-QQ-RECHKSPAM: 0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add PHY ID reading functionality for Amber-Lite NICs. Due to hardware design differences, the process for obtaining the PHY ID on Amber-Lite NICs differs from Sapphire NICs and requires additional delay handling. Signed-off-by: Zaiyu Wang --- drivers/net/txgbe/base/txgbe_phy.c | 35 ++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c index 81e9aee295..bf7260a295 100644 --- a/drivers/net/txgbe/base/txgbe_phy.c +++ b/drivers/net/txgbe/base/txgbe_phy.c @@ -173,6 +173,41 @@ s32 txgbe_get_phy_id(struct txgbe_hw *hw) u32 err; u16 phy_id_high = 0; u16 phy_id_low = 0; + u32 i = 0; + u32 status; + + if (hw->mac.type == txgbe_mac_aml) { + hw->phy.addr = 0; + + for (i = 0; i < 32; i++) { + hw->phy.addr = i; + status = txgbe_read_phy_reg_mdi(hw, TXGBE_MD_PHY_ID_HIGH, 0, &phy_id_high); + if (status) { + DEBUGOUT("txgbe_read_phy_reg_mdi failed 1"); + return status; + } + DEBUGOUT("%d: phy_id_high 0x%x", i, phy_id_high); + if ((phy_id_high & 0xFFFF) == 0x0141) + break; + } + + if (i == 32) { + DEBUGOUT("txgbe_read_phy_reg_mdi failed"); + return TXGBE_ERR_PHY; + } + + status = txgbe_read_phy_reg_mdi(hw, TXGBE_MD_PHY_ID_LOW, 0, &phy_id_low); + if (status) { + DEBUGOUT("txgbe_read_phy_reg_mdi failed 2"); + return status; + } + hw->phy.id = (u32)(phy_id_high & 0xFFFF) << 6; + hw->phy.id |= (u32)((phy_id_low & 0xFC00) >> 10); + + DEBUGOUT("phy_id 0x%x", hw->phy.id); + + return status; + } err = hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_HIGH, TXGBE_MD_DEV_PMA_PMD, From patchwork Tue Sep 30 09:59:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zaiyu Wang X-Patchwork-Id: 157131 X-Patchwork-Delegate: stephen@networkplumber.org Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 619B34886F; Tue, 30 Sep 2025 12:02:25 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 818BC40BA6; Tue, 30 Sep 2025 12:01:08 +0200 (CEST) Received: from smtpbgsg1.qq.com (smtpbgsg1.qq.com [54.254.200.92]) by mails.dpdk.org (Postfix) with ESMTP id 172A740E49 for ; Tue, 30 Sep 2025 12:01:05 +0200 (CEST) X-QQ-mid: esmtpgz13t1759226461tc6e16d2f X-QQ-Originating-IP: a92wwSbOnQMsXIhVE4thtFmNwaNZVPbbaoc9afWepxo= Received: from DSK-zaiyuwang.trustnetic.com ( [115.220.225.164]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 30 Sep 2025 18:01:00 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 6243097873924131335 EX-QQ-RecipientCnt: 4 From: Zaiyu Wang To: dev@dpdk.org Cc: Zaiyu Wang , Jiawen Wu , Jian Wang Subject: [PATCH v4 18/20] net/txgbe: add thermal sensor configuration for Amber-Lite NICs Date: Tue, 30 Sep 2025 17:59:50 +0800 Message-Id: <20250930095953.18508-19-zaiyuwang@trustnetic.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20250930095953.18508-1-zaiyuwang@trustnetic.com> References: <20250418094131.24136-1-zaiyuwang@trustnetic.com> <20250930095953.18508-1-zaiyuwang@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:trustnetic.com:qybglogicsvrgz:qybglogicsvrgz5a-1 X-QQ-XMAILINFO: OYMEOeTae7ml8FT4JGggEyTAwP78x0YL96ArpK3Q2RkkurCfsBxngI/u d4z1ECcq+mTDUBSZ6zaMBh0gdsCqCInRWDfg/V51ng2jAaGHeR6l0yr23Utaf4iBZdAbGsD vOpZUYjB5xJkl/6J1lLEVf7wUxtibp1GgknZpKlYCcoEPSHdkWkz4ffNwh3qtgXa4dfkafa crJjhgM9CQ3KCJZtFo7LEkUKyhwaD2rn+ZIEr3DZkIJcUHRxbFeLZk2kUjhkUUJcm5B+Fcf OD+s5CDyRQvUYYNrmocvWCL+x5gWCf1iKOXxZR6fKkr6AEQAvJZoxKJwyM29SjLxytCl9NB EqUlvEN4Iq0EvOB4N/LFGnpLm0rJt5CGp/0m/dv5eHT8sJzmpn+8sKCAdTDJPnCCk4GnrxC VxK2lSTu8mCk0sdAEqCLUG81r2L8teRSN5WKAi6Hc4/Krzotl1riJYsy0LKwa4wGMtv1a7q 5rHfiH2mKsnbmL9R1LwzTf6mEy8LoceSm07p8TKz7u8gg2DugOuitw4yRMKFqifEhN2MtVo bjK5bH+OjwKYetLR7cZEQrdgPVH5Imclo4Smw7x5QFp99UNjqMD/EUsILEUQuOHnn4q7zuU oQY7SgER8vVoV7ZlwG0cUBxCAJysjVVqU7Z7utAewMuTFEZHe1AcvwV/nrN+n/HjPp4clsI HATjV/gjDypaRXiGX5IwJYM1TjtK5iQIuJGXTzktLtJmdapvMQUZvhvbcgbhnROoBLGG21z Pvv1c/9B9dJvMwRE/VhrgLShpP4Cu1oh85n3mSF5k+Jgq28egBFVwqX/0IfDwqHsVhOkYKb 7edjCqT0xRuU6AOT0IZ/M8LFy4sKM/LFbEc3/PU4nJaE+QcJCs2R1ekkFMpCz8P4AO1+svQ r5ZrtI9OGqumRbms5j6joRaBz2M4/6HU9u1Jm3mhhvNVQ6Lb293QmYHkfPbd+Bllpp/eavV ZsDgcT37BhoQTbg0sv2J0Lju85lHDCKVlEXR30xhlYDge8PMdb4oGC44oWhLHD8qf+2RXMU Oa3lW0X3U4i+V1CN3vrKfBoVKPSHG9KRE18NWiTA== X-QQ-XMRINFO: Nq+8W0+stu50PRdwbJxPCL0= X-QQ-RECHKSPAM: 0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add thermal sensor configuration code for Amber-Lite NICs. Due to differences in hardware design, Amber-Lite NICs require different configuration from Sapphire NICs to initialize and retrieve thermal sensor data. Signed-off-by: Zaiyu Wang --- drivers/net/txgbe/base/txgbe_hw.c | 81 ++++++++++++++++++++++------- drivers/net/txgbe/base/txgbe_type.h | 27 ++++++++++ 2 files changed, 90 insertions(+), 18 deletions(-) diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c index 3cbb21a686..5017886896 100644 --- a/drivers/net/txgbe/base/txgbe_hw.c +++ b/drivers/net/txgbe/base/txgbe_hw.c @@ -2220,27 +2220,56 @@ void txgbe_clear_tx_pending(struct txgbe_hw *hw) * * Returns the thermal sensor data structure **/ +#define PHYINIT_TIMEOUT 1000 s32 txgbe_get_thermal_sensor_data(struct txgbe_hw *hw) { struct txgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; s64 tsv; u32 ts_stat; + u32 data_code; + int temp_data, temp_fraction; + int i = 0; /* Only support thermal sensors attached to physical port 0 */ if (hw->bus.lan_id != 0) return TXGBE_NOT_IMPLEMENTED; - ts_stat = rd32(hw, TXGBE_TSSTAT); - tsv = (s64)TXGBE_TSSTAT_DATA(ts_stat); - tsv = tsv > 1200 ? tsv : 1200; - tsv = -(48380 << 8) / 1000 - + tsv * (31020 << 8) / 100000 - - tsv * tsv * (18201 << 8) / 100000000 - + tsv * tsv * tsv * (81542 << 8) / 1000000000000 - - tsv * tsv * tsv * tsv * (16743 << 8) / 1000000000000000; - tsv >>= 8; + if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) { + wr32(hw, TXGBE_AML_TS_ENA, 0x0001); + + while (1) { + data_code = rd32(hw, TXGBE_AML_TS_STS); + if ((data_code & TXGBE_AML_TS_STS_VLD) != 0) + break; + msleep(1); + if (i++ > PHYINIT_TIMEOUT) { + PMD_DRV_LOG(ERR, "ERROR: Wait 0x1033c Timeout!!!"); + return -1; + } + } + + data_code = data_code & 0xFFF; + temp_data = 419400 + 2205 * (data_code * 1000 / 4094 - 500); - data->sensor[0].temp = (s16)tsv; + /* Change double Temperature to int */ + tsv = temp_data / 10000; + temp_fraction = temp_data - (tsv * 10000); + if (temp_fraction >= 5000) + tsv += 1; + data->sensor[0].temp = (s16)tsv; + } else { + ts_stat = rd32(hw, TXGBE_TSSTAT); + tsv = (s64)TXGBE_TSSTAT_DATA(ts_stat); + tsv = tsv > 1200 ? tsv : 1200; + tsv = -(48380 << 8) / 1000 + + tsv * (31020 << 8) / 100000 + - tsv * tsv * (18201 << 8) / 100000000 + + tsv * tsv * tsv * (81542 << 8) / 1000000000000 + - tsv * tsv * tsv * tsv * (16743 << 8) / 1000000000000000; + tsv >>= 8; + + data->sensor[0].temp = (s16)tsv; + } return 0; } @@ -2261,16 +2290,32 @@ s32 txgbe_init_thermal_sensor_thresh(struct txgbe_hw *hw) if (hw->bus.lan_id != 0) return TXGBE_NOT_IMPLEMENTED; - wr32(hw, TXGBE_TSCTRL, TXGBE_TSCTRL_EVALMD); - wr32(hw, TXGBE_TSINTR, - TXGBE_TSINTR_AEN | TXGBE_TSINTR_DEN); - wr32(hw, TXGBE_TSEN, TXGBE_TSEN_ENA); - - data->sensor[0].alarm_thresh = 100; - wr32(hw, TXGBE_TSATHRE, 677); data->sensor[0].dalarm_thresh = 90; - wr32(hw, TXGBE_TSDTHRE, 614); + + if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) { + wr32(hw, TXGBE_AML_TS_ENA, 0x0); + wr32(hw, TXGBE_AML_INTR_RAW_LO, TXGBE_AML_INTR_CL_LO); + wr32(hw, TXGBE_AML_INTR_RAW_HI, TXGBE_AML_INTR_CL_HI); + + wr32(hw, TXGBE_AML_INTR_HIGH_EN, TXGBE_AML_INTR_EN_HI); + wr32(hw, TXGBE_AML_INTR_LOW_EN, TXGBE_AML_INTR_EN_LO); + + wr32m(hw, TXGBE_AML_TS_CTL1, TXGBE_AML_EVAL_MODE_MASK, 0x10); + wr32m(hw, TXGBE_AML_TS_CTL1, TXGBE_AML_ALARM_THRE_MASK, 0x186a0000); + wr32m(hw, TXGBE_AML_TS_CTL1, TXGBE_AML_DALARM_THRE_MASK, 0x16f60); + wr32(hw, TXGBE_AML_TS_ENA, 0x1); + } else { + wr32(hw, TXGBE_TSCTRL, TXGBE_TSCTRL_EVALMD); + wr32(hw, TXGBE_TSINTR, + TXGBE_TSINTR_AEN | TXGBE_TSINTR_DEN); + wr32(hw, TXGBE_TSEN, TXGBE_TSEN_ENA); + + data->sensor[0].alarm_thresh = 100; + wr32(hw, TXGBE_TSATHRE, 677); + data->sensor[0].dalarm_thresh = 90; + wr32(hw, TXGBE_TSDTHRE, 614); + } return 0; } diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h index c5f51b3ade..07b443c2e0 100644 --- a/drivers/net/txgbe/base/txgbe_type.h +++ b/drivers/net/txgbe/base/txgbe_type.h @@ -37,6 +37,33 @@ #include "txgbe_osdep.h" #include "txgbe_devids.h" +/* Sensors for AMLITE PVT(Process Voltage Temperature) */ +#define TXGBE_AML_INTR_RAW_HI 0x10300 +#define TXGBE_AML_INTR_RAW_ME 0x10304 +#define TXGBE_AML_INTR_RAW_LO 0x10308 +#define TXGBE_AML_TS_CTL1 0x10330 +#define TXGBE_AML_TS_CTL2 0x10334 +#define TXGBE_AML_TS_ENA 0x10338 +#define TXGBE_AML_TS_STS 0x1033C +#define TXGBE_AML_INTR_HIGH_EN 0x10318 +#define TXGBE_AML_INTR_MED_EN 0x1031C +#define TXGBE_AML_INTR_LOW_EN 0x10320 +#define TXGBE_AML_INTR_HIGH_STS 0x1030C +#define TXGBE_AML_INTR_MED_STS 0x10310 +#define TXGBE_AML_INTR_LOW_STS 0x10314 + +#define TXGBE_AML_TS_STS_VLD 0x00001000U +#define TXGBE_AML_INTR_EN_HI 0x00000002U +#define TXGBE_AML_INTR_EN_ME 0x00000001U +#define TXGBE_AML_INTR_EN_LO 0x00000001U +#define TXGBE_AML_INTR_CL_HI 0x00000002U +#define TXGBE_AML_INTR_CL_ME 0x00000001U +#define TXGBE_AML_INTR_CL_LO 0x00000001U +#define TXGBE_AML_EVAL_MODE_MASK 0x00000010U +#define TXGBE_AML_CAL_MODE_MASK 0x00000008U +#define TXGBE_AML_ALARM_THRE_MASK 0x1FFE0000U +#define TXGBE_AML_DALARM_THRE_MASK 0x0001FFE0U + struct txgbe_thermal_diode_data { s16 temp; s16 alarm_thresh; From patchwork Tue Sep 30 09:59:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zaiyu Wang X-Patchwork-Id: 157132 X-Patchwork-Delegate: stephen@networkplumber.org Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 85FE94886F; Tue, 30 Sep 2025 12:02:33 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6318D40A67; Tue, 30 Sep 2025 12:01:12 +0200 (CEST) Received: from smtpbg154.qq.com (smtpbg154.qq.com [15.184.224.54]) by mails.dpdk.org (Postfix) with ESMTP id 712A240A6D for ; Tue, 30 Sep 2025 12:01:10 +0200 (CEST) X-QQ-mid: esmtpgz13t1759226464tedd72ce0 X-QQ-Originating-IP: +WQc+99DG+pKG9f4bDKnr0SoRQrb3wfLINY1PmXHPDI= Received: from DSK-zaiyuwang.trustnetic.com ( [115.220.225.164]) by bizesmtp.qq.com (ESMTP) with id ; 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The Amber-Lite NIC series provides comprehensive RSS support with hardware implementation identical to Sapphire NICs. This commit enables RSS by applying the existing RSS configuration directly to Amber-Lite NICs without requiring architectural changes. Signed-off-by: Zaiyu Wang --- drivers/net/txgbe/txgbe_ethdev.c | 7 +++++-- drivers/net/txgbe/txgbe_ethdev.h | 2 +- drivers/net/txgbe/txgbe_rxtx.c | 2 +- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c index c7c3668066..768a4b4997 100644 --- a/drivers/net/txgbe/txgbe_ethdev.c +++ b/drivers/net/txgbe/txgbe_ethdev.c @@ -3849,7 +3849,7 @@ txgbe_dev_rss_reta_update(struct rte_eth_dev *dev, PMD_INIT_FUNC_TRACE(); - if (!txgbe_rss_update_sp(hw->mac.type)) { + if (!txgbe_rss_update(hw->mac.type)) { PMD_DRV_LOG(ERR, "RSS reta update is not supported on this " "NIC."); return -ENOTSUP; @@ -5174,11 +5174,14 @@ txgbe_get_module_eeprom(struct rte_eth_dev *dev, } bool -txgbe_rss_update_sp(enum txgbe_mac_type mac_type) +txgbe_rss_update(enum txgbe_mac_type mac_type) { switch (mac_type) { case txgbe_mac_sp: case txgbe_mac_sp_vf: + case txgbe_mac_aml: + case txgbe_mac_aml40: + case txgbe_mac_aml_vf: return 1; default: return 0; diff --git a/drivers/net/txgbe/txgbe_ethdev.h b/drivers/net/txgbe/txgbe_ethdev.h index 9295d8fbd0..15fa888aa2 100644 --- a/drivers/net/txgbe/txgbe_ethdev.h +++ b/drivers/net/txgbe/txgbe_ethdev.h @@ -517,7 +517,7 @@ int txgbe_dev_rss_hash_update(struct rte_eth_dev *dev, int txgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, struct rte_eth_rss_conf *rss_conf); -bool txgbe_rss_update_sp(enum txgbe_mac_type mac_type); +bool txgbe_rss_update(enum txgbe_mac_type mac_type); int txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev, struct rte_eth_ntuple_filter *filter, diff --git a/drivers/net/txgbe/txgbe_rxtx.c b/drivers/net/txgbe/txgbe_rxtx.c index 957aa5c6eb..4110e7b681 100644 --- a/drivers/net/txgbe/txgbe_rxtx.c +++ b/drivers/net/txgbe/txgbe_rxtx.c @@ -3111,7 +3111,7 @@ txgbe_dev_rss_hash_update(struct rte_eth_dev *dev, uint64_t rss_hf; uint16_t i; - if (!txgbe_rss_update_sp(hw->mac.type)) { + if (!txgbe_rss_update(hw->mac.type)) { PMD_DRV_LOG(ERR, "RSS hash update is not supported on this " "NIC."); return -ENOTSUP; From patchwork Tue Sep 30 09:59:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zaiyu Wang X-Patchwork-Id: 157133 X-Patchwork-Delegate: stephen@networkplumber.org Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 610A74886F; Tue, 30 Sep 2025 12:02:39 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id ABE7840DCB; Tue, 30 Sep 2025 12:01:14 +0200 (CEST) Received: from smtpbguseast2.qq.com (smtpbguseast2.qq.com [54.204.34.130]) by mails.dpdk.org (Postfix) with ESMTP id 665A040ED3 for ; Tue, 30 Sep 2025 12:01:12 +0200 (CEST) X-QQ-mid: esmtpgz13t1759226466tf45d875d X-QQ-Originating-IP: ivnSXICBGpUW6OrFupakm+gpGl1Hzy6Sv2mK+qYXl+A= Received: from DSK-zaiyuwang.trustnetic.com ( [115.220.225.164]) by bizesmtp.qq.com (ESMTP) with id ; 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Signed-off-by: Zaiyu Wang --- doc/guides/nics/txgbe.rst | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/doc/guides/nics/txgbe.rst b/doc/guides/nics/txgbe.rst index 93fb592759..e7b657f9a0 100644 --- a/doc/guides/nics/txgbe.rst +++ b/doc/guides/nics/txgbe.rst @@ -4,8 +4,12 @@ TXGBE Poll Mode Driver ====================== -The TXGBE PMD (librte_pmd_txgbe) provides poll mode driver support -for Wangxun 10 Gigabit Ethernet NICs. +Supported NICs +-------------- + +- Wangxun 10 Gigabit Ethernet NICs +- Wangxun 25 Gigabit Ethernet NICs +- Wangxun 40 Gigabit Ethernet NICs Features --------