From patchwork Fri Aug 30 14:00:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sriharsha Basavapatna X-Patchwork-Id: 143465 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7D947458A8; Fri, 30 Aug 2024 15:51:09 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1969542E95; Fri, 30 Aug 2024 15:51:05 +0200 (CEST) Received: from mail-pl1-f195.google.com (mail-pl1-f195.google.com [209.85.214.195]) by mails.dpdk.org (Postfix) with ESMTP id 02994402D8 for ; Fri, 30 Aug 2024 15:51:03 +0200 (CEST) Received: by mail-pl1-f195.google.com with SMTP id d9443c01a7336-20223b5c1c0so17297235ad.2 for ; Fri, 30 Aug 2024 06:51:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1725025862; x=1725630662; darn=dpdk.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qnrlqimcdF/FxHoq41uAJefGaCja7NU+W3mUgmYJQr0=; b=ejwn1R9MVRvGmTyMVfHFrCvhipJe4xiSnQueRZw36GLbCAs0swwTEzKPgcdzEJcf2m 29S/c+d5K7emd9USeszPXAVpZLYeMiyZWnRl8M4B7gNGEDQo1+87n4+xLFvqOlNMfQjJ lTdndySwR1gJSYmZOmG52deLxy/q+xdsQ5P+g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1725025862; x=1725630662; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qnrlqimcdF/FxHoq41uAJefGaCja7NU+W3mUgmYJQr0=; b=sT1J66PNp/pssA1fnLEcLQy04NH3SrpRFPAMPNZfLBFYs1qH5/NmOxyYdX/dDJlmmV w9Rj14akMbYRj7yAl9iuQtH/yiHd4jBXo8l3c4gnH86XhhFLf8rpMSqKPoJtfTcmJUWq vywT/FzLsVe7L2MZcS26uSmiKnRrf6G2jToJL7koXdiN6MA222z2Aww+52jlcdplSHBE yTxj6fRqtyIiTyfDIhvFbkofUZZQnTnXYIAYmJCNWB4XSFFUJIitp8mZw52qVfqc9X25 unB/rPt9btv6gV9/5zwsGX3gI7GBD9PoLuWgtqxHkA0vSBVi+bKG4CiT3XCLECCuzPs2 K9aQ== X-Gm-Message-State: AOJu0YyZLJ7iZ21+tVxqAGRdhc1mvALvdoesIutMy+6dov2aeIFduGH6 HC4/YhFl1YkcU87lTfqNWapeYlCsEyYuLQ8N9aZ9L/YHyiYAI2XBjJTPkVxwnba8UIdDIFxsVou O0NydQMzXhNAYGwt9Zg7gjVJ9aVm/WszU3V9IU5AUkR3AKRzcrLipTjRJSdYM+IThb0mGvDqI9k rfSMVzn10xMYDJgty9ox8fafN3jMZ0Wnr+o09WmXQ0RvBJd1U= X-Google-Smtp-Source: AGHT+IGPDoj/bhDFgdYbpPTU0PtLdKrGcfaKoOPVNsL93pxZPYK62j2Wrm52xK958ZuazHSf0Nwajw== X-Received: by 2002:a17:902:cec8:b0:202:5af:47fc with SMTP id d9443c01a7336-2050c21967dmr75827515ad.13.1725025861566; Fri, 30 Aug 2024 06:51:01 -0700 (PDT) Received: from dhcp-10-123-154-23.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-205155658dfsm27067145ad.297.2024.08.30.06.50.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Aug 2024 06:51:01 -0700 (PDT) From: Sriharsha Basavapatna To: dev@dpdk.org Cc: Shahaji Bhosle , Randy Schacher , Kishore Padmanabha , Sriharsha Basavapatna Subject: [PATCH 01/47] net/bnxt: tf_core: fix wc tcam multi slice delete issue Date: Fri, 30 Aug 2024 19:30:03 +0530 Message-Id: <20240830140049.1715230-2-sriharsha.basavapatna@broadcom.com> X-Mailer: git-send-email 2.39.0.189.g4dbebc36b0 In-Reply-To: <20240830140049.1715230-1-sriharsha.basavapatna@broadcom.com> References: <20240830140049.1715230-1-sriharsha.basavapatna@broadcom.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shahaji Bhosle FW tries to update the HWRM request data in the delete case to update the mode bit and also update invalid profile id. This update only happens when the data is send over DMA. HWRM requests are read only buffers and cannot be updated. So driver now will always send WC tcam set message over DMA channel. Update tunnel alloc apis to provide error message. Fixes: ca5e61bd562d ("net/bnxt: support EM and TCAM lookup with table scope") Signed-off-by: Shahaji Bhosle Reviewed-by: Randy Schacher Reviewed-by: Kishore Padmanabha Signed-off-by: Sriharsha Basavapatna --- drivers/net/bnxt/tf_core/tf_msg.c | 28 +++++++++++----------- drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c | 18 ++++++++++++-- 2 files changed, 30 insertions(+), 16 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index 1c66c7e01a..4aa90f6b07 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -1612,20 +1612,20 @@ tf_msg_tcam_entry_set(struct tf *tfp, req.result_size = parms->result_size; data_size = 2 * req.key_size + req.result_size; - if (data_size <= TF_PCI_BUF_SIZE_MAX) { - /* use pci buffer */ - data = &req.dev_data[0]; - } else { - /* use dma buffer */ - req.flags |= HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA; - rc = tf_msg_alloc_dma_buf(&buf, data_size); - if (rc) - goto cleanup; - data = buf.va_addr; - tfp_memcpy(&req.dev_data[0], - &buf.pa_addr, - sizeof(buf.pa_addr)); - } + /* + * Always use dma buffer, as the delete multi slice + * tcam entries not support with HWRM request buffer + * only DMA'ed buffer can update the mode bits for + * the delete to work + */ + req.flags |= HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA; + rc = tf_msg_alloc_dma_buf(&buf, data_size); + if (rc) + goto cleanup; + data = buf.va_addr; + tfp_memcpy(&req.dev_data[0], + &buf.pa_addr, + sizeof(buf.pa_addr)); tfp_memcpy(&data[0], parms->key, parms->key_size); tfp_memcpy(&data[parms->key_size], parms->mask, parms->key_size); diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c index 96d61c3ed2..7e4952c062 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c @@ -32,9 +32,17 @@ bnxt_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port, uint8_t type) { - return bnxt_hwrm_tunnel_dst_port_alloc(bp, + int rc = 0; + rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, port, type); + if (rc) { + PMD_DRV_LOG(ERR, "Tunnel type:%d alloc failed for port:%d error:%s\n", + type, port, + (rc == HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_ALLOCATED) ? + "already allocated" : "no resource"); + } + return rc; } int @@ -589,7 +597,13 @@ bnxt_pmd_global_tunnel_set(uint16_t port_id, uint8_t type, } rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_port, hwtype); - if (!rc) { + if (rc) { + PMD_DRV_LOG(ERR, "Tunnel type:%d alloc failed for port:%d error:%s\n", + hwtype, udp_port, + (rc == + HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_ALLOCATED) ? + "already allocated" : "no resource"); + } else { ulp_global_tunnel_db[type].ref_cnt++; ulp_global_tunnel_db[type].dport = udp_port; bnxt_pmd_global_reg_data_to_hndl(port_id, bp->ecpri_upar_in_use, From patchwork Fri Aug 30 14:00:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sriharsha Basavapatna X-Patchwork-Id: 143466 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 23738458A8; Fri, 30 Aug 2024 15:51:17 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2D63D42E9D; Fri, 30 Aug 2024 15:51:07 +0200 (CEST) Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) by mails.dpdk.org (Postfix) with ESMTP id 88AD642E9B for ; Fri, 30 Aug 2024 15:51:05 +0200 (CEST) Received: by mail-pl1-f177.google.com with SMTP id d9443c01a7336-2020b730049so16768505ad.3 for ; Fri, 30 Aug 2024 06:51:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1725025864; x=1725630664; darn=dpdk.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yDoyMat/PNz+XyP8StqQe8jk8VIXQr8HGm4w3rSsbm4=; b=TbLz8XDj6qthDqW/ZufJn+RdyrsHN49VZXa5TmEw0juWfNMH0CAbJ0N/2/mujSHbst fwZKevspHEKRcGgwj9EwE2ewbJDqmzFIuE+Bg4j1KSELeSKczUfrCoQsDsJ9bZcWvLAE yhgUMEgd38182QChiuvtwuL5MV39TnUnKpMzs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1725025864; x=1725630664; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yDoyMat/PNz+XyP8StqQe8jk8VIXQr8HGm4w3rSsbm4=; b=iSVQW3ykTKq75yQ4T1LocKWCj6Gun7IM0WfzXzS//54V9hVtTFRB35T5hz2oUuOJQj 8hb/EWGK2zcPb9s9Mq+PPs3X2Z3u5zO0/1bFanRCkIoXzh0HUJjFmuZOrf+ddffCkKfF 6tQxdy/0CyRtcG1ZMox+4qM+wAxeP47+nmgSe6gdoO79tEjHeQTrUzfb+Rp8GEo0B8xP /w1DfnUnF/gRswotLyB0g/XNoUQA2zKZFdoJWaV+zmVLRcKWodEa6VaUQ7KMIB1l8ZC7 oYj+KSHIRm2BcPiS/hZxf71MbweaQ7nzKm+JOUMpMYCYOVtTCHXMl+cE7RPibxAJ1jOY 1iuw== X-Gm-Message-State: AOJu0YxtWASzjLQ0MsBKws8ixAZQMaVAjkzYuyaGhWxMWr1QvYGQ+Qw/ 2tXlyhXkd2iG3lLlOZg6brNbDnZvsGlIGdCGz6waVrbeu1HppTrJN1fSHG/3XrFcKPB44GbEI9Q 61z2n0P9IChEJSvBmjDwP01EIqK0LcuPsHTh9DPUm7ZyMGp9IqHy/nUuZ+ZY6Z1oCyGf3d4ujCS FxxUzyvMq9aztpybb0vFZ715MTFiBYeJkEHw6uoB7ViF4Q X-Google-Smtp-Source: AGHT+IHI6BfuahP3YeJXepek3jlkCwsbn4SnQO1V/dIxxCGo9XEdj6cuuyQW+hEZ1JbGFC7qnStd9A== X-Received: by 2002:a17:902:e804:b0:202:3107:e769 with SMTP id d9443c01a7336-2050c237fdfmr71175895ad.22.1725025864013; Fri, 30 Aug 2024 06:51:04 -0700 (PDT) Received: from dhcp-10-123-154-23.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-205155658dfsm27067145ad.297.2024.08.30.06.51.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Aug 2024 06:51:03 -0700 (PDT) From: Sriharsha Basavapatna To: dev@dpdk.org Cc: Shahaji Bhosle , Farah Smith , Kishore Padmanabha , Shuanglin Wang , Sriharsha Basavapatna Subject: [PATCH 02/47] net/bnxt: tf_core: tcam manager data corruption Date: Fri, 30 Aug 2024 19:30:04 +0530 Message-Id: <20240830140049.1715230-3-sriharsha.basavapatna@broadcom.com> X-Mailer: git-send-email 2.39.0.189.g4dbebc36b0 In-Reply-To: <20240830140049.1715230-1-sriharsha.basavapatna@broadcom.com> References: <20240830140049.1715230-1-sriharsha.basavapatna@broadcom.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shahaji Bhosle Max entries per session were not getting initialized to 0, when the sessions were closed. Reset max entries counter session when the session is initialized Fixes: 97435d7906d7 ("net/bnxt: update Truflow core") Signed-off-by: Shahaji Bhosle Reviewed-by: Farah Smith Reviewed-by: Kishore Padmanabha Reviewed-by: Shuanglin Wang Signed-off-by: Sriharsha Basavapatna --- drivers/net/bnxt/tf_core/cfa_tcam_mgr.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c index f26d93e7a9..9df2d2b937 100644 --- a/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c @@ -909,6 +909,7 @@ cfa_tcam_mgr_init(int sess_idx, enum cfa_tcam_mgr_device_type type, /* Now calculate the max entries per table and global max entries based * on the updated table limits. */ + cfa_tcam_mgr_max_entries[sess_idx] = 0; for (dir = 0; dir < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx]); dir++) for (tbl_type = 0; tbl_type < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx][dir]); @@ -958,8 +959,8 @@ cfa_tcam_mgr_init(int sess_idx, enum cfa_tcam_mgr_device_type type, if (parms != NULL) parms->max_entries = cfa_tcam_mgr_max_entries[sess_idx]; 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Fri, 30 Aug 2024 06:51:06 -0700 (PDT) Received: from dhcp-10-123-154-23.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-205155658dfsm27067145ad.297.2024.08.30.06.51.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Aug 2024 06:51:06 -0700 (PDT) From: Sriharsha Basavapatna To: dev@dpdk.org Cc: Shuanglin Wang , Shahaji Bhosle , Farah Smith , Sriharsha Basavapatna Subject: [PATCH 03/47] net/bnxt: tf_core: External EM support cleanup Date: Fri, 30 Aug 2024 19:30:05 +0530 Message-Id: <20240830140049.1715230-4-sriharsha.basavapatna@broadcom.com> X-Mailer: git-send-email 2.39.0.189.g4dbebc36b0 In-Reply-To: <20240830140049.1715230-1-sriharsha.basavapatna@broadcom.com> References: <20240830140049.1715230-1-sriharsha.basavapatna@broadcom.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shuanglin Wang Isolate external EM support as it is now defunct on Wh+. Signed-off-by: Shuanglin Wang Reviewed-by: Shahaji Bhosle Reviewed-by: Farah Smith Signed-off-by: Sriharsha Basavapatna --- drivers/net/bnxt/tf_core/meson.build | 2 - drivers/net/bnxt/tf_core/tf_core.h | 34 +- drivers/net/bnxt/tf_core/tf_device.c | 30 - drivers/net/bnxt/tf_core/tf_device_p4.c | 17 +- drivers/net/bnxt/tf_core/tf_device_p4.h | 1 + drivers/net/bnxt/tf_core/tf_device_p58.c | 6 +- drivers/net/bnxt/tf_core/tf_em.h | 361 +------ drivers/net/bnxt/tf_core/tf_em_common.c | 1191 ---------------------- drivers/net/bnxt/tf_core/tf_em_common.h | 1 + drivers/net/bnxt/tf_core/tf_em_host.c | 574 ----------- drivers/net/bnxt/tf_core/tf_msg.c | 465 --------- drivers/net/bnxt/tf_core/tf_tcam.c | 1 - 12 files changed, 71 insertions(+), 2612 deletions(-) diff --git a/drivers/net/bnxt/tf_core/meson.build b/drivers/net/bnxt/tf_core/meson.build index ae44aa34cf..13a71738a0 100644 --- a/drivers/net/bnxt/tf_core/meson.build +++ b/drivers/net/bnxt/tf_core/meson.build @@ -21,9 +21,7 @@ sources += files( 'tf_device.c', 'tf_device_p4.c', 'tf_device_p58.c', - 'tf_em_common.c', 'tf_em_hash_internal.c', - 'tf_em_host.c', 'tf_em_internal.c', 'tf_global_cfg.c', 'tf_hash.c', diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index 3da1d2a5ca..fd1ee2f454 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -21,9 +21,15 @@ /********** BEGIN Truflow Core DEFINITIONS **********/ +/** + * \cond DO_NOT_DOCUMENT + */ #define TF_KILOBYTE 1024 #define TF_MEGABYTE (1024 * 1024) +/** + * \endcond + */ /** * direction */ @@ -93,15 +99,19 @@ enum tf_sram_bank_id { * * Convert absolute offset to action record pointer in EEM record entry * Convert action record pointer in EEM record entry to absolute offset + * \cond DO_NOT_DOCUMENT */ #define TF_ACT_REC_OFFSET_2_PTR(offset) ((offset) >> 4) #define TF_ACT_REC_PTR_2_OFFSET(offset) ((offset) << 4) -/* +/** * Helper Macros */ #define TF_BITS_2_BYTES(num_bits) (((num_bits) + 7) / 8) +/** + * \endcond + */ /********** BEGIN API FUNCTION PROTOTYPES/PARAMETERS **********/ /** @@ -147,6 +157,8 @@ enum tf_sram_bank_id { * TruFlow session. Session ID is constructed from the passed in * ctrl_chan_name in tf_open_session() together with an allocated * fw_session_id. Done by TruFlow on tf_open_session(). + * + * \cond DO_NOT_DOCUMENT */ union tf_session_id { uint32_t id; @@ -172,6 +184,10 @@ union tf_session_client_id { uint8_t fw_session_client_id; } internal; }; +/** + * \endcond + */ + /** * Session Version @@ -181,12 +197,17 @@ union tf_session_client_id { * versions can be supported. * * Please see the TF_VER_MAJOR/MINOR and UPDATE defines. + * + * \cond DO_NOT_DOCUMENT */ struct tf_session_version { uint8_t major; uint8_t minor; uint8_t update; }; +/** + * \endcond + */ /** * Session supported device types @@ -485,6 +506,7 @@ struct tf_session_info { * * NOTE: This struct must be within the BNXT PMD struct bnxt * (bp). This allows use of container_of() to get access to the PMD. + * \cond DO_NOT_DOCUMENT */ struct tf { struct tf_session_info *session; @@ -493,6 +515,9 @@ struct tf { */ void *bp; }; +/** + * \endcond + */ /** * Identifier resource definition @@ -716,12 +741,15 @@ int tf_open_session(struct tf *tfp, /** * General internal resource info - * + * \cond DO_NOT_DOCUMENT */ struct tf_resource_info { uint16_t start; uint16_t stride; }; +/** + * \endcond + */ /** * Identifier resource definition @@ -2386,6 +2414,7 @@ struct tf_get_version_parms { /* [out] major * * Version Major number. + * \cond DO_NOT_DOCUMENT */ uint8_t major; @@ -2402,6 +2431,7 @@ struct tf_get_version_parms { uint8_t update; /** + * \endcond * [out] dev_ident_caps * * fw available identifier resource list diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c index 02a9ebd7b2..d023194d0c 100644 --- a/drivers/net/bnxt/tf_core/tf_device.c +++ b/drivers/net/bnxt/tf_core/tf_device.c @@ -153,28 +153,6 @@ tf_dev_bind_p4(struct tf *tfp, } no_rsv_flag = false; } - - /* - * EEM - */ - - em_cfg.cfg = tf_em_ext_p4; - rsv_cnt = tf_dev_reservation_check(TF_EM_TBL_TYPE_MAX, - em_cfg.cfg, - (uint16_t *)resources->em_cnt); - if (rsv_cnt) { - em_cfg.num_elements = TF_EM_TBL_TYPE_MAX; - em_cfg.resources = resources; - em_cfg.mem_type = TF_EEM_MEM_TYPE_HOST; - rc = tf_em_ext_common_bind(tfp, &em_cfg); - if (rc) { - TFP_DRV_LOG(ERR, - "EEM initialization failure\n"); - goto fail; - } - no_rsv_flag = false; - } - /* * EM */ @@ -294,14 +272,6 @@ tf_dev_unbind_p4(struct tf *tfp) "Device unbind failed, Table Type\n"); fail = true; } - - rc = tf_em_ext_common_unbind(tfp); - if (rc) { - TFP_DRV_LOG(INFO, - "Device unbind failed, EEM\n"); - fail = true; - } - rc = tf_em_int_unbind(tfp); if (rc) { TFP_DRV_LOG(INFO, diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index 911ea92471..4df1918bc5 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -15,6 +15,7 @@ #include "tf_if_tbl.h" #include "tfp.h" #include "tf_msg_common.h" +#include "tf_util.h" #define TF_DEV_P4_PARIF_MAX 16 #define TF_DEV_P4_PF_MASK 0xfUL @@ -528,13 +529,13 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_get_tbl_info = NULL, .tf_dev_is_sram_managed = tf_dev_p4_is_sram_managed, .tf_dev_alloc_tbl = tf_tbl_alloc, - .tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc, + .tf_dev_alloc_ext_tbl = NULL, .tf_dev_alloc_sram_tbl = tf_tbl_alloc, .tf_dev_free_tbl = tf_tbl_free, - .tf_dev_free_ext_tbl = tf_tbl_ext_free, + .tf_dev_free_ext_tbl = NULL, .tf_dev_free_sram_tbl = tf_tbl_free, .tf_dev_set_tbl = tf_tbl_set, - .tf_dev_set_ext_tbl = tf_tbl_ext_common_set, + .tf_dev_set_ext_tbl = NULL, .tf_dev_set_sram_tbl = NULL, .tf_dev_get_tbl = tf_tbl_get, .tf_dev_get_sram_tbl = NULL, @@ -551,13 +552,13 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_get_tcam_resc_info = tf_tcam_get_resc_info, .tf_dev_insert_int_em_entry = tf_em_insert_int_entry, .tf_dev_delete_int_em_entry = tf_em_delete_int_entry, - .tf_dev_insert_ext_em_entry = tf_em_insert_ext_entry, - .tf_dev_delete_ext_em_entry = tf_em_delete_ext_entry, + .tf_dev_insert_ext_em_entry = NULL, + .tf_dev_delete_ext_em_entry = NULL, .tf_dev_get_em_resc_info = tf_em_get_resc_info, - .tf_dev_alloc_tbl_scope = tf_em_ext_common_alloc, - .tf_dev_map_tbl_scope = tf_em_ext_map_tbl_scope, + .tf_dev_alloc_tbl_scope = NULL, + .tf_dev_map_tbl_scope = NULL, .tf_dev_map_parif = tf_dev_p4_map_parif, - .tf_dev_free_tbl_scope = tf_em_ext_common_free, + .tf_dev_free_tbl_scope = NULL, .tf_dev_set_if_tbl = tf_if_tbl_set, .tf_dev_get_if_tbl = tf_if_tbl_get, .tf_dev_set_global_cfg = tf_global_cfg_set, diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h index 20da2f97db..750e50f787 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.h +++ b/drivers/net/bnxt/tf_core/tf_device_p4.h @@ -11,6 +11,7 @@ #include "tf_rm.h" #include "tf_if_tbl.h" #include "tf_global_cfg.h" +#include "hcapi_cfa_defs.h" extern struct tf_rm_element_cfg tf_tbl_p4[TF_DIR_MAX][TF_TBL_TYPE_MAX]; diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 6916c50fdc..51c260b5d7 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -853,12 +853,12 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_get_tbl_info = tf_dev_p58_get_sram_tbl_info, .tf_dev_alloc_tbl = tf_tbl_alloc, .tf_dev_alloc_sram_tbl = tf_tbl_sram_alloc, - .tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc, + .tf_dev_alloc_ext_tbl = NULL, .tf_dev_free_tbl = tf_tbl_free, - .tf_dev_free_ext_tbl = tf_tbl_ext_free, + .tf_dev_free_ext_tbl = NULL, .tf_dev_free_sram_tbl = tf_tbl_sram_free, .tf_dev_set_tbl = tf_tbl_set, - .tf_dev_set_ext_tbl = tf_tbl_ext_common_set, + .tf_dev_set_ext_tbl = NULL, .tf_dev_set_sram_tbl = tf_tbl_sram_set, .tf_dev_get_tbl = tf_tbl_get, .tf_dev_get_sram_tbl = tf_tbl_sram_get, diff --git a/drivers/net/bnxt/tf_core/tf_em.h b/drivers/net/bnxt/tf_core/tf_em.h index 97cdb48f14..15f810521c 100644 --- a/drivers/net/bnxt/tf_core/tf_em.h +++ b/drivers/net/bnxt/tf_core/tf_em.h @@ -12,70 +12,11 @@ #include "hcapi_cfa_defs.h" -#define TF_EM_MIN_ENTRIES (1 << 15) /* 32K */ -#define TF_EM_MAX_ENTRIES (1 << 27) /* 128M */ - #define TF_P4_HW_EM_KEY_MAX_SIZE 52 #define TF_P4_EM_KEY_RECORD_SIZE 64 #define TF_P58_HW_EM_KEY_MAX_SIZE 80 -#define TF_EM_MAX_MASK 0x7FFF -#define TF_EM_MAX_ENTRY (128 * 1024 * 1024) - -/** - * Hardware Page sizes supported for EEM: - * 4K, 8K, 64K, 256K, 1M, 2M, 4M, 1G. - * - * Round-down other page sizes to the lower hardware page - * size supported. - */ -#define TF_EM_PAGE_SIZE_4K 12 -#define TF_EM_PAGE_SIZE_8K 13 -#define TF_EM_PAGE_SIZE_64K 16 -#define TF_EM_PAGE_SIZE_256K 18 -#define TF_EM_PAGE_SIZE_1M 20 -#define TF_EM_PAGE_SIZE_2M 21 -#define TF_EM_PAGE_SIZE_4M 22 -#define TF_EM_PAGE_SIZE_1G 30 - -/* Set page size */ -#define BNXT_TF_PAGE_SIZE TF_EM_PAGE_SIZE_2M - -#if (BNXT_TF_PAGE_SIZE == TF_EM_PAGE_SIZE_4K) /** 4K */ -#define TF_EM_PAGE_SHIFT TF_EM_PAGE_SIZE_4K -#define TF_EM_PAGE_SIZE_ENUM HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4K -#elif (BNXT_TF_PAGE_SIZE == TF_EM_PAGE_SIZE_8K) /** 8K */ -#define TF_EM_PAGE_SHIFT TF_EM_PAGE_SIZE_8K -#define TF_EM_PAGE_SIZE_ENUM HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8K -#elif (BNXT_TF_PAGE_SIZE == TF_EM_PAGE_SIZE_64K) /** 64K */ -#define TF_EM_PAGE_SHIFT TF_EM_PAGE_SIZE_64K -#define TF_EM_PAGE_SIZE_ENUM HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_64K -#elif (BNXT_TF_PAGE_SIZE == TF_EM_PAGE_SIZE_256K) /** 256K */ -#define TF_EM_PAGE_SHIFT TF_EM_PAGE_SIZE_256K -#define TF_EM_PAGE_SIZE_ENUM HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_256K -#elif (BNXT_TF_PAGE_SIZE == TF_EM_PAGE_SIZE_1M) /** 1M */ -#define TF_EM_PAGE_SHIFT TF_EM_PAGE_SIZE_1M -#define TF_EM_PAGE_SIZE_ENUM HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1M -#elif (BNXT_TF_PAGE_SIZE == TF_EM_PAGE_SIZE_2M) /** 2M */ -#define TF_EM_PAGE_SHIFT TF_EM_PAGE_SIZE_2M -#define TF_EM_PAGE_SIZE_ENUM HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_2M -#elif (BNXT_TF_PAGE_SIZE == TF_EM_PAGE_SIZE_4M) /** 4M */ -#define TF_EM_PAGE_SHIFT TF_EM_PAGE_SIZE_4M -#define TF_EM_PAGE_SIZE_ENUM HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4M -#elif (BNXT_TF_PAGE_SIZE == TF_EM_PAGE_SIZE_1G) /** 1G */ -#define TF_EM_PAGE_SHIFT TF_EM_PAGE_SIZE_1G -#define TF_EM_PAGE_SIZE_ENUM HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G -#else -#error "Invalid Page Size specified. Please use a TF_EM_PAGE_SIZE_n define" -#endif - -/* - * System memory always uses 4K pages - */ -#define TF_EM_PAGE_SIZE (1 << TF_EM_PAGE_SHIFT) -#define TF_EM_PAGE_ALIGNMENT (1 << TF_EM_PAGE_SHIFT) - /* * Used to build GFID: * @@ -90,16 +31,6 @@ #define TF_EM_INTERNAL_INDEX_MASK 0xFFFC #define TF_EM_INTERNAL_ENTRY_MASK 0x3 -/** EM Entry - * Each EM entry is 512-bit (64-bytes) but ordered differently to - * EEM. - */ -struct tf_em_64b_entry { - /** Header is 8 bytes long */ - struct cfa_p4_eem_entry_hdr hdr; - /** Key is 448 bits - 56 bytes */ - uint8_t key[TF_P4_EM_KEY_RECORD_SIZE - sizeof(struct cfa_p4_eem_entry_hdr)]; -}; /** EEM Memory Type * @@ -132,6 +63,17 @@ struct tf_em_cfg_parms { enum tf_mem_type mem_type; }; +/** EM Entry + * Each EM entry is 512-bit (64-bytes) but ordered differently to + * EEM. + */ +struct tf_em_64b_entry { + /** Header is 8 bytes long */ + struct cfa_p4_eem_entry_hdr hdr; + /** Key is 448 bits - 56 bytes */ + uint8_t key[TF_P4_EM_KEY_RECORD_SIZE - sizeof(struct cfa_p4_eem_entry_hdr)]; +}; + /** * EM database * @@ -153,29 +95,33 @@ struct em_rm_db { * * @ref tf_em_delete_int_entry * - * @ref tf_em_insert_ext_entry + * @ref tf_em_insert_ext_entry DEFUNCT * - * @ref tf_em_delete_ext_entry + * @ref tf_em_delete_ext_entry DEFUNCT * - * @ref tf_em_insert_ext_sys_entry + * @ref tf_em_insert_ext_sys_entry DEFUNCT * - * @ref tf_em_delete_ext_sys_entry + * @ref tf_em_delete_ext_sys_entry DEFUNCT * * @ref tf_em_int_bind * * @ref tf_em_int_unbind * - * @ref tf_em_ext_common_bind + * @ref tf_em_ext_common_bind DEFUNCT * - * @ref tf_em_ext_common_unbind + * @ref tf_em_ext_common_unbind DEFUNCT * - * @ref tf_em_ext_alloc + * @ref tf_em_ext_host_alloc DEFUNCT * - * @ref tf_em_ext_free + * @ref tf_em_ext_host_free DEFUNCT * - * @ref tf_em_ext_common_free + * @ref tf_em_ext_system_alloc DEFUNCT * - * @ref tf_em_ext_common_alloc + * @ref tf_em_ext_system_free DEFUNCT + * + * @ref tf_em_ext_common_free DEFUNCT + * + * @ref tf_em_ext_common_alloc DEFUNCT */ /** @@ -258,70 +204,6 @@ int tf_em_hash_delete_int_entry(struct tf *tfp, int tf_em_move_int_entry(struct tf *tfp, struct tf_move_em_entry_parms *parms); -/** - * Insert record in to external EEM table - * - * [in] tfp - * Pointer to TruFlow handle - * - * [in] parms - * Pointer to input parameters - * - * Returns: - * 0 - Success - * -EINVAL - Parameter error - */ -int tf_em_insert_ext_entry(struct tf *tfp, - struct tf_insert_em_entry_parms *parms); - -/** - * Insert record from external EEM table - * - * [in] tfp - * Pointer to TruFlow handle - * - * [in] parms - * Pointer to input parameters - * - * Returns: - * 0 - Success - * -EINVAL - Parameter error - */ -int tf_em_delete_ext_entry(struct tf *tfp, - struct tf_delete_em_entry_parms *parms); - -/** - * Insert record in to external system EEM table - * - * [in] tfp - * Pointer to TruFlow handle - * - * [in] parms - * Pointer to input parameters - * - * Returns: - * 0 - Success - * -EINVAL - Parameter error - */ -int tf_em_insert_ext_sys_entry(struct tf *tfp, - struct tf_insert_em_entry_parms *parms); - -/** - * Delete record from external system EEM table - * - * [in] tfp - * Pointer to TruFlow handle - * - * [in] parms - * Pointer to input parameters - * - * Returns: - * 0 - Success - * -EINVAL - Parameter error - */ -int tf_em_delete_ext_sys_entry(struct tf *tfp, - struct tf_delete_em_entry_parms *parms); - /** * Bind internal EM device interface * @@ -353,199 +235,6 @@ int tf_em_int_bind(struct tf *tfp, */ int tf_em_int_unbind(struct tf *tfp); -/** - * Common bind for EEM device interface. Used for both host and - * system memory - * - * [in] tfp - * Pointer to TruFlow handle - * - * [in] parms - * Pointer to input parameters - * - * Returns: - * 0 - Success - * -EINVAL - Parameter error - */ -int tf_em_ext_common_bind(struct tf *tfp, - struct tf_em_cfg_parms *parms); - -/** - * Common unbind for EEM device interface. Used for both host and - * system memory - * - * [in] tfp - * Pointer to TruFlow handle - * - * [in] parms - * Pointer to input parameters - * - * Returns: - * 0 - Success - * -EINVAL - Parameter error - */ -int tf_em_ext_common_unbind(struct tf *tfp); - -/** - * Alloc for external EEM using host memory - * - * [in] tfp - * Pointer to TruFlow handle - * - * [in] parms - * Pointer to input parameters - * - * Returns: - * 0 - Success - * -EINVAL - Parameter error - */ -int tf_em_ext_alloc(struct tf *tfp, - struct tf_alloc_tbl_scope_parms *parms); - -/** - * Free for external EEM using host memory - * - * [in] tfp - * Pointer to TruFlow handle - * - * [in] parms - * Pointer to input parameters - * - * Returns: - * 0 - Success - * -EINVAL - Parameter error - */ -int tf_em_ext_free(struct tf *tfp, - struct tf_free_tbl_scope_parms *parms); - -/** - * Common free table scope for external EEM using host or system memory - * - * [in] tfp - * Pointer to TruFlow handle - * - * [in] parms - * Pointer to input parameters - * - * Returns: - * 0 - Success - * -EINVAL - Parameter error - */ -int tf_em_ext_common_free(struct tf *tfp, - struct tf_free_tbl_scope_parms *parms); - -/** - * Common alloc table scope for external EEM using host or system memory - * - * [in] tfp - * Pointer to TruFlow handle - * - * [in] parms - * Pointer to input parameters - * - * Returns: - * 0 - Success - * -EINVAL - Parameter error - */ -int tf_em_ext_common_alloc(struct tf *tfp, - struct tf_alloc_tbl_scope_parms *parms); -/** - * Map a set of parifs to a set of EEM base addresses (table scope) - * - * [in] tfp - * Pointer to TruFlow handle - * - * [in] parms - * Pointer to input parameters - * - * Returns: - * 0 - Success - * -EINVAL - Parameter error - */ -int tf_em_ext_map_tbl_scope(struct tf *tfp, - struct tf_map_tbl_scope_parms *parms); - -/** - * Allocate External Tbl entry from the scope pool. - * - * [in] tfp - * Pointer to Truflow Handle - * [in] parms - * Allocation parameters - * - * Return: - * 0 - Success, entry allocated - no search support - * -ENOMEM -EINVAL -EOPNOTSUPP - * - Failure, entry not allocated, out of resources - */ -int -tf_tbl_ext_alloc(struct tf *tfp, - struct tf_tbl_alloc_parms *parms); - -/** - * Free External Tbl entry to the scope pool. - * - * [in] tfp - * Pointer to Truflow Handle - * [in] parms - * Allocation parameters - * - * Return: - * 0 - Success, entry freed - * - * - Failure, entry not successfully freed for these reasons - * -ENOMEM - * -EOPNOTSUPP - * -EINVAL - */ -int -tf_tbl_ext_free(struct tf *tfp, - struct tf_tbl_free_parms *parms); - -/** - * Sets the specified external table type element. - * - * This API sets the specified element data by invoking the - * firmware. - * - * [in] tfp - * Pointer to TF handle - * - * [in] parms - * Pointer to table set parameters - * - * Returns - * - (0) if successful. - * - (-EINVAL) on failure. - */ -int tf_tbl_ext_common_set(struct tf *tfp, - struct tf_tbl_set_parms *parms); - -/** - * Sets the specified external table type element. - * - * This API sets the specified element data by invoking the - * firmware. - * - * [in] tfp - * Pointer to TF handle - * - * [in] parms - * Pointer to table set parameters - * - * Returns - * - (0) if successful. - * - (-EINVAL) on failure. - */ -int tf_tbl_ext_set(struct tf *tfp, - struct tf_tbl_set_parms *parms); - -int -tf_em_ext_system_bind(struct tf *tfp, - struct tf_em_cfg_parms *parms); - -int offload_system_mmap(struct tf_tbl_scope_cb *tbl_scope_cb); - /** * Retrieves the allocated resource info * diff --git a/drivers/net/bnxt/tf_core/tf_em_common.c b/drivers/net/bnxt/tf_core/tf_em_common.c index c518150d1f..2449759db0 100644 --- a/drivers/net/bnxt/tf_core/tf_em_common.c +++ b/drivers/net/bnxt/tf_core/tf_em_common.c @@ -21,1194 +21,3 @@ #include "hcapi_cfa.h" #include "bnxt.h" -/** Invalid table scope id */ -#define TF_TBL_SCOPE_INVALID 0xffffffff - -/* Number of pointers per page_size */ -#define MAX_PAGE_PTRS(page_size) ((page_size) / sizeof(void *)) - -/** - * Host or system - */ -static enum tf_mem_type mem_type; - -/* API defined in tf_em.h */ -int -tf_create_tbl_pool_external(enum tf_dir dir, - struct tf_tbl_scope_cb *tbl_scope_cb, - uint32_t num_entries, - uint32_t entry_sz_bytes) -{ - struct tfp_calloc_parms parms; - uint32_t i; - int32_t j; - int rc = 0; - struct stack *pool = &tbl_scope_cb->ext_act_pool[dir]; - - parms.nitems = num_entries; - parms.size = sizeof(uint32_t); - parms.alignment = 0; - - if (tfp_calloc(&parms) != 0) { - TFP_DRV_LOG(ERR, "%s: TBL: external pool failure %s\n", - tf_dir_2_str(dir), strerror(ENOMEM)); - return -ENOMEM; - } - - /* Create empty stack - */ - rc = stack_init(num_entries, parms.mem_va, pool); - - if (rc != 0) { - TFP_DRV_LOG(ERR, "%s: TBL: stack init failure %s\n", - tf_dir_2_str(dir), strerror(-rc)); - goto cleanup; - } - - /* Save the malloced memory address so that it can - * be freed when the table scope is freed. - */ - tbl_scope_cb->ext_act_pool_mem[dir] = (uint32_t *)parms.mem_va; - - /* Fill pool with indexes in reverse - */ - j = (num_entries - 1) * entry_sz_bytes; - - for (i = 0; i < num_entries; i++) { - rc = stack_push(pool, j); - if (rc != 0) { - TFP_DRV_LOG(ERR, "%s TBL: stack failure %s\n", - tf_dir_2_str(dir), strerror(-rc)); - goto cleanup; - } - - if (j < 0) { - TFP_DRV_LOG(ERR, "%d TBL: invalid offset (%d)\n", - dir, j); - goto cleanup; - } - j -= entry_sz_bytes; - } - - if (!stack_is_full(pool)) { - rc = -EINVAL; - TFP_DRV_LOG(ERR, "%s TBL: stack failure %s\n", - tf_dir_2_str(dir), strerror(-rc)); - goto cleanup; - } - return 0; -cleanup: - tfp_free((void *)parms.mem_va); - return rc; -} - -/** - * Destroy External Tbl pool of memory indexes. - * - * [in] dir - * direction - * [in] tbl_scope_cb - * pointer to the table scope - */ -void -tf_destroy_tbl_pool_external(enum tf_dir dir, - struct tf_tbl_scope_cb *tbl_scope_cb) -{ - uint32_t *ext_act_pool_mem = - tbl_scope_cb->ext_act_pool_mem[dir]; - - tfp_free(ext_act_pool_mem); -} - -/** - * Looks up table scope control block using tbl_scope_id from tf_session. - * - * [in] tfp - * Pointer to Truflow Handle - * [in] tbl_scope_id - * table scope id - * - * Return: - * - Pointer to the tf_tbl_scope_cb, if found. - * - (NULL) on failure, not found. - */ -struct tf_tbl_scope_cb * -tf_em_ext_common_tbl_scope_find(struct tf *tfp, - uint32_t tbl_scope_id) -{ - int rc; - struct em_ext_db *ext_db; - void *ext_ptr = NULL; - struct tf_tbl_scope_cb *tbl_scope_cb = NULL; - struct ll_entry *entry; - - rc = tf_session_get_em_ext_db(tfp, &ext_ptr); - if (rc) - return NULL; - - ext_db = (struct em_ext_db *)ext_ptr; - - for (entry = ext_db->tbl_scope_ll.head; entry != NULL; - entry = entry->next) { - tbl_scope_cb = (struct tf_tbl_scope_cb *)entry; - if (tbl_scope_cb->tbl_scope_id == tbl_scope_id) - return tbl_scope_cb; - } - - return NULL; -} - -/** - * Allocate External Tbl entry from the scope pool. - * - * [in] tfp - * Pointer to Truflow Handle - * [in] parms - * Allocation parameters - * - * Return: - * 0 - Success, entry allocated - no search support - * -ENOMEM -EINVAL -EOPNOTSUPP - * - Failure, entry not allocated, out of resources - */ -int -tf_tbl_ext_alloc(struct tf *tfp, - struct tf_tbl_alloc_parms *parms) -{ - int rc; - uint32_t index; - struct tf_tbl_scope_cb *tbl_scope_cb; - struct stack *pool; - - TF_CHECK_PARMS2(tfp, parms); - - tbl_scope_cb = tf_em_ext_common_tbl_scope_find(tfp, parms->tbl_scope_id); - if (tbl_scope_cb == NULL) { - TFP_DRV_LOG(ERR, - "%s, table scope not allocated\n", - tf_dir_2_str(parms->dir)); - return -EINVAL; - } - - pool = &tbl_scope_cb->ext_act_pool[parms->dir]; - - /* Allocate an element - */ - rc = stack_pop(pool, &index); - - if (rc != 0) { - TFP_DRV_LOG(ERR, - "%s, Allocation failed, type:%d\n", - tf_dir_2_str(parms->dir), - parms->type); - return rc; - } - - *parms->idx = index; - return rc; -} - -/** - * Free External Tbl entry to the scope pool. - * - * [in] tfp - * Pointer to Truflow Handle - * [in] parms - * Allocation parameters - * - * Return: - * 0 - Success, entry freed - * - * - Failure, entry not successfully freed for these reasons - * -ENOMEM - * -EOPNOTSUPP - * -EINVAL - */ -int -tf_tbl_ext_free(struct tf *tfp, - struct tf_tbl_free_parms *parms) -{ - int rc = 0; - uint32_t index; - struct tf_tbl_scope_cb *tbl_scope_cb; - struct stack *pool; - - TF_CHECK_PARMS2(tfp, parms); - - tbl_scope_cb = tf_em_ext_common_tbl_scope_find(tfp, parms->tbl_scope_id); - if (tbl_scope_cb == NULL) { - TFP_DRV_LOG(ERR, - "%s, table scope error\n", - tf_dir_2_str(parms->dir)); - return -EINVAL; - } - pool = &tbl_scope_cb->ext_act_pool[parms->dir]; - - index = parms->idx; - - rc = stack_push(pool, index); - - if (rc != 0) { - TFP_DRV_LOG(ERR, - "%s, consistency error, stack full, type:%d, idx:%d\n", - tf_dir_2_str(parms->dir), - parms->type, - index); - } - return rc; -} - -uint32_t -tf_em_get_key_mask(int num_entries) -{ - uint32_t mask = num_entries - 1; - - if (num_entries & TF_EM_MAX_MASK) - return 0; - - if (num_entries > TF_EM_MAX_ENTRY) - return 0; - - return mask; -} - -void -tf_em_create_key_entry(struct cfa_p4_eem_entry_hdr *result, - uint8_t *in_key, - struct cfa_p4_eem_64b_entry *key_entry) -{ - key_entry->hdr.word1 = result->word1; - key_entry->hdr.pointer = result->pointer; - memcpy(key_entry->key, in_key, TF_P4_HW_EM_KEY_MAX_SIZE + 4); -} - -/** - * Return the number of page table pages needed to - * reference the given number of next level pages. - * - * [in] num_pages - * Number of EM pages - * - * [in] page_size - * Size of each EM page - * - * Returns: - * Number of EM page table pages - */ -static uint32_t -tf_em_page_tbl_pgcnt(uint32_t num_pages, - uint32_t page_size) -{ - return roundup(num_pages, MAX_PAGE_PTRS(page_size)) / - MAX_PAGE_PTRS(page_size); - return 0; -} - -/** - * Given the number of data pages, page_size and the maximum - * number of page table levels (already determined), size - * the number of page table pages required at each level. - * - * [in] max_lvl - * Max number of levels - * - * [in] num_data_pages - * Number of EM data pages - * - * [in] page_size - * Size of an EM page - * - * [out] *page_cnt - * EM page count - */ -static void -tf_em_size_page_tbls(int max_lvl, - uint64_t num_data_pages, - uint32_t page_size, - uint32_t *page_cnt) -{ - if (max_lvl == TF_PT_LVL_0) { - page_cnt[TF_PT_LVL_0] = num_data_pages; - } else if (max_lvl == TF_PT_LVL_1) { - page_cnt[TF_PT_LVL_1] = num_data_pages; - page_cnt[TF_PT_LVL_0] = - tf_em_page_tbl_pgcnt(page_cnt[TF_PT_LVL_1], page_size); - } else if (max_lvl == TF_PT_LVL_2) { - page_cnt[TF_PT_LVL_2] = num_data_pages; - page_cnt[TF_PT_LVL_1] = - tf_em_page_tbl_pgcnt(page_cnt[TF_PT_LVL_2], page_size); - page_cnt[TF_PT_LVL_0] = - tf_em_page_tbl_pgcnt(page_cnt[TF_PT_LVL_1], page_size); - } else { - return; - } -} - -/** - * Given the page size, size of each data item (entry size), - * and the total number of entries needed, determine the number - * of page table levels and the number of data pages required. - * - * [in] page_size - * Page size - * - * [in] entry_size - * Entry size - * - * [in] num_entries - * Number of entries needed - * - * [out] num_data_pages - * Number of pages required - * - * Returns: - * Success - Number of EM page levels required - * -ENOMEM - Out of memory - */ -static int -tf_em_size_page_tbl_lvl(uint32_t page_size, - uint32_t entry_size, - uint32_t num_entries, - uint64_t *num_data_pages) -{ - uint64_t lvl_data_size = page_size; - int lvl = TF_PT_LVL_0; - uint64_t data_size; - - *num_data_pages = 0; - data_size = (uint64_t)num_entries * entry_size; - - while (lvl_data_size < data_size) { - lvl++; - - if (lvl == TF_PT_LVL_1) - lvl_data_size = (uint64_t)MAX_PAGE_PTRS(page_size) * - page_size; - else if (lvl == TF_PT_LVL_2) - lvl_data_size = (uint64_t)MAX_PAGE_PTRS(page_size) * - MAX_PAGE_PTRS(page_size) * page_size; - else - return -ENOMEM; - } - - *num_data_pages = roundup(data_size, page_size) / page_size; - - return lvl; -} - -/** - * Size the EM table based on capabilities - * - * [in] tbl - * EM table to size - * - * Returns: - * 0 - Success - * - EINVAL - Parameter error - * - ENOMEM - Out of memory - */ -int -tf_em_size_table(struct hcapi_cfa_em_table *tbl, - uint32_t page_size) -{ - uint64_t num_data_pages; - uint32_t *page_cnt; - int max_lvl; - uint32_t num_entries; - uint32_t cnt = TF_EM_MIN_ENTRIES; - - /* Ignore entry if both size and number are zero */ - if (!tbl->entry_size && !tbl->num_entries) - return 0; - - /* If only one is set then error */ - if (!tbl->entry_size || !tbl->num_entries) - return -EINVAL; - - /* Determine number of page table levels and the number - * of data pages needed to process the given eem table. - */ - if (tbl->type == TF_RECORD_TABLE) { - /* - * For action records just a memory size is provided. Work - * backwards to resolve to number of entries - */ - num_entries = tbl->num_entries / tbl->entry_size; - if (num_entries < TF_EM_MIN_ENTRIES) { - num_entries = TF_EM_MIN_ENTRIES; - } else { - while (num_entries > cnt && cnt <= TF_EM_MAX_ENTRIES) - cnt *= 2; - num_entries = cnt; - } - } else { - num_entries = tbl->num_entries; - } - - max_lvl = tf_em_size_page_tbl_lvl(page_size, - tbl->entry_size, - tbl->num_entries, - &num_data_pages); - if (max_lvl < 0) { - TFP_DRV_LOG(WARNING, "EEM: Failed to size page table levels\n"); - TFP_DRV_LOG(WARNING, - "table: %d data-sz: %016" PRIu64 " page-sz: %u\n", - tbl->type, (uint64_t)num_entries * tbl->entry_size, - page_size); - return -ENOMEM; - } - - tbl->num_lvl = max_lvl + 1; - tbl->num_data_pages = num_data_pages; - - /* Determine the number of pages needed at each level */ - page_cnt = tbl->page_cnt; - memset(page_cnt, 0, sizeof(tbl->page_cnt)); - tf_em_size_page_tbls(max_lvl, num_data_pages, page_size, - page_cnt); - - TFP_DRV_LOG(INFO, "EEM: Sized page table: %d\n", tbl->type); - TFP_DRV_LOG(INFO, - "EEM: lvls: %d sz: %016" PRIu64 " pgs: %016" PRIu64 \ - " l0: %u l1: %u l2: %u\n", - max_lvl + 1, - (uint64_t)num_data_pages * page_size, - num_data_pages, - page_cnt[TF_PT_LVL_0], - page_cnt[TF_PT_LVL_1], - page_cnt[TF_PT_LVL_2]); - - return 0; -} - -/** - * Validates EM number of entries requested - * - * [in] tbl_scope_cb - * Pointer to table scope control block to be populated - * - * [in] parms - * Pointer to input parameters - * - * Returns: - * 0 - Success - * -EINVAL - Parameter error - */ -int -tf_em_validate_num_entries(struct tf_tbl_scope_cb *tbl_scope_cb, - struct tf_alloc_tbl_scope_parms *parms) -{ - uint32_t cnt; - - if (parms->rx_mem_size_in_mb != 0) { - uint32_t key_b = 2 * ((parms->rx_max_key_sz_in_bits / 8) + 1); - uint32_t action_b = ((parms->rx_max_action_entry_sz_in_bits / 8) - + 1); - uint32_t num_entries = (parms->rx_mem_size_in_mb * - TF_MEGABYTE) / (key_b + action_b); - - if (num_entries < TF_EM_MIN_ENTRIES) { - TFP_DRV_LOG(ERR, "EEM: Insufficient memory requested:" - "%uMB\n", - parms->rx_mem_size_in_mb); - return -EINVAL; - } - - cnt = TF_EM_MIN_ENTRIES; - while (num_entries > cnt && - cnt <= TF_EM_MAX_ENTRIES) - cnt *= 2; - - if (cnt > TF_EM_MAX_ENTRIES) { - TFP_DRV_LOG(ERR, "EEM: Invalid number of Tx requested: " - "%u\n", - (parms->tx_num_flows_in_k * TF_KILOBYTE)); - return -EINVAL; - } - - parms->rx_num_flows_in_k = cnt / TF_KILOBYTE; - } else { - if ((parms->rx_num_flows_in_k * TF_KILOBYTE) < - TF_EM_MIN_ENTRIES || - (parms->rx_num_flows_in_k * TF_KILOBYTE) > - tbl_scope_cb->em_caps[TF_DIR_RX].max_entries_supported) { - TFP_DRV_LOG(ERR, - "EEM: Invalid number of Rx flows " - "requested:%u max:%u\n", - parms->rx_num_flows_in_k * TF_KILOBYTE, - tbl_scope_cb->em_caps[TF_DIR_RX].max_entries_supported); - return -EINVAL; - } - - /* must be a power-of-2 supported value - * in the range 32K - 128M - */ - cnt = TF_EM_MIN_ENTRIES; - while ((parms->rx_num_flows_in_k * TF_KILOBYTE) != cnt && - cnt <= TF_EM_MAX_ENTRIES) - cnt *= 2; - - if (cnt > TF_EM_MAX_ENTRIES) { - TFP_DRV_LOG(ERR, - "EEM: Invalid number of Rx requested: %u\n", - (parms->rx_num_flows_in_k * TF_KILOBYTE)); - return -EINVAL; - } - } - - if (parms->tx_mem_size_in_mb != 0) { - uint32_t key_b = 2 * (parms->tx_max_key_sz_in_bits / 8 + 1); - uint32_t action_b = ((parms->tx_max_action_entry_sz_in_bits / 8) - + 1); - uint32_t num_entries = (parms->tx_mem_size_in_mb * - (TF_KILOBYTE * TF_KILOBYTE)) / - (key_b + action_b); - - if (num_entries < TF_EM_MIN_ENTRIES) { - TFP_DRV_LOG(ERR, - "EEM: Insufficient memory requested:%uMB\n", - parms->rx_mem_size_in_mb); - return -EINVAL; - } - - cnt = TF_EM_MIN_ENTRIES; - while (num_entries > cnt && - cnt <= TF_EM_MAX_ENTRIES) - cnt *= 2; - - if (cnt > TF_EM_MAX_ENTRIES) { - TFP_DRV_LOG(ERR, - "EEM: Invalid number of Tx requested: %u\n", - (parms->tx_num_flows_in_k * TF_KILOBYTE)); - return -EINVAL; - } - - parms->tx_num_flows_in_k = cnt / TF_KILOBYTE; - } else { - if ((parms->tx_num_flows_in_k * TF_KILOBYTE) < - TF_EM_MIN_ENTRIES || - (parms->tx_num_flows_in_k * TF_KILOBYTE) > - tbl_scope_cb->em_caps[TF_DIR_TX].max_entries_supported) { - TFP_DRV_LOG(ERR, - "EEM: Invalid number of Tx flows " - "requested:%u max:%u\n", - (parms->tx_num_flows_in_k * TF_KILOBYTE), - tbl_scope_cb->em_caps[TF_DIR_TX].max_entries_supported); - return -EINVAL; - } - - cnt = TF_EM_MIN_ENTRIES; - while ((parms->tx_num_flows_in_k * TF_KILOBYTE) != cnt && - cnt <= TF_EM_MAX_ENTRIES) - cnt *= 2; - - if (cnt > TF_EM_MAX_ENTRIES) { - TFP_DRV_LOG(ERR, - "EEM: Invalid number of Tx requested: %u\n", - (parms->tx_num_flows_in_k * TF_KILOBYTE)); - return -EINVAL; - } - } - - if (parms->rx_num_flows_in_k != 0 && - parms->rx_max_key_sz_in_bits / 8 == 0) { - TFP_DRV_LOG(ERR, - "EEM: Rx key size required: %u\n", - (parms->rx_max_key_sz_in_bits)); - return -EINVAL; - } - - if (parms->tx_num_flows_in_k != 0 && - parms->tx_max_key_sz_in_bits / 8 == 0) { - TFP_DRV_LOG(ERR, - "EEM: Tx key size required: %u\n", - (parms->tx_max_key_sz_in_bits)); - return -EINVAL; - } - /* Rx */ - tbl_scope_cb->em_ctx_info[TF_DIR_RX].em_tables[TF_KEY0_TABLE].num_entries = - parms->rx_num_flows_in_k * TF_KILOBYTE; - tbl_scope_cb->em_ctx_info[TF_DIR_RX].em_tables[TF_KEY0_TABLE].entry_size = - parms->rx_max_key_sz_in_bits / 8; - - tbl_scope_cb->em_ctx_info[TF_DIR_RX].em_tables[TF_KEY1_TABLE].num_entries = - parms->rx_num_flows_in_k * TF_KILOBYTE; - tbl_scope_cb->em_ctx_info[TF_DIR_RX].em_tables[TF_KEY1_TABLE].entry_size = - parms->rx_max_key_sz_in_bits / 8; - - tbl_scope_cb->em_ctx_info[TF_DIR_RX].em_tables[TF_RECORD_TABLE].num_entries = - parms->rx_num_flows_in_k * TF_KILOBYTE; - tbl_scope_cb->em_ctx_info[TF_DIR_RX].em_tables[TF_RECORD_TABLE].entry_size = - parms->rx_max_action_entry_sz_in_bits / 8; - - tbl_scope_cb->em_ctx_info[TF_DIR_RX].em_tables[TF_EFC_TABLE].num_entries = - 0; - - tbl_scope_cb->em_ctx_info[TF_DIR_RX].em_tables[TF_ACTION_TABLE].num_entries = - parms->rx_num_flows_in_k * TF_KILOBYTE; - tbl_scope_cb->em_ctx_info[TF_DIR_RX].em_tables[TF_ACTION_TABLE].entry_size = - parms->rx_max_action_entry_sz_in_bits / 8; - - tbl_scope_cb->em_ctx_info[TF_DIR_RX].em_tables[TF_EM_LKUP_TABLE].num_entries = - parms->rx_num_flows_in_k * TF_KILOBYTE; - tbl_scope_cb->em_ctx_info[TF_DIR_RX].em_tables[TF_EM_LKUP_TABLE].entry_size = - parms->rx_max_key_sz_in_bits / 8; - - /* Tx */ - tbl_scope_cb->em_ctx_info[TF_DIR_TX].em_tables[TF_KEY0_TABLE].num_entries = - parms->tx_num_flows_in_k * TF_KILOBYTE; - tbl_scope_cb->em_ctx_info[TF_DIR_TX].em_tables[TF_KEY0_TABLE].entry_size = - parms->tx_max_key_sz_in_bits / 8; - - tbl_scope_cb->em_ctx_info[TF_DIR_TX].em_tables[TF_KEY1_TABLE].num_entries = - parms->tx_num_flows_in_k * TF_KILOBYTE; - tbl_scope_cb->em_ctx_info[TF_DIR_TX].em_tables[TF_KEY1_TABLE].entry_size = - parms->tx_max_key_sz_in_bits / 8; - - tbl_scope_cb->em_ctx_info[TF_DIR_TX].em_tables[TF_RECORD_TABLE].num_entries = - parms->tx_num_flows_in_k * TF_KILOBYTE; - tbl_scope_cb->em_ctx_info[TF_DIR_TX].em_tables[TF_RECORD_TABLE].entry_size = - parms->tx_max_action_entry_sz_in_bits / 8; - - tbl_scope_cb->em_ctx_info[TF_DIR_TX].em_tables[TF_EFC_TABLE].num_entries = - 0; - - tbl_scope_cb->em_ctx_info[TF_DIR_TX].em_tables[TF_ACTION_TABLE].num_entries = - parms->rx_num_flows_in_k * TF_KILOBYTE; - tbl_scope_cb->em_ctx_info[TF_DIR_TX].em_tables[TF_ACTION_TABLE].entry_size = - parms->tx_max_action_entry_sz_in_bits / 8; - - tbl_scope_cb->em_ctx_info[TF_DIR_TX].em_tables[TF_EM_LKUP_TABLE].num_entries = - parms->rx_num_flows_in_k * TF_KILOBYTE; - tbl_scope_cb->em_ctx_info[TF_DIR_TX].em_tables[TF_EM_LKUP_TABLE].entry_size = - parms->tx_max_key_sz_in_bits / 8; - - return 0; -} - -/** insert EEM entry API - * - * returns: - * 0 - * TF_ERR - unable to get lock - * - * insert callback returns: - * 0 - * TF_ERR_EM_DUP - key is already in table - */ -static int -tf_insert_eem_entry(struct tf_dev_info *dev, - struct tf_tbl_scope_cb *tbl_scope_cb, - struct tf_insert_em_entry_parms *parms) -{ - uint32_t mask; - uint32_t key0_hash; - uint32_t key1_hash; - uint32_t key0_index; - uint32_t key1_index; - struct cfa_p4_eem_64b_entry key_entry; - uint32_t index; - enum hcapi_cfa_em_table_type table_type; - uint32_t gfid; - struct hcapi_cfa_hwop op; - struct hcapi_cfa_key_tbl key_tbl; - struct hcapi_cfa_key_data key_obj; - struct hcapi_cfa_key_loc key_loc; - uint64_t big_hash; - int rc; - - /* Get mask to use on hash */ - mask = tf_em_get_key_mask(tbl_scope_cb->em_ctx_info[parms->dir].em_tables[TF_KEY0_TABLE].num_entries); - - if (!mask) - return -EINVAL; - - if (dev->ops->tf_dev_cfa_key_hash == NULL) - return -EINVAL; - - big_hash = dev->ops->tf_dev_cfa_key_hash((uint64_t *)parms->key, - (TF_P4_HW_EM_KEY_MAX_SIZE + 4) * 8); - key0_hash = (uint32_t)(big_hash >> 32); - key1_hash = (uint32_t)(big_hash & 0xFFFFFFFF); - - key0_index = key0_hash & mask; - key1_index = key1_hash & mask; - - /* - * Use the "result" arg to populate all of the key entry then - * store the byte swapped "raw" entry in a local copy ready - * for insertion in to the table. - */ - tf_em_create_key_entry((struct cfa_p4_eem_entry_hdr *)parms->em_record, - ((uint8_t *)parms->key), - &key_entry); - - /* - * Try to add to Key0 table, if that does not work then - * try the key1 table. - */ - index = key0_index; - op.opcode = HCAPI_CFA_HWOPS_ADD; - key_tbl.base0 = - (uint8_t *)&tbl_scope_cb->em_ctx_info[parms->dir].em_tables[TF_KEY0_TABLE]; - key_tbl.page_size = TF_EM_PAGE_SIZE; - key_obj.offset = index * TF_P4_EM_KEY_RECORD_SIZE; - key_obj.data = (uint8_t *)&key_entry; - key_obj.size = TF_P4_EM_KEY_RECORD_SIZE; - - rc = cfa_p4_devops.hcapi_cfa_key_hw_op(&op, - &key_tbl, - &key_obj, - &key_loc); - - if (rc == 0) { - table_type = TF_KEY0_TABLE; - } else { - index = key1_index; - - key_tbl.base0 = - (uint8_t *)&tbl_scope_cb->em_ctx_info[parms->dir].em_tables[TF_KEY1_TABLE]; - key_obj.offset = index * TF_P4_EM_KEY_RECORD_SIZE; - - rc = cfa_p4_devops.hcapi_cfa_key_hw_op(&op, - &key_tbl, - &key_obj, - &key_loc); - if (rc != 0) - return rc; - - table_type = TF_KEY1_TABLE; - } - - TF_SET_GFID(gfid, - index, - table_type); - TF_SET_FLOW_ID(parms->flow_id, - gfid, - TF_GFID_TABLE_EXTERNAL, - parms->dir); - TF_SET_FIELDS_IN_FLOW_HANDLE(parms->flow_handle, - 0, - 0, - 0, - index, - 0, - table_type); - - return 0; -} - -/** delete EEM hash entry API - * - * returns: - * 0 - * -EINVAL - parameter error - * TF_NO_SESSION - bad session ID - * TF_ERR_TBL_SCOPE - invalid table scope - * TF_ERR_TBL_IF - invalid table interface - * - * insert callback returns - * 0 - * TF_NO_EM_MATCH - entry not found - */ -static int -tf_delete_eem_entry(struct tf_tbl_scope_cb *tbl_scope_cb, - struct tf_delete_em_entry_parms *parms) -{ - enum hcapi_cfa_em_table_type hash_type; - uint32_t index; - struct hcapi_cfa_hwop op; - struct hcapi_cfa_key_tbl key_tbl; - struct hcapi_cfa_key_data key_obj; - struct hcapi_cfa_key_loc key_loc; - int rc; - - TF_GET_HASH_TYPE_FROM_FLOW_HANDLE(parms->flow_handle, hash_type); - TF_GET_INDEX_FROM_FLOW_HANDLE(parms->flow_handle, index); - - op.opcode = HCAPI_CFA_HWOPS_DEL; - key_tbl.base0 = - (uint8_t *)&tbl_scope_cb->em_ctx_info[parms->dir].em_tables - [(hash_type == 0 ? TF_KEY0_TABLE : TF_KEY1_TABLE)]; - key_tbl.page_size = TF_EM_PAGE_SIZE; - key_obj.offset = index * TF_P4_EM_KEY_RECORD_SIZE; - key_obj.data = NULL; - key_obj.size = TF_P4_EM_KEY_RECORD_SIZE; - - rc = cfa_p4_devops.hcapi_cfa_key_hw_op(&op, - &key_tbl, - &key_obj, - &key_loc); - - if (!rc) - return rc; - - return 0; -} - -/** insert EM hash entry API - * - * returns: - * 0 - Success - * -EINVAL - Error - */ -int -tf_em_insert_ext_entry(struct tf *tfp, - struct tf_insert_em_entry_parms *parms) -{ - int rc; - struct tf_tbl_scope_cb *tbl_scope_cb; - struct tf_session *tfs; - struct tf_dev_info *dev; - - tbl_scope_cb = tf_em_ext_common_tbl_scope_find(tfp, parms->tbl_scope_id); - if (tbl_scope_cb == NULL) { - TFP_DRV_LOG(ERR, "Invalid tbl_scope_cb\n"); - return -EINVAL; - } - - /* Retrieve the session information */ - rc = tf_session_get_session_internal(tfp, &tfs); - if (rc) - return rc; - - /* Retrieve the device information */ - rc = tf_session_get_device(tfs, &dev); - if (rc) - return rc; - - return tf_insert_eem_entry - (dev, - tbl_scope_cb, - parms); -} - -/** Delete EM hash entry API - * - * returns: - * 0 - Success - * -EINVAL - Error - */ -int -tf_em_delete_ext_entry(struct tf *tfp, - struct tf_delete_em_entry_parms *parms) -{ - struct tf_tbl_scope_cb *tbl_scope_cb; - - tbl_scope_cb = tf_em_ext_common_tbl_scope_find(tfp, parms->tbl_scope_id); - if (tbl_scope_cb == NULL) { - TFP_DRV_LOG(ERR, "Invalid tbl_scope_cb\n"); - return -EINVAL; - } - - return tf_delete_eem_entry(tbl_scope_cb, parms); -} - -int -tf_em_ext_common_bind(struct tf *tfp, - struct tf_em_cfg_parms *parms) -{ - int rc; - int i; - struct tf_rm_create_db_parms db_cfg = { 0 }; - struct em_ext_db *ext_db; - struct tfp_calloc_parms cparms; - - TF_CHECK_PARMS2(tfp, parms); - - cparms.nitems = 1; - cparms.size = sizeof(struct em_ext_db); - cparms.alignment = 0; - if (tfp_calloc(&cparms) != 0) { - TFP_DRV_LOG(ERR, "em_ext_db alloc error %s\n", - strerror(ENOMEM)); - return -ENOMEM; - } - - ext_db = cparms.mem_va; - ll_init(&ext_db->tbl_scope_ll); - for (i = 0; i < TF_DIR_MAX; i++) - ext_db->eem_db[i] = NULL; - tf_session_set_em_ext_db(tfp, ext_db); - - db_cfg.module = TF_MODULE_TYPE_EM; - db_cfg.num_elements = parms->num_elements; - db_cfg.cfg = parms->cfg; - - for (i = 0; i < TF_DIR_MAX; i++) { - db_cfg.dir = i; - db_cfg.alloc_cnt = parms->resources->em_cnt[i].cnt; - - /* Check if we got any request to support EEM, if so - * we build an EM Ext DB holding Table Scopes. - */ - if (db_cfg.alloc_cnt[TF_EM_TBL_TYPE_TBL_SCOPE] == 0) - continue; - - db_cfg.rm_db = (void *)&ext_db->eem_db[i]; - rc = tf_rm_create_db(tfp, &db_cfg); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: EM Ext DB creation failed\n", - tf_dir_2_str(i)); - - return rc; - } - } - - mem_type = parms->mem_type; - - return 0; -} - -int -tf_em_ext_common_unbind(struct tf *tfp) -{ - int rc; - int i; - struct tf_rm_free_db_parms fparms = { 0 }; - struct em_ext_db *ext_db = NULL; - struct tf_session *tfs = NULL; - struct tf_dev_info *dev; - struct ll_entry *entry; - struct tf_tbl_scope_cb *tbl_scope_cb = NULL; - void *ext_ptr = NULL; - struct tf_free_tbl_scope_parms tparms = { 0 }; - - TF_CHECK_PARMS1(tfp); - - rc = tf_session_get_session_internal(tfp, &tfs); - if (rc) { - TFP_DRV_LOG(ERR, "Failed to get tf_session, rc:%s\n", - strerror(-rc)); - return rc; - } - - /* Retrieve the device information */ - rc = tf_session_get_device(tfs, &dev); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to lookup device, rc:%s\n", - strerror(-rc)); - return rc; - } - - rc = tf_session_get_em_ext_db(tfp, &ext_ptr); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to get em_ext_db from session, rc:%s\n", - strerror(-rc)); - return rc; - } - - ext_db = (struct em_ext_db *)ext_ptr; - if (ext_db != NULL) { - entry = ext_db->tbl_scope_ll.head; - while (entry != NULL) { - tbl_scope_cb = (struct tf_tbl_scope_cb *)entry; - entry = entry->next; - tparms.tbl_scope_id = - tbl_scope_cb->tbl_scope_id; - - if (dev->ops->tf_dev_free_tbl_scope) { - dev->ops->tf_dev_free_tbl_scope(tfp, - &tparms); - } else { - /* should not reach here */ - ll_delete(&ext_db->tbl_scope_ll, - &tbl_scope_cb->ll_entry); - tfp_free(tbl_scope_cb); - } - } - - for (i = 0; i < TF_DIR_MAX; i++) { - if (ext_db->eem_db[i] == NULL) - continue; - - fparms.dir = i; - fparms.rm_db = ext_db->eem_db[i]; - rc = tf_rm_free_db(tfp, &fparms); - if (rc) - return rc; - - ext_db->eem_db[i] = NULL; - } - - tfp_free(ext_db); - } - - tf_session_set_em_ext_db(tfp, NULL); - - return 0; -} - -/** - * Sets the specified external table type element. - * - * This API sets the specified element data - * - * [in] tfp - * Pointer to TF handle - * - * [in] parms - * Pointer to table set parameters - * - * Returns - * - (0) if successful. - * - (-EINVAL) on failure. - */ -int tf_tbl_ext_common_set(struct tf *tfp, - struct tf_tbl_set_parms *parms) -{ - int rc = 0; - struct tf_tbl_scope_cb *tbl_scope_cb; - uint32_t tbl_scope_id; - struct hcapi_cfa_hwop op; - struct hcapi_cfa_key_tbl key_tbl; - struct hcapi_cfa_key_data key_obj; - struct hcapi_cfa_key_loc key_loc; - - TF_CHECK_PARMS2(tfp, parms); - - if (parms->data == NULL) { - TFP_DRV_LOG(ERR, - "%s, invalid parms->data\n", - tf_dir_2_str(parms->dir)); - return -EINVAL; - } - - tbl_scope_id = parms->tbl_scope_id; - - if (tbl_scope_id == TF_TBL_SCOPE_INVALID) { - TFP_DRV_LOG(ERR, - "%s, Table scope not allocated\n", - tf_dir_2_str(parms->dir)); - return -EINVAL; - } - - tbl_scope_cb = tf_em_ext_common_tbl_scope_find(tfp, tbl_scope_id); - if (tbl_scope_cb == NULL) { - TFP_DRV_LOG(ERR, - "%s, table scope error\n", - tf_dir_2_str(parms->dir)); - return -EINVAL; - } - - op.opcode = HCAPI_CFA_HWOPS_PUT; - key_tbl.base0 = - (uint8_t *)&tbl_scope_cb->em_ctx_info[parms->dir].em_tables[TF_RECORD_TABLE]; - key_tbl.page_size = TF_EM_PAGE_SIZE; - key_obj.offset = parms->idx; - key_obj.data = parms->data; - key_obj.size = parms->data_sz_in_bytes; - - rc = cfa_p4_devops.hcapi_cfa_key_hw_op(&op, - &key_tbl, - &key_obj, - &key_loc); - - return rc; -} - -int -tf_em_ext_common_alloc(struct tf *tfp, - struct tf_alloc_tbl_scope_parms *parms) -{ - return tf_em_ext_alloc(tfp, parms); -} - -int -tf_em_ext_common_free(struct tf *tfp, - struct tf_free_tbl_scope_parms *parms) -{ - return tf_em_ext_free(tfp, parms); -} - -int tf_em_ext_map_tbl_scope(struct tf *tfp, - struct tf_map_tbl_scope_parms *parms) -{ - int rc = 0; - struct tf_session *tfs; - struct tf_tbl_scope_cb *tbl_scope_cb; - struct tf_global_cfg_parms gcfg_parms = { 0 }; - struct tfp_calloc_parms aparms; - uint32_t *data, *mask; - uint32_t sz_in_bytes = 8; - struct tf_dev_info *dev; - - /* Retrieve the session information */ - rc = tf_session_get_session_internal(tfp, &tfs); - if (rc) - return rc; - - /* Retrieve the device information */ - rc = tf_session_get_device(tfs, &dev); - if (rc) - return rc; - - tbl_scope_cb = tf_em_ext_common_tbl_scope_find(tfp, parms->tbl_scope_id); - if (tbl_scope_cb == NULL) { - TFP_DRV_LOG(ERR, "Invalid tbl_scope_cb tbl_scope_id(%d)\n", - parms->tbl_scope_id); - return -EINVAL; - } - - if (dev->ops->tf_dev_map_tbl_scope == NULL) { - rc = -EOPNOTSUPP; - TFP_DRV_LOG(ERR, - "Map table scope operation not supported, rc:%s\n", - strerror(-rc)); - return rc; - } - - aparms.nitems = 2; - aparms.size = sizeof(uint32_t); - aparms.alignment = 0; - - if (tfp_calloc(&aparms) != 0) { - TFP_DRV_LOG(ERR, "Map tbl scope alloc data error %s\n", - strerror(ENOMEM)); - return -ENOMEM; - } - data = aparms.mem_va; - - if (tfp_calloc(&aparms) != 0) { - TFP_DRV_LOG(ERR, "Map tbl scope alloc mask error %s\n", - strerror(ENOMEM)); - rc = -ENOMEM; - goto clean; - } - mask = aparms.mem_va; - - rc = dev->ops->tf_dev_map_parif(tfp, parms->parif_bitmask, - tbl_scope_cb->pf, - (uint8_t *)data, (uint8_t *)mask, - sz_in_bytes); - - if (rc) { - TFP_DRV_LOG(ERR, - "Map table scope config failure, rc:%s\n", - strerror(-rc)); - goto cleaner; - } - - /* Note that TF_GLOBAL_CFG_INTERNAL_PARIF_2_PF is same as below enum */ - gcfg_parms.type = TF_GLOBAL_CFG_TYPE_MAX; - gcfg_parms.offset = 0; - gcfg_parms.config = (uint8_t *)data; - gcfg_parms.config_mask = (uint8_t *)mask; - gcfg_parms.config_sz_in_bytes = sizeof(uint64_t); - - rc = tf_msg_set_global_cfg(tfp, &gcfg_parms); - if (rc) { - TFP_DRV_LOG(ERR, - "Map tbl scope, set failed, rc:%s\n", - strerror(-rc)); - } -cleaner: - tfp_free(mask); -clean: - tfp_free(data); - - return rc; -} diff --git a/drivers/net/bnxt/tf_core/tf_em_common.h b/drivers/net/bnxt/tf_core/tf_em_common.h index 0ae95f260a..3625673952 100644 --- a/drivers/net/bnxt/tf_core/tf_em_common.h +++ b/drivers/net/bnxt/tf_core/tf_em_common.h @@ -6,6 +6,7 @@ #ifndef _TF_EM_COMMON_H_ #define _TF_EM_COMMON_H_ +#include "hcapi_cfa_defs.h" #include "tf_core.h" #include "tf_session.h" #include "ll.h" diff --git a/drivers/net/bnxt/tf_core/tf_em_host.c b/drivers/net/bnxt/tf_core/tf_em_host.c index 9efffe4ee5..6db0057b2c 100644 --- a/drivers/net/bnxt/tf_core/tf_em_host.c +++ b/drivers/net/bnxt/tf_core/tf_em_host.c @@ -21,577 +21,3 @@ #include "tf_ext_flow_handle.h" #include "bnxt.h" - -#define PTU_PTE_VALID 0x1UL -#define PTU_PTE_LAST 0x2UL -#define PTU_PTE_NEXT_TO_LAST 0x4UL - -/* Number of pointers per page_size */ -#define MAX_PAGE_PTRS(page_size) ((page_size) / sizeof(void *)) - -/** - * Function to free a page table - * - * [in] tp - * Pointer to the page table to free - */ -static void -tf_em_free_pg_tbl(struct hcapi_cfa_em_page_tbl *tp) -{ - uint32_t i; - - for (i = 0; i < tp->pg_count; i++) { - if (!tp->pg_va_tbl[i]) { - TFP_DRV_LOG(WARNING, - "No mapping for page: %d table: %016" PRIu64 "\n", - i, - (uint64_t)(uintptr_t)tp); - continue; - } - - tfp_free(tp->pg_va_tbl[i]); - tp->pg_va_tbl[i] = NULL; - } - - tp->pg_count = 0; - tfp_free(tp->pg_va_tbl); - tp->pg_va_tbl = NULL; - tfp_free(tp->pg_pa_tbl); - tp->pg_pa_tbl = NULL; -} - -/** - * Function to free an EM table - * - * [in] tbl - * Pointer to the EM table to free - */ -static void -tf_em_free_page_table(struct hcapi_cfa_em_table *tbl) -{ - struct hcapi_cfa_em_page_tbl *tp; - int i; - - for (i = 0; i < tbl->num_lvl; i++) { - tp = &tbl->pg_tbl[i]; - TFP_DRV_LOG(INFO, - "EEM: Freeing page table: size %u lvl %d cnt %u\n", - TF_EM_PAGE_SIZE, - i, - tp->pg_count); - - tf_em_free_pg_tbl(tp); - } - - tbl->l0_addr = NULL; - tbl->l0_dma_addr = 0; - tbl->num_lvl = 0; - tbl->num_data_pages = 0; -} - -/** - * Allocation of page tables - * - * [in] tfp - * Pointer to a TruFlow handle - * - * [in] pg_count - * Page count to allocate - * - * [in] pg_size - * Size of each page - * - * Returns: - * 0 - Success - * -ENOMEM - Out of memory - */ -static int -tf_em_alloc_pg_tbl(struct hcapi_cfa_em_page_tbl *tp, - uint32_t pg_count, - uint32_t pg_size) -{ - uint32_t i; - struct tfp_calloc_parms parms; - - parms.nitems = pg_count; - parms.size = sizeof(void *); - parms.alignment = 0; - - if (tfp_calloc(&parms) != 0) - return -ENOMEM; - - tp->pg_va_tbl = parms.mem_va; - - if (tfp_calloc(&parms) != 0) { - tfp_free(tp->pg_va_tbl); - return -ENOMEM; - } - - tp->pg_pa_tbl = parms.mem_va; - - tp->pg_count = 0; - tp->pg_size = pg_size; - - for (i = 0; i < pg_count; i++) { - parms.nitems = 1; - parms.size = pg_size; - parms.alignment = TF_EM_PAGE_ALIGNMENT; - - if (tfp_calloc(&parms) != 0) - goto cleanup; - - tp->pg_pa_tbl[i] = (uintptr_t)parms.mem_pa; - tp->pg_va_tbl[i] = parms.mem_va; - - memset(tp->pg_va_tbl[i], 0, pg_size); - tp->pg_count++; - } - - return 0; - -cleanup: - tf_em_free_pg_tbl(tp); - return -ENOMEM; -} - -/** - * Allocates EM page tables - * - * [in] tbl - * Table to allocate pages for - * - * Returns: - * 0 - Success - * -ENOMEM - Out of memory - */ -static int -tf_em_alloc_page_table(struct hcapi_cfa_em_table *tbl) -{ - struct hcapi_cfa_em_page_tbl *tp; - int rc = 0; - int i; - uint32_t j; - - for (i = 0; i < tbl->num_lvl; i++) { - tp = &tbl->pg_tbl[i]; - - rc = tf_em_alloc_pg_tbl(tp, - tbl->page_cnt[i], - TF_EM_PAGE_SIZE); - if (rc) { - TFP_DRV_LOG(WARNING, - "Failed to allocate page table: lvl: %d, rc:%s\n", - i, - strerror(-rc)); - goto cleanup; - } - - for (j = 0; j < tp->pg_count; j++) { - TFP_DRV_LOG(INFO, - "EEM: Allocated page table: size %u lvl %d cnt" - " %u VA:%p PA:%p\n", - TF_EM_PAGE_SIZE, - i, - tp->pg_count, - (void *)(uintptr_t)tp->pg_va_tbl[j], - (void *)(uintptr_t)tp->pg_pa_tbl[j]); - } - } - return rc; - -cleanup: - tf_em_free_page_table(tbl); - return rc; -} - -/** - * Links EM page tables - * - * [in] tp - * Pointer to page table - * - * [in] tp_next - * Pointer to the next page table - * - * [in] set_pte_last - * Flag controlling if the page table is last - */ -static void -tf_em_link_page_table(struct hcapi_cfa_em_page_tbl *tp, - struct hcapi_cfa_em_page_tbl *tp_next, - bool set_pte_last) -{ - uint64_t *pg_pa = tp_next->pg_pa_tbl; - uint64_t *pg_va; - uint64_t valid; - uint32_t k = 0; - uint32_t i; - uint32_t j; - - for (i = 0; i < tp->pg_count; i++) { - pg_va = tp->pg_va_tbl[i]; - - for (j = 0; j < MAX_PAGE_PTRS(tp->pg_size); j++) { - if (k == tp_next->pg_count - 2 && set_pte_last) - valid = PTU_PTE_NEXT_TO_LAST | PTU_PTE_VALID; - else if (k == tp_next->pg_count - 1 && set_pte_last) - valid = PTU_PTE_LAST | PTU_PTE_VALID; - else - valid = PTU_PTE_VALID; - - pg_va[j] = tfp_cpu_to_le_64(pg_pa[k] | valid); - if (++k >= tp_next->pg_count) - return; - } - } -} - -/** - * Setup a EM page table - * - * [in] tbl - * Pointer to EM page table - */ -static void -tf_em_setup_page_table(struct hcapi_cfa_em_table *tbl) -{ - struct hcapi_cfa_em_page_tbl *tp_next; - struct hcapi_cfa_em_page_tbl *tp; - bool set_pte_last = 0; - int i; - - for (i = 0; i < tbl->num_lvl - 1; i++) { - tp = &tbl->pg_tbl[i]; - tp_next = &tbl->pg_tbl[i + 1]; - if (i == tbl->num_lvl - 2) - set_pte_last = 1; - tf_em_link_page_table(tp, tp_next, set_pte_last); - } - - tbl->l0_addr = tbl->pg_tbl[TF_PT_LVL_0].pg_va_tbl[0]; - tbl->l0_dma_addr = tbl->pg_tbl[TF_PT_LVL_0].pg_pa_tbl[0]; -} - -/** - * Unregisters EM Ctx in Firmware - * - * [in] tfp - * Pointer to a TruFlow handle - * - * [in] tbl_scope_cb - * Pointer to a table scope control block - * - * [in] dir - * Receive or transmit direction - */ -static void -tf_em_ctx_unreg(struct tf *tfp, - struct tf_tbl_scope_cb *tbl_scope_cb, - int dir) -{ - struct hcapi_cfa_em_ctx_mem_info *ctxp = &tbl_scope_cb->em_ctx_info[dir]; - struct hcapi_cfa_em_table *tbl; - int i; - - for (i = TF_KEY0_TABLE; i < TF_MAX_TABLE; i++) { - tbl = &ctxp->em_tables[i]; - - if (tbl->num_entries != 0 && tbl->entry_size != 0) { - tf_msg_em_mem_unrgtr(tfp, &tbl->ctx_id); - tf_em_free_page_table(tbl); - } - } -} - -/** - * Registers EM Ctx in Firmware - * - * [in] tfp - * Pointer to a TruFlow handle - * - * [in] tbl_scope_cb - * Pointer to a table scope control block - * - * [in] dir - * Receive or transmit direction - * - * Returns: - * 0 - Success - * -ENOMEM - Out of Memory - */ -static int -tf_em_ctx_reg(struct tf *tfp, - struct tf_tbl_scope_cb *tbl_scope_cb, - int dir) -{ - struct hcapi_cfa_em_ctx_mem_info *ctxp = &tbl_scope_cb->em_ctx_info[dir]; - struct hcapi_cfa_em_table *tbl; - int rc = 0; - int i; - - for (i = TF_KEY0_TABLE; i < TF_MAX_TABLE; i++) { - tbl = &ctxp->em_tables[i]; - - if (tbl->num_entries && tbl->entry_size) { - rc = tf_em_size_table(tbl, TF_EM_PAGE_SIZE); - - if (rc) - goto cleanup; - - rc = tf_em_alloc_page_table(tbl); - if (rc) - goto cleanup; - - tf_em_setup_page_table(tbl); - rc = tf_msg_em_mem_rgtr(tfp, - tbl->num_lvl - 1, - TF_EM_PAGE_SIZE_ENUM, - tbl->l0_dma_addr, - &tbl->ctx_id); - if (rc) - goto cleanup; - } - } - return rc; - -cleanup: - tf_em_ctx_unreg(tfp, tbl_scope_cb, dir); - return rc; -} - -int -tf_em_ext_alloc(struct tf *tfp, - struct tf_alloc_tbl_scope_parms *parms) -{ - int rc; - enum tf_dir dir; - struct tf_tbl_scope_cb *tbl_scope_cb; - struct hcapi_cfa_em_table *em_tables; - struct tf_free_tbl_scope_parms free_parms; - struct tf_rm_allocate_parms aparms = { 0 }; - struct tf_rm_free_parms fparms = { 0 }; - struct tfp_calloc_parms cparms; - struct tf_session *tfs = NULL; - struct em_ext_db *ext_db = NULL; - void *ext_ptr = NULL; - uint16_t pf; - - rc = tf_session_get_session_internal(tfp, &tfs); - if (rc) { - TFP_DRV_LOG(ERR, "Failed to get tf_session, rc:%s\n", - strerror(-rc)); - return rc; - } - - rc = tf_session_get_em_ext_db(tfp, &ext_ptr); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to get em_ext_db from session, rc:%s\n", - strerror(-rc)); - return rc; - } - ext_db = (struct em_ext_db *)ext_ptr; - - rc = tfp_get_pf(tfp, &pf); - if (rc) { - TFP_DRV_LOG(ERR, - "EEM: PF query error rc:%s\n", - strerror(-rc)); - goto cleanup; - } - - /* Get Table Scope control block from the session pool */ - aparms.rm_db = ext_db->eem_db[TF_DIR_RX]; - aparms.subtype = TF_EM_TBL_TYPE_TBL_SCOPE; - aparms.index = (uint32_t *)&parms->tbl_scope_id; - rc = tf_rm_allocate(&aparms); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to allocate table scope\n"); - goto cleanup; - } - - /* Create tbl_scope, initialize and attach to the session */ - cparms.nitems = 1; - cparms.size = sizeof(struct tf_tbl_scope_cb); - cparms.alignment = 0; - rc = tfp_calloc(&cparms); - if (rc) { - /* Log error */ - TFP_DRV_LOG(ERR, - "Failed to allocate session table scope, rc:%s\n", - strerror(-rc)); - goto cleanup; - } - - tbl_scope_cb = cparms.mem_va; - tbl_scope_cb->tbl_scope_id = parms->tbl_scope_id; - tbl_scope_cb->pf = pf; - - for (dir = 0; dir < TF_DIR_MAX; dir++) { - rc = tf_msg_em_qcaps(tfp, - dir, - &tbl_scope_cb->em_caps[dir]); - if (rc) { - TFP_DRV_LOG(ERR, - "EEM: Unable to query for EEM capability," - " rc:%s\n", - strerror(-rc)); - goto cleanup_ts; - } - } - - /* - * Validate and setup table sizes - */ - if (tf_em_validate_num_entries(tbl_scope_cb, parms)) - goto cleanup_ts; - - for (dir = 0; dir < TF_DIR_MAX; dir++) { - /* - * Allocate tables and signal configuration to FW - */ - rc = tf_em_ctx_reg(tfp, tbl_scope_cb, dir); - if (rc) { - TFP_DRV_LOG(ERR, - "EEM: Unable to register for EEM ctx," - " rc:%s\n", - strerror(-rc)); - goto cleanup_ts; - } - - em_tables = tbl_scope_cb->em_ctx_info[dir].em_tables; - rc = tf_msg_em_cfg(tfp, - em_tables[TF_KEY0_TABLE].num_entries, - em_tables[TF_KEY0_TABLE].ctx_id, - em_tables[TF_KEY1_TABLE].ctx_id, - em_tables[TF_RECORD_TABLE].ctx_id, - em_tables[TF_EFC_TABLE].ctx_id, - parms->hw_flow_cache_flush_timer, - dir); - if (rc) { - TFP_DRV_LOG(ERR, - "TBL: Unable to configure EEM in firmware" - " rc:%s\n", - strerror(-rc)); - goto cleanup_full; - } - - rc = tf_msg_em_op(tfp, - dir, - HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_ENABLE); - - if (rc) { - TFP_DRV_LOG(ERR, - "EEM: Unable to enable EEM in firmware" - " rc:%s\n", - strerror(-rc)); - goto cleanup_full; - } - - /* Allocate the pool of offsets of the external memory. - * Initially, this is a single fixed size pool for all external - * actions related to a single table scope. - */ - rc = tf_create_tbl_pool_external(dir, - tbl_scope_cb, - em_tables[TF_RECORD_TABLE].num_entries, - em_tables[TF_RECORD_TABLE].entry_size); - if (rc) { - TFP_DRV_LOG(ERR, - "%s TBL: Unable to allocate idx pools %s\n", - tf_dir_2_str(dir), - strerror(-rc)); - goto cleanup_full; - } - } - - /* Insert into session tbl_scope list */ - ll_insert(&ext_db->tbl_scope_ll, &tbl_scope_cb->ll_entry); - return 0; - -cleanup_full: - free_parms.tbl_scope_id = parms->tbl_scope_id; - /* Insert into session list prior to ext_free */ - ll_insert(&ext_db->tbl_scope_ll, &tbl_scope_cb->ll_entry); - tf_em_ext_free(tfp, &free_parms); - return -EINVAL; - -cleanup_ts: - tfp_free(tbl_scope_cb); - -cleanup: - /* Free Table control block */ - fparms.rm_db = ext_db->eem_db[TF_DIR_RX]; - fparms.subtype = TF_EM_TBL_TYPE_TBL_SCOPE; - fparms.index = parms->tbl_scope_id; - rc = tf_rm_free(&fparms); - if (rc) - TFP_DRV_LOG(ERR, "Failed to free table scope\n"); - - return -EINVAL; -} - -int -tf_em_ext_free(struct tf *tfp, - struct tf_free_tbl_scope_parms *parms) -{ - int rc = 0; - enum tf_dir dir; - struct tf_tbl_scope_cb *tbl_scope_cb; - struct tf_session *tfs; - struct em_ext_db *ext_db = NULL; - void *ext_ptr = NULL; - struct tf_rm_free_parms aparms = { 0 }; - - rc = tf_session_get_session_internal(tfp, &tfs); - if (rc) { - TFP_DRV_LOG(ERR, "Failed to get tf_session, rc:%s\n", - strerror(-rc)); - return -EINVAL; - } - - rc = tf_session_get_em_ext_db(tfp, &ext_ptr); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to get em_ext_db from session, rc:%s\n", - strerror(-rc)); - return rc; - } - ext_db = (struct em_ext_db *)ext_ptr; - - tbl_scope_cb = tf_em_ext_common_tbl_scope_find(tfp, parms->tbl_scope_id); - if (tbl_scope_cb == NULL) { - TFP_DRV_LOG(ERR, "Table scope error\n"); - return -EINVAL; - } - - /* Free Table control block */ - aparms.rm_db = ext_db->eem_db[TF_DIR_RX]; - aparms.subtype = TF_EM_TBL_TYPE_TBL_SCOPE; - aparms.index = parms->tbl_scope_id; - rc = tf_rm_free(&aparms); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to free table scope\n"); - } - - /* free table scope locks */ - for (dir = 0; dir < TF_DIR_MAX; dir++) { - /* Free associated external pools - */ - tf_destroy_tbl_pool_external(dir, - tbl_scope_cb); - tf_msg_em_op(tfp, - dir, - HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_DISABLE); - - /* free table scope and all associated resources */ - tf_em_ctx_unreg(tfp, tbl_scope_cb, dir); - } - - /* remove from session list and free tbl_scope */ - ll_delete(&ext_db->tbl_scope_ll, &tbl_scope_cb->ll_entry); - tfp_free(tbl_scope_cb); - return rc; -} diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index 4aa90f6b07..08e9783d52 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -1100,471 +1100,6 @@ tf_msg_move_em_entry(struct tf *tfp, return 0; } -int tf_msg_ext_em_ctxt_mem_alloc(struct tf *tfp, - struct hcapi_cfa_em_table *tbl, - uint64_t *dma_addr, - uint32_t *page_lvl, - uint32_t *page_size) -{ - struct tfp_send_msg_parms parms = { 0 }; - struct hwrm_tf_ctxt_mem_alloc_input req = {0}; - struct hwrm_tf_ctxt_mem_alloc_output resp = {0}; - uint32_t mem_size_k; - int rc = 0; - struct tf_dev_info *dev; - struct tf_session *tfs; - uint32_t fw_se_id; - - /* Retrieve the session information */ - rc = tf_session_get_session_internal(tfp, &tfs); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to lookup session, rc:%s\n", - strerror(-rc)); - return rc; - } - - /* Retrieve the device information */ - rc = tf_session_get_device(tfs, &dev); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to lookup device, rc:%s\n", - strerror(-rc)); - return rc; - } - /* Retrieve the session information */ - fw_se_id = tfs->session_id.internal.fw_session_id; - - if (tbl->num_entries && tbl->entry_size) { - /* unit: kbytes */ - mem_size_k = (tbl->num_entries / TF_KILOBYTE) * tbl->entry_size; - req.mem_size = tfp_cpu_to_le_32(mem_size_k); - req.fw_session_id = tfp_cpu_to_le_32(fw_se_id); - parms.tf_type = HWRM_TF_CTXT_MEM_ALLOC; - parms.req_data = (uint32_t *)&req; - parms.req_size = sizeof(req); - parms.resp_data = (uint32_t *)&resp; - parms.resp_size = sizeof(resp); - parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); - if (rc) { - TFP_DRV_LOG(ERR, "Failed ext_em_alloc error rc:%s\n", - strerror(-rc)); - return rc; - } - - *dma_addr = tfp_le_to_cpu_64(resp.page_dir); - *page_lvl = resp.page_level; - *page_size = resp.page_size; - } - - return rc; -} - -int tf_msg_ext_em_ctxt_mem_free(struct tf *tfp, - uint32_t mem_size_k, - uint64_t dma_addr, - uint8_t page_level, - uint8_t page_size) -{ - struct tfp_send_msg_parms parms = { 0 }; - struct hwrm_tf_ctxt_mem_free_input req = {0}; - struct hwrm_tf_ctxt_mem_free_output resp = {0}; - int rc = 0; - struct tf_dev_info *dev; - struct tf_session *tfs; - uint32_t fw_se_id; - - /* Retrieve the session information */ - rc = tf_session_get_session_internal(tfp, &tfs); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to lookup session, rc:%s\n", - strerror(-rc)); - return rc; - } - - /* Retrieve the device information */ - rc = tf_session_get_device(tfs, &dev); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to lookup device, rc:%s\n", - strerror(-rc)); - return rc; - } - /* Retrieve the session information */ - fw_se_id = tfs->session_id.internal.fw_session_id; - - req.fw_session_id = tfp_cpu_to_le_32(fw_se_id); - req.mem_size = tfp_cpu_to_le_32(mem_size_k); - req.page_dir = tfp_cpu_to_le_64(dma_addr); - req.page_level = page_level; - req.page_size = page_size; - parms.tf_type = HWRM_TF_CTXT_MEM_FREE; - parms.req_data = (uint32_t *)&req; - parms.req_size = sizeof(req); - parms.resp_data = (uint32_t *)&resp; - parms.resp_size = sizeof(resp); - parms.mailbox = dev->ops->tf_dev_get_mailbox(); - rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); - - return rc; -} - -int -tf_msg_em_mem_rgtr(struct tf *tfp, - int page_lvl, - int page_size, - uint64_t dma_addr, - uint16_t *ctx_id) -{ - int rc; - struct hwrm_tf_ctxt_mem_rgtr_input req = { 0 }; - struct hwrm_tf_ctxt_mem_rgtr_output resp = { 0 }; - struct tfp_send_msg_parms parms = { 0 }; - struct tf_dev_info *dev; - struct tf_session *tfs; - uint32_t fw_se_id; - - /* Retrieve the session information */ - rc = tf_session_get_session_internal(tfp, &tfs); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to lookup session, rc:%s\n", - strerror(-rc)); - return rc; - } - - /* Retrieve the device information */ - rc = tf_session_get_device(tfs, &dev); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to lookup device, rc:%s\n", - strerror(-rc)); - return rc; - } - fw_se_id = tfs->session_id.internal.fw_session_id; - - req.fw_session_id = tfp_cpu_to_le_32(fw_se_id); - req.page_level = page_lvl; - req.page_size = page_size; - req.page_dir = tfp_cpu_to_le_64(dma_addr); - - parms.tf_type = HWRM_TF_CTXT_MEM_RGTR; - parms.req_data = (uint32_t *)&req; - parms.req_size = sizeof(req); - parms.resp_data = (uint32_t *)&resp; - parms.resp_size = sizeof(resp); - parms.mailbox = dev->ops->tf_dev_get_mailbox(); - - rc = tfp_send_msg_direct(tf_session_get_bp(tfp), - &parms); - if (rc) - return rc; - - *ctx_id = tfp_le_to_cpu_16(resp.ctx_id); - - return rc; -} - -int -tf_msg_em_mem_unrgtr(struct tf *tfp, - uint16_t *ctx_id) -{ - int rc; - struct hwrm_tf_ctxt_mem_unrgtr_input req = {0}; - struct hwrm_tf_ctxt_mem_unrgtr_output resp = {0}; - struct tfp_send_msg_parms parms = { 0 }; - struct tf_dev_info *dev; - struct tf_session *tfs; - uint32_t fw_se_id; - - /* Retrieve the session information */ - rc = tf_session_get_session_internal(tfp, &tfs); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to lookup session, rc:%s\n", - strerror(-rc)); - return rc; - } - - /* Retrieve the device information */ - rc = tf_session_get_device(tfs, &dev); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to lookup device, rc:%s\n", - strerror(-rc)); - return rc; - } - - fw_se_id = tfs->session_id.internal.fw_session_id; - req.fw_session_id = tfp_cpu_to_le_32(fw_se_id); - - req.ctx_id = tfp_cpu_to_le_32(*ctx_id); - - parms.tf_type = HWRM_TF_CTXT_MEM_UNRGTR; - parms.req_data = (uint32_t *)&req; - parms.req_size = sizeof(req); - parms.resp_data = (uint32_t *)&resp; - parms.resp_size = sizeof(resp); - parms.mailbox = dev->ops->tf_dev_get_mailbox(); - - rc = tfp_send_msg_direct(tf_session_get_bp(tfp), - &parms); - return rc; -} - -int -tf_msg_em_qcaps(struct tf *tfp, - int dir, - struct tf_em_caps *em_caps) -{ - int rc; - struct hwrm_tf_ext_em_qcaps_input req = {0}; - struct hwrm_tf_ext_em_qcaps_output resp = { 0 }; - uint32_t flags; - struct tfp_send_msg_parms parms = { 0 }; - struct tf_dev_info *dev; - struct tf_session *tfs; - uint32_t fw_se_id; - - /* Retrieve the session information */ - rc = tf_session_get_session_internal(tfp, &tfs); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Failed to lookup session, rc:%s\n", - tf_dir_2_str(dir), - strerror(-rc)); - return rc; - } - fw_se_id = tfs->session_id.internal.fw_session_id; - - /* Retrieve the device information */ - rc = tf_session_get_device(tfs, &dev); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Failed to lookup device, rc:%s\n", - tf_dir_2_str(dir), - strerror(-rc)); - return rc; - } - - flags = (dir == TF_DIR_TX ? HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX : - HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX); - req.flags = tfp_cpu_to_le_32(flags); - - parms.tf_type = HWRM_TF_EXT_EM_QCAPS; - req.fw_session_id = tfp_cpu_to_le_32(fw_se_id); - parms.req_data = (uint32_t *)&req; - parms.req_size = sizeof(req); - parms.resp_data = (uint32_t *)&resp; - parms.resp_size = sizeof(resp); - parms.mailbox = dev->ops->tf_dev_get_mailbox(); - - rc = tfp_send_msg_direct(tf_session_get_bp(tfp), - &parms); - if (rc) - return rc; - - em_caps->supported = tfp_le_to_cpu_32(resp.supported); - em_caps->max_entries_supported = - tfp_le_to_cpu_32(resp.max_entries_supported); - em_caps->key_entry_size = tfp_le_to_cpu_16(resp.key_entry_size); - em_caps->record_entry_size = - tfp_le_to_cpu_16(resp.record_entry_size); - em_caps->efc_entry_size = tfp_le_to_cpu_16(resp.efc_entry_size); - - return rc; -} - -int -tf_msg_em_cfg(struct tf *tfp, - uint32_t num_entries, - uint16_t key0_ctx_id, - uint16_t key1_ctx_id, - uint16_t record_ctx_id, - uint16_t efc_ctx_id, - uint8_t flush_interval, - int dir) -{ - int rc; - struct hwrm_tf_ext_em_cfg_input req = {0}; - struct hwrm_tf_ext_em_cfg_output resp = {0}; - uint32_t flags; - struct tfp_send_msg_parms parms = { 0 }; - struct tf_dev_info *dev; - struct tf_session *tfs; - - /* Retrieve the session information */ - rc = tf_session_get_session_internal(tfp, &tfs); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Failed to lookup session, rc:%s\n", - tf_dir_2_str(dir), - strerror(-rc)); - return rc; - } - - /* Retrieve the device information */ - rc = tf_session_get_device(tfs, &dev); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Failed to lookup device, rc:%s\n", - tf_dir_2_str(dir), - strerror(-rc)); - return rc; - } - - flags = (dir == TF_DIR_TX ? HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX : - HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX); - flags |= HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD; - - req.flags = tfp_cpu_to_le_32(flags); - req.num_entries = tfp_cpu_to_le_32(num_entries); - - req.flush_interval = flush_interval; - - req.key0_ctx_id = tfp_cpu_to_le_16(key0_ctx_id); - req.key1_ctx_id = tfp_cpu_to_le_16(key1_ctx_id); - req.record_ctx_id = tfp_cpu_to_le_16(record_ctx_id); - req.efc_ctx_id = tfp_cpu_to_le_16(efc_ctx_id); - - parms.tf_type = HWRM_TF_EXT_EM_CFG; - parms.req_data = (uint32_t *)&req; - parms.req_size = sizeof(req); - parms.resp_data = (uint32_t *)&resp; - parms.resp_size = sizeof(resp); - parms.mailbox = dev->ops->tf_dev_get_mailbox(); - - rc = tfp_send_msg_direct(tf_session_get_bp(tfp), - &parms); - return rc; -} - -int -tf_msg_ext_em_cfg(struct tf *tfp, - struct tf_tbl_scope_cb *tbl_scope_cb, - uint32_t st_buckets, - uint8_t flush_interval, - enum tf_dir dir) -{ - struct hcapi_cfa_em_ctx_mem_info *ctxp = &tbl_scope_cb->em_ctx_info[dir]; - struct hcapi_cfa_em_table *lkup_tbl, *act_tbl; - struct hwrm_tf_ext_em_cfg_input req = {0}; - struct hwrm_tf_ext_em_cfg_output resp = {0}; - struct tfp_send_msg_parms parms = { 0 }; - uint32_t flags; - struct tf_dev_info *dev; - struct tf_session *tfs; - uint32_t fw_se_id; - int rc; - - /* Retrieve the session information */ - rc = tf_session_get_session_internal(tfp, &tfs); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Failed to lookup session, rc:%s\n", - tf_dir_2_str(dir), - strerror(-rc)); - return rc; - } - - /* Retrieve the device information */ - rc = tf_session_get_device(tfs, &dev); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Failed to lookup device, rc:%s\n", - tf_dir_2_str(dir), - strerror(-rc)); - return rc; - } - fw_se_id = tfs->session_id.internal.fw_session_id; - - lkup_tbl = &ctxp->em_tables[TF_EM_LKUP_TABLE]; - act_tbl = &ctxp->em_tables[TF_ACTION_TABLE]; - flags = (dir == TF_DIR_TX ? HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX : - HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX); - flags |= HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD; - - req.flags = tfp_cpu_to_le_32(flags); - req.num_entries = tfp_cpu_to_le_32(act_tbl->num_entries); - req.lkup_static_buckets = tfp_cpu_to_le_32(st_buckets); - req.fw_session_id = tfp_cpu_to_le_32(fw_se_id); - req.flush_interval = flush_interval; - req.action_ctx_id = tfp_cpu_to_le_16(act_tbl->ctx_id); - req.action_tbl_scope = tfp_cpu_to_le_16(tbl_scope_cb->tbl_scope_id); - req.lkup_ctx_id = tfp_cpu_to_le_16(lkup_tbl->ctx_id); - req.lkup_tbl_scope = tfp_cpu_to_le_16(tbl_scope_cb->tbl_scope_id); - - req.enables = (HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_CTX_ID | - HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_TBL_SCOPE | - HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_CTX_ID | - HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_TBL_SCOPE | - HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_STATIC_BUCKETS | - HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_NUM_ENTRIES); - - parms.tf_type = HWRM_TF_EXT_EM_CFG; - parms.req_data = (uint32_t *)&req; - parms.req_size = sizeof(req); - parms.resp_data = (uint32_t *)&resp; - parms.resp_size = sizeof(resp); - parms.mailbox = dev->ops->tf_dev_get_mailbox(); - - rc = tfp_send_msg_direct(tf_session_get_bp(tfp), - &parms); - return rc; -} - -int -tf_msg_em_op(struct tf *tfp, - int dir, - uint16_t op) -{ - int rc; - struct hwrm_tf_ext_em_op_input req = {0}; - struct hwrm_tf_ext_em_op_output resp = {0}; - uint32_t flags; - struct tfp_send_msg_parms parms = { 0 }; - struct tf_dev_info *dev; - struct tf_session *tfs; - - /* Retrieve the session information */ - rc = tf_session_get_session_internal(tfp, &tfs); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Failed to lookup session, rc:%s\n", - tf_dir_2_str(dir), - strerror(-rc)); - return rc; - } - - /* Retrieve the device information */ - rc = tf_session_get_device(tfs, &dev); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Failed to lookup device, rc:%s\n", - tf_dir_2_str(dir), - strerror(-rc)); - return rc; - } - - flags = (dir == TF_DIR_TX ? HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX : - HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX); - req.flags = tfp_cpu_to_le_32(flags); - req.op = tfp_cpu_to_le_16(op); - - parms.tf_type = HWRM_TF_EXT_EM_OP; - parms.req_data = (uint32_t *)&req; - parms.req_size = sizeof(req); - parms.resp_data = (uint32_t *)&resp; - parms.resp_size = sizeof(resp); - parms.mailbox = dev->ops->tf_dev_get_mailbox(); - - rc = tfp_send_msg_direct(tf_session_get_bp(tfp), - &parms); - return rc; -} - int tf_msg_tcam_entry_set(struct tf *tfp, struct tf_dev_info *dev, diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c index 9e0671d47b..df5cad75b5 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam.c +++ b/drivers/net/bnxt/tf_core/tf_tcam.c @@ -261,7 +261,6 @@ tf_tcam_unbind(struct tf *tfp) tcam_db->tcam_db[i] = NULL; } - } rc = tf_tcam_mgr_unbind_msg(tfp, dev); From patchwork Fri Aug 30 14:00:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sriharsha Basavapatna X-Patchwork-Id: 143468 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 51B12458A8; Fri, 30 Aug 2024 15:51:38 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BA80A42EAC; Fri, 30 Aug 2024 15:51:12 +0200 (CEST) Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) by mails.dpdk.org (Postfix) with ESMTP id 63EED40291 for ; Fri, 30 Aug 2024 15:51:10 +0200 (CEST) Received: by mail-pl1-f174.google.com with SMTP id d9443c01a7336-201e64607a5so14531055ad.2 for ; Fri, 30 Aug 2024 06:51:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1725025869; x=1725630669; darn=dpdk.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2uQKaMu+75/OrhVAdYbc60KaEuLlpQZzWTNakjmiCPQ=; b=VA+tobbI2gTxy41S0FgaQCQzS4t25CWqlq8y0F5rKvFqCBXNhP9kem0fvILfet0fiR W5EAi8MJwVVU4EBBdRgy7y/FtGcCKaEmHy7jjfzxlhIkufmGW1G6YMEf8ceaHdv51TZe 0B4hW0Bsg75dOlydyefRjLAcqVWrlUGJasP+0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1725025869; x=1725630669; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2uQKaMu+75/OrhVAdYbc60KaEuLlpQZzWTNakjmiCPQ=; b=h0aDQO5vEpUwDANeUnSXOYW2fjUc//HTTgk29UGoekPyDPztnzv+33OrJqA2BA+Y4Y +6SndqoFsCnn7ZYsauYevSwsm/yljQ2e9RB8pGxJ+LapieLWOFAO2yrDDUuFiwGU17Wy 4avLxmSZl7ModrVpdrMXYynBhpxDdef0xaeTlUEhsYrgbuI2t1cW2Rm9B3jP/ZgVl5Z/ ZDL85tlZ6OawG+QTJGm38cXuvpmrpIkt7Ee7G0zMCeiH4wq52sZjiA00Dog+PxqF8EUM WiL50N2AXxuJ3/c3GiWztVtPOlgZFDioJocLNcUcPUoYIdGLYKL4+ix/6Lo+HFAyJqlw wSaA== X-Gm-Message-State: AOJu0Yw2uRZUkmmy6+PMP+jG9JN6D/KAZJX2nRgR6/nLU0Nmstr7zIRz 3tyjVtYV3TJyBMLbnnErFOVZpWIod8iFHY7gO8WpEZ7eHXLBAIy6dqIKUeSg7zFxJMZutwvmYhU 1dT/ljVsvYP62+7l0rHCScsx4uJmEtvgWQeFZ2iofvz72QFc+uXoRYiI1qY64NxUgzO5DacGdiW 1P7DajNGC9cn+A8wTHjrCgpbP13lZXHSKOnkDyr+y3ZQMJ X-Google-Smtp-Source: AGHT+IHWeVoDj554UMS90aoSrEbXqrDzltABKVeKy/rcoLh7VJQ8SRi1px2c0Y8O4Wmi4HS+dhiaHA== X-Received: by 2002:a17:902:dac2:b0:1ff:4d66:d7bb with SMTP id d9443c01a7336-2050c3730bfmr76751775ad.36.1725025868978; Fri, 30 Aug 2024 06:51:08 -0700 (PDT) Received: from dhcp-10-123-154-23.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-205155658dfsm27067145ad.297.2024.08.30.06.51.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Aug 2024 06:51:08 -0700 (PDT) From: Sriharsha Basavapatna To: dev@dpdk.org Cc: Farah Smith , Kishore Padmanabha , Shahaji Bhosle , Sriharsha Basavapatna Subject: [PATCH 04/47] net/bnxt: tf_core: Thor TF EM key size check Date: Fri, 30 Aug 2024 19:30:06 +0530 Message-Id: <20240830140049.1715230-5-sriharsha.basavapatna@broadcom.com> X-Mailer: git-send-email 2.39.0.189.g4dbebc36b0 In-Reply-To: <20240830140049.1715230-1-sriharsha.basavapatna@broadcom.com> References: <20240830140049.1715230-1-sriharsha.basavapatna@broadcom.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Farah Smith The maximum EM key size is 640 bits for Thor. But the lookup record + the key size is 679 bits. This value must be rounded up to a 128 bit aligned number. So the size check should be 96 bytes rather than 80. This fix allows keys > 601 bits to be successfully inserted. Fixes: 539931eab3a5 ("net/bnxt: support EM with FKB") Signed-off-by: Farah Smith Reviewed-by: Farah Smith Reviewed-by: Kishore Padmanabha Reviewed-by: Shahaji Bhosle Signed-off-by: Sriharsha Basavapatna --- drivers/net/bnxt/tf_core/tf_msg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index 08e9783d52..dd5ea1c80e 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -25,7 +25,7 @@ */ #define TF_MSG_SET_GLOBAL_CFG_DATA_SIZE 16 #define TF_MSG_EM_INSERT_KEY_SIZE 64 -#define TF_MSG_EM_INSERT_RECORD_SIZE 80 +#define TF_MSG_EM_INSERT_RECORD_SIZE 96 #define TF_MSG_TBL_TYPE_SET_DATA_SIZE 88 /* Compile check - Catch any msg changes that we depend on, like the From patchwork Fri Aug 30 14:00:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sriharsha Basavapatna X-Patchwork-Id: 143469 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5900F458A8; Fri, 30 Aug 2024 15:51:48 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4BE6042EB8; Fri, 30 Aug 2024 15:51:16 +0200 (CEST) Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) by mails.dpdk.org (Postfix) with ESMTP id AE2E542EA3 for ; Fri, 30 Aug 2024 15:51:12 +0200 (CEST) Received: by mail-pl1-f171.google.com with SMTP id d9443c01a7336-202089e57d8so12891595ad.0 for ; Fri, 30 Aug 2024 06:51:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1725025872; x=1725630672; darn=dpdk.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=A0owi3G+5csWPOy7Nju2kNDeR+SBjbNxjHuo/0VM7n0=; b=bIR2amfi6u3XhYIY86+QxqEMxi5V3q3zRZrHlRRYE5tHpwKhooo8ANNAJHBU+TOgLM s8gngloUmUwFgExqxgpnZOjQCxbpHqSsDTUB4NpwVoiujbsLXKyfaJyWiSwHu2kYAj1E 5IeyGXX+ZsJ8GhcjW8XH8C+4WCSwLsVknAzP4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1725025872; x=1725630672; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=A0owi3G+5csWPOy7Nju2kNDeR+SBjbNxjHuo/0VM7n0=; b=CghhrEL+W/TyrNfAGC56L9g3ol7TZIJs4ctexnmeU5BJa6X43KPBQUUwLhPDe41UPf tSFj4uRbWO/Sutkg3CTTkKf1LxyNooYOAuKLnLPQMVEE9wXuKsQIweSPvpYNrH8CCmSC xy1R/XWLRlV11MfzM58H/NtLvdPag/sNI+hG92gSoTihWnjHwfBShhPdioWuqRnWU5Yd +6a93+TOMr9dBw82TMqg50dCK4Q8E8cwokF5HdVp2fjMiX7mmlKf6PvBv18Ja4DmmxNF tH4XJvtKO6dpDSKEOFS+GOL5hd4UVNQtJjrysvaWQ2S/FrJX5T1zqzqsOcLnq/TyA28c 8KyQ== X-Gm-Message-State: AOJu0YxjXXo/gNudA2U7fc+ZDN4/TSGlhiDvbJhEHmG5OcRZh4YqaJLR Q1CEteMyD9ke2/f1DdMtYI9Ssw0WtoON/73rr0teJNaiLLJBYDBoWZgPpWWyjEoYF/xNi+xR9Fo 5s2mYEhH89bbYktBSd4Jg2YwJzUkOkKELjC+z+5ZR10Kny+lqS+KTSZ2KO7YKmFA/n0PW2p93eB XkQpknjflCc35wHwRlAts1sS1k9ZygRjDDWay0zp4F8fZ0 X-Google-Smtp-Source: AGHT+IENKYKc1NO6Fg3RzGWFUkm7ZpP1t6pdaHHTfxsTPtddLBzyZcVc1jyRS/oMLE0m9tExIQrBXg== X-Received: by 2002:a17:903:94d:b0:205:3475:63be with SMTP id d9443c01a7336-20534756a0dmr21994165ad.25.1725025871384; Fri, 30 Aug 2024 06:51:11 -0700 (PDT) Received: from dhcp-10-123-154-23.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-205155658dfsm27067145ad.297.2024.08.30.06.51.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Aug 2024 06:51:11 -0700 (PDT) From: Sriharsha Basavapatna To: dev@dpdk.org Cc: Kishore Padmanabha , Michael Baucom , Ajit Khaparde , Shahaji Bhosle , Sriharsha Basavapatna Subject: [PATCH 05/47] net/bnxt: tf_core: flow scale improvement Date: Fri, 30 Aug 2024 19:30:07 +0530 Message-Id: <20240830140049.1715230-6-sriharsha.basavapatna@broadcom.com> X-Mailer: git-send-email 2.39.0.189.g4dbebc36b0 In-Reply-To: <20240830140049.1715230-1-sriharsha.basavapatna@broadcom.com> References: <20240830140049.1715230-1-sriharsha.basavapatna@broadcom.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Kishore Padmanabha Added logic to add flows to wildcard tcam if flows fail to be added to exact match table. Signed-off-by: Kishore Padmanabha Reviewed-by: Michael Baucom Reviewed-by: Ajit Khaparde Reviewed-by: Shahaji Bhosle Signed-off-by: Sriharsha Basavapatna --- drivers/net/bnxt/tf_core/tf_em_hash_internal.c | 4 ++-- drivers/net/bnxt/tf_core/tf_msg.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_em_hash_internal.c b/drivers/net/bnxt/tf_core/tf_em_hash_internal.c index d72ac83295..cb8da0e370 100644 --- a/drivers/net/bnxt/tf_core/tf_em_hash_internal.c +++ b/drivers/net/bnxt/tf_core/tf_em_hash_internal.c @@ -65,7 +65,7 @@ tf_em_hash_insert_int_entry(struct tf *tfp, PMD_DRV_LOG(ERR, "%s, EM entry index allocation failed\n", tf_dir_2_str(parms->dir)); - return -1; + return -ENOMEM; /* no more space to add entries */ } if (dev->ops->tf_dev_cfa_key_hash == NULL) @@ -87,7 +87,7 @@ tf_em_hash_insert_int_entry(struct tf *tfp, if (rc) { /* Free the allocated index before returning */ dpool_free(pool, index); - return -1; + return rc; } TF_SET_GFID(gfid, diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index dd5ea1c80e..1ef828a1e9 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -925,7 +925,7 @@ tf_msg_hash_insert_em_internal_entry(struct tf *tfp, if (msg_record_size > TF_MSG_EM_INSERT_RECORD_SIZE) { rc = -EINVAL; TFP_DRV_LOG(ERR, - "%s: Record size to large, rc:%s\n", + "%s: Record size too large, rc:%s\n", tf_dir_2_str(em_parms->dir), strerror(-rc)); return rc; From patchwork Fri Aug 30 14:00:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sriharsha Basavapatna X-Patchwork-Id: 143470 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C98CB458A8; Fri, 30 Aug 2024 15:51:56 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DC78A42EBC; Fri, 30 Aug 2024 15:51:17 +0200 (CEST) Received: from mail-pl1-f193.google.com (mail-pl1-f193.google.com [209.85.214.193]) by mails.dpdk.org (Postfix) with ESMTP id D7DD542E91 for ; Fri, 30 Aug 2024 15:51:15 +0200 (CEST) Received: by mail-pl1-f193.google.com with SMTP id d9443c01a7336-2025031eb60so16328915ad.3 for ; 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Fri, 30 Aug 2024 06:51:13 -0700 (PDT) Received: from dhcp-10-123-154-23.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-205155658dfsm27067145ad.297.2024.08.30.06.51.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Aug 2024 06:51:13 -0700 (PDT) From: Sriharsha Basavapatna To: dev@dpdk.org Cc: Shuanglin Wang , Kishore Padmanabha , Sriharsha Basavapatna Subject: [PATCH 06/47] net/bnxt: tf_core: TF support flow scale query Date: Fri, 30 Aug 2024 19:30:08 +0530 Message-Id: <20240830140049.1715230-7-sriharsha.basavapatna@broadcom.com> X-Mailer: git-send-email 2.39.0.189.g4dbebc36b0 In-Reply-To: <20240830140049.1715230-1-sriharsha.basavapatna@broadcom.com> References: <20240830140049.1715230-1-sriharsha.basavapatna@broadcom.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shuanglin Wang TF supports the flow scale query feature for OVS application. The resource usage is tracked when opening a TF session or adding/deleting a flow. The resources includes WC TCAM, EM, Action, Counter, Meter, ACT_ENCAP, ACT_ENCAP, and SP_SMAC. User can query the resource usage using niccli. Several improvements on flow scale query feature: 1. Some default rules require both RX and TX resources; need to update usage states on both direcitons. 2. Update resoure usage state for regular flows only. 3. Added a buffer dirty state to avoid unnecessary state sync with firmware. This feature is disabled by default. Using the build flag -DTF_FLOW_SCALE_QUERY to enable it. Signed-off-by: Shuanglin Wang Reviewed-by: Kishore Padmanabha Signed-off-by: Sriharsha Basavapatna --- drivers/net/bnxt/hsi_struct_def_dpdk.h | 342 ++++++++-- drivers/net/bnxt/tf_core/cfa_tcam_mgr.c | 57 +- .../net/bnxt/tf_core/cfa_tcam_mgr_device.h | 9 + .../net/bnxt/tf_core/cfa_tcam_mgr_session.c | 13 + .../net/bnxt/tf_core/cfa_tcam_mgr_session.h | 3 + drivers/net/bnxt/tf_core/meson.build | 1 + drivers/net/bnxt/tf_core/tf_core.c | 150 +++++ drivers/net/bnxt/tf_core/tf_core.h | 52 ++ drivers/net/bnxt/tf_core/tf_device.h | 65 ++ drivers/net/bnxt/tf_core/tf_device_p4.c | 10 + drivers/net/bnxt/tf_core/tf_device_p58.c | 105 +++ .../net/bnxt/tf_core/tf_em_hash_internal.c | 28 +- drivers/net/bnxt/tf_core/tf_em_internal.c | 7 + drivers/net/bnxt/tf_core/tf_msg.c | 175 +++++ drivers/net/bnxt/tf_core/tf_msg.h | 57 ++ drivers/net/bnxt/tf_core/tf_resources.c | 608 ++++++++++++++++++ drivers/net/bnxt/tf_core/tf_resources.h | 129 ++++ drivers/net/bnxt/tf_core/tf_rm.c | 39 +- drivers/net/bnxt/tf_core/tf_session.c | 10 + drivers/net/bnxt/tf_ulp/ulp_mapper.c | 16 + 20 files changed, 1806 insertions(+), 70 deletions(-) create mode 100644 drivers/net/bnxt/tf_core/tf_resources.c diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index 9beacd94aa..cec4b59d1a 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright (c) 2014-2023 Broadcom Inc. + * Copyright (c) 2014-2024 Broadcom Inc. * All rights reserved. * * DO NOT MODIFY!!! This file is automatically generated. @@ -836,6 +836,10 @@ struct cmd_nums { #define HWRM_TF_IF_TBL_SET UINT32_C(0x2fe) /* Experimental */ #define HWRM_TF_IF_TBL_GET UINT32_C(0x2ff) + /* Experimental */ + #define HWRM_TF_RESC_USAGE_SET UINT32_C(0x300) + /* Experimental */ + #define HWRM_TF_RESC_USAGE_QUERY UINT32_C(0x301) /* TruFlow command to check firmware table scope capabilities. */ #define HWRM_TFC_TBL_SCOPE_QCAPS UINT32_C(0x380) /* TruFlow command to allocate a table scope ID and create the pools. */ @@ -14960,32 +14964,18 @@ struct hwrm_func_qcaps_output { uint16_t xid_partition_cap; /* * When this bit is '1', it indicates that FW is capable of - * supporting partition based XID management for KTLS TX + * supporting partition based XID management for Tx crypto * key contexts. */ - #define HWRM_FUNC_QCAPS_OUTPUT_XID_PARTITION_CAP_KTLS_TKC \ + #define HWRM_FUNC_QCAPS_OUTPUT_XID_PARTITION_CAP_TX_CK \ UINT32_C(0x1) /* * When this bit is '1', it indicates that FW is capable of - * supporting partition based XID management for KTLS RX + * supporting partition based XID management for Rx crypto * key contexts. */ - #define HWRM_FUNC_QCAPS_OUTPUT_XID_PARTITION_CAP_KTLS_RKC \ + #define HWRM_FUNC_QCAPS_OUTPUT_XID_PARTITION_CAP_RX_CK \ UINT32_C(0x2) - /* - * When this bit is '1', it indicates that FW is capable of - * supporting partition based XID management for QUIC TX - * key contexts. - */ - #define HWRM_FUNC_QCAPS_OUTPUT_XID_PARTITION_CAP_QUIC_TKC \ - UINT32_C(0x4) - /* - * When this bit is '1', it indicates that FW is capable of - * supporting partition based XID management for QUIC RX - * key contexts. - */ - #define HWRM_FUNC_QCAPS_OUTPUT_XID_PARTITION_CAP_QUIC_RKC \ - UINT32_C(0x8) /* * This value uniquely identifies the hardware NIC used by the * function. The value returned will be the same for all functions. @@ -15804,8 +15794,21 @@ struct hwrm_func_qcfg_output { * initialize_fw. */ uint32_t roce_max_gid_per_vf; - /* Bitmap of context types that have XID partition enabled. */ + /* + * Bitmap of context types that have XID partition enabled. + * Only valid for PF. + */ uint16_t xid_partition_cfg; + /* + * When this bit is '1', it indicates that driver enables XID + * partition on Tx crypto key contexts. + */ + #define HWRM_FUNC_QCFG_OUTPUT_XID_PARTITION_CFG_TX_CK UINT32_C(0x1) + /* + * When this bit is '1', it indicates that driver enables XID + * partition on Rx crypto key contexts. + */ + #define HWRM_FUNC_QCFG_OUTPUT_XID_PARTITION_CFG_RX_CK UINT32_C(0x2) uint8_t unused_7; /* * This field is used in Output records to indicate that the output @@ -16886,34 +16889,20 @@ struct hwrm_func_cfg_input { /* Number of GIDs per VF. Only valid for PF. */ uint32_t roce_max_gid_per_vf; /* - * Bitmap of context kinds that have XID partition enabled. + * Bitmap of context types that have XID partition enabled. * Only valid for PF. */ uint16_t xid_partition_cfg; /* * When this bit is '1', it indicates that driver enables XID - * partition on KTLS TX key contexts. - */ - #define HWRM_FUNC_CFG_INPUT_XID_PARTITION_CFG_KTLS_TKC \ - UINT32_C(0x1) - /* - * When this bit is '1', it indicates that driver enables XID - * partition on KTLS RX key contexts. + * partition on Tx crypto key contexts. */ - #define HWRM_FUNC_CFG_INPUT_XID_PARTITION_CFG_KTLS_RKC \ - UINT32_C(0x2) + #define HWRM_FUNC_CFG_INPUT_XID_PARTITION_CFG_TX_CK UINT32_C(0x1) /* * When this bit is '1', it indicates that driver enables XID - * partition on QUIC TX key contexts. + * partition on Rx crypto key contexts. */ - #define HWRM_FUNC_CFG_INPUT_XID_PARTITION_CFG_QUIC_TKC \ - UINT32_C(0x4) - /* - * When this bit is '1', it indicates that driver enables XID - * partition on QUIC RX key contexts. - */ - #define HWRM_FUNC_CFG_INPUT_XID_PARTITION_CFG_QUIC_RKC \ - UINT32_C(0x8) + #define HWRM_FUNC_CFG_INPUT_XID_PARTITION_CFG_RX_CK UINT32_C(0x2) uint16_t unused_2; } __rte_packed; @@ -22737,11 +22726,11 @@ struct hwrm_func_backing_store_cfg_v2_input { /* TIM. */ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TIM \ UINT32_C(0xf) - /* Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TKC \ + /* Tx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TX_CK \ UINT32_C(0x13) - /* Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RKC \ + /* Rx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RX_CK \ UINT32_C(0x14) /* Mid-path TQM ring. */ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MP_TQM_RING \ @@ -22781,7 +22770,7 @@ struct hwrm_func_backing_store_cfg_v2_input { * RE_CFA_LKUP (0), RE_CFA_ACT (1), TE_CFA_LKUP(2), TE_CFA_ACT (3) * 3. If the backing store type is XID partition, use the following * instance value to map to context types: - * KTLS_TKC (0), KTLS_RKC (1), QUIC_TKC (2), QUIC_RKC (3) + * TX_CK (0), RX_CK (1) */ uint16_t instance; /* Control flags. */ @@ -22990,11 +22979,11 @@ struct hwrm_func_backing_store_qcfg_v2_input { /* TIM. */ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TIM \ UINT32_C(0xf) - /* Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TKC \ + /* Tx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TX_CK \ UINT32_C(0x13) - /* Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RKC \ + /* Rx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RX_CK \ UINT32_C(0x14) /* Mid-path TQM ring. */ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MP_TQM_RING \ @@ -23034,7 +23023,7 @@ struct hwrm_func_backing_store_qcfg_v2_input { * RE_CFA_LKUP (0), RE_CFA_ACT (1), TE_CFA_LKUP(2), TE_CFA_ACT (3) * 3. If the backing store type is XID partition, use the following * instance value to map to context types: - * KTLS_TKC (0), KTLS_RKC (1), QUIC_TKC (2), QUIC_RKC (3) + * TX_CK (0), RX_CK (1) */ uint16_t instance; uint8_t rsvd[4]; @@ -23111,7 +23100,7 @@ struct hwrm_func_backing_store_qcfg_v2_output { * RE_CFA_LKUP (0), RE_CFA_ACT (1), TE_CFA_LKUP(2), TE_CFA_ACT (3) * 3. If the backing store type is XID partition, use the following * instance value to map to context types: - * KTLS_TKC (0), KTLS_RKC (1), QUIC_TKC (2), QUIC_RKC (3) + * TX_CK (0), RX_CK (1) */ uint16_t instance; /* Control flags. */ @@ -23190,6 +23179,7 @@ struct hwrm_func_backing_store_qcfg_v2_output { * | VINC | vnic_split_entries | * | MRAV | mrav_split_entries | * | TS | ts_split_entries | + * | CK | ck_split_entries | */ uint32_t split_entry_0; /* Split entry #1. */ @@ -23271,6 +23261,19 @@ struct ts_split_entries { uint32_t rsvd2[2]; } __rte_packed; +/* Common structure to cast crypto key split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is TX_CK or RX_CK. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */ +/* ck_split_entries (size:128b/16B) */ +struct ck_split_entries { + /* + * Number of QUIC backing store entries. That means the number of KTLS + * backing store entries is the difference between this number and the + * total number of crypto key entries. + */ + uint32_t num_quic_entries; + uint32_t rsvd; + uint32_t rsvd2[2]; +} __rte_packed; + /************************************ * hwrm_func_backing_store_qcaps_v2 * ************************************/ @@ -23490,7 +23493,7 @@ struct hwrm_func_backing_store_qcaps_v2_output { * RE_CFA_LKUP (0), RE_CFA_ACT (1), TE_CFA_LKUP(2), TE_CFA_ACT (3) * 3. If the backing store type is VF XID partition in-use table, use * the following bits to map to context types: - * KTLS_TKC (0), KTLS_RKC (1), QUIC_TKC (2), QUIC_RKC (3) + * TX_CK (0), RX_CK (1) */ uint32_t instance_bit_map; /* @@ -23587,6 +23590,7 @@ struct hwrm_func_backing_store_qcaps_v2_output { * | VINC | vnic_split_entries | * | MRAV | mrav_split_entries | * | TS | ts_split_entries | + * | CK | ck_split_entries | */ uint32_t split_entry_0; /* Split entry #1. */ @@ -27288,8 +27292,14 @@ struct hwrm_port_phy_qcfg_output { /* QSFP112 */ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP112 \ (UINT32_C(0x1e) << 24) + /* SFP-DD CMIS */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFPDD \ + (UINT32_C(0x1f) << 24) + /* SFP CMIS */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_CSFP \ + (UINT32_C(0x20) << 24) #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \ - HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP112 + HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_CSFP /* * This value represents the current configuration of * Forward Error Correction (FEC) on the port. @@ -51794,7 +51804,7 @@ struct hwrm_cfa_lag_group_member_unrgtr_output { *****************************/ -/* hwrm_cfa_tls_filter_alloc_input (size:704b/88B) */ +/* hwrm_cfa_tls_filter_alloc_input (size:768b/96B) */ struct hwrm_cfa_tls_filter_alloc_input { /* The HWRM command request type. */ uint16_t req_type; @@ -51892,6 +51902,12 @@ struct hwrm_cfa_tls_filter_alloc_input { */ #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ UINT32_C(0x400) + /* + * This bit must be '1' for the quic_dst_connect_id field to be + * configured. + */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_QUIC_DST_CONNECT_ID \ + UINT32_C(0x800) /* * This value identifies a set of CFA data structures used for an L2 * context. @@ -51970,10 +51986,12 @@ struct hwrm_cfa_tls_filter_alloc_input { */ uint16_t dst_port; /* - * The Key Context Identifier (KID) for use with KTLS. + * The Key Context Identifier (KID) for use with KTLS or QUIC. * KID is limited to 20-bits. */ uint32_t kid; + /* The Destination Connection ID of QUIC. */ + uint64_t quic_dst_connect_id; } __rte_packed; /* hwrm_cfa_tls_filter_alloc_output (size:192b/24B) */ @@ -55766,6 +55784,222 @@ struct hwrm_tf_session_hotup_state_get_output { uint8_t valid; } __rte_packed; +/************************** + * hwrm_tf_resc_usage_set * + **************************/ + + +/* hwrm_tf_resc_usage_set_input (size:1024b/128B) */ +struct hwrm_tf_resc_usage_set_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DIR_TX + /* Indicate table data is being sent via DMA. */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DMA UINT32_C(0x2) + /* Types of the resource to set their usage state. */ + uint16_t types; + /* WC TCAM Pool */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_WC_TCAM \ + UINT32_C(0x1) + /* EM Internal Memory Pool */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_EM \ + UINT32_C(0x2) + /* Meter Instance */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_METER \ + UINT32_C(0x4) + /* Counter Record Table */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_COUNTER \ + UINT32_C(0x8) + /* Action Record Table */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_ACTION \ + UINT32_C(0x10) + /* ACT MODIFY/ENCAP Record Table */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_ACT_MOD_ENCAP \ + UINT32_C(0x20) + /* Source Property SMAC Record Table */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_SP_SMAC \ + UINT32_C(0x40) + /* All Resource Types */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_ALL \ + UINT32_C(0x80) + /* Size of the data to set. */ + uint16_t size; + /* unused */ + uint8_t unused1[6]; + /* Data to be set. */ + uint8_t data[96]; +} __rte_packed; + +/* hwrm_tf_resc_usage_set_output (size:128b/16B) */ +struct hwrm_tf_resc_usage_set_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/**************************** + * hwrm_tf_resc_usage_query * + ****************************/ + + +/* hwrm_tf_resc_usage_query_input (size:256b/32B) */ +struct hwrm_tf_resc_usage_query_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_TX + /* unused. */ + uint8_t unused0[2]; + /* Types of the resource to retrieve their usage state. */ + uint16_t types; + /* WC TCAM Pool */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_WC_TCAM \ + UINT32_C(0x1) + /* EM Internal Memory Pool */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_EM \ + UINT32_C(0x2) + /* Meter Instance */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_METER \ + UINT32_C(0x4) + /* Counter Record Table */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_COUNTER \ + UINT32_C(0x8) + /* Action Record Table */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_ACTION \ + UINT32_C(0x10) + /* ACT MODIFY/ENCAP Record Table */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_ACT_MOD_ENCAP \ + UINT32_C(0x20) + /* Source Property SMAC Record Table */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_SP_SMAC \ + UINT32_C(0x40) + /* All Resource Types */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_ALL \ + UINT32_C(0x80) + /* unused */ + uint8_t unused1[6]; +} __rte_packed; + +/* hwrm_tf_resc_usage_query_output (size:960b/120B) */ +struct hwrm_tf_resc_usage_query_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Response code. */ + uint32_t resp_code; + /* Response size. */ + uint16_t size; + /* unused */ + uint16_t unused0; + /* Response data. */ + uint8_t data[96]; + /* unused */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + /**************************** * hwrm_tfc_tbl_scope_qcaps * ****************************/ diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c index 9df2d2b937..349f52caba 100644 --- a/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c @@ -20,15 +20,6 @@ #define TF_TCAM_SLICE_INVALID (-1) -/* - * The following macros are for setting the entry status in a row entry. - * row is (struct cfa_tcam_mgr_table_rows_0 *) - */ -#define ROW_ENTRY_INUSE(row, entry) ((row)->entry_inuse & (1U << (entry))) -#define ROW_ENTRY_SET(row, entry) ((row)->entry_inuse |= (1U << (entry))) -#define ROW_ENTRY_CLEAR(row, entry) ((row)->entry_inuse &= ~(1U << (entry))) -#define ROW_INUSE(row) ((row)->entry_inuse != 0) - static struct cfa_tcam_mgr_entry_data *entry_data[TF_TCAM_MAX_SESSIONS]; static int global_data_initialized[TF_TCAM_MAX_SESSIONS]; @@ -685,6 +676,27 @@ cfa_tcam_mgr_rows_combine(int sess_idx, struct cfa_tcam_mgr_context *context, if (entry_moved) break; } + +#ifdef TF_FLOW_SCALE_QUERY + /* CFA update usage state when moved entries */ + if (entry_moved) { + if (tf_tcam_usage_update(context->tfp->session->session_id.id, + parms->dir, + parms->type, + to_row, + TF_RESC_ALLOC)) { + CFA_TCAM_MGR_TRACE(DEBUG, "TF tcam usage update failed\n"); + } + if (tf_tcam_usage_update(context->tfp->session->session_id.id, + parms->dir, + parms->type, + from_row, + TF_RESC_FREE)) { + CFA_TCAM_MGR_TRACE(DEBUG, "TF tcam usage update failed\n"); + } + } +#endif /* TF_FLOW_SCALE_QUERY */ + if (ROW_INUSE(from_row)) entry_moved = false; else @@ -1207,6 +1219,11 @@ cfa_tcam_mgr_bind(struct cfa_tcam_mgr_context *context, return rc; } +#ifdef TF_FLOW_SCALE_QUERY + /* Initialize the WC TCAM usage state */ + tf_tcam_usage_init(tfp); +#endif /* TF_FLOW_SCALE_QUERY */ + return 0; } @@ -1352,6 +1369,17 @@ cfa_tcam_mgr_alloc(struct cfa_tcam_mgr_context *context, parms->id = new_entry_id; +#ifdef TF_FLOW_SCALE_QUERY + /* CFA update usage state */ + if (tf_tcam_usage_update(session_id, + parms->dir, + parms->type, + row, + TF_RESC_ALLOC)) { + CFA_TCAM_MGR_TRACE(DEBUG, "TF tcam usage update failed\n"); + } +#endif /* TF_FLOW_SCALE_QUERY */ + return 0; } @@ -1443,6 +1471,17 @@ cfa_tcam_mgr_free(struct cfa_tcam_mgr_context *context, table_data->max_slices); ROW_ENTRY_CLEAR(row, entry->slice); +#ifdef TF_FLOW_SCALE_QUERY + /* CFA update usage state */ + if (tf_tcam_usage_update(session_id, + parms->dir, + parms->type, + row, + TF_RESC_FREE)) { + CFA_TCAM_MGR_TRACE(DEBUG, "TF tcam usage update failed\n"); + } +#endif /* TF_FLOW_SCALE_QUERY */ + new_row_to_free = entry->row; cfa_tcam_mgr_rows_combine(sess_idx, context, parms, table_data, new_row_to_free); diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_device.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_device.h index 6ab9b5e118..c24e5c8389 100644 --- a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_device.h +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_device.h @@ -42,6 +42,15 @@ TF_TCAM_TABLE_ROWS_DEF(2); TF_TCAM_TABLE_ROWS_DEF(4); TF_TCAM_TABLE_ROWS_DEF(8); +/* + * The following macros are for setting the entry status in a row entry. + * row is (struct cfa_tcam_mgr_table_rows_0 *) + */ +#define ROW_ENTRY_INUSE(row, entry) ((row)->entry_inuse & (1U << (entry))) +#define ROW_ENTRY_SET(row, entry) ((row)->entry_inuse |= (1U << (entry))) +#define ROW_ENTRY_CLEAR(row, entry) ((row)->entry_inuse &= ~(1U << (entry))) +#define ROW_INUSE(row) ((row)->entry_inuse != 0) + #define TF_TCAM_MAX_ENTRIES (L2_CTXT_TCAM_RX_MAX_ENTRIES + \ L2_CTXT_TCAM_TX_MAX_ENTRIES + \ PROF_TCAM_RX_MAX_ENTRIES + \ diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.c b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.c index 3d085bc69e..40bbcc54c8 100644 --- a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.c +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.c @@ -74,6 +74,19 @@ cfa_tcam_mgr_session_find(unsigned int session_id) return -CFA_TCAM_MGR_ERR_CODE(INVAL); } +int +cfa_tcam_mgr_session_empty(void) +{ + unsigned int sess_idx; + + for (sess_idx = 0; sess_idx < ARRAY_SIZE(session_data); sess_idx++) { + if (session_data[sess_idx].session_id) + return 0; + } + + return 1; +} + int cfa_tcam_mgr_session_add(unsigned int session_id) { diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.h index 69311b7e1d..7e75776686 100644 --- a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.h +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.h @@ -19,6 +19,9 @@ cfa_tcam_mgr_get_session_from_context(struct cfa_tcam_mgr_context *context, int cfa_tcam_mgr_session_find(unsigned int session_id); +int +cfa_tcam_mgr_session_empty(void); + int cfa_tcam_mgr_session_add(unsigned int session_id); diff --git a/drivers/net/bnxt/tf_core/meson.build b/drivers/net/bnxt/tf_core/meson.build index 13a71738a0..7d38ab8793 100644 --- a/drivers/net/bnxt/tf_core/meson.build +++ b/drivers/net/bnxt/tf_core/meson.build @@ -30,6 +30,7 @@ sources += files( 'tf_msg.c', 'tfp.c', 'tf_rm.c', + 'tf_resources.c', 'tf_session.c', 'tf_sram_mgr.c', 'tf_tbl.c', diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index 3a812bee3a..1c728aadd8 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -1101,6 +1101,21 @@ tf_alloc_tbl_entry(struct tf *tfp, parms->idx = idx; +#ifdef TF_FLOW_SCALE_QUERY + /* Update resource usage buffer */ + if (!rc && dev->ops->tf_dev_update_tbl_usage_buffer) { + rc = dev->ops->tf_dev_update_tbl_usage_buffer(tfs->session_id.id, + parms->dir, + parms->type, + TF_RESC_ALLOC); + if (rc) { + TFP_DRV_LOG(DEBUG, + "%s: Table usage update failed!\n", + tf_dir_2_str(parms->dir)); + } + } +#endif /* TF_FLOW_SCALE_QUERY */ + return 0; } @@ -1181,6 +1196,22 @@ tf_free_tbl_entry(struct tf *tfp, return rc; } } + +#ifdef TF_FLOW_SCALE_QUERY + /* Update resource usage buffer */ + if (!rc && dev->ops->tf_dev_update_tbl_usage_buffer) { + rc = dev->ops->tf_dev_update_tbl_usage_buffer(tfs->session_id.id, + parms->dir, + parms->type, + TF_RESC_FREE); + if (rc) { + TFP_DRV_LOG(DEBUG, + "%s: Table usage update failed!\n", + tf_dir_2_str(parms->dir)); + } + } +#endif /* TF_FLOW_SCALE_QUERY */ + return 0; } @@ -2027,3 +2058,122 @@ int tf_get_session_hotup_state(struct tf *tfp, return rc; } + +#ifdef TF_FLOW_SCALE_QUERY +/* Update TF resource usage state with firmware */ +int tf_update_resc_usage(struct tf *tfp, + enum tf_dir dir, + enum tf_flow_resc_type flow_resc_type) +{ + int rc; + struct tf_session *tfs; + struct tf_dev_info *dev; + TF_CHECK_PARMS1(tfp); + + /* Retrieve the session information */ + rc = tf_session_get_session(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup session, rc:%s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup device, rc:%s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } + + /* Support Thor(P5) on the first session */ + if (dev->type != TF_DEVICE_TYPE_P5 || tfs->session_id.internal.fw_session_id) + return rc; + + if (dev->ops->tf_dev_update_resc_usage == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "%s: Operation not supported, rc:%s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } + + rc = dev->ops->tf_dev_update_resc_usage(tfp, dir, flow_resc_type); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Flow resource usage update failed, rc:%s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } + + TFP_DRV_LOG(DEBUG, + "%s: Flow resource usage updated: usage type %d\n", + tf_dir_2_str(dir), flow_resc_type); + + return 0; +} + +/* Get TF resource usage state from firmware*/ +int tf_query_resc_usage(struct tf *tfp, + struct tf_query_resc_usage_parms *parms) +{ + int rc; + struct tf_session *tfs; + struct tf_dev_info *dev; + + TF_CHECK_PARMS2(tfp, parms); + + /* Retrieve the session information */ + rc = tf_session_get_session(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup session, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup device, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + /* Support Thor(P5) on the first session */ + if (dev->type != TF_DEVICE_TYPE_P5 || tfs->session_id.internal.fw_session_id) + return rc; + + if (dev->ops->tf_dev_query_resc_usage == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "%s: Operation not supported, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + rc = dev->ops->tf_dev_query_resc_usage(tfp, parms); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Flow resource usage query failed, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + TFP_DRV_LOG(DEBUG, + "%s: Flow resource usage query successfully: usage type %d\n", + tf_dir_2_str(parms->dir), parms->flow_resc_type); + return 0; +} +#endif /* TF_FLOW_SCALE_QUERY */ diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index fd1ee2f454..90637c6508 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -2584,4 +2584,56 @@ struct tf_get_sram_policy_parms { */ int tf_get_sram_policy(struct tf *tfp, struct tf_get_sram_policy_parms *parms); + +#ifdef TF_FLOW_SCALE_QUERY +enum tf_flow_resc_type { + TF_FLOW_RESC_TYPE_WCTCAM, + TF_FLOW_RESC_TYPE_EM, + TF_FLOW_RESC_TYPE_METER, + TF_FLOW_RESC_TYPE_COUNTER, + TF_FLOW_RESC_TYPE_ACTION, + TF_FLOW_RESC_TYPE_ACT_MOD_ENCAP, + TF_FLOW_RESC_TYPE_SP_SMAC, + TF_FLOW_RESC_TYPE_ALL, +}; + +/** + * Update TF resource usage state with firmware + * + * Returns success or failure code. + */ +int tf_update_resc_usage(struct tf *tfp, + enum tf_dir dir, + enum tf_flow_resc_type flow_resc_type); + +/** + * tf_query_resc_usage parameter definition + */ +struct tf_query_resc_usage_parms { + /** + * [in] receive or transmit direction + */ + enum tf_dir dir; + /** + * [in] RESC type + */ + enum tf_flow_resc_type flow_resc_type; + /** + * [in] received buffer size + */ + uint32_t size; + /** + * [out] buffer for query data + */ + uint8_t data[96]; +}; +/** + * Get TF resource usage state from firmware + * + * Returns success or failure code. + */ +int tf_query_resc_usage(struct tf *tfp, + struct tf_query_resc_usage_parms *parms); + +#endif /* TF_FLOW_SCALE_QUERY */ #endif /* _TF_CORE_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index 06c17a7212..0b0ca8b42f 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -1127,6 +1127,71 @@ struct tf_dev_ops { */ int (*tf_dev_get_sram_policy)(enum tf_dir dir, enum tf_sram_bank_id *bank_id); + +#ifdef TF_FLOW_SCALE_QUERY + /** + * Update resource usage state with firmware + * + * [in] tfp + * Pointer to TF handle + * + * [in] dir + * Receive or transmit direction + * + * [in] flow_resc_type + * Resource type to update its usage state + * + * returns: + * 0 - Success + * -EINVAL - Error + */ + int (*tf_dev_update_resc_usage)(struct tf *tfp, + enum tf_dir dir, + enum tf_flow_resc_type flow_resc_type); + + /** + * Query resource usage state from firmware + * + * [in] tfp + * Pointer to TF handle + * + * [in] dir + * Receive or transmit direction + * + * [in] flow_resc_type + * Resource type to query its usage state + * + * returns: + * 0 - Success + * -EINVAL - Error + */ + int (*tf_dev_query_resc_usage)(struct tf *tfp, + struct tf_query_resc_usage_parms *parms); + + /** + * Update buffer of table usage + * + * [in] session_id + * The TruFlow session id + * + * [in] dir + * Receive or transmit direction + * + * [in] tbl_type + * SRAM table type to update its usage state + * + * [in] resc_opt + * Alloca or free resource + * + * returns: + * 0 - Success + * -EINVAL - Error + */ + int (*tf_dev_update_tbl_usage_buffer)(uint32_t session_id, + enum tf_dir dir, + enum tf_tbl_type tbl_type, + uint32_t resc_opt); +#endif /* TF_FLOW_SCALE_QUERY */ }; /** diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index 4df1918bc5..6f6526e552 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -512,6 +512,11 @@ const struct tf_dev_ops tf_dev_ops_p4_init = { .tf_dev_get_sram_resources = NULL, .tf_dev_set_sram_policy = NULL, .tf_dev_get_sram_policy = NULL, +#ifdef TF_FLOW_SCALE_QUERY + .tf_dev_update_resc_usage = NULL, + .tf_dev_query_resc_usage = NULL, + .tf_dev_update_tbl_usage_buffer = NULL, +#endif /* TF_FLOW_SCALE_QUERY */ }; /** @@ -570,4 +575,9 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_get_sram_resources = NULL, .tf_dev_set_sram_policy = NULL, .tf_dev_get_sram_policy = NULL, +#ifdef TF_FLOW_SCALE_QUERY + .tf_dev_update_resc_usage = NULL, + .tf_dev_query_resc_usage = NULL, + .tf_dev_update_tbl_usage_buffer = NULL, +#endif /* TF_FLOW_SCALE_QUERY */ }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 51c260b5d7..8f915744a7 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -15,8 +15,10 @@ #include "tf_if_tbl.h" #include "tfp.h" #include "tf_msg_common.h" + #include "tf_msg.h" #include "tf_tbl_sram.h" #include "tf_util.h" +#include "tf_resources.h" #define TF_DEV_P58_PARIF_MAX 16 #define TF_DEV_P58_PF_MASK 0xfUL @@ -781,6 +783,99 @@ static int tf_dev_p58_get_sram_policy(enum tf_dir dir, return 0; } +#ifdef TF_FLOW_SCALE_QUERY +/** + * Update resource usage to firmware. + * + * [in] tfp + * Pointer to TF handle + * + * [in] dir + * Receive or transmit direction + * + * [in] flow_resc_type + * Types of the resource to update their usage state. + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p58_update_resc_usage(struct tf *tfp, + enum tf_dir dir, + enum tf_flow_resc_type flow_resc_type) +{ + int rc; + + struct cfa_tf_resc_usage *usage_state = &tf_resc_usage[dir]; + + flow_resc_type |= HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_ALL; + rc = tf_msg_set_resc_usage(tfp, + dir, + flow_resc_type, + sizeof(cfa_tf_resc_usage_t), + (uint8_t *)usage_state); + + return rc; +} + +/** + * Query resource usage from firmware. + * + * [in] tfp + * Pointer to TF handle + * + * [in/out] parms + * Pointer to parms structure + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p58_query_resc_usage(struct tf *tfp, + struct tf_query_resc_usage_parms *parms) +{ + int rc = 0; + + parms->size = sizeof(struct cfa_tf_resc_usage); + rc = tf_msg_query_resc_usage(tfp, + parms->dir, + parms->flow_resc_type, + &parms->size, + (void *)parms->data); + return rc; +} + +/** + * Update buffer of table usage state + * + * [in] session_id + * Pointer to TF handle + * + * [in] dir + * Receive or transmit direction + * + * [in] tbl_type + * SRAM table type to update its usage state + * + * [in] resc_opt + * Alloca or free resource + * + * returns: + * 0 - Success + * -EINVAL - Error + */ +static int +tf_dev_p58_update_tbl_usage_buffer(uint32_t session_id, + enum tf_dir dir, + enum tf_tbl_type tbl_type, + enum tf_resc_opt resc_opt) +{ + int rc; + rc = tf_tbl_usage_update(session_id, dir, tbl_type, resc_opt); + return rc; +} +#endif /* TF_FLOW_SCALE_QUERY */ + /** * Truflow P58 device specific functions */ @@ -835,6 +930,11 @@ const struct tf_dev_ops tf_dev_ops_p58_init = { .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources, .tf_dev_set_sram_policy = tf_dev_p58_set_sram_policy, .tf_dev_get_sram_policy = tf_dev_p58_get_sram_policy, +#ifdef TF_FLOW_SCALE_QUERY + .tf_dev_update_resc_usage = tf_dev_p58_update_resc_usage, + .tf_dev_query_resc_usage = tf_dev_p58_query_resc_usage, + .tf_dev_update_tbl_usage_buffer = tf_dev_p58_update_tbl_usage_buffer, +#endif /* TF_FLOW_SCALE_QUERY */ }; /** @@ -894,4 +994,9 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources, .tf_dev_set_sram_policy = tf_dev_p58_set_sram_policy, .tf_dev_get_sram_policy = tf_dev_p58_get_sram_policy, +#ifdef TF_FLOW_SCALE_QUERY + .tf_dev_update_resc_usage = tf_dev_p58_update_resc_usage, + .tf_dev_query_resc_usage = tf_dev_p58_query_resc_usage, + .tf_dev_update_tbl_usage_buffer = tf_dev_p58_update_tbl_usage_buffer, +#endif /* TF_FLOW_SCALE_QUERY */ }; diff --git a/drivers/net/bnxt/tf_core/tf_em_hash_internal.c b/drivers/net/bnxt/tf_core/tf_em_hash_internal.c index cb8da0e370..35589c9844 100644 --- a/drivers/net/bnxt/tf_core/tf_em_hash_internal.c +++ b/drivers/net/bnxt/tf_core/tf_em_hash_internal.c @@ -108,6 +108,15 @@ tf_em_hash_insert_int_entry(struct tf *tfp, rptr_entry, 0); dpool_set_entry_data(pool, index, parms->flow_handle); + +#ifdef TF_FLOW_SCALE_QUERY + /* Update usage state buffer for EM */ + tf_em_usage_update(tfs->session_id.id, + parms->dir, + num_of_entries, + TF_RESC_ALLOC); +#endif /* TF_FLOW_SCALE_QUERY */ + return 0; } @@ -124,6 +133,10 @@ tf_em_hash_delete_int_entry(struct tf *tfp, int rc = 0; struct tf_session *tfs; struct dpool *pool; +#ifdef TF_FLOW_SCALE_QUERY + uint32_t size; +#endif /* TF_FLOW_SCALE_QUERY */ + /* Retrieve the session information */ rc = tf_session_get_session(tfp, &tfs); if (rc) { @@ -137,11 +150,18 @@ tf_em_hash_delete_int_entry(struct tf *tfp, rc = tf_msg_delete_em_entry(tfp, parms); /* Return resource to pool */ - if (rc == 0) { - pool = (struct dpool *)tfs->em_pool[parms->dir]; - dpool_free(pool, parms->index); - } + pool = (struct dpool *)tfs->em_pool[parms->dir]; + +#ifdef TF_FLOW_SCALE_QUERY + /* Update usage state buffer for EM */ + size = DP_FLAGS_SIZE(pool->entry[parms->index - pool->start_index].flags); + tf_em_usage_update(tfs->session_id.id, + parms->dir, + size, + TF_RESC_FREE); +#endif /* TF_FLOW_SCALE_QUERY */ + dpool_free(pool, parms->index); return rc; } diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c index 46de63a9da..6dfefce2f2 100644 --- a/drivers/net/bnxt/tf_core/tf_em_internal.c +++ b/drivers/net/bnxt/tf_core/tf_em_internal.c @@ -293,6 +293,13 @@ tf_em_int_bind(struct tf *tfp, /* Logging handled in tf_create_em_pool */ if (rc) return rc; + +#ifdef TF_FLOW_SCALE_QUERY + /* Initialize the usage state buffer for EM */ + tf_em_usage_init(tfs->session_id.id, + i, + iparms.info->entry.stride); +#endif /* TF_FLOW_SCALE_QUERY */ } if (rc) { diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index 1ef828a1e9..f2d2de859c 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -1995,3 +1995,178 @@ tf_msg_session_get_hotup_state(struct tf *tfp, return rc; } + +#ifdef TF_FLOW_SCALE_QUERY +/* Send set resource usage request to the firmware. */ +int +tf_msg_set_resc_usage(struct tf *tfp, + enum tf_dir dir, + uint32_t resc_types, + uint32_t size, + uint8_t *data) +{ + int rc; + struct hwrm_tf_resc_usage_set_input req = { 0 }; + struct hwrm_tf_resc_usage_set_output resp = { 0 }; + struct tfp_send_msg_parms parms = { 0 }; + struct tf_msg_dma_buf buf = { 0 }; + uint8_t fw_session_id; + struct tf_dev_info *dev; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup session, rc:%s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup device, rc:%s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } + + rc = tf_session_get_fw_session_id(tfp, &fw_session_id); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Unable to lookup FW id, rc:%s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } + + /* Populate the request */ + req.fw_session_id = tfp_cpu_to_le_32(fw_session_id); + req.flags = tfp_cpu_to_le_16(dir); + req.types = tfp_cpu_to_le_32(resc_types); + req.size = tfp_cpu_to_le_16(size); +#if (TF_RM_MSG_DEBUG == 1) + /* Dump data */ + dump_tf_resc_usage(dir, data, size); +#endif /* (TF_RM_MSG_DEBUG == 1) */ + /* Check for data size conformity */ + if (size > sizeof(req.data)) { + /* use dma buffer */ + req.flags |= HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DMA; + rc = tf_msg_alloc_dma_buf(&buf, size); + if (rc) + goto exit; + tfp_memcpy(buf.va_addr, data, size); + tfp_memcpy(&req.data[0], + &buf.pa_addr, + sizeof(buf.pa_addr)); + } else { + tfp_memcpy(&req.data, data, size); + } + + parms.tf_type = HWRM_TF_RESC_USAGE_SET; + parms.req_data = (uint32_t *)&req; + parms.req_size = sizeof(req); + parms.resp_data = (uint32_t *)&resp; + parms.resp_size = sizeof(resp); + parms.mailbox = dev->ops->tf_dev_get_mailbox(); + + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), + &parms); + + /* Free dma buffer */ + if (size > sizeof(req.data)) + tf_msg_free_dma_buf(&buf); +exit: + return rc; +} + +/* Send query resource usage request to the firmware. */ +int tf_msg_query_resc_usage(struct tf *tfp, + enum tf_dir dir, + uint32_t resc_types, + uint32_t *size, + uint8_t *data) +{ + int rc; + struct hwrm_tf_resc_usage_query_input req = { 0 }; + struct hwrm_tf_resc_usage_query_output resp = { 0 }; + struct tfp_send_msg_parms parms = { 0 }; + uint8_t fw_session_id; + struct tf_dev_info *dev; + struct tf_session *tfs; + uint32_t flags = 0; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup session, rc:%s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to lookup device, rc:%s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } + + rc = tf_session_get_fw_session_id(tfp, &fw_session_id); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Unable to lookup FW id, rc:%s\n", + tf_dir_2_str(dir), + strerror(-rc)); + return rc; + } + flags = (dir == TF_DIR_TX ? + HWRM_TF_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_TX : + HWRM_TF_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_RX); + + /* Populate the request */ + req.fw_session_id = tfp_cpu_to_le_32(fw_session_id); + req.flags = tfp_cpu_to_le_16(flags); + req.types = tfp_cpu_to_le_32(resc_types); + + parms.tf_type = HWRM_TF_RESC_USAGE_QUERY; + parms.req_data = (uint32_t *)&req; + parms.req_size = sizeof(req); + parms.resp_data = (uint32_t *)&resp; + parms.resp_size = sizeof(resp); + parms.mailbox = dev->ops->tf_dev_get_mailbox(); + + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), + &parms); + if (rc) + return rc; + + /* The response size should be less than or equal to (<=) the input buffer size. */ + if (resp.size > *size) + return -EINVAL; + + *size = resp.size; + + /* + * Copy the requested number of bytes + */ + tfp_memcpy(data, + &resp.data, + resp.size); + +#if (TF_RM_MSG_DEBUG == 1) + /* dump data */ + dump_tf_resc_usage(dir, data, resp.size); +#endif /* (TF_RM_MSG_DEBUG == 1) */ + + return 0; +} +#endif /* TF_FLOW_SCALE_QUERY */ diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h index 24d0ae5f43..f3364c1518 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.h +++ b/drivers/net/bnxt/tf_core/tf_msg.h @@ -797,4 +797,61 @@ int tf_msg_session_get_hotup_state(struct tf *tfp, uint16_t *state, uint16_t *ref_cnt); + +#ifdef TF_FLOW_SCALE_QUERY +/** + * Send set resource usage request to the firmware. + * + * [in] tfp + * Pointer to session handle + * + * [in] dir + * Receive or Transmit direction + * + * [in] resc_types + * Type of resource to update its usage state + * + * [in] size + * The size of data buffer + * + * [in] data + * Pointer of the resource usage state + * + * Returns: + * 0 on Success else internal Truflow error + */ +int tf_msg_set_resc_usage(struct tf *tfp, + enum tf_dir dir, + uint32_t resc_types, + uint32_t size, + uint8_t *data); + +/** + * Send query resource usage request to the firmware. + * + * [in] tfp + * Pointer to session handle + * + * [in] dir + * Receive or Transmit direction + * + * [in] resc_types + * Type of resource to update its usage state + * + * [in/out] size + * Pointer to the size of data buffer + * + * [out] data + * Pointer of the resource usage state + * + * Returns: + * 0 on Success else internal Truflow error + */ +int tf_msg_query_resc_usage(struct tf *tfp, + enum tf_dir dir, + uint32_t resc_types, + uint32_t *size, + uint8_t *data); +#endif /* TF_FLOW_SCALE_QUERY */ + #endif /* _TF_MSG_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_resources.c b/drivers/net/bnxt/tf_core/tf_resources.c new file mode 100644 index 0000000000..4c64d23b86 --- /dev/null +++ b/drivers/net/bnxt/tf_core/tf_resources.c @@ -0,0 +1,608 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019-2023 Broadcom + * All rights reserved. + */ + +/* Truflow Table APIs and supporting code */ + +#include + +#include "tf_tbl.h" +#include "tf_common.h" +#include "tf_rm.h" +#include "tf_util.h" +#include "tf_msg.h" +#include "tfp.h" +#include "tf_session.h" +#include "tf_device.h" +#include "cfa_tcam_mgr_device.h" +#include "cfa_tcam_mgr_session.h" + +#ifdef TF_FLOW_SCALE_QUERY + +/* Logging defines */ +#define TF_FLOW_SCALE_QUERY_DEBUG 0 + +/* global data stored in firmware memory and TruFlow driver*/ +struct cfa_tf_resc_usage tf_resc_usage[TF_DIR_MAX]; + +struct tf_resc_usage_buffer_control { + enum tf_device_type device_type; + bool fw_sync_paused; + uint32_t buffer_dirty[TF_DIR_MAX]; +}; + +static struct tf_resc_usage_buffer_control resc_usage_control; + +/* Check if supporting resource usage */ +static bool tf_resc_usage_support(int session_id) +{ + bool support = true; + int sess_idx; + + /* Not valid session id */ + if (!session_id) + return false; + + /* Support Generic template with one session */ + sess_idx = cfa_tcam_mgr_session_find(session_id); + if (sess_idx < 0 && !cfa_tcam_mgr_session_empty()) + support = false; + + /* Support Thor */ + if (resc_usage_control.device_type != TF_DEVICE_TYPE_P5) + support = false; + +#if (TF_FLOW_SCALE_QUERY_DEBUG == 1) + TFP_DRV_LOG(INFO, "Resc usage update sess_id: %x, idx: %d, type: %d, allow: %s\n", + session_id, + sess_idx, + resc_usage_control.device_type, + support ? "True" : "False"); +#endif /* TF_FLOW_SCALE_QUERY_DEBUG == 1 */ + return support; +} + +/* Reset the resource usage buffer */ +void tf_resc_usage_reset(enum tf_device_type type, int session_id) +{ + /* Check if supported on this device */ + if (cfa_tcam_mgr_session_find(session_id) > 0) + return; + + /* Support Thor only*/ + if (type != TF_DEVICE_TYPE_P5) + return; + + resc_usage_control.fw_sync_paused = false; + resc_usage_control.device_type = type; + resc_usage_control.buffer_dirty[TF_DIR_RX] = 1; + resc_usage_control.buffer_dirty[TF_DIR_TX] = 1; + memset(tf_resc_usage, 0, sizeof(tf_resc_usage)); +} + +/* Check the bumber of the used slices in a row */ +static int +tf_tcam_mgr_row_entry_used(struct cfa_tcam_mgr_table_rows_0 *row, + int max_slices) +{ + int used = 0, j; + + for (j = 0; j < (max_slices / row->entry_size); j++) { + if (ROW_ENTRY_INUSE(row, j)) + used++; + } + return used; +} + +/* Initialize the resource usage buffer for WC-TCAM tables */ +void tf_tcam_usage_init(int session_id) +{ + enum tf_dir dir; + enum cfa_tcam_mgr_tbl_type type = CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS; + struct cfa_tcam_mgr_table_data *table_data = NULL; + struct tf_resc_wc_tcam_usage *usage_data = NULL; + int sess_idx = cfa_tcam_mgr_session_find(session_id); + + /* Check if supported on this device */ + if (!tf_resc_usage_support(session_id)) + return; + + /* Iterate over all directions */ + for (dir = 0; dir < TF_DIR_MAX; dir++) { + table_data = &cfa_tcam_mgr_tables[sess_idx][dir][type]; + usage_data = &tf_resc_usage[dir].wc_tcam_usage; + + /* cfa_tcam_mgr_table_dump(session_id, dir, type); */ + memset(usage_data, 0, sizeof(*usage_data)); + if (table_data->start_row != table_data->end_row) + usage_data->max_row_number = table_data->end_row - + table_data->start_row + 1; + usage_data->unused_row_number = usage_data->max_row_number; + +#if (TF_FLOW_SCALE_QUERY_DEBUG == 1) + /* dump usage data */ + CFA_TCAM_MGR_LOG(INFO, "WC-TCAM: 1-p 1-f 2-p 2-f 4-f free-rows\n"); + CFA_TCAM_MGR_LOG(INFO, "%s %-4d %-4d %-4d %-4d %-4d %-4d\n", + (dir == TF_DIR_RX) ? "RX" : "TX", + usage_data->slice_row_1_p_used, + usage_data->slice_row_1_f_used, + usage_data->slice_row_2_p_used, + usage_data->slice_row_2_f_used, + usage_data->slice_row_4_used, + usage_data->unused_row_number); +#endif + } +} + +/* Update wc-tcam table resoure usage */ +int tf_tcam_usage_update(int session_id, + enum tf_dir dir, + int tcam_tbl_type, + void *data, + enum tf_resc_opt resc_opt) +{ + struct tf_resc_wc_tcam_usage *usage_data; + int used_entries; + struct cfa_tcam_mgr_table_rows_0 *key_row = (struct cfa_tcam_mgr_table_rows_0 *)data; + int key_slices = key_row->entry_size; + + /* Check if supported on this device */ + if (!tf_resc_usage_support(session_id)) + return -1; + + /* Support WC-TCAM APPs only */ + if (tcam_tbl_type != CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS) + return 0; + + resc_usage_control.buffer_dirty[dir] = 1; + usage_data = &tf_resc_usage[dir].wc_tcam_usage; + if (resc_opt == TF_RESC_ALLOC) { + switch (key_slices) { + case 4: + usage_data->unused_row_number -= 1; + usage_data->slice_row_4_used += 1; + break; + case 2: + used_entries = tf_tcam_mgr_row_entry_used(key_row, 4); + if (used_entries == 2) { + usage_data->slice_row_2_p_used -= 1; + usage_data->slice_row_2_f_used += 1; + } else { + usage_data->unused_row_number -= 1; + usage_data->slice_row_2_p_used += 1; + } + break; + case 1: + used_entries = tf_tcam_mgr_row_entry_used(key_row, 4); + if (used_entries == 4) { + usage_data->slice_row_1_p_used -= 1; + usage_data->slice_row_1_f_used += 1; + } else if (used_entries == 1) { + usage_data->slice_row_1_p_used += 1; + usage_data->unused_row_number -= 1; + } + break; + default: + CFA_TCAM_MGR_LOG(ERR, "CFA invalid size of key slices: %d\n", key_slices); + break; + } + } else { /* free one entry */ + switch (key_slices) { + case 4: + usage_data->unused_row_number += 1; + usage_data->slice_row_4_used -= 1; + break; + case 2: + if (!ROW_INUSE(key_row)) { /* empty */ + usage_data->unused_row_number += 1; + usage_data->slice_row_2_p_used -= 1; + } else { + usage_data->slice_row_2_p_used += 1; + usage_data->slice_row_2_f_used -= 1; + } + break; + case 1: + used_entries = tf_tcam_mgr_row_entry_used(key_row, 4); + if (!ROW_INUSE(key_row)) { /* empty */ + usage_data->unused_row_number += 1; + usage_data->slice_row_1_p_used -= 1; + } else if (used_entries == 3) { + usage_data->slice_row_1_f_used -= 1; + usage_data->slice_row_1_p_used += 1; + } + break; + default: + CFA_TCAM_MGR_LOG(ERR, "CFA invalid size of key slices: %d\n", key_slices); + break; + } + } + +#if (TF_FLOW_SCALE_QUERY_DEBUG == 1) + /* dump usage data*/ + CFA_TCAM_MGR_LOG(INFO, "WC-TCAM: 1-p 1-f 2-p 2-f 4-f free-rows\n"); + CFA_TCAM_MGR_LOG(INFO, " %-4d %-4d %-4d %-4d %-4d %-4d\n", + usage_data->slice_row_1_p_used, + usage_data->slice_row_1_f_used, + usage_data->slice_row_2_p_used, + usage_data->slice_row_2_f_used, + usage_data->slice_row_4_used, + usage_data->unused_row_number); +#endif + return 0; +} + +/* Initialize the EM usage table */ +void tf_em_usage_init(uint32_t session_id, enum tf_dir dir, uint16_t max_entries) +{ + struct tf_resc_em_usage *em; + + /* Check if supported on this device */ + if (!tf_resc_usage_support(session_id)) + return; + + em = &tf_resc_usage[dir].em_int_usage; + em->max_entries = max_entries; + em->used_entries = 0; +} + +/* Update the EM usage table */ +int tf_em_usage_update(uint32_t session_id, + enum tf_dir dir, + uint16_t size, + enum tf_resc_opt resc_opt) +{ + struct tf_resc_em_usage *em; + +#if (TF_FLOW_SCALE_QUERY_DEBUG == 1) + CFA_TCAM_MGR_LOG(INFO, "%s: %s: EM record size: %d, %s\n", + __func__, + dir ? "TX" : "RX", + size, + resc_opt == TF_RESC_ALLOC ? "Alloc" : "Free"); +#endif /* TF_FLOW_SCALE_QUERY_DEBUG == 1 */ + + /* Check if supported on this device */ + if (!tf_resc_usage_support(session_id)) + return -1; + + /* not valid size */ + if (!size) + return 0; + + resc_usage_control.buffer_dirty[dir] = 1; + em = &tf_resc_usage[dir].em_int_usage; + if (resc_opt == TF_RESC_ALLOC) { + em->used_entries += size; + assert(em->used_entries <= em->max_entries); + } else { + assert(em->used_entries >= size); + em->used_entries -= size; + } + return 0; +} + +/* Initialize the usage buffer for all kinds of sram tables */ +void tf_tbl_usage_init(uint32_t session_id, + enum tf_dir dir, + uint32_t tbl_type, + uint16_t max_entries) +{ + struct tf_rm_element_cfg *tbl_cfg = tf_tbl_p58[dir]; + +#if (TF_FLOW_SCALE_QUERY_DEBUG == 1) + CFA_TCAM_MGR_LOG(INFO, "%s: %s: tbl_type: %d[%s], max entries: [%d]:[0x%x]\n", + __func__, + dir ? "TX" : "RX", + tbl_type, + tf_tbl_type_2_str(tbl_type), + max_entries, + max_entries); +#endif /* TF_FLOW_SCALE_QUERY_DEBUG == 1 */ + + /* Check if supported on this device */ + if (!tf_resc_usage_support(session_id)) + return; + + /* Convert to entries */ + if (tbl_cfg[tbl_type].slices) + max_entries *= (16 / tbl_cfg[tbl_type].slices); + + switch (tbl_type) { + /* Counter Action */ + case TF_TBL_TYPE_ACT_STATS_64: + { + struct tf_resc_cnt_usage *cnt; + cnt = &tf_resc_usage[dir].cnt_usage; + cnt->max_entries = max_entries; + cnt->used_entries = 0; + break; + } + /* Action Recrod */ + case TF_TBL_TYPE_COMPACT_ACT_RECORD: + case TF_TBL_TYPE_FULL_ACT_RECORD: + { + struct tf_resc_act_usage *act; + act = &tf_resc_usage[dir].act_usage; + act->max_entries += max_entries; + act->free_entries += max_entries; + act->num_compact_act_records = 0; + act->num_full_act_records = 0; + break; + } + /* ACT_ENCAP adn ACT_MODIFY Records */ + case TF_TBL_TYPE_ACT_ENCAP_8B: + case TF_TBL_TYPE_ACT_ENCAP_16B: + case TF_TBL_TYPE_ACT_ENCAP_32B: + case TF_TBL_TYPE_ACT_ENCAP_64B: + case TF_TBL_TYPE_ACT_ENCAP_128B: + case TF_TBL_TYPE_ACT_MODIFY_8B: + case TF_TBL_TYPE_ACT_MODIFY_16B: + case TF_TBL_TYPE_ACT_MODIFY_32B: + case TF_TBL_TYPE_ACT_MODIFY_64B: + { + struct tf_resc_act_mod_enc_usage *mod_encap; + mod_encap = &tf_resc_usage[dir].mod_encap_usage; + mod_encap->max_entries += max_entries; + mod_encap->free_entries += max_entries; + break; + } + /* SP_SMAC Record */ + case TF_TBL_TYPE_ACT_SP_SMAC: + case TF_TBL_TYPE_ACT_SP_SMAC_IPV4: + case TF_TBL_TYPE_ACT_SP_SMAC_IPV6: + { + struct tf_resc_act_sp_smac_usage *sp_smac; + sp_smac = &tf_resc_usage[dir].sp_smac_usage; + sp_smac->max_entries += max_entries; + sp_smac->free_entries += max_entries; + break; + } + /** Meter Profiles */ + case TF_TBL_TYPE_METER_PROF: + tf_resc_usage[dir].meter_usage.max_meter_profile = max_entries; + break; + /** Meter Instance */ + case TF_TBL_TYPE_METER_INST: + tf_resc_usage[dir].meter_usage.max_meter_instance = max_entries; + break; + default: + break; + } +} + +/* Update the usage buffer for sram tables: add or free one entry */ +int tf_tbl_usage_update(uint32_t session_id, + enum tf_dir dir, + uint32_t tbl_type, + enum tf_resc_opt resc_opt) +{ + struct tf_rm_element_cfg *tbl_cfg = tf_tbl_p58[dir]; + struct tf_resc_cnt_usage *cnt; + int inc = (resc_opt == TF_RESC_ALLOC) ? 1 : -1; + int slices = tbl_cfg[tbl_type].slices; + int entries = 0; + + /* Check if supported on this device */ + if (!tf_resc_usage_support(session_id)) + return -1; + + /* Convert to entries */ + if (slices) + entries = inc * (16 / slices); + +#if (TF_FLOW_SCALE_QUERY_DEBUG == 1) + TFP_DRV_LOG(INFO, "%s: %s: tbl_type: %d[%s] %s, Entries: %d\n", __func__, + dir ? "TX" : "RX", + tbl_type, + tf_tbl_type_2_str(tbl_type), + resc_opt ? "Alloc" : "Free", + entries); +#endif /* TF_FLOW_SCALE_QUERY_DEBUG == 1 */ + + resc_usage_control.buffer_dirty[dir] = 1; + switch (tbl_type) { + /* Counter Action */ + case TF_TBL_TYPE_ACT_STATS_64: + cnt = &tf_resc_usage[dir].cnt_usage; + cnt->used_entries += inc; + break; + /* ACTION Record */ + case TF_TBL_TYPE_FULL_ACT_RECORD: + case TF_TBL_TYPE_COMPACT_ACT_RECORD: + { + struct tf_resc_act_usage *act; + act = &tf_resc_usage[dir].act_usage; + if (tbl_type == TF_TBL_TYPE_COMPACT_ACT_RECORD) + act->num_compact_act_records += inc; + else + act->num_full_act_records += inc; + act->free_entries -= entries; + break; + } + /* ACT_ENCAP and ACT_MODIFY Records */ + case TF_TBL_TYPE_ACT_ENCAP_8B: + case TF_TBL_TYPE_ACT_ENCAP_16B: + case TF_TBL_TYPE_ACT_ENCAP_32B: + case TF_TBL_TYPE_ACT_ENCAP_64B: + case TF_TBL_TYPE_ACT_ENCAP_128B: + case TF_TBL_TYPE_ACT_MODIFY_8B: + case TF_TBL_TYPE_ACT_MODIFY_16B: + case TF_TBL_TYPE_ACT_MODIFY_32B: + case TF_TBL_TYPE_ACT_MODIFY_64B: + { + struct tf_resc_act_mod_enc_usage *mod_encap; + mod_encap = &tf_resc_usage[dir].mod_encap_usage; + switch (slices) { + case 1: + mod_encap->data.num_128b_records += inc; + break; + case 2: + mod_encap->data.num_64b_records += inc; + break; + case 4: + mod_encap->data.num_32b_records += inc; + break; + case 8: + mod_encap->data.num_16b_records += inc; + break; + case 16: + mod_encap->data.num_8b_records += inc; + break; + default: + break; + } + mod_encap->free_entries -= entries; + break; + } + /* SP SMAC table */ + case TF_TBL_TYPE_ACT_SP_SMAC: + case TF_TBL_TYPE_ACT_SP_SMAC_IPV4: + case TF_TBL_TYPE_ACT_SP_SMAC_IPV6: + { + struct tf_resc_act_sp_smac_usage *sp_smac; + sp_smac = &tf_resc_usage[dir].sp_smac_usage; + if (tbl_type == TF_TBL_TYPE_ACT_SP_SMAC) + sp_smac->num_sp_smac_records += inc; + else if (tbl_type == TF_TBL_TYPE_ACT_SP_SMAC_IPV4) + sp_smac->num_sp_smac_ipv4_records += inc; + else if (tbl_type == TF_TBL_TYPE_ACT_SP_SMAC_IPV6) + sp_smac->num_sp_smac_ipv6_records += inc; + sp_smac->free_entries -= entries; + break; + } + /* Meter Profiles */ + case TF_TBL_TYPE_METER_PROF: + tf_resc_usage[dir].meter_usage.used_meter_profile += inc; + break; + /* Meter Instance */ + case TF_TBL_TYPE_METER_INST: + tf_resc_usage[dir].meter_usage.used_meter_instance += inc; + break; + default: + /* not support types */ + break; + } + return 0; +} + +/* pause usage state update with firmware */ +void tf_resc_pause_usage_update(void) +{ + resc_usage_control.fw_sync_paused = true; +} + +/* resume usage state update with firmware */ +void tf_resc_resume_usage_update(void) +{ + resc_usage_control.fw_sync_paused = false; +} + +/* check if paused the resource usage update with firmware */ +static bool tf_resc_usage_update_paused(void) +{ + return resc_usage_control.fw_sync_paused; +} + +/* resync all resource usage state with firmware for both direction */ +void tf_resc_usage_update_all(struct bnxt *bp) +{ + struct tf *tfp; + enum tf_dir dir; + + /* When paused state update with firmware, do nothing */ + if (tf_resc_usage_update_paused()) + return; + + tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT); + if (!tfp || !tfp->session) { + BNXT_DRV_DBG(ERR, "Failed to get truflow or session pointer\n"); + return; + } + + /* Check if supported on this device */ + if (!tf_resc_usage_support(tfp->session->session_id.id)) + return; + + /* update usage state with firmware for each direction */ + for (dir = 0; dir < TF_DIR_MAX; dir++) { + if (resc_usage_control.buffer_dirty[dir]) { + tf_update_resc_usage(tfp, dir, TF_FLOW_RESC_TYPE_ALL); + resc_usage_control.buffer_dirty[dir] = 0; + } + } +} + +#if (TF_FLOW_SCALE_QUERY_DEBUG == 0) +void dump_tf_resc_usage(__rte_unused enum tf_dir dir, + __rte_unused void *data, + __rte_unused uint32_t size) +{ + /* empty routine */ +} +#else +void dump_tf_resc_usage(enum tf_dir dir, void *data, uint32_t size) +{ + struct cfa_tf_resc_usage *state = (struct cfa_tf_resc_usage *)data; + struct tf_resc_act_sp_smac_usage *sp_smac; + const unsigned char *bytebuffer = (const unsigned char *)data; + + printf("\n%s: Buffer Dump: Size: %u bytes\n", dir ? "TX" : "RX", size); + for (size_t i = 0; i < size; i++) { + printf("%02X ", bytebuffer[i]); + + /* Print a newline after every 16 bytes for better readability */ + if ((i + 1) % 16 == 0 || i == size - 1) + printf("\n"); + } + + printf("EM-----------------------------------------------------------------------\n"); + printf(" %4d: %4d\n", + state->em_int_usage.max_entries, + state->em_int_usage.used_entries); + printf("WC TCAM------------------------------------------------------------------\n"); + printf(" %4d(row): %4d %4d %4d %4d %4d %4d(free row)\n", + state->wc_tcam_usage.max_row_number, + state->wc_tcam_usage.slice_row_1_p_used, + state->wc_tcam_usage.slice_row_1_f_used, + state->wc_tcam_usage.slice_row_2_p_used, + state->wc_tcam_usage.slice_row_2_f_used, + state->wc_tcam_usage.slice_row_4_used, + state->wc_tcam_usage.unused_row_number); + printf("COUNTER------------------------------------------------------------------\n"); + printf(" %4d: %4d\n", + state->cnt_usage.max_entries, + state->cnt_usage.used_entries); + printf("METER------------------------------------------------------------------\n"); + printf(" %4d(Inst): %4d, %4d(Prof): %4d\n", + state->meter_usage.max_meter_instance, + state->meter_usage.used_meter_instance, + state->meter_usage.max_meter_profile, + state->meter_usage.used_meter_profile); + printf("ACTION-------------------------------------------------------------------\n"); + printf(" %4d(MAX): %4d(compact) %4d(full) %4d(free)\n", + state->act_usage.max_entries, + state->act_usage.num_compact_act_records, + state->act_usage.num_full_act_records, + state->act_usage.free_entries); + printf("SP SMAC------------------------------------------------------------------\n"); + sp_smac = &state->sp_smac_usage; + printf(" %4d(Max): %4d(8B) %4d(IPv4=16B) %4d(IPv6=32B) %4d(free)\n", + sp_smac->max_entries, + sp_smac->num_sp_smac_records, + sp_smac->num_sp_smac_ipv4_records, + sp_smac->num_sp_smac_ipv6_records, + sp_smac->free_entries); + printf("ACT MOD/ENCAP------------------------------------------------------------\n"); + printf(" %4d: %4d(8B) %4d(16B) %4d(32B) %4d(64B) %4d(128B) %4d(free)\n\n\n", + state->mod_encap_usage.max_entries, + state->mod_encap_usage.data.num_8b_records, + state->mod_encap_usage.data.num_16b_records, + state->mod_encap_usage.data.num_32b_records, + state->mod_encap_usage.data.num_64b_records, + state->mod_encap_usage.data.num_128b_records, + state->mod_encap_usage.free_entries); +} +#endif /* #if (TF_FLOW_SCALE_QUERY_DEBUG == 0) */ + +#endif /* TF_FLOW_SCALE_QUERY */ diff --git a/drivers/net/bnxt/tf_core/tf_resources.h b/drivers/net/bnxt/tf_core/tf_resources.h index 8c28d3dc68..715c9e0d94 100644 --- a/drivers/net/bnxt/tf_core/tf_resources.h +++ b/drivers/net/bnxt/tf_core/tf_resources.h @@ -5,6 +5,135 @@ #ifndef _TF_RESOURCES_H_ #define _TF_RESOURCES_H_ +#include +#include +#include "bnxt.h" #define TF_NUM_TBL_SCOPE 16 /* < Number of TBL scopes */ + +#ifdef TF_FLOW_SCALE_QUERY +/* Feature of flow scale query */ +enum tf_resc_opt { + TF_RESC_FREE, + TF_RESC_ALLOC +}; + +/** + * WC TCAM includes a set of rows, and each row have 4-slices; + * each slice has 160bit + */ +typedef struct tf_resc_wc_tcam_usage { + uint16_t max_row_number; /* Max number of rows (excluding AFM), 160bit row */ + uint16_t slice_row_1_p_used; /* 1-slice rows partially used */ + uint16_t slice_row_1_f_used; /* 1-slice rows fully used */ + uint16_t slice_row_2_p_used; /* 2-slice rows partially used */ + uint16_t slice_row_2_f_used; /* 2-slice rows fully used */ + uint16_t slice_row_4_used; /* 4-slice rows fully used */ + uint16_t unused_row_number; /* number of unused rows */ + uint8_t reserved[2]; +} __rte_packed tf_resc_wc_tcam_usage_t; + +/* Resource Internal EM memory pool; vary size records */ +typedef struct tf_resc_em_usage { + uint16_t max_entries; /* Max 16-Bytes entries */ + uint16_t used_entries; /* each record takes up to 7 entries by design */ +} __rte_packed tf_resc_em_usage_t; + +/* Resource Meter */ +typedef struct tf_resc_meter_usage { + uint16_t max_meter_instance; /* 1023 for Thor, app can reserve some entries */ + uint16_t max_meter_profile; /* 256 for Thor, app can reserve some profiles */ + uint16_t used_meter_instance; /* meter instance: fixed size record */ + uint16_t used_meter_profile; /* meter profile: fixed size record */ +} __rte_packed tf_resc_meter_usage_t; + +/* Resource Counter */ +typedef struct tf_resc_cnt_usage { + uint16_t max_entries; /* each counter take 64-Bytes */ + uint16_t used_entries; /* each record uses one entry */ +} __rte_packed tf_resc_cnt_usage_t; + +/* Resource Action */ +typedef struct tf_resc_act_usage { + uint16_t max_entries; /* Max 8-Bytes entries */ + uint16_t num_compact_act_records; /* 8-Bytes records */ + uint16_t num_full_act_records; /* 16-Bytes records */ + uint16_t free_entries; /* unused entries */ +} __rte_packed tf_resc_act_usage_t; + +/* Resource SP SMAC */ +typedef struct tf_resc_act_sp_smac_usage { + uint16_t max_entries; /* Max 8-Bytes entries */ + uint16_t num_sp_smac_records; /* 8-Bytes records */ + uint16_t num_sp_smac_ipv4_records; /* 8-Bytes records */ + uint16_t num_sp_smac_ipv6_records; /* 16-Bytes records */ + uint16_t free_entries; /* unused entries */ +} __rte_packed tf_resc_act_sp_smac_usage_t; + +/* Resource ACT MODIFY and ACT ENCAP */ +typedef struct tf_resc_act_mod_enc_usage { + uint16_t max_entries; /* Max 8-Bytes entries */ + struct { + uint16_t num_8b_records; /* 8-bytes records */ + uint16_t num_16b_records; /* 16-bytes records */ + uint16_t num_32b_records; /* 32-bytes records */ + uint16_t num_64b_records; /* 64-bytes records */ + uint16_t num_128b_records; /* 128-bytes records */ + } data; + int16_t free_entries; /* unused entries */ +} __rte_packed tf_resc_act_mod_enc_usage_t; + +/* All types of resource usage on both direction */ +typedef struct cfa_tf_resc_usage { + tf_resc_em_usage_t em_int_usage; + tf_resc_wc_tcam_usage_t wc_tcam_usage; + tf_resc_cnt_usage_t cnt_usage; + tf_resc_act_usage_t act_usage; + tf_resc_meter_usage_t meter_usage; + tf_resc_act_mod_enc_usage_t mod_encap_usage; + tf_resc_act_sp_smac_usage_t sp_smac_usage; +} __rte_packed cfa_tf_resc_usage_t; + +/* global data stored in firmware memory and TruFlow driver */ +extern cfa_tf_resc_usage_t tf_resc_usage[TF_DIR_MAX]; + +void tf_resc_usage_reset(enum tf_device_type type, int session_id); + +void tf_tcam_usage_init(int session_id); + +int tf_tcam_usage_update(int session_id, + enum tf_dir dir, + int tcam_tbl_type, + void *key_row, + enum tf_resc_opt resc_opt); + +void tf_em_usage_init(uint32_t session_id, enum tf_dir dir, uint16_t max_entries); + +int tf_em_usage_update(uint32_t session_id, + enum tf_dir dir, + uint16_t size, + enum tf_resc_opt resc_opt); + +void tf_tbl_usage_init(uint32_t session_id, + enum tf_dir dir, + uint32_t tbl_type, + uint16_t max_entries); + +int tf_tbl_usage_update(uint32_t session_id, + enum tf_dir dir, + uint32_t tbl_type, + enum tf_resc_opt resc_opt); + +void dump_tf_resc_usage(enum tf_dir dir, void *data, uint32_t size); + +extern struct tf_rm_element_cfg tf_tbl_p58[TF_DIR_MAX][TF_TBL_TYPE_MAX]; + +void tf_resc_pause_usage_update(void); + +void tf_resc_resume_usage_update(void); + +void tf_resc_usage_update_all(struct bnxt *bp); + +#endif /* TF_FLOW_SCALE_QUERY */ + #endif /* _TF_RESOURCES_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c index 9b85f5397d..e38bfcf4f6 100644 --- a/drivers/net/bnxt/tf_core/tf_rm.c +++ b/drivers/net/bnxt/tf_core/tf_rm.c @@ -364,7 +364,8 @@ tf_rm_update_parent_reservations(struct tf *tfp, struct tf_rm_element_cfg *cfg, uint16_t *alloc_cnt, uint16_t num_elements, - uint16_t *req_cnt) + uint16_t *req_cnt, + __rte_unused enum tf_dir dir) { int parent, child; const char *type_str = NULL; @@ -388,6 +389,13 @@ tf_rm_update_parent_reservations(struct tf *tfp, dev->ops->tf_dev_get_resource_str(tfp, cfg[parent].hcapi_type, &type_str); +#ifdef TF_FLOW_SCALE_QUERY + /* Initialize the usage buffer for SRAM tables */ + tf_tbl_usage_init(tfp, + dir, + parent, + alloc_cnt[parent]); +#endif /* TF_FLOW_SCALE_QUERY */ } /* Search again through all the elements */ @@ -418,6 +426,13 @@ tf_rm_update_parent_reservations(struct tf *tfp, combined_cnt += cnt; /* Clear the requested child count */ req_cnt[child] = 0; +#ifdef TF_FLOW_SCALE_QUERY + /* Initialize the usage buffer for SRAM tables */ + tf_tbl_usage_init(tfp->session->session_id.id, + dir, + child, + alloc_cnt[child]); +#endif /* TF_FLOW_SCALE_QUERY */ } } /* Save the parent count to be requested */ @@ -501,7 +516,8 @@ tf_rm_create_db(struct tf *tfp, tf_rm_update_parent_reservations(tfp, dev, parms->cfg, parms->alloc_cnt, parms->num_elements, - req_cnt); + req_cnt, + parms->dir); /* Process capabilities against DB requirements. However, as a * DB can hold elements that are not HCAPI we can reduce the @@ -672,6 +688,22 @@ tf_rm_create_db(struct tf *tfp, } } j++; + +#ifdef TF_FLOW_SCALE_QUERY + /* Initialize the usage buffer for Meter tables */ + if (cfg->hcapi_type == CFA_RESOURCE_TYPE_P58_METER || + cfg->hcapi_type == CFA_RESOURCE_TYPE_P58_METER_PROF) { + uint32_t tbl_type; + if (cfg->hcapi_type == CFA_RESOURCE_TYPE_P58_METER) + tbl_type = TF_TBL_TYPE_METER_INST; + else + tbl_type = TF_TBL_TYPE_METER_PROF; + tf_tbl_usage_init(tfp->session->session_id.id, + parms->dir, + tbl_type, + req_cnt[i]); + } +#endif /* TF_FLOW_SCALE_QUERY */ } else { /* Bail out as we want what we requested for * all elements, not any less. @@ -755,7 +787,8 @@ tf_rm_create_db_no_reservation(struct tf *tfp, tf_rm_update_parent_reservations(tfp, dev, parms->cfg, parms->alloc_cnt, parms->num_elements, - req_cnt); + req_cnt, + parms->dir); /* Process capabilities against DB requirements. However, as a * DB can hold elements that are not HCAPI we can reduce the diff --git a/drivers/net/bnxt/tf_core/tf_session.c b/drivers/net/bnxt/tf_core/tf_session.c index 253d716572..7545974c93 100644 --- a/drivers/net/bnxt/tf_core/tf_session.c +++ b/drivers/net/bnxt/tf_core/tf_session.c @@ -197,6 +197,11 @@ tf_session_create(struct tf *tfp, parms->open_cfg->shared_session_creator = true; } +#ifdef TF_FLOW_SCALE_QUERY + /* Reset the resource usage buffer before binding a device */ + tf_resc_usage_reset(parms->open_cfg->device_type, tfp->session->session_id.id); +#endif /* TF_FLOW_SCALE_QUERY */ + rc = tf_dev_bind(tfp, parms->open_cfg->device_type, &parms->open_cfg->resources, @@ -216,6 +221,11 @@ tf_session_create(struct tf *tfp, session->dev_init = true; +#ifdef TF_FLOW_SCALE_QUERY + /* Sync the initial resource usage with firmware */ + tf_resc_usage_update_all(parms->open_cfg->bp); +#endif /* TF_FLOW_SCALE_QUERY */ + return 0; cleanup: diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index 6d345e12c7..1e95905e21 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -4410,6 +4410,22 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx, goto flow_error; } +#ifdef TF_FLOW_SCALE_QUERY + tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT); + if (!tfp) { + BNXT_DRV_DBG(ERR, "Failed to get truflow pointer\n"); + return -EINVAL; + } + + if (parms->act_bitmap->bits & BNXT_ULP_FLOW_DIR_BITMASK_EGR) + dir = TF_DIR_TX; + else + dir = TF_DIR_RX; + + /* sync resource usage state with firmware */ + tf_update_resc_usage(tfp, dir, TF_FLOW_RESC_TYPE_ALL); +#endif /* TF_FLOW_SCALE_QUERY */ + return rc; flow_error: From patchwork Fri Aug 30 14:00:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sriharsha Basavapatna X-Patchwork-Id: 143471 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 03FA2458A8; Fri, 30 Aug 2024 15:52:06 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2F31342EC2; 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Fri, 30 Aug 2024 06:51:15 -0700 (PDT) From: Sriharsha Basavapatna To: dev@dpdk.org Cc: Sangtani Parag Satishbhai , Sriharsha Basavapatna Subject: [PATCH 07/47] net/bnxt: tf_core: fix slice count in case of HA entry move Date: Fri, 30 Aug 2024 19:30:09 +0530 Message-Id: <20240830140049.1715230-8-sriharsha.basavapatna@broadcom.com> X-Mailer: git-send-email 2.39.0.189.g4dbebc36b0 In-Reply-To: <20240830140049.1715230-1-sriharsha.basavapatna@broadcom.com> References: <20240830140049.1715230-1-sriharsha.basavapatna@broadcom.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sangtani Parag Satishbhai When entries are moved during HA, a shared move function transfers TCAM entries by using get/set message APIs, and the slice number of the entry is required to accomplish the movement. The slice number is calculated as the product of row_slice and entry size. Before calling get/set message APIs, the source entry size should be updated with the destination entry size; otherwise, it might corrupt the slice number field, which may result in writing an incorrect entry. A fix is made which now copies the entry size from the source to the destination before calling get/set message APIs, ensuring the correct slice number is modified. Signed-off-by: Sangtani Parag Satishbhai Reviewed-by: Sriharsha Basavapatna Signed-off-by: Sriharsha Basavapatna --- drivers/net/bnxt/tf_core/cfa_tcam_mgr.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c index 349f52caba..33b1e4121e 100644 --- a/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c @@ -1717,6 +1717,11 @@ cfa_tcam_mgr_shared_entry_move(int sess_idx, struct cfa_tcam_mgr_context *contex uint8_t key[CFA_TCAM_MGR_MAX_KEY_SIZE]; uint8_t mask[CFA_TCAM_MGR_MAX_KEY_SIZE]; uint8_t result[CFA_TCAM_MGR_MAX_KEY_SIZE]; + /* + * Copy entry size before moving else if + * slice number is non zero and entry size is zero it will cause issues + */ + dst_row->entry_size = src_row->entry_size; int rc; @@ -1791,7 +1796,6 @@ cfa_tcam_mgr_shared_entry_move(int sess_idx, struct cfa_tcam_mgr_context *contex ROW_ENTRY_SET(dst_row, dst_row_slice); dst_row->entries[dst_row_slice] = entry_id; - dst_row->entry_size = src_row->entry_size; dst_row->priority = src_row->priority; ROW_ENTRY_CLEAR(src_row, entry->slice); entry->row = dst_row_index; From patchwork Fri Aug 30 14:00:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sriharsha Basavapatna X-Patchwork-Id: 143472 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5BC3A458A8; Fri, 30 Aug 2024 15:52:16 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0866542EC6; Fri, 30 Aug 2024 15:51:23 +0200 (CEST) Received: from mail-pl1-f194.google.com (mail-pl1-f194.google.com [209.85.214.194]) by mails.dpdk.org (Postfix) with ESMTP id 80F3C42EB1 for ; Fri, 30 Aug 2024 15:51:21 +0200 (CEST) Received: by mail-pl1-f194.google.com with SMTP id d9443c01a7336-2053a0bd0a6so2543735ad.3 for ; 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Fri, 30 Aug 2024 06:51:19 -0700 (PDT) Received: from dhcp-10-123-154-23.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-205155658dfsm27067145ad.297.2024.08.30.06.51.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Aug 2024 06:51:18 -0700 (PDT) From: Sriharsha Basavapatna To: dev@dpdk.org Cc: Randy Schacher , Sriharsha Basavapatna , Farah Smith , Shuanglin Wang , Shahaji Bhosle Subject: [PATCH 08/47] net/bnxt: tf_core: convert priority based TCAM manager to dynamic allocation Date: Fri, 30 Aug 2024 19:30:10 +0530 Message-Id: <20240830140049.1715230-9-sriharsha.basavapatna@broadcom.com> X-Mailer: git-send-email 2.39.0.189.g4dbebc36b0 In-Reply-To: <20240830140049.1715230-1-sriharsha.basavapatna@broadcom.com> References: <20240830140049.1715230-1-sriharsha.basavapatna@broadcom.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Randy Schacher Previously, TCAM entries were allocated statically, but this takes up too much stack memory. Change the identifier for TCAM entries from an index which is tied to the HW location, to an abstract entry ID associated with the session. Signed-off-by: Randy Schacher Signed-off-by: Sriharsha Basavapatna Reviewed-by: Farah Smith Reviewed-by: Shuanglin Wang Reviewed-by: Shahaji Bhosle --- drivers/net/bnxt/tf_core/cfa_tcam_mgr.c | 1363 ++++++++++------- drivers/net/bnxt/tf_core/cfa_tcam_mgr.h | 58 +- .../net/bnxt/tf_core/cfa_tcam_mgr_device.h | 86 +- .../net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.c | 135 +- .../net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.h | 18 +- drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c | 596 ++++--- drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.h | 9 +- drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c | 586 ++++--- drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.h | 10 +- .../net/bnxt/tf_core/cfa_tcam_mgr_session.h | 57 - drivers/net/bnxt/tf_core/meson.build | 3 +- drivers/net/bnxt/tf_core/tf_core.c | 6 +- drivers/net/bnxt/tf_core/tf_device.h | 4 +- drivers/net/bnxt/tf_core/tf_device_p58.c | 6 +- .../net/bnxt/tf_core/tf_em_hash_internal.c | 6 +- drivers/net/bnxt/tf_core/tf_em_internal.c | 4 +- drivers/net/bnxt/tf_core/tf_resources.c | 185 ++- drivers/net/bnxt/tf_core/tf_resources.h | 16 +- drivers/net/bnxt/tf_core/tf_rm.c | 6 +- drivers/net/bnxt/tf_core/tf_session.c | 4 +- drivers/net/bnxt/tf_core/tf_session.h | 6 +- drivers/net/bnxt/tf_core/tf_tcam.c | 4 +- drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c | 55 +- 23 files changed, 1884 insertions(+), 1339 deletions(-) delete mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.h diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c index 33b1e4121e..165376182e 100644 --- a/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2021-2023 Broadcom + * Copyright(c) 2021-2024 Broadcom * All rights reserved. */ @@ -12,22 +12,13 @@ #include "tf_session.h" #include "tf_util.h" #include "cfa_tcam_mgr.h" -#include "cfa_tcam_mgr_hwop_msg.h" #include "cfa_tcam_mgr_device.h" -#include "cfa_tcam_mgr_session.h" +#include "cfa_tcam_mgr_hwop_msg.h" #include "cfa_tcam_mgr_p58.h" #include "cfa_tcam_mgr_p4.h" #define TF_TCAM_SLICE_INVALID (-1) -static struct cfa_tcam_mgr_entry_data *entry_data[TF_TCAM_MAX_SESSIONS]; - -static int global_data_initialized[TF_TCAM_MAX_SESSIONS]; -int cfa_tcam_mgr_max_entries[TF_TCAM_MAX_SESSIONS]; - -struct cfa_tcam_mgr_table_data -cfa_tcam_mgr_tables[TF_TCAM_MAX_SESSIONS][TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX]; - static int physical_table_types[CFA_TCAM_MGR_TBL_TYPE_MAX] = { [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS] = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, @@ -109,7 +100,7 @@ cfa_tcam_mgr_get_num_slices(unsigned int key_size, unsigned int slice_width) { int num_slices = 0; - if (key_size == 0) + if (!key_size) return -CFA_TCAM_MGR_ERR_CODE(INVAL); num_slices = ((key_size - 1U) / slice_width) + 1U; @@ -132,36 +123,43 @@ cfa_tcam_mgr_get_num_slices(unsigned int key_size, unsigned int slice_width) } static struct cfa_tcam_mgr_entry_data * -cfa_tcam_mgr_entry_get(int sess_idx, uint16_t id) +cfa_tcam_mgr_entry_get(struct cfa_tcam_mgr_data *tcam_mgr_data, uint16_t id) { - if (id > cfa_tcam_mgr_max_entries[sess_idx]) + if (id > tcam_mgr_data->cfa_tcam_mgr_max_entries) return NULL; - return &entry_data[sess_idx][id]; + return &tcam_mgr_data->entry_data[id]; } /* Insert an entry into the entry table */ static int -cfa_tcam_mgr_entry_insert(int sess_idx, uint16_t id, +cfa_tcam_mgr_entry_insert(struct cfa_tcam_mgr_data *tcam_mgr_data, + struct tf *tfp __rte_unused, uint16_t id, struct cfa_tcam_mgr_entry_data *entry) { - if (id > cfa_tcam_mgr_max_entries[sess_idx]) + if (id > tcam_mgr_data->cfa_tcam_mgr_max_entries) return -CFA_TCAM_MGR_ERR_CODE(INVAL); - memcpy(&entry_data[sess_idx][id], entry, - sizeof(entry_data[sess_idx][id])); + memcpy(&tcam_mgr_data->entry_data[id], entry, + sizeof(tcam_mgr_data->entry_data[id])); + + CFA_TCAM_MGR_TRACE(INFO, "Added entry %d to table\n", id); return 0; } /* Delete an entry from the entry table */ static int -cfa_tcam_mgr_entry_delete(int sess_idx, uint16_t id) +cfa_tcam_mgr_entry_delete(struct cfa_tcam_mgr_data *tcam_mgr_data, + struct tf *tfp __rte_unused, uint16_t id) { - if (id > cfa_tcam_mgr_max_entries[sess_idx]) + if (id > tcam_mgr_data->cfa_tcam_mgr_max_entries) return -CFA_TCAM_MGR_ERR_CODE(INVAL); - memset(&entry_data[sess_idx][id], 0, sizeof(entry_data[sess_idx][id])); + memset(&tcam_mgr_data->entry_data[id], 0, + sizeof(tcam_mgr_data->entry_data[id])); + + CFA_TCAM_MGR_TRACE(INFO, "Deleted entry %d from table.\n", id); return 0; } @@ -170,11 +168,12 @@ cfa_tcam_mgr_entry_delete(int sess_idx, uint16_t id) * TCAM supports. */ static int -cfa_tcam_mgr_row_size_get(int sess_idx, enum tf_dir dir, +cfa_tcam_mgr_row_size_get(struct cfa_tcam_mgr_data *tcam_mgr_data, + enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type) { return sizeof(struct cfa_tcam_mgr_table_rows_0) + - (cfa_tcam_mgr_tables[sess_idx][dir][type].max_slices * + (tcam_mgr_data->cfa_tcam_mgr_tables[dir][type].max_slices * sizeof(((struct cfa_tcam_mgr_table_rows_0 *)0)->entries[0])); } @@ -188,18 +187,19 @@ cfa_tcam_mgr_row_ptr_get(void *base, int index, int row_size) * Searches a table to find the direction and type of an entry. */ static int -cfa_tcam_mgr_entry_find_in_table(int sess_idx, int id, enum tf_dir dir, +cfa_tcam_mgr_entry_find_in_table(struct cfa_tcam_mgr_data *tcam_mgr_data, + int id, enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type) { struct cfa_tcam_mgr_table_data *table_data; - struct cfa_tcam_mgr_table_rows_0 *row; int max_slices, row_idx, row_size, slice; + struct cfa_tcam_mgr_table_rows_0 *row; - table_data = &cfa_tcam_mgr_tables[sess_idx][dir][type]; + table_data = &tcam_mgr_data->cfa_tcam_mgr_tables[dir][type]; if (table_data->max_entries > 0 && table_data->hcapi_type > 0) { max_slices = table_data->max_slices; - row_size = cfa_tcam_mgr_row_size_get(sess_idx, dir, type); + row_size = cfa_tcam_mgr_row_size_get(tcam_mgr_data, dir, type); for (row_idx = table_data->start_row; row_idx <= table_data->end_row; row_idx++) { @@ -225,19 +225,24 @@ cfa_tcam_mgr_entry_find_in_table(int sess_idx, int id, enum tf_dir dir, * Searches all the tables to find the direction and type of an entry. */ static int -cfa_tcam_mgr_entry_find(int sess_idx, int id, enum tf_dir *tbl_dir, +cfa_tcam_mgr_entry_find(struct cfa_tcam_mgr_data *tcam_mgr_data, int id, + enum tf_dir *tbl_dir, enum cfa_tcam_mgr_tbl_type *tbl_type) { - enum tf_dir dir; enum cfa_tcam_mgr_tbl_type type; int rc = -CFA_TCAM_MGR_ERR_CODE(NOENT); + enum tf_dir dir; - for (dir = TF_DIR_RX; dir < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx]); dir++) { + for (dir = TF_DIR_RX; dir < + ARRAY_SIZE(tcam_mgr_data->cfa_tcam_mgr_tables); + dir++) { for (type = CFA_TCAM_MGR_TBL_TYPE_START; - type < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx][dir]); + type < + ARRAY_SIZE(tcam_mgr_data->cfa_tcam_mgr_tables[dir]); type++) { - rc = cfa_tcam_mgr_entry_find_in_table(sess_idx, id, dir, type); - if (rc == 0) { + rc = cfa_tcam_mgr_entry_find_in_table(tcam_mgr_data, + id, dir, type); + if (!rc) { *tbl_dir = dir; *tbl_type = type; return rc; @@ -262,11 +267,11 @@ cfa_tcam_mgr_row_is_entry_free(struct cfa_tcam_mgr_table_rows_0 *row, return j; } } - return -1; + return -CFA_TCAM_MGR_ERR_CODE(INVAL); } static int -cfa_tcam_mgr_entry_move(int sess_idx, struct cfa_tcam_mgr_context *context, +cfa_tcam_mgr_entry_move(struct cfa_tcam_mgr_data *tcam_mgr_data, struct tf *tfp, enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type, int entry_id, struct cfa_tcam_mgr_table_data *table_data, @@ -280,15 +285,15 @@ cfa_tcam_mgr_entry_move(int sess_idx, struct cfa_tcam_mgr_context *context, struct cfa_tcam_mgr_set_parms sparms = { 0 }; struct cfa_tcam_mgr_free_parms fparms = { 0 }; struct cfa_tcam_mgr_entry_data *entry; - uint8_t key[CFA_TCAM_MGR_MAX_KEY_SIZE]; - uint8_t mask[CFA_TCAM_MGR_MAX_KEY_SIZE]; uint8_t result[CFA_TCAM_MGR_MAX_KEY_SIZE]; + uint8_t mask[CFA_TCAM_MGR_MAX_KEY_SIZE]; + uint8_t key[CFA_TCAM_MGR_MAX_KEY_SIZE]; int j, rc; - entry = cfa_tcam_mgr_entry_get(sess_idx, entry_id); - if (entry == NULL) - return -1; + entry = cfa_tcam_mgr_entry_get(tcam_mgr_data, entry_id); + if (!entry) + return -CFA_TCAM_MGR_ERR_CODE(INVAL); gparms.dir = dir; gparms.type = type; @@ -300,11 +305,11 @@ cfa_tcam_mgr_entry_move(int sess_idx, struct cfa_tcam_mgr_context *context, gparms.key_size = sizeof(key); gparms.result_size = sizeof(result); - rc = cfa_tcam_mgr_entry_get_msg(sess_idx, context, &gparms, + rc = cfa_tcam_mgr_entry_get_msg(tcam_mgr_data, tfp, &gparms, source_row_index, entry->slice * source_row->entry_size, table_data->max_slices); - if (rc != 0) + if (rc) return rc; sparms.dir = dir; @@ -332,18 +337,19 @@ cfa_tcam_mgr_entry_move(int sess_idx, struct cfa_tcam_mgr_context *context, if (dest_row_slice < 0) return -CFA_TCAM_MGR_ERR_CODE(PERM); - rc = cfa_tcam_mgr_entry_set_msg(sess_idx, context, &sparms, + rc = cfa_tcam_mgr_entry_set_msg(tcam_mgr_data, tfp, &sparms, dest_row_index, dest_row_slice * dest_row->entry_size, table_data->max_slices); - if (rc != 0) + if (rc) return rc; if (free_source_entry) { fparms.dir = dir; fparms.type = type; fparms.hcapi_type = table_data->hcapi_type; - rc = cfa_tcam_mgr_entry_free_msg(sess_idx, context, &fparms, + rc = cfa_tcam_mgr_entry_free_msg(tcam_mgr_data, + tfp, &fparms, source_row_index, entry->slice * dest_row->entry_size, @@ -352,15 +358,15 @@ cfa_tcam_mgr_entry_move(int sess_idx, struct cfa_tcam_mgr_context *context, source_row->entry_size, table_data->result_size, table_data->max_slices); - if (rc != 0) { + if (rc) { CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, dir, type, - "Failed to free entry ID %d at" - " row %d, slice %d for sess_idx %d. rc: %d.\n", + "Failed to free entry ID:%d" + " at row:%d slice:%d" + " rc:%d\n", gparms.id, source_row_index, entry->slice, - sess_idx, -rc); } } @@ -371,13 +377,17 @@ cfa_tcam_mgr_entry_move(int sess_idx, struct cfa_tcam_mgr_context *context, entry->row = dest_row_index; entry->slice = dest_row_slice; +#ifdef CFA_TCAM_MGR_TRACING + cfa_tcam_mgr_rows_dump(tfp, dir, type); +#endif + return 0; } static int -cfa_tcam_mgr_row_move(int sess_idx, struct cfa_tcam_mgr_context *context, +cfa_tcam_mgr_row_move(struct cfa_tcam_mgr_data *tcam_mgr_data, struct tf *tfp, enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type, - struct cfa_tcam_mgr_table_data *table_data, + struct cfa_tcam_mgr_table_data *tbl_data, int dest_row_index, struct cfa_tcam_mgr_table_rows_0 *dest_row, int source_row_index, @@ -392,30 +402,32 @@ cfa_tcam_mgr_row_move(int sess_idx, struct cfa_tcam_mgr_context *context, fparms.dir = dir; fparms.type = type; - fparms.hcapi_type = table_data->hcapi_type; + fparms.hcapi_type = tbl_data->hcapi_type; for (j = 0; - j < (table_data->max_slices / source_row->entry_size); + j < (tbl_data->max_slices / source_row->entry_size); j++) { if (ROW_ENTRY_INUSE(source_row, j)) { - cfa_tcam_mgr_entry_move(sess_idx, context, dir, type, + cfa_tcam_mgr_entry_move(tcam_mgr_data, tfp, + dir, type, source_row->entries[j], - table_data, + tbl_data, dest_row_index, j, dest_row, source_row_index, source_row, true); } else { /* Slice not in use, write an empty slice. */ - rc = cfa_tcam_mgr_entry_free_msg(sess_idx, context, &fparms, - dest_row_index, - j * - dest_row->entry_size, - table_data->row_width / - table_data->max_slices * - dest_row->entry_size, - table_data->result_size, - table_data->max_slices); - if (rc != 0) + rc = cfa_tcam_mgr_entry_free_msg(tcam_mgr_data, + tfp, &fparms, + dest_row_index, + j * + dest_row->entry_size, + tbl_data->row_width / + tbl_data->max_slices * + dest_row->entry_size, + tbl_data->result_size, + tbl_data->max_slices); + if (rc) return rc; } } @@ -425,7 +437,7 @@ cfa_tcam_mgr_row_move(int sess_idx, struct cfa_tcam_mgr_context *context, /* Install entry into in-memory tables, not into TCAM (yet). */ static void -cfa_tcam_mgr_row_entry_install(int sess_idx, +cfa_tcam_mgr_row_entry_install(struct tf *tfp __rte_unused, struct cfa_tcam_mgr_table_rows_0 *row, struct cfa_tcam_mgr_alloc_parms *parms, struct cfa_tcam_mgr_entry_data *entry, @@ -433,12 +445,6 @@ cfa_tcam_mgr_row_entry_install(int sess_idx, int key_slices, int row_index, int slice) { - if (global_data_initialized[sess_idx] == 0) { - CFA_TCAM_MGR_LOG(INFO, "PANIC: No TCAM data created for sess_idx %d\n", - sess_idx); - return; - } - if (slice == TF_TCAM_SLICE_INVALID) { slice = 0; row->entry_size = key_slices; @@ -449,36 +455,55 @@ cfa_tcam_mgr_row_entry_install(int sess_idx, row->entries[slice] = id; entry->row = row_index; entry->slice = slice; + + CFA_TCAM_MGR_TRACE(INFO, + "Entry %d installed row:%d slice:%d prio:%d\n", + id, row_index, slice, row->priority); +#ifdef CFA_TCAM_MGR_TRACING + cfa_tcam_mgr_rows_dump(tfp, parms->dir, parms->type); +#endif } /* Finds an empty row that can be used and reserve for entry. If necessary, * entries will be shuffled in order to make room. */ static struct cfa_tcam_mgr_table_rows_0 * -cfa_tcam_mgr_empty_row_alloc(int sess_idx, struct cfa_tcam_mgr_context *context, +cfa_tcam_mgr_empty_row_alloc(struct cfa_tcam_mgr_data *tcam_mgr_data, + struct tf *tfp, struct cfa_tcam_mgr_alloc_parms *parms, struct cfa_tcam_mgr_entry_data *entry, - uint16_t id, - int key_slices) + uint16_t id, int key_slices) { + int to_row_idx, from_row_idx, slice, start_row, end_row; struct cfa_tcam_mgr_table_rows_0 *tcam_rows; + struct cfa_tcam_mgr_table_data *table_data; struct cfa_tcam_mgr_table_rows_0 *from_row; struct cfa_tcam_mgr_table_rows_0 *to_row; struct cfa_tcam_mgr_table_rows_0 *row; - struct cfa_tcam_mgr_table_data *table_data; int i, max_slices, row_size; - int to_row_idx, from_row_idx, slice, start_row, end_row; - int empty_row = -1; int target_row = -1; + int empty_row = -1; - table_data = &cfa_tcam_mgr_tables[sess_idx][parms->dir][parms->type]; + table_data = + &tcam_mgr_data->cfa_tcam_mgr_tables[parms->dir][parms->type]; - start_row = table_data->start_row; - end_row = table_data->end_row; + start_row = table_data->start_row; + end_row = table_data->end_row; max_slices = table_data->max_slices; - tcam_rows = table_data->tcam_rows; + tcam_rows = table_data->tcam_rows; - row_size = cfa_tcam_mgr_row_size_get(sess_idx, parms->dir, parms->type); + row_size = cfa_tcam_mgr_row_size_get(tcam_mgr_data, parms->dir, + parms->type); + /* + * Note: The rows are ordered from highest priority to lowest priority. + * That is, the first row in the table will have the highest priority + * and the last row in the table will have the lowest priority. + */ + + CFA_TCAM_MGR_TRACE(INFO, "Trying to alloc space for entry with " + "priority %d and width %d slices.\n", + parms->priority, + key_slices); /* * First check for partially used entries, but only if the key needs @@ -497,10 +522,11 @@ cfa_tcam_mgr_empty_row_alloc(int sess_idx, struct cfa_tcam_mgr_context *context, max_slices, key_slices); if (slice >= 0) { - cfa_tcam_mgr_row_entry_install(sess_idx, row, parms, + cfa_tcam_mgr_row_entry_install(tfp, + row, parms, entry, id, - key_slices, - i, slice); + key_slices, i, + slice); return row; } } @@ -519,11 +545,10 @@ cfa_tcam_mgr_empty_row_alloc(int sess_idx, struct cfa_tcam_mgr_context *context, for (i = start_row; i <= end_row; i++) { row = cfa_tcam_mgr_row_ptr_get(tcam_rows, i, row_size); if (!ROW_INUSE(row)) { - cfa_tcam_mgr_row_entry_install(sess_idx, + cfa_tcam_mgr_row_entry_install(tfp, row, parms, - entry, - id, key_slices, - i, + entry, id, + key_slices, i, TF_TCAM_SLICE_INVALID); return row; } @@ -563,7 +588,7 @@ cfa_tcam_mgr_empty_row_alloc(int sess_idx, struct cfa_tcam_mgr_context *context, * just install new entry in empty_row. */ row = cfa_tcam_mgr_row_ptr_get(tcam_rows, empty_row, row_size); - cfa_tcam_mgr_row_entry_install(sess_idx, row, parms, entry, id, + cfa_tcam_mgr_row_entry_install(tfp, row, parms, entry, id, key_slices, empty_row, TF_TCAM_SLICE_INVALID); return row; @@ -587,15 +612,19 @@ cfa_tcam_mgr_empty_row_alloc(int sess_idx, struct cfa_tcam_mgr_context *context, from_row_idx = i; from_row = row; } - cfa_tcam_mgr_row_move(sess_idx, context, parms->dir, parms->type, + cfa_tcam_mgr_row_move(tcam_mgr_data, tfp, parms->dir, + parms->type, table_data, to_row_idx, to_row, from_row_idx, from_row); + CFA_TCAM_MGR_TRACE(INFO, "Moved row %d to row %d.\n", + from_row_idx, to_row_idx); + to_row = from_row; to_row_idx = from_row_idx; } to_row = cfa_tcam_mgr_row_ptr_get(tcam_rows, target_row, row_size); memset(to_row, 0, row_size); - cfa_tcam_mgr_row_entry_install(sess_idx, to_row, parms, entry, id, + cfa_tcam_mgr_row_entry_install(tfp, to_row, parms, entry, id, key_slices, target_row, TF_TCAM_SLICE_INVALID); @@ -607,24 +636,26 @@ cfa_tcam_mgr_empty_row_alloc(int sess_idx, struct cfa_tcam_mgr_context *context, * used necessary for the entries that are installed. */ static void -cfa_tcam_mgr_rows_combine(int sess_idx, struct cfa_tcam_mgr_context *context, +cfa_tcam_mgr_rows_combine(struct cfa_tcam_mgr_data *tcam_mgr_data, + struct tf *tfp, struct cfa_tcam_mgr_free_parms *parms, struct cfa_tcam_mgr_table_data *table_data, int changed_row_index) { + int to_row_idx, from_row_idx, start_row, end_row, max_slices; struct cfa_tcam_mgr_table_rows_0 *from_row = NULL; - struct cfa_tcam_mgr_table_rows_0 *to_row; struct cfa_tcam_mgr_table_rows_0 *tcam_rows; - int i, j, row_size; - int to_row_idx, from_row_idx, start_row, end_row, max_slices; + struct cfa_tcam_mgr_table_rows_0 *to_row; bool entry_moved = false; + int i, j, row_size; start_row = table_data->start_row; end_row = table_data->end_row; max_slices = table_data->max_slices; tcam_rows = table_data->tcam_rows; - row_size = cfa_tcam_mgr_row_size_get(sess_idx, parms->dir, parms->type); + row_size = cfa_tcam_mgr_row_size_get(tcam_mgr_data, parms->dir, + parms->type); from_row_idx = changed_row_index; from_row = cfa_tcam_mgr_row_ptr_get(tcam_rows, from_row_idx, row_size); @@ -658,8 +689,8 @@ cfa_tcam_mgr_rows_combine(int sess_idx, struct cfa_tcam_mgr_context *context, j++) { if (!ROW_ENTRY_INUSE(to_row, j)) { cfa_tcam_mgr_entry_move - (sess_idx, - context, + (tcam_mgr_data, + tfp, parms->dir, parms->type, from_row->entries[i], @@ -680,14 +711,14 @@ cfa_tcam_mgr_rows_combine(int sess_idx, struct cfa_tcam_mgr_context *context, #ifdef TF_FLOW_SCALE_QUERY /* CFA update usage state when moved entries */ if (entry_moved) { - if (tf_tcam_usage_update(context->tfp->session->session_id.id, + if (tf_tcam_usage_update(tfp, parms->dir, parms->type, to_row, TF_RESC_ALLOC)) { CFA_TCAM_MGR_TRACE(DEBUG, "TF tcam usage update failed\n"); } - if (tf_tcam_usage_update(context->tfp->session->session_id.id, + if (tf_tcam_usage_update(tfp, parms->dir, parms->type, from_row, @@ -707,29 +738,28 @@ cfa_tcam_mgr_rows_combine(int sess_idx, struct cfa_tcam_mgr_context *context, /* * This function will ensure that all rows, except those of the highest - * priority, at the end of the table. When this function is finished, all the + * priority, are at the end of the table. When this function is finished, all * empty rows should be between the highest priority rows at the beginning of * the table and the rest of the rows with lower priorities. - */ -/* - * Will need to free the row left newly empty as a result of moving. * + * Will need to free the row left newly empty as a result of moving. * Return row to free to caller. If new_row_to_free < 0, then no new row to * free. */ static void -cfa_tcam_mgr_rows_compact(int sess_idx, struct cfa_tcam_mgr_context *context, +cfa_tcam_mgr_rows_compact(struct cfa_tcam_mgr_data *tcam_mgr_data, + struct tf *tfp, struct cfa_tcam_mgr_free_parms *parms, struct cfa_tcam_mgr_table_data *table_data, int *new_row_to_free, int changed_row_index) { + int to_row_idx = 0, from_row_idx = 0, start_row = 0, end_row = 0; struct cfa_tcam_mgr_table_rows_0 *from_row = NULL; + struct cfa_tcam_mgr_table_rows_0 *tcam_rows; struct cfa_tcam_mgr_table_rows_0 *to_row; struct cfa_tcam_mgr_table_rows_0 *row; - struct cfa_tcam_mgr_table_rows_0 *tcam_rows; int i, row_size, priority; - int to_row_idx = 0, from_row_idx = 0, start_row = 0, end_row = 0; *new_row_to_free = -1; @@ -737,7 +767,8 @@ cfa_tcam_mgr_rows_compact(int sess_idx, struct cfa_tcam_mgr_context *context, end_row = table_data->end_row; tcam_rows = table_data->tcam_rows; - row_size = cfa_tcam_mgr_row_size_get(sess_idx, parms->dir, parms->type); + row_size = cfa_tcam_mgr_row_size_get(tcam_mgr_data, parms->dir, + parms->type); /* * The row is no longer in use, so see if rows need to be moved in order @@ -791,14 +822,21 @@ cfa_tcam_mgr_rows_compact(int sess_idx, struct cfa_tcam_mgr_context *context, * to fill the newly empty (by free or by move) * row. */ - if (from_row != NULL) { - cfa_tcam_mgr_row_move(sess_idx, context, + if (from_row) { + cfa_tcam_mgr_row_move(tcam_mgr_data, + tfp, parms->dir, parms->type, table_data, - to_row_idx, to_row, + to_row_idx, + to_row, from_row_idx, from_row); + CFA_TCAM_MGR_TRACE(INFO, + "Moved row %d " + "to row %d.\n", + from_row_idx, + to_row_idx); *new_row_to_free = from_row_idx; to_row = from_row; to_row_idx = from_row_idx; @@ -811,11 +849,12 @@ cfa_tcam_mgr_rows_compact(int sess_idx, struct cfa_tcam_mgr_context *context, } } - if (from_row != NULL) { - cfa_tcam_mgr_row_move(sess_idx, context, parms->dir, parms->type, - table_data, - to_row_idx, to_row, - from_row_idx, from_row); + if (from_row) { + cfa_tcam_mgr_row_move(tcam_mgr_data, tfp, parms->dir, + parms->type, table_data, to_row_idx, + to_row, from_row_idx, from_row); + CFA_TCAM_MGR_TRACE(INFO, "Moved row %d to row %d.\n", + from_row_idx, to_row_idx); *new_row_to_free = from_row_idx; } } @@ -824,46 +863,51 @@ cfa_tcam_mgr_rows_compact(int sess_idx, struct cfa_tcam_mgr_context *context, * This function is to set table limits for the logical TCAM tables. */ static int -cfa_tcam_mgr_table_limits_set(int sess_idx, struct cfa_tcam_mgr_init_parms *parms) +cfa_tcam_mgr_table_limits_set(struct cfa_tcam_mgr_data *tcam_mgr_data, + struct cfa_tcam_mgr_init_parms *parms) { struct cfa_tcam_mgr_table_data *table_data; unsigned int dir, type; int start, stride; - if (parms == NULL) + if (!parms) return 0; - for (dir = 0; dir < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx]); dir++) + for (dir = 0; dir < ARRAY_SIZE(tcam_mgr_data->cfa_tcam_mgr_tables); + dir++) for (type = 0; - type < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx][dir]); + type < + ARRAY_SIZE(tcam_mgr_data->cfa_tcam_mgr_tables[dir]); type++) { - table_data = &cfa_tcam_mgr_tables[sess_idx][dir][type]; + table_data = + &tcam_mgr_data->cfa_tcam_mgr_tables[dir][type]; /* * If num_rows is zero, then TCAM Manager did not * allocate any row storage for that table so cannot * manage it. */ - if (table_data->num_rows == 0) + if (!table_data->num_rows) continue; start = parms->resc[dir][type].start; stride = parms->resc[dir][type].stride; if (start % table_data->max_slices > 0) { CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, dir, type, - "Start of resources (%d) for table (%d) " - "does not begin on row boundary.\n", - start, sess_idx); + "Start of resources" + " (%d) does not begin" + " on row boundary.\n", + start); CFA_TCAM_MGR_LOG_DIR(ERR, dir, - "Start is %d, number of slices " - "is %d.\n", + "Start is %d, number of" + " slices is %d.\n", start, table_data->max_slices); return -CFA_TCAM_MGR_ERR_CODE(INVAL); } if (stride % table_data->max_slices > 0) { CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, dir, type, - "Stride of resources (%d) for table (%d)" + "Stride of resources (%d) " " does not end on row boundary.\n", - stride, sess_idx); + stride); CFA_TCAM_MGR_LOG_DIR(ERR, dir, "Stride is %d, number of " "slices is %d.\n", @@ -871,7 +915,7 @@ cfa_tcam_mgr_table_limits_set(int sess_idx, struct cfa_tcam_mgr_init_parms *parm table_data->max_slices); return -CFA_TCAM_MGR_ERR_CODE(INVAL); } - if (stride == 0) { + if (!stride) { table_data->start_row = 0; table_data->end_row = 0; table_data->max_entries = 0; @@ -890,49 +934,123 @@ cfa_tcam_mgr_table_limits_set(int sess_idx, struct cfa_tcam_mgr_init_parms *parm return 0; } +static int +cfa_tcam_mgr_bitmap_alloc(struct tf *tfp __rte_unused, + struct cfa_tcam_mgr_data *tcam_mgr_data) +{ + struct tfp_calloc_parms cparms; + uint64_t session_bmp_size; + struct bitalloc *session_bmp; + int32_t first_idx; + int max_entries; + int rc; + + if (!tcam_mgr_data->cfa_tcam_mgr_max_entries) + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + + max_entries = tcam_mgr_data->cfa_tcam_mgr_max_entries; + session_bmp_size = (sizeof(uint64_t) * + (((max_entries - 1) / sizeof(uint64_t)) + 1)); + + cparms.nitems = 1; + cparms.size = session_bmp_size; + cparms.alignment = 0; + rc = tfp_calloc(&cparms); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "Failed to allocate session bmp, rc:%s\n", + strerror(-rc)); + return -CFA_TCAM_MGR_ERR_CODE(NOMEM); + } + + session_bmp = (struct bitalloc *)cparms.mem_va; + rc = ba_init(session_bmp, max_entries, true); + + tcam_mgr_data->session_bmp = session_bmp; + tcam_mgr_data->session_bmp_size = max_entries; + + /* Allocate first index to avoid idx 0 */ + first_idx = ba_alloc(tcam_mgr_data->session_bmp); + if (first_idx == BA_FAIL) + return -CFA_TCAM_MGR_ERR_CODE(NOSPC); + + TFP_DRV_LOG(INFO, + "session bitmap size is %" PRIX64 "\n", + tcam_mgr_data->session_bmp_size); + + return 0; +} + +static void +cfa_tcam_mgr_uninit(struct tf *tfp, + enum cfa_tcam_mgr_device_type type) +{ + switch (type) { + case CFA_TCAM_MGR_DEVICE_TYPE_P4: + cfa_tcam_mgr_uninit_p4(tfp); + break; + case CFA_TCAM_MGR_DEVICE_TYPE_P5: + cfa_tcam_mgr_uninit_p58(tfp); + break; + default: + CFA_TCAM_MGR_LOG(ERR, "No such device %d\n", type); + return; + } +} + int -cfa_tcam_mgr_init(int sess_idx, enum cfa_tcam_mgr_device_type type, +cfa_tcam_mgr_init(struct tf *tfp, enum cfa_tcam_mgr_device_type type, struct cfa_tcam_mgr_init_parms *parms) { struct cfa_tcam_mgr_table_data *table_data; + struct cfa_tcam_mgr_data *tcam_mgr_data; unsigned int dir, tbl_type; + struct tf_session *tfs; int rc; + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + switch (type) { case CFA_TCAM_MGR_DEVICE_TYPE_P4: - case CFA_TCAM_MGR_DEVICE_TYPE_SR: - rc = cfa_tcam_mgr_init_p4(sess_idx, &entry_data[sess_idx]); + rc = cfa_tcam_mgr_init_p4(tfp); break; case CFA_TCAM_MGR_DEVICE_TYPE_P5: - rc = cfa_tcam_mgr_init_p58(sess_idx, &entry_data[sess_idx]); + rc = cfa_tcam_mgr_init_p58(tfp); break; default: - CFA_TCAM_MGR_LOG(ERR, "No such device %d for sess_idx %d\n", - type, sess_idx); + CFA_TCAM_MGR_LOG(ERR, "No such device %d\n", type); return -CFA_TCAM_MGR_ERR_CODE(NODEV); } - if (rc < 0) + if (rc) return rc; - rc = cfa_tcam_mgr_table_limits_set(sess_idx, parms); - if (rc < 0) + tcam_mgr_data = tfs->tcam_mgr_handle; + rc = cfa_tcam_mgr_table_limits_set(tcam_mgr_data, parms); + if (rc) return rc; /* Now calculate the max entries per table and global max entries based * on the updated table limits. */ - cfa_tcam_mgr_max_entries[sess_idx] = 0; - for (dir = 0; dir < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx]); dir++) + tcam_mgr_data->cfa_tcam_mgr_max_entries = 0; + for (dir = 0; dir < ARRAY_SIZE(tcam_mgr_data->cfa_tcam_mgr_tables); + dir++) for (tbl_type = 0; - tbl_type < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx][dir]); + tbl_type < + ARRAY_SIZE(tcam_mgr_data->cfa_tcam_mgr_tables[dir]); tbl_type++) { - table_data = &cfa_tcam_mgr_tables[sess_idx][dir][tbl_type]; + table_data = + &tcam_mgr_data->cfa_tcam_mgr_tables[dir] + [tbl_type]; /* * If num_rows is zero, then TCAM Manager did not * allocate any row storage for that table so cannot * manage it. */ - if (table_data->num_rows == 0) { + if (!table_data->num_rows) { table_data->start_row = 0; table_data->end_row = 0; table_data->max_entries = 0; @@ -940,14 +1058,13 @@ cfa_tcam_mgr_init(int sess_idx, enum cfa_tcam_mgr_device_type type, table_data->num_rows) { CFA_TCAM_MGR_LOG_DIR_TYPE(EMERG, dir, tbl_type, "End row is out of " - "range (%d >= %d) for sess_idx %d\n", + "range (%d >= %d)\n", table_data->end_row, - table_data->num_rows, - sess_idx); + table_data->num_rows); return -CFA_TCAM_MGR_ERR_CODE(FAULT); - } else if (table_data->max_entries == 0 && - table_data->start_row == 0 && - table_data->end_row == 0) { + } else if (!table_data->max_entries && + !table_data->start_row && + !table_data->end_row) { /* Nothing to do */ } else { table_data->max_entries = @@ -955,51 +1072,45 @@ cfa_tcam_mgr_init(int sess_idx, enum cfa_tcam_mgr_device_type type, (table_data->end_row - table_data->start_row + 1); } - cfa_tcam_mgr_max_entries[sess_idx] += table_data->max_entries; + tcam_mgr_data->cfa_tcam_mgr_max_entries += + table_data->max_entries; } - rc = cfa_tcam_mgr_hwops_init(type); - if (rc < 0) + rc = cfa_tcam_mgr_hwops_init(tcam_mgr_data, type); + if (rc) return rc; - rc = cfa_tcam_mgr_session_init(sess_idx, type); - if (rc < 0) + rc = cfa_tcam_mgr_bitmap_alloc(tfp, tcam_mgr_data); + if (rc) return rc; - global_data_initialized[sess_idx] = 1; - - if (parms != NULL) - parms->max_entries = cfa_tcam_mgr_max_entries[sess_idx]; + if (parms) + parms->max_entries = tcam_mgr_data->cfa_tcam_mgr_max_entries; - CFA_TCAM_MGR_LOG(DEBUG, "Global TCAM table initialized for sess_idx %d max entries %d.\n", - sess_idx, cfa_tcam_mgr_max_entries[sess_idx]); + CFA_TCAM_MGR_LOG(DEBUG, "Global TCAM tbl initialized max entries %d\n", + tcam_mgr_data->cfa_tcam_mgr_max_entries); return 0; } int -cfa_tcam_mgr_qcaps(struct cfa_tcam_mgr_context *context __rte_unused, +cfa_tcam_mgr_qcaps(struct tf *tfp __rte_unused, struct cfa_tcam_mgr_qcaps_parms *parms) { + struct cfa_tcam_mgr_data *tcam_mgr_data; + struct tf_session *tfs; unsigned int type; - int rc, sess_idx; - uint32_t session_id; + int rc; - CFA_TCAM_MGR_CHECK_PARMS2(context, parms); + CFA_TCAM_MGR_CHECK_PARMS2(tfp, parms); - rc = cfa_tcam_mgr_get_session_from_context(context, &session_id); - if (rc < 0) + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) return rc; - sess_idx = cfa_tcam_mgr_session_find(session_id); - if (sess_idx < 0) { - CFA_TCAM_MGR_LOG_0(ERR, "Session not found.\n"); - return sess_idx; - } - - if (global_data_initialized[sess_idx] == 0) { - CFA_TCAM_MGR_LOG(ERR, "PANIC: No TCAM data created for sess_idx %d\n", - sess_idx); + tcam_mgr_data = tfs->tcam_mgr_handle; + if (!tcam_mgr_data) { + CFA_TCAM_MGR_LOG_0(ERR, "No TCAM data created for session.\n"); return -CFA_TCAM_MGR_ERR_CODE(PERM); } @@ -1011,12 +1122,91 @@ cfa_tcam_mgr_qcaps(struct cfa_tcam_mgr_context *context __rte_unused, parms->rx_tcam_supported = 0; parms->tx_tcam_supported = 0; for (type = 0; type < CFA_TCAM_MGR_TBL_TYPE_MAX; type++) { - if (cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX][type].max_entries > 0 && - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX][type].hcapi_type > 0) - parms->rx_tcam_supported |= 1 << cfa_tcam_mgr_get_phys_table_type(type); - if (cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX][type].max_entries > 0 && - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX][type].hcapi_type > 0) - parms->tx_tcam_supported |= 1 << cfa_tcam_mgr_get_phys_table_type(type); + if (tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] + [type].max_entries > 0 && + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] + [type].hcapi_type > 0) + parms->rx_tcam_supported |= + 1 << cfa_tcam_mgr_get_phys_table_type(type); + if (tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] + [type].max_entries > 0 && + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] + [type].hcapi_type > 0) + parms->tx_tcam_supported |= + 1 << cfa_tcam_mgr_get_phys_table_type(type); + } + + return 0; +} + +static +int cfa_tcam_mgr_validate_tcam_cnt(struct tf *tfp __rte_unused, + struct cfa_tcam_mgr_data *tcam_mgr_data, + uint16_t tcam_cnt[] + [CFA_TCAM_MGR_TBL_TYPE_MAX]) +{ + struct cfa_tcam_mgr_table_data *table_data; + unsigned int dir, type; + uint16_t requested_cnt; + + /* Validate session request */ + for (dir = 0; dir < ARRAY_SIZE(tcam_mgr_data->cfa_tcam_mgr_tables); + dir++) { + for (type = 0; + type < ARRAY_SIZE(tcam_mgr_data->cfa_tcam_mgr_tables[dir]); + type++) { + table_data = + &tcam_mgr_data->cfa_tcam_mgr_tables[dir][type]; + requested_cnt = tcam_cnt[dir][type]; + /* Only check if table supported (max_entries > 0). */ + if (table_data->max_entries > 0 && + requested_cnt > table_data->max_entries) { + CFA_TCAM_MGR_TRACE(ERR, + "%s: %s Requested %d, available %d\n", + tf_dir_2_str(dir), + cfa_tcam_mgr_tbl_2_str(type), + requested_cnt, + table_data->max_entries); + return -CFA_TCAM_MGR_ERR_CODE(NOSPC); + } + } + } + + return 0; +} + +static int cfa_tcam_mgr_free_entries(struct tf *tfp) +{ + struct cfa_tcam_mgr_free_parms free_parms; + struct cfa_tcam_mgr_data *tcam_mgr_data; + struct tf_session *tfs; + int entry_id = 0; + int rc = 0; + + CFA_TCAM_MGR_TRACE(DEBUG, "%s: Unbinding session\n", __func__); + + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + tcam_mgr_data = tfs->tcam_mgr_handle; + memset(&free_parms, 0, sizeof(free_parms)); + + /* + * Since we are freeing all pending TCAM entries (which is typically + * done during tcam_unbind), we don't know the type of each entry. + * So we set the type to MAX as a hint to cfa_tcam_mgr_free() to + * figure out the actual type. We need to set it through each + * iteration in the loop below; otherwise, the type determined for + * the first entry would be used for subsequent entries that may or + * may not be of the same type, resulting in errors. + */ + + while ((entry_id = ba_find_next_inuse_free(tcam_mgr_data->session_bmp, + 0)) >= 0) { + free_parms.id = entry_id; + free_parms.type = CFA_TCAM_MGR_TBL_TYPE_MAX; + cfa_tcam_mgr_free(tfp, &free_parms); } return 0; @@ -1027,7 +1217,7 @@ cfa_tcam_mgr_qcaps(struct cfa_tcam_mgr_context *context __rte_unused, * and also update the sizes in the tcam count array */ static int -cfa_tcam_mgr_shared_wc_bind(uint32_t sess_idx, bool dual_ha_app, +cfa_tcam_mgr_shared_wc_bind(struct tf *tfp, bool dual_ha_app, uint16_t tcam_cnt[][CFA_TCAM_MGR_TBL_TYPE_MAX]) { uint16_t start_row, end_row, max_entries, slices; @@ -1036,13 +1226,13 @@ cfa_tcam_mgr_shared_wc_bind(uint32_t sess_idx, bool dual_ha_app, int rc; for (dir = 0; dir < TF_DIR_MAX; dir++) { - rc = cfa_tcam_mgr_tables_get(sess_idx, dir, + rc = cfa_tcam_mgr_tables_get(tfp, dir, CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS, &start_row, &end_row, &max_entries, &slices); if (rc) return rc; if (max_entries) { - rc = cfa_tcam_mgr_tables_set(sess_idx, dir, + rc = cfa_tcam_mgr_tables_set(tfp, dir, CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS, start_row, start_row + @@ -1050,7 +1240,7 @@ cfa_tcam_mgr_shared_wc_bind(uint32_t sess_idx, bool dual_ha_app, max_entries / num_pools); if (rc) return rc; - rc = cfa_tcam_mgr_tables_set(sess_idx, dir, + rc = cfa_tcam_mgr_tables_set(tfp, dir, CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS, start_row + ((max_entries / slices) / num_pools), @@ -1059,7 +1249,7 @@ cfa_tcam_mgr_shared_wc_bind(uint32_t sess_idx, bool dual_ha_app, max_entries / num_pools); if (rc) return rc; - rc = cfa_tcam_mgr_tables_set(sess_idx, dir, + rc = cfa_tcam_mgr_tables_set(tfp, dir, CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS, 0, 0, 0); if (rc) @@ -1076,24 +1266,24 @@ cfa_tcam_mgr_shared_wc_bind(uint32_t sess_idx, bool dual_ha_app, } int -cfa_tcam_mgr_bind(struct cfa_tcam_mgr_context *context, +cfa_tcam_mgr_bind(struct tf *tfp, struct cfa_tcam_mgr_cfg_parms *parms) { - struct cfa_tcam_mgr_table_data *table_data; + struct cfa_tcam_mgr_table_data *table_data; + enum cfa_tcam_mgr_device_type device_type; + struct cfa_tcam_mgr_data *tcam_mgr_data; struct tf_dev_info *dev; - unsigned int dir; - int rc, sess_idx; - uint32_t session_id; struct tf_session *tfs; - unsigned int type; int prev_max_entries; + unsigned int type; int start, stride; - enum cfa_tcam_mgr_device_type device_type; + unsigned int dir; + int rc; - CFA_TCAM_MGR_CHECK_PARMS2(context, parms); + CFA_TCAM_MGR_CHECK_PARMS2(tfp, parms); /* Retrieve the session information */ - rc = tf_session_get_session_internal(context->tfp, &tfs); + rc = tf_session_get_session_internal(tfp, &tfs); if (rc) return rc; @@ -1106,9 +1296,6 @@ cfa_tcam_mgr_bind(struct cfa_tcam_mgr_context *context, case TF_DEVICE_TYPE_P4: device_type = CFA_TCAM_MGR_DEVICE_TYPE_P4; break; - case TF_DEVICE_TYPE_SR: - device_type = CFA_TCAM_MGR_DEVICE_TYPE_SR; - break; case TF_DEVICE_TYPE_P5: device_type = CFA_TCAM_MGR_DEVICE_TYPE_P5; break; @@ -1117,27 +1304,21 @@ cfa_tcam_mgr_bind(struct cfa_tcam_mgr_context *context, return -CFA_TCAM_MGR_ERR_CODE(NODEV); } - rc = cfa_tcam_mgr_get_session_from_context(context, &session_id); - if (rc < 0) - return rc; - - sess_idx = cfa_tcam_mgr_session_add(session_id); - if (sess_idx < 0) - return sess_idx; - - if (global_data_initialized[sess_idx] == 0) { - rc = cfa_tcam_mgr_init(sess_idx, device_type, NULL); - if (rc < 0) + tcam_mgr_data = tfs->tcam_mgr_handle; + if (!tcam_mgr_data) { + rc = cfa_tcam_mgr_init(tfp, device_type, NULL); + if (rc) return rc; + tcam_mgr_data = tfs->tcam_mgr_handle; } - if (parms->num_elements != ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx][dir])) { + if (parms->num_elements != + ARRAY_SIZE(tcam_mgr_data->cfa_tcam_mgr_tables[dir])) { CFA_TCAM_MGR_LOG(ERR, "Session element count (%d) differs " - "from table count (%zu) for sess_idx %d.\n", + "from table count (%zu)\n", parms->num_elements, - ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx][dir]), - sess_idx); + ARRAY_SIZE(tcam_mgr_data->cfa_tcam_mgr_tables[dir])); return -CFA_TCAM_MGR_ERR_CODE(INVAL); } @@ -1145,48 +1326,51 @@ cfa_tcam_mgr_bind(struct cfa_tcam_mgr_context *context, * Only managing one session. resv_res contains the resources allocated * to this session by the resource manager. Update the limits on TCAMs. */ - for (dir = 0; dir < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx]); dir++) { + for (dir = 0; dir < ARRAY_SIZE(tcam_mgr_data->cfa_tcam_mgr_tables); + dir++) { for (type = 0; - type < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx][dir]); + type < + ARRAY_SIZE(tcam_mgr_data->cfa_tcam_mgr_tables[dir]); type++) { - table_data = &cfa_tcam_mgr_tables[sess_idx][dir][type]; + table_data = + &tcam_mgr_data->cfa_tcam_mgr_tables[dir][type]; prev_max_entries = table_data->max_entries; /* * In AFM logical tables, max_entries is initialized to * zero. These logical tables are not used when TCAM * Manager is in the core so skip. */ - if (prev_max_entries == 0) + if (!prev_max_entries) continue; start = parms->resv_res[dir][type].start; stride = parms->resv_res[dir][type].stride; if (start % table_data->max_slices > 0) { CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, dir, type, - "Start of resources (%d) for table(%d) " - "does not begin on row boundary.\n", - start, sess_idx); + "%s: %s Resource:%d not row bounded\n", + tf_dir_2_str(dir), + cfa_tcam_mgr_tbl_2_str(type), + start); CFA_TCAM_MGR_LOG_DIR(ERR, dir, - "Start is %d, number of slices " - "is %d.\n", - start, + "%s: Start:%d, num slices:%d\n", + tf_dir_2_str(dir), start, table_data->max_slices); - (void)cfa_tcam_mgr_session_free(session_id, context); + cfa_tcam_mgr_free_entries(tfp); return -CFA_TCAM_MGR_ERR_CODE(INVAL); } if (stride % table_data->max_slices > 0) { CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, dir, type, - "Stride of resources (%d) for table(%d) " - "does not end on row boundary.\n", - stride, sess_idx); + "%s: %s Resource:%d not row bound\n", + tf_dir_2_str(dir), + cfa_tcam_mgr_tbl_2_str(type), + stride); CFA_TCAM_MGR_LOG_DIR(ERR, dir, - "Stride is %d, number of " - "slices is %d.\n", - stride, + "%s: Stride:%d num slices:%d\n", + tf_dir_2_str(dir), stride, table_data->max_slices); - (void)cfa_tcam_mgr_session_free(session_id, context); + cfa_tcam_mgr_free_entries(tfp); return -CFA_TCAM_MGR_ERR_CODE(INVAL); } - if (stride == 0) { + if (!stride) { table_data->start_row = 0; table_data->end_row = 0; table_data->max_entries = 0; @@ -1200,25 +1384,34 @@ cfa_tcam_mgr_bind(struct cfa_tcam_mgr_context *context, (table_data->end_row - table_data->start_row + 1); } - cfa_tcam_mgr_max_entries[sess_idx] += (table_data->max_entries - - prev_max_entries); + tcam_mgr_data->cfa_tcam_mgr_max_entries += + (table_data->max_entries - prev_max_entries); } } + CFA_TCAM_MGR_LOG(DEBUG, "TCAM table bind for max entries %d.\n", + tcam_mgr_data->cfa_tcam_mgr_max_entries); + if (tf_session_is_shared_hotup_session(tfs)) { - rc = cfa_tcam_mgr_shared_wc_bind(sess_idx, false, parms->tcam_cnt); + rc = cfa_tcam_mgr_shared_wc_bind(tfp, false, + parms->tcam_cnt); if (rc) { - (void)cfa_tcam_mgr_session_free(session_id, context); + cfa_tcam_mgr_free_entries(tfp); return rc; } } - rc = cfa_tcam_mgr_session_cfg(session_id, parms->tcam_cnt); - if (rc < 0) { - (void)cfa_tcam_mgr_session_free(session_id, context); + rc = cfa_tcam_mgr_validate_tcam_cnt(tfp, tcam_mgr_data, + parms->tcam_cnt); + if (rc) { + cfa_tcam_mgr_free_entries(tfp); return rc; } +#ifdef CFA_TCAM_MGR_TRACING + cfa_tcam_mgr_tables_dump(tfp, TF_DIR_MAX, CFA_TCAM_MGR_TBL_TYPE_MAX); +#endif + #ifdef TF_FLOW_SCALE_QUERY /* Initialize the WC TCAM usage state */ tf_tcam_usage_init(tfp); @@ -1228,48 +1421,106 @@ cfa_tcam_mgr_bind(struct cfa_tcam_mgr_context *context, } int -cfa_tcam_mgr_unbind(struct cfa_tcam_mgr_context *context) +cfa_tcam_mgr_unbind(struct tf *tfp) { - int rc, sess_idx; - uint32_t session_id; + enum cfa_tcam_mgr_device_type device_type; + struct cfa_tcam_mgr_data *tcam_mgr_data; + struct tf_dev_info *dev; + struct tf_session *tfs; + int rc; - CFA_TCAM_MGR_CHECK_PARMS1(context); + CFA_TCAM_MGR_CHECK_PARMS1(tfp); - rc = cfa_tcam_mgr_get_session_from_context(context, &session_id); - if (rc < 0) + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) return rc; - sess_idx = cfa_tcam_mgr_session_find(session_id); - if (sess_idx < 0) { - CFA_TCAM_MGR_LOG_0(ERR, "Session not found.\n"); - return sess_idx; + switch (dev->type) { + case TF_DEVICE_TYPE_P4: + device_type = CFA_TCAM_MGR_DEVICE_TYPE_P4; + break; + case TF_DEVICE_TYPE_P5: + device_type = CFA_TCAM_MGR_DEVICE_TYPE_P5; + break; + default: + CFA_TCAM_MGR_TRACE(DEBUG, + "%s: TF tcam get dev type failed\n", + __func__); + return -CFA_TCAM_MGR_ERR_CODE(NODEV); } - if (global_data_initialized[sess_idx] == 0) { - CFA_TCAM_MGR_LOG(INFO, "PANIC: No TCAM data created for sess_idx %d\n", - sess_idx); + tcam_mgr_data = tfs->tcam_mgr_handle; + if (!tcam_mgr_data) { + CFA_TCAM_MGR_TRACE(ERROR, + "%s: No TCAM data created for session\n", + __func__); return -CFA_TCAM_MGR_ERR_CODE(PERM); } - (void)cfa_tcam_mgr_session_free(session_id, context); + cfa_tcam_mgr_free_entries(tfp); + cfa_tcam_mgr_uninit(tfp, device_type); + + return 0; +} + +static int cfa_tcam_mgr_alloc_entry(struct tf *tfp __rte_unused, + struct cfa_tcam_mgr_data *tcam_mgr_data, + enum tf_dir dir __rte_unused) +{ + int32_t free_idx; + + /* Scan bitmap to get the free pool */ + free_idx = ba_alloc(tcam_mgr_data->session_bmp); + if (free_idx == BA_FAIL) { + CFA_TCAM_MGR_TRACE(ERROR, + "%s: Table full (session)\n", __func__); + return -CFA_TCAM_MGR_ERR_CODE(NOSPC); + } + + return free_idx; +} + +static int cfa_tcam_mgr_free_entry(struct tf *tfp __rte_unused, + struct cfa_tcam_mgr_data *tcam_mgr_data, + unsigned int entry_id, + enum tf_dir dir __rte_unused, + enum cfa_tcam_mgr_tbl_type type __rte_unused) +{ + int rc = 0; + + if (entry_id >= tcam_mgr_data->session_bmp_size) + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + + rc = ba_free(tcam_mgr_data->session_bmp, entry_id); + if (rc) + return rc; + + CFA_TCAM_MGR_TRACE(INFO, + "%s: Remove session from entry %d\n", + __func__, entry_id); - global_data_initialized[sess_idx] = 0; return 0; } int -cfa_tcam_mgr_alloc(struct cfa_tcam_mgr_context *context, +cfa_tcam_mgr_alloc(struct tf *tfp, struct cfa_tcam_mgr_alloc_parms *parms) { - struct cfa_tcam_mgr_entry_data entry; + struct cfa_tcam_mgr_table_data *table_data; + struct cfa_tcam_mgr_data *tcam_mgr_data; struct cfa_tcam_mgr_table_rows_0 *row; - struct cfa_tcam_mgr_table_data *table_data; + struct cfa_tcam_mgr_entry_data entry; + struct tf_session *tfs; + int key_slices, rc; int dir, tbl_type; - int key_slices, rc, sess_idx; int new_entry_id; - uint32_t session_id; - CFA_TCAM_MGR_CHECK_PARMS2(context, parms); + CFA_TCAM_MGR_CHECK_PARMS2(tfp, parms); dir = parms->dir; tbl_type = parms->type; @@ -1289,40 +1540,31 @@ cfa_tcam_mgr_alloc(struct cfa_tcam_mgr_context *context, #if TF_TCAM_PRIORITY_MAX < UINT16_MAX if (parms->priority > TF_TCAM_PRIORITY_MAX) { CFA_TCAM_MGR_LOG_DIR(ERR, dir, - "Priority (%u) out of range (%u -%u).\n", - parms->priority, + "%s: Priority:%u out of range (%u-%u).\n", + tf_dir_2_str(dir), parms->priority, TF_TCAM_PRIORITY_MIN, TF_TCAM_PRIORITY_MAX); } #endif - /* Check for session limits */ - rc = cfa_tcam_mgr_get_session_from_context(context, &session_id); - if (rc < 0) + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) return rc; - sess_idx = cfa_tcam_mgr_session_find(session_id); - if (sess_idx < 0) { - CFA_TCAM_MGR_LOG(ERR, "Session 0x%08x not found.\n", - session_id); - return -CFA_TCAM_MGR_ERR_CODE(NODEV); - } - - if (global_data_initialized[sess_idx] == 0) { - CFA_TCAM_MGR_LOG(ERR, "PANIC: No TCAM data created for sess_idx %d\n", - sess_idx); + tcam_mgr_data = tfs->tcam_mgr_handle; + if (!tcam_mgr_data) { + CFA_TCAM_MGR_LOG(ERR, "No TCAM data created for session\n"); return -CFA_TCAM_MGR_ERR_CODE(PERM); } - table_data = &cfa_tcam_mgr_tables[sess_idx][dir][tbl_type]; + table_data = &tcam_mgr_data->cfa_tcam_mgr_tables[dir][tbl_type]; - if (parms->key_size == 0 || + if (!parms->key_size || parms->key_size > table_data->row_width) { CFA_TCAM_MGR_LOG_DIR(ERR, dir, - "Invalid key size:%d (range 1-%d) sess_idx %d.\n", + "Invalid key size:%d (range 1-%d).\n", parms->key_size, - table_data->row_width, - sess_idx); + table_data->row_width); return -CFA_TCAM_MGR_ERR_CODE(INVAL); } @@ -1330,48 +1572,46 @@ cfa_tcam_mgr_alloc(struct cfa_tcam_mgr_context *context, if (table_data->used_entries >= table_data->max_entries) { CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, dir, tbl_type, - "Table full sess_idx %d.\n", - sess_idx); + "Table full.\n"); return -CFA_TCAM_MGR_ERR_CODE(NOSPC); } /* There is room, now increment counts and allocate an entry. */ - new_entry_id = cfa_tcam_mgr_session_entry_alloc(session_id, - parms->dir, - parms->type); + new_entry_id = cfa_tcam_mgr_alloc_entry(tfp, tcam_mgr_data, parms->dir); if (new_entry_id < 0) return new_entry_id; memset(&entry, 0, sizeof(entry)); entry.ref_cnt++; + CFA_TCAM_MGR_TRACE(INFO, "Allocated entry ID %d.\n", new_entry_id); + key_slices = cfa_tcam_mgr_get_num_slices(parms->key_size, (table_data->row_width / table_data->max_slices)); - row = cfa_tcam_mgr_empty_row_alloc(sess_idx, context, parms, &entry, + row = cfa_tcam_mgr_empty_row_alloc(tcam_mgr_data, tfp, parms, &entry, new_entry_id, key_slices); - if (row == NULL) { + if (!row) { CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, parms->dir, parms->type, - "Table full (HW) sess_idx %d.\n", - sess_idx); - (void)cfa_tcam_mgr_session_entry_free(session_id, new_entry_id, - parms->dir, parms->type); + "Table full (HW).\n"); + cfa_tcam_mgr_free_entry(tfp, tcam_mgr_data, new_entry_id, + parms->dir, parms->type); return -CFA_TCAM_MGR_ERR_CODE(NOSPC); } - memcpy(&entry_data[sess_idx][new_entry_id], + memcpy(&tcam_mgr_data->entry_data[new_entry_id], &entry, - sizeof(entry_data[sess_idx][new_entry_id])); + sizeof(tcam_mgr_data->entry_data[new_entry_id])); table_data->used_entries += 1; - cfa_tcam_mgr_entry_insert(sess_idx, new_entry_id, &entry); + cfa_tcam_mgr_entry_insert(tcam_mgr_data, tfp, new_entry_id, &entry); parms->id = new_entry_id; #ifdef TF_FLOW_SCALE_QUERY /* CFA update usage state */ - if (tf_tcam_usage_update(session_id, + if (tf_tcam_usage_update(tfp, parms->dir, parms->type, row, @@ -1384,46 +1624,38 @@ cfa_tcam_mgr_alloc(struct cfa_tcam_mgr_context *context, } int -cfa_tcam_mgr_free(struct cfa_tcam_mgr_context *context, +cfa_tcam_mgr_free(struct tf *tfp, struct cfa_tcam_mgr_free_parms *parms) { + struct cfa_tcam_mgr_table_data *table_data; + struct cfa_tcam_mgr_data *tcam_mgr_data; struct cfa_tcam_mgr_entry_data *entry; struct cfa_tcam_mgr_table_rows_0 *row; - struct cfa_tcam_mgr_table_data *table_data; - int row_size, rc, sess_idx, new_row_to_free; - uint32_t session_id; + int row_size, rc, new_row_to_free; + struct tf_session *tfs; uint16_t id; - CFA_TCAM_MGR_CHECK_PARMS2(context, parms); + CFA_TCAM_MGR_CHECK_PARMS2(tfp, parms); - rc = cfa_tcam_mgr_get_session_from_context(context, &session_id); - if (rc < 0) + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) return rc; - sess_idx = cfa_tcam_mgr_session_find(session_id); - if (sess_idx < 0) { - CFA_TCAM_MGR_LOG(ERR, "Session 0x%08x not found.\n", - session_id); - return sess_idx; - } - - if (global_data_initialized[sess_idx] == 0) { - CFA_TCAM_MGR_LOG(INFO, "PANIC: No TCAM data created for sess_idx %d\n", - sess_idx); + tcam_mgr_data = tfs->tcam_mgr_handle; + if (!tcam_mgr_data) { + CFA_TCAM_MGR_LOG(ERR, "No TCAM data created for session\n"); return -CFA_TCAM_MGR_ERR_CODE(PERM); } id = parms->id; - entry = cfa_tcam_mgr_entry_get(sess_idx, id); - if (entry == NULL) { - CFA_TCAM_MGR_LOG(INFO, "Entry %d not found for sess_idx %d.\n", - id, sess_idx); + entry = cfa_tcam_mgr_entry_get(tcam_mgr_data, id); + if (!entry) { + CFA_TCAM_MGR_LOG(INFO, "Entry %d not found\n", id); return -CFA_TCAM_MGR_ERR_CODE(INVAL); } - if (entry->ref_cnt == 0) { - CFA_TCAM_MGR_LOG(ERR, "Entry %d not in use for sess_idx %d.\n", - id, sess_idx); + if (!entry->ref_cnt) { + CFA_TCAM_MGR_LOG(ERR, "Entry %d not in use.\n", id); return -CFA_TCAM_MGR_ERR_CODE(INVAL); } @@ -1439,30 +1671,38 @@ cfa_tcam_mgr_free(struct cfa_tcam_mgr_context *context, */ if (parms->type == CFA_TCAM_MGR_TBL_TYPE_MAX) { /* Need to search for the entry in the tables */ - rc = cfa_tcam_mgr_entry_find(sess_idx, id, &parms->dir, &parms->type); - if (rc < 0) { - CFA_TCAM_MGR_LOG(ERR, "Entry %d not in tables for sess_idx %d.\n", - id, sess_idx); + rc = cfa_tcam_mgr_entry_find(tcam_mgr_data, id, &parms->dir, + &parms->type); + if (rc) { + CFA_TCAM_MGR_LOG(ERR, + "Entry %d not in tables\n", id); return rc; } + CFA_TCAM_MGR_TRACE(INFO, "%s: id: %d dir: 0x%x type: 0x%x\n", + __func__, id, parms->dir, parms->type); } - table_data = &cfa_tcam_mgr_tables[sess_idx][parms->dir][parms->type]; + table_data = + &tcam_mgr_data->cfa_tcam_mgr_tables[parms->dir][parms->type]; parms->hcapi_type = table_data->hcapi_type; - row_size = cfa_tcam_mgr_row_size_get(sess_idx, parms->dir, parms->type); + row_size = cfa_tcam_mgr_row_size_get(tcam_mgr_data, parms->dir, + parms->type); row = cfa_tcam_mgr_row_ptr_get(table_data->tcam_rows, entry->row, row_size); entry->ref_cnt--; - (void)cfa_tcam_mgr_session_entry_free(session_id, id, - parms->dir, parms->type); + cfa_tcam_mgr_free_entry(tfp, tcam_mgr_data, id, parms->dir, + parms->type); - if (entry->ref_cnt == 0) { - cfa_tcam_mgr_entry_free_msg(sess_idx, context, parms, - entry->row, + if (!entry->ref_cnt) { + CFA_TCAM_MGR_TRACE(INFO, + "Freeing entry %d, row %d, slice %d.\n", + id, entry->row, entry->slice); + cfa_tcam_mgr_entry_free_msg(tcam_mgr_data, tfp, + parms, entry->row, entry->slice * row->entry_size, table_data->row_width / table_data->max_slices * @@ -1473,7 +1713,7 @@ cfa_tcam_mgr_free(struct cfa_tcam_mgr_context *context, #ifdef TF_FLOW_SCALE_QUERY /* CFA update usage state */ - if (tf_tcam_usage_update(session_id, + if (tf_tcam_usage_update(tfp, parms->dir, parms->type, row, @@ -1483,71 +1723,72 @@ cfa_tcam_mgr_free(struct cfa_tcam_mgr_context *context, #endif /* TF_FLOW_SCALE_QUERY */ new_row_to_free = entry->row; - cfa_tcam_mgr_rows_combine(sess_idx, context, parms, table_data, - new_row_to_free); + cfa_tcam_mgr_rows_combine(tcam_mgr_data, tfp, parms, + table_data, new_row_to_free); if (!ROW_INUSE(row)) { - cfa_tcam_mgr_rows_compact(sess_idx, context, + cfa_tcam_mgr_rows_compact(tcam_mgr_data, tfp, parms, table_data, &new_row_to_free, new_row_to_free); if (new_row_to_free >= 0) - cfa_tcam_mgr_entry_free_msg(sess_idx, context, parms, + cfa_tcam_mgr_entry_free_msg(tcam_mgr_data, + tfp, parms, new_row_to_free, 0, table_data->row_width, table_data->result_size, table_data->max_slices); } - cfa_tcam_mgr_entry_delete(sess_idx, id); + cfa_tcam_mgr_entry_delete(tcam_mgr_data, tfp, id); table_data->used_entries -= 1; + CFA_TCAM_MGR_TRACE(INFO, "Freed entry %d.\n", id); + } else { + CFA_TCAM_MGR_TRACE(INFO, "Entry %d ref cnt = %d.\n", + id, + entry->ref_cnt); } return 0; } int -cfa_tcam_mgr_set(struct cfa_tcam_mgr_context *context, +cfa_tcam_mgr_set(struct tf *tfp, struct cfa_tcam_mgr_set_parms *parms) { + struct cfa_tcam_mgr_table_data *table_data; + struct cfa_tcam_mgr_data *tcam_mgr_data; struct cfa_tcam_mgr_entry_data *entry; struct cfa_tcam_mgr_table_rows_0 *row; - struct cfa_tcam_mgr_table_data *table_data; - int rc; - int row_size, sess_idx; int entry_size_in_bytes; - uint32_t session_id; + struct tf_session *tfs; + int row_size; + int rc; - CFA_TCAM_MGR_CHECK_PARMS2(context, parms); + CFA_TCAM_MGR_CHECK_PARMS2(tfp, parms); - rc = cfa_tcam_mgr_get_session_from_context(context, &session_id); - if (rc < 0) + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) return rc; - sess_idx = cfa_tcam_mgr_session_find(session_id); - if (sess_idx < 0) { - CFA_TCAM_MGR_LOG(ERR, "Session 0x%08x not found.\n", - session_id); - return sess_idx; - } - - if (global_data_initialized[sess_idx] == 0) { - CFA_TCAM_MGR_LOG(ERR, "PANIC: No TCAM data created for sess_idx %d\n", - sess_idx); + tcam_mgr_data = tfs->tcam_mgr_handle; + if (!tcam_mgr_data) { + CFA_TCAM_MGR_LOG(ERR, "No TCAM data created for session\n"); return -CFA_TCAM_MGR_ERR_CODE(PERM); } - entry = cfa_tcam_mgr_entry_get(sess_idx, parms->id); - if (entry == NULL) { - CFA_TCAM_MGR_LOG(ERR, "Entry %d not found for sess_idx %d.\n", - parms->id, sess_idx); + entry = cfa_tcam_mgr_entry_get(tcam_mgr_data, parms->id); + if (!entry) { + CFA_TCAM_MGR_LOG(ERR, "Entry %d not found.\n", parms->id); return -CFA_TCAM_MGR_ERR_CODE(INVAL); } - table_data = &cfa_tcam_mgr_tables[sess_idx][parms->dir][parms->type]; + table_data = + &tcam_mgr_data->cfa_tcam_mgr_tables[parms->dir][parms->type]; parms->hcapi_type = table_data->hcapi_type; - row_size = cfa_tcam_mgr_row_size_get(sess_idx, parms->dir, parms->type); + row_size = cfa_tcam_mgr_row_size_get(tcam_mgr_data, parms->dir, + parms->type); row = cfa_tcam_mgr_row_ptr_get(table_data->tcam_rows, entry->row, row_size); @@ -1558,71 +1799,68 @@ cfa_tcam_mgr_set(struct cfa_tcam_mgr_context *context, CFA_TCAM_MGR_LOG(ERR, "Key size(%d) is different from entry " "size(%d).\n", - parms->key_size, - entry_size_in_bytes); + parms->key_size, entry_size_in_bytes); return -CFA_TCAM_MGR_ERR_CODE(INVAL); } - rc = cfa_tcam_mgr_entry_set_msg(sess_idx, context, parms, + rc = cfa_tcam_mgr_entry_set_msg(tcam_mgr_data, tfp, parms, entry->row, entry->slice * row->entry_size, table_data->max_slices); - if (rc < 0) { + if (rc) { CFA_TCAM_MGR_LOG_0(ERR, "Failed to set TCAM data.\n"); return rc; } + CFA_TCAM_MGR_TRACE(INFO, "Set data for entry %d\n", parms->id); + return 0; } int -cfa_tcam_mgr_get(struct cfa_tcam_mgr_context *context __rte_unused, +cfa_tcam_mgr_get(struct tf *tfp __rte_unused, struct cfa_tcam_mgr_get_parms *parms) { + struct cfa_tcam_mgr_table_data *table_data; + struct cfa_tcam_mgr_data *tcam_mgr_data; struct cfa_tcam_mgr_entry_data *entry; struct cfa_tcam_mgr_table_rows_0 *row; - struct cfa_tcam_mgr_table_data *table_data; + struct tf_session *tfs; + int row_size; int rc; - int row_size, sess_idx; - uint32_t session_id; - CFA_TCAM_MGR_CHECK_PARMS2(context, parms); + CFA_TCAM_MGR_CHECK_PARMS2(tfp, parms); - rc = cfa_tcam_mgr_get_session_from_context(context, &session_id); - if (rc < 0) + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) return rc; - sess_idx = cfa_tcam_mgr_session_find(session_id); - if (sess_idx < 0) { - CFA_TCAM_MGR_LOG(ERR, "Session 0x%08x not found.\n", - session_id); - return sess_idx; - } - - if (global_data_initialized[sess_idx] == 0) { - CFA_TCAM_MGR_LOG(ERR, "PANIC: No TCAM data created for sess_idx %d\n", - sess_idx); + tcam_mgr_data = tfs->tcam_mgr_handle; + if (!tcam_mgr_data) { + CFA_TCAM_MGR_LOG(ERR, "No TCAM data created for session\n"); return -CFA_TCAM_MGR_ERR_CODE(PERM); } - entry = cfa_tcam_mgr_entry_get(sess_idx, parms->id); - if (entry == NULL) { + entry = cfa_tcam_mgr_entry_get(tcam_mgr_data, parms->id); + if (!entry) { CFA_TCAM_MGR_LOG(ERR, "Entry %d not found.\n", parms->id); return -CFA_TCAM_MGR_ERR_CODE(INVAL); } - table_data = &cfa_tcam_mgr_tables[sess_idx][parms->dir][parms->type]; + table_data = + &tcam_mgr_data->cfa_tcam_mgr_tables[parms->dir][parms->type]; parms->hcapi_type = table_data->hcapi_type; - row_size = cfa_tcam_mgr_row_size_get(sess_idx, parms->dir, parms->type); + row_size = cfa_tcam_mgr_row_size_get(tcam_mgr_data, parms->dir, + parms->type); row = cfa_tcam_mgr_row_ptr_get(table_data->tcam_rows, entry->row, row_size); - rc = cfa_tcam_mgr_entry_get_msg(sess_idx, context, parms, + rc = cfa_tcam_mgr_entry_get_msg(tcam_mgr_data, tfp, parms, entry->row, entry->slice * row->entry_size, table_data->max_slices); - if (rc < 0) { + if (rc) { CFA_TCAM_MGR_LOG_0(ERR, "Failed to read from TCAM.\n"); return rc; } @@ -1630,49 +1868,44 @@ cfa_tcam_mgr_get(struct cfa_tcam_mgr_context *context __rte_unused, return 0; } -int cfa_tcam_mgr_shared_clear(struct cfa_tcam_mgr_context *context, - struct cfa_tcam_mgr_shared_clear_parms *parms) +int cfa_tcam_mgr_shared_clear(struct tf *tfp, + struct cfa_tcam_mgr_shared_clear_parms *parms) { - int rc; - uint16_t row, slice = 0; - int sess_idx; - uint32_t session_id; - struct cfa_tcam_mgr_free_parms fparms; - struct cfa_tcam_mgr_table_data *table_data; uint16_t start_row, end_row, max_entries, max_slices; + struct cfa_tcam_mgr_table_data *table_data; + struct cfa_tcam_mgr_data *tcam_mgr_data; + struct cfa_tcam_mgr_free_parms fparms; + uint16_t row, slice = 0; + struct tf_session *tfs; + int rc; - CFA_TCAM_MGR_CHECK_PARMS2(context, parms); + CFA_TCAM_MGR_CHECK_PARMS2(tfp, parms); - rc = cfa_tcam_mgr_get_session_from_context(context, &session_id); - if (rc < 0) + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) return rc; - sess_idx = cfa_tcam_mgr_session_find(session_id); - if (sess_idx < 0) { - CFA_TCAM_MGR_LOG(ERR, "Session 0x%08x not found.\n", - session_id); - return sess_idx; - } - - if (global_data_initialized[sess_idx] == 0) { - CFA_TCAM_MGR_LOG(ERR, "PANIC: No TCAM data created for sess_idx %d\n", - sess_idx); + tcam_mgr_data = tfs->tcam_mgr_handle; + if (!tcam_mgr_data) { + CFA_TCAM_MGR_LOG(ERR, "No TCAM data created for session\n"); return -CFA_TCAM_MGR_ERR_CODE(PERM); } - table_data = &cfa_tcam_mgr_tables[sess_idx][parms->dir][parms->type]; + table_data = + &tcam_mgr_data->cfa_tcam_mgr_tables[parms->dir][parms->type]; fparms.dir = parms->dir; fparms.type = parms->type; fparms.hcapi_type = table_data->hcapi_type; fparms.id = 0; - rc = cfa_tcam_mgr_tables_get(sess_idx, parms->dir, parms->type, - &start_row, &end_row, &max_entries, &max_slices); + rc = cfa_tcam_mgr_tables_get(tfp, parms->dir, parms->type, + &start_row, &end_row, &max_entries, + &max_slices); if (rc) return rc; for (row = start_row; row <= end_row; row++) { - cfa_tcam_mgr_entry_free_msg(sess_idx, context, &fparms, + cfa_tcam_mgr_entry_free_msg(tcam_mgr_data, tfp, &fparms, row, slice, table_data->row_width, @@ -1683,16 +1916,11 @@ int cfa_tcam_mgr_shared_clear(struct cfa_tcam_mgr_context *context, } static void -cfa_tcam_mgr_mv_used_entries_cnt(int sess_idx, enum tf_dir dir, - struct cfa_tcam_mgr_table_data *dst_table_data, +cfa_tcam_mgr_mv_used_entries_cnt(struct cfa_tcam_mgr_table_data *dst_table_data, struct cfa_tcam_mgr_table_data *src_table_data) { dst_table_data->used_entries++; src_table_data->used_entries--; - - cfa_tcam_mgr_mv_session_used_entries_cnt(sess_idx, dir, - CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS, - CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS); } /* @@ -1700,33 +1928,34 @@ cfa_tcam_mgr_mv_used_entries_cnt(int sess_idx, enum tf_dir dir, * This happens when secondary is becoming primary */ static int -cfa_tcam_mgr_shared_entry_move(int sess_idx, struct cfa_tcam_mgr_context *context, - enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type, - int entry_id, - struct cfa_tcam_mgr_table_data *dst_table_data, - struct cfa_tcam_mgr_table_data *table_data, - int dst_row_index, int dst_row_slice, - struct cfa_tcam_mgr_table_rows_0 *dst_row, - int src_row_index, - struct cfa_tcam_mgr_table_rows_0 *src_row) +cfa_tcam_mgr_shared_entry_move(struct cfa_tcam_mgr_data *tcam_mgr_data, + struct tf *tfp, + enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type, + int entry_id, + struct cfa_tcam_mgr_table_data *dst_table_data, + struct cfa_tcam_mgr_table_data *table_data, + int dst_row_index, int dst_row_slice, + struct cfa_tcam_mgr_table_rows_0 *dst_row, + int src_row_index, + struct cfa_tcam_mgr_table_rows_0 *src_row) { + struct cfa_tcam_mgr_free_parms fparms = { 0 }; struct cfa_tcam_mgr_get_parms gparms = { 0 }; struct cfa_tcam_mgr_set_parms sparms = { 0 }; - struct cfa_tcam_mgr_free_parms fparms = { 0 }; - struct cfa_tcam_mgr_entry_data *entry; - uint8_t key[CFA_TCAM_MGR_MAX_KEY_SIZE]; - uint8_t mask[CFA_TCAM_MGR_MAX_KEY_SIZE]; uint8_t result[CFA_TCAM_MGR_MAX_KEY_SIZE]; + uint8_t mask[CFA_TCAM_MGR_MAX_KEY_SIZE]; + uint8_t key[CFA_TCAM_MGR_MAX_KEY_SIZE]; + struct cfa_tcam_mgr_entry_data *entry; + int rc; + /* * Copy entry size before moving else if * slice number is non zero and entry size is zero it will cause issues */ dst_row->entry_size = src_row->entry_size; - int rc; - - entry = cfa_tcam_mgr_entry_get(sess_idx, entry_id); - if (entry == NULL) + entry = cfa_tcam_mgr_entry_get(tcam_mgr_data, entry_id); + if (!entry) return -1; gparms.dir = dir; @@ -1739,11 +1968,11 @@ cfa_tcam_mgr_shared_entry_move(int sess_idx, struct cfa_tcam_mgr_context *contex gparms.key_size = sizeof(key); gparms.result_size = sizeof(result); - rc = cfa_tcam_mgr_entry_get_msg(sess_idx, context, &gparms, + rc = cfa_tcam_mgr_entry_get_msg(tcam_mgr_data, tfp, &gparms, src_row_index, entry->slice * src_row->entry_size, table_data->max_slices); - if (rc != 0) + if (rc) return rc; sparms.dir = dir; @@ -1756,17 +1985,17 @@ cfa_tcam_mgr_shared_entry_move(int sess_idx, struct cfa_tcam_mgr_context *contex sparms.key_size = gparms.key_size; sparms.result_size = gparms.result_size; - rc = cfa_tcam_mgr_entry_set_msg(sess_idx, context, &sparms, + rc = cfa_tcam_mgr_entry_set_msg(tcam_mgr_data, tfp, &sparms, dst_row_index, dst_row_slice * dst_row->entry_size, table_data->max_slices); - if (rc != 0) + if (rc) return rc; fparms.dir = dir; fparms.type = type; fparms.hcapi_type = table_data->hcapi_type; - rc = cfa_tcam_mgr_entry_free_msg(sess_idx, context, &fparms, + rc = cfa_tcam_mgr_entry_free_msg(tcam_mgr_data, tfp, &fparms, src_row_index, entry->slice * dst_row->entry_size, @@ -1775,17 +2004,15 @@ cfa_tcam_mgr_shared_entry_move(int sess_idx, struct cfa_tcam_mgr_context *contex src_row->entry_size, table_data->result_size, table_data->max_slices); - if (rc != 0) { + if (rc) CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, dir, type, "Failed to free entry ID %d at" - " row %d, slice %d for sess_idx %d. rc: %d.\n", + " row %d, slice %d. rc: %d.\n", gparms.id, src_row_index, entry->slice, - sess_idx, -rc); - } #ifdef CFA_TCAM_MGR_TRACING CFA_TCAM_MGR_TRACE(INFO, "Moved entry %d from row %d, slice %d to " @@ -1801,54 +2028,50 @@ cfa_tcam_mgr_shared_entry_move(int sess_idx, struct cfa_tcam_mgr_context *contex entry->row = dst_row_index; entry->slice = dst_row_slice; - cfa_tcam_mgr_mv_used_entries_cnt(sess_idx, dir, dst_table_data, table_data); + cfa_tcam_mgr_mv_used_entries_cnt(dst_table_data, table_data); #ifdef CFA_TCAM_MGR_TRACING - cfa_tcam_mgr_rows_dump(sess_idx, dir, type); - cfa_tcam_mgr_rows_dump(sess_idx, dir, CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS); + cfa_tcam_mgr_rows_dump(tfp, dir, type); + cfa_tcam_mgr_rows_dump(tfp, dir, + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS); #endif return 0; } -int cfa_tcam_mgr_shared_move(struct cfa_tcam_mgr_context *context, - struct cfa_tcam_mgr_shared_move_parms *parms) +int cfa_tcam_mgr_shared_move(struct tf *tfp, + struct cfa_tcam_mgr_shared_move_parms *parms) { - int rc; - int sess_idx; - uint32_t session_id; - uint16_t src_row, dst_row, row_size, slice; struct cfa_tcam_mgr_table_rows_0 *src_table_row; struct cfa_tcam_mgr_table_rows_0 *dst_table_row; struct cfa_tcam_mgr_table_data *src_table_data; struct cfa_tcam_mgr_table_data *dst_table_data; + uint16_t src_row, dst_row, row_size, slice; + struct cfa_tcam_mgr_data *tcam_mgr_data; + struct tf_session *tfs; + int rc; - CFA_TCAM_MGR_CHECK_PARMS2(context, parms); + CFA_TCAM_MGR_CHECK_PARMS2(tfp, parms); - rc = cfa_tcam_mgr_get_session_from_context(context, &session_id); + rc = tf_session_get_session_internal(tfp, &tfs); if (rc < 0) return rc; - sess_idx = cfa_tcam_mgr_session_find(session_id); - if (sess_idx < 0) { - CFA_TCAM_MGR_LOG(ERR, "Session 0x%08x not found.\n", - session_id); - return sess_idx; - } - - if (global_data_initialized[sess_idx] == 0) { - CFA_TCAM_MGR_LOG(ERR, "PANIC: No TCAM data created for sess_idx %d\n", - sess_idx); + tcam_mgr_data = tfs->tcam_mgr_handle; + if (!tcam_mgr_data) { + CFA_TCAM_MGR_LOG(ERR, "No TCAM data created for session\n"); return -CFA_TCAM_MGR_ERR_CODE(PERM); } src_table_data = - &cfa_tcam_mgr_tables[sess_idx][parms->dir][CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS]; + &tcam_mgr_data->cfa_tcam_mgr_tables[parms->dir] + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS]; dst_table_data = - &cfa_tcam_mgr_tables[sess_idx][parms->dir][CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS]; + &tcam_mgr_data->cfa_tcam_mgr_tables[parms->dir] + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS]; row_size = - cfa_tcam_mgr_row_size_get(sess_idx, + cfa_tcam_mgr_row_size_get(tcam_mgr_data, parms->dir, CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS); @@ -1868,13 +2091,13 @@ int cfa_tcam_mgr_shared_move(struct cfa_tcam_mgr_context *context, #ifdef CFA_TCAM_MGR_TRACING CFA_TCAM_MGR_TRACE(INFO, "Move entry id %d " "from src_row %d, slice %d " - "to dst_row %d, slice %d.\n", + "to dst_row %d, slice %d\n", src_table_row->entries[slice], src_row, slice, dst_row, slice); #endif - rc = cfa_tcam_mgr_shared_entry_move(sess_idx, - context, + rc = cfa_tcam_mgr_shared_entry_move(tcam_mgr_data, + tfp, parms->dir, CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS, src_table_row->entries[slice], @@ -1893,15 +2116,15 @@ int cfa_tcam_mgr_shared_move(struct cfa_tcam_mgr_context *context, } static void -cfa_tcam_mgr_tbl_get(int sess_idx, enum tf_dir dir, - enum cfa_tcam_mgr_tbl_type type, - uint16_t *start_row, - uint16_t *end_row, - uint16_t *max_entries, - uint16_t *slices) +cfa_tcam_mgr_tbl_get(struct cfa_tcam_mgr_data *tcam_mgr_data, enum tf_dir dir, + enum cfa_tcam_mgr_tbl_type type, + uint16_t *start_row, + uint16_t *end_row, + uint16_t *max_entries, + uint16_t *slices) { struct cfa_tcam_mgr_table_data *table_data = - &cfa_tcam_mgr_tables[sess_idx][dir][type]; + &tcam_mgr_data->cfa_tcam_mgr_tables[dir][type]; /* Get start, end and max for tcam type*/ *start_row = table_data->start_row; @@ -1911,51 +2134,59 @@ cfa_tcam_mgr_tbl_get(int sess_idx, enum tf_dir dir, } int -cfa_tcam_mgr_tables_get(int sess_idx, enum tf_dir dir, +cfa_tcam_mgr_tables_get(struct tf *tfp, enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type, uint16_t *start_row, uint16_t *end_row, uint16_t *max_entries, uint16_t *slices) { + struct cfa_tcam_mgr_data *tcam_mgr_data; + struct tf_session *tfs; + int rc; + CFA_TCAM_MGR_CHECK_PARMS3(start_row, end_row, max_entries); - if (global_data_initialized[sess_idx] == 0) { - CFA_TCAM_MGR_LOG(ERR, "PANIC: TCAM not initialized for sess_idx %d.\n", - sess_idx); - return -CFA_TCAM_MGR_ERR_CODE(INVAL); + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + tcam_mgr_data = tfs->tcam_mgr_handle; + if (!tcam_mgr_data) { + CFA_TCAM_MGR_LOG_0(ERR, "No TCAM data created for session.\n"); + return -CFA_TCAM_MGR_ERR_CODE(PERM); } if (dir >= TF_DIR_MAX) { - CFA_TCAM_MGR_LOG(ERR, "Must specify valid dir (0-%d) forsess_idx %d.\n", - TF_DIR_MAX - 1, sess_idx); + CFA_TCAM_MGR_LOG(ERR, "Must specify valid dir (0-%d).\n", + TF_DIR_MAX - 1); return -CFA_TCAM_MGR_ERR_CODE(INVAL); } if (type >= CFA_TCAM_MGR_TBL_TYPE_MAX) { - CFA_TCAM_MGR_LOG(ERR, "Must specify valid tbl type (0-%d) forsess_idx %d.\n", - CFA_TCAM_MGR_TBL_TYPE_MAX - 1, sess_idx); + CFA_TCAM_MGR_LOG(ERR, "Must specify valid tbl type (0-%d).\n", + CFA_TCAM_MGR_TBL_TYPE_MAX - 1); return -CFA_TCAM_MGR_ERR_CODE(INVAL); } - cfa_tcam_mgr_tbl_get(sess_idx, dir, - type, - start_row, - end_row, - max_entries, - slices); + cfa_tcam_mgr_tbl_get(tcam_mgr_data, dir, + type, + start_row, + end_row, + max_entries, + slices); return 0; } static void -cfa_tcam_mgr_tbl_set(int sess_idx, enum tf_dir dir, - enum cfa_tcam_mgr_tbl_type type, - uint16_t start_row, - uint16_t end_row, - uint16_t max_entries) +cfa_tcam_mgr_tbl_set(struct cfa_tcam_mgr_data *tcam_mgr_data, enum tf_dir dir, + enum cfa_tcam_mgr_tbl_type type, + uint16_t start_row, + uint16_t end_row, + uint16_t max_entries) { struct cfa_tcam_mgr_table_data *table_data = - &cfa_tcam_mgr_tables[sess_idx][dir][type]; + &tcam_mgr_data->cfa_tcam_mgr_tables[dir][type]; /* Update start, end and max for tcam type*/ table_data->start_row = start_row; @@ -1964,52 +2195,58 @@ cfa_tcam_mgr_tbl_set(int sess_idx, enum tf_dir dir, } int -cfa_tcam_mgr_tables_set(int sess_idx, enum tf_dir dir, +cfa_tcam_mgr_tables_set(struct tf *tfp, enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type, uint16_t start_row, uint16_t end_row, uint16_t max_entries) { - if (global_data_initialized[sess_idx] == 0) { - CFA_TCAM_MGR_LOG(ERR, "PANIC: TCAM not initialized for sess_idx %d.\n", - sess_idx); - return -CFA_TCAM_MGR_ERR_CODE(INVAL); + struct cfa_tcam_mgr_data *tcam_mgr_data; + struct tf_session *tfs; + int rc; + + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + tcam_mgr_data = tfs->tcam_mgr_handle; + if (!tcam_mgr_data) { + CFA_TCAM_MGR_LOG_0(ERR, "No TCAM data created for session.\n"); + return -CFA_TCAM_MGR_ERR_CODE(PERM); } if (dir >= TF_DIR_MAX) { - CFA_TCAM_MGR_LOG(ERR, "Must specify valid dir (0-%d) forsess_idx %d.\n", - TF_DIR_MAX - 1, sess_idx); + CFA_TCAM_MGR_LOG(ERR, "Must specify valid dir (0-%d).\n", + TF_DIR_MAX - 1); return -CFA_TCAM_MGR_ERR_CODE(INVAL); } if (type >= CFA_TCAM_MGR_TBL_TYPE_MAX) { - CFA_TCAM_MGR_LOG(ERR, "Must specify valid tbl type (0-%d) forsess_idx %d.\n", - CFA_TCAM_MGR_TBL_TYPE_MAX - 1, sess_idx); + CFA_TCAM_MGR_LOG(ERR, "Must specify valid tbl type (0-%d).\n", + CFA_TCAM_MGR_TBL_TYPE_MAX - 1); return -CFA_TCAM_MGR_ERR_CODE(INVAL); } - cfa_tcam_mgr_tbl_set(sess_idx, dir, - type, - start_row, - end_row, - max_entries); + cfa_tcam_mgr_tbl_set(tcam_mgr_data, dir, + type, + start_row, + end_row, + max_entries); return 0; } void -cfa_tcam_mgr_rows_dump(int sess_idx, enum tf_dir dir, +cfa_tcam_mgr_rows_dump(struct tf *tfp, enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type) { - struct cfa_tcam_mgr_table_data *table_data; struct cfa_tcam_mgr_table_rows_0 *table_row; - int i, row, row_size; + struct cfa_tcam_mgr_table_data *table_data; + struct cfa_tcam_mgr_data *tcam_mgr_data; + struct tf_session *tfs; bool row_found = false; bool empty_row = false; - - if (global_data_initialized[sess_idx] == 0) { - printf("PANIC: TCAM not initialized for sess_idx %d.\n", sess_idx); - return; - } + int i, row, row_size; + int rc; if (dir >= TF_DIR_MAX) { printf("Must specify a valid direction (0-%d).\n", @@ -2022,14 +2259,24 @@ cfa_tcam_mgr_rows_dump(int sess_idx, enum tf_dir dir, return; } - table_data = &cfa_tcam_mgr_tables[sess_idx][dir][type]; - row_size = cfa_tcam_mgr_row_size_get(sess_idx, dir, type); + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return; + + tcam_mgr_data = tfs->tcam_mgr_handle; + if (!tcam_mgr_data) { + printf("No TCAM data created for session\n"); + return; + } + + table_data = &tcam_mgr_data->cfa_tcam_mgr_tables[dir][type]; + row_size = cfa_tcam_mgr_row_size_get(tcam_mgr_data, dir, type); printf("\nTCAM Rows:\n"); printf("Rows for direction %s, Logical table type %s\n", tf_dir_2_str(dir), cfa_tcam_mgr_tbl_2_str(type)); - printf("Managed rows %d-%d for sess_idx %d:\n", - table_data->start_row, table_data->end_row, sess_idx); + printf("Managed rows %d-%d:\n", + table_data->start_row, table_data->end_row); printf("Index Pri Size Entry IDs\n"); printf(" Sl 0"); @@ -2066,11 +2313,12 @@ cfa_tcam_mgr_rows_dump(int sess_idx, enum tf_dir dir, } static void -cfa_tcam_mgr_table_dump(int sess_idx, enum tf_dir dir, +cfa_tcam_mgr_table_dump(struct cfa_tcam_mgr_data *tcam_mgr_data, + struct tf *tfp __rte_unused, enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type) { struct cfa_tcam_mgr_table_data *table_data = - &cfa_tcam_mgr_tables[sess_idx][dir][type]; + &tcam_mgr_data->cfa_tcam_mgr_tables[dir][type]; printf("%3s %-22s %5u %5u %5u %5u %6u %7u %2u\n", tf_dir_2_str(dir), @@ -2089,16 +2337,26 @@ cfa_tcam_mgr_table_dump(int sess_idx, enum tf_dir dir, "MaxEnt UsedEnt Slices\n" void -cfa_tcam_mgr_tables_dump(int sess_idx, enum tf_dir dir, +cfa_tcam_mgr_tables_dump(struct tf *tfp, enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type) { - if (global_data_initialized[sess_idx] == 0) { - printf("PANIC: TCAM not initialized for sess_idx %d.\n", sess_idx); + struct cfa_tcam_mgr_data *tcam_mgr_data; + struct tf_session *tfs; + int rc; + + printf("\nTCAM Table(s):\n"); + printf(TABLE_DUMP_HEADER); + + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return; + + tcam_mgr_data = tfs->tcam_mgr_handle; + if (!tcam_mgr_data) { + printf("No TCAM data created for session\n"); return; } - printf("\nTCAM Table(s) for sess_idx %d:\n", sess_idx); - printf(TABLE_DUMP_HEADER); if (dir >= TF_DIR_MAX) { /* Iterate over all directions */ for (dir = 0; dir < TF_DIR_MAX; dir++) { @@ -2107,44 +2365,53 @@ cfa_tcam_mgr_tables_dump(int sess_idx, enum tf_dir dir, for (type = 0; type < CFA_TCAM_MGR_TBL_TYPE_MAX; type++) { - cfa_tcam_mgr_table_dump(sess_idx, dir, type); + cfa_tcam_mgr_table_dump(tcam_mgr_data, + tfp, dir, type); } } else { /* Display a specific type */ - cfa_tcam_mgr_table_dump(sess_idx, dir, type); + cfa_tcam_mgr_table_dump(tcam_mgr_data, tfp, + dir, type); } } } else if (type >= CFA_TCAM_MGR_TBL_TYPE_MAX) { /* Iterate over all types for a direction */ for (type = 0; type < CFA_TCAM_MGR_TBL_TYPE_MAX; type++) - cfa_tcam_mgr_table_dump(sess_idx, dir, type); + cfa_tcam_mgr_table_dump(tcam_mgr_data, tfp, dir, type); } else { /* Display a specific direction and type */ - cfa_tcam_mgr_table_dump(sess_idx, dir, type); + cfa_tcam_mgr_table_dump(tcam_mgr_data, tfp, dir, type); } } #define ENTRY_DUMP_HEADER "Entry RefCnt Row Slice\n" void -cfa_tcam_mgr_entries_dump(int sess_idx) +cfa_tcam_mgr_entries_dump(struct tf *tfp) { + struct cfa_tcam_mgr_data *tcam_mgr_data; struct cfa_tcam_mgr_entry_data *entry; bool entry_found = false; + struct tf_session *tfs; uint16_t id; + int rc; + + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return; - if (global_data_initialized[sess_idx] == 0) { - CFA_TCAM_MGR_LOG(INFO, "PANIC: No TCAM data created for sess_idx %d\n", - sess_idx); + tcam_mgr_data = tfs->tcam_mgr_handle; + if (!tcam_mgr_data) { + printf("No TCAM data created for session\n"); return; } printf("\nGlobal Maximum Entries: %d\n\n", - cfa_tcam_mgr_max_entries[sess_idx]); + tcam_mgr_data->cfa_tcam_mgr_max_entries); printf("TCAM Entry Table:\n"); - for (id = 0; id < cfa_tcam_mgr_max_entries[sess_idx]; id++) { - if (entry_data[sess_idx][id].ref_cnt > 0) { - entry = &entry_data[sess_idx][id]; + for (id = 0; id < tcam_mgr_data->cfa_tcam_mgr_max_entries; id++) { + if (tcam_mgr_data->entry_data[id].ref_cnt > 0) { + entry = &tcam_mgr_data->entry_data[id]; if (!entry_found) printf(ENTRY_DUMP_HEADER); printf("%5u %5u %5u %5u", diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.h index e6d81cb95a..d4f8512d2a 100644 --- a/drivers/net/bnxt/tf_core/cfa_tcam_mgr.h +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2021-2023 Broadcom + * Copyright(c) 2021-2024 Broadcom * All rights reserved. */ @@ -15,10 +15,6 @@ * The TCAM module provides processing of Internal TCAM types. */ -#ifndef TF_TCAM_MAX_SESSIONS -#define TF_TCAM_MAX_SESSIONS 16 -#endif - #define ENTRY_ID_INVALID UINT16_MAX #define TF_TCAM_PRIORITY_MIN 0 @@ -45,6 +41,15 @@ TFP_DRV_LOG(level, "%s: %s " fmt, tf_dir_2_str(dir), \ cfa_tcam_mgr_tbl_2_str(type)) +/* #define CFA_TCAM_MGR_TRACING */ + +#ifdef CFA_TCAM_MGR_TRACING +#define CFA_TCAM_MGR_TRACE(level, fmt, args...) \ + printf("%s: " fmt, __func__, ## args) +#else +#define CFA_TCAM_MGR_TRACE(level, fmt, args...) +#endif + #define CFA_TCAM_MGR_ERR_CODE(type) E ## type /** @@ -79,9 +84,10 @@ } \ } while (0) +#define CFA_TCAM_MGR_TBL_TYPE_START 0 + +/* Logical TCAM tables */ enum cfa_tcam_mgr_tbl_type { - /* Logical TCAM tables */ - CFA_TCAM_MGR_TBL_TYPE_START, CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM = CFA_TCAM_MGR_TBL_TYPE_START, CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS, @@ -106,15 +112,10 @@ enum cfa_tcam_mgr_tbl_type { enum cfa_tcam_mgr_device_type { CFA_TCAM_MGR_DEVICE_TYPE_P4 = 0, - CFA_TCAM_MGR_DEVICE_TYPE_SR, CFA_TCAM_MGR_DEVICE_TYPE_P5, CFA_TCAM_MGR_DEVICE_TYPE_MAX }; -struct cfa_tcam_mgr_context { - struct tf *tfp; -}; - /** * TCAM Manager initialization parameters */ @@ -361,7 +362,7 @@ cfa_tcam_mgr_tbl_2_str(enum cfa_tcam_mgr_tbl_type tcam_type); * - (<0) on failure. */ int -cfa_tcam_mgr_init(int sess_idx, enum cfa_tcam_mgr_device_type type, +cfa_tcam_mgr_init(struct tf *tfp, enum cfa_tcam_mgr_device_type type, struct cfa_tcam_mgr_init_parms *parms); /** @@ -391,7 +392,7 @@ cfa_tcam_mgr_get_phys_table_type(enum cfa_tcam_mgr_tbl_type type); * - (<0) on failure. */ int -cfa_tcam_mgr_qcaps(struct cfa_tcam_mgr_context *context __rte_unused, +cfa_tcam_mgr_qcaps(struct tf *tfp __rte_unused, struct cfa_tcam_mgr_qcaps_parms *parms); /** @@ -408,7 +409,7 @@ cfa_tcam_mgr_qcaps(struct cfa_tcam_mgr_context *context __rte_unused, * - (0) if successful. * - (-EINVAL) on failure. */ -int cfa_tcam_mgr_bind(struct cfa_tcam_mgr_context *context, +int cfa_tcam_mgr_bind(struct tf *tfp, struct cfa_tcam_mgr_cfg_parms *parms); /** @@ -424,7 +425,7 @@ int cfa_tcam_mgr_bind(struct cfa_tcam_mgr_context *context, * - (0) if successful. * - (-EINVAL) on failure. */ -int cfa_tcam_mgr_unbind(struct cfa_tcam_mgr_context *context); +int cfa_tcam_mgr_unbind(struct tf *tfp); /** * Allocates the requested tcam type from the internal RM DB. @@ -439,7 +440,7 @@ int cfa_tcam_mgr_unbind(struct cfa_tcam_mgr_context *context); * - (0) if successful. * - (-EINVAL) on failure. */ -int cfa_tcam_mgr_alloc(struct cfa_tcam_mgr_context *context, +int cfa_tcam_mgr_alloc(struct tf *tfp, struct cfa_tcam_mgr_alloc_parms *parms); /** @@ -456,7 +457,7 @@ int cfa_tcam_mgr_alloc(struct cfa_tcam_mgr_context *context, * - (0) if successful. * - (-EINVAL) on failure. */ -int cfa_tcam_mgr_free(struct cfa_tcam_mgr_context *context, +int cfa_tcam_mgr_free(struct tf *tfp, struct cfa_tcam_mgr_free_parms *parms); /** @@ -473,7 +474,7 @@ int cfa_tcam_mgr_free(struct cfa_tcam_mgr_context *context, * - (0) if successful. * - (-EINVAL) on failure. */ -int cfa_tcam_mgr_set(struct cfa_tcam_mgr_context *context, +int cfa_tcam_mgr_set(struct tf *tfp, struct cfa_tcam_mgr_set_parms *parms); /** @@ -490,30 +491,33 @@ int cfa_tcam_mgr_set(struct cfa_tcam_mgr_context *context, * - (0) if successful. * - (-EINVAL) on failure. */ -int cfa_tcam_mgr_get(struct cfa_tcam_mgr_context *context, +int cfa_tcam_mgr_get(struct tf *tfp, struct cfa_tcam_mgr_get_parms *parms); int -cfa_tcam_mgr_tables_get(int sess_idx, enum tf_dir dir, +cfa_tcam_mgr_tables_get(struct tf *tfp, enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type, uint16_t *start_row, uint16_t *end_row, uint16_t *max_entries, uint16_t *slices); int -cfa_tcam_mgr_tables_set(int sess_idx, enum tf_dir dir, +cfa_tcam_mgr_tables_set(struct tf *tfp, enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type, uint16_t start_row, uint16_t end_row, uint16_t max_entries); -int cfa_tcam_mgr_shared_clear(struct cfa_tcam_mgr_context *context, +int cfa_tcam_mgr_shared_clear(struct tf *tfp, struct cfa_tcam_mgr_shared_clear_parms *parms); -int cfa_tcam_mgr_shared_move(struct cfa_tcam_mgr_context *context, +int cfa_tcam_mgr_shared_move(struct tf *tfp, struct cfa_tcam_mgr_shared_move_parms *parms); -void cfa_tcam_mgr_rows_dump(int sess_idx, enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type); -void cfa_tcam_mgr_tables_dump(int sess_idx, enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type); -void cfa_tcam_mgr_entries_dump(int sess_idx); +void cfa_tcam_mgr_rows_dump(struct tf *tfp, enum tf_dir dir, + enum cfa_tcam_mgr_tbl_type type); +void cfa_tcam_mgr_tables_dump(struct tf *tfp, enum tf_dir dir, + enum cfa_tcam_mgr_tbl_type type); +void cfa_tcam_mgr_entries_dump(struct tf *tfp); + #endif /* _CFA_TCAM_MGR_H */ diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_device.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_device.h index c24e5c8389..9d7f560e7b 100644 --- a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_device.h +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_device.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2021-2023 Broadcom + * Copyright(c) 2021-2024 Broadcom * All rights reserved. */ @@ -8,6 +8,34 @@ #include #include "cfa_tcam_mgr.h" +#include "bitalloc.h" + +struct cfa_tcam_mgr_data; + +/* HW OP definitions */ +typedef int (*cfa_tcam_mgr_hwop_set_func_t)(struct cfa_tcam_mgr_data + *tcam_mgr_data, + struct cfa_tcam_mgr_set_parms + *parms, int row, int slice, + int max_slices); +typedef int (*cfa_tcam_mgr_hwop_get_func_t)(struct cfa_tcam_mgr_data + *tcam_mgr_data, + struct cfa_tcam_mgr_get_parms + *parms, int row, int slice, + int max_slices); +typedef int (*cfa_tcam_mgr_hwop_free_func_t)(struct cfa_tcam_mgr_data + *tcam_mgr_data, + struct cfa_tcam_mgr_free_parms + *parms, int row, int slice, + int max_slices); + +struct cfa_tcam_mgr_hwops_funcs { + cfa_tcam_mgr_hwop_set_func_t set; + cfa_tcam_mgr_hwop_get_func_t get; + cfa_tcam_mgr_hwop_free_func_t free; +}; + +/* End: HW OP definitions */ /* * This identifier is to be used for one-off variable sizes. Do not use it for @@ -42,8 +70,7 @@ TF_TCAM_TABLE_ROWS_DEF(2); TF_TCAM_TABLE_ROWS_DEF(4); TF_TCAM_TABLE_ROWS_DEF(8); -/* - * The following macros are for setting the entry status in a row entry. +/* The following macros are for setting the entry status in a row entry. * row is (struct cfa_tcam_mgr_table_rows_0 *) */ #define ROW_ENTRY_INUSE(row, entry) ((row)->entry_inuse & (1U << (entry))) @@ -64,6 +91,13 @@ TF_TCAM_TABLE_ROWS_DEF(8); VEB_TCAM_RX_MAX_ENTRIES + \ VEB_TCAM_TX_MAX_ENTRIES) +#define TCAM_SET_END_ROW(n) ((n) ? (n) - 1 : 0) + +#define L2_CTXT_TCAM_RX_APP_LO_START (L2_CTXT_TCAM_RX_NUM_ROWS / 2) +#define L2_CTXT_TCAM_RX_APP_HI_END (L2_CTXT_TCAM_RX_APP_LO_START - 1) +#define L2_CTXT_TCAM_TX_APP_LO_START (L2_CTXT_TCAM_TX_NUM_ROWS / 2) +#define L2_CTXT_TCAM_TX_APP_HI_END (L2_CTXT_TCAM_TX_APP_LO_START - 1) + struct cfa_tcam_mgr_entry_data { uint16_t row; uint8_t slice; @@ -73,38 +107,28 @@ struct cfa_tcam_mgr_entry_data { struct cfa_tcam_mgr_table_data { struct cfa_tcam_mgr_table_rows_0 *tcam_rows; uint16_t hcapi_type; - uint16_t num_rows; /* Rows in physical TCAM */ - uint16_t start_row; /* Where the logical TCAM starts */ - uint16_t end_row; /* Where the logical TCAM ends */ + uint16_t num_rows; /* Rows in physical TCAM */ + uint16_t start_row; /* Where the logical TCAM starts */ + uint16_t end_row; /* Where the logical TCAM ends */ uint16_t max_entries; uint16_t used_entries; - uint8_t row_width; /* bytes */ - uint8_t result_size; /* bytes */ + uint8_t row_width; /* bytes */ + uint8_t result_size; /* bytes */ uint8_t max_slices; }; -extern int cfa_tcam_mgr_max_entries[TF_TCAM_MAX_SESSIONS]; - -extern struct cfa_tcam_mgr_table_data -cfa_tcam_mgr_tables[TF_TCAM_MAX_SESSIONS][TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX]; - -/* HW OP definitions begin here */ -typedef int (*cfa_tcam_mgr_hwop_set_func_t)(int sess_idx, - struct cfa_tcam_mgr_set_parms - *parms, int row, int slice, - int max_slices); -typedef int (*cfa_tcam_mgr_hwop_get_func_t)(int sess_idx, - struct cfa_tcam_mgr_get_parms - *parms, int row, int slice, - int max_slices); -typedef int (*cfa_tcam_mgr_hwop_free_func_t)(int sess_idx, - struct cfa_tcam_mgr_free_parms - *parms, int row, int slice, - int max_slices); - -struct cfa_tcam_mgr_hwops_funcs { - cfa_tcam_mgr_hwop_set_func_t set; - cfa_tcam_mgr_hwop_get_func_t get; - cfa_tcam_mgr_hwop_free_func_t free; +struct cfa_tcam_mgr_data { + int cfa_tcam_mgr_max_entries; + struct cfa_tcam_mgr_table_data + cfa_tcam_mgr_tables[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX]; + void *table_rows; + struct cfa_tcam_mgr_entry_data *entry_data; + struct bitalloc *session_bmp; + uint64_t session_bmp_size; + void *row_tables[TF_DIR_MAX][TF_TCAM_TBL_TYPE_MAX]; + void *rx_row_data; + void *tx_row_data; + struct cfa_tcam_mgr_hwops_funcs hwop_funcs; }; + #endif /* CFA_TCAM_MGR_DEVICE_H */ diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.c b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.c index 0fb5563cc3..b421309e89 100644 --- a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.c +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2021-2023 Broadcom + * Copyright(c) 2021-2024 Broadcom * All rights reserved. */ @@ -14,8 +14,8 @@ #include "tf_tcam.h" #include "hcapi_cfa_defs.h" #include "cfa_tcam_mgr.h" -#include "cfa_tcam_mgr_hwop_msg.h" #include "cfa_tcam_mgr_device.h" +#include "cfa_tcam_mgr_hwop_msg.h" #include "cfa_tcam_mgr_p58.h" #include "cfa_tcam_mgr_p4.h" #include "tf_session.h" @@ -23,20 +23,18 @@ #include "tfp.h" #include "tf_util.h" -/* - * The free hwop will free more than a single slice so cannot be used. - */ -struct cfa_tcam_mgr_hwops_funcs hwop_funcs; - int -cfa_tcam_mgr_hwops_init(enum cfa_tcam_mgr_device_type type) +cfa_tcam_mgr_hwops_init(struct cfa_tcam_mgr_data *tcam_mgr_data, + enum cfa_tcam_mgr_device_type type) { + struct cfa_tcam_mgr_hwops_funcs *hwop_funcs = + &tcam_mgr_data->hwop_funcs; + switch (type) { case CFA_TCAM_MGR_DEVICE_TYPE_P4: - case CFA_TCAM_MGR_DEVICE_TYPE_SR: - return cfa_tcam_mgr_hwops_get_funcs_p4(&hwop_funcs); + return cfa_tcam_mgr_hwops_get_funcs_p4(hwop_funcs); case CFA_TCAM_MGR_DEVICE_TYPE_P5: - return cfa_tcam_mgr_hwops_get_funcs_p58(&hwop_funcs); + return cfa_tcam_mgr_hwops_get_funcs_p58(hwop_funcs); default: CFA_TCAM_MGR_LOG(ERR, "No such device\n"); return -CFA_TCAM_MGR_ERR_CODE(NODEV); @@ -51,27 +49,27 @@ cfa_tcam_mgr_hwops_init(enum cfa_tcam_mgr_device_type type) */ int -cfa_tcam_mgr_entry_set_msg(int sess_idx, struct cfa_tcam_mgr_context *context - __rte_unused, +cfa_tcam_mgr_entry_set_msg(struct cfa_tcam_mgr_data *tcam_mgr_data, + struct tf *tfp __rte_unused, struct cfa_tcam_mgr_set_parms *parms, int row, int slice, int max_slices __rte_unused) { + enum tf_tcam_tbl_type type = + cfa_tcam_mgr_get_phys_table_type(parms->type); cfa_tcam_mgr_hwop_set_func_t set_func; - - set_func = hwop_funcs.set; - if (set_func == NULL) - return -CFA_TCAM_MGR_ERR_CODE(PERM); - struct tf_tcam_set_parms sparms; - struct tf_session *tfs; struct tf_dev_info *dev; + struct tf_session *tfs; int rc; - enum tf_tcam_tbl_type type = - cfa_tcam_mgr_get_phys_table_type(parms->type); + + set_func = tcam_mgr_data->hwop_funcs.set; + if (!set_func) + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + /* Retrieve the session information */ - rc = tf_session_get_session_internal(context->tfp, &tfs); + rc = tf_session_get_session_internal(tfp, &tfs); if (rc) return rc; @@ -91,63 +89,75 @@ cfa_tcam_mgr_entry_set_msg(int sess_idx, struct cfa_tcam_mgr_context *context sparms.result = parms->result; sparms.result_size = parms->result_size; - rc = tf_msg_tcam_entry_set(context->tfp, dev, &sparms); +#ifdef CFA_TCAM_MGR_TRACING + CFA_TCAM_MGR_LOG_DIR_TYPE(INFO, parms->dir, parms->type, + "%s: %s row:%d slice:%d " + "set tcam physical idx 0x%x\n", + tf_dir_2_str(parms->dir), + cfa_tcam_mgr_tbl_2_str(parms->type), + row, slice, sparms.idx); +#endif + + rc = tf_msg_tcam_entry_set(tfp, dev, &sparms); if (rc) { - /* Log error */ CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, parms->dir, parms->type, - "Entry %d set failed, rc:%d\n", + "%s: %s entry:%d " + "set tcam failed, rc:%d\n", + tf_dir_2_str(parms->dir), + cfa_tcam_mgr_tbl_2_str(parms->type), parms->id, -rc); return rc; } - return set_func(sess_idx, parms, row, slice, max_slices); + return set_func(tcam_mgr_data, parms, row, slice, max_slices); } int -cfa_tcam_mgr_entry_get_msg(int sess_idx, struct cfa_tcam_mgr_context *context - __rte_unused, +cfa_tcam_mgr_entry_get_msg(struct cfa_tcam_mgr_data *tcam_mgr_data, + struct tf *tfp __rte_unused, struct cfa_tcam_mgr_get_parms *parms, int row, int slice, int max_slices __rte_unused) { cfa_tcam_mgr_hwop_get_func_t get_func; - get_func = hwop_funcs.get; - if (get_func == NULL) + get_func = tcam_mgr_data->hwop_funcs.get; + if (!get_func) return -CFA_TCAM_MGR_ERR_CODE(PERM); - return get_func(sess_idx, parms, row, slice, max_slices); + return get_func(tcam_mgr_data, parms, row, slice, max_slices); } int -cfa_tcam_mgr_entry_free_msg(int sess_idx, struct cfa_tcam_mgr_context *context - __rte_unused, +cfa_tcam_mgr_entry_free_msg(struct cfa_tcam_mgr_data *tcam_mgr_data, + struct tf *tfp __rte_unused, struct cfa_tcam_mgr_free_parms *parms, int row, int slice, int key_size, int result_size, int max_slices) { + enum tf_tcam_tbl_type type = + cfa_tcam_mgr_get_phys_table_type(parms->type); + uint8_t mask[CFA_TCAM_MGR_MAX_KEY_SIZE] = { 0 }; + uint8_t key[CFA_TCAM_MGR_MAX_KEY_SIZE] = { 0 }; cfa_tcam_mgr_hwop_free_func_t free_func; - - free_func = hwop_funcs.free; - if (free_func == NULL) - return -CFA_TCAM_MGR_ERR_CODE(PERM); - + struct tf_tcam_set_parms sparms; struct tf_dev_info *dev; struct tf_session *tfs; int rc; - enum tf_tcam_tbl_type type = - cfa_tcam_mgr_get_phys_table_type(parms->type); - /* Free will clear an entire row. */ - /* Use set message to clear an individual entry */ - struct tf_tcam_set_parms sparms; - uint8_t key[CFA_TCAM_MGR_MAX_KEY_SIZE] = { 0 }; - uint8_t mask[CFA_TCAM_MGR_MAX_KEY_SIZE] = { 0 }; + free_func = tcam_mgr_data->hwop_funcs.free; + if (!free_func) + return -CFA_TCAM_MGR_ERR_CODE(PERM); + + /* + * The free hwop will free more than a single slice (an entire row), + * so cannot be used. Use set message to clear an individual entry + */ /* Retrieve the session information */ - rc = tf_session_get_session_internal(context->tfp, &tfs); + rc = tf_session_get_session_internal(tfp, &tfs); if (rc) return rc; @@ -158,7 +168,9 @@ cfa_tcam_mgr_entry_free_msg(int sess_idx, struct cfa_tcam_mgr_context *context if (key_size > CFA_TCAM_MGR_MAX_KEY_SIZE) { CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, parms->dir, parms->type, - "Entry %d key size is %d greater than:%d\n", + "%s: %s entry:%d key size:%d > %d\n", + tf_dir_2_str(parms->dir), + cfa_tcam_mgr_tbl_2_str(parms->type), parms->id, key_size, CFA_TCAM_MGR_MAX_KEY_SIZE); return -EINVAL; @@ -166,7 +178,9 @@ cfa_tcam_mgr_entry_free_msg(int sess_idx, struct cfa_tcam_mgr_context *context if (result_size > CFA_TCAM_MGR_MAX_KEY_SIZE) { CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, parms->dir, parms->type, - "Entry %d result size is %d greater than:%d\n", + "%s: %s entry:%d res size:%d > %d\n", + tf_dir_2_str(parms->dir), + cfa_tcam_mgr_tbl_2_str(parms->type), parms->id, result_size, CFA_TCAM_MGR_MAX_KEY_SIZE); return -EINVAL; @@ -186,16 +200,27 @@ cfa_tcam_mgr_entry_free_msg(int sess_idx, struct cfa_tcam_mgr_context *context sparms.key_size = key_size; sparms.result_size = result_size; - rc = tf_msg_tcam_entry_set(context->tfp, dev, &sparms); +#ifdef CFA_TCAM_MGR_TRACING + CFA_TCAM_MGR_LOG_DIR_TYPE(INFO, parms->dir, parms->type, + "%s: %s row:%d slice:%d free idx:%d " + "key_sz:%d result_sz:%d\n", + tf_dir_2_str(parms->dir), + cfa_tcam_mgr_tbl_2_str(parms->type), + row, slice, sparms.idx, key_size, + result_size); +#endif + + rc = tf_msg_tcam_entry_set(tfp, dev, &sparms); if (rc) { /* Log error */ CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, parms->dir, parms->type, - "Row %d, slice %d set failed, " - "rc:%d.\n", - row, - slice, - rc); + "%s: %s row:%d slice:%d set failed, " + "rc:%d\n", + tf_dir_2_str(parms->dir), + cfa_tcam_mgr_tbl_2_str(parms->type), + row, slice, rc); return rc; } - return free_func(sess_idx, parms, row, slice, max_slices); + + return free_func(tcam_mgr_data, parms, row, slice, max_slices); } diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.h index f7ba625c07..3b896d4548 100644 --- a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.h +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2021-2023 Broadcom + * Copyright(c) 2021-2024 Broadcom * All rights reserved. */ @@ -7,22 +7,24 @@ #define CFA_TCAM_MGR_HWOP_MSG_H int -cfa_tcam_mgr_hwops_init(enum cfa_tcam_mgr_device_type type); +cfa_tcam_mgr_hwops_init(struct cfa_tcam_mgr_data *tcam_mgr_data, + enum cfa_tcam_mgr_device_type type); int -cfa_tcam_mgr_entry_set_msg(int sess_idx, - struct cfa_tcam_mgr_context *context, +cfa_tcam_mgr_entry_set_msg(struct cfa_tcam_mgr_data *tcam_mgr_data, + struct tf *tfp, struct cfa_tcam_mgr_set_parms *parms, int row, int slice, int max_slices); int -cfa_tcam_mgr_entry_get_msg(int sess_idx, - struct cfa_tcam_mgr_context *context, +cfa_tcam_mgr_entry_get_msg(struct cfa_tcam_mgr_data *tcam_mgr_data, + struct tf *tfp, struct cfa_tcam_mgr_get_parms *parms, int row, int slice, int max_slices); int -cfa_tcam_mgr_entry_free_msg(int sess_idx, - struct cfa_tcam_mgr_context *context, +cfa_tcam_mgr_entry_free_msg(struct cfa_tcam_mgr_data *tcam_mgr_data, + struct tf *tfp, struct cfa_tcam_mgr_free_parms *parms, int row, int slice, int key_size, int result_size, int max_slices); + #endif /* CFA_TCAM_MGR_HWOP_MSG_H */ diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c index 63c84c5938..b2eadde61e 100644 --- a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2021-2023 Broadcom + * Copyright(c) 2021-2024 Broadcom * All rights reserved. */ @@ -12,6 +12,7 @@ #include "tfp.h" #include "assert.h" #include "tf_util.h" +#include "tf_session.h" /* * Sizings of the TCAMs on P4 @@ -126,38 +127,40 @@ * Array sizes have 1 added to avoid zero length arrays. */ -static struct cfa_tcam_mgr_table_rows_1 - cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[TF_TCAM_MAX_SESSIONS][L2_CTXT_TCAM_RX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_1 - cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[TF_TCAM_MAX_SESSIONS][L2_CTXT_TCAM_TX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_1 - cfa_tcam_mgr_table_rows_PROF_TCAM_RX[TF_TCAM_MAX_SESSIONS][PROF_TCAM_RX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_1 - cfa_tcam_mgr_table_rows_PROF_TCAM_TX[TF_TCAM_MAX_SESSIONS][PROF_TCAM_TX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_4 - cfa_tcam_mgr_table_rows_WC_TCAM_RX[TF_TCAM_MAX_SESSIONS][WC_TCAM_RX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_4 - cfa_tcam_mgr_table_rows_WC_TCAM_TX[TF_TCAM_MAX_SESSIONS][WC_TCAM_TX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_1 - cfa_tcam_mgr_table_rows_SP_TCAM_RX[TF_TCAM_MAX_SESSIONS][SP_TCAM_RX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_1 - cfa_tcam_mgr_table_rows_SP_TCAM_TX[TF_TCAM_MAX_SESSIONS][SP_TCAM_TX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_1 - cfa_tcam_mgr_table_rows_CT_RULE_TCAM_RX[TF_TCAM_MAX_SESSIONS][CT_RULE_TCAM_RX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_1 - cfa_tcam_mgr_table_rows_CT_RULE_TCAM_TX[TF_TCAM_MAX_SESSIONS][CT_RULE_TCAM_TX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_1 - cfa_tcam_mgr_table_rows_VEB_TCAM_RX[TF_TCAM_MAX_SESSIONS][VEB_TCAM_RX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_1 - cfa_tcam_mgr_table_rows_VEB_TCAM_TX[TF_TCAM_MAX_SESSIONS][VEB_TCAM_TX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_4 - cfa_tcam_mgr_table_rows_WC_TCAM_RX_HIGH[TF_TCAM_MAX_SESSIONS][WC_TCAM_RX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_4 - cfa_tcam_mgr_table_rows_WC_TCAM_RX_LOW[TF_TCAM_MAX_SESSIONS][WC_TCAM_RX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_4 - cfa_tcam_mgr_table_rows_WC_TCAM_TX_HIGH[TF_TCAM_MAX_SESSIONS][WC_TCAM_TX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_4 - cfa_tcam_mgr_table_rows_WC_TCAM_TX_LOW[TF_TCAM_MAX_SESSIONS][WC_TCAM_TX_NUM_ROWS + 1]; +struct cfa_tcam_mgr_table_rows_p4 { + struct cfa_tcam_mgr_table_rows_1 + table_rows_L2_CTXT_TCAM_RX[L2_CTXT_TCAM_RX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_1 + table_rows_L2_CTXT_TCAM_TX[L2_CTXT_TCAM_TX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_1 + table_rows_PROF_TCAM_RX[PROF_TCAM_RX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_1 + table_rows_PROF_TCAM_TX[PROF_TCAM_TX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_4 + table_rows_WC_TCAM_RX[WC_TCAM_RX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_4 + table_rows_WC_TCAM_TX[WC_TCAM_TX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_1 + table_rows_SP_TCAM_RX[SP_TCAM_RX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_1 + table_rows_SP_TCAM_TX[SP_TCAM_TX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_1 + table_rows_CT_RULE_TCAM_RX[CT_RULE_TCAM_RX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_1 + table_rows_CT_RULE_TCAM_TX[CT_RULE_TCAM_TX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_1 + table_rows_VEB_TCAM_RX[VEB_TCAM_RX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_1 + table_rows_VEB_TCAM_TX[VEB_TCAM_TX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_4 + table_rows_WC_TCAM_RX_HIGH[WC_TCAM_RX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_4 + table_rows_WC_TCAM_RX_LOW[WC_TCAM_RX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_4 + table_rows_WC_TCAM_TX_HIGH[WC_TCAM_TX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_4 + table_rows_WC_TCAM_TX_LOW[WC_TCAM_TX_NUM_ROWS + 1]; +}; struct cfa_tcam_mgr_table_data cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { @@ -177,7 +180,7 @@ cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH, .num_rows = L2_CTXT_TCAM_RX_NUM_ROWS, .start_row = 0, - .end_row = (L2_CTXT_TCAM_RX_NUM_ROWS / 2) - 1, + .end_row = L2_CTXT_TCAM_RX_APP_HI_END, .max_entries = (L2_CTXT_TCAM_RX_MAX_ENTRIES / 2), .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE, .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH, @@ -196,7 +199,7 @@ cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES, .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH, .num_rows = L2_CTXT_TCAM_RX_NUM_ROWS, - .start_row = (L2_CTXT_TCAM_RX_NUM_ROWS / 2), + .start_row = L2_CTXT_TCAM_RX_APP_LO_START, .end_row = L2_CTXT_TCAM_RX_NUM_ROWS - 1, .max_entries = (L2_CTXT_TCAM_RX_MAX_ENTRIES / 2), .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE, @@ -277,7 +280,8 @@ cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .num_rows = CT_RULE_TCAM_RX_NUM_ROWS, .start_row = 0, #if CT_RULE_TCAM_RX_NUM_ROWS > 0 - .end_row = CT_RULE_TCAM_RX_NUM_ROWS - 1, + .end_row = + TCAM_SET_END_ROW(CT_RULE_TCAM_RX_NUM_ROWS), #else .end_row = CT_RULE_TCAM_RX_NUM_ROWS, #endif @@ -299,7 +303,8 @@ cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .num_rows = VEB_TCAM_RX_NUM_ROWS, .start_row = 0, #if VEB_TCAM_RX_NUM_ROWS > 0 - .end_row = VEB_TCAM_RX_NUM_ROWS - 1, + .end_row = + TCAM_SET_END_ROW(VEB_TCAM_RX_NUM_ROWS), #else .end_row = VEB_TCAM_RX_NUM_ROWS, #endif @@ -363,7 +368,7 @@ cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH, .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS, .start_row = 0, - .end_row = (L2_CTXT_TCAM_TX_NUM_ROWS / 2) - 1, + .end_row = L2_CTXT_TCAM_TX_APP_HI_END, .max_entries = (L2_CTXT_TCAM_TX_MAX_ENTRIES / 2), .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE, .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH, @@ -382,7 +387,7 @@ cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES, .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH, .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS, - .start_row = (L2_CTXT_TCAM_TX_NUM_ROWS / 2), + .start_row = L2_CTXT_TCAM_TX_APP_LO_START, .end_row = L2_CTXT_TCAM_TX_NUM_ROWS - 1, .max_entries = (L2_CTXT_TCAM_TX_MAX_ENTRIES / 2), .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE, @@ -463,7 +468,8 @@ cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .num_rows = CT_RULE_TCAM_TX_NUM_ROWS, .start_row = 0, #if CT_RULE_TCAM_TX_NUM_ROWS > 0 - .end_row = CT_RULE_TCAM_TX_NUM_ROWS - 1, + .end_row = + TCAM_SET_END_ROW(CT_RULE_TCAM_TX_NUM_ROWS), #else .end_row = CT_RULE_TCAM_TX_NUM_ROWS, #endif @@ -487,6 +493,7 @@ cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .end_row = VEB_TCAM_TX_NUM_ROWS - 1, .max_entries = VEB_TCAM_TX_MAX_ENTRIES, .result_size = VEB_TCAM_RX_RESULT_SIZE, +/* .hcapi_type = */ }, { /* AFM */ .max_slices = WC_TCAM_TX_MAX_SLICES, @@ -531,221 +538,311 @@ cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { }, }; -static struct cfa_tcam_mgr_entry_data entry_data_p4[TF_TCAM_MAX_SESSIONS][TF_TCAM_MAX_ENTRIES]; - -static struct sbmp session_bmp_p4[TF_TCAM_MAX_SESSIONS][TF_TCAM_MAX_ENTRIES]; +static int cfa_tcam_mgr_row_data_alloc(struct cfa_tcam_mgr_data *tcam_mgr_data); +static void cfa_tcam_mgr_row_data_free(struct cfa_tcam_mgr_data *tcam_mgr_data); -int -cfa_tcam_mgr_sess_table_get_p4(int sess_idx, struct sbmp **session_bmp) +static void cfa_tcam_mgr_data_free(struct tf_session *tfs) { - *session_bmp = session_bmp_p4[sess_idx]; - return 0; + struct cfa_tcam_mgr_data *tcam_mgr_data = tfs->tcam_mgr_handle; + + if (!tcam_mgr_data) + return; + + tfp_free(tcam_mgr_data->table_rows); + tfp_free(tcam_mgr_data->entry_data); + tfp_free(tcam_mgr_data->session_bmp); + cfa_tcam_mgr_row_data_free(tcam_mgr_data); + + tfp_free(tcam_mgr_data); + tfs->tcam_mgr_handle = NULL; } int -cfa_tcam_mgr_init_p4(int sess_idx, struct cfa_tcam_mgr_entry_data **global_entry_data) +cfa_tcam_mgr_init_p4(struct tf *tfp) { - int max_row_width = 0; + struct cfa_tcam_mgr_table_rows_p4 *table_rows; + struct cfa_tcam_mgr_data *tcam_mgr_data; + struct tfp_calloc_parms cparms; int max_result_size = 0; + struct tf_session *tfs; + int max_row_width = 0; int dir, type; + int rc; + + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + cparms.nitems = 1; + cparms.size = sizeof(struct cfa_tcam_mgr_data); + cparms.alignment = 0; + rc = tfp_calloc(&cparms); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "Failed to allocate block, rc:%s\n", + strerror(-rc)); + return rc; + } - *global_entry_data = entry_data_p4[sess_idx]; + tfs->tcam_mgr_handle = (struct cfa_tcam_mgr_data *)cparms.mem_va; + tcam_mgr_data = tfs->tcam_mgr_handle; - memcpy(&cfa_tcam_mgr_tables[sess_idx], + cparms.nitems = 1; + cparms.size = sizeof(struct cfa_tcam_mgr_table_rows_p4); + cparms.alignment = 0; + rc = tfp_calloc(&cparms); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "Failed to allocate block, rc:%s\n", + strerror(-rc)); + tfp_free(tfs->tcam_mgr_handle); + tfs->tcam_mgr_handle = NULL; + return rc; + } + tcam_mgr_data->table_rows = + (struct cfa_tcam_mgr_table_rows_p4 *)cparms.mem_va; + table_rows = tcam_mgr_data->table_rows; + + cparms.nitems = TF_TCAM_MAX_ENTRIES; + cparms.size = sizeof(struct cfa_tcam_mgr_entry_data); + cparms.alignment = 0; + rc = tfp_calloc(&cparms); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "Failed to allocate block, rc:%s\n", + strerror(-rc)); + goto fail; + } + tcam_mgr_data->entry_data = + (struct cfa_tcam_mgr_entry_data *)cparms.mem_va; + + rc = cfa_tcam_mgr_row_data_alloc(tcam_mgr_data); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "Failed to allocate tcam_mgr_row_data, rc:%s\n", + strerror(-rc)); + goto fail; + } + + memcpy(&tcam_mgr_data->cfa_tcam_mgr_tables, &cfa_tcam_mgr_tables_p4, - sizeof(cfa_tcam_mgr_tables[sess_idx])); + sizeof(tcam_mgr_data->cfa_tcam_mgr_tables)); - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + &table_rows->table_rows_L2_CTXT_TCAM_RX[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx]; + &table_rows->table_rows_L2_CTXT_TCAM_RX[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + &table_rows->table_rows_L2_CTXT_TCAM_TX[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx]; + &table_rows->table_rows_L2_CTXT_TCAM_TX[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + &table_rows->table_rows_L2_CTXT_TCAM_RX[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx]; + &table_rows->table_rows_L2_CTXT_TCAM_RX[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + &table_rows->table_rows_L2_CTXT_TCAM_TX[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx]; + &table_rows->table_rows_L2_CTXT_TCAM_TX[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_PROF_TCAM_RX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + &table_rows->table_rows_PROF_TCAM_RX[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_PROF_TCAM_RX[sess_idx]; + &table_rows->table_rows_PROF_TCAM_RX[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_PROF_TCAM_TX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + &table_rows->table_rows_PROF_TCAM_TX[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_PROF_TCAM_TX[sess_idx]; + &table_rows->table_rows_PROF_TCAM_TX[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_WC_TCAM_RX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + &table_rows->table_rows_WC_TCAM_RX[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_WC_TCAM_RX[sess_idx]; + &table_rows->table_rows_WC_TCAM_RX[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_WC_TCAM_TX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + &table_rows->table_rows_WC_TCAM_TX[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_WC_TCAM_TX[sess_idx]; + &table_rows->table_rows_WC_TCAM_TX[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_SP_TCAM_RX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + &table_rows->table_rows_SP_TCAM_RX[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_SP_TCAM_RX[sess_idx]; + &table_rows->table_rows_SP_TCAM_RX[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_SP_TCAM_TX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + &table_rows->table_rows_SP_TCAM_TX[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_SP_TCAM_TX[sess_idx]; + &table_rows->table_rows_SP_TCAM_TX[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_RX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + &table_rows->table_rows_CT_RULE_TCAM_RX[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_RX[sess_idx]; + &table_rows->table_rows_CT_RULE_TCAM_RX[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_TX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + &table_rows->table_rows_CT_RULE_TCAM_TX[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_TX[sess_idx]; + &table_rows->table_rows_CT_RULE_TCAM_TX[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_VEB_TCAM_RX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + &table_rows->table_rows_VEB_TCAM_RX[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_VEB_TCAM_RX[sess_idx]; + &table_rows->table_rows_VEB_TCAM_RX[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_VEB_TCAM_TX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + &table_rows->table_rows_VEB_TCAM_TX[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_VEB_TCAM_TX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + &table_rows->table_rows_VEB_TCAM_TX[0]; + + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_WC_TCAM_RX_HIGH[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + &table_rows->table_rows_WC_TCAM_RX_HIGH[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_WC_TCAM_RX_HIGH[sess_idx]; + &table_rows->table_rows_WC_TCAM_RX_HIGH[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_WC_TCAM_TX_HIGH[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + &table_rows->table_rows_WC_TCAM_TX_HIGH[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_WC_TCAM_TX_HIGH[sess_idx]; + &table_rows->table_rows_WC_TCAM_TX_HIGH[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_WC_TCAM_RX_LOW[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + &table_rows->table_rows_WC_TCAM_RX_LOW[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_WC_TCAM_RX_LOW[sess_idx]; + &table_rows->table_rows_WC_TCAM_RX_LOW[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_WC_TCAM_TX_LOW[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + &table_rows->table_rows_WC_TCAM_TX_LOW[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_WC_TCAM_TX_LOW[sess_idx]; + &table_rows->table_rows_WC_TCAM_TX_LOW[0]; for (dir = 0; dir < TF_DIR_MAX; dir++) { for (type = 0; type < CFA_TCAM_MGR_TBL_TYPE_MAX; type++) { - if (cfa_tcam_mgr_tables[sess_idx][dir][type].row_width > - max_row_width) + if (tcam_mgr_data->cfa_tcam_mgr_tables[dir] + [type].row_width > + max_row_width) max_row_width = - cfa_tcam_mgr_tables[sess_idx][dir][type].row_width; - if (cfa_tcam_mgr_tables[sess_idx][dir][type].result_size > - max_result_size) + tcam_mgr_data->cfa_tcam_mgr_tables[dir] + [type].row_width; + if (tcam_mgr_data->cfa_tcam_mgr_tables[dir] + [type].result_size > + max_result_size) max_result_size = - cfa_tcam_mgr_tables[sess_idx][dir][type].result_size; + tcam_mgr_data->cfa_tcam_mgr_tables[dir] + [type].result_size; } } if (max_row_width != MAX_ROW_WIDTH) { CFA_TCAM_MGR_LOG(ERR, - "MAX_ROW_WIDTH (%d) does not match actual " - "value (%d).\n", - MAX_ROW_WIDTH, - max_row_width); - return -CFA_TCAM_MGR_ERR_CODE(INVAL); + "MAX_ROW_WIDTH:%d does not match val:%d\n", + MAX_ROW_WIDTH, max_row_width); + rc = -CFA_TCAM_MGR_ERR_CODE(INVAL); + goto fail; } if (max_result_size != MAX_RESULT_SIZE) { CFA_TCAM_MGR_LOG(ERR, - "MAX_RESULT_SIZE (%d) does not match actual " - "value (%d).\n", - MAX_RESULT_SIZE, - max_result_size); - return -CFA_TCAM_MGR_ERR_CODE(INVAL); + "MAX_RESULT_SIZE:%d does not match val:%d\n", + MAX_RESULT_SIZE, max_result_size); + rc = -CFA_TCAM_MGR_ERR_CODE(INVAL); + goto fail; } + return 0; + +fail: + cfa_tcam_mgr_data_free(tfs); + return rc; +} + +void cfa_tcam_mgr_uninit_p4(struct tf *tfp) +{ + struct tf_session *tfs; + int rc; + + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return; + + cfa_tcam_mgr_data_free(tfs); } /* HW OP declarations begin here */ @@ -776,133 +873,182 @@ struct cfa_tcam_mgr_TCAM_row_data { (CT_RULE_TCAM_TX_MAX_SLICES * CT_RULE_TCAM_TX_NUM_ROWS) #define VEB_TX_MAX_ROWS (VEB_TCAM_TX_MAX_SLICES * VEB_TCAM_TX_NUM_ROWS) -static int cfa_tcam_mgr_max_rows[TF_TCAM_TBL_TYPE_MAX] = { - L2_CTXT_RX_MAX_ROWS, - L2_CTXT_RX_MAX_ROWS, - PROF_RX_MAX_ROWS, - WC_RX_MAX_ROWS, - SP_RX_MAX_ROWS, - CT_RULE_RX_MAX_ROWS, - VEB_RX_MAX_ROWS, - WC_RX_MAX_ROWS, - WC_RX_MAX_ROWS +struct cfa_tcam_mgr_rx_row_data { + struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[L2_CTXT_RX_MAX_ROWS + 1]; + struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_PROF_TCAM_RX_row_data[PROF_RX_MAX_ROWS + 1]; + struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_WC_TCAM_RX_row_data[WC_RX_MAX_ROWS + 1]; + struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_SP_TCAM_RX_row_data[SP_RX_MAX_ROWS + 1]; + struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_CT_RULE_TCAM_RX_row_data[CT_RULE_RX_MAX_ROWS + 1]; + struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_VEB_TCAM_RX_row_data[VEB_RX_MAX_ROWS + 1]; }; -static struct cfa_tcam_mgr_TCAM_row_data - cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][L2_CTXT_RX_MAX_ROWS]; -static struct cfa_tcam_mgr_TCAM_row_data - cfa_tcam_mgr_PROF_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][PROF_RX_MAX_ROWS]; -static struct cfa_tcam_mgr_TCAM_row_data - cfa_tcam_mgr_WC_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][WC_RX_MAX_ROWS]; -static struct cfa_tcam_mgr_TCAM_row_data - cfa_tcam_mgr_SP_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][SP_RX_MAX_ROWS]; -static struct cfa_tcam_mgr_TCAM_row_data - cfa_tcam_mgr_CT_RULE_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][CT_RULE_RX_MAX_ROWS]; -static struct cfa_tcam_mgr_TCAM_row_data - cfa_tcam_mgr_VEB_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][VEB_RX_MAX_ROWS]; -static struct cfa_tcam_mgr_TCAM_row_data - cfa_tcam_mgr_WC_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][WC_RX_MAX_ROWS]; - -static struct cfa_tcam_mgr_TCAM_row_data - cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][L2_CTXT_TX_MAX_ROWS]; -static struct cfa_tcam_mgr_TCAM_row_data - cfa_tcam_mgr_PROF_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][PROF_TX_MAX_ROWS]; -static struct cfa_tcam_mgr_TCAM_row_data - cfa_tcam_mgr_WC_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][WC_TX_MAX_ROWS]; -static struct cfa_tcam_mgr_TCAM_row_data - cfa_tcam_mgr_SP_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][SP_TX_MAX_ROWS]; -static struct cfa_tcam_mgr_TCAM_row_data - cfa_tcam_mgr_CT_RULE_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][CT_RULE_TX_MAX_ROWS]; -static struct cfa_tcam_mgr_TCAM_row_data - cfa_tcam_mgr_VEB_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][VEB_TX_MAX_ROWS]; -static struct cfa_tcam_mgr_TCAM_row_data - cfa_tcam_mgr_WC_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][WC_TX_MAX_ROWS]; - -static struct cfa_tcam_mgr_TCAM_row_data * -row_tables[TF_DIR_MAX][TF_TCAM_TBL_TYPE_MAX] = { - { - cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[0], - cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[0], - cfa_tcam_mgr_PROF_TCAM_RX_row_data[0], - cfa_tcam_mgr_WC_TCAM_RX_row_data[0], - cfa_tcam_mgr_SP_TCAM_RX_row_data[0], - cfa_tcam_mgr_CT_RULE_TCAM_RX_row_data[0], - cfa_tcam_mgr_VEB_TCAM_RX_row_data[0], - cfa_tcam_mgr_WC_TCAM_RX_row_data[0], - cfa_tcam_mgr_WC_TCAM_RX_row_data[0], - }, - { - cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[0], - cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[0], - cfa_tcam_mgr_PROF_TCAM_TX_row_data[0], - cfa_tcam_mgr_WC_TCAM_TX_row_data[0], - cfa_tcam_mgr_SP_TCAM_TX_row_data[0], - cfa_tcam_mgr_CT_RULE_TCAM_TX_row_data[0], - cfa_tcam_mgr_VEB_TCAM_TX_row_data[0], - cfa_tcam_mgr_WC_TCAM_TX_row_data[0], - cfa_tcam_mgr_WC_TCAM_TX_row_data[0], - } + +struct cfa_tcam_mgr_tx_row_data { + struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[L2_CTXT_TX_MAX_ROWS + 1]; + struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_PROF_TCAM_TX_row_data[PROF_TX_MAX_ROWS + 1]; + struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_WC_TCAM_TX_row_data[WC_TX_MAX_ROWS + 1]; + struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_SP_TCAM_TX_row_data[SP_TX_MAX_ROWS + 1]; + struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_CT_RULE_TCAM_TX_row_data[CT_RULE_TX_MAX_ROWS + 1]; + struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_VEB_TCAM_TX_row_data[VEB_TX_MAX_ROWS + 1]; }; -static int cfa_tcam_mgr_get_max_rows(enum tf_tcam_tbl_type type) +#define TF_TCAM_L2_CTX_HI TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH +#define TF_TCAM_L2_CTX_LO TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW +#define TF_TCAM_PROF TF_TCAM_TBL_TYPE_PROF_TCAM +#define TF_TCAM_WC TF_TCAM_TBL_TYPE_WC_TCAM +#define TF_TCAM_SP TF_TCAM_TBL_TYPE_SP_TCAM +#define TF_TCAM_CT TF_TCAM_TBL_TYPE_CT_RULE_TCAM +#define TF_TCAM_VEB TF_TCAM_TBL_TYPE_VEB_TCAM +#define TF_TCAM_WC_HI TF_TCAM_TBL_TYPE_WC_TCAM_HIGH +#define TF_TCAM_WC_LO TF_TCAM_TBL_TYPE_WC_TCAM_LOW + +static int cfa_tcam_mgr_row_data_alloc(struct cfa_tcam_mgr_data *tcam_mgr_data) { - if (type >= TF_TCAM_TBL_TYPE_MAX) - assert(0); - else - return cfa_tcam_mgr_max_rows[type]; + struct cfa_tcam_mgr_rx_row_data *rx_row_data; + struct cfa_tcam_mgr_tx_row_data *tx_row_data; + struct tfp_calloc_parms cparms; + int rc; + + cparms.nitems = 1; + cparms.size = sizeof(struct cfa_tcam_mgr_rx_row_data); + cparms.alignment = 0; + rc = tfp_calloc(&cparms); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "Failed to allocate rx_row_data, rc:%s\n", + strerror(-rc)); + return -ENOMEM; + } + + rx_row_data = (struct cfa_tcam_mgr_rx_row_data *)cparms.mem_va; + + cparms.nitems = 1; + cparms.size = sizeof(struct cfa_tcam_mgr_tx_row_data); + cparms.alignment = 0; + rc = tfp_calloc(&cparms); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "Failed to allocate tx_row_data, rc:%s\n", + strerror(-rc)); + tfp_free(rx_row_data); + return -ENOMEM; + } + + tx_row_data = (struct cfa_tcam_mgr_tx_row_data *)cparms.mem_va; + + tcam_mgr_data->rx_row_data = rx_row_data; + tcam_mgr_data->tx_row_data = tx_row_data; + + tcam_mgr_data->row_tables[TF_DIR_RX][TF_TCAM_L2_CTX_HI] = + &rx_row_data->cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_RX][TF_TCAM_L2_CTX_LO] = + &rx_row_data->cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_RX][TF_TCAM_PROF] = + &rx_row_data->cfa_tcam_mgr_PROF_TCAM_RX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_RX][TF_TCAM_WC] = + &rx_row_data->cfa_tcam_mgr_WC_TCAM_RX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_RX][TF_TCAM_SP] = + &rx_row_data->cfa_tcam_mgr_SP_TCAM_RX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_RX][TF_TCAM_CT] = + &rx_row_data->cfa_tcam_mgr_CT_RULE_TCAM_RX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_RX][TF_TCAM_VEB] = + &rx_row_data->cfa_tcam_mgr_VEB_TCAM_RX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_RX][TF_TCAM_WC_HI] = + &rx_row_data->cfa_tcam_mgr_WC_TCAM_RX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_RX][TF_TCAM_WC_LO] = + &rx_row_data->cfa_tcam_mgr_WC_TCAM_RX_row_data[0]; + + tcam_mgr_data->row_tables[TF_DIR_TX][TF_TCAM_L2_CTX_HI] = + &tx_row_data->cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_TX][TF_TCAM_L2_CTX_LO] = + &tx_row_data->cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_TX][TF_TCAM_PROF] = + &tx_row_data->cfa_tcam_mgr_PROF_TCAM_TX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_TX][TF_TCAM_WC] = + &tx_row_data->cfa_tcam_mgr_WC_TCAM_TX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_TX][TF_TCAM_SP] = + &tx_row_data->cfa_tcam_mgr_SP_TCAM_TX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_TX][TF_TCAM_CT] = + &tx_row_data->cfa_tcam_mgr_CT_RULE_TCAM_TX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_TX][TF_TCAM_VEB] = + &tx_row_data->cfa_tcam_mgr_VEB_TCAM_TX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_TX][TF_TCAM_WC_HI] = + &tx_row_data->cfa_tcam_mgr_WC_TCAM_TX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_TX][TF_TCAM_WC_LO] = + &tx_row_data->cfa_tcam_mgr_WC_TCAM_TX_row_data[0]; + + return 0; } -static int cfa_tcam_mgr_hwop_set(int sess_idx, +static void cfa_tcam_mgr_row_data_free(struct cfa_tcam_mgr_data + *tcam_mgr_data) +{ + tfp_free(tcam_mgr_data->rx_row_data); + tfp_free(tcam_mgr_data->tx_row_data); +} + +static int cfa_tcam_mgr_hwop_set(struct cfa_tcam_mgr_data *tcam_mgr_data, struct cfa_tcam_mgr_set_parms *parms, int row, int slice, int max_slices) { struct cfa_tcam_mgr_TCAM_row_data *this_table; struct cfa_tcam_mgr_TCAM_row_data *this_row; - this_table = row_tables[parms->dir] + + this_table = tcam_mgr_data->row_tables[parms->dir] [cfa_tcam_mgr_get_phys_table_type(parms->type)]; - this_table += (sess_idx * - cfa_tcam_mgr_get_max_rows(cfa_tcam_mgr_get_phys_table_type(parms->type))); this_row = &this_table[row * max_slices + slice]; this_row->key_size = parms->key_size; memcpy(&this_row->key, parms->key, parms->key_size); memcpy(&this_row->mask, parms->mask, parms->key_size); this_row->result_size = parms->result_size; - if (parms->result != ((void *)0)) + if (parms->result) memcpy(&this_row->result, parms->result, parms->result_size); return 0; }; -static int cfa_tcam_mgr_hwop_get(int sess_idx, +static int cfa_tcam_mgr_hwop_get(struct cfa_tcam_mgr_data *tcam_mgr_data, struct cfa_tcam_mgr_get_parms *parms, int row, int slice, int max_slices) { struct cfa_tcam_mgr_TCAM_row_data *this_table; struct cfa_tcam_mgr_TCAM_row_data *this_row; - this_table = row_tables[parms->dir] + + this_table = tcam_mgr_data->row_tables[parms->dir] [cfa_tcam_mgr_get_phys_table_type(parms->type)]; - this_table += (sess_idx * - cfa_tcam_mgr_get_max_rows(cfa_tcam_mgr_get_phys_table_type(parms->type))); this_row = &this_table[row * max_slices + slice]; parms->key_size = this_row->key_size; parms->result_size = this_row->result_size; - if (parms->key != ((void *)0)) + if (parms->key) memcpy(parms->key, &this_row->key, parms->key_size); - if (parms->mask != ((void *)0)) + if (parms->mask) memcpy(parms->mask, &this_row->mask, parms->key_size); - if (parms->result != ((void *)0)) + if (parms->result) memcpy(parms->result, &this_row->result, parms->result_size); return 0; }; -static int cfa_tcam_mgr_hwop_free(int sess_idx, +static int cfa_tcam_mgr_hwop_free(struct cfa_tcam_mgr_data *tcam_mgr_data, struct cfa_tcam_mgr_free_parms *parms, int row, int slice, int max_slices) { struct cfa_tcam_mgr_TCAM_row_data *this_table; struct cfa_tcam_mgr_TCAM_row_data *this_row; - this_table = row_tables[parms->dir] + + this_table = tcam_mgr_data->row_tables[parms->dir] [cfa_tcam_mgr_get_phys_table_type(parms->type)]; - this_table += (sess_idx * - cfa_tcam_mgr_get_max_rows(cfa_tcam_mgr_get_phys_table_type(parms->type))); this_row = &this_table[row * max_slices + slice]; memset(&this_row->key, 0, sizeof(this_row->key)); memset(&this_row->mask, 0, sizeof(this_row->mask)); diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.h index 3ca59b2aeb..acf3029578 100644 --- a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.h +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2021-2023 Broadcom + * Copyright(c) 2021-2024 Broadcom * All rights reserved. */ @@ -7,13 +7,12 @@ #define CFA_TCAM_MGR_P4_H #include "cfa_tcam_mgr_device.h" -#include "cfa_tcam_mgr_sbmp.h" int -cfa_tcam_mgr_init_p4(int sess_idx, struct cfa_tcam_mgr_entry_data **global_entry_data); +cfa_tcam_mgr_init_p4(struct tf *tfp); -int -cfa_tcam_mgr_sess_table_get_p4(int sess_idx, struct sbmp **session_bmp); +void +cfa_tcam_mgr_uninit_p4(struct tf *tfp); int cfa_tcam_mgr_hwops_get_funcs_p4(struct cfa_tcam_mgr_hwops_funcs *hwop_funcs); diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c index 656b10641e..aa322b4452 100644 --- a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2021-2023 Broadcom + * Copyright(c) 2021-2024 Broadcom * All rights reserved. */ @@ -12,6 +12,7 @@ #include "tfp.h" #include "assert.h" #include "tf_util.h" +#include "tf_session.h" /* * Sizings of the TCAMs on P5 @@ -126,38 +127,40 @@ * Array sizes have 1 added to avoid zero length arrays. */ -static struct cfa_tcam_mgr_table_rows_1 - cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[TF_TCAM_MAX_SESSIONS][L2_CTXT_TCAM_RX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_1 - cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[TF_TCAM_MAX_SESSIONS][L2_CTXT_TCAM_TX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_1 - cfa_tcam_mgr_table_rows_PROF_TCAM_RX[TF_TCAM_MAX_SESSIONS][PROF_TCAM_RX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_1 - cfa_tcam_mgr_table_rows_PROF_TCAM_TX[TF_TCAM_MAX_SESSIONS][PROF_TCAM_TX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_4 - cfa_tcam_mgr_table_rows_WC_TCAM_RX[TF_TCAM_MAX_SESSIONS][WC_TCAM_RX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_4 - cfa_tcam_mgr_table_rows_WC_TCAM_TX[TF_TCAM_MAX_SESSIONS][WC_TCAM_TX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_1 - cfa_tcam_mgr_table_rows_SP_TCAM_RX[TF_TCAM_MAX_SESSIONS][SP_TCAM_RX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_1 - cfa_tcam_mgr_table_rows_SP_TCAM_TX[TF_TCAM_MAX_SESSIONS][SP_TCAM_TX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_1 - cfa_tcam_mgr_table_rows_CT_RULE_TCAM_RX[TF_TCAM_MAX_SESSIONS][CT_RULE_TCAM_RX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_1 - cfa_tcam_mgr_table_rows_CT_RULE_TCAM_TX[TF_TCAM_MAX_SESSIONS][CT_RULE_TCAM_TX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_1 - cfa_tcam_mgr_table_rows_VEB_TCAM_RX[TF_TCAM_MAX_SESSIONS][VEB_TCAM_RX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_1 - cfa_tcam_mgr_table_rows_VEB_TCAM_TX[TF_TCAM_MAX_SESSIONS][VEB_TCAM_TX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_4 - cfa_tcam_mgr_table_rows_WC_TCAM_RX_HIGH[TF_TCAM_MAX_SESSIONS][WC_TCAM_RX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_4 - cfa_tcam_mgr_table_rows_WC_TCAM_RX_LOW[TF_TCAM_MAX_SESSIONS][WC_TCAM_RX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_4 - cfa_tcam_mgr_table_rows_WC_TCAM_TX_HIGH[TF_TCAM_MAX_SESSIONS][WC_TCAM_TX_NUM_ROWS + 1]; -static struct cfa_tcam_mgr_table_rows_4 - cfa_tcam_mgr_table_rows_WC_TCAM_TX_LOW[TF_TCAM_MAX_SESSIONS][WC_TCAM_TX_NUM_ROWS + 1]; +struct cfa_tcam_mgr_table_rows_p58 { + struct cfa_tcam_mgr_table_rows_1 + table_rows_L2_CTXT_TCAM_RX[L2_CTXT_TCAM_RX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_1 + table_rows_L2_CTXT_TCAM_TX[L2_CTXT_TCAM_TX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_1 + table_rows_PROF_TCAM_RX[PROF_TCAM_RX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_1 + table_rows_PROF_TCAM_TX[PROF_TCAM_TX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_4 + table_rows_WC_TCAM_RX[WC_TCAM_RX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_4 + table_rows_WC_TCAM_TX[WC_TCAM_TX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_1 + table_rows_SP_TCAM_RX[SP_TCAM_RX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_1 + table_rows_SP_TCAM_TX[SP_TCAM_TX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_1 + table_rows_CT_RULE_TCAM_RX[CT_RULE_TCAM_RX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_1 + table_rows_CT_RULE_TCAM_TX[CT_RULE_TCAM_TX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_1 + table_rows_VEB_TCAM_RX[VEB_TCAM_RX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_1 + table_rows_VEB_TCAM_TX[VEB_TCAM_TX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_4 + table_rows_WC_TCAM_RX_HIGH[WC_TCAM_RX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_4 + table_rows_WC_TCAM_RX_LOW[WC_TCAM_RX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_4 + table_rows_WC_TCAM_TX_HIGH[WC_TCAM_TX_NUM_ROWS + 1]; + struct cfa_tcam_mgr_table_rows_4 + table_rows_WC_TCAM_TX_LOW[WC_TCAM_TX_NUM_ROWS + 1]; +}; struct cfa_tcam_mgr_table_data cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { @@ -177,7 +180,7 @@ cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH, .num_rows = L2_CTXT_TCAM_RX_NUM_ROWS, .start_row = 0, - .end_row = (L2_CTXT_TCAM_RX_NUM_ROWS / 2) - 1, + .end_row = L2_CTXT_TCAM_RX_APP_HI_END, .max_entries = (L2_CTXT_TCAM_RX_MAX_ENTRIES / 2), .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE, .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH, @@ -196,7 +199,7 @@ cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES, .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH, .num_rows = L2_CTXT_TCAM_RX_NUM_ROWS, - .start_row = (L2_CTXT_TCAM_RX_NUM_ROWS / 2), + .start_row = L2_CTXT_TCAM_RX_APP_LO_START, .end_row = L2_CTXT_TCAM_RX_NUM_ROWS - 1, .max_entries = (L2_CTXT_TCAM_RX_MAX_ENTRIES / 2), .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE, @@ -275,7 +278,8 @@ cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .num_rows = CT_RULE_TCAM_RX_NUM_ROWS, .start_row = 0, #if CT_RULE_TCAM_RX_NUM_ROWS > 0 - .end_row = CT_RULE_TCAM_RX_NUM_ROWS - 1, + .end_row = + TCAM_SET_END_ROW(CT_RULE_TCAM_RX_NUM_ROWS), #else .end_row = CT_RULE_TCAM_RX_NUM_ROWS, #endif @@ -298,7 +302,7 @@ cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .num_rows = VEB_TCAM_RX_NUM_ROWS, .start_row = 0, #if VEB_TCAM_RX_NUM_ROWS > 0 - .end_row = VEB_TCAM_RX_NUM_ROWS - 1, + .end_row = TCAM_SET_END_ROW(VEB_TCAM_RX_NUM_ROWS), #else .end_row = VEB_TCAM_RX_NUM_ROWS, #endif @@ -363,7 +367,7 @@ cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH, .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS, .start_row = 0, - .end_row = (L2_CTXT_TCAM_TX_NUM_ROWS / 2) - 1, + .end_row = L2_CTXT_TCAM_TX_APP_HI_END, .max_entries = (L2_CTXT_TCAM_TX_MAX_ENTRIES / 2), .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE, .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH, @@ -382,7 +386,7 @@ cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES, .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH, .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS, - .start_row = (L2_CTXT_TCAM_TX_NUM_ROWS / 2), + .start_row = L2_CTXT_TCAM_TX_APP_LO_START, .end_row = L2_CTXT_TCAM_TX_NUM_ROWS - 1, .max_entries = (L2_CTXT_TCAM_TX_MAX_ENTRIES / 2), .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE, @@ -461,7 +465,8 @@ cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .num_rows = CT_RULE_TCAM_TX_NUM_ROWS, .start_row = 0, #if CT_RULE_TCAM_TX_NUM_ROWS > 0 - .end_row = CT_RULE_TCAM_TX_NUM_ROWS - 1, + .end_row = + TCAM_SET_END_ROW(CT_RULE_TCAM_TX_NUM_ROWS), #else .end_row = CT_RULE_TCAM_TX_NUM_ROWS, #endif @@ -531,222 +536,305 @@ cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { }, }; -static struct cfa_tcam_mgr_entry_data entry_data_p58[TF_TCAM_MAX_SESSIONS][TF_TCAM_MAX_ENTRIES]; - -static struct sbmp session_bmp_p58[TF_TCAM_MAX_SESSIONS][TF_TCAM_MAX_ENTRIES]; +static int cfa_tcam_mgr_row_data_alloc(struct cfa_tcam_mgr_data *tcam_mgr_data); +static void cfa_tcam_mgr_row_data_free(struct cfa_tcam_mgr_data *tcam_mgr_data); -int -cfa_tcam_mgr_sess_table_get_p58(int sess_idx, struct sbmp **session_bmp) +static void cfa_tcam_mgr_data_free(struct tf_session *tfs) { - *session_bmp = session_bmp_p58[sess_idx]; - return 0; + struct cfa_tcam_mgr_data *tcam_mgr_data = tfs->tcam_mgr_handle; + + if (!tcam_mgr_data) + return; + + tfp_free(tcam_mgr_data->table_rows); + tfp_free(tcam_mgr_data->entry_data); + tfp_free(tcam_mgr_data->session_bmp); + cfa_tcam_mgr_row_data_free(tcam_mgr_data); + + tfp_free(tcam_mgr_data); + tfs->tcam_mgr_handle = NULL; } int -cfa_tcam_mgr_init_p58(int sess_idx, struct cfa_tcam_mgr_entry_data **global_entry_data) +cfa_tcam_mgr_init_p58(struct tf *tfp) { - int max_row_width = 0; + struct cfa_tcam_mgr_table_rows_p58 *table_rows; + struct cfa_tcam_mgr_data *tcam_mgr_data; + struct tfp_calloc_parms cparms; int max_result_size = 0; + struct tf_session *tfs; + int max_row_width = 0; int dir, type; + int rc; + + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + cparms.nitems = 1; + cparms.size = sizeof(struct cfa_tcam_mgr_data); + cparms.alignment = 0; + rc = tfp_calloc(&cparms); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "Failed to allocate block, rc:%s\n", + strerror(-rc)); + return rc; + } + tcam_mgr_data = (struct cfa_tcam_mgr_data *)cparms.mem_va; + tfs->tcam_mgr_handle = tcam_mgr_data; + + cparms.nitems = 1; + cparms.size = sizeof(struct cfa_tcam_mgr_table_rows_p58); + cparms.alignment = 0; + rc = tfp_calloc(&cparms); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "Failed to allocate block, rc:%s\n", + strerror(-rc)); + tfp_free(tfs->tcam_mgr_handle); + tfs->tcam_mgr_handle = NULL; + return rc; + } + table_rows = (struct cfa_tcam_mgr_table_rows_p58 *)cparms.mem_va; + tcam_mgr_data->table_rows = table_rows; - *global_entry_data = entry_data_p58[sess_idx]; + cparms.nitems = TF_TCAM_MAX_ENTRIES; + cparms.size = sizeof(struct cfa_tcam_mgr_entry_data); + cparms.alignment = 0; + rc = tfp_calloc(&cparms); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "Failed to allocate block, rc:%s\n", + strerror(-rc)); + goto fail; + } + tcam_mgr_data->entry_data = + (struct cfa_tcam_mgr_entry_data *)cparms.mem_va; + + rc = cfa_tcam_mgr_row_data_alloc(tcam_mgr_data); + if (rc) + goto fail; - memcpy(&cfa_tcam_mgr_tables[sess_idx], + memcpy(tcam_mgr_data->cfa_tcam_mgr_tables, &cfa_tcam_mgr_tables_p58, - sizeof(cfa_tcam_mgr_tables[sess_idx])); + sizeof(tcam_mgr_data->cfa_tcam_mgr_tables)); - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + &table_rows->table_rows_L2_CTXT_TCAM_RX[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx]; + &table_rows->table_rows_L2_CTXT_TCAM_RX[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + &table_rows->table_rows_L2_CTXT_TCAM_TX[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx]; + &table_rows->table_rows_L2_CTXT_TCAM_TX[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + &table_rows->table_rows_L2_CTXT_TCAM_RX[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx]; + &table_rows->table_rows_L2_CTXT_TCAM_RX[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + &table_rows->table_rows_L2_CTXT_TCAM_TX[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx]; + &table_rows->table_rows_L2_CTXT_TCAM_TX[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_PROF_TCAM_RX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + &table_rows->table_rows_PROF_TCAM_RX[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_PROF_TCAM_RX[sess_idx]; + &table_rows->table_rows_PROF_TCAM_RX[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_PROF_TCAM_TX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + &table_rows->table_rows_PROF_TCAM_TX[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_PROF_TCAM_TX[sess_idx]; + &table_rows->table_rows_PROF_TCAM_TX[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_WC_TCAM_RX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + &table_rows->table_rows_WC_TCAM_RX[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_WC_TCAM_RX[sess_idx]; + &table_rows->table_rows_WC_TCAM_RX[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_WC_TCAM_TX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + &table_rows->table_rows_WC_TCAM_TX[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_WC_TCAM_TX[sess_idx]; + &table_rows->table_rows_WC_TCAM_TX[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_SP_TCAM_RX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + &table_rows->table_rows_SP_TCAM_RX[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_SP_TCAM_RX[sess_idx]; + &table_rows->table_rows_SP_TCAM_RX[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_SP_TCAM_TX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + &table_rows->table_rows_SP_TCAM_TX[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_SP_TCAM_TX[sess_idx]; + &table_rows->table_rows_SP_TCAM_TX[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_RX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + &table_rows->table_rows_CT_RULE_TCAM_RX[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_RX[sess_idx]; + &table_rows->table_rows_CT_RULE_TCAM_RX[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_TX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + &table_rows->table_rows_CT_RULE_TCAM_TX[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_TX[sess_idx]; + &table_rows->table_rows_CT_RULE_TCAM_TX[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_VEB_TCAM_RX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + &table_rows->table_rows_VEB_TCAM_RX[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_VEB_TCAM_RX[sess_idx]; + &table_rows->table_rows_VEB_TCAM_RX[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_VEB_TCAM_TX[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + &table_rows->table_rows_VEB_TCAM_TX[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_VEB_TCAM_TX[sess_idx]; + &table_rows->table_rows_VEB_TCAM_TX[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_WC_TCAM_RX_HIGH[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + &table_rows->table_rows_WC_TCAM_RX_HIGH[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_WC_TCAM_RX_HIGH[sess_idx]; + &table_rows->table_rows_WC_TCAM_RX_HIGH[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_WC_TCAM_TX_HIGH[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + &table_rows->table_rows_WC_TCAM_TX_HIGH[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_WC_TCAM_TX_HIGH[sess_idx]; + &table_rows->table_rows_WC_TCAM_TX_HIGH[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_WC_TCAM_RX_LOW[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + &table_rows->table_rows_WC_TCAM_RX_LOW[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_WC_TCAM_RX_LOW[sess_idx]; + &table_rows->table_rows_WC_TCAM_RX_LOW[0]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_AFM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_WC_TCAM_TX_LOW[sess_idx]; - cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + &table_rows->table_rows_WC_TCAM_TX_LOW[0]; + tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) - &cfa_tcam_mgr_table_rows_WC_TCAM_TX_LOW[sess_idx]; + &table_rows->table_rows_WC_TCAM_TX_LOW[0]; + for (dir = 0; dir < TF_DIR_MAX; dir++) { for (type = 0; type < CFA_TCAM_MGR_TBL_TYPE_MAX; type++) { - if (cfa_tcam_mgr_tables[sess_idx][dir][type].row_width > + if (tcam_mgr_data->cfa_tcam_mgr_tables[dir] + [type].row_width > max_row_width) max_row_width = - cfa_tcam_mgr_tables[sess_idx][dir][type].row_width; - if (cfa_tcam_mgr_tables[sess_idx][dir][type].result_size > + tcam_mgr_data->cfa_tcam_mgr_tables[dir] + [type].row_width; + if (tcam_mgr_data->cfa_tcam_mgr_tables[dir] + [type].result_size > max_result_size) max_result_size = - cfa_tcam_mgr_tables[sess_idx][dir][type].result_size; + tcam_mgr_data->cfa_tcam_mgr_tables[dir] + [type].result_size; } } if (max_row_width != MAX_ROW_WIDTH) { - CFA_TCAM_MGR_LOG(ERR, - "MAX_ROW_WIDTH (%d) does not match actual " - "value (%d).\n", - MAX_ROW_WIDTH, - max_row_width); - return -CFA_TCAM_MGR_ERR_CODE(INVAL); + TFP_DRV_LOG(ERR, + "MAX_ROW_WIDTH:%d does not match actual val:%d\n", + MAX_ROW_WIDTH, max_row_width); + rc = -EINVAL; + goto fail; } if (max_result_size != MAX_RESULT_SIZE) { - CFA_TCAM_MGR_LOG(ERR, - "MAX_RESULT_SIZE (%d) does not match actual " - "value (%d).\n", - MAX_RESULT_SIZE, - max_result_size); - return -CFA_TCAM_MGR_ERR_CODE(INVAL); + TFP_DRV_LOG(ERR, + "MAX_RESULT_SIZE:%d does not match actual val:%d\n", + MAX_RESULT_SIZE, max_result_size); + rc = -EINVAL; + goto fail; } + return 0; + +fail: + cfa_tcam_mgr_data_free(tfs); + return rc; +} + +void cfa_tcam_mgr_uninit_p58(struct tf *tfp) +{ + struct tf_session *tfs; + int rc; + + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return; + + cfa_tcam_mgr_data_free(tfs); } /* HW OP declarations begin here */ @@ -778,134 +866,182 @@ struct cfa_tcam_mgr_TCAM_row_data { (CT_RULE_TCAM_TX_MAX_SLICES * CT_RULE_TCAM_TX_NUM_ROWS) #define VEB_TX_MAX_ROWS (VEB_TCAM_TX_MAX_SLICES * VEB_TCAM_TX_NUM_ROWS) -static int cfa_tcam_mgr_max_rows[TF_TCAM_TBL_TYPE_MAX] = { - L2_CTXT_RX_MAX_ROWS, - L2_CTXT_RX_MAX_ROWS, - PROF_RX_MAX_ROWS, - WC_RX_MAX_ROWS, - SP_RX_MAX_ROWS, - CT_RULE_RX_MAX_ROWS, - VEB_RX_MAX_ROWS, - WC_RX_MAX_ROWS, - WC_RX_MAX_ROWS +struct cfa_tcam_mgr_rx_row_data { + struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[L2_CTXT_RX_MAX_ROWS + 1]; + struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_PROF_TCAM_RX_row_data[PROF_RX_MAX_ROWS + 1]; + struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_WC_TCAM_RX_row_data[WC_TX_MAX_ROWS + 1]; + struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_SP_TCAM_RX_row_data[SP_RX_MAX_ROWS + 1]; + struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_CT_RULE_TCAM_RX_row_data[CT_RULE_RX_MAX_ROWS + 1]; + struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_VEB_TCAM_RX_row_data[VEB_RX_MAX_ROWS + 1]; }; -static struct cfa_tcam_mgr_TCAM_row_data - cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][L2_CTXT_RX_MAX_ROWS]; -static struct cfa_tcam_mgr_TCAM_row_data - cfa_tcam_mgr_PROF_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][PROF_RX_MAX_ROWS]; -static struct cfa_tcam_mgr_TCAM_row_data - cfa_tcam_mgr_WC_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][WC_RX_MAX_ROWS]; -static struct cfa_tcam_mgr_TCAM_row_data - cfa_tcam_mgr_SP_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][SP_RX_MAX_ROWS]; -static struct cfa_tcam_mgr_TCAM_row_data - cfa_tcam_mgr_CT_RULE_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][CT_RULE_RX_MAX_ROWS]; -static struct cfa_tcam_mgr_TCAM_row_data - cfa_tcam_mgr_VEB_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][VEB_RX_MAX_ROWS]; -static struct cfa_tcam_mgr_TCAM_row_data - cfa_tcam_mgr_WC_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][WC_RX_MAX_ROWS]; - -static struct cfa_tcam_mgr_TCAM_row_data - cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][L2_CTXT_TX_MAX_ROWS]; -static struct cfa_tcam_mgr_TCAM_row_data - cfa_tcam_mgr_PROF_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][PROF_TX_MAX_ROWS]; -static struct cfa_tcam_mgr_TCAM_row_data - cfa_tcam_mgr_WC_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][WC_TX_MAX_ROWS]; -static struct cfa_tcam_mgr_TCAM_row_data - cfa_tcam_mgr_SP_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][SP_TX_MAX_ROWS]; -static struct cfa_tcam_mgr_TCAM_row_data - cfa_tcam_mgr_CT_RULE_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][CT_RULE_TX_MAX_ROWS]; -static struct cfa_tcam_mgr_TCAM_row_data - cfa_tcam_mgr_VEB_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][VEB_TX_MAX_ROWS]; -static struct cfa_tcam_mgr_TCAM_row_data - cfa_tcam_mgr_WC_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][WC_TX_MAX_ROWS]; - -static struct cfa_tcam_mgr_TCAM_row_data * -row_tables[TF_DIR_MAX][TF_TCAM_TBL_TYPE_MAX] = { - { - cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[0], - cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[0], - cfa_tcam_mgr_PROF_TCAM_RX_row_data[0], - cfa_tcam_mgr_WC_TCAM_RX_row_data[0], - cfa_tcam_mgr_SP_TCAM_RX_row_data[0], - cfa_tcam_mgr_CT_RULE_TCAM_RX_row_data[0], - cfa_tcam_mgr_VEB_TCAM_RX_row_data[0], - cfa_tcam_mgr_WC_TCAM_RX_row_data[0], - cfa_tcam_mgr_WC_TCAM_RX_row_data[0], - }, - { - cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[0], - cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[0], - cfa_tcam_mgr_PROF_TCAM_TX_row_data[0], - cfa_tcam_mgr_WC_TCAM_TX_row_data[0], - cfa_tcam_mgr_SP_TCAM_TX_row_data[0], - cfa_tcam_mgr_CT_RULE_TCAM_TX_row_data[0], - cfa_tcam_mgr_VEB_TCAM_TX_row_data[0], - cfa_tcam_mgr_WC_TCAM_TX_row_data[0], - cfa_tcam_mgr_WC_TCAM_TX_row_data[0], - } +struct cfa_tcam_mgr_tx_row_data { + struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[L2_CTXT_TX_MAX_ROWS + 1]; + struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_PROF_TCAM_TX_row_data[PROF_TX_MAX_ROWS + 1]; + struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_WC_TCAM_TX_row_data[WC_TX_MAX_ROWS + 1]; + struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_SP_TCAM_TX_row_data[SP_TX_MAX_ROWS + 1]; + struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_CT_RULE_TCAM_TX_row_data[CT_RULE_TX_MAX_ROWS + 1]; + struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_VEB_TCAM_TX_row_data[VEB_TX_MAX_ROWS + 1]; }; -static int cfa_tcam_mgr_get_max_rows(enum tf_tcam_tbl_type type) +#define TF_TCAM_L2_CTX_HI TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH +#define TF_TCAM_L2_CTX_LO TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW +#define TF_TCAM_PROF TF_TCAM_TBL_TYPE_PROF_TCAM +#define TF_TCAM_WC TF_TCAM_TBL_TYPE_WC_TCAM +#define TF_TCAM_SP TF_TCAM_TBL_TYPE_SP_TCAM +#define TF_TCAM_CT TF_TCAM_TBL_TYPE_CT_RULE_TCAM +#define TF_TCAM_VEB TF_TCAM_TBL_TYPE_VEB_TCAM +#define TF_TCAM_WC_HI TF_TCAM_TBL_TYPE_WC_TCAM_HIGH +#define TF_TCAM_WC_LO TF_TCAM_TBL_TYPE_WC_TCAM_LOW + +static int cfa_tcam_mgr_row_data_alloc(struct cfa_tcam_mgr_data *tcam_mgr_data) +{ + struct cfa_tcam_mgr_rx_row_data *rx_row_data; + struct cfa_tcam_mgr_tx_row_data *tx_row_data; + struct tfp_calloc_parms cparms; + int rc; + + cparms.nitems = 1; + cparms.size = sizeof(struct cfa_tcam_mgr_rx_row_data); + cparms.alignment = 0; + rc = tfp_calloc(&cparms); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "Failed to allocate rx_row_data, rc:%s\n", + strerror(-rc)); + return -ENOMEM; + } + + rx_row_data = (struct cfa_tcam_mgr_rx_row_data *)cparms.mem_va; + + cparms.nitems = 1; + cparms.size = sizeof(struct cfa_tcam_mgr_tx_row_data); + cparms.alignment = 0; + rc = tfp_calloc(&cparms); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "Failed to allocate tx_row_data, rc:%s\n", + strerror(-rc)); + tfp_free(rx_row_data); + return -ENOMEM; + } + + tx_row_data = (struct cfa_tcam_mgr_tx_row_data *)cparms.mem_va; + + tcam_mgr_data->rx_row_data = rx_row_data; + tcam_mgr_data->tx_row_data = tx_row_data; + + tcam_mgr_data->row_tables[TF_DIR_RX][TF_TCAM_L2_CTX_HI] = + &rx_row_data->cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_RX][TF_TCAM_L2_CTX_LO] = + &rx_row_data->cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_RX][TF_TCAM_PROF] = + &rx_row_data->cfa_tcam_mgr_PROF_TCAM_RX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_RX][TF_TCAM_WC] = + &rx_row_data->cfa_tcam_mgr_WC_TCAM_RX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_RX][TF_TCAM_SP] = + &rx_row_data->cfa_tcam_mgr_SP_TCAM_RX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_RX][TF_TCAM_CT] = + &rx_row_data->cfa_tcam_mgr_CT_RULE_TCAM_RX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_RX][TF_TCAM_VEB] = + &rx_row_data->cfa_tcam_mgr_VEB_TCAM_RX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_RX][TF_TCAM_WC_HI] = + &rx_row_data->cfa_tcam_mgr_WC_TCAM_RX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_RX][TF_TCAM_WC_LO] = + &rx_row_data->cfa_tcam_mgr_WC_TCAM_RX_row_data[0]; + + tcam_mgr_data->row_tables[TF_DIR_TX][TF_TCAM_L2_CTX_HI] = + &tx_row_data->cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_TX][TF_TCAM_L2_CTX_LO] = + &tx_row_data->cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_TX][TF_TCAM_PROF] = + &tx_row_data->cfa_tcam_mgr_PROF_TCAM_TX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_TX][TF_TCAM_WC] = + &tx_row_data->cfa_tcam_mgr_WC_TCAM_TX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_TX][TF_TCAM_SP] = + &tx_row_data->cfa_tcam_mgr_SP_TCAM_TX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_TX][TF_TCAM_CT] = + &tx_row_data->cfa_tcam_mgr_CT_RULE_TCAM_TX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_TX][TF_TCAM_VEB] = + &tx_row_data->cfa_tcam_mgr_VEB_TCAM_TX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_TX][TF_TCAM_WC_HI] = + &tx_row_data->cfa_tcam_mgr_WC_TCAM_TX_row_data[0]; + tcam_mgr_data->row_tables[TF_DIR_TX][TF_TCAM_WC_LO] = + &tx_row_data->cfa_tcam_mgr_WC_TCAM_TX_row_data[0]; + + return 0; +} + +static void cfa_tcam_mgr_row_data_free(struct cfa_tcam_mgr_data + *tcam_mgr_data) { - if (type >= TF_TCAM_TBL_TYPE_MAX) - assert(0); - else - return cfa_tcam_mgr_max_rows[type]; + tfp_free(tcam_mgr_data->rx_row_data); + tfp_free(tcam_mgr_data->tx_row_data); } -static int cfa_tcam_mgr_hwop_set(int sess_idx, +static int cfa_tcam_mgr_hwop_set(struct cfa_tcam_mgr_data *tcam_mgr_data, struct cfa_tcam_mgr_set_parms *parms, int row, int slice, int max_slices) { struct cfa_tcam_mgr_TCAM_row_data *this_table; struct cfa_tcam_mgr_TCAM_row_data *this_row; - this_table = row_tables[parms->dir] + + this_table = tcam_mgr_data->row_tables[parms->dir] [cfa_tcam_mgr_get_phys_table_type(parms->type)]; - this_table += (sess_idx * - cfa_tcam_mgr_get_max_rows(cfa_tcam_mgr_get_phys_table_type(parms->type))); this_row = &this_table[row * max_slices + slice]; this_row->key_size = parms->key_size; memcpy(&this_row->key, parms->key, parms->key_size); memcpy(&this_row->mask, parms->mask, parms->key_size); this_row->result_size = parms->result_size; - if (parms->result != ((void *)0)) + if (parms->result) memcpy(&this_row->result, parms->result, parms->result_size); return 0; }; -static int cfa_tcam_mgr_hwop_get(int sess_idx, +static int cfa_tcam_mgr_hwop_get(struct cfa_tcam_mgr_data *tcam_mgr_data, struct cfa_tcam_mgr_get_parms *parms, int row, int slice, int max_slices) { struct cfa_tcam_mgr_TCAM_row_data *this_table; struct cfa_tcam_mgr_TCAM_row_data *this_row; - this_table = row_tables[parms->dir] + + this_table = tcam_mgr_data->row_tables[parms->dir] [cfa_tcam_mgr_get_phys_table_type(parms->type)]; - this_table += (sess_idx * - cfa_tcam_mgr_get_max_rows(cfa_tcam_mgr_get_phys_table_type(parms->type))); this_row = &this_table[row * max_slices + slice]; parms->key_size = this_row->key_size; parms->result_size = this_row->result_size; - if (parms->key != ((void *)0)) + if (parms->key) memcpy(parms->key, &this_row->key, parms->key_size); - if (parms->mask != ((void *)0)) + if (parms->mask) memcpy(parms->mask, &this_row->mask, parms->key_size); - if (parms->result != ((void *)0)) + if (parms->result) memcpy(parms->result, &this_row->result, parms->result_size); return 0; }; -static int cfa_tcam_mgr_hwop_free(int sess_idx, +static int cfa_tcam_mgr_hwop_free(struct cfa_tcam_mgr_data *tcam_mgr_data, struct cfa_tcam_mgr_free_parms *parms, int row, int slice, int max_slices) { struct cfa_tcam_mgr_TCAM_row_data *this_table; struct cfa_tcam_mgr_TCAM_row_data *this_row; - this_table = row_tables[parms->dir] + + this_table = tcam_mgr_data->row_tables[parms->dir] [cfa_tcam_mgr_get_phys_table_type(parms->type)]; - this_table += (sess_idx * - cfa_tcam_mgr_get_max_rows(cfa_tcam_mgr_get_phys_table_type(parms->type))); this_row = &this_table[row * max_slices + slice]; memset(&this_row->key, 0, sizeof(this_row->key)); memset(&this_row->mask, 0, sizeof(this_row->mask)); diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.h index 7640f91911..0fa5e06898 100644 --- a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.h +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2021-2023 Broadcom + * Copyright(c) 2021-2024 Broadcom * All rights reserved. */ @@ -7,14 +7,14 @@ #define CFA_TCAM_MGR_P58_H #include "cfa_tcam_mgr_device.h" -#include "cfa_tcam_mgr_sbmp.h" int -cfa_tcam_mgr_init_p58(int sess_idx, struct cfa_tcam_mgr_entry_data **global_entry_data); +cfa_tcam_mgr_init_p58(struct tf *tfp); -int -cfa_tcam_mgr_sess_table_get_p58(int sess_idx, struct sbmp **session_bmp); +void +cfa_tcam_mgr_uninit_p58(struct tf *tfp); int cfa_tcam_mgr_hwops_get_funcs_p58(struct cfa_tcam_mgr_hwops_funcs *hwop_funcs); + #endif /* CFA_TCAM_MGR_P58_H */ diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.h deleted file mode 100644 index 7e75776686..0000000000 --- a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2023 Broadcom - * All rights reserved. - */ - -#ifndef CFA_TCAM_MGR_SESSION_H -#define CFA_TCAM_MGR_SESSION_H - -#include -#include "cfa_tcam_mgr.h" - -int -cfa_tcam_mgr_session_init(int sess_idx, enum cfa_tcam_mgr_device_type type); - -int -cfa_tcam_mgr_get_session_from_context(struct cfa_tcam_mgr_context *context, - uint32_t *session_id); - -int -cfa_tcam_mgr_session_find(unsigned int session_id); - -int -cfa_tcam_mgr_session_empty(void); - -int -cfa_tcam_mgr_session_add(unsigned int session_id); - -int -cfa_tcam_mgr_session_free(unsigned int session_id, - struct cfa_tcam_mgr_context *context); - -int -cfa_tcam_mgr_session_cfg(unsigned int session_id, - uint16_t tcam_cnt[][CFA_TCAM_MGR_TBL_TYPE_MAX]); - -int -cfa_tcam_mgr_session_entry_alloc(unsigned int session_id, - enum tf_dir dir, - enum cfa_tcam_mgr_tbl_type type); -int -cfa_tcam_mgr_session_entry_free(unsigned int session_id, - unsigned int entry_id, - enum tf_dir dir, - enum cfa_tcam_mgr_tbl_type type); - -void -cfa_tcam_mgr_sessions_dump(void); -void -cfa_tcam_mgr_entry_sessions_dump(int sess_idx, uint16_t id); -void -cfa_tcam_mgr_session_entries_dump(int sess_idx); - -void -cfa_tcam_mgr_mv_session_used_entries_cnt(int sess_idx, enum tf_dir dir, - enum cfa_tcam_mgr_tbl_type dst_type, - enum cfa_tcam_mgr_tbl_type src_type); -#endif /* CFA_TCAM_MGR_SESSION_H */ diff --git a/drivers/net/bnxt/tf_core/meson.build b/drivers/net/bnxt/tf_core/meson.build index 7d38ab8793..803a89cbb5 100644 --- a/drivers/net/bnxt/tf_core/meson.build +++ b/drivers/net/bnxt/tf_core/meson.build @@ -1,6 +1,6 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2018 Intel Corporation -# Copyright(c) 2023 Broadcom +# Copyright(c) 2024 Broadcom #Include the folder for headers includes += include_directories('.') @@ -12,7 +12,6 @@ sources += files( 'cfa_tcam_mgr_hwop_msg.c', 'cfa_tcam_mgr_p4.c', 'cfa_tcam_mgr_p58.c', - 'cfa_tcam_mgr_session.c', 'dpool.c', 'll.c', 'rand.c', diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index 1c728aadd8..f1b3be48aa 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2023 Broadcom + * Copyright(c) 2019-2024 Broadcom * All rights reserved. */ @@ -1104,7 +1104,7 @@ tf_alloc_tbl_entry(struct tf *tfp, #ifdef TF_FLOW_SCALE_QUERY /* Update resource usage buffer */ if (!rc && dev->ops->tf_dev_update_tbl_usage_buffer) { - rc = dev->ops->tf_dev_update_tbl_usage_buffer(tfs->session_id.id, + rc = dev->ops->tf_dev_update_tbl_usage_buffer(tfp, parms->dir, parms->type, TF_RESC_ALLOC); @@ -1200,7 +1200,7 @@ tf_free_tbl_entry(struct tf *tfp, #ifdef TF_FLOW_SCALE_QUERY /* Update resource usage buffer */ if (!rc && dev->ops->tf_dev_update_tbl_usage_buffer) { - rc = dev->ops->tf_dev_update_tbl_usage_buffer(tfs->session_id.id, + rc = dev->ops->tf_dev_update_tbl_usage_buffer(tfp, parms->dir, parms->type, TF_RESC_FREE); diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index 0b0ca8b42f..e58c53000e 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2023 Broadcom + * Copyright(c) 2019-2024 Broadcom * All rights reserved. */ @@ -1187,7 +1187,7 @@ struct tf_dev_ops { * 0 - Success * -EINVAL - Error */ - int (*tf_dev_update_tbl_usage_buffer)(uint32_t session_id, + int (*tf_dev_update_tbl_usage_buffer)(struct tf *tfp, enum tf_dir dir, enum tf_tbl_type tbl_type, uint32_t resc_opt); diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 8f915744a7..fb4123eb80 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2023 Broadcom + * Copyright(c) 2019-2024 Broadcom * All rights reserved. */ @@ -865,13 +865,13 @@ static int tf_dev_p58_query_resc_usage(struct tf *tfp, * -EINVAL - Error */ static int -tf_dev_p58_update_tbl_usage_buffer(uint32_t session_id, +tf_dev_p58_update_tbl_usage_buffer(struct tf *tfp, enum tf_dir dir, enum tf_tbl_type tbl_type, enum tf_resc_opt resc_opt) { int rc; - rc = tf_tbl_usage_update(session_id, dir, tbl_type, resc_opt); + rc = tf_tbl_usage_update(tfp, dir, tbl_type, resc_opt); return rc; } #endif /* TF_FLOW_SCALE_QUERY */ diff --git a/drivers/net/bnxt/tf_core/tf_em_hash_internal.c b/drivers/net/bnxt/tf_core/tf_em_hash_internal.c index 35589c9844..7c38fa6076 100644 --- a/drivers/net/bnxt/tf_core/tf_em_hash_internal.c +++ b/drivers/net/bnxt/tf_core/tf_em_hash_internal.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2023 Broadcom + * Copyright(c) 2019-2024 Broadcom * All rights reserved. */ @@ -111,7 +111,7 @@ tf_em_hash_insert_int_entry(struct tf *tfp, #ifdef TF_FLOW_SCALE_QUERY /* Update usage state buffer for EM */ - tf_em_usage_update(tfs->session_id.id, + tf_em_usage_update(tfp, parms->dir, num_of_entries, TF_RESC_ALLOC); @@ -155,7 +155,7 @@ tf_em_hash_delete_int_entry(struct tf *tfp, #ifdef TF_FLOW_SCALE_QUERY /* Update usage state buffer for EM */ size = DP_FLAGS_SIZE(pool->entry[parms->index - pool->start_index].flags); - tf_em_usage_update(tfs->session_id.id, + tf_em_usage_update(tfp, parms->dir, size, TF_RESC_FREE); diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c index 6dfefce2f2..f620002cc0 100644 --- a/drivers/net/bnxt/tf_core/tf_em_internal.c +++ b/drivers/net/bnxt/tf_core/tf_em_internal.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2023 Broadcom + * Copyright(c) 2019-2024 Broadcom * All rights reserved. */ @@ -296,7 +296,7 @@ tf_em_int_bind(struct tf *tfp, #ifdef TF_FLOW_SCALE_QUERY /* Initialize the usage state buffer for EM */ - tf_em_usage_init(tfs->session_id.id, + tf_em_usage_init(tfp, i, iparms.info->entry.stride); #endif /* TF_FLOW_SCALE_QUERY */ diff --git a/drivers/net/bnxt/tf_core/tf_resources.c b/drivers/net/bnxt/tf_core/tf_resources.c index 4c64d23b86..d4fd3c2333 100644 --- a/drivers/net/bnxt/tf_core/tf_resources.c +++ b/drivers/net/bnxt/tf_core/tf_resources.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2023 Broadcom + * Copyright(c) 2019-2024 Broadcom * All rights reserved. */ @@ -16,7 +16,6 @@ #include "tf_session.h" #include "tf_device.h" #include "cfa_tcam_mgr_device.h" -#include "cfa_tcam_mgr_session.h" #ifdef TF_FLOW_SCALE_QUERY @@ -35,41 +34,32 @@ struct tf_resc_usage_buffer_control { static struct tf_resc_usage_buffer_control resc_usage_control; /* Check if supporting resource usage */ -static bool tf_resc_usage_support(int session_id) +static bool tf_resc_usage_support(struct tf *tfp) { + struct tf_session *tfs; bool support = true; - int sess_idx; + int rc; /* Not valid session id */ - if (!session_id) + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) return false; - /* Support Generic template with one session */ - sess_idx = cfa_tcam_mgr_session_find(session_id); - if (sess_idx < 0 && !cfa_tcam_mgr_session_empty()) - support = false; - /* Support Thor */ - if (resc_usage_control.device_type != TF_DEVICE_TYPE_P5) + if (resc_usage_control.device_type != tfs->dev.type) support = false; #if (TF_FLOW_SCALE_QUERY_DEBUG == 1) - TFP_DRV_LOG(INFO, "Resc usage update sess_id: %x, idx: %d, type: %d, allow: %s\n", - session_id, - sess_idx, - resc_usage_control.device_type, - support ? "True" : "False"); + TFP_DRV_LOG(INFO, "Resc usage update on device type: %d, allow: %s\n", + resc_usage_control.device_type, + support ? "True" : "False"); #endif /* TF_FLOW_SCALE_QUERY_DEBUG == 1 */ return support; } /* Reset the resource usage buffer */ -void tf_resc_usage_reset(enum tf_device_type type, int session_id) +void tf_resc_usage_reset(struct tf *tfp __rte_unused, enum tf_device_type type) { - /* Check if supported on this device */ - if (cfa_tcam_mgr_session_find(session_id) > 0) - return; - /* Support Thor only*/ if (type != TF_DEVICE_TYPE_P5) return; @@ -96,24 +86,35 @@ tf_tcam_mgr_row_entry_used(struct cfa_tcam_mgr_table_rows_0 *row, } /* Initialize the resource usage buffer for WC-TCAM tables */ -void tf_tcam_usage_init(int session_id) +void tf_tcam_usage_init(struct tf *tfp) { - enum tf_dir dir; enum cfa_tcam_mgr_tbl_type type = CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS; struct cfa_tcam_mgr_table_data *table_data = NULL; struct tf_resc_wc_tcam_usage *usage_data = NULL; - int sess_idx = cfa_tcam_mgr_session_find(session_id); + struct cfa_tcam_mgr_data *tcam_mgr_data; + struct tf_session *tfs; + enum tf_dir dir; + int rc; /* Check if supported on this device */ - if (!tf_resc_usage_support(session_id)) + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) return; + tcam_mgr_data = tfs->tcam_mgr_handle; + if (!tcam_mgr_data) { + TFP_DRV_LOG(ERR, + "%s: No TCAM data created for session\n", + __func__); + return; + } + /* Iterate over all directions */ for (dir = 0; dir < TF_DIR_MAX; dir++) { - table_data = &cfa_tcam_mgr_tables[sess_idx][dir][type]; + table_data = &tcam_mgr_data->cfa_tcam_mgr_tables[dir][type]; usage_data = &tf_resc_usage[dir].wc_tcam_usage; - /* cfa_tcam_mgr_table_dump(session_id, dir, type); */ + /* cfa_tcam_mgr_table_dump(tfs->session_id.id, dir, type); */ memset(usage_data, 0, sizeof(*usage_data)); if (table_data->start_row != table_data->end_row) usage_data->max_row_number = table_data->end_row - @@ -122,33 +123,49 @@ void tf_tcam_usage_init(int session_id) #if (TF_FLOW_SCALE_QUERY_DEBUG == 1) /* dump usage data */ - CFA_TCAM_MGR_LOG(INFO, "WC-TCAM: 1-p 1-f 2-p 2-f 4-f free-rows\n"); - CFA_TCAM_MGR_LOG(INFO, "%s %-4d %-4d %-4d %-4d %-4d %-4d\n", - (dir == TF_DIR_RX) ? "RX" : "TX", - usage_data->slice_row_1_p_used, - usage_data->slice_row_1_f_used, - usage_data->slice_row_2_p_used, - usage_data->slice_row_2_f_used, - usage_data->slice_row_4_used, - usage_data->unused_row_number); + TFP_DRV_LOG(INFO, "WC-TCAM: 1-p 1-f 2-p 2-f 4-f free-rows\n"); + TFP_DRV_LOG(INFO, "%s %-4d %-4d %-4d %-4d %-4d %-4d\n", + (dir == TF_DIR_RX) ? "RX" : "TX", + usage_data->slice_row_1_p_used, + usage_data->slice_row_1_f_used, + usage_data->slice_row_2_p_used, + usage_data->slice_row_2_f_used, + usage_data->slice_row_4_used, + usage_data->unused_row_number); #endif } } /* Update wc-tcam table resoure usage */ -int tf_tcam_usage_update(int session_id, +int tf_tcam_usage_update(struct tf *tfp, enum tf_dir dir, int tcam_tbl_type, void *data, enum tf_resc_opt resc_opt) { - struct tf_resc_wc_tcam_usage *usage_data; - int used_entries; struct cfa_tcam_mgr_table_rows_0 *key_row = (struct cfa_tcam_mgr_table_rows_0 *)data; + struct tf_resc_wc_tcam_usage *usage_data; + struct cfa_tcam_mgr_data *tcam_mgr_data; int key_slices = key_row->entry_size; + struct tf_session *tfs; + int used_entries; + int rc; + + /* Check if supported on this device */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + tcam_mgr_data = tfs->tcam_mgr_handle; + if (!tcam_mgr_data) { + TFP_DRV_LOG(ERR, + "%s: No TCAM data created for session\n", + __func__); + return -CFA_TCAM_MGR_ERR_CODE(PERM); + } /* Check if supported on this device */ - if (!tf_resc_usage_support(session_id)) + if (!tf_resc_usage_support(tfp)) return -1; /* Support WC-TCAM APPs only */ @@ -184,7 +201,8 @@ int tf_tcam_usage_update(int session_id, } break; default: - CFA_TCAM_MGR_LOG(ERR, "CFA invalid size of key slices: %d\n", key_slices); + TFP_DRV_LOG(ERR, "CFA invalid size of key slices: %d\n", + key_slices); break; } } else { /* free one entry */ @@ -213,32 +231,33 @@ int tf_tcam_usage_update(int session_id, } break; default: - CFA_TCAM_MGR_LOG(ERR, "CFA invalid size of key slices: %d\n", key_slices); + TFP_DRV_LOG(ERR, "CFA invalid size of key slices: %d\n", + key_slices); break; } } #if (TF_FLOW_SCALE_QUERY_DEBUG == 1) /* dump usage data*/ - CFA_TCAM_MGR_LOG(INFO, "WC-TCAM: 1-p 1-f 2-p 2-f 4-f free-rows\n"); - CFA_TCAM_MGR_LOG(INFO, " %-4d %-4d %-4d %-4d %-4d %-4d\n", - usage_data->slice_row_1_p_used, - usage_data->slice_row_1_f_used, - usage_data->slice_row_2_p_used, - usage_data->slice_row_2_f_used, - usage_data->slice_row_4_used, - usage_data->unused_row_number); + TFP_DRV_LOG(INFO, "WC-TCAM: 1-p 1-f 2-p 2-f 4-f free-rows\n"); + TFP_DRV_LOG(INFO, " %-4d %-4d %-4d %-4d %-4d %-4d\n", + usage_data->slice_row_1_p_used, + usage_data->slice_row_1_f_used, + usage_data->slice_row_2_p_used, + usage_data->slice_row_2_f_used, + usage_data->slice_row_4_used, + usage_data->unused_row_number); #endif return 0; } /* Initialize the EM usage table */ -void tf_em_usage_init(uint32_t session_id, enum tf_dir dir, uint16_t max_entries) +void tf_em_usage_init(struct tf *tfp, enum tf_dir dir, uint16_t max_entries) { struct tf_resc_em_usage *em; /* Check if supported on this device */ - if (!tf_resc_usage_support(session_id)) + if (!tf_resc_usage_support(tfp)) return; em = &tf_resc_usage[dir].em_int_usage; @@ -247,7 +266,7 @@ void tf_em_usage_init(uint32_t session_id, enum tf_dir dir, uint16_t max_entries } /* Update the EM usage table */ -int tf_em_usage_update(uint32_t session_id, +int tf_em_usage_update(struct tf *tfp, enum tf_dir dir, uint16_t size, enum tf_resc_opt resc_opt) @@ -255,15 +274,15 @@ int tf_em_usage_update(uint32_t session_id, struct tf_resc_em_usage *em; #if (TF_FLOW_SCALE_QUERY_DEBUG == 1) - CFA_TCAM_MGR_LOG(INFO, "%s: %s: EM record size: %d, %s\n", - __func__, - dir ? "TX" : "RX", - size, - resc_opt == TF_RESC_ALLOC ? "Alloc" : "Free"); + TFP_DRV_LOG(INFO, "%s: %s: EM record size: %d, %s\n", + __func__, + dir ? "TX" : "RX", + size, + resc_opt == TF_RESC_ALLOC ? "Alloc" : "Free"); #endif /* TF_FLOW_SCALE_QUERY_DEBUG == 1 */ /* Check if supported on this device */ - if (!tf_resc_usage_support(session_id)) + if (!tf_resc_usage_support(tfp)) return -1; /* not valid size */ @@ -283,7 +302,7 @@ int tf_em_usage_update(uint32_t session_id, } /* Initialize the usage buffer for all kinds of sram tables */ -void tf_tbl_usage_init(uint32_t session_id, +void tf_tbl_usage_init(struct tf *tfp, enum tf_dir dir, uint32_t tbl_type, uint16_t max_entries) @@ -291,17 +310,17 @@ void tf_tbl_usage_init(uint32_t session_id, struct tf_rm_element_cfg *tbl_cfg = tf_tbl_p58[dir]; #if (TF_FLOW_SCALE_QUERY_DEBUG == 1) - CFA_TCAM_MGR_LOG(INFO, "%s: %s: tbl_type: %d[%s], max entries: [%d]:[0x%x]\n", - __func__, - dir ? "TX" : "RX", - tbl_type, - tf_tbl_type_2_str(tbl_type), - max_entries, - max_entries); + TFP_DRV_LOG(INFO, "%s: %s: tbl_type: %d[%s], max entries: [%d]:[0x%x]\n", + __func__, + dir ? "TX" : "RX", + tbl_type, + tf_tbl_type_2_str(tbl_type), + max_entries, + max_entries); #endif /* TF_FLOW_SCALE_QUERY_DEBUG == 1 */ /* Check if supported on this device */ - if (!tf_resc_usage_support(session_id)) + if (!tf_resc_usage_support(tfp)) return; /* Convert to entries */ @@ -372,7 +391,7 @@ void tf_tbl_usage_init(uint32_t session_id, } /* Update the usage buffer for sram tables: add or free one entry */ -int tf_tbl_usage_update(uint32_t session_id, +int tf_tbl_usage_update(struct tf *tfp, enum tf_dir dir, uint32_t tbl_type, enum tf_resc_opt resc_opt) @@ -384,7 +403,7 @@ int tf_tbl_usage_update(uint32_t session_id, int entries = 0; /* Check if supported on this device */ - if (!tf_resc_usage_support(session_id)) + if (!tf_resc_usage_support(tfp)) return -1; /* Convert to entries */ @@ -393,11 +412,11 @@ int tf_tbl_usage_update(uint32_t session_id, #if (TF_FLOW_SCALE_QUERY_DEBUG == 1) TFP_DRV_LOG(INFO, "%s: %s: tbl_type: %d[%s] %s, Entries: %d\n", __func__, - dir ? "TX" : "RX", - tbl_type, - tf_tbl_type_2_str(tbl_type), - resc_opt ? "Alloc" : "Free", - entries); + dir ? "TX" : "RX", + tbl_type, + tf_tbl_type_2_str(tbl_type), + resc_opt ? "Alloc" : "Free", + entries); #endif /* TF_FLOW_SCALE_QUERY_DEBUG == 1 */ resc_usage_control.buffer_dirty[dir] = 1; @@ -521,7 +540,7 @@ void tf_resc_usage_update_all(struct bnxt *bp) } /* Check if supported on this device */ - if (!tf_resc_usage_support(tfp->session->session_id.id)) + if (!tf_resc_usage_support(tfp)) return; /* update usage state with firmware for each direction */ @@ -557,11 +576,11 @@ void dump_tf_resc_usage(enum tf_dir dir, void *data, uint32_t size) } printf("EM-----------------------------------------------------------------------\n"); - printf(" %4d: %4d\n", + printf(" %4d: %4d\n", state->em_int_usage.max_entries, state->em_int_usage.used_entries); printf("WC TCAM------------------------------------------------------------------\n"); - printf(" %4d(row): %4d %4d %4d %4d %4d %4d(free row)\n", + printf(" %4d(row): %4d %4d %4d %4d %4d %4d(free row)\n", state->wc_tcam_usage.max_row_number, state->wc_tcam_usage.slice_row_1_p_used, state->wc_tcam_usage.slice_row_1_f_used, @@ -570,31 +589,31 @@ void dump_tf_resc_usage(enum tf_dir dir, void *data, uint32_t size) state->wc_tcam_usage.slice_row_4_used, state->wc_tcam_usage.unused_row_number); printf("COUNTER------------------------------------------------------------------\n"); - printf(" %4d: %4d\n", + printf(" %4d: %4d\n", state->cnt_usage.max_entries, state->cnt_usage.used_entries); printf("METER------------------------------------------------------------------\n"); - printf(" %4d(Inst): %4d, %4d(Prof): %4d\n", + printf(" %4d(Inst): %4d, %4d(Prof): %4d\n", state->meter_usage.max_meter_instance, state->meter_usage.used_meter_instance, state->meter_usage.max_meter_profile, state->meter_usage.used_meter_profile); printf("ACTION-------------------------------------------------------------------\n"); - printf(" %4d(MAX): %4d(compact) %4d(full) %4d(free)\n", + printf(" %4d(MAX): %4d(compact) %4d(full) %4d(free)\n", state->act_usage.max_entries, state->act_usage.num_compact_act_records, state->act_usage.num_full_act_records, state->act_usage.free_entries); printf("SP SMAC------------------------------------------------------------------\n"); sp_smac = &state->sp_smac_usage; - printf(" %4d(Max): %4d(8B) %4d(IPv4=16B) %4d(IPv6=32B) %4d(free)\n", + printf(" %4d(Max): %4d(8B) %4d(IPv4=16B) %4d(IPv6=32B) %4d(free)\n", sp_smac->max_entries, sp_smac->num_sp_smac_records, sp_smac->num_sp_smac_ipv4_records, sp_smac->num_sp_smac_ipv6_records, sp_smac->free_entries); printf("ACT MOD/ENCAP------------------------------------------------------------\n"); - printf(" %4d: %4d(8B) %4d(16B) %4d(32B) %4d(64B) %4d(128B) %4d(free)\n\n\n", + printf(" %4d: %4d(8B) %4d(16B) %4d(32B) %4d(64B) %4d(128B) %4d(free)\n\n\n", state->mod_encap_usage.max_entries, state->mod_encap_usage.data.num_8b_records, state->mod_encap_usage.data.num_16b_records, diff --git a/drivers/net/bnxt/tf_core/tf_resources.h b/drivers/net/bnxt/tf_core/tf_resources.h index 715c9e0d94..e77e882b70 100644 --- a/drivers/net/bnxt/tf_core/tf_resources.h +++ b/drivers/net/bnxt/tf_core/tf_resources.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2023 Broadcom + * Copyright(c) 2019-2024 Broadcom * All rights reserved. */ @@ -97,29 +97,29 @@ typedef struct cfa_tf_resc_usage { /* global data stored in firmware memory and TruFlow driver */ extern cfa_tf_resc_usage_t tf_resc_usage[TF_DIR_MAX]; -void tf_resc_usage_reset(enum tf_device_type type, int session_id); +void tf_resc_usage_reset(struct tf *tfp, enum tf_device_type type); -void tf_tcam_usage_init(int session_id); +void tf_tcam_usage_init(struct tf *tfp); -int tf_tcam_usage_update(int session_id, +int tf_tcam_usage_update(struct tf *tfp, enum tf_dir dir, int tcam_tbl_type, void *key_row, enum tf_resc_opt resc_opt); -void tf_em_usage_init(uint32_t session_id, enum tf_dir dir, uint16_t max_entries); +void tf_em_usage_init(struct tf *tfp, enum tf_dir dir, uint16_t max_entries); -int tf_em_usage_update(uint32_t session_id, +int tf_em_usage_update(struct tf *tfp, enum tf_dir dir, uint16_t size, enum tf_resc_opt resc_opt); -void tf_tbl_usage_init(uint32_t session_id, +void tf_tbl_usage_init(struct tf *tfp, enum tf_dir dir, uint32_t tbl_type, uint16_t max_entries); -int tf_tbl_usage_update(uint32_t session_id, +int tf_tbl_usage_update(struct tf *tfp, enum tf_dir dir, uint32_t tbl_type, enum tf_resc_opt resc_opt); diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c index e38bfcf4f6..e9a2fbd851 100644 --- a/drivers/net/bnxt/tf_core/tf_rm.c +++ b/drivers/net/bnxt/tf_core/tf_rm.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2023 Broadcom + * Copyright(c) 2019-2024 Broadcom * All rights reserved. */ @@ -428,7 +428,7 @@ tf_rm_update_parent_reservations(struct tf *tfp, req_cnt[child] = 0; #ifdef TF_FLOW_SCALE_QUERY /* Initialize the usage buffer for SRAM tables */ - tf_tbl_usage_init(tfp->session->session_id.id, + tf_tbl_usage_init(tfp, dir, child, alloc_cnt[child]); @@ -698,7 +698,7 @@ tf_rm_create_db(struct tf *tfp, tbl_type = TF_TBL_TYPE_METER_INST; else tbl_type = TF_TBL_TYPE_METER_PROF; - tf_tbl_usage_init(tfp->session->session_id.id, + tf_tbl_usage_init(tfp, parms->dir, tbl_type, req_cnt[i]); diff --git a/drivers/net/bnxt/tf_core/tf_session.c b/drivers/net/bnxt/tf_core/tf_session.c index 7545974c93..1c14378d11 100644 --- a/drivers/net/bnxt/tf_core/tf_session.c +++ b/drivers/net/bnxt/tf_core/tf_session.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2023 Broadcom + * Copyright(c) 2019-2024 Broadcom * All rights reserved. */ @@ -199,7 +199,7 @@ tf_session_create(struct tf *tfp, #ifdef TF_FLOW_SCALE_QUERY /* Reset the resource usage buffer before binding a device */ - tf_resc_usage_reset(parms->open_cfg->device_type, tfp->session->session_id.id); + tf_resc_usage_reset(tfp, parms->open_cfg->device_type); #endif /* TF_FLOW_SCALE_QUERY */ rc = tf_dev_bind(tfp, diff --git a/drivers/net/bnxt/tf_core/tf_session.h b/drivers/net/bnxt/tf_core/tf_session.h index 9bbbccf125..d46d89e9e9 100644 --- a/drivers/net/bnxt/tf_core/tf_session.h +++ b/drivers/net/bnxt/tf_core/tf_session.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2023 Broadcom + * Copyright(c) 2019-2024 Broadcom * All rights reserved. */ @@ -179,6 +179,10 @@ struct tf_session { */ int tcam_mgr_control[TF_DIR_MAX][TF_TCAM_TBL_TYPE_MAX]; + /** + * TCAM Manager handle pointing to session based tcam memory + */ + void *tcam_mgr_handle; }; /** diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c index df5cad75b5..fa8f60777d 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam.c +++ b/drivers/net/bnxt/tf_core/tf_tcam.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2023 Broadcom + * Copyright(c) 2019-2024 Broadcom * All rights reserved. */ @@ -27,7 +27,7 @@ tf_tcam_bind(struct tf *tfp, int d, t; struct tf_rm_alloc_info info; struct tf_rm_free_db_parms fparms; - struct tf_rm_create_db_parms db_cfg; + struct tf_rm_create_db_parms db_cfg = { 0 }; struct tf_tcam_resources local_tcam_cnt[TF_DIR_MAX]; struct tf_tcam_resources *tcam_cnt; struct tf_rm_get_alloc_info_parms ainfo; diff --git a/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c b/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c index c535f4f4f6..8c1e6d2e0f 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c +++ b/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2021-2023 Broadcom + * Copyright(c) 2021-2024 Broadcom * All rights reserved. */ @@ -8,6 +8,7 @@ #include "tfp.h" #include "tf_tcam.h" #include "cfa_tcam_mgr.h" +#include "cfa_tcam_mgr_device.h" #include "tf_tcam_mgr_msg.h" /* @@ -53,13 +54,11 @@ tf_tcam_mgr_qcaps_msg(struct tf *tfp, uint32_t *rx_tcam_supported, uint32_t *tx_tcam_supported) { - struct cfa_tcam_mgr_context context; struct cfa_tcam_mgr_qcaps_parms mgr_parms; int rc; - context.tfp = tfp; memset(&mgr_parms, 0, sizeof(mgr_parms)); - rc = cfa_tcam_mgr_qcaps(&context, &mgr_parms); + rc = cfa_tcam_mgr_qcaps(tfp, &mgr_parms); if (rc >= 0) { *rx_tcam_supported = mgr_parms.rx_tcam_supported; *tx_tcam_supported = mgr_parms.tx_tcam_supported; @@ -75,7 +74,10 @@ tf_tcam_mgr_bind_msg(struct tf *tfp, __rte_unused ) { - /* Common Code */ + struct tf_rm_resc_entry + mgr_resv_res[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX]; + struct cfa_tcam_mgr_cfg_parms mgr_parms; + int dir, rc; int type; if (parms->num_elements != TF_TCAM_TBL_TYPE_MAX) { @@ -91,14 +93,6 @@ tf_tcam_mgr_bind_msg(struct tf *tfp, for (type = 0; type < TF_TCAM_TBL_TYPE_MAX; type++) hcapi_type[type] = parms->cfg[type].hcapi_type; - struct cfa_tcam_mgr_context context; - struct cfa_tcam_mgr_cfg_parms mgr_parms; - struct tf_rm_resc_entry - mgr_resv_res[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX]; - int dir, rc; - - context.tfp = tfp; - memset(&mgr_parms, 0, sizeof(mgr_parms)); mgr_parms.num_elements = CFA_TCAM_MGR_TBL_TYPE_MAX; @@ -116,7 +110,7 @@ tf_tcam_mgr_bind_msg(struct tf *tfp, } mgr_parms.resv_res = mgr_resv_res; - rc = cfa_tcam_mgr_bind(&context, &mgr_parms); + rc = cfa_tcam_mgr_bind(tfp, &mgr_parms); return rc; } @@ -125,11 +119,7 @@ int tf_tcam_mgr_unbind_msg(struct tf *tfp, struct tf_dev_info *dev __rte_unused) { - struct cfa_tcam_mgr_context context; - - context.tfp = tfp; - - return cfa_tcam_mgr_unbind(&context); + return cfa_tcam_mgr_unbind(tfp); } int @@ -137,7 +127,6 @@ tf_tcam_mgr_alloc_msg(struct tf *tfp, struct tf_dev_info *dev __rte_unused, struct tf_tcam_alloc_parms *parms) { - struct cfa_tcam_mgr_context context; struct cfa_tcam_mgr_alloc_parms mgr_parms; int rc; @@ -148,8 +137,6 @@ tf_tcam_mgr_alloc_msg(struct tf *tfp, return -EINVAL; } - context.tfp = tfp; - mgr_parms.dir = parms->dir; mgr_parms.type = tcam_types[parms->type]; mgr_parms.hcapi_type = hcapi_type[parms->type]; @@ -159,7 +146,7 @@ tf_tcam_mgr_alloc_msg(struct tf *tfp, else mgr_parms.priority = TF_TCAM_PRIORITY_MAX - parms->priority - 1; - rc = cfa_tcam_mgr_alloc(&context, &mgr_parms); + rc = cfa_tcam_mgr_alloc(tfp, &mgr_parms); if (rc) return rc; @@ -172,7 +159,6 @@ tf_tcam_mgr_free_msg(struct tf *tfp, struct tf_dev_info *dev __rte_unused, struct tf_tcam_free_parms *parms) { - struct cfa_tcam_mgr_context context; struct cfa_tcam_mgr_free_parms mgr_parms; if (parms->type >= TF_TCAM_TBL_TYPE_MAX) { @@ -182,13 +168,12 @@ tf_tcam_mgr_free_msg(struct tf *tfp, return -EINVAL; } - context.tfp = tfp; mgr_parms.dir = parms->dir; mgr_parms.type = tcam_types[parms->type]; mgr_parms.hcapi_type = hcapi_type[parms->type]; mgr_parms.id = parms->idx; - return cfa_tcam_mgr_free(&context, &mgr_parms); + return cfa_tcam_mgr_free(tfp, &mgr_parms); } int @@ -196,7 +181,6 @@ tf_tcam_mgr_set_msg(struct tf *tfp, struct tf_dev_info *dev __rte_unused, struct tf_tcam_set_parms *parms) { - struct cfa_tcam_mgr_context context; struct cfa_tcam_mgr_set_parms mgr_parms; if (parms->type >= TF_TCAM_TBL_TYPE_MAX) { @@ -206,7 +190,6 @@ tf_tcam_mgr_set_msg(struct tf *tfp, return -EINVAL; } - context.tfp = tfp; mgr_parms.dir = parms->dir; mgr_parms.type = tcam_types[parms->type]; mgr_parms.hcapi_type = hcapi_type[parms->type]; @@ -217,7 +200,7 @@ tf_tcam_mgr_set_msg(struct tf *tfp, mgr_parms.result = parms->result; mgr_parms.result_size = parms->result_size; - return cfa_tcam_mgr_set(&context, &mgr_parms); + return cfa_tcam_mgr_set(tfp, &mgr_parms); } int @@ -225,9 +208,8 @@ tf_tcam_mgr_get_msg(struct tf *tfp, struct tf_dev_info *dev __rte_unused, struct tf_tcam_get_parms *parms) { - int rc; - struct cfa_tcam_mgr_context context; struct cfa_tcam_mgr_get_parms mgr_parms; + int rc; if (parms->type >= TF_TCAM_TBL_TYPE_MAX) { TFP_DRV_LOG(ERR, @@ -236,7 +218,6 @@ tf_tcam_mgr_get_msg(struct tf *tfp, return -EINVAL; } - context.tfp = tfp; mgr_parms.dir = parms->dir; mgr_parms.type = tcam_types[parms->type]; mgr_parms.hcapi_type = hcapi_type[parms->type]; @@ -247,7 +228,7 @@ tf_tcam_mgr_get_msg(struct tf *tfp, mgr_parms.result = parms->result; mgr_parms.result_size = parms->result_size; - rc = cfa_tcam_mgr_get(&context, &mgr_parms); + rc = cfa_tcam_mgr_get(tfp, &mgr_parms); if (rc) return rc; @@ -261,26 +242,22 @@ int tf_tcam_mgr_shared_clear_msg(struct tf *tfp, struct tf_clear_tcam_shared_entries_parms *parms) { - struct cfa_tcam_mgr_context context; struct cfa_tcam_mgr_shared_clear_parms mgr_parms; - context.tfp = tfp; mgr_parms.dir = parms->dir; mgr_parms.type = tcam_types[parms->tcam_tbl_type]; - return cfa_tcam_mgr_shared_clear(&context, &mgr_parms); + return cfa_tcam_mgr_shared_clear(tfp, &mgr_parms); } int tf_tcam_mgr_shared_move_msg(struct tf *tfp, struct tf_move_tcam_shared_entries_parms *parms) { - struct cfa_tcam_mgr_context context; struct cfa_tcam_mgr_shared_move_parms mgr_parms; - context.tfp = tfp; mgr_parms.dir = parms->dir; mgr_parms.type = tcam_types[parms->tcam_tbl_type]; - return cfa_tcam_mgr_shared_move(&context, &mgr_parms); + return cfa_tcam_mgr_shared_move(tfp, &mgr_parms); } From patchwork Fri Aug 30 14:00:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sriharsha Basavapatna X-Patchwork-Id: 143473 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8976E458A8; Fri, 30 Aug 2024 15:52:28 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BA73E42EDC; Fri, 30 Aug 2024 15:51:25 +0200 (CEST) Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) by mails.dpdk.org (Postfix) with ESMTP id 6808342ECE for ; Fri, 30 Aug 2024 15:51:23 +0200 (CEST) Received: by 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d9443c01a7336-205155658dfsm27067145ad.297.2024.08.30.06.51.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Aug 2024 06:51:21 -0700 (PDT) From: Sriharsha Basavapatna To: dev@dpdk.org Cc: Randy Schacher , Farah Smith , Kishore Padmanabha , Sriharsha Basavapatna Subject: [PATCH 09/47] net/bnxt: tf_core: remove dead AFM code from session-based priority TCAM mgr Date: Fri, 30 Aug 2024 19:30:11 +0530 Message-Id: <20240830140049.1715230-10-sriharsha.basavapatna@broadcom.com> X-Mailer: git-send-email 2.39.0.189.g4dbebc36b0 In-Reply-To: <20240830140049.1715230-1-sriharsha.basavapatna@broadcom.com> References: <20240830140049.1715230-1-sriharsha.basavapatna@broadcom.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Randy Schacher Remove references to AFM allocated memory which is no longer supported with TCAM mgr and truflow Signed-off-by: Randy Schacher Reviewed-by: Farah Smith Reviewed-by: Kishore Padmanabha Signed-off-by: Sriharsha Basavapatna --- drivers/net/bnxt/tf_core/cfa_tcam_mgr.c | 121 ++++---- drivers/net/bnxt/tf_core/cfa_tcam_mgr.h | 27 +- drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c | 320 +++----------------- drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c | 320 +++----------------- drivers/net/bnxt/tf_core/tf_resources.c | 4 +- drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c | 18 +- 6 files changed, 143 insertions(+), 667 deletions(-) diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c index 165376182e..380e828da8 100644 --- a/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c @@ -20,23 +20,23 @@ #define TF_TCAM_SLICE_INVALID (-1) static int physical_table_types[CFA_TCAM_MGR_TBL_TYPE_MAX] = { - [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS] = + [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH] = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS] = + [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW] = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS] = + [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM] = TF_TCAM_TBL_TYPE_PROF_TCAM, - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS] = + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM] = TF_TCAM_TBL_TYPE_WC_TCAM, - [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS] = + [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM] = TF_TCAM_TBL_TYPE_SP_TCAM, - [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS] = + [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM] = TF_TCAM_TBL_TYPE_CT_RULE_TCAM, - [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS] = + [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM] = TF_TCAM_TBL_TYPE_VEB_TCAM, - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS] = + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH] = TF_TCAM_TBL_TYPE_WC_TCAM_HIGH, - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS] = + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW] = TF_TCAM_TBL_TYPE_WC_TCAM_LOW, }; @@ -53,41 +53,23 @@ const char * cfa_tcam_mgr_tbl_2_str(enum cfa_tcam_mgr_tbl_type tcam_type) { switch (tcam_type) { - case CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM: - return "l2_ctxt_tcam_high AFM"; - case CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS: + case CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH: return "l2_ctxt_tcam_high Apps"; - case CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_AFM: - return "l2_ctxt_tcam_low AFM"; - case CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS: + case CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW: return "l2_ctxt_tcam_low Apps"; - case CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_AFM: - return "prof_tcam AFM"; - case CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS: + case CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM: return "prof_tcam Apps"; - case CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_AFM: - return "wc_tcam AFM"; - case CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS: + case CFA_TCAM_MGR_TBL_TYPE_WC_TCAM: return "wc_tcam Apps"; - case CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_AFM: - return "veb_tcam AFM"; - case CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS: + case CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM: return "veb_tcam Apps"; - case CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_AFM: - return "sp_tcam AFM"; - case CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS: + case CFA_TCAM_MGR_TBL_TYPE_SP_TCAM: return "sp_tcam Apps"; - case CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_AFM: - return "ct_rule_tcam AFM"; - case CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS: + case CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM: return "ct_rule_tcam Apps"; - case CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_AFM: - return "wc_tcam_high AFM"; - case CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS: + case CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH: return "wc_tcam_high Apps"; - case CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_AFM: - return "wc_tcam_low AFM"; - case CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS: + case CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW: return "wc_tcam_low Apps"; default: return "Invalid tcam table type"; @@ -972,10 +954,13 @@ cfa_tcam_mgr_bitmap_alloc(struct tf *tfp __rte_unused, /* Allocate first index to avoid idx 0 */ first_idx = ba_alloc(tcam_mgr_data->session_bmp); - if (first_idx == BA_FAIL) + if (first_idx == BA_FAIL) { + tfp_free(tcam_mgr_data->session_bmp); + tcam_mgr_data->session_bmp = NULL; return -CFA_TCAM_MGR_ERR_CODE(NOSPC); + } - TFP_DRV_LOG(INFO, + TFP_DRV_LOG(DEBUG, "session bitmap size is %" PRIX64 "\n", tcam_mgr_data->session_bmp_size); @@ -1087,8 +1072,9 @@ cfa_tcam_mgr_init(struct tf *tfp, enum cfa_tcam_mgr_device_type type, if (parms) parms->max_entries = tcam_mgr_data->cfa_tcam_mgr_max_entries; - CFA_TCAM_MGR_LOG(DEBUG, "Global TCAM tbl initialized max entries %d\n", - tcam_mgr_data->cfa_tcam_mgr_max_entries); + CFA_TCAM_MGR_TRACE(DEBUG, + "Global TCAM tbl initialized max entries %d\n", + tcam_mgr_data->cfa_tcam_mgr_max_entries); return 0; } @@ -1227,38 +1213,41 @@ cfa_tcam_mgr_shared_wc_bind(struct tf *tfp, bool dual_ha_app, for (dir = 0; dir < TF_DIR_MAX; dir++) { rc = cfa_tcam_mgr_tables_get(tfp, dir, - CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS, - &start_row, &end_row, &max_entries, &slices); + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM, + &start_row, &end_row, &max_entries, + &slices); if (rc) return rc; if (max_entries) { rc = cfa_tcam_mgr_tables_set(tfp, dir, - CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS, + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH, start_row, start_row + - ((max_entries / slices) / num_pools) - 1, + ((max_entries / slices) / + num_pools) - 1, max_entries / num_pools); if (rc) return rc; rc = cfa_tcam_mgr_tables_set(tfp, dir, - CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS, + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW, start_row + - ((max_entries / slices) / num_pools), + ((max_entries / slices) / + num_pools), start_row + (max_entries / slices) - 1, max_entries / num_pools); if (rc) return rc; rc = cfa_tcam_mgr_tables_set(tfp, dir, - CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS, + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM, 0, 0, 0); if (rc) return rc; - tcam_cnt[dir][CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS] = + tcam_cnt[dir][CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH] = max_entries / num_pools; - tcam_cnt[dir][CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS] = + tcam_cnt[dir][CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW] = max_entries / num_pools; - tcam_cnt[dir][CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS] = 0; + tcam_cnt[dir][CFA_TCAM_MGR_TBL_TYPE_WC_TCAM] = 0; } } @@ -1389,8 +1378,8 @@ cfa_tcam_mgr_bind(struct tf *tfp, } } - CFA_TCAM_MGR_LOG(DEBUG, "TCAM table bind for max entries %d.\n", - tcam_mgr_data->cfa_tcam_mgr_max_entries); + CFA_TCAM_MGR_TRACE(DEBUG, "TCAM table bind for max entries %d.\n", + tcam_mgr_data->cfa_tcam_mgr_max_entries); if (tf_session_is_shared_hotup_session(tfs)) { rc = cfa_tcam_mgr_shared_wc_bind(tfp, false, @@ -1537,16 +1526,6 @@ cfa_tcam_mgr_alloc(struct tf *tfp, return -CFA_TCAM_MGR_ERR_CODE(INVAL); } -#if TF_TCAM_PRIORITY_MAX < UINT16_MAX - if (parms->priority > TF_TCAM_PRIORITY_MAX) { - CFA_TCAM_MGR_LOG_DIR(ERR, dir, - "%s: Priority:%u out of range (%u-%u).\n", - tf_dir_2_str(dir), parms->priority, - TF_TCAM_PRIORITY_MIN, - TF_TCAM_PRIORITY_MAX); - } -#endif - rc = tf_session_get_session_internal(tfp, &tfs); if (rc) return rc; @@ -1650,7 +1629,7 @@ cfa_tcam_mgr_free(struct tf *tfp, id = parms->id; entry = cfa_tcam_mgr_entry_get(tcam_mgr_data, id); if (!entry) { - CFA_TCAM_MGR_LOG(INFO, "Entry %d not found\n", id); + CFA_TCAM_MGR_LOG(ERR, "Entry %d not found\n", id); return -CFA_TCAM_MGR_ERR_CODE(INVAL); } @@ -1976,7 +1955,7 @@ cfa_tcam_mgr_shared_entry_move(struct cfa_tcam_mgr_data *tcam_mgr_data, return rc; sparms.dir = dir; - sparms.type = CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS; + sparms.type = CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW; sparms.hcapi_type = table_data->hcapi_type; sparms.key = key; sparms.mask = mask; @@ -2033,7 +2012,7 @@ cfa_tcam_mgr_shared_entry_move(struct cfa_tcam_mgr_data *tcam_mgr_data, #ifdef CFA_TCAM_MGR_TRACING cfa_tcam_mgr_rows_dump(tfp, dir, type); cfa_tcam_mgr_rows_dump(tfp, dir, - CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS); + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW); #endif return 0; @@ -2065,15 +2044,15 @@ int cfa_tcam_mgr_shared_move(struct tf *tfp, src_table_data = &tcam_mgr_data->cfa_tcam_mgr_tables[parms->dir] - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS]; + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH]; dst_table_data = &tcam_mgr_data->cfa_tcam_mgr_tables[parms->dir] - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS]; + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW]; row_size = cfa_tcam_mgr_row_size_get(tcam_mgr_data, parms->dir, - CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS); + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH); for (src_row = src_table_data->start_row, dst_row = dst_table_data->start_row; @@ -2099,8 +2078,8 @@ int cfa_tcam_mgr_shared_move(struct tf *tfp, rc = cfa_tcam_mgr_shared_entry_move(tcam_mgr_data, tfp, parms->dir, - CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS, - src_table_row->entries[slice], + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH, + src_table_row->entries[slice], dst_table_data, src_table_data, dst_row, slice, @@ -2235,6 +2214,7 @@ cfa_tcam_mgr_tables_set(struct tf *tfp, enum tf_dir dir, return 0; } +#ifdef CFA_TCAM_MGR_TRACING void cfa_tcam_mgr_rows_dump(struct tf *tfp, enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type) @@ -2425,3 +2405,4 @@ cfa_tcam_mgr_entries_dump(struct tf *tfp) if (!entry_found) printf("No entries found.\n"); } +#endif /* CFA_TCAM_MGR_TRACING */ diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.h index d4f8512d2a..25654a8351 100644 --- a/drivers/net/bnxt/tf_core/cfa_tcam_mgr.h +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.h @@ -88,25 +88,16 @@ /* Logical TCAM tables */ enum cfa_tcam_mgr_tbl_type { - CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM = + CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH = CFA_TCAM_MGR_TBL_TYPE_START, - CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS, - CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_AFM, - CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS, - CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_AFM, - CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS, - CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_AFM, - CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS, - CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_AFM, - CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS, - CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_AFM, - CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS, - CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_AFM, - CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS, - CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_AFM, - CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS, - CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_AFM, - CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS, + CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW, + CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM, + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM, + CFA_TCAM_MGR_TBL_TYPE_SP_TCAM, + CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM, + CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM, + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH, + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW, CFA_TCAM_MGR_TBL_TYPE_MAX }; diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c index b2eadde61e..acb3a8f832 100644 --- a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c @@ -165,17 +165,7 @@ struct cfa_tcam_mgr_table_rows_p4 { struct cfa_tcam_mgr_table_data cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { { /* RX */ - { /* High AFM */ - .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES, - .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH, - .num_rows = L2_CTXT_TCAM_RX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE, - .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH, - }, - { /* High APPS */ + { .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES, .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH, .num_rows = L2_CTXT_TCAM_RX_NUM_ROWS, @@ -185,17 +175,7 @@ cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE, .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH, }, - { /* Low AFM */ - .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES, - .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH, - .num_rows = L2_CTXT_TCAM_RX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE, - .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW, - }, - { /* Low APPS */ + { .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES, .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH, .num_rows = L2_CTXT_TCAM_RX_NUM_ROWS, @@ -205,17 +185,7 @@ cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE, .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW, }, - { /* AFM */ - .max_slices = PROF_TCAM_RX_MAX_SLICES, - .row_width = PROF_TCAM_RX_ROW_WIDTH, - .num_rows = PROF_TCAM_RX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = PROF_TCAM_RX_RESULT_SIZE, - .hcapi_type = CFA_RESOURCE_TYPE_P4_PROF_TCAM, - }, - { /* APPS */ + { .max_slices = PROF_TCAM_RX_MAX_SLICES, .row_width = PROF_TCAM_RX_ROW_WIDTH, .num_rows = PROF_TCAM_RX_NUM_ROWS, @@ -225,17 +195,7 @@ cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .result_size = PROF_TCAM_RX_RESULT_SIZE, .hcapi_type = CFA_RESOURCE_TYPE_P4_PROF_TCAM, }, - { /* AFM */ - .max_slices = WC_TCAM_RX_MAX_SLICES, - .row_width = WC_TCAM_RX_ROW_WIDTH, - .num_rows = WC_TCAM_RX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = WC_TCAM_RX_RESULT_SIZE, - .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM, - }, - { /* APPS */ + { .max_slices = WC_TCAM_RX_MAX_SLICES, .row_width = WC_TCAM_RX_ROW_WIDTH, .num_rows = WC_TCAM_RX_NUM_ROWS, @@ -245,17 +205,7 @@ cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .result_size = WC_TCAM_RX_RESULT_SIZE, .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM, }, - { /* AFM */ - .max_slices = SP_TCAM_RX_MAX_SLICES, - .row_width = SP_TCAM_RX_ROW_WIDTH, - .num_rows = SP_TCAM_RX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = SP_TCAM_RX_RESULT_SIZE, - .hcapi_type = CFA_RESOURCE_TYPE_P4_SP_TCAM, - }, - { /* APPS */ + { .max_slices = SP_TCAM_RX_MAX_SLICES, .row_width = SP_TCAM_RX_ROW_WIDTH, .num_rows = SP_TCAM_RX_NUM_ROWS, @@ -265,16 +215,7 @@ cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .result_size = SP_TCAM_RX_RESULT_SIZE, .hcapi_type = CFA_RESOURCE_TYPE_P4_SP_TCAM, }, - { /* AFM */ - .max_slices = CT_RULE_TCAM_RX_MAX_SLICES, - .row_width = CT_RULE_TCAM_RX_ROW_WIDTH, - .num_rows = CT_RULE_TCAM_RX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = CT_RULE_TCAM_RX_RESULT_SIZE, - }, - { /* APPS */ + { .max_slices = CT_RULE_TCAM_RX_MAX_SLICES, .row_width = CT_RULE_TCAM_RX_ROW_WIDTH, .num_rows = CT_RULE_TCAM_RX_NUM_ROWS, @@ -288,16 +229,7 @@ cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .max_entries = CT_RULE_TCAM_RX_MAX_ENTRIES, .result_size = CT_RULE_TCAM_RX_RESULT_SIZE, }, - { /* AFM */ - .max_slices = VEB_TCAM_RX_MAX_SLICES, - .row_width = VEB_TCAM_RX_ROW_WIDTH, - .num_rows = VEB_TCAM_RX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = VEB_TCAM_RX_RESULT_SIZE, - }, - { /* APPS */ + { .max_slices = VEB_TCAM_RX_MAX_SLICES, .row_width = VEB_TCAM_RX_ROW_WIDTH, .num_rows = VEB_TCAM_RX_NUM_ROWS, @@ -311,17 +243,7 @@ cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .max_entries = VEB_TCAM_RX_MAX_ENTRIES, .result_size = VEB_TCAM_RX_RESULT_SIZE, }, - { /* AFM */ - .max_slices = WC_TCAM_RX_MAX_SLICES, - .row_width = WC_TCAM_RX_ROW_WIDTH, - .num_rows = WC_TCAM_RX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = WC_TCAM_RX_RESULT_SIZE, - .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM, - }, - { /* APPS */ + { .max_slices = WC_TCAM_RX_MAX_SLICES, .row_width = WC_TCAM_RX_ROW_WIDTH, .num_rows = WC_TCAM_RX_NUM_ROWS, @@ -331,17 +253,7 @@ cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .result_size = WC_TCAM_RX_RESULT_SIZE, .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM, }, - { /* AFM */ - .max_slices = WC_TCAM_RX_MAX_SLICES, - .row_width = WC_TCAM_RX_ROW_WIDTH, - .num_rows = WC_TCAM_RX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = WC_TCAM_RX_RESULT_SIZE, - .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM, - }, - { /* APPS */ + { .max_slices = WC_TCAM_RX_MAX_SLICES, .row_width = WC_TCAM_RX_ROW_WIDTH, .num_rows = WC_TCAM_RX_NUM_ROWS, @@ -353,17 +265,7 @@ cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { }, }, { /* TX */ - { /* AFM */ - .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES, - .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH, - .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE, - .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH, - }, - { /* APPS */ + { .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES, .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH, .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS, @@ -373,17 +275,7 @@ cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE, .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH, }, - { /* AFM */ - .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES, - .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH, - .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE, - .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW, - }, - { /* APPS */ + { .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES, .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH, .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS, @@ -393,17 +285,7 @@ cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE, .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW, }, - { /* AFM */ - .max_slices = PROF_TCAM_TX_MAX_SLICES, - .row_width = PROF_TCAM_TX_ROW_WIDTH, - .num_rows = PROF_TCAM_TX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = PROF_TCAM_TX_RESULT_SIZE, - .hcapi_type = CFA_RESOURCE_TYPE_P4_PROF_TCAM, - }, - { /* APPS */ + { .max_slices = PROF_TCAM_TX_MAX_SLICES, .row_width = PROF_TCAM_TX_ROW_WIDTH, .num_rows = PROF_TCAM_TX_NUM_ROWS, @@ -413,17 +295,7 @@ cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .result_size = PROF_TCAM_TX_RESULT_SIZE, .hcapi_type = CFA_RESOURCE_TYPE_P4_PROF_TCAM, }, - { /* AFM */ - .max_slices = WC_TCAM_TX_MAX_SLICES, - .row_width = WC_TCAM_TX_ROW_WIDTH, - .num_rows = WC_TCAM_TX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = WC_TCAM_TX_RESULT_SIZE, - .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM, - }, - { /* APPS */ + { .max_slices = WC_TCAM_TX_MAX_SLICES, .row_width = WC_TCAM_TX_ROW_WIDTH, .num_rows = WC_TCAM_TX_NUM_ROWS, @@ -433,17 +305,7 @@ cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .result_size = WC_TCAM_TX_RESULT_SIZE, .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM, }, - { /* AFM */ - .max_slices = SP_TCAM_TX_MAX_SLICES, - .row_width = SP_TCAM_TX_ROW_WIDTH, - .num_rows = SP_TCAM_TX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = SP_TCAM_TX_RESULT_SIZE, - .hcapi_type = CFA_RESOURCE_TYPE_P4_SP_TCAM, - }, - { /* APPS */ + { .max_slices = SP_TCAM_TX_MAX_SLICES, .row_width = SP_TCAM_TX_ROW_WIDTH, .num_rows = SP_TCAM_TX_NUM_ROWS, @@ -453,16 +315,7 @@ cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .result_size = SP_TCAM_TX_RESULT_SIZE, .hcapi_type = CFA_RESOURCE_TYPE_P4_SP_TCAM, }, - { /* AFM */ - .max_slices = CT_RULE_TCAM_TX_MAX_SLICES, - .row_width = CT_RULE_TCAM_TX_ROW_WIDTH, - .num_rows = CT_RULE_TCAM_TX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = CT_RULE_TCAM_RX_RESULT_SIZE, - }, - { /* APPS */ + { .max_slices = CT_RULE_TCAM_TX_MAX_SLICES, .row_width = CT_RULE_TCAM_TX_ROW_WIDTH, .num_rows = CT_RULE_TCAM_TX_NUM_ROWS, @@ -476,16 +329,7 @@ cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .max_entries = CT_RULE_TCAM_TX_MAX_ENTRIES, .result_size = CT_RULE_TCAM_RX_RESULT_SIZE, }, - { /* AFM */ - .max_slices = VEB_TCAM_TX_MAX_SLICES, - .row_width = VEB_TCAM_TX_ROW_WIDTH, - .num_rows = VEB_TCAM_TX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = VEB_TCAM_RX_RESULT_SIZE, - }, - { /* APPS */ + { .max_slices = VEB_TCAM_TX_MAX_SLICES, .row_width = VEB_TCAM_TX_ROW_WIDTH, .num_rows = VEB_TCAM_TX_NUM_ROWS, @@ -495,17 +339,7 @@ cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .result_size = VEB_TCAM_RX_RESULT_SIZE, /* .hcapi_type = */ }, - { /* AFM */ - .max_slices = WC_TCAM_TX_MAX_SLICES, - .row_width = WC_TCAM_TX_ROW_WIDTH, - .num_rows = WC_TCAM_TX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = WC_TCAM_TX_RESULT_SIZE, - .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM, - }, - { /* APPS */ + { .max_slices = WC_TCAM_TX_MAX_SLICES, .row_width = WC_TCAM_TX_ROW_WIDTH, .num_rows = WC_TCAM_TX_NUM_ROWS, @@ -515,17 +349,7 @@ cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .result_size = WC_TCAM_TX_RESULT_SIZE, .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM, }, - { /* AFM */ - .max_slices = WC_TCAM_TX_MAX_SLICES, - .row_width = WC_TCAM_TX_ROW_WIDTH, - .num_rows = WC_TCAM_TX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = WC_TCAM_TX_RESULT_SIZE, - .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM, - }, - { /* APPS */ + { .max_slices = WC_TCAM_TX_MAX_SLICES, .row_width = WC_TCAM_TX_ROW_WIDTH, .num_rows = WC_TCAM_TX_NUM_ROWS, @@ -633,164 +457,92 @@ cfa_tcam_mgr_init_p4(struct tf *tfp) sizeof(tcam_mgr_data->cfa_tcam_mgr_tables)); tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_L2_CTXT_TCAM_RX[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_L2_CTXT_TCAM_RX[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_L2_CTXT_TCAM_TX[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_L2_CTXT_TCAM_TX[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_L2_CTXT_TCAM_RX[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_L2_CTXT_TCAM_RX[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_L2_CTXT_TCAM_TX[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_L2_CTXT_TCAM_TX[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_PROF_TCAM_RX[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_PROF_TCAM_RX[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_PROF_TCAM_TX[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_PROF_TCAM_TX[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_WC_TCAM_RX[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_WC_TCAM_RX[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_WC_TCAM_TX[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_WC_TCAM_TX[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_SP_TCAM_RX[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_SP_TCAM_RX[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_SP_TCAM_TX[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_SP_TCAM_TX[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_CT_RULE_TCAM_RX[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_CT_RULE_TCAM_RX[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_CT_RULE_TCAM_TX[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_CT_RULE_TCAM_TX[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_VEB_TCAM_RX[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_VEB_TCAM_RX[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_VEB_TCAM_TX[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_VEB_TCAM_TX[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_WC_TCAM_RX_HIGH[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_WC_TCAM_RX_HIGH[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_WC_TCAM_TX_HIGH[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_WC_TCAM_TX_HIGH[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_WC_TCAM_RX_LOW[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_WC_TCAM_RX_LOW[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_WC_TCAM_TX_LOW[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_WC_TCAM_TX_LOW[0]; diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c index aa322b4452..3edffab10f 100644 --- a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c @@ -165,17 +165,7 @@ struct cfa_tcam_mgr_table_rows_p58 { struct cfa_tcam_mgr_table_data cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { { /* RX */ - { /* High AFM */ - .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES, - .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH, - .num_rows = 0, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE, - .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH, - }, - { /* High APPS */ + { .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES, .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH, .num_rows = L2_CTXT_TCAM_RX_NUM_ROWS, @@ -185,17 +175,7 @@ cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE, .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH, }, - { /* Low AFM */ - .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES, - .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH, - .num_rows = 0, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE, - .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW, - }, - { /* Low APPS */ + { .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES, .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH, .num_rows = L2_CTXT_TCAM_RX_NUM_ROWS, @@ -205,17 +185,7 @@ cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE, .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW, }, - { /* AFM */ - .max_slices = PROF_TCAM_RX_MAX_SLICES, - .row_width = PROF_TCAM_RX_ROW_WIDTH, - .num_rows = 0, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = PROF_TCAM_RX_RESULT_SIZE, - .hcapi_type = CFA_RESOURCE_TYPE_P58_PROF_TCAM, - }, - { /* APPS */ + { .max_slices = PROF_TCAM_RX_MAX_SLICES, .row_width = PROF_TCAM_RX_ROW_WIDTH, .num_rows = PROF_TCAM_RX_NUM_ROWS, @@ -225,17 +195,7 @@ cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .result_size = PROF_TCAM_RX_RESULT_SIZE, .hcapi_type = CFA_RESOURCE_TYPE_P58_PROF_TCAM, }, - { /* AFM */ - .max_slices = WC_TCAM_RX_MAX_SLICES, - .row_width = WC_TCAM_RX_ROW_WIDTH, - .num_rows = WC_TCAM_RX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = WC_TCAM_RX_RESULT_SIZE, - .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM, - }, - { /* APPS */ + { .max_slices = WC_TCAM_RX_MAX_SLICES, .row_width = WC_TCAM_RX_ROW_WIDTH, .num_rows = WC_TCAM_RX_NUM_ROWS, @@ -245,16 +205,7 @@ cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .result_size = WC_TCAM_RX_RESULT_SIZE, .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM, }, - { /* AFM */ - .max_slices = SP_TCAM_RX_MAX_SLICES, - .row_width = SP_TCAM_RX_ROW_WIDTH, - .num_rows = 0, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = SP_TCAM_RX_RESULT_SIZE, - }, - { /* APPS */ + { .max_slices = SP_TCAM_RX_MAX_SLICES, .row_width = SP_TCAM_RX_ROW_WIDTH, .num_rows = SP_TCAM_RX_NUM_ROWS, @@ -263,16 +214,7 @@ cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .max_entries = SP_TCAM_RX_MAX_ENTRIES, .result_size = SP_TCAM_RX_RESULT_SIZE, }, - { /* AFM */ - .max_slices = CT_RULE_TCAM_RX_MAX_SLICES, - .row_width = CT_RULE_TCAM_RX_ROW_WIDTH, - .num_rows = CT_RULE_TCAM_RX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = CT_RULE_TCAM_RX_RESULT_SIZE, - }, - { /* APPS */ + { .max_slices = CT_RULE_TCAM_RX_MAX_SLICES, .row_width = CT_RULE_TCAM_RX_ROW_WIDTH, .num_rows = CT_RULE_TCAM_RX_NUM_ROWS, @@ -286,17 +228,7 @@ cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .max_entries = CT_RULE_TCAM_RX_MAX_ENTRIES, .result_size = CT_RULE_TCAM_RX_RESULT_SIZE, }, - { /* AFM */ - .max_slices = VEB_TCAM_RX_MAX_SLICES, - .row_width = VEB_TCAM_RX_ROW_WIDTH, - .num_rows = VEB_TCAM_RX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = VEB_TCAM_RX_RESULT_SIZE, - .hcapi_type = CFA_RESOURCE_TYPE_P58_VEB_TCAM, - }, - { /* APPS */ + { .max_slices = VEB_TCAM_RX_MAX_SLICES, .row_width = VEB_TCAM_RX_ROW_WIDTH, .num_rows = VEB_TCAM_RX_NUM_ROWS, @@ -310,17 +242,7 @@ cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .result_size = VEB_TCAM_RX_RESULT_SIZE, .hcapi_type = CFA_RESOURCE_TYPE_P58_VEB_TCAM, }, - { /* AFM */ - .max_slices = WC_TCAM_RX_MAX_SLICES, - .row_width = WC_TCAM_RX_ROW_WIDTH, - .num_rows = WC_TCAM_RX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = WC_TCAM_RX_RESULT_SIZE, - .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM, - }, - { /* APPS */ + { .max_slices = WC_TCAM_RX_MAX_SLICES, .row_width = WC_TCAM_RX_ROW_WIDTH, .num_rows = WC_TCAM_RX_NUM_ROWS, @@ -330,17 +252,7 @@ cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .result_size = WC_TCAM_RX_RESULT_SIZE, .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM, }, - { /* AFM */ - .max_slices = WC_TCAM_RX_MAX_SLICES, - .row_width = WC_TCAM_RX_ROW_WIDTH, - .num_rows = WC_TCAM_RX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = WC_TCAM_RX_RESULT_SIZE, - .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM, - }, - { /* APPS */ + { .max_slices = WC_TCAM_RX_MAX_SLICES, .row_width = WC_TCAM_RX_ROW_WIDTH, .num_rows = WC_TCAM_RX_NUM_ROWS, @@ -352,17 +264,7 @@ cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { }, }, { /* TX */ - { /* AFM */ - .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES, - .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH, - .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE, - .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH, - }, - { /* APPS */ + { .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES, .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH, .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS, @@ -372,17 +274,7 @@ cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE, .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH, }, - { /* AFM */ - .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES, - .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH, - .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE, - .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW, - }, - { /* APPS */ + { .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES, .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH, .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS, @@ -392,17 +284,7 @@ cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE, .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW, }, - { /* AFM */ - .max_slices = PROF_TCAM_TX_MAX_SLICES, - .row_width = PROF_TCAM_TX_ROW_WIDTH, - .num_rows = PROF_TCAM_TX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = PROF_TCAM_TX_RESULT_SIZE, - .hcapi_type = CFA_RESOURCE_TYPE_P58_PROF_TCAM, - }, - { /* APPS */ + { .max_slices = PROF_TCAM_TX_MAX_SLICES, .row_width = PROF_TCAM_TX_ROW_WIDTH, .num_rows = PROF_TCAM_TX_NUM_ROWS, @@ -412,17 +294,7 @@ cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .result_size = PROF_TCAM_TX_RESULT_SIZE, .hcapi_type = CFA_RESOURCE_TYPE_P58_PROF_TCAM, }, - { /* AFM */ - .max_slices = WC_TCAM_TX_MAX_SLICES, - .row_width = WC_TCAM_TX_ROW_WIDTH, - .num_rows = WC_TCAM_TX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = WC_TCAM_TX_RESULT_SIZE, - .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM, - }, - { /* APPS */ + { .max_slices = WC_TCAM_TX_MAX_SLICES, .row_width = WC_TCAM_TX_ROW_WIDTH, .num_rows = WC_TCAM_TX_NUM_ROWS, @@ -432,16 +304,7 @@ cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .result_size = WC_TCAM_TX_RESULT_SIZE, .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM, }, - { /* AFM */ - .max_slices = SP_TCAM_TX_MAX_SLICES, - .row_width = SP_TCAM_TX_ROW_WIDTH, - .num_rows = SP_TCAM_TX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = SP_TCAM_TX_RESULT_SIZE, - }, - { /* APPS */ + { .max_slices = SP_TCAM_TX_MAX_SLICES, .row_width = SP_TCAM_TX_ROW_WIDTH, .num_rows = SP_TCAM_TX_NUM_ROWS, @@ -450,16 +313,7 @@ cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .max_entries = SP_TCAM_TX_MAX_ENTRIES, .result_size = SP_TCAM_TX_RESULT_SIZE, }, - { /* AFM */ - .max_slices = CT_RULE_TCAM_TX_MAX_SLICES, - .row_width = CT_RULE_TCAM_TX_ROW_WIDTH, - .num_rows = CT_RULE_TCAM_TX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = CT_RULE_TCAM_RX_RESULT_SIZE, - }, - { /* APPS */ + { .max_slices = CT_RULE_TCAM_TX_MAX_SLICES, .row_width = CT_RULE_TCAM_TX_ROW_WIDTH, .num_rows = CT_RULE_TCAM_TX_NUM_ROWS, @@ -473,17 +327,7 @@ cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .max_entries = CT_RULE_TCAM_TX_MAX_ENTRIES, .result_size = CT_RULE_TCAM_RX_RESULT_SIZE, }, - { /* AFM */ - .max_slices = VEB_TCAM_TX_MAX_SLICES, - .row_width = VEB_TCAM_TX_ROW_WIDTH, - .num_rows = VEB_TCAM_TX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = VEB_TCAM_RX_RESULT_SIZE, - .hcapi_type = CFA_RESOURCE_TYPE_P58_VEB_TCAM, - }, - { /* APPS */ + { .max_slices = VEB_TCAM_TX_MAX_SLICES, .row_width = VEB_TCAM_TX_ROW_WIDTH, .num_rows = VEB_TCAM_TX_NUM_ROWS, @@ -493,17 +337,7 @@ cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .result_size = VEB_TCAM_RX_RESULT_SIZE, .hcapi_type = CFA_RESOURCE_TYPE_P58_VEB_TCAM, }, - { /* AFM */ - .max_slices = WC_TCAM_TX_MAX_SLICES, - .row_width = WC_TCAM_TX_ROW_WIDTH, - .num_rows = WC_TCAM_TX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = WC_TCAM_TX_RESULT_SIZE, - .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM, - }, - { /* APPS */ + { .max_slices = WC_TCAM_TX_MAX_SLICES, .row_width = WC_TCAM_TX_ROW_WIDTH, .num_rows = WC_TCAM_TX_NUM_ROWS, @@ -513,17 +347,7 @@ cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { .result_size = WC_TCAM_TX_RESULT_SIZE, .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM, }, - { /* AFM */ - .max_slices = WC_TCAM_TX_MAX_SLICES, - .row_width = WC_TCAM_TX_ROW_WIDTH, - .num_rows = WC_TCAM_TX_NUM_ROWS, - .start_row = 0, - .end_row = 0, - .max_entries = 0, - .result_size = WC_TCAM_TX_RESULT_SIZE, - .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM, - }, - { /* APPS */ + { .max_slices = WC_TCAM_TX_MAX_SLICES, .row_width = WC_TCAM_TX_ROW_WIDTH, .num_rows = WC_TCAM_TX_NUM_ROWS, @@ -624,164 +448,92 @@ cfa_tcam_mgr_init_p58(struct tf *tfp) sizeof(tcam_mgr_data->cfa_tcam_mgr_tables)); tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_L2_CTXT_TCAM_RX[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_L2_CTXT_TCAM_RX[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_L2_CTXT_TCAM_TX[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_L2_CTXT_TCAM_TX[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_L2_CTXT_TCAM_RX[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_L2_CTXT_TCAM_RX[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_L2_CTXT_TCAM_TX[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_L2_CTXT_TCAM_TX[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_PROF_TCAM_RX[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_PROF_TCAM_RX[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_PROF_TCAM_TX[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_PROF_TCAM_TX[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_WC_TCAM_RX[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_WC_TCAM_RX[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_WC_TCAM_TX[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_WC_TCAM_TX[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_SP_TCAM_RX[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_SP_TCAM_RX[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_SP_TCAM_TX[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_SP_TCAM_TX[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_CT_RULE_TCAM_RX[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_CT_RULE_TCAM_RX[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_CT_RULE_TCAM_TX[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_CT_RULE_TCAM_TX[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_VEB_TCAM_RX[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_VEB_TCAM_RX[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_VEB_TCAM_TX[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_VEB_TCAM_TX[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_WC_TCAM_RX_HIGH[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_WC_TCAM_RX_HIGH[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_WC_TCAM_TX_HIGH[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_WC_TCAM_TX_HIGH[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_WC_TCAM_RX_LOW[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_WC_TCAM_RX_LOW[0]; tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_AFM].tcam_rows = - (struct cfa_tcam_mgr_table_rows_0 *) - &table_rows->table_rows_WC_TCAM_TX_LOW[0]; - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS].tcam_rows = + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW].tcam_rows = (struct cfa_tcam_mgr_table_rows_0 *) &table_rows->table_rows_WC_TCAM_TX_LOW[0]; diff --git a/drivers/net/bnxt/tf_core/tf_resources.c b/drivers/net/bnxt/tf_core/tf_resources.c index d4fd3c2333..600149d77e 100644 --- a/drivers/net/bnxt/tf_core/tf_resources.c +++ b/drivers/net/bnxt/tf_core/tf_resources.c @@ -88,7 +88,7 @@ tf_tcam_mgr_row_entry_used(struct cfa_tcam_mgr_table_rows_0 *row, /* Initialize the resource usage buffer for WC-TCAM tables */ void tf_tcam_usage_init(struct tf *tfp) { - enum cfa_tcam_mgr_tbl_type type = CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS; + enum cfa_tcam_mgr_tbl_type type = CFA_TCAM_MGR_TBL_TYPE_WC_TCAM; struct cfa_tcam_mgr_table_data *table_data = NULL; struct tf_resc_wc_tcam_usage *usage_data = NULL; struct cfa_tcam_mgr_data *tcam_mgr_data; @@ -169,7 +169,7 @@ int tf_tcam_usage_update(struct tf *tfp, return -1; /* Support WC-TCAM APPs only */ - if (tcam_tbl_type != CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS) + if (tcam_tbl_type != CFA_TCAM_MGR_TBL_TYPE_WC_TCAM) return 0; resc_usage_control.buffer_dirty[dir] = 1; diff --git a/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c b/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c index 8c1e6d2e0f..8cf4d4d1fb 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c +++ b/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c @@ -17,23 +17,23 @@ */ static enum cfa_tcam_mgr_tbl_type tcam_types[TF_TCAM_TBL_TYPE_MAX] = { [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = - CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS, + CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH, [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = - CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS, + CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW, [TF_TCAM_TBL_TYPE_PROF_TCAM] = - CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS, + CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM, [TF_TCAM_TBL_TYPE_WC_TCAM] = - CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS, + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM, [TF_TCAM_TBL_TYPE_SP_TCAM] = - CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS, + CFA_TCAM_MGR_TBL_TYPE_SP_TCAM, [TF_TCAM_TBL_TYPE_CT_RULE_TCAM] = - CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS, + CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM, [TF_TCAM_TBL_TYPE_VEB_TCAM] = - CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS, + CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM, [TF_TCAM_TBL_TYPE_WC_TCAM_HIGH] = - CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS, + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH, [TF_TCAM_TBL_TYPE_WC_TCAM_LOW] = - CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS, + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW, }; static uint16_t hcapi_type[TF_TCAM_TBL_TYPE_MAX]; From patchwork Fri Aug 30 14:00:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: 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from session-based priority TCAM mgr Date: Fri, 30 Aug 2024 19:30:12 +0530 Message-Id: <20240830140049.1715230-11-sriharsha.basavapatna@broadcom.com> X-Mailer: git-send-email 2.39.0.189.g4dbebc36b0 In-Reply-To: <20240830140049.1715230-1-sriharsha.basavapatna@broadcom.com> References: <20240830140049.1715230-1-sriharsha.basavapatna@broadcom.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Randy Schacher Remove references to tx_tcam_supported and rx_tcam_supported logic which chooses between FW-based tcam resource allocation and driver-based tcam manager. Signed-off-by: Randy Schacher Reviewed-by: Peter Spreadborough Reviewed-by: Manish Kurup Reviewed-by: Farah Smith Signed-off-by: Sriharsha Basavapatna --- drivers/net/bnxt/tf_core/cfa_tcam_mgr.c | 46 ---- drivers/net/bnxt/tf_core/cfa_tcam_mgr.h | 29 -- drivers/net/bnxt/tf_core/tf_session.h | 5 - drivers/net/bnxt/tf_core/tf_tcam.c | 294 +-------------------- drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c | 28 -- drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.h | 6 - 6 files changed, 8 insertions(+), 400 deletions(-) diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c index 380e828da8..3875a0b934 100644 --- a/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c @@ -1079,52 +1079,6 @@ cfa_tcam_mgr_init(struct tf *tfp, enum cfa_tcam_mgr_device_type type, return 0; } -int -cfa_tcam_mgr_qcaps(struct tf *tfp __rte_unused, - struct cfa_tcam_mgr_qcaps_parms *parms) -{ - struct cfa_tcam_mgr_data *tcam_mgr_data; - struct tf_session *tfs; - unsigned int type; - int rc; - - CFA_TCAM_MGR_CHECK_PARMS2(tfp, parms); - - rc = tf_session_get_session_internal(tfp, &tfs); - if (rc) - return rc; - - tcam_mgr_data = tfs->tcam_mgr_handle; - if (!tcam_mgr_data) { - CFA_TCAM_MGR_LOG_0(ERR, "No TCAM data created for session.\n"); - return -CFA_TCAM_MGR_ERR_CODE(PERM); - } - - /* - * This code will indicate if TCAM Manager is managing a logical TCAM - * table or not. If not, then the physical TCAM will have to be - * accessed using the traditional methods. - */ - parms->rx_tcam_supported = 0; - parms->tx_tcam_supported = 0; - for (type = 0; type < CFA_TCAM_MGR_TBL_TYPE_MAX; type++) { - if (tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [type].max_entries > 0 && - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_RX] - [type].hcapi_type > 0) - parms->rx_tcam_supported |= - 1 << cfa_tcam_mgr_get_phys_table_type(type); - if (tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [type].max_entries > 0 && - tcam_mgr_data->cfa_tcam_mgr_tables[TF_DIR_TX] - [type].hcapi_type > 0) - parms->tx_tcam_supported |= - 1 << cfa_tcam_mgr_get_phys_table_type(type); - } - - return 0; -} - static int cfa_tcam_mgr_validate_tcam_cnt(struct tf *tfp __rte_unused, struct cfa_tcam_mgr_data *tcam_mgr_data, diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.h index 25654a8351..1cbd25e7d1 100644 --- a/drivers/net/bnxt/tf_core/cfa_tcam_mgr.h +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.h @@ -122,18 +122,6 @@ struct cfa_tcam_mgr_init_parms { uint32_t max_entries; }; -/** - * TCAM Manager initialization parameters - */ -struct cfa_tcam_mgr_qcaps_parms { - /** - * [out] Bitmasks. Set if TCAM Manager is managing a logical TCAM. - * Each bitmask is indexed by logical TCAM table ID. - */ - uint32_t rx_tcam_supported; - uint32_t tx_tcam_supported; -}; - /** * TCAM Manager configuration parameters */ @@ -369,23 +357,6 @@ cfa_tcam_mgr_init(struct tf *tfp, enum cfa_tcam_mgr_device_type type, int cfa_tcam_mgr_get_phys_table_type(enum cfa_tcam_mgr_tbl_type type); -/** - * Queries the capabilities of TCAM Manager. - * - * [in] context - * Pointer to context information - * - * [out] parms - * Pointer to parameters to be returned - * - * Returns - * - (0) if successful. - * - (<0) on failure. - */ -int -cfa_tcam_mgr_qcaps(struct tf *tfp __rte_unused, - struct cfa_tcam_mgr_qcaps_parms *parms); - /** * Initializes the TCAM module with the requested DBs. Must be * invoked as the first thing before any of the access functions. diff --git a/drivers/net/bnxt/tf_core/tf_session.h b/drivers/net/bnxt/tf_core/tf_session.h index d46d89e9e9..7668e9d0e0 100644 --- a/drivers/net/bnxt/tf_core/tf_session.h +++ b/drivers/net/bnxt/tf_core/tf_session.h @@ -174,11 +174,6 @@ struct tf_session { */ uint16_t wc_num_slices_per_row; - /** - * Indicates if TCAM is controlled by TCAM Manager - */ - int tcam_mgr_control[TF_DIR_MAX][TF_TCAM_TBL_TYPE_MAX]; - /** * TCAM Manager handle pointing to session based tcam memory */ diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c index fa8f60777d..e9bff62f88 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam.c +++ b/drivers/net/bnxt/tf_core/tf_tcam.c @@ -37,9 +37,6 @@ tf_tcam_bind(struct tf *tfp, struct tcam_rm_db *tcam_db; struct tfp_calloc_parms cparms; struct tf_resource_info resv_res[TF_DIR_MAX][TF_TCAM_TBL_TYPE_MAX]; - uint32_t rx_supported; - uint32_t tx_supported; - bool no_req = true; TF_CHECK_PARMS2(tfp, parms); @@ -167,39 +164,16 @@ tf_tcam_bind(struct tf *tfp, if (rc) return rc; - rc = tf_tcam_mgr_qcaps_msg(tfp, dev, - &rx_supported, &tx_supported); - if (rc) - return rc; - - for (t = 0; t < TF_TCAM_TBL_TYPE_MAX; t++) { - if (rx_supported & 1 << t) - tfs->tcam_mgr_control[TF_DIR_RX][t] = 1; - if (tx_supported & 1 << t) - tfs->tcam_mgr_control[TF_DIR_TX][t] = 1; - } - /* * Make a local copy of tcam_cnt with only resources not managed by TCAM * Manager requested. */ memcpy(&local_tcam_cnt, tcam_cnt, sizeof(local_tcam_cnt)); tcam_cnt = local_tcam_cnt; - for (d = 0; d < TF_DIR_MAX; d++) { - for (t = 0; t < TF_TCAM_TBL_TYPE_MAX; t++) { - /* If controlled by TCAM Manager */ - if (tfs->tcam_mgr_control[d][t]) - tcam_cnt[d].cnt[t] = 0; - else if (tcam_cnt[d].cnt[t] > 0) - no_req = false; - } - } - - /* If no resources left to request */ - if (no_req) - goto finished; + for (d = 0; d < TF_DIR_MAX; d++) + for (t = 0; t < TF_TCAM_TBL_TYPE_MAX; t++) + tcam_cnt[d].cnt[t] = 0; -finished: TFP_DRV_LOG(INFO, "TCAM - initialized\n"); @@ -274,14 +248,10 @@ int tf_tcam_alloc(struct tf *tfp, struct tf_tcam_alloc_parms *parms) { - int rc, i; + int rc; struct tf_session *tfs; struct tf_dev_info *dev; - struct tf_rm_allocate_parms aparms; uint16_t num_slices = 1; - uint32_t index; - struct tcam_rm_db *tcam_db; - void *tcam_db_ptr = NULL; TF_CHECK_PARMS2(tfp, parms); @@ -312,43 +282,7 @@ tf_tcam_alloc(struct tf *tfp, if (rc) return rc; - /* If TCAM controlled by TCAM Manager */ - if (tfs->tcam_mgr_control[parms->dir][parms->type]) - return tf_tcam_mgr_alloc_msg(tfp, dev, parms); - rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to get tcam_db from session, rc:%s\n", - strerror(-rc)); - return rc; - } - tcam_db = (struct tcam_rm_db *)tcam_db_ptr; - - /* - * For WC TCAM, number of slices could be 4, 2, 1 based on - * the key_size. For other TCAM, it is always 1 - */ - for (i = 0; i < num_slices; i++) { - memset(&aparms, 0, sizeof(aparms)); - aparms.rm_db = tcam_db->tcam_db[parms->dir]; - aparms.subtype = parms->type; - aparms.priority = parms->priority; - aparms.index = &index; - rc = tf_rm_allocate(&aparms); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Failed tcam, type:%d\n", - tf_dir_2_str(parms->dir), - parms->type); - return rc; - } - - /* return the start index of each row */ - if (i == 0) - parms->idx = index; - } - - return 0; + return tf_tcam_mgr_alloc_msg(tfp, dev, parms); } int @@ -358,14 +292,7 @@ tf_tcam_free(struct tf *tfp, int rc; struct tf_session *tfs; struct tf_dev_info *dev; - struct tf_rm_is_allocated_parms aparms; - struct tf_rm_free_parms fparms; - struct tf_rm_get_hcapi_parms hparms; uint16_t num_slices = 1; - int allocated = 0; - int i; - struct tcam_rm_db *tcam_db; - void *tcam_db_ptr = NULL; TF_CHECK_PARMS2(tfp, parms); @@ -396,91 +323,7 @@ tf_tcam_free(struct tf *tfp, if (rc) return rc; - /* If TCAM controlled by TCAM Manager */ - if (tfs->tcam_mgr_control[parms->dir][parms->type]) - /* - * If a session can have multiple references to an entry, check - * the reference count here before actually freeing the entry. - */ - return tf_tcam_mgr_free_msg(tfp, dev, parms); - - if (parms->idx % num_slices) { - TFP_DRV_LOG(ERR, - "%s: TCAM reserved resource is not multiple of %d\n", - tf_dir_2_str(parms->dir), - num_slices); - return -EINVAL; - } - - rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to get em_ext_db from session, rc:%s\n", - strerror(-rc)); - return rc; - } - tcam_db = (struct tcam_rm_db *)tcam_db_ptr; - - /* Check if element is in use */ - memset(&aparms, 0, sizeof(aparms)); - aparms.rm_db = tcam_db->tcam_db[parms->dir]; - aparms.subtype = parms->type; - aparms.index = parms->idx; - aparms.allocated = &allocated; - rc = tf_rm_is_allocated(&aparms); - if (rc) - return rc; - - if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { - TFP_DRV_LOG(ERR, - "%s: Entry already free, type:%d, index:%d\n", - tf_dir_2_str(parms->dir), - parms->type, - parms->idx); - return -EINVAL; - } - - for (i = 0; i < num_slices; i++) { - /* Free requested element */ - memset(&fparms, 0, sizeof(fparms)); - fparms.rm_db = tcam_db->tcam_db[parms->dir]; - fparms.subtype = parms->type; - fparms.index = parms->idx + i; - rc = tf_rm_free(&fparms); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Free failed, type:%d, index:%d\n", - tf_dir_2_str(parms->dir), - parms->type, - parms->idx); - return rc; - } - } - - /* Convert TF type to HCAPI RM type */ - memset(&hparms, 0, sizeof(hparms)); - - hparms.rm_db = tcam_db->tcam_db[parms->dir]; - hparms.subtype = parms->type; - hparms.hcapi_type = &parms->hcapi_type; - - rc = tf_rm_get_hcapi_type(&hparms); - if (rc) - return rc; - - rc = tf_msg_tcam_entry_free(tfp, dev, parms); - if (rc) { - /* Log error */ - TFP_DRV_LOG(ERR, - "%s: %s: Entry %d free failed, rc:%s\n", - tf_dir_2_str(parms->dir), - tf_tcam_tbl_2_str(parms->type), - parms->idx, - strerror(-rc)); - return rc; - } - - return 0; + return tf_tcam_mgr_free_msg(tfp, dev, parms); } int @@ -490,12 +333,7 @@ tf_tcam_set(struct tf *tfp __rte_unused, int rc; struct tf_session *tfs; struct tf_dev_info *dev; - struct tf_rm_is_allocated_parms aparms; - struct tf_rm_get_hcapi_parms hparms; uint16_t num_slice_per_row = 1; - int allocated = 0; - struct tcam_rm_db *tcam_db; - void *tcam_db_ptr = NULL; TF_CHECK_PARMS2(tfp, parms); @@ -526,62 +364,7 @@ tf_tcam_set(struct tf *tfp __rte_unused, if (rc) return rc; - /* If TCAM controlled by TCAM Manager */ - if (tfs->tcam_mgr_control[parms->dir][parms->type]) - return tf_tcam_mgr_set_msg(tfp, dev, parms); - - rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to get em_ext_db from session, rc:%s\n", - strerror(-rc)); - return rc; - } - tcam_db = (struct tcam_rm_db *)tcam_db_ptr; - - /* Check if element is in use */ - memset(&aparms, 0, sizeof(aparms)); - - aparms.rm_db = tcam_db->tcam_db[parms->dir]; - aparms.subtype = parms->type; - aparms.index = parms->idx; - aparms.allocated = &allocated; - rc = tf_rm_is_allocated(&aparms); - if (rc) - return rc; - - if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { - TFP_DRV_LOG(ERR, - "%s: Entry is not allocated, type:%d, index:%d\n", - tf_dir_2_str(parms->dir), - parms->type, - parms->idx); - return -EINVAL; - } - - /* Convert TF type to HCAPI RM type */ - memset(&hparms, 0, sizeof(hparms)); - - hparms.rm_db = tcam_db->tcam_db[parms->dir]; - hparms.subtype = parms->type; - hparms.hcapi_type = &parms->hcapi_type; - - rc = tf_rm_get_hcapi_type(&hparms); - if (rc) - return rc; - - rc = tf_msg_tcam_entry_set(tfp, dev, parms); - if (rc) { - /* Log error */ - TFP_DRV_LOG(ERR, - "%s: %s: Entry %d set failed, rc:%s", - tf_dir_2_str(parms->dir), - tf_tcam_tbl_2_str(parms->type), - parms->idx, - strerror(-rc)); - return rc; - } - return 0; + return tf_tcam_mgr_set_msg(tfp, dev, parms); } int @@ -591,11 +374,6 @@ tf_tcam_get(struct tf *tfp __rte_unused, int rc; struct tf_session *tfs; struct tf_dev_info *dev; - struct tf_rm_is_allocated_parms aparms; - struct tf_rm_get_hcapi_parms hparms; - int allocated = 0; - struct tcam_rm_db *tcam_db; - void *tcam_db_ptr = NULL; TF_CHECK_PARMS2(tfp, parms); @@ -609,63 +387,7 @@ tf_tcam_get(struct tf *tfp __rte_unused, if (rc) return rc; - /* If TCAM controlled by TCAM Manager */ - if (tfs->tcam_mgr_control[parms->dir][parms->type]) - return tf_tcam_mgr_get_msg(tfp, dev, parms); - - rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to get em_ext_db from session, rc:%s\n", - strerror(-rc)); - return rc; - } - tcam_db = (struct tcam_rm_db *)tcam_db_ptr; - - /* Check if element is in use */ - memset(&aparms, 0, sizeof(aparms)); - - aparms.rm_db = tcam_db->tcam_db[parms->dir]; - aparms.subtype = parms->type; - aparms.index = parms->idx; - aparms.allocated = &allocated; - rc = tf_rm_is_allocated(&aparms); - if (rc) - return rc; - - if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { - TFP_DRV_LOG(ERR, - "%s: Entry is not allocated, type:%d, index:%d\n", - tf_dir_2_str(parms->dir), - parms->type, - parms->idx); - return -EINVAL; - } - - /* Convert TF type to HCAPI RM type */ - memset(&hparms, 0, sizeof(hparms)); - - hparms.rm_db = tcam_db->tcam_db[parms->dir]; - hparms.subtype = parms->type; - hparms.hcapi_type = &parms->hcapi_type; - - rc = tf_rm_get_hcapi_type(&hparms); - if (rc) - return rc; - - rc = tf_msg_tcam_entry_get(tfp, dev, parms); - if (rc) { - /* Log error */ - TFP_DRV_LOG(ERR, - "%s: %s: Entry %d set failed, rc:%s", - tf_dir_2_str(parms->dir), - tf_tcam_tbl_2_str(parms->type), - parms->idx, - strerror(-rc)); - return rc; - } - - return 0; + return tf_tcam_mgr_get_msg(tfp, dev, parms); } int diff --git a/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c b/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c index 8cf4d4d1fb..9e5d39fde5 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c +++ b/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c @@ -38,34 +38,6 @@ static enum cfa_tcam_mgr_tbl_type tcam_types[TF_TCAM_TBL_TYPE_MAX] = { static uint16_t hcapi_type[TF_TCAM_TBL_TYPE_MAX]; -/* - * This is the glue between the core tf_tcam and the TCAM manager. It is - * intended to abstract out the location of the TCAM manager so that the core - * code will be the same if the TCAM manager is in the core or in firmware. - * - * If the TCAM manager is in the core, then this file will just translate to - * TCAM manager APIs. If TCAM manager is in firmware, then this file will cause - * messages to be sent (except for bind and unbind). - */ - -int -tf_tcam_mgr_qcaps_msg(struct tf *tfp, - struct tf_dev_info *dev __rte_unused, - uint32_t *rx_tcam_supported, - uint32_t *tx_tcam_supported) -{ - struct cfa_tcam_mgr_qcaps_parms mgr_parms; - int rc; - - memset(&mgr_parms, 0, sizeof(mgr_parms)); - rc = cfa_tcam_mgr_qcaps(tfp, &mgr_parms); - if (rc >= 0) { - *rx_tcam_supported = mgr_parms.rx_tcam_supported; - *tx_tcam_supported = mgr_parms.tx_tcam_supported; - } - return rc; -} - int tf_tcam_mgr_bind_msg(struct tf *tfp, struct tf_dev_info *dev __rte_unused, diff --git a/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.h b/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.h index 8a8d136f5e..eb4617049a 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.h +++ b/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.h @@ -9,12 +9,6 @@ #include "tf_tcam.h" #include "tf_rm.h" -int -tf_tcam_mgr_qcaps_msg(struct tf *tfp, - struct tf_dev_info *dev __rte_unused, - uint32_t *rx_tcam_supported, - uint32_t *tx_tcam_supported); - int tf_tcam_mgr_bind_msg(struct tf *tfp, struct tf_dev_info *dev, From patchwork Fri Aug 30 14:00:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sriharsha Basavapatna X-Patchwork-Id: 143499 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7B1AA458A9; Fri, 30 Aug 2024 16:03:22 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EA34C42EE2; Fri, 30 Aug 2024 16:03:21 +0200 (CEST) Received: from mail-pf1-f179.google.com (mail-pf1-f179.google.com [209.85.210.179]) by mails.dpdk.org (Postfix) with ESMTP id 8C9C842E95 for ; Fri, 30 Aug 2024 15:51:50 +0200 (CEST) Received: by mail-pf1-f179.google.com with SMTP id d2e1a72fcca58-7141d7b270dso1510970b3a.2 for ; Fri, 30 Aug 2024 06:51:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1725025909; x=1725630709; darn=dpdk.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KfsHuElOuoDbbkKc7k0wNNTHSCFc9fP3TjYhmyKHCqQ=; b=WojvDkLJqQ6YcgY9Ix5obobLrJwLHt0tERAwUQBYP27jQUgFFDFfjFiC2w8EhyZhs0 O1N8ktMu8skcfMK1SmUwlAQYPbraSpT+Wdlt/8I7ElWK06gn+BCQrnCQhqzNerNywYwl SkLmAu5EmX4bpu+MHPDoCoL4ElDzBui+kOw4A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1725025909; x=1725630709; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KfsHuElOuoDbbkKc7k0wNNTHSCFc9fP3TjYhmyKHCqQ=; b=LUn1xJcPABl91y/hoz6oIlCvC65+4hYh0971wJdgAn/u1ESa0+PD104gIpOj6EOB4k RWtjw38HGQXQ/Sj3XL4sI+b4Muf7ZNp/JVQ8/v8bQ/V+VFXLo0Hgqv9KRzBRjUParTu1 7OGo1uEcs1PUgCD5lIyvz2vNTDqNwYocpNvaE2hNJJZyVjpd3AEgU3sSNEZQXQqk/hES xAyqo/V5CnhtdEFAZj8nnsRMvXC9QsMmkuV/Yk3x71L1xP6yZP+OMODpdr4doQWuAK5E H+KaZBpJ14YpA2zp/gaT+t/8nXLujWA9u8VljcsNxYrdY7Ld2cGr24epMfjTMuxPHbdn YLHQ== X-Gm-Message-State: AOJu0Yyk87+MM9FbOarXQADdUWj4iTTm6PAh1glTeWxvUOvQI2XKf5OK 9aKqCqdUYLGJMU76498Is6HqDGUwxaCOAZWuZrog+cuWtjJ3naL2Z12oJeeCJFbx1LfKKPWJyYD oVDBeEguU/gcChB2APcrV7mB8AgnJe4yFac1jevvzppx9jGEDhUN3arY6ueRrFPl+ZYJ+T62naH VY1BEEP34VaDZBrjjnCRj5ia7jzdGdNmH5RxeKV+N/mYF6 X-Google-Smtp-Source: AGHT+IEepITSRLDbDsWlPfxwkbyijFHYAeNZsj4eliJObjCnEddoWNt4dewkW/c//ki7SZXyYj/CtA== X-Received: by 2002:a05:6a21:6f83:b0:1c0:f2a5:c8dc with SMTP id adf61e73a8af0-1cce10fe2edmr5797805637.50.1725025904533; Fri, 30 Aug 2024 06:51:44 -0700 (PDT) Received: from dhcp-10-123-154-23.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-205155658dfsm27067145ad.297.2024.08.30.06.51.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Aug 2024 06:51:42 -0700 (PDT) From: Sriharsha Basavapatna To: dev@dpdk.org Cc: Farah Smith , Jay Ding , Peter Spreadborough , Shahaji Bhosle , Sriharsha Basavapatna Subject: [PATCH 11/47] net/bnxt: tfc: support tf-core for Thor2 Date: Fri, 30 Aug 2024 19:30:13 +0530 Message-Id: <20240830140049.1715230-12-sriharsha.basavapatna@broadcom.com> X-Mailer: git-send-email 2.39.0.189.g4dbebc36b0 In-Reply-To: <20240830140049.1715230-1-sriharsha.basavapatna@broadcom.com> References: <20240830140049.1715230-1-sriharsha.basavapatna@broadcom.com> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 30 Aug 2024 16:03:19 +0200 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Farah Smith This patch introduces tf-core (tfc) functionality for Thor2 chips. The new code is added under ~/tf_core/v3/ and ~/hcapi/cfa_v3/. There are some dependent changes needed in some of the core bnxt pmd files. Those also have been updated accordingly. TruFlow(TF) is the software library that exposes CFA HW resources to upper layer protocols or applications. This patch series implements the tfc library as a part of bnxt_en driver so that upper layer APIs such as flow add can access the hardware. The tfc is designed to expose the CFA HW tables to the TF ULP via a set of TF APIs. The TF APIs are the gateway to the CFA HW resources. Most API calls will result in a call to the TF FW to carry out the actual HW programming. The APIs support Thor2. As a first step, the tfc object is opened during which memory is allocated and initialized to manage memory associated with table scopes and store the session. Table scopes are used to manage host memory used for EM (exact match) lookups and actions. Sessions are created by the application and other hardware resources can be allocated associated with the session or associated with a function. HCAPI (hardware control APIs) consist of APIs supporting MPC (midpath control) messages sent to the CFA to access table scope memory. Additional table scope management tools Table scope instance manager (TIM) and Table scope pool manager (TPM) reside within HCAPI to support VFs requiring table scope memory. The HWRMs are implemented in tfc_msg.c and they are grouped as shown below: Session management: HWRM_TFC_SESSION_ID_ALLOC HWRM_TFC_SESSION_FID_ADD HWRM_TFC_SESSION_FID_REM Table Scope management: HWRM_TFC_TBL_SCOPE_QCAPS HWRM_TFC_TBL_SCOPE_ID_ALLOC HWRM_TFC_TBL_SCOPE_CONFIG HWRM_TFC_TBL_SCOPE_DECONFIG HWRM_TFC_TBL_SCOPE_FID_ADD HWRM_TFC_TBL_SCOPE_FID_REM HWRM_TFC_TBL_SCOPE_POOL_ALLOC HWRM_TFC_TBL_SCOPE_POOL_FREE HWRM_TFC_TBL_SCOPE_CONFIG_GET HW/Table Management: HWRM_TFC_IDENT_ALLOC HWRM_TFC_IDENT_FREE HWRM_TFC_IDX_TBL_ALLOC HWRM_TFC_IDX_TBL_ALLOC_SET HWRM_TFC_IDX_TBL_SET HWRM_TFC_IDX_TBL_GET HWRM_TFC_IDX_TBL_FREE HWRM_TFC_GLOBAL_ID_ALLOC HWRM_TFC_TCAM_SET HWRM_TFC_TCAM_GET HWRM_TFC_TCAM_ALLOC HWRM_TFC_TCAM_ALLOC_SET HWRM_TFC_TCAM_FREE HWRM_TFC_IF_TBL_SET HWRM_TFC_IF_TBL_GET HWRM_TFC_RESC_USAGE_QUERY This patch also includes the required header files to support these APIs, listed below. TF-Core APIs: tfc.h TF HWRM messages: tfc_msg.h, tfc_vf2pf_msg.h TF Object: tfo.h TF Table Scope: tfc_em.h, tfc_action_handle.h, tfc_flow_handle.h, tfc_cpm.h, cfa_tim.h, cfa_tim_priv.h, cfa_tpm.h, cfa_tpm_priv.h TF general support: tfc_debug.h tfc_priv.h tfc_util.h CFA HW files: cfa_bld_defs.h, cfa_resource_types.h, cfa_bld_p70_defs.h, cfa_bld_p70_field_ids.h, cfa_bld_p70_fkb_keycodes.h cfa_bld_p70_mpc.h, cfa_p70.h cfa_p70_hw.h cfa_p70_mpc_structs.h, cfa_p70_mpc_structs.h, cfa_bld_mpc_field_ids.h, cfa_bld.h, cfa_bld_mpcops.h Signed-off-by: Farah Smith Signed-off-by: Jay Ding Signed-off-by: Peter Spreadborough Reviewed-by: Shahaji Bhosle Signed-off-by: Sriharsha Basavapatna --- drivers/net/bnxt/bnxt.h | 3 + drivers/net/bnxt/bnxt_cpr.h | 24 +- drivers/net/bnxt/bnxt_hwrm.c | 83 +- drivers/net/bnxt/bnxt_hwrm.h | 9 + drivers/net/bnxt/bnxt_mpc.c | 853 + drivers/net/bnxt/bnxt_mpc.h | 117 + drivers/net/bnxt/bnxt_ring.c | 19 +- drivers/net/bnxt/bnxt_ring.h | 54 +- drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h | 15 +- drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h | 576 +- drivers/net/bnxt/hcapi/cfa_v3/CMakeLists.txt | 92 + .../bnxt/hcapi/cfa_v3/bld/host/cfa_bld_mpc.c | 42 + .../hcapi/cfa_v3/bld/include/cfa_bld_defs.h | 578 + .../hcapi/cfa_v3/bld/include/host/cfa_bld.h | 524 + .../cfa_v3/bld/include/host/cfa_bld_devops.h | 297 + .../bld/include/host/cfa_bld_field_ids.h | 1542 + .../bld/include/host/cfa_bld_mpc_field_ids.h | 1286 + .../cfa_v3/bld/include/host/cfa_bld_mpcops.h | 598 + .../cfa_v3/bld/include/p70/cfa_bld_p70_defs.h | 543 + .../bld/include/p70/cfa_bld_p70_field_ids.h | 1542 + .../cfa_v3/bld/include/p70/cfa_bld_p70_mpc.h | 548 + .../hcapi/cfa_v3/bld/include/p70/cfa_p70.h | 164 + .../hcapi/cfa_v3/bld/include/p70/cfa_p70_hw.h | 4286 ++ .../bld/include/p70/cfa_p70_mpc_structs.h | 1496 + .../hcapi/cfa_v3/bld/p70/cfa_bld_p70_mpc.c | 927 + .../cfa_v3/bld/p70/cfa_bld_p70_mpc_defs.h | 51 + .../p70/host/cfa_bld_p70_host_mpc_wrapper.c | 1127 + .../p70/host/cfa_bld_p70_host_mpc_wrapper.h | 83 + .../cfa_v3/bld/p70/host/cfa_bld_p70_mpcops.c | 56 + .../cfa_v3/bld/p70/host/cfa_bld_p70_mpcops.h | 22 + .../bld/p70/host/cfa_p70_mpc_field_ids.h | 1177 + .../bld/p70/host/cfa_p70_mpc_field_mapping.h | 775 + .../bnxt/hcapi/cfa_v3/include/cfa_resources.h | 185 + .../net/bnxt/hcapi/cfa_v3/include/cfa_trace.h | 273 + .../net/bnxt/hcapi/cfa_v3/include/cfa_types.h | 122 + .../net/bnxt/hcapi/cfa_v3/include/cfa_util.h | 44 + .../include/platform/dpdk/cfa_debug_defs.h | 52 + .../net/bnxt/hcapi/cfa_v3/include/sys_util.h | 101 + drivers/net/bnxt/hcapi/cfa_v3/meson.build | 36 + .../net/bnxt/hcapi/cfa_v3/mm/CMakeLists.txt | 42 + drivers/net/bnxt/hcapi/cfa_v3/mm/cfa_mm.c | 624 + .../net/bnxt/hcapi/cfa_v3/mm/cfa_mm_priv.h | 92 + .../net/bnxt/hcapi/cfa_v3/mm/include/cfa_mm.h | 173 + .../net/bnxt/hcapi/cfa_v3/tim/CMakeLists.txt | 43 + drivers/net/bnxt/hcapi/cfa_v3/tim/cfa_tim.c | 124 + .../net/bnxt/hcapi/cfa_v3/tim/cfa_tim_priv.h | 85 + .../bnxt/hcapi/cfa_v3/tim/include/cfa_tim.h | 133 + .../net/bnxt/hcapi/cfa_v3/tpm/CMakeLists.txt | 44 + drivers/net/bnxt/hcapi/cfa_v3/tpm/cfa_tpm.c | 273 + .../net/bnxt/hcapi/cfa_v3/tpm/cfa_tpm_priv.h | 47 + .../bnxt/hcapi/cfa_v3/tpm/include/cfa_tpm.h | 215 + drivers/net/bnxt/hsi_struct_def_dpdk.h | 54800 +++++++++------- drivers/net/bnxt/meson.build | 5 +- drivers/net/bnxt/tf_core/v3/meson.build | 34 + drivers/net/bnxt/tf_core/v3/tfc.h | 1527 + drivers/net/bnxt/tf_core/v3/tfc_act.c | 843 + .../net/bnxt/tf_core/v3/tfc_action_handle.h | 68 + drivers/net/bnxt/tf_core/v3/tfc_cpm.c | 439 + drivers/net/bnxt/tf_core/v3/tfc_cpm.h | 214 + drivers/net/bnxt/tf_core/v3/tfc_debug.h | 28 + drivers/net/bnxt/tf_core/v3/tfc_em.c | 1053 + drivers/net/bnxt/tf_core/v3/tfc_em.h | 174 + drivers/net/bnxt/tf_core/v3/tfc_flow_handle.h | 81 + drivers/net/bnxt/tf_core/v3/tfc_global_id.c | 58 + drivers/net/bnxt/tf_core/v3/tfc_ident.c | 83 + drivers/net/bnxt/tf_core/v3/tfc_idx_tbl.c | 328 + drivers/net/bnxt/tf_core/v3/tfc_if_tbl.c | 133 + drivers/net/bnxt/tf_core/v3/tfc_init.c | 69 + drivers/net/bnxt/tf_core/v3/tfc_mpc_table.c | 1206 + drivers/net/bnxt/tf_core/v3/tfc_msg.c | 1202 + drivers/net/bnxt/tf_core/v3/tfc_msg.h | 164 + drivers/net/bnxt/tf_core/v3/tfc_priv.c | 124 + drivers/net/bnxt/tf_core/v3/tfc_priv.h | 78 + drivers/net/bnxt/tf_core/v3/tfc_resources.c | 99 + drivers/net/bnxt/tf_core/v3/tfc_resources.h | 15 + drivers/net/bnxt/tf_core/v3/tfc_session.c | 155 + drivers/net/bnxt/tf_core/v3/tfc_tbl_scope.c | 2069 + drivers/net/bnxt/tf_core/v3/tfc_tcam.c | 299 + drivers/net/bnxt/tf_core/v3/tfc_util.c | 230 + drivers/net/bnxt/tf_core/v3/tfc_util.h | 123 + drivers/net/bnxt/tf_core/v3/tfc_vf2pf_msg.c | 360 + drivers/net/bnxt/tf_core/v3/tfc_vf2pf_msg.h | 220 + drivers/net/bnxt/tf_core/v3/tfo.c | 575 + drivers/net/bnxt/tf_core/v3/tfo.h | 429 + drivers/net/bnxt/tf_ulp/bnxt_ulp_tfc.h | 74 + 85 files changed, 65315 insertions(+), 24261 deletions(-) create mode 100644 drivers/net/bnxt/bnxt_mpc.c create mode 100644 drivers/net/bnxt/bnxt_mpc.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/CMakeLists.txt create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/host/cfa_bld_mpc.c create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/include/cfa_bld_defs.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_devops.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_field_ids.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_mpc_field_ids.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_mpcops.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_bld_p70_defs.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_bld_p70_field_ids.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_bld_p70_mpc.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_p70.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_p70_hw.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_p70_mpc_structs.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/p70/cfa_bld_p70_mpc.c create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/p70/cfa_bld_p70_mpc_defs.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_bld_p70_host_mpc_wrapper.c create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_bld_p70_host_mpc_wrapper.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_bld_p70_mpcops.c create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_bld_p70_mpcops.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_p70_mpc_field_ids.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_p70_mpc_field_mapping.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/include/cfa_resources.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/include/cfa_trace.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/include/cfa_types.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/include/cfa_util.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/include/platform/dpdk/cfa_debug_defs.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/include/sys_util.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/meson.build create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/mm/CMakeLists.txt create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/mm/cfa_mm.c create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/mm/cfa_mm_priv.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/mm/include/cfa_mm.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/tim/CMakeLists.txt create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/tim/cfa_tim.c create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/tim/cfa_tim_priv.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/tim/include/cfa_tim.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/tpm/CMakeLists.txt create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/tpm/cfa_tpm.c create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/tpm/cfa_tpm_priv.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/tpm/include/cfa_tpm.h create mode 100644 drivers/net/bnxt/tf_core/v3/meson.build create mode 100644 drivers/net/bnxt/tf_core/v3/tfc.h create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_act.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_action_handle.h create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_cpm.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_cpm.h create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_debug.h create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_em.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_em.h create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_flow_handle.h create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_global_id.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_ident.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_idx_tbl.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_if_tbl.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_init.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_mpc_table.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_msg.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_msg.h create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_priv.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_priv.h create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_resources.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_resources.h create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_session.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_tbl_scope.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_tcam.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_util.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_util.h create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_vf2pf_msg.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_vf2pf_msg.h create mode 100644 drivers/net/bnxt/tf_core/v3/tfo.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfo.h create mode 100644 drivers/net/bnxt/tf_ulp/bnxt_ulp_tfc.h diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index aaa7ea00cc..00123e51ac 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -24,8 +24,10 @@ #include "bnxt_util.h" #include "tf_core.h" +#include "tfc.h" #include "bnxt_ulp.h" #include "bnxt_tf_common.h" +#include "bnxt_mpc.h" #include "bnxt_vnic.h" /* Vendor ID */ @@ -1034,6 +1036,7 @@ struct bnxt { struct bnxt_ring_stats_ext *prev_tx_ring_stats_ext; struct bnxt_vnic_queue_db vnic_queue_db; + struct bnxt_mpc *mpc; #define BNXT_MAX_MC_ADDRS ((bp)->max_mcast_addr) struct rte_ether_addr *mcast_addr_list; rte_iova_t mc_list_dma_addr; diff --git a/drivers/net/bnxt/bnxt_cpr.h b/drivers/net/bnxt/bnxt_cpr.h index 43f06fdc92..d97e0befd5 100644 --- a/drivers/net/bnxt/bnxt_cpr.h +++ b/drivers/net/bnxt/bnxt_cpr.h @@ -8,6 +8,7 @@ #include #include +#include #include "hsi_struct_def_dpdk.h" struct bnxt_db_info; @@ -15,6 +16,10 @@ struct bnxt_db_info; #define CMP_TYPE(cmp) \ (((struct cmpl_base *)cmp)->type & CMPL_BASE_TYPE_MASK) +#define CMPL_VALID(cmp, v) \ + (!!(rte_le_to_cpu_32(((struct cmpl_base *)(cmp))->info3_v) & \ + CMPL_BASE_V) == !(v)) + /* Get completion length from completion type, in 16-byte units. */ #define CMP_LEN(cmp_type) (((cmp_type) & 1) + 1) @@ -28,6 +33,14 @@ struct bnxt_db_info; #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID) #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS) +#define NEXT_CMPL(cpr, idx, v, inc) do { \ + (idx) += (inc); \ + if (unlikely((idx) >= (cpr)->cp_ring_struct->ring_size)) { \ + (v) = !(v); \ + (idx) = 0; \ + } \ +} while (0) + #define B_CP_DB_REARM(cpr, raw_cons) \ rte_write32((DB_CP_REARM_FLAGS | \ DB_RING_IDX(&((cpr)->cp_db), raw_cons)), \ @@ -74,6 +87,8 @@ struct bnxt_cp_ring_info { uint32_t hw_stats_ctx_id; struct bnxt_ring *cp_ring_struct; + bool valid; + uint32_t epoch; }; #define RX_CMP_L2_ERRORS \ @@ -104,10 +119,13 @@ bool bnxt_is_recovery_enabled(struct bnxt *bp); bool bnxt_is_primary_func(struct bnxt *bp); void bnxt_stop_rxtx(struct rte_eth_dev *eth_dev); +#if (RTE_VERSION_NUM(21, 8, 0, 0) < RTE_VERSION) +void bnxt_start_rxtx(struct rte_eth_dev *eth_dev); +#endif /** * Check validity of a completion ring entry. If the entry is valid, include a - * C11 rte_memory_order_acquire fence to ensure that subsequent loads of fields in the + * C11 __ATOMIC_ACQUIRE fence to ensure that subsequent loads of fields in the * completion are not hoisted by the compiler or by the CPU to come before the * loading of the "valid" field. * @@ -124,13 +142,13 @@ void bnxt_stop_rxtx(struct rte_eth_dev *eth_dev); static __rte_always_inline bool bnxt_cpr_cmp_valid(const void *cmpl, uint32_t raw_cons, uint32_t ring_size) { - const struct cmpl_base *c = cmpl; + const struct cmpl_base *c = (const struct cmpl_base *)cmpl; bool expected, valid; expected = !(raw_cons & ring_size); valid = !!(rte_le_to_cpu_32(c->info3_v) & CMPL_BASE_V); if (valid == expected) { - rte_atomic_thread_fence(rte_memory_order_acquire); + rte_atomic_thread_fence(__ATOMIC_ACQUIRE); return true; } return false; diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index fc142672f6..4e62dbbcca 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -2370,7 +2370,7 @@ int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) return rc; } -static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) +int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) { int rc; struct hwrm_stat_ctx_free_input req = {.req_type = 0 }; @@ -7449,6 +7449,49 @@ int bnxt_hwrm_config_host_mtu(struct bnxt *bp) return rc; } +int bnxt_hwrm_func_cfg_mpc(struct bnxt *bp, uint8_t mpc_chnls_msk, bool enable) +{ + struct hwrm_func_cfg_input req = {0}; + struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr; + int rc; + uint16_t mpc_chnls = 0; + + HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB); + req.fid = rte_cpu_to_le_16(0xffff); + req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MPC_CHNLS); + if (enable) { + if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_TCE)) + mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_ENABLE; + if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_RCE)) + mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_ENABLE; + if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_TE_CFA)) + mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_ENABLE; + if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_RE_CFA)) + mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_ENABLE; + if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_PRIMATE)) + mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_ENABLE; + } else { + if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_TCE)) + mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_DISABLE; + if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_RCE)) + mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_DISABLE; + if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_TE_CFA)) + mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_DISABLE; + if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_RE_CFA)) + mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_DISABLE; + if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_PRIMATE)) + mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_DISABLE; + } + req.mpc_chnls = rte_cpu_to_le_16(mpc_chnls); + + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); + + HWRM_CHECK_RESULT(); + HWRM_UNLOCK(); + + return rc; +} + int bnxt_vnic_rss_clear_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic) { @@ -7471,3 +7514,41 @@ bnxt_vnic_rss_clear_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic) return rc; } + +int bnxt_hwrm_tf_oem_cmd(struct bnxt *bp, + uint32_t *in, + uint16_t in_len, + uint32_t *out, + uint16_t out_len) +{ + struct hwrm_oem_cmd_output *resp = bp->hwrm_cmd_resp_addr; + struct hwrm_oem_cmd_input req = {0}; + int rc = 0; + + if (!BNXT_VF(bp)) { + PMD_DRV_LOG(DEBUG, "Not a VF. Command not supported\n"); + return -ENOTSUP; + } + + HWRM_PREP(&req, HWRM_OEM_CMD, BNXT_USE_CHIMP_MB); + + req.oem_id = rte_cpu_to_le_32(0x14e4); + req.naming_authority = + HWRM_OEM_CMD_INPUT_NAMING_AUTHORITY_PCI_SIG; + req.message_family = + HWRM_OEM_CMD_INPUT_MESSAGE_FAMILY_TRUFLOW; + memcpy(req.oem_data, in, in_len); + + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); + + HWRM_CHECK_RESULT(); + if (resp->oem_id == 0x14e4 && + resp->naming_authority == + HWRM_OEM_CMD_INPUT_NAMING_AUTHORITY_PCI_SIG && + resp->message_family == + HWRM_OEM_CMD_INPUT_MESSAGE_FAMILY_TRUFLOW) + memcpy(out, resp->oem_data, out_len); + HWRM_UNLOCK(); + + return rc; +} diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h index 19fb35f223..ec639bdbce 100644 --- a/drivers/net/bnxt/bnxt_hwrm.h +++ b/drivers/net/bnxt/bnxt_hwrm.h @@ -367,6 +367,10 @@ int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr); void bnxt_free_hwrm_tx_ring(struct bnxt *bp, int queue_index); int bnxt_alloc_hwrm_tx_ring(struct bnxt *bp, int queue_index); int bnxt_hwrm_config_host_mtu(struct bnxt *bp); +int bnxt_hwrm_func_cfg_mpc(struct bnxt *bp, + uint8_t mpc_chnls_msk, + bool enable); +int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr); int bnxt_vnic_rss_clear_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic); int bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic); int bnxt_hwrm_func_backing_store_qcaps_v2(struct bnxt *bp); @@ -375,4 +379,9 @@ int bnxt_hwrm_func_backing_store_cfg_v2(struct bnxt *bp, int bnxt_hwrm_func_backing_store_types_count(struct bnxt *bp); int bnxt_hwrm_func_backing_store_ctx_alloc(struct bnxt *bp, uint16_t types); int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp); +int bnxt_hwrm_tf_oem_cmd(struct bnxt *bp, + uint32_t *in, + uint16_t in_len, + uint32_t *out, + uint16_t out_len); #endif diff --git a/drivers/net/bnxt/bnxt_mpc.c b/drivers/net/bnxt/bnxt_mpc.c new file mode 100644 index 0000000000..0ae571e57f --- /dev/null +++ b/drivers/net/bnxt/bnxt_mpc.c @@ -0,0 +1,853 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2014-2020 Broadcom + * All rights reserved. + */ + +#include +#include +#include + +#include "bnxt.h" +#include "bnxt_ring.h" +#include "bnxt_mpc.h" +#include "bnxt_hwrm.h" +#include "hsi_struct_def_dpdk.h" + +/*#define MPC_DEBUG 1*/ + +#define BNXT_MPC_BP_SIZE 16 + +static int bnxt_mpc_chnls_enable(struct bnxt *bp) +{ + struct bnxt_mpc *mpc = bp->mpc; + uint8_t mpc_chnl_msk = 0; + int i, rc; + + if (!mpc) + return -EINVAL; + + for (i = 0; i < BNXT_MPC_CHNL_MAX; i++) { + if (!(mpc->mpc_chnls_cap & (1 << i))) + continue; + mpc_chnl_msk |= (1 << i); + } + mpc->mpc_chnls_en = mpc_chnl_msk; + + if (!BNXT_PF(bp)) + return 0; + + rc = bnxt_hwrm_func_cfg_mpc(bp, mpc_chnl_msk, true); + if (rc != 0) { + mpc->mpc_chnls_en = 0; + PMD_DRV_LOG(ERR, "MPC chnls enabling failed rc:%d\n", rc); + } + + return rc; +} + +static int bnxt_mpc_chnls_disable(struct bnxt *bp) +{ + struct bnxt_mpc *mpc = bp->mpc; + uint8_t mpc_chnl_msk = 0; + int i, rc; + + if (!mpc) + return -EINVAL; + mpc->mpc_chnls_en = 0; + + if (!BNXT_PF(bp)) + return 0; + + for (i = 0; i < BNXT_MPC_CHNL_MAX; i++) { + if (!(mpc->mpc_chnls_en & (1 << i))) + continue; + mpc_chnl_msk |= (1 << i); + } + rc = bnxt_hwrm_func_cfg_mpc(bp, mpc_chnl_msk, false); + if (rc != 0) + PMD_DRV_LOG(ERR, "MPC chnls disabling failed rc:%d\n", rc); + + return rc; +} + +static void bnxt_mpc_queue_release_mbufs(struct bnxt_mpc_txq *mpc_queue) +{ + struct bnxt_sw_mpc_bd *sw_ring; + uint16_t i; + + if (!mpc_queue) + return; + + sw_ring = mpc_queue->mpc_ring->mpc_buf_ring; + if (!sw_ring) + return; + + for (i = 0; i < mpc_queue->mpc_ring->mpc_ring_struct->ring_size; i++) { + if (sw_ring[i].mpc_mbuf) { + rte_free(sw_ring[i].mpc_mbuf); + sw_ring[i].mpc_mbuf = NULL; + } + } +} + +static void bnxt_mpc_queue_release_one(struct bnxt_mpc_txq *mpc_queue) +{ + if (!mpc_queue) + return; + + if (is_bnxt_in_error(mpc_queue->bp)) + return; + /* Free MPC ring HW descriptors */ + bnxt_mpc_queue_release_mbufs(mpc_queue); + bnxt_free_ring(mpc_queue->mpc_ring->mpc_ring_struct); + /* Free MPC completion ring HW descriptors */ + bnxt_free_ring(mpc_queue->cp_ring->cp_ring_struct); + + rte_memzone_free(mpc_queue->mz); + mpc_queue->mz = NULL; + + rte_free(mpc_queue->free); + rte_free(mpc_queue); +} + +static void bnxt_mpc_ring_free_one(struct bnxt_mpc_txq *mpc_queue) +{ + struct bnxt_cp_ring_info *cpr; + struct bnxt_mpc_ring_info *mpr; + struct bnxt_ring *ring; + + if (!mpc_queue) + return; + + if (is_bnxt_in_error(mpc_queue->bp)) + return; + + mpr = mpc_queue->mpc_ring; + ring = mpr->mpc_ring_struct; + if (ring->fw_ring_id == INVALID_HW_RING_ID) + return; + + cpr = mpc_queue->cp_ring; + bnxt_hwrm_ring_free(mpc_queue->bp, ring, + HWRM_RING_FREE_INPUT_RING_TYPE_TX, + cpr->cp_ring_struct->fw_ring_id); + ring->fw_ring_id = INVALID_HW_RING_ID; + memset(mpr->mpc_desc_ring, 0, + mpr->mpc_ring_struct->ring_size * sizeof(*mpr->mpc_desc_ring)); + memset(mpr->mpc_buf_ring, 0, + mpr->mpc_ring_struct->ring_size * sizeof(*mpr->mpc_buf_ring)); + mpr->raw_prod = 0; + mpr->raw_cons = 0; + + bnxt_free_cp_ring(mpc_queue->bp, cpr); + bnxt_hwrm_stat_ctx_free(mpc_queue->bp, cpr); +} + +int bnxt_mpc_close(struct bnxt *bp) +{ + int i, rc = 0; + struct bnxt_mpc_txq *mpc_queue; + struct bnxt_mpc *mpc; + + rc = is_bnxt_in_error(bp); + if (rc) + return rc; + + if (!bp->mpc) + return 0; + + mpc = bp->mpc; + /* free the MPC TX ring for each channel. */ + for (i = 0 ; i < BNXT_MPC_CHNL_MAX; i++) { + if (!(mpc->mpc_chnls_en & (1 << i))) + continue; + mpc_queue = mpc->mpc_txq[i]; + if (!mpc_queue) + continue; + bnxt_mpc_ring_free_one(mpc_queue); + bnxt_mpc_queue_release_one(mpc_queue); + mpc->mpc_txq[i] = NULL; + } + + rc = bnxt_mpc_chnls_disable(bp); + if (rc) + PMD_DRV_LOG(ERR, "MPC channels disable failed rc:%d\n", rc); + + return rc; +} + +static int bnxt_init_mpc_ring_struct(struct bnxt_mpc_txq *mpc_queue, + unsigned int socket_id) +{ + struct bnxt_cp_ring_info *cpr; + struct bnxt_mpc_ring_info *mpr; + struct bnxt_ring *ring; + int rc = 0; + + mpr = rte_zmalloc_socket("bnxt_mpc_ring", + sizeof(struct bnxt_mpc_ring_info), + RTE_CACHE_LINE_SIZE, socket_id); + if (mpr == NULL) + return -ENOMEM; + mpc_queue->mpc_ring = mpr; + + ring = rte_zmalloc_socket("bnxt_mpc_ring_struct", + sizeof(struct bnxt_ring), + RTE_CACHE_LINE_SIZE, socket_id); + if (ring == NULL) { + PMD_DRV_LOG(ERR, "MPC ring struct alloc failed rc:%d\n", rc); + rc = -ENOMEM; + goto bnxt_init_mpc_ring_struct_err; + } + + mpr->mpc_ring_struct = ring; + ring->ring_size = rte_align32pow2(mpc_queue->nb_mpc_desc); + ring->ring_mask = ring->ring_size - 1; + ring->bd = (void *)mpr->mpc_desc_ring; + ring->bd_dma = mpr->mpc_desc_mapping; + ring->vmem_size = ring->ring_size * sizeof(struct bnxt_sw_mpc_bd); + ring->vmem = (void **)&mpr->mpc_buf_ring; + ring->fw_ring_id = INVALID_HW_RING_ID; + + cpr = rte_zmalloc_socket("bnxt_mpc_ring", + sizeof(struct bnxt_cp_ring_info), + RTE_CACHE_LINE_SIZE, socket_id); + if (cpr == NULL) { + PMD_DRV_LOG(ERR, "MPC cp ring alloc failed rc:%d\n", rc); + rc = -ENOMEM; + goto bnxt_init_mpc_ring_struct_err1; + } + mpc_queue->cp_ring = cpr; + + ring = rte_zmalloc_socket("bnxt_mpc_ring_struct", + sizeof(struct bnxt_ring), + RTE_CACHE_LINE_SIZE, socket_id); + if (ring == NULL) { + PMD_DRV_LOG(ERR, "MPC cp ring struct alloc failed rc:%d\n", rc); + rc = -ENOMEM; + goto bnxt_init_mpc_ring_struct_err2; + } + cpr->cp_ring_struct = ring; + ring->ring_size = mpr->mpc_ring_struct->ring_size; + ring->ring_mask = ring->ring_size - 1; + ring->bd = (void *)cpr->cp_desc_ring; + ring->bd_dma = cpr->cp_desc_mapping; + ring->vmem_size = 0; + ring->vmem = NULL; + ring->fw_ring_id = INVALID_HW_RING_ID; + + return 0; + +bnxt_init_mpc_ring_struct_err2: + rte_free(cpr); +bnxt_init_mpc_ring_struct_err1: + rte_free(ring); +bnxt_init_mpc_ring_struct_err: + rte_free(mpr); + mpc_queue->mpc_ring = NULL; + return rc; +} + +/* + * For a MPC queue, allocates a completion ring with vmem and bd ring, + * stats mem, a TX ring with vmem and bd ring. + * + * Order in the allocation is: + * stats - Always non-zero length + * cp vmem - Always zero-length, supported for the bnxt_ring abstraction + * tx vmem - Only non-zero length + * cp bd ring - Always non-zero length + * tx bd ring - Only non-zero length + */ + +static int bnxt_alloc_mpc_rings(struct bnxt_mpc_txq *mpc_queue, + const char *suffix) +{ + struct bnxt_ring *cp_ring; + struct bnxt_cp_ring_info *cp_ring_info; + struct bnxt_mpc_ring_info *mpc_ring_info; + struct bnxt_ring *ring; + struct rte_pci_device *pdev; + const struct rte_memzone *mz = NULL; + char mz_name[RTE_MEMZONE_NAMESIZE]; + rte_iova_t mz_phys_addr; + + if (!mpc_queue) + return -EINVAL; + + pdev = mpc_queue->bp->pdev; + mpc_ring_info = mpc_queue->mpc_ring; + cp_ring = mpc_queue->cp_ring->cp_ring_struct; + cp_ring_info = mpc_queue->cp_ring; + + int stats_len = BNXT_HWRM_CTX_GET_SIZE(mpc_queue->bp); + stats_len = RTE_CACHE_LINE_ROUNDUP(stats_len); + stats_len = RTE_ALIGN(stats_len, 128); + + int cp_vmem_start = stats_len; + int cp_vmem_len = RTE_CACHE_LINE_ROUNDUP(cp_ring->vmem_size); + cp_vmem_len = RTE_ALIGN(cp_vmem_len, 128); + + int nq_vmem_len = RTE_CACHE_LINE_ROUNDUP(cp_ring->vmem_size); + nq_vmem_len = RTE_ALIGN(nq_vmem_len, 128); + + int nq_vmem_start = cp_vmem_start + cp_vmem_len; + + int mpc_vmem_start = nq_vmem_start + nq_vmem_len; + int mpc_vmem_len = + RTE_CACHE_LINE_ROUNDUP(mpc_ring_info->mpc_ring_struct->vmem_size); + mpc_vmem_len = RTE_ALIGN(mpc_vmem_len, 128); + + int cp_ring_start = mpc_vmem_start + mpc_vmem_len; + cp_ring_start = RTE_ALIGN(cp_ring_start, 4096); + + int cp_ring_len = RTE_CACHE_LINE_ROUNDUP(cp_ring->ring_size * + sizeof(struct cmpl_base)); + cp_ring_len = RTE_ALIGN(cp_ring_len, 128); + + int mpc_ring_start = cp_ring_start + cp_ring_len; + mpc_ring_start = RTE_ALIGN(mpc_ring_start, 4096); + int mpc_ring_len = + RTE_CACHE_LINE_ROUNDUP(mpc_ring_info->mpc_ring_struct->ring_size * + sizeof(struct tx_bd_mp_cmd)); + mpc_ring_len = RTE_ALIGN(mpc_ring_len, 4096); + + int total_alloc_len = mpc_ring_start + mpc_ring_len; + snprintf(mz_name, RTE_MEMZONE_NAMESIZE, + "bnxt_" PCI_PRI_FMT "-%04x_%s", pdev->addr.domain, + pdev->addr.bus, pdev->addr.devid, pdev->addr.function, + mpc_queue->chnl_id, suffix); + mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; + mz = rte_memzone_lookup(mz_name); + if (!mz) { + mz = rte_memzone_reserve_aligned(mz_name, total_alloc_len, + SOCKET_ID_ANY, + RTE_MEMZONE_2MB | + RTE_MEMZONE_SIZE_HINT_ONLY | + RTE_MEMZONE_IOVA_CONTIG, + getpagesize()); + if (mz == NULL || !mz->addr) + return -ENOMEM; + } + memset(mz->addr, 0, mz->len); + mz_phys_addr = mz->iova; + + mpc_queue->mz = mz; + ring = mpc_ring_info->mpc_ring_struct; + + ring->bd = ((char *)mz->addr + mpc_ring_start); + mpc_ring_info->mpc_desc_ring = (struct tx_bd_mp_cmd *)ring->bd; + ring->bd_dma = mz_phys_addr + mpc_ring_start; + mpc_ring_info->mpc_desc_mapping = ring->bd_dma; + ring->mem_zone = (const void *)mz; + + if (ring->vmem_size) { + ring->vmem = (void **)((char *)mz->addr + mpc_vmem_start); + mpc_ring_info->mpc_buf_ring = + (struct bnxt_sw_mpc_bd *)ring->vmem; + } + + cp_ring->bd = ((char *)mz->addr + cp_ring_start); + cp_ring->bd_dma = mz_phys_addr + cp_ring_start; + cp_ring_info->cp_desc_ring = cp_ring->bd; + cp_ring_info->cp_desc_mapping = cp_ring->bd_dma; + cp_ring->mem_zone = (const void *)mz; + + if (cp_ring->vmem_size) + *cp_ring->vmem = (char *)mz->addr + stats_len; + + cp_ring_info->hw_stats = mz->addr; + cp_ring_info->hw_stats_map = mz_phys_addr; + cp_ring_info->hw_stats_ctx_id = HWRM_NA_SIGNATURE; + + return 0; +} + +static void bnxt_init_one_mpc_ring(struct bnxt_mpc_txq *mpc_queue) +{ + struct bnxt_mpc_ring_info *mpr = mpc_queue->mpc_ring; + struct bnxt_cp_ring_info *cpr = mpc_queue->cp_ring; + struct bnxt_ring *ring = mpr->mpc_ring_struct; + + mpc_queue->wake_thresh = ring->ring_size / 2; + ring->fw_ring_id = INVALID_HW_RING_ID; + mpr->epoch = 0; + cpr->epoch = 0; +} + +static uint16_t get_mpc_ring_logical_id(uint8_t mpc_cap, + enum bnxt_mpc_chnl chnl_id, + uint16_t offset) +{ + unsigned int i; + uint8_t logical_id = 0; + + for (i = 0; i < BNXT_MPC_CHNL_MAX; i++) { + if (!(mpc_cap & (1 << i))) + continue; + + if (i == chnl_id) + return (logical_id + offset); + + logical_id++; + } + + return INVALID_HW_RING_ID; +} + +static int bnxt_mpc_queue_setup_one(struct bnxt *bp, enum bnxt_mpc_chnl chnl_id, + uint16_t nb_desc, unsigned int socket_id) +{ + int rc = 0; + struct bnxt_mpc *mpc; + struct bnxt_mpc_txq *mpc_queue; + + if (!bp || !bp->mpc) + return 0; + + mpc = bp->mpc; + mpc_queue = rte_zmalloc_socket("bnxt_mpc_queue", + sizeof(struct bnxt_mpc_txq), + RTE_CACHE_LINE_SIZE, socket_id); + if (!mpc_queue) { + PMD_DRV_LOG(ERR, "bnxt_mpc_queue allocation failed!"); + return -ENOMEM; + } + + mpc_queue->free = + rte_zmalloc_socket(NULL, + sizeof(struct bnxt_mpc_mbuf *) * nb_desc, + RTE_CACHE_LINE_SIZE, socket_id); + if (!mpc_queue->free) { + PMD_DRV_LOG(ERR, "allocation of mpc mbuf free array failed!"); + rc = -ENOMEM; + goto bnxt_mpc_queue_setup_one_err; + } + mpc_queue->bp = bp; + mpc_queue->nb_mpc_desc = nb_desc; + /* TBD: hardcoded to 1 for now and should be tuned later for perf */ + mpc_queue->free_thresh = BNXT_MPC_DESC_THRESH; + + rc = bnxt_init_mpc_ring_struct(mpc_queue, socket_id); + if (rc) + goto bnxt_mpc_queue_setup_one_err1; + + mpc_queue->chnl_id = chnl_id; + + /* allocate MPC TX ring hardware descriptors */ + rc = bnxt_alloc_mpc_rings(mpc_queue, "mpc"); + if (rc) { + PMD_DRV_LOG(ERR, "ring_dma_zone_reserve for mpc_ring failed!"); + rc = -ENOMEM; + goto bnxt_mpc_queue_setup_one_err1; + } + bnxt_init_one_mpc_ring(mpc_queue); + mpc_queue->queue_idx = get_mpc_ring_logical_id(bp->mpc->mpc_chnls_cap, + chnl_id, + bp->tx_cp_nr_rings); + mpc_queue->started = true; + mpc->mpc_txq[chnl_id] = mpc_queue; + + return 0; + +bnxt_mpc_queue_setup_one_err1: + rte_free(mpc_queue->free); +bnxt_mpc_queue_setup_one_err: + rte_free(mpc_queue); + return rc; +} + +static int bnxt_mpc_ring_alloc_one(struct bnxt *bp, enum bnxt_mpc_chnl chnl_id) +{ + int rc = 0; + struct bnxt_mpc_txq *mpc_queue; + struct bnxt_cp_ring_info *cpr; + struct bnxt_ring *cp_ring; + struct bnxt_mpc_ring_info *mpr; + struct bnxt_ring *ring; + struct bnxt_coal coal; + uint32_t map_index; + + if (!bp || !bp->mpc) + return 0; + + mpc_queue = bp->mpc->mpc_txq[chnl_id]; + if (!mpc_queue) + return -EINVAL; + + bnxt_init_dflt_coal(&coal); + cpr = mpc_queue->cp_ring; + cp_ring = cpr->cp_ring_struct; + map_index = mpc_queue->queue_idx; + + rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr); + if (rc) { + PMD_DRV_LOG(ERR, "mpc ring %d stats alloc failed rc:%d!\n", + chnl_id, rc); + return rc; + } + rc = bnxt_alloc_cmpl_ring(bp, map_index, cpr); + if (rc) { + PMD_DRV_LOG(ERR, "mpc ring %d cmpl ring alloc failed rc:%d!\n", + chnl_id, rc); + goto bnxt_mpc_ring_alloc_one_err; + } + mpr = mpc_queue->mpc_ring; + ring = mpr->mpc_ring_struct; + map_index = BNXT_MPC_MAP_INDEX(chnl_id, mpc_queue->queue_idx); + + rc = bnxt_hwrm_ring_alloc(bp, + ring, + HWRM_RING_ALLOC_INPUT_RING_TYPE_TX, + map_index, + cpr->hw_stats_ctx_id, + cp_ring->fw_ring_id, + MPC_HW_COS_ID); + if (rc) { + PMD_DRV_LOG(ERR, "mpc ring %d tx ring alloc failed rc:%d!\n", + chnl_id, rc); + goto bnxt_mpc_ring_alloc_one_err1; + } + + bnxt_set_db(bp, &mpr->db, HWRM_RING_ALLOC_INPUT_RING_TYPE_TX, chnl_id, + ring->fw_ring_id, ring->ring_mask); + + bnxt_hwrm_set_ring_coal(bp, &coal, cp_ring->fw_ring_id); + + return rc; + +bnxt_mpc_ring_alloc_one_err1: + bnxt_free_cp_ring(bp, cpr); +bnxt_mpc_ring_alloc_one_err: + bnxt_hwrm_stat_ctx_free(bp, cpr); + return rc; +} + +int bnxt_mpc_open(struct bnxt *bp) +{ + int rc = 0; + enum bnxt_mpc_chnl i; + struct bnxt_mpc *mpc; + unsigned int socket_id; + + rc = is_bnxt_in_error(bp); + if (rc) + return rc; + + if (!bp->mpc) + return 0; + + /* enable the MPC channels first */ + rc = bnxt_mpc_chnls_enable(bp); + if (rc) { + PMD_DRV_LOG(ERR, "MPC channels enable failed rc:%d\n", rc); + return rc; + } + socket_id = rte_lcore_to_socket_id(rte_get_main_lcore()); + mpc = bp->mpc; + + /* Limit to MPC TE_CFA and RE_CFA */ + mpc->mpc_chnls_cap &= (1 << HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TE_CFA) | + (1 << HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RE_CFA); + + /* allocate one MPC TX ring for each channel. */ + for (i = 0; i < BNXT_MPC_CHNL_MAX; i++) { + if (!(mpc->mpc_chnls_cap & (1 << i))) + continue; + rc = bnxt_mpc_queue_setup_one(bp, i, BNXT_MPC_NB_DESC, socket_id); + if (rc) { + PMD_DRV_LOG(ERR, "MPC queue %d setup failed rc:%d\n", + i, rc); + goto bnxt_mpc_open_err; + } + rc = bnxt_mpc_ring_alloc_one(bp, i); + if (rc) { + PMD_DRV_LOG(ERR, "MPC ring %d alloc failed rc:%d\n", + i, rc); + goto bnxt_mpc_open_err; + } + } + + return rc; + +bnxt_mpc_open_err: + bnxt_mpc_close(bp); + return rc; +} + +static inline uint32_t bnxt_mpc_bds_in_hw(struct bnxt_mpc_txq *mpc_queue) +{ + struct bnxt_mpc_ring_info *mpc_ring = mpc_queue->mpc_ring; +#ifdef MPC_DEBUG + printf("Raw prod:%d Raw cons:%d Mask:0x%08x Result:%d\n", + mpc_ring->raw_prod, + mpc_ring->raw_cons, + mpc_ring->mpc_ring_struct->ring_mask, + ((mpc_ring->raw_prod - mpc_ring->raw_cons) & + mpc_ring->mpc_ring_struct->ring_mask)); + printf("Ring size:%d\n", mpc_queue->mpc_ring->mpc_ring_struct->ring_size); +#endif + return ((mpc_ring->raw_prod - mpc_ring->raw_cons) & + mpc_ring->mpc_ring_struct->ring_mask); +} + +int bnxt_mpc_cmd_cmpl(struct bnxt_mpc_txq *mpc_queue, struct bnxt_mpc_mbuf *out_msg) +{ + struct bnxt_cp_ring_info *cpr = mpc_queue->cp_ring; + uint32_t raw_cons = cpr->cp_raw_cons; + uint32_t cons; + struct cmpl_base *mpc_cmpl; + uint32_t nb_mpc_cmds = 0; + struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring; + struct bnxt_ring *cp_ring_struct = cpr->cp_ring_struct; + uint32_t ring_mask = cp_ring_struct->ring_mask; + uint32_t idx = raw_cons; + uint32_t num_bds; + bool is_long = + (out_msg->cmp_type == CMPL_BASE_TYPE_MID_PATH_LONG ? true : false); + + do { + cons = RING_CMPL(ring_mask, raw_cons); +#ifdef MPC_DEBUG + printf("raw_cons:%d cons:%d\n", raw_cons, cons); +#endif + mpc_cmpl = &cpr->cp_desc_ring[cons]; + + rte_prefetch_non_temporal(&cp_desc_ring[(cons + 2) & + ring_mask]); + + if (!CMPL_VALID(mpc_cmpl, cpr->valid)) { + break; + } else if (is_long) { + uint32_t cons_tmp = cons + 1; + uint32_t valid; + struct cmpl_base *tmp_mpc_cmpl = &cp_desc_ring[cons_tmp & ring_mask]; + + if ((cons_tmp & ring_mask) < (cons & ring_mask)) + valid = !cpr->valid; + else + valid = cpr->valid; + + if (!CMPL_VALID(tmp_mpc_cmpl, valid)) + break; + } + + NEXT_CMPL(cpr, + cons, + cpr->valid, + (is_long ? 2 : 1)); + + rte_prefetch0(&cp_desc_ring[cons]); + + if (likely(CMP_TYPE(mpc_cmpl) == out_msg->cmp_type)) { + nb_mpc_cmds++; + idx = raw_cons; + raw_cons = cons; + break; + } else { + RTE_LOG_DP(DEBUG, BNXT, "Unhandled CMP type %02x\n", + CMP_TYPE(mpc_cmpl)); + } +#ifdef MPC_DEBUG + printf("info2:0x%08x nb_mpc_cmds:%d\n", mpc_cmpl->info2, nb_mpc_cmds); +#endif + raw_cons = cons; + } while (nb_mpc_cmds < ring_mask); + + if (nb_mpc_cmds) { + memcpy(out_msg->msg_data, + &cpr->cp_desc_ring[idx], + BNXT_MPC_BP_SIZE); + + if (is_long) { + uint32_t tidx = idx + 1; + + if (tidx >= BNXT_MPC_NB_DESC) + tidx = 0; + + memcpy(out_msg->msg_data + BNXT_MPC_BP_SIZE, + &cpr->cp_desc_ring[tidx], + BNXT_MPC_BP_SIZE); + } + +#ifdef MPC_DEBUG + printf("cp_raw_cons:%d\n", cpr->cp_raw_cons); +#endif + if (is_long) + num_bds = 2; + else + num_bds = 1; + + cpr->cp_raw_cons = idx + num_bds; + + /* Handle the wrap */ + if (cpr->cp_raw_cons >= BNXT_MPC_NB_DESC) { +#ifdef MPC_DEBUG + printf("Completion queue epoch flip from: %d to %d\n", + cpr->epoch, + (cpr->epoch == 0 ? 1 : 0)); +#endif + cpr->epoch = (cpr->epoch == 0 ? 1 : 0); + cpr->cp_raw_cons -= BNXT_MPC_NB_DESC; + } + + bnxt_db_mpc_cq(cpr); + } + + return nb_mpc_cmds; +} + +static inline uint32_t bnxt_mpc_avail(struct bnxt_mpc_txq *mpc_queue) +{ + /* Tell compiler to fetch mpc indices from memory. */ + rte_compiler_barrier(); + + return ((mpc_queue->mpc_ring->mpc_ring_struct->ring_size - + bnxt_mpc_bds_in_hw(mpc_queue)) - 1); +} + +#ifdef MPC_DEBUG +void dump_bd(uint8_t *bd, uint32_t num_bd) +{ + int j; + int i; + + for (j = 0; j < num_bd; j++) { + printf("%d: ", j); + for (i = 0; i < BNXT_MPC_BP_SIZE; i++) { + printf("%02x", *bd); + bd++; + } + + printf("\n"); + } + printf("\n"); +} +#endif + +static uint16_t bnxt_mpc_xmit(struct bnxt_mpc_mbuf *mpc_cmd, + struct bnxt_mpc_txq *mpc_queue, + uint32_t *opaque) +{ + struct bnxt_mpc_ring_info *mpr = mpc_queue->mpc_ring; + struct bnxt_ring *ring = mpr->mpc_ring_struct; + unsigned short nr_bds = 0; + uint16_t prod; + struct bnxt_sw_mpc_bd *mpc_buf; + struct tx_bd_mp_cmd *mpc_bd; + uint8_t *msg_buf; + int i; + + if (unlikely(is_bnxt_in_error(mpc_queue->bp))) + return -EIO; + + nr_bds = (mpc_cmd->msg_size + sizeof(struct tx_bd_mp_cmd) - 1) + / sizeof(struct tx_bd_mp_cmd) + 1; + + prod = RING_IDX(ring, mpr->raw_prod); +#ifdef MPC_DEBUG + printf("tx raw prod:%d prod:%d\n", mpr->raw_prod, prod); +#endif + mpc_buf = &mpr->mpc_buf_ring[prod]; + mpc_buf->mpc_mbuf = mpc_cmd; + mpc_buf->nr_bds = nr_bds; + + mpc_bd = &mpr->mpc_desc_ring[prod]; + memset(mpc_bd, 0, sizeof(struct tx_bd_mp_cmd)); + mpc_bd->opaque = *opaque; + mpc_bd->flags_type = nr_bds << TX_BD_MP_CMD_FLAGS_BD_CNT_SFT; + mpc_bd->flags_type |= TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD; + mpc_bd->len = mpc_cmd->msg_size; + + /* copy the messages to the subsequent inline bds */ + for (i = 0; i < nr_bds - 1; i++) { + mpr->raw_prod = RING_NEXT(mpr->raw_prod) % BNXT_MPC_NB_DESC; + prod = RING_IDX(ring, mpr->raw_prod); +#ifdef MPC_DEUBG + printf("tx raw prod:%d prod:%d\n", mpr->raw_prod, prod); +#endif + mpc_bd = &mpr->mpc_desc_ring[prod]; + msg_buf = mpc_cmd->msg_data + i * sizeof(struct tx_bd_mp_cmd); + memcpy(mpc_bd, msg_buf, sizeof(struct tx_bd_mp_cmd)); + } + + mpr->raw_prod = RING_NEXT(mpr->raw_prod) % BNXT_MPC_NB_DESC; +#ifdef MPC_DEBUG + printf("tx raw prod:%d prod:%d\n", mpr->raw_prod, prod); +#endif + return 0; +} + +int bnxt_mpc_send(struct bnxt *bp, + struct bnxt_mpc_mbuf *in_msg, + struct bnxt_mpc_mbuf *out_msg, + uint32_t *opaque, + bool batch) +{ + int rc; + struct bnxt_mpc_txq *mpc_queue = bp->mpc->mpc_txq[in_msg->chnl_id]; + int retry = BNXT_MPC_RX_RETRY; + uint32_t pi = 0; + + if (out_msg->cmp_type != CMPL_BASE_TYPE_MID_PATH_SHORT && + out_msg->cmp_type != CMPL_BASE_TYPE_MID_PATH_LONG) + return -1; + +#ifdef MPC_DEBUG + if (mpc_queue == NULL || mpc_queue->mpc_ring == NULL) + return -1; +#endif + + /* + * Save the producer index so that if wrapping occurs + * it can be detected. + */ + pi = mpc_queue->mpc_ring->raw_prod; + rc = bnxt_mpc_xmit(in_msg, mpc_queue, opaque); + + if (unlikely(rc)) + return -1; +#ifdef MPC_DEBUG + printf("raw_prod:%d pi:%d\n", mpc_queue->mpc_ring->raw_prod, pi); +#endif + /* + * If the producer index wraps then toggle the epoch. + */ + if (mpc_queue->mpc_ring->raw_prod < pi) { +#ifdef MPC_DEBUG + printf("Tx queue epoch flip from: %d to %d\n", + mpc_queue->mpc_ring->epoch, + (mpc_queue->mpc_ring->epoch == 0 ? 1 : 0)); +#endif + mpc_queue->mpc_ring->epoch = (mpc_queue->mpc_ring->epoch == 0 ? 1 : 0); + } + +#ifdef MPC_DEBUG + dump_bd(&mpc_queue->mpc_ring->mpc_desc_ring[pi], 4); +#endif + /* + * Ring the Tx doorbell. + */ + bnxt_db_mpc_write(&mpc_queue->mpc_ring->db, + mpc_queue->mpc_ring->raw_prod, + mpc_queue->mpc_ring->epoch); + + if (batch) + return 0; + + /* Wait for response */ + do { + rte_delay_us_block(BNXT_MPC_RX_US_DELAY); + + rc = bnxt_mpc_cmd_cmpl(mpc_queue, out_msg); + + if (rc == 1) + return 0; +#ifdef MPC_DEBUG + printf("Received zero or more than one completion:%d\n", rc); +#endif + retry--; + } while (retry); + + return -1; +} diff --git a/drivers/net/bnxt/bnxt_mpc.h b/drivers/net/bnxt/bnxt_mpc.h new file mode 100644 index 0000000000..cfbb461e9c --- /dev/null +++ b/drivers/net/bnxt/bnxt_mpc.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2014-2020 Broadcom + * All rights reserved. + */ + +#ifndef _BNXT_MPC_H_ +#define _BNXT_MPC_H_ + +#include +#include +#include + +/* MPC Batch support */ +extern bool bnxt_tfc_mpc_batch; +extern uint8_t bnxt_mpc_batch_count; + +#define BNXT_MPC_RX_RETRY 100000 + +#define BNXT_MPC_NB_DESC 128 +#define BNXT_MPC_DESC_THRESH 3 +#define BNXT_MPC_CHNL_SHIFT 16 +#define BNXT_MPC_QIDX_MSK 0xFFFF +#define BNXT_MPC_CHNL(x) ((x) >> BNXT_MPC_CHNL_SHIFT) +#define BNXT_MPC_QIDX(x) ((x) & BNXT_MPC_QIDX_MSK) +#define BNXT_MPC_MAP_INDEX(x, y) (((x) << BNXT_MPC_CHNL_SHIFT) | (y)) + +#define BNXT_MPC_CHNLS_SUPPORTED 2 /* Limit to MPC TE_CFA and RE_CFA */ + +/* BNXT_MPC_RINGS_SUPPORTED set to 1 TE_CFA and 1 1 RE_CFA types. + * Can be set upto tx_nr_rings * BNXT_MPC_CHNLS_SUPPORTED if needed. + */ +#define BNXT_MPC_RINGS_SUPPORTED (1 * BNXT_MPC_CHNLS_SUPPORTED) + +/* Defines the number of msgs there are in an MPC msg completion event. + * Used to pass an opaque value into the MPC msg xmit function. The + * completion processing uses this value to ring the doorbell correctly to + * signal "completion event processing complete" to the hardware. + */ +#define BNXT_MPC_COMP_MSG_COUNT 1 + +/* Defines the uS delay prior to processing an MPC completion */ +#define BNXT_MPC_RX_US_DELAY 1 + +enum bnxt_mpc_chnl { + BNXT_MPC_CHNL_TCE = 0, + BNXT_MPC_CHNL_RCE = 1, + BNXT_MPC_CHNL_TE_CFA = 2, + BNXT_MPC_CHNL_RE_CFA = 3, + BNXT_MPC_CHNL_PRIMATE = 4, + BNXT_MPC_CHNL_MAX = 5, +}; + +struct bnxt_sw_mpc_bd { + struct bnxt_mpc_mbuf *mpc_mbuf; /* mpc mbuf associated with mpc bd */ + unsigned short nr_bds; +}; + +struct bnxt_mpc_ring_info { + uint16_t raw_prod; + uint16_t raw_cons; + struct bnxt_db_info db; + + struct tx_bd_mp_cmd *mpc_desc_ring; + struct bnxt_sw_mpc_bd *mpc_buf_ring; + + rte_iova_t mpc_desc_mapping; + + uint32_t dev_state; + + struct bnxt_ring *mpc_ring_struct; + uint32_t epoch; +}; + +struct bnxt_mpc_mbuf { + enum bnxt_mpc_chnl chnl_id; + uint8_t cmp_type; + uint8_t *msg_data; + /* MPC msg size in bytes, must be multiple of 16Bytes */ + uint16_t msg_size; +}; + +struct bnxt_mpc_txq { + enum bnxt_mpc_chnl chnl_id; + uint32_t queue_idx; + uint16_t nb_mpc_desc; /* number of MPC descriptors */ + uint16_t free_thresh;/* minimum mpc cmds before freeing */ + int wake_thresh; + uint8_t started; /* MPC queue is started */ + + struct bnxt *bp; + struct bnxt_mpc_ring_info *mpc_ring; + unsigned int cp_nr_rings; + struct bnxt_cp_ring_info *cp_ring; + const struct rte_memzone *mz; + struct bnxt_mpc_mbuf **free; + + void (*cmpl_handler_cb)(struct bnxt_mpc_txq *mpc_queue, + uint32_t nb_mpc_cmds); +}; + +struct bnxt_mpc { + uint8_t mpc_chnls_cap; + uint8_t mpc_chnls_en; + struct bnxt_mpc_txq *mpc_txq[BNXT_MPC_CHNL_MAX]; +}; + +int bnxt_mpc_open(struct bnxt *bp); +int bnxt_mpc_close(struct bnxt *bp); +int bnxt_mpc_send(struct bnxt *bp, + struct bnxt_mpc_mbuf *in_msg, + struct bnxt_mpc_mbuf *out_msg, + uint32_t *opaque, + bool batch); +int bnxt_mpc_cmd_cmpl(struct bnxt_mpc_txq *mpc_queue, struct bnxt_mpc_mbuf *out_msg); +int bnxt_mpc_poll_cmd_cmpls(struct bnxt_mpc_txq *mpc_queue); + +#endif diff --git a/drivers/net/bnxt/bnxt_ring.c b/drivers/net/bnxt/bnxt_ring.c index 9e512321d9..c4a5877ccc 100644 --- a/drivers/net/bnxt/bnxt_ring.c +++ b/drivers/net/bnxt/bnxt_ring.c @@ -57,6 +57,7 @@ int bnxt_alloc_ring_grps(struct bnxt *bp) /* P5 does not support ring groups. * But we will use the array to save RSS context IDs. */ + /* TODO Revisit for Thor 2 */ if (BNXT_CHIP_P5_P7(bp)) { bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5; } else if (bp->max_ring_grps < bp->rx_cp_nr_rings) { @@ -329,7 +330,7 @@ int bnxt_alloc_rings(struct bnxt *bp, unsigned int socket_id, uint16_t qidx, return 0; } -static void bnxt_init_dflt_coal(struct bnxt_coal *coal) +void bnxt_init_dflt_coal(struct bnxt_coal *coal) { /* Tick values in micro seconds. * 1 coal_buf x bufs_per_record = 1 completion record. @@ -347,12 +348,12 @@ static void bnxt_init_dflt_coal(struct bnxt_coal *coal) coal->cmpl_aggr_dma_tmr_during_int = BNXT_CMPL_AGGR_DMA_TMR_DURING_INT; } -static void bnxt_set_db(struct bnxt *bp, - struct bnxt_db_info *db, - uint32_t ring_type, - uint32_t map_idx, - uint32_t fid, - uint32_t ring_mask) +void bnxt_set_db(struct bnxt *bp, + struct bnxt_db_info *db, + uint32_t ring_type, + uint32_t map_idx, + uint32_t fid, + uint32_t ring_mask) { if (BNXT_CHIP_P5_P7(bp)) { int db_offset = DB_PF_OFFSET; @@ -400,8 +401,8 @@ static void bnxt_set_db(struct bnxt *bp, db->db_ring_mask = ring_mask; } -static int bnxt_alloc_cmpl_ring(struct bnxt *bp, int queue_index, - struct bnxt_cp_ring_info *cpr) +int bnxt_alloc_cmpl_ring(struct bnxt *bp, int queue_index, + struct bnxt_cp_ring_info *cpr) { struct bnxt_ring *cp_ring = cpr->cp_ring_struct; uint32_t nq_ring_id = HWRM_NA_SIGNATURE; diff --git a/drivers/net/bnxt/bnxt_ring.h b/drivers/net/bnxt/bnxt_ring.h index b33fb75284..be0a560ead 100644 --- a/drivers/net/bnxt/bnxt_ring.h +++ b/drivers/net/bnxt/bnxt_ring.h @@ -37,7 +37,8 @@ #define MAX_CP_DESC_CNT (16 * 1024) #define INVALID_HW_RING_ID ((uint16_t)-1) -#define INVALID_STATS_CTX_ID ((uint16_t)-1) +#define INVALID_STATS_CTX_ID ((uint16_t)-1) +#define MPC_HW_COS_ID ((uint16_t)-2) struct bnxt_ring { void *bd; @@ -80,6 +81,15 @@ void bnxt_free_async_cp_ring(struct bnxt *bp); int bnxt_alloc_async_ring_struct(struct bnxt *bp); int bnxt_alloc_rxtx_nq_ring(struct bnxt *bp); void bnxt_free_rxtx_nq_ring(struct bnxt *bp); +void bnxt_init_dflt_coal(struct bnxt_coal *coal); +int bnxt_alloc_cmpl_ring(struct bnxt *bp, int queue_index, + struct bnxt_cp_ring_info *cpr); +void bnxt_set_db(struct bnxt *bp, + struct bnxt_db_info *db, + uint32_t ring_type, + uint32_t map_idx, + uint32_t fid, + uint32_t ring_mask); static inline void bnxt_db_write(struct bnxt_db_info *db, uint32_t idx) { @@ -98,6 +108,27 @@ static inline void bnxt_db_write(struct bnxt_db_info *db, uint32_t idx) } } +static inline void bnxt_db_mpc_write(struct bnxt_db_info *db, uint32_t idx, uint32_t epoch) +{ + uint32_t db_idx = DB_RING_IDX(db, idx); + void *doorbell = db->doorbell; + + if (likely(db->db_64)) { + uint64_t key_idx = db->db_key64 | db_idx | + (epoch << 24); +#ifdef RING_DEBUG + printf("DB: 0x%08x:%08x\n", + (uint32_t)((key_idx >> 32) & 0xFFFFFFFF), + (uint32_t)(key_idx & 0xFFFFFFFF)); +#endif + rte_write64_relaxed(key_idx, doorbell); + } else { + uint32_t key_idx = db->db_key32 | db_idx; + + rte_write32_relaxed(key_idx, doorbell); + } +} + /* Ring an NQ doorbell and disable interrupts for the ring. */ static inline void bnxt_db_nq(struct bnxt_cp_ring_info *cpr) { @@ -143,4 +174,25 @@ static inline void bnxt_db_cq(struct bnxt_cp_ring_info *cpr) B_CP_DIS_DB(cpr, cp_raw_cons); } } + +static inline void bnxt_db_mpc_cq(struct bnxt_cp_ring_info *cpr) +{ + struct bnxt_db_info *db = &cpr->cp_db; + uint32_t idx = DB_RING_IDX(&cpr->cp_db, cpr->cp_raw_cons); + + if (likely(db->db_64)) { + uint64_t key_idx = db->db_key64 | idx | + (cpr->epoch << 24); + void *doorbell = db->doorbell; + + rte_compiler_barrier(); + rte_write64_relaxed(key_idx, doorbell); + } else { + uint32_t cp_raw_cons = cpr->cp_raw_cons; + + rte_compiler_barrier(); + B_CP_DIS_DB(cpr, cp_raw_cons); + } +} + #endif diff --git a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h index f9190fcd89..fd83e4881d 100644 --- a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h +++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h @@ -3,6 +3,10 @@ * All rights reserved. */ +/*! + * \file + * \brief Exported functions for CFA HW programming + */ #ifndef _HCAPI_CFA_H_ #define _HCAPI_CFA_H_ @@ -104,18 +108,7 @@ struct hcapi_cfa_devops { extern const size_t CFA_RM_HANDLE_DATA_SIZE; -#if SUPPORT_CFA_HW_ALL -extern const struct hcapi_cfa_devops cfa_p4_devops; -extern const struct hcapi_cfa_devops cfa_p58_devops; - -#elif defined(SUPPORT_CFA_HW_P4) && SUPPORT_CFA_HW_P4 extern const struct hcapi_cfa_devops cfa_p4_devops; -uint64_t hcapi_cfa_p4_key_hash(uint64_t *key_data, uint16_t bitlen); -/* SUPPORT_CFA_HW_P4 */ -#elif defined(SUPPORT_CFA_HW_P58) && SUPPORT_CFA_HW_P58 extern const struct hcapi_cfa_devops cfa_p58_devops; -uint64_t hcapi_cfa_p58_key_hash(uint64_t *key_data, uint16_t bitlen); -/* SUPPORT_CFA_HW_P58 */ -#endif #endif /* HCAPI_CFA_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h index 16a31598d6..7d19bf3847 100644 --- a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h +++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h @@ -1,12 +1,8 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ -/*! - * \file - * \brief Exported functions for CFA HW programming - */ #ifndef _HCAPI_CFA_DEFS_H_ #define _HCAPI_CFA_DEFS_H_ @@ -23,34 +19,24 @@ #define CFA_BITS_PER_BYTE (8) #define CFA_BITS_PER_WORD (sizeof(uint32_t) * CFA_BITS_PER_BYTE) #define __CFA_ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask)) +#ifndef CFA_ALIGN #define CFA_ALIGN(x, a) __CFA_ALIGN_MASK((x), (a) - 1) +#endif #define CFA_ALIGN_256(x) CFA_ALIGN(x, 256) #define CFA_ALIGN_128(x) CFA_ALIGN(x, 128) #define CFA_ALIGN_32(x) CFA_ALIGN(x, 32) -#define NUM_WORDS_ALIGN_32BIT(x) (CFA_ALIGN_32(x) / CFA_BITS_PER_WORD) -#define NUM_WORDS_ALIGN_128BIT(x) (CFA_ALIGN_128(x) / CFA_BITS_PER_WORD) -#define NUM_WORDS_ALIGN_256BIT(x) (CFA_ALIGN_256(x) / CFA_BITS_PER_WORD) - /* TODO: redefine according to chip variant */ #define CFA_GLOBAL_CFG_DATA_SZ (100) -#ifndef SUPPORT_CFA_HW_P4 -#define SUPPORT_CFA_HW_P4 (0) -#endif - -#ifndef SUPPORT_CFA_HW_P45 -#define SUPPORT_CFA_HW_P45 (0) -#endif - -#ifndef SUPPORT_CFA_HW_P58 -#define SUPPORT_CFA_HW_P58 (0) -#endif - -#if SUPPORT_CFA_HW_ALL #include "hcapi_cfa_p4.h" #include "hcapi_cfa_p58.h" -#endif /* SUPPORT_CFA_HW_ALL */ + +#define CFA_PROF_L2CTXT_TCAM_MAX_FIELD_CNT CFA_P58_PROF_L2_CTXT_TCAM_MAX_FLD +#define CFA_PROF_L2CTXT_REMAP_MAX_FIELD_CNT CFA_P58_PROF_L2_CTXT_RMP_DR_MAX_FLD +#define CFA_PROF_MAX_KEY_CFG_SZ sizeof(struct cfa_p58_prof_key_cfg) +#define CFA_KEY_MAX_FIELD_CNT 0 +#define CFA_ACT_MAX_TEMPLATE_SZ 0 /* * Hashing defines @@ -61,6 +47,7 @@ #define ucrc32(ch, crc) (crc32tbl[((crc) ^ (ch)) & 0xff] ^ ((crc) >> 8)) #define crc32(x, y) crc32i(~0, x, y) + /** * CFA HW version definition */ @@ -68,7 +55,8 @@ enum hcapi_cfa_ver { HCAPI_CFA_P40 = 0, /**< CFA phase 4.0 */ HCAPI_CFA_P45 = 1, /**< CFA phase 4.5 */ HCAPI_CFA_P58 = 2, /**< CFA phase 5.8 */ - HCAPI_CFA_PMAX = 3 + HCAPI_CFA_P59 = 3, /**< CFA phase 5.9 */ + HCAPI_CFA_PMAX = 4 }; /** @@ -100,7 +88,7 @@ enum hcapi_cfa_hwops { * operation is also undo the add operation * performed by the HCAPI_CFA_HWOPS_ADD op. */ - HCAPI_CFA_HWOPS_EVICT, /*< This operation is used to evict entries from + HCAPI_CFA_HWOPS_EVICT, /*< This operation is used to edit entries from * CFA cache memories. This operation is only * applicable to tables that use CFA caches. */ @@ -116,6 +104,44 @@ enum hcapi_cfa_key_ctrlops { HCAPI_CFA_KEY_CTRLOPS_MAX }; +/** + * CFA HW field structure definition + */ +struct hcapi_cfa_field { + /** [in] Starting bit position pf the HW field within a HW table + * entry. + */ + uint16_t bitpos; + /** [in] Number of bits for the HW field. */ + uint16_t bitlen; +}; + +/** + * CFA HW table entry layout structure definition + */ +struct hcapi_cfa_layout { + /** [out] Bit order of layout */ + bool is_msb_order; + /** [out] Size in bits of entry */ + uint32_t total_sz_in_bits; + /** [out] data pointer of the HW layout fields array */ + struct hcapi_cfa_field *field_array; + /** [out] number of HW field entries in the HW layout field array */ + uint32_t array_sz; + /** [out] layout_id - layout id associated with the layout */ + uint16_t layout_id; +}; + +/** + * CFA HW data object definition + */ +struct hcapi_cfa_data_obj { + /** [in] HW field identifier. Used as an index to a HW table layout */ + uint16_t field_id; + /** [in] Value of the HW field */ + uint64_t val; +}; + /** * CFA HW definition */ @@ -294,6 +320,91 @@ struct hcapi_cfa_key_loc { uint32_t mem_idx; }; +/** + * CFA HW layout table definition + */ +struct hcapi_cfa_layout_tbl { + /** [out] data pointer to an array of fix formatted layouts supported. + * The index to the array is the CFA HW table ID + */ + const struct hcapi_cfa_layout *tbl; + /** [out] number of fix formatted layouts in the layout array */ + uint16_t num_layouts; +}; + +/** + * Key template consists of key fields that can be enabled/disabled + * individually. + */ +struct hcapi_cfa_key_template { + /** [in] key field enable field array, set 1 to the correspeonding + * field enable to make a field valid + */ + uint8_t field_en[CFA_KEY_MAX_FIELD_CNT]; + /** [in] Identify if the key template is for TCAM. If false, the + * key template is for EM. This field is mandantory for device that + * only support fix key formats. + */ + bool is_wc_tcam_key; + /** [in] Identify if the key template will be use for IPv6 Keys. + * + */ + bool is_ipv6_key; +}; + +/** + * key layout consist of field array, key bitlen, key ID, and other meta data + * pertain to a key + */ +struct hcapi_cfa_key_layout { + /** [out] key layout data */ + struct hcapi_cfa_layout *layout; + /** [out] actual key size in number of bits */ + uint16_t bitlen; + /** [out] key identifier and this field is only valid for device + * that supports fix key formats + */ + uint16_t id; + /** [out] Identified the key layout is WC TCAM key */ + bool is_wc_tcam_key; + /** [out] Identify if the key template will be use for IPv6 Keys. + * + */ + bool is_ipv6_key; + /** [out] total slices size, valid for WC TCAM key only. It can be + * used by the user to determine the total size of WC TCAM key slices + * in bytes. + */ + uint16_t slices_size; +}; + +/** + * key layout memory contents + */ +struct hcapi_cfa_key_layout_contents { + /** key layouts */ + struct hcapi_cfa_key_layout key_layout; + + /** layout */ + struct hcapi_cfa_layout layout; + + /** fields */ + struct hcapi_cfa_field field_array[CFA_KEY_MAX_FIELD_CNT]; +}; + +/** + * Action template consists of action fields that can be enabled/disabled + * individually. + */ +struct hcapi_cfa_action_template { + /** [in] CFA version for the action template */ + enum hcapi_cfa_ver hw_ver; + /** [in] action field enable field array, set 1 to the correspeonding + * field enable to make a field valid + */ + uint8_t data[CFA_ACT_MAX_TEMPLATE_SZ]; +}; + /** * Action record info */ @@ -332,6 +443,421 @@ struct hcapi_cfa_action_obj { struct hcapi_cfa_action_layout *layout; }; +/** + * action layout consist of field array, action wordlen and action format ID + */ +struct hcapi_cfa_action_layout { + /** [in] action identifier */ + uint16_t id; + /** [out] action layout data */ + struct hcapi_cfa_layout *layout; + /** [out] actual action record size in number of bits */ + uint16_t bitlen; +}; + +/** + * CFA backing store type definition + */ +enum hcapi_cfa_bs_type { + HCAPI_CFA_BS_TYPE_LKUP, /**< EM LKUP backing store type */ + HCAPI_CFA_BS_TYPE_ACT, /**< Action backing store type */ + HCAPI_CFA_BS_TYPE_MAX +}; + +/** + * CFA backing store configuration data object + */ +struct hcapi_cfa_bs_cfg { + enum hcapi_cfa_bs_type type; + uint16_t tbl_scope; + struct hcapi_cfa_bs_db *bs_db; +}; + +/** + * CFA backing store data base object + */ +struct hcapi_cfa_bs_db { + /** [in] memory manager database signature */ + uint32_t signature; +#define HCAPI_CFA_BS_SIGNATURE 0xCFA0B300 + /** [in] memory manager database base pointer (VA) */ + void *mgmt_db; + /** [in] memory manager database size in bytes */ + uint32_t mgmt_db_sz; + /** [in] Backing store memory pool base pointer + * (VA – backed by IOVA which is DMA accessible)) + */ + void *bs_ptr; + /** [in] bs_offset - byte offset to the section of the + * backing store memory managed by the backing store + * memory manager. + * For EM backing store, this is the starting byte + * offset to the EM record memory. + * For Action backing store, this offset is 0. + */ + uint32_t offset; + /** [in] backing store memory pool size in bytes + */ + uint32_t bs_sz; +}; + +/** + * \defgroup CFA_HCAPI_PUT_API + * HCAPI used for writing to the hardware + * @{ + */ + +/** + * This API provides the functionality to program a specified value to a + * HW field based on the provided programming layout. + * + * @param[in,out] obj_data + * A data pointer to a CFA HW key/mask data + * + * @param[in] layout + * A pointer to CFA HW programming layout + * + * @param[in] field_id + * ID of the HW field to be programmed + * + * @param[in] val + * Value of the HW field to be programmed + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int hcapi_cfa_put_field(uint64_t *data_buf, + const struct hcapi_cfa_layout *layout, + uint16_t field_id, uint64_t val); + +/** + * This API provides the functionality to program an array of field values + * with corresponding field IDs to a number of profiler sub-block fields + * based on the fixed profiler sub-block hardware programming layout. + * + * @param[in, out] obj_data + * A pointer to a CFA profiler key/mask object data + * + * @param[in] layout + * A pointer to CFA HW programming layout + * + * @param[in] field_tbl + * A pointer to an array that consists of the object field + * ID/value pairs + * + * @param[in] field_tbl_sz + * Number of entries in the table + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int hcapi_cfa_put_fields(uint64_t *obj_data, + const struct hcapi_cfa_layout *layout, + struct hcapi_cfa_data_obj *field_tbl, + uint16_t field_tbl_sz); +/** + * This API provides the functionality to program an array of field values + * with corresponding field IDs to a number of profiler sub-block fields + * based on the fixed profiler sub-block hardware programming layout. This + * API will swap the n byte blocks before programming the field array. + * + * @param[in, out] obj_data + * A pointer to a CFA profiler key/mask object data + * + * @param[in] layout + * A pointer to CFA HW programming layout + * + * @param[in] field_tbl + * A pointer to an array that consists of the object field + * ID/value pairs + * + * @param[in] field_tbl_sz + * Number of entries in the table + * + * @param[in] data_size + * size of the data in bytes + * + * @param[in] n + * block size in bytes + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int hcapi_cfa_put_fields_swap(uint64_t *obj_data, + const struct hcapi_cfa_layout *layout, + struct hcapi_cfa_data_obj *field_tbl, + uint16_t field_tbl_sz, uint16_t data_size, + uint16_t n); +/** + * This API provides the functionality to write a value to a + * field within the bit position and bit length of a HW data + * object based on a provided programming layout. + * + * @param[in, out] act_obj + * A pointer of the action object to be initialized + * + * @param[in] layout + * A pointer of the programming layout + * + * @param field_id + * [in] Identifier of the HW field + * + * @param[in] bitpos_adj + * Bit position adjustment value + * + * @param[in] bitlen_adj + * Bit length adjustment value + * + * @param[in] val + * HW field value to be programmed + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int hcapi_cfa_put_field_rel(uint64_t *obj_data, + const struct hcapi_cfa_layout *layout, + uint16_t field_id, int16_t bitpos_adj, + int16_t bitlen_adj, uint64_t val); + +/*@}*/ + +/** + * \defgroup CFA_HCAPI_GET_API + * HCAPI used for writing to the hardware + * @{ + */ + +/** + * This API provides the functionality to get the word length of + * a layout object. + * + * @param[in] layout + * A pointer of the HW layout + * + * @return + * Word length of the layout object + */ +uint16_t hcapi_cfa_get_wordlen(const struct hcapi_cfa_layout *layout); + +/** + * The API provides the functionality to get bit offset and bit + * length information of a field from a programming layout. + * + * @param[in] layout + * A pointer of the action layout + * + * @param[out] slice + * A pointer to the action offset info data structure + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int hcapi_cfa_get_slice(const struct hcapi_cfa_layout *layout, + uint16_t field_id, struct hcapi_cfa_field *slice); + +/** + * This API provides the functionality to read the value of a + * CFA HW field from CFA HW data object based on the hardware + * programming layout. + * + * @param[in] obj_data + * A pointer to a CFA HW key/mask object data + * + * @param[in] layout + * A pointer to CFA HW programming layout + * + * @param[in] field_id + * ID of the HW field to be programmed + * + * @param[out] val + * Value of the HW field + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int hcapi_cfa_get_field(uint64_t *obj_data, + const struct hcapi_cfa_layout *layout, + uint16_t field_id, uint64_t *val); + +/** + * This API provides the functionality to read 128-bit value of + * a CFA HW field from CFA HW data object based on the hardware + * programming layout. + * + * @param[in] obj_data + * A pointer to a CFA HW key/mask object data + * + * @param[in] layout + * A pointer to CFA HW programming layout + * + * @param[in] field_id + * ID of the HW field to be programmed + * + * @param[out] val_msb + * Msb value of the HW field + * + * @param[out] val_lsb + * Lsb value of the HW field + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int hcapi_cfa_get128_field(uint64_t *obj_data, + const struct hcapi_cfa_layout *layout, + uint16_t field_id, uint64_t *val_msb, + uint64_t *val_lsb); + +/** + * This API provides the functionality to read a number of + * HW fields from a CFA HW data object based on the hardware + * programming layout. + * + * @param[in] obj_data + * A pointer to a CFA profiler key/mask object data + * + * @param[in] layout + * A pointer to CFA HW programming layout + * + * @param[in, out] field_tbl + * A pointer to an array that consists of the object field + * ID/value pairs + * + * @param[in] field_tbl_sz + * Number of entries in the table + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int hcapi_cfa_get_fields(uint64_t *obj_data, + const struct hcapi_cfa_layout *layout, + struct hcapi_cfa_data_obj *field_tbl, + uint16_t field_tbl_sz); + +/** + * This API provides the functionality to read a number of + * HW fields from a CFA HW data object based on the hardware + * programming layout.This API will swap the n byte blocks before + * retrieving the field array. + * + * @param[in] obj_data + * A pointer to a CFA profiler key/mask object data + * + * @param[in] layout + * A pointer to CFA HW programming layout + * + * @param[in, out] field_tbl + * A pointer to an array that consists of the object field + * ID/value pairs + * + * @param[in] field_tbl_sz + * Number of entries in the table + * + * @param[in] data_size + * size of the data in bytes + * + * @param[in] n + * block size in bytes + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int hcapi_cfa_get_fields_swap(uint64_t *obj_data, + const struct hcapi_cfa_layout *layout, + struct hcapi_cfa_data_obj *field_tbl, + uint16_t field_tbl_sz, uint16_t data_size, + uint16_t n); + +/** + * Get a value to a specific location relative to a HW field + * + * This API provides the functionality to read HW field from + * a section of a HW data object identified by the bit position + * and bit length from a given programming layout in order to avoid + * reading the entire HW data object. + * + * @param[in] obj_data + * A pointer of the data object to read from + * + * @param[in] layout + * A pointer of the programming layout + * + * @param[in] field_id + * Identifier of the HW field + * + * @param[in] bitpos_adj + * Bit position adjustment value + * + * @param[in] bitlen_adj + * Bit length adjustment value + * + * @param[out] val + * Value of the HW field + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int hcapi_cfa_get_field_rel(uint64_t *obj_data, + const struct hcapi_cfa_layout *layout, + uint16_t field_id, int16_t bitpos_adj, + int16_t bitlen_adj, uint64_t *val); + +/** + * Get the length of the layout in words + * + * @param[in] layout + * A pointer to the layout to determine the number of words + * required + * + * @return + * number of words needed for the given layout + */ +uint16_t cfa_hw_get_wordlen(const struct hcapi_cfa_layout *layout); + +/** + * This function is used to initialize a layout_contents structure + * + * The struct hcapi_cfa_key_layout is complex as there are three + * layers of abstraction. Each of those layer need to be properly + * initialized. + * + * @param[in] contents + * A pointer of the layout contents to initialize + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int hcapi_cfa_init_key_contents(struct hcapi_cfa_key_layout_contents *contents); + +/** + * This function is used to validate a key template + * + * The struct hcapi_cfa_key_template is complex as there are three + * layers of abstraction. Each of those layer need to be properly + * validated. + * + * @param[in] key_template + * A pointer of the key template contents to validate + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int hcapi_cfa_is_valid_key_template(struct hcapi_cfa_key_template *key_template); + +/** + * This function is used to validate a key layout + * + * The struct hcapi_cfa_key_layout is complex as there are three + * layers of abstraction. Each of those layer need to be properly + * validated. + * + * @param[in] key_layout + * A pointer of the key layout contents to validate + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int hcapi_cfa_is_valid_key_layout(struct hcapi_cfa_key_layout *key_layout); + /** * This function is used to hash E/EM keys * diff --git a/drivers/net/bnxt/hcapi/cfa_v3/CMakeLists.txt b/drivers/net/bnxt/hcapi/cfa_v3/CMakeLists.txt new file mode 100644 index 0000000000..a6b6103c99 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/CMakeLists.txt @@ -0,0 +1,92 @@ +# +# Copyright(c) 2019-2021 Broadcom Limited, all rights reserved +# Contains proprietary and confidential information. +# +# This source file is the property of Broadcom Limited, and +# may not be copied or distributed in any isomorphic form without +# the prior written consent of Broadcom Limited. +# + +# Needed for compilation with chip-specific regdef.h +add_definitions(-DFIRMWARE_VIEW=1) + +# Platform specific defines +if (cfa_p70) + add_definitions(-DSUPPORT_CFA_HW_P70=1) + set(PXX_FOLDER p70) + set (tsm_needed 1) + set (mm_needed 1) +endif () + +if (cfa_p80) + add_definitions(-DSUPPORT_CFA_HW_P80=1) + set(PXX_FOLDER p80) + set (tcm_needed 1) +endif () + +# Reset Doc dir variables +set(CFA_API_DOC_DIRS "" CACHE INTERNAL "") +set(CFA_DESIGN_DOC_DIRS "" CACHE INTERNAL "") +set(CFA_UT_DOC_DIRS "" CACHE INTERNAL "") + +# Include sub directories + +if (idm_needed) + add_subdirectory(idm) + set(idm_libs cfa-idm-lib cfa-idm-lib-ut) +endif () + +if (tbm_needed) + add_subdirectory(tbm) + set(tbm_libs cfa-tbm-lib cfa-tbm-lib-ut) +endif () + +if (gim_needed) + add_subdirectory(gim) + set(gim_libs cfa-gim-lib cfa-gim-lib-ut) +endif () + +if (mm_needed) + add_subdirectory(mm) + set(mm_libs cfa-mm-lib cfa-mm-lib-ut) +endif () + +if (tsm_needed) + add_subdirectory(tpm) + add_subdirectory(tim) + set(cfa-tim-lib cfa-tim-lib-ut cfa-tpm-lib cfa-tpm-lib-ut) +endif () + +if (tcm_needed) + add_subdirectory(tcm) + set(tcm_libs cfa-tcm-lib cfa-tcm-lib-ut) +endif () + +if (rdm_needed) + add_subdirectory(rdm) + set(rdm_libs cfa-rdm-lib cfa-rdm-lib-ut) +endif () + +# Update Doxygen dirs for api documentation +#set(CFA_API_DOC_DIRS ${CFA_API_DOC_DIRS} +# ${CMAKE_CURRENT_SOURCE_DIR}/include +# CACHE INTERNAL "") + +# Update Doxygen dirs for design documentation +#set(CFA_DESIGN_DOC_DIRS ${CFA_DESIGN_DOC_DIRS} +# ${CMAKE_CURRENT_SOURCE_DIR}/include +# CACHE INTERNAL "") + +# Include docs +#if (DOXYGEN_FOUND) +# add_subdirectory(docs) +# add_custom_target(cfa-v3-docs +# DEPENDS hcapi-cfa-api-docs +# hcapi-cfa-design-docs +# hcapi-cfa-ut-docs +# ) +#endif (DOXYGEN_FOUND) + +add_custom_target(cfa-v3-libs + ALL + DEPENDS ${tpm_libs} ${tim_libs} ${mm_libs}) diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/host/cfa_bld_mpc.c b/drivers/net/bnxt/hcapi/cfa_v3/bld/host/cfa_bld_mpc.c new file mode 100644 index 0000000000..e84341b52f --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/host/cfa_bld_mpc.c @@ -0,0 +1,42 @@ +/**************************************************************************** + * Copyright(c) 2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_bld_mpc.c + * + * @brief CFA Builder MPC binding api + */ + +#include +#include "cfa_bld.h" +#include "host/cfa_bld_mpcops.h" + +#if SUPPORT_CFA_HW_P70 +#include "cfa_bld_p70_mpcops.h" +#endif + +int cfa_bld_mpc_bind(enum cfa_ver hw_ver, struct cfa_bld_mpcinfo *mpcinfo) +{ + if (!mpcinfo) + return -EINVAL; + + switch (hw_ver) { + case CFA_P40: + case CFA_P45: + case CFA_P58: + case CFA_P59: + return -ENOTSUP; + case CFA_P70: +#if SUPPORT_CFA_HW_P70 + return cfa_bld_p70_mpc_bind(hw_ver, mpcinfo); +#else + return -ENOTSUP; +#endif + default: + return -EINVAL; + } +} diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/include/cfa_bld_defs.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/cfa_bld_defs.h new file mode 100644 index 0000000000..8acd770589 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/cfa_bld_defs.h @@ -0,0 +1,578 @@ +/**************************************************************************** + * Copyright(c) 2021 - 2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_bld_defs.h + * + * @brief CFA Builder library structure definitions and API + */ + +#ifndef _CFA_BLD_DEFS_H_ +#define _CFA_BLD_DEFS_H_ + +#include +#include + +#include "cfa_resources.h" +#include "cfa_types.h" + +/** + * @addtogroup CFA_BLD CFA Builder Library + * \ingroup CFA_V3 + * The CFA builder library is a set of APIs provided the following services: + * + * 1. Provide users generic put service to convert software programming data + * into a hardware data bit stream according to a HW layout representation, + * or generic get service to extract value of a field or values of a number + * of fields from the raw hardware data bit stream according to a HW layout. + * + * - A software programming data is represented in {field_idx, val} + * structure. + * - A HW layout is represented with array of CFA field structures with + * {bitpos, bitlen} and identified by a layout id corresponding to a CFA + * HW table. + * - A HW data bit stream are bits that is formatted according to a HW + * layout representation. + * + * 2. Provide EM/WC key and action related service APIs to compile layout, + * init, and manipulate key and action data objects. + * + * 3. Provide CFA mid-path message building APIs. (TBD) + * + * The CFA builder library is designed to run in the primate firmware and also + * as part of the following host base diagnostic software. + * - Lcdiag + * - Truflow CLI + * - coredump decorder + * + * @{ + */ + +/** @name CFA Builder Common Definition + * CFA builder common structures and enumerations + */ + +/**@{*/ +/** + * CFA HW KEY CONTROL OPCODE definition + */ +enum cfa_key_ctrlops { + CFA_KEY_CTRLOPS_INSERT, /**< insert WC control bits */ + CFA_KEY_CTRLOPS_STRIP, /**< strip WC control bits */ + CFA_KEY_CTRLOPS_SWAP, /**< swap EM cache lines */ + CFA_KEY_CTRLOPS_MAX +}; + +/** + * CFA HW field structure definition + */ +struct cfa_field { + /** [in] Starting bit position pf the HW field within a HW table + * entry. + */ + uint16_t bitpos; + /** [in] Number of bits for the HW field. */ + uint16_t bitlen; +}; + +/** + * CFA HW table entry layout structure definition + */ +struct cfa_layout { + /** [out] Bit order of layout + * if swap_order_bitpos is non-zero, the bit order of the layout + * will be swapped after this bit. swap_order_bitpos must be a + * multiple of 64. This is currently only used for inlined action + * records where the AR is lsb and the following inlined actions + * must be msb. + */ + bool is_msb_order; + /** [out] Reverse is_msb_order after this bit if non-zero */ + uint16_t swap_order_bitpos; + /** [out] Size in bits of entry */ + uint32_t total_sz_in_bits; + /** [in/out] data pointer of the HW layout fields array */ + struct cfa_field *field_array; + /** [out] number of HW field entries in the HW layout field array */ + uint32_t array_sz; + /** [out] layout_id - layout id associated with the layout */ + uint16_t layout_id; +}; + +/** + * CFA HW data object definition + */ +struct cfa_data_obj { + /** [in] HW field identifier. Used as an index to a HW table layout */ + uint16_t field_id; + /** [in] Value of the HW field */ + uint64_t val; +}; + +/** + * CFA HW key buffer definition + */ +struct cfa_key_obj { + /** [in] pointer to the key data buffer */ + uint32_t *data; + /** [in] buffer len in bytes */ + uint32_t data_len_bytes; + /** [out] Data length in bits + * When cfa_key_obj is passed as an output parameter, the updated + * key length (if the key length changes) is returned in this field by the + * key processing api (e.g cfa_bld_key_transform) + * When cfa_key_obj is passed as an input parameter, this field is unused + * and need not be initialized by the caller. + */ + uint32_t data_len_bits; + /** [in] Pointer to the key layout */ + struct cfa_key_layout *layout; +}; + +/** + * CFA HW layout table definition + */ +struct cfa_layout_tbl { + /** [out] data pointer to an array of fix formatted layouts supported. + * The index to the array is either the CFA resource subtype or + * remap table ID + */ + const struct cfa_layout *layouts; + /** [out] number of fix formatted layouts in the layout array */ + uint16_t num_layouts; +}; + +/** + * key layout consist of field array, key bitlen, key ID, and other meta data + * pertain to a key + */ +struct cfa_key_layout { + /** [in/out] key layout data */ + struct cfa_layout *layout; + /** [out] actual key size in number of bits */ + uint16_t bitlen; + /** [out] key identifier and this field is only valid for device + * that supports fix key formats + */ + uint16_t id; + /** [out] Identified the key layout is WC TCAM key */ + bool is_wc_tcam_key; + /** [out] Identify if the key template will be use for IPv6 Keys. + * + * Note: This is important for Thor2 as the field length for the FlowId + * is dependent on the L3 flow type. For Thor2 for IPv4 Keys, the Flow + * Id field is 16 bits, for all other types (IPv6, ARP, PTP, EAP, RoCE, + * FCoE, UPAR), the Flow Id field length is 20 bits. + */ + bool is_ipv6_key; + /** [out] total number of slices, valid for WC TCAM key only. It can be + * used by the user to pass in the num_slices to write to the hardware. + */ + uint16_t num_slices; +}; + +/** + * CFA HW key table definition + * + * Applicable to EEM and on-chip EM table only. + */ +struct cfa_key_tbl { + /** [in] For EEM, this is the KEY0 base mem pointer. For off-chip EM, + * this is the base mem pointer of the key table. + */ + uint8_t *base0; + /** [in] total size of the key table in bytes. For EEM, this size is + * same for both KEY0 and KEY1 table. + */ + uint32_t size; + /** [in] number of key buckets, applicable for newer chips */ + uint32_t num_buckets; + /** [in] For EEM, this is KEY1 base mem pointer. Fo on-chip EM, + * this is the key record memory base pointer within the key table, + * applicable for newer chip + */ + uint8_t *base1; + /** [in] Optional - If the table is managed by a Backing Store + * database, then this object can be use to configure the EM Key. + */ + struct cfa_bs_db *bs_db; + /** [in] Page size for EEM tables */ + uint32_t page_size; +}; + +/** + * CFA HW key data definition + */ +struct cfa_key_data { + /** [in] For on-chip key table, it is the offset in unit of smallest + * key. For off-chip key table, it is the byte offset relative + * to the key record memory base and adjusted for page and entry size. + */ + uint32_t offset; + /** [in] HW key data buffer pointer */ + uint8_t *data; + /** [in] size of the key in bytes */ + uint16_t size; + /** [in] optional table scope ID */ + uint8_t tbl_scope; + /** [in] the fid owner of the key */ + uint64_t metadata; + /** [in] stored with the bucket which can be used to by + * the caller to retreved later via the GET HW OP. + */ +}; + +/** + * CFA HW key location definition + */ +struct cfa_key_loc { + /** [out] on-chip EM bucket offset or off-chip EM bucket mem pointer */ + uint64_t bucket_mem_ptr; + /** [out] off-chip EM key offset mem pointer */ + uint64_t mem_ptr; + /** [out] index within the array of the EM buckets */ + uint32_t bucket_mem_idx; + /** [out] index within the EM bucket */ + uint8_t bucket_idx; + /** [out] index within the EM records */ + uint32_t mem_idx; +}; + +/** + * Action record info + */ +struct cfa_action_addr { + /** [in] action SRAM block ID for on-chip action records or table + * scope of the action backing store + */ + uint16_t blk_id; + /** [in] ar_id or cache line aligned address offset for the action + * record + */ + uint32_t offset; +}; + +/** + * Action object definition + */ +struct cfa_action_obj { + /** [in] pointer to the action data buffer */ + uint64_t *data; + /** [in] buffer len in bytes */ + uint32_t len; + /** [in] pointer to the action layout */ + struct cfa_action_layout *layout; +}; + +/** + * action layout consist of field array, action wordlen and action format ID + */ +struct cfa_action_layout { + /** [in] action identifier */ + uint16_t id; + /** [out] action layout data */ + struct cfa_layout *layout; + /** [out] actual action record size in number of bits */ + uint16_t bitlen; +}; + +/**@}*/ + +/** @name CFA Builder PUT_FIELD APIs + * CFA Manager apis used for generating hw layout specific data objects that + * can be programmed to the hardware + */ + +/**@{*/ +/** + * @brief This API provides the functionality to program a specified value to a + * HW field based on the provided programming layout. + * + * @param[in,out] data_buf + * A data pointer to a CFA HW key/mask data + * + * @param[in] layout + * A pointer to CFA HW programming layout + * + * @param[in] field_id + * ID of the HW field to be programmed + * + * @param[in] val + * Value of the HW field to be programmed + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int cfa_put_field(uint64_t *data_buf, const struct cfa_layout *layout, + uint16_t field_id, uint64_t val); + +/** + * @brief This API provides the functionality to program an array of field + * values with corresponding field IDs to a number of profiler sub-block fields + * based on the fixed profiler sub-block hardware programming layout. + * + * @param[in, out] obj_data + * A pointer to a CFA profiler key/mask object data + * + * @param[in] layout + * A pointer to CFA HW programming layout + * + * @param[in] field_tbl + * A pointer to an array that consists of the object field + * ID/value pairs + * + * @param[in] field_tbl_sz + * Number of entries in the table + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int cfa_put_fields(uint64_t *obj_data, const struct cfa_layout *layout, + struct cfa_data_obj *field_tbl, uint16_t field_tbl_sz); + +/** + * @brief This API provides the functionality to program an array of field + * values with corresponding field IDs to a number of profiler sub-block fields + * based on the fixed profiler sub-block hardware programming layout. This + * API will swap the n byte blocks before programming the field array. + * + * @param[in, out] obj_data + * A pointer to a CFA profiler key/mask object data + * + * @param[in] layout + * A pointer to CFA HW programming layout + * + * @param[in] field_tbl + * A pointer to an array that consists of the object field + * ID/value pairs + * + * @param[in] field_tbl_sz + * Number of entries in the table + * + * @param[in] data_size + * size of the data in bytes + * + * @param[in] n + * block size in bytes + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int cfa_put_fields_swap(uint64_t *obj_data, const struct cfa_layout *layout, + struct cfa_data_obj *field_tbl, uint16_t field_tbl_sz, + uint16_t data_size, uint16_t n); + +/** + * @brief This API provides the functionality to write a value to a + * field within the bit position and bit length of a HW data + * object based on a provided programming layout. + * + * @param[in, out] obj_data + * A pointer of the action object to be initialized + * + * @param[in] layout + * A pointer of the programming layout + * + * @param field_id + * [in] Identifier of the HW field + * + * @param[in] bitpos_adj + * Bit position adjustment value + * + * @param[in] bitlen_adj + * Bit length adjustment value + * + * @param[in] val + * HW field value to be programmed + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int cfa_put_field_rel(uint64_t *obj_data, const struct cfa_layout *layout, + uint16_t field_id, int16_t bitpos_adj, int16_t bitlen_adj, + uint64_t val); + +/**@}*/ + +/** @name CFA Builder GET_FIELD APIs + * CFA Manager apis used for extract hw layout specific fields from CFA HW + * data objects + */ + +/**@{*/ +/** + * @brief The API provides the functionality to get bit offset and bit + * length information of a field from a programming layout. + * + * @param[in] layout + * A pointer of the action layout + * + * @param[in] field_id + * The field for which to retrieve the slice + * + * @param[out] slice + * A pointer to the action offset info data structure + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int cfa_get_slice(const struct cfa_layout *layout, uint16_t field_id, + struct cfa_field *slice); + +/** + * @brief This API provides the functionality to read the value of a + * CFA HW field from CFA HW data object based on the hardware + * programming layout. + * + * @param[in] obj_data + * A pointer to a CFA HW key/mask object data + * + * @param[in] layout + * A pointer to CFA HW programming layout + * + * @param[in] field_id + * ID of the HW field to be programmed + * + * @param[out] val + * Value of the HW field + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int cfa_get_field(uint64_t *obj_data, const struct cfa_layout *layout, + uint16_t field_id, uint64_t *val); + +/** + * @brief This API provides the functionality to read 128-bit value of + * a CFA HW field from CFA HW data object based on the hardware + * programming layout. + * + * @param[in] obj_data + * A pointer to a CFA HW key/mask object data + * + * @param[in] layout + * A pointer to CFA HW programming layout + * + * @param[in] field_id + * ID of the HW field to be programmed + * + * @param[out] val_msb + * Msb value of the HW field + * + * @param[out] val_lsb + * Lsb value of the HW field + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int cfa_get128_field(uint64_t *obj_data, const struct cfa_layout *layout, + uint16_t field_id, uint64_t *val_msb, uint64_t *val_lsb); + +/** + * @brief This API provides the functionality to read a number of + * HW fields from a CFA HW data object based on the hardware + * programming layout. + * + * @param[in] obj_data + * A pointer to a CFA profiler key/mask object data + * + * @param[in] layout + * A pointer to CFA HW programming layout + * + * @param[in, out] field_tbl + * A pointer to an array that consists of the object field + * ID/value pairs + * + * @param[in] field_tbl_sz + * Number of entries in the table + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int cfa_get_fields(uint64_t *obj_data, const struct cfa_layout *layout, + struct cfa_data_obj *field_tbl, uint16_t field_tbl_sz); + +/** + * @brief This API provides the functionality to read a number of + * HW fields from a CFA HW data object based on the hardware + * programming layout.This API will swap the n byte blocks before + * retrieving the field array. + * + * @param[in] obj_data + * A pointer to a CFA profiler key/mask object data + * + * @param[in] layout + * A pointer to CFA HW programming layout + * + * @param[in, out] field_tbl + * A pointer to an array that consists of the object field + * ID/value pairs + * + * @param[in] field_tbl_sz + * Number of entries in the table + * + * @param[in] data_size + * size of the data in bytes + * + * @param[in] n + * block size in bytes + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int cfa_get_fields_swap(uint64_t *obj_data, const struct cfa_layout *layout, + struct cfa_data_obj *field_tbl, uint16_t field_tbl_sz, + uint16_t data_size, uint16_t n); + +/** + * @brief Get a value to a specific location relative to a HW field + * This API provides the functionality to read HW field from + * a section of a HW data object identified by the bit position + * and bit length from a given programming layout in order to avoid + * reading the entire HW data object. + * + * @param[in] obj_data + * A pointer of the data object to read from + * + * @param[in] layout + * A pointer of the programming layout + * + * @param[in] field_id + * Identifier of the HW field + * + * @param[in] bitpos_adj + * Bit position adjustment value + * + * @param[in] bitlen_adj + * Bit length adjustment value + * + * @param[out] val + * Value of the HW field + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int cfa_get_field_rel(uint64_t *obj_data, const struct cfa_layout *layout, + uint16_t field_id, int16_t bitpos_adj, int16_t bitlen_adj, + uint64_t *val); + +/** + * @brief Get the length of the layout in words + * + * @param[in] layout + * A pointer to the layout to determine the number of words + * required + * + * @return + * number of words needed for the given layout + */ +uint16_t cfa_get_wordlen(const struct cfa_layout *layout); + +/**@}*/ + +/**@}*/ +#endif /* _CFA_BLD_DEFS_H_*/ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld.h new file mode 100644 index 0000000000..ce16d10e5b --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld.h @@ -0,0 +1,524 @@ +/**************************************************************************** + * Copyright(c) 2021 - 2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_bld.h + * + * @brief CFA HW independent Builder library public api header + */ + +#ifndef _CFA_BLD_H_ +#define _CFA_BLD_H_ + +#include "sys_util.h" +#include "cfa_bld_defs.h" +#include "cfa_bld_field_ids.h" + +/** + * @addtogroup CFA_BLD CFA Builder Library + * \ingroup CFA_V3 + * @{ + */ + +/** + * Maximum key array size + */ +#define CFA_V3_KEY_MAX_FIELD_CNT \ + MAX((uint16_t)CFA_BLD_EM_KEY_LAYOUT_MAX_FLD, \ + (uint16_t)CFA_BLD_WC_TCAM_FKB_MAX_FLD) +#define CFA_V3_ACT_MAX_TEMPLATE_SZ sizeof(struct cfa_bld_action_template) + +/** @name CFA Builder Templates + * CFA builder action and key templates definition and enumerations + */ + +/**@{*/ +enum action_type { + /** Select this type to build an Full Action Record Object + */ + CFA_BLD_ACT_OBJ_TYPE_FULL_ACT, + /** Select this type to build an Compact Action Record Object + */ + CFA_BLD_ACT_OBJ_TYPE_COMPACT_ACT, + /** Select this type to build an MCG Action Record Object + */ + CFA_BLD_ACT_OBJ_TYPE_MCG_ACT, + /** Select this type to build Standalone Modify Action Record Object */ + CFA_BLD_ACT_OBJ_TYPE_MODIFY, + /** Select this type to build Standalone Stat Action Record Object */ + CFA_BLD_ACT_OBJ_TYPE_STAT, + /** Select this type to build Standalone Source Action Record Object */ + CFA_BLD_ACT_OBJ_TYPE_SRC_PROP, + /** Select this type to build Standalone Encap Action Record Object */ + CFA_BLD_ACT_OBJ_TYPE_ENCAP, +}; + +enum stat_op { + /** Set to statistic to ingress to CFA + */ + CFA_BLD_STAT_OP_INGRESS = 0, + /** Set to statistic to egress from CFA + */ + CFA_BLD_STAT_OP_EGRESS = 1, +}; + +enum stat_type { + /** Set to statistic to Foward packet count(64b)/Foward byte + * count(64b) + */ + CFA_BLD_STAT_COUNTER_SIZE_16B = 0, + /** Set to statistic to Forward packet count(64b)/Forward byte + * count(64b)/ TCP Flags(16b)/Timestamp(32b) + */ + CFA_BLD_STAT_COUNTER_SIZE_24B = 1, + /** Set to statistic to Forward packet count(64b)/Forward byte + * count(64b)/Meter(drop or red) packet count(64b)/Meter(drop + * or red) byte count(64b) + */ + CFA_BLD_STAT_COUNTER_SIZE_32B = 2, + /** Set to statistic to Forward packet count(64b)/Forward byte + * count(64b)/Meter(drop or red) packet count(38b)/Meter(drop + * or red) byte count(42b)/TCP Flags(16b)/Timestamp(32b) + */ + CFA_BLD_STAT_COUNTER_SIZE_32B_ALL = 3, +}; + +enum encap_vtag { + CFA_BLD_ACT_ENCAP_VTAGS_PUSH_0 = 0, + CFA_BLD_ACT_ENCAP_VTAGS_PUSH_1, + CFA_BLD_ACT_ENCAP_VTAGS_PUSH_2 +}; + +enum encap_l3 { + /** Set to disable any L3 encapsulation + * processing, default + */ + CFA_BLD_ACT_ENCAP_L3_NONE = 0, + /** Set to enable L3 IPv4 encapsulation + */ + CFA_BLD_ACT_ENCAP_L3_IPV4 = 4, + /** Set to enable L3 IPv6 encapsulation + */ + CFA_BLD_ACT_ENCAP_L3_IPV6 = 5, + /** Set to enable L3 MPLS 8847 encapsulation + */ + CFA_BLD_ACT_ENCAP_L3_MPLS_8847 = 6, + /** Set to enable L3 MPLS 8848 encapsulation + */ + CFA_BLD_ACT_ENCAP_L3_MPLS_8848 = 7 +}; + +enum encap_tunnel { + /** Set to disable Tunnel header encapsulation + * processing, default + */ + CFA_BLD_ACT_ENCAP_TNL_NONE = 0, + /** Set to enable Tunnel Generic Full header + * encapsulation + */ + CFA_BLD_ACT_ENCAP_TNL_GENERIC_FULL, + /** Set to enable VXLAN header encapsulation + */ + CFA_BLD_ACT_ENCAP_TNL_VXLAN, + /** Set to enable NGE (VXLAN2) header encapsulation + */ + CFA_BLD_ACT_ENCAP_TNL_NGE, + /** Set to enable NVGRE header encapsulation + */ + CFA_BLD_ACT_ENCAP_TNL_NVGRE, + /** Set to enable GRE header encapsulation + */ + CFA_BLD_ACT_ENCAP_TNL_GRE, + /** Set to enable Generic header after Tunnel + * L4 encapsulation + */ + CFA_BLD_ACT_ENCAP_TNL_GENERIC_AFTER_TL4, + /** Set to enable Generic header after Tunnel + * encapsulation + */ + CFA_BLD_ACT_ENCAP_TNL_GENERIC_AFTER_TNL +}; + +enum source_rec_type { + /** Set to Source MAC Address + */ + CFA_BLD_SOURCE_MAC = 0, + /** Set to Source MAC and IPv4 Addresses + */ + CFA_BLD_SOURCE_MAC_IPV4 = 1, + /** Set to Source MAC and IPv6 Addresses + */ + CFA_BLD_SOURCE_MAC_IPV6 = 2, +}; + +/** + * From CFA phase 7.0 onwards, setting the modify vector bit + * 'ACT_MODIFY_TUNNEL_MODIFY' requires corresponding data fields to be + * set. This enum defines the parameters that determine the + * layout of this associated data fields. This structure + * is not used for versions older than CFA Phase 7.0 and setting + * the 'ACT_MODIFY_TUNNEL_MODIFY' bit will just delete the internal tunnel + */ +enum tunnel_modify_mode { + /* No change to tunnel protocol */ + CFA_BLD_ACT_MOD_TNL_NO_PROTO_CHANGE = 0, + /* 8-bit tunnel protocol change */ + CFA_BLD_ACT_MOD_TNL_8B_PROTO_CHANGE = 1, + /* 16-bit tunnel protocol change */ + CFA_BLD_ACT_MOD_TNL_16B_PROTO_CHANGE = 2, + CFA_BLD_ACT_MOD_TNL_MAX +}; + +/** + * Action object template structure + * + * Template structure presents data fields that are necessary to know + * at the beginning of Action Builder (AB) processing. Like before the + * AB compilation. One such example could be a template that is + * flexible in size (Encap Record) and the presence of these fields + * allows for determining the template size as well as where the + * fields are located in the record. + * + * The template may also present fields that are not made visible to + * the caller by way of the action fields. + * + * Template fields also allow for additional checking on user visible + * fields. One such example could be the encap pointer behavior on a + * CFA_BLD_ACT_OBJ_TYPE_ACT or CFA_BLD_ACT_OBJ_TYPE_ACT_SRAM. + */ +struct cfa_bld_action_template { + /** Action Object type + * + * Controls the type of the Action Template + */ + enum action_type obj_type; + + /** Action Control + * + * Controls the internals of the Action Template + * + * act is valid when: + * ((obj_type == CFA_BLD_ACT_OBJ_TYPE_FULL_ACT) + * || + * (obj_type == CFA_BLD_ACT_OBJ_TYPE_COMPACT_ACT)) + * + * Specifies whether each action is to be in-line or not. + */ + struct { + /** Set to true to enable statistics + */ + uint8_t stat_enable; + /** Set to true to enable statistics to be inlined + */ + uint8_t stat_inline; + /** Set to true to enable statistics 1 + */ + uint8_t stat1_enable; + /** Set to true to enable statistics 1 to be inlined + */ + uint8_t stat1_inline; + /** Set to true to enable encapsulation + */ + uint8_t encap_enable; + /** Set to true to enable encapsulation to be inlined + */ + uint8_t encap_inline; + /** Set to true to align the encap record to cache + * line + */ + uint8_t encap_align; + /** Set to true to source + */ + uint8_t source_enable; + /** Set to true to enable source to be inlined + */ + uint8_t source_inline; + /** Set to true to enable modfication + */ + uint8_t mod_enable; + /** Set to true to enable modify to be inlined + */ + uint8_t mod_inline; + /** Set to true to enable subsequent MCGs + */ + uint8_t mcg_subseq_enable; + } act; + + /** Statistic Control + * Controls the type of statistic the template is describing + * + * stat is valid when: + * ((obj_type == CFA_BLD_ACT_OBJ_TYPE_FULL_ACT) || + * (obj_type == CFA_BLD_ACT_OBJ_TYPE_COMPACT_ACT)) && + * act.stat_enable || act.stat_inline) + */ + struct { + enum stat_op op; + enum stat_type type; + } stat; + + /** Encap Control + * Controls the type of encapsulation the template is + * describing + * + * encap is valid when: + * ((obj_type == CFA_BLD_ACT_OBJ_TYPE_FULL_ACT) || + * (obj_type == CFA_BLD_ACT_OBJ_TYPE_COMPACT_ACT) && + * act.encap_enable || act.encap_inline) + */ + struct { + /** Set to true to enable L2 capability in the + * template + */ + uint8_t l2_enable; + /** vtag controls the Encap Vector - VTAG Encoding, 4 bits + * + *
    + *
  • CFA_BLD_ACT_ENCAP_VTAGS_PUSH_0, default, no VLAN + * Tags applied + *
  • CFA_BLD_ACT_ENCAP_VTAGS_PUSH_1, adds capability to + * set 1 VLAN Tag. Action Template compile adds + * the following field to the action object + * TF_ER_VLAN1 + *
  • CFA_BLD_ACT_ENCAP_VTAGS_PUSH_2, adds capability to + * set 2 VLAN Tags. Action Template compile adds + * the following fields to the action object + * TF_ER_VLAN1 and TF_ER_VLAN2 + *
+ */ + enum encap_vtag vtag; + + /* + * The remaining fields are NOT supported when + * direction is RX and ((obj_type == + * CFA_BLD_ACT_OBJ_TYPE_ACT) && act.encap_enable). + * cfa_bld_devops.act_compile_layout will perform the + * checking and skip remaining fields. + */ + /** L3 Encap controls the Encap Vector - L3 Encoding, + * 3 bits. Defines the type of L3 Encapsulation the + * template is describing. + *
    + *
  • CFA_BLD_ACT_ENCAP_L3_NONE, default, no L3 + * Encapsulation processing. + *
  • CFA_BLD_ACT_ENCAP_L3_IPV4, enables L3 IPv4 + * Encapsulation. + *
  • CFA_BLD_ACT_ENCAP_L3_IPV6, enables L3 IPv6 + * Encapsulation. + *
  • CFA_BLD_ACT_ENCAP_L3_MPLS_8847, enables L3 MPLS + * 8847 Encapsulation. + *
  • CFA_BLD_ACT_ENCAP_L3_MPLS_8848, enables L3 MPLS + * 8848 Encapsulation. + *
+ */ + enum encap_l3 l3; + +#define CFA_BLD_ACT_ENCAP_MAX_MPLS_LABELS 8 + /** 1-8 labels, valid when + * (l3 == CFA_BLD_ACT_ENCAP_L3_MPLS_8847) || + * (l3 == CFA_BLD_ACT_ENCAP_L3_MPLS_8848) + * + * MAX number of MPLS Labels 8. + */ + uint8_t l3_num_mpls_labels; + + /** Set to true to enable L4 capability in the + * template. + * + * true adds TF_EN_UDP_SRC_PORT and + * TF_EN_UDP_DST_PORT to the template. + */ + uint8_t l4_enable; + + /** Tunnel Encap controls the Encap Vector - Tunnel + * Encap, 3 bits. Defines the type of Tunnel + * encapsulation the template is describing + *
    + *
  • CFA_BLD_ACT_ENCAP_TNL_NONE, default, no Tunnel + * Encapsulation processing. + *
  • CFA_BLD_ACT_ENCAP_TNL_GENERIC_FULL + *
  • CFA_BLD_ACT_ENCAP_TNL_VXLAN. NOTE: Expects + * l4_enable set to true; + *
  • CFA_BLD_ACT_ENCAP_TNL_NGE. NOTE: Expects l4_enable + * set to true; + *
  • CFA_BLD_ACT_ENCAP_TNL_NVGRE. NOTE: only valid if + * l4_enable set to false. + *
  • CFA_BLD_ACT_ENCAP_TNL_GRE.NOTE: only valid if + * l4_enable set to false. + *
  • CFA_BLD_ACT_ENCAP_TNL_GENERIC_AFTER_TL4 + *
  • CFA_BLD_ACT_ENCAP_TNL_GENERIC_AFTER_TNL + *
+ */ + enum encap_tunnel tnl; + +#define CFA_BLD_ACT_ENCAP_MAX_TUNNEL_GENERIC_SIZE 128 + /** Number of bytes of generic tunnel header, + * valid when + * (tnl == CFA_BLD_ACT_ENCAP_TNL_GENERIC_FULL) || + * (tnl == CFA_BLD_ACT_ENCAP_TNL_GENERIC_AFTER_TL4) || + * (tnl == CFA_BLD_ACT_ENCAP_TNL_GENERIC_AFTER_TNL) + */ + uint8_t tnl_generic_size; + +#define CFA_BLD_ACT_ENCAP_MAX_OPLEN 15 + /** Number of 32b words of nge options, + * valid when + * (tnl == CFA_BLD_ACT_ENCAP_TNL_NGE) + */ + uint8_t tnl_nge_op_len; + + /** Set to true to enable SPDNIC tunnel + * template, + * valid when + * (tnl == CFA_BLD_ACT_ENCAP_TNL_GENERIC_FULL) + */ + uint8_t spdnic_enable; + + /** SPDNIC flags field, + * valid when + * (tnl == CFA_BLD_ACT_ENCAP_TNL_GENERIC_FULL) + */ + uint8_t tnl_spdnic_flags; + + /** Set to true to enable MAC/VLAN/IP/TNL overrides in the + * template + */ + bool encap_override; + /* Currently not planned */ + /* Custom Header */ + /* uint8_t custom_enable; */ + } encap; + + /** Modify Control + * + * Controls the type of the Modify Action the template is + * describing + * + * modify is valid when: + * ((obj_type == CFA_BLD_ACT_OBJ_TYPE_FULL_ACT) || + * (obj_type == CFA_BLD_ACT_OBJ_TYPE_COMPACT_ACT) && + * act.modify_enable || act.modify_inline) + */ +/** Set to enable Modify of Metadata + */ +#define CFA_BLD_ACT_MODIFY_META 0x1 +/** Set to enable Delete of Outer VLAN + */ +#define CFA_BLD_ACT_MODIFY_DEL_OVLAN 0x2 +/** Set to enable Delete of Inner VLAN + */ +#define CFA_BLD_ACT_MODIFY_DEL_IVLAN 0x4 +/** Set to enable Replace or Add of Outer VLAN + */ +#define CFA_BLD_ACT_MODIFY_REPL_ADD_OVLAN 0x8 +/** Set to enable Replace or Add of Inner VLAN + */ +#define CFA_BLD_ACT_MODIFY_REPL_ADD_IVLAN 0x10 +/** Set to enable Modify of TTL + */ +#define CFA_BLD_ACT_MODIFY_TTL_UPDATE 0x20 +/** Set to enable delete of INT Tunnel + */ +#define CFA_BLD_ACT_MODIFY_DEL_INT_TNL 0x40 +/** For phase 7.0 this bit can be used to modify the tunnel + * protocol in addition to deleting internal or outer tunnel + */ +#define CFA_BLD_ACT_MODIFY_TUNNEL_MODIFY CFA_BLD_ACT_MODIFY_DEL_INT_TNL +/** Set to enable Modify of Field + */ +#define CFA_BLD_ACT_MODIFY_FIELD 0x80 +/** Set to enable Modify of Destination MAC + */ +#define CFA_BLD_ACT_MODIFY_DMAC 0x100 +/** Set to enable Modify of Source MAC + */ +#define CFA_BLD_ACT_MODIFY_SMAC 0x200 +/** Set to enable Modify of Source IPv6 Address + */ +#define CFA_BLD_ACT_MODIFY_SRC_IPV6 0x400 +/** Set to enable Modify of Destination IPv6 Address + */ +#define CFA_BLD_ACT_MODIFY_DST_IPV6 0x800 +/** Set to enable Modify of Source IPv4 Address + */ +#define CFA_BLD_ACT_MODIFY_SRC_IPV4 0x1000 +/** Set to enable Modify of Destination IPv4 Address + */ +#define CFA_BLD_ACT_MODIFY_DST_IPV4 0x2000 +/** Set to enable Modify of L4 Source Port + */ +#define CFA_BLD_ACT_MODIFY_SRC_PORT 0x4000 +/** Set to enable Modify of L4 Destination Port + */ +#define CFA_BLD_ACT_MODIFY_DST_PORT 0x8000 + uint16_t modify; + +/** Set to enable Modify of KID + */ +#define CFA_BLD_ACT_MODIFY_FIELD_KID 0x1 + + /* Valid for phase 7.0 or higher */ + uint16_t field_modify; + + /* Valid for phase 7.0 or higher */ + enum tunnel_modify_mode tnl_mod_mode; + + /** Source Control + * + * Controls the type of the Source Action the template is + * describing + * + * source is valid when: + * ((obj_type == CFA_BLD_ACT_OBJ_TYPE_FULL_ACT) || + * (obj_type == CFA_BLD_ACT_OBJ_TYPE_COMPACT_ACT) && + * act.source_enable || act.source_inline) + */ + enum source_rec_type source; +}; + +/** + * Key template consists of key fields that can be enabled/disabled + * individually. + */ +struct cfa_key_template { + /** [in] Identify if the key template is for TCAM. If false, the + * key template is for EM. This field is mandantory for device that + * only support fix key formats. + */ + bool is_wc_tcam_key; + /** [in] Identify if the key template will be use for IPv6 Keys. + * + * Note: This is important for THOR2 as the field length for the FlowId + * is dependent on the L3 flow type. For THOR2 for IPv4 Keys, the Flow + * Id field is 16 bits, for all other types (IPv6, ARP, PTP, EAP, RoCE, + * FCoE, UPAR), the Flow Id field length is 20 bits. + */ + bool is_ipv6_key; + /** [in] key field enable field array, set 1 to the corresponding + * field enable to make a field valid + */ + uint8_t field_en[CFA_V3_KEY_MAX_FIELD_CNT]; +}; + +/** + * Action template consists of action fields that can be enabled/disabled + * individually. + */ +struct cfa_action_template { + /** [in] CFA version for the action template */ + enum cfa_ver hw_ver; + /** [in] action field enable field array, set 1 to the corresponding + * field enable to make a field valid + */ + uint8_t data[CFA_V3_ACT_MAX_TEMPLATE_SZ]; +}; + +/**@}*/ + +/**@}*/ + +#endif /* _CFA_BLD_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_devops.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_devops.h new file mode 100644 index 0000000000..64b5fc6b56 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_devops.h @@ -0,0 +1,297 @@ +/**************************************************************************** + * Copyright(c) 2021 - 2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_bld_devops.h + * + * @brief CFA Builder devops interface for host applications + */ + +#ifndef _CFA_BLD_DEVOPS_H_ +#define _CFA_BLD_DEVOPS_H_ + +#include + +#include "cfa_bld.h" +#include "cfa_bld_defs.h" + +struct cfa_bld_devops; + +/** + * @addtogroup CFA_BLD CFA Builder Library + * \ingroup CFA_V3 + * @{ + */ + +/** + * CFA device information + */ +struct cfa_bld_devinfo { + /** [out] CFA Builder operations function pointer table */ + const struct cfa_bld_devops *devops; +}; + +/** + * @name CFA_BLD CFA Builder Host Device OPS API + * CFA builder host specific API used by host CFA application to bind + * to different CFA devices and access device by using device OPS. + */ + +/**@{*/ +/** CFA bind builder API + * + * This API retrieves the CFA global device configuration. This API should be + * called first before doing any operations to CFA through API. The returned + * global device information should be referenced throughout the lifetime of + * the CFA application. + * + * @param[in] hw_ver + * hardware version of the CFA + * + * @param[out] dev_info + * CFA global device information + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int cfa_bld_bind(enum cfa_ver hw_ver, struct cfa_bld_devinfo *dev_info); + +/** CFA device specific function hooks structure + * + * The following device hooks can be defined; unless noted otherwise, they are + * optional and can be filled with a null pointer. The pupose of these hooks + * to support CFA device operations for different device variants. + */ +struct cfa_bld_devops { + /** Get CFA layout for hw fix format tables + * + * This API takes returns the CFA layout for a given resource type + * resource subtype and CFA direction. + * + * @param[in] rtype + * CFA HW resource type. Valid values are CFA_RTYPE_XXX + * + * @param[in] rsubtype + * CFA HW resource sub type for the given resource type 'rtype' + * Valid values are CFA_RSUBTYPE_XXX_YYY, where XXX is the resource + * type + * + * @param[in] dir + * CFA direction. RX/TX. Note that the returned layout is different + * for RX and TX, only for VEB and VSPT tables. For all tables, the + * layout is the same for both directions. + * + * @param[out] layout + * Pointer to the table layout to be returned + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + * @note example usage: To get L2 context TCAM table, use + * struct cfa_layout *l2ctxt_tcam_layout; + * devops->cfa_bld_get_table_layout(CFA_RTYPE_TCAM, + * CFA_RSUBTYPE_TCAM_L2CTX, + * CFA_TX, + * &l2ctxt_tcam_layout); + */ + int (*cfa_bld_get_table_layout)(enum cfa_resource_type rtype, + uint8_t rsubtype, enum cfa_dir dir, + struct cfa_layout **layout); + + /** Get CFA layout for HW remap tables + * + * This API takes returns the CFA remap layout for a given tcam + * resource sub type, remap type and CFA direction. + * + * @param[in] st + * CFA TCAM table sub types. Valid values are CFA_RSUBTYPE_TCAM_XXX + * + * @param[in] rmp_tt + * CFA Remap table type. See enum cfa_remap_tbl_type + * + * @param[in] dir + * CFA direction. RX/TX. + * + * @param[out] layout + * Pointer to the remap table layout to be returned + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + * @note example usage: To get Profiler TCAM Remap bypass table, use + * struct cfa_layout *prof_tcam_rmp_byp_layout; + * devops->cfa_bld_get_remap_table_layout(CFA_RSUBTYPE_TCAM_PROF_TCAM, + * CFA_REMAP_TBL_TYPE_BYPASS, + * CFA_TX, + * &prof_tcam_rmp_byp_layout); + */ + int (*cfa_bld_get_remap_table_layout)(enum cfa_resource_subtype_tcam st, + enum cfa_remap_tbl_type rmp_tt, + enum cfa_dir dir, + struct cfa_layout **layout); + + /** build key layout + * + * This API takes the user provided key template as input and + * compiles it into a key layout supported by the hardware. + * It is intended that an application will only compile a + * key layout once for the provided key template and then + * reference the key layout throughout the lifetime of that + * key template. + * + * @param[in] key_template + * A pointer to the key template + * + * @param[in,out] layout + * A pointer of the key layout + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ + int (*cfa_bld_key_compile_layout)(struct cfa_key_template *t, + struct cfa_key_layout *l); + + /** Print formatted key object + * + * This API prints in human readable form the data in a key + * object based upon the key layout provided. It also provides the + * option to provide a raw byte output. + * + * @param[in] stream + * Generally set to stdout (stderr possible) + * + * @param[in] key_obj + * A pointer to the key_obj to be displayed + * + * @param[in] key_layout + * A pointer to the key_layout indicating the key format + * + * @param[in] decode + * If set, decode the fields, if clear provide raw byte output. + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ + int (*cfa_bld_key_print_obj)(FILE *stream, struct cfa_key_obj *key_obj, + struct cfa_key_layout *key_layout, + bool decode); + + /** Transform key data with device specific control information + * + * This API inserts or strips device specific control information + * to/from a key object. + * + * @param[in] op + * specify key transform operations. + * + * @param[in] key_obj + * A pointer of the key object to be transformed + * + * @param[out] key_obj_out + * A pointer of the transformed key data object + * The updated bitlen for the transformed key is returned + * in the data_len_bits field of this object. + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ + int (*cfa_bld_key_transform)(enum cfa_key_ctrlops op, + struct cfa_key_obj *key_obj, + struct cfa_key_obj *key_obj_out); + + /** build action layout + * + * This API takes the user provided action template as input and + * compiles it into an action layout supported by the hardware. + * It is intended that an application will only compile an + * action layout once for the provided action template and then + * reference the action layout throughout the lifetime of that + * action template. + * + * @param[in] act_template + * A pointer to the action template + * + * @param[in,out] layout + * A pointer of the action layout + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ + int (*cfa_bld_act_compile_layout)(struct cfa_action_template *t, + struct cfa_action_layout *l); + + /** initialize action private fields + * + * This API provides the functionality to zero out the action + * object data fields and set pre-initialized private fields + * based on the layout. Any action object must be initialized + * using this API before any put and get APIs can be executed + * for an action object. + * + * @param[in,out] act_obj + * A pointer of the action object to be initialized + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ + int (*cfa_bld_action_init_obj)(struct cfa_action_obj *act_obj); + + /** compute inline action object pointers/offsets + * + * This API provides the functionality to compute and set + * pointers/offset to the inlined actions in an action record. + * This API is applicable only to the action object type that + * support inline actions. + * + * @param[in,out] act_obj + * A pointer of the action object to be initialized + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ + int (*cfa_bld_action_compute_ptr)(struct cfa_action_obj *obj); + + /** Print action object + * + * This API presents the action object in human readable + * format. + * + * + * @param[in] stream + * Generally set to stdout (stderr possible) + * + * @param[in,out] act_obj + * A pointer of the action object to be displayed + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ + int (*cfa_bld_action_print_obj)(FILE *stream, + struct cfa_action_obj *obj, + bool decode); + + /** Print field object + * + * This API prints out the raw field output + * + * @param[in] fld_obj + * A pointer fld_obj to be displayed + * + * @param[in] fld_layout + * A pointer to the cfa_layout indicating the field format + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ + int (*cfa_bld_fld_print_obj)(uint64_t *fld_obj, + struct cfa_layout *layout); +}; + +/**@}*/ + +/**@}*/ +#endif /* _CFA_BLD_DEVOPS_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_field_ids.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_field_ids.h new file mode 100644 index 0000000000..1860aa2e3e --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_field_ids.h @@ -0,0 +1,1542 @@ +/**************************************************************************** + * Copyright(c) 2021 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_bld_field_ids.h + * + * @brief Enumerations definitions for CFA HW table fields, Action record + * fields and Lookup Key (EM/WC-TCAM) fields. + * + * This file is independent of the CFA HW version and defines the + * superset of the enumeration values for table, action and EM/WC-TCAM + * bit fields. This file is meant for use by host applications that + * support multiple devices with different CFA Hw versions. + * + * These enum definitions should be updated whenever any of the + * definitions in the auto-generated header 'cfa_bld_pxx_field_ids.h' + * file gets any new enum values. + */ + +#ifndef _CFA_BLD_FIELD_IDS_H_ +#define _CFA_BLD_FIELD_IDS_H_ + +/** + * Lookup Field Range Check Range Memory Fields: + */ +enum cfa_bld_lkup_frc_profile_flds { + CFA_BLD_LKUP_FRC_PROFILE_FIELD_SEL_1_FLD = 0, + CFA_BLD_LKUP_FRC_PROFILE_RANGE_CHECK_1_FLD = 1, + CFA_BLD_LKUP_FRC_PROFILE_FIELD_SEL_0_FLD = 2, + CFA_BLD_LKUP_FRC_PROFILE_RANGE_CHECK_0_FLD = 3, + CFA_BLD_LKUP_FRC_PROFILE_MAX_FLD +}; + +/** + * Lookup Connection Tracking State Memory Fields: + */ +enum cfa_bld_lkup_ct_state_flds { + CFA_BLD_LKUP_CT_STATE_NOTIFY_FLD = 0, + CFA_BLD_LKUP_CT_STATE_NOTIFY_STATE_FLD = 1, + CFA_BLD_LKUP_CT_STATE_ACTION_FLD = 2, + CFA_BLD_LKUP_CT_STATE_TIMER_SELECT_FLD = 3, + CFA_BLD_LKUP_CT_STATE_TIMER_PRELOAD_FLD = 4, + CFA_BLD_LKUP_CT_STATE_MAX_FLD +}; + +/** + * Lookup Connection Tracking State Machine Rule Memory Fields: + */ +enum cfa_bld_lkup_ct_rule_flds { + CFA_BLD_LKUP_CT_RULE_VALID_FLD = 0, + CFA_BLD_LKUP_CT_RULE_MASK_FLD = 1, + CFA_BLD_LKUP_CT_RULE_PKT_NOT_BG_FLD = 2, + CFA_BLD_LKUP_CT_RULE_STATE_FLD = 3, + CFA_BLD_LKUP_CT_RULE_TCP_FLAGS_FLD = 4, + CFA_BLD_LKUP_CT_RULE_PROT_IS_TCP_FLD = 5, + CFA_BLD_LKUP_CT_RULE_MSB_UPDT_FLD = 6, + CFA_BLD_LKUP_CT_RULE_FLAGS_FAILED_FLD = 7, + CFA_BLD_LKUP_CT_RULE_WIN_FAILED_FLD = 8, + CFA_BLD_LKUP_CT_RULE_MAX_FLD +}; + +/** + * Lookup Connection Tracking State Machine Rule Record Memory Fields: + */ +enum cfa_bld_lkup_ct_rule_record_flds { + CFA_BLD_LKUP_CT_RULE_RECORD_ACTION_FLD = 0, + CFA_BLD_LKUP_CT_RULE_RECORD_NEXT_STATE_FLD = 1, + CFA_BLD_LKUP_CT_RULE_RECORD_SEND_FLD = 2, + CFA_BLD_LKUP_CT_RULE_RECORD_MAX_FLD +}; + +/** + * VEB Destination Bitmap Remap Table. Fields: + */ +enum cfa_bld_act_veb_rmp_flds { + CFA_BLD_ACT_VEB_RMP_MODE_FLD = 0, + CFA_BLD_ACT_VEB_RMP_ENABLE_FLD = 1, + CFA_BLD_ACT_VEB_RMP_BITMAP_FLD = 2, + CFA_BLD_ACT_VEB_RMP_MAX_FLD +}; + +/** + * Lookup Field Range Check Range Memory Fields: + */ +enum cfa_bld_lkup_frc_range_flds { + CFA_BLD_LKUP_FRC_RANGE_RANGE_LO_FLD = 0, + CFA_BLD_LKUP_FRC_RANGE_RANGE_HI_FLD = 1, + CFA_BLD_LKUP_FRC_RANGE_MAX_FLD +}; + +/** + * L2 Context TCAM. Fields: + */ +enum cfa_bld_prof_l2_ctxt_tcam_flds { + CFA_BLD_PROF_L2_CTXT_TCAM_VALID_FLD = 0, + CFA_BLD_PROF_L2_CTXT_TCAM_SPARE_FLD = 1, + CFA_BLD_PROF_L2_CTXT_TCAM_MPASS_CNT_FLD = 2, + CFA_BLD_PROF_L2_CTXT_TCAM_RCYC_FLD = 3, + CFA_BLD_PROF_L2_CTXT_TCAM_LOOPBACK_FLD = 4, + CFA_BLD_PROF_L2_CTXT_TCAM_SPIF_FLD = 5, + CFA_BLD_PROF_L2_CTXT_TCAM_PARIF_FLD = 6, + CFA_BLD_PROF_L2_CTXT_TCAM_SVIF_FLD = 7, + CFA_BLD_PROF_L2_CTXT_TCAM_METADATA_FLD = 8, + CFA_BLD_PROF_L2_CTXT_TCAM_L2_FUNC_FLD = 9, + CFA_BLD_PROF_L2_CTXT_TCAM_ROCE_FLD = 10, + CFA_BLD_PROF_L2_CTXT_TCAM_PURE_LLC_FLD = 11, + CFA_BLD_PROF_L2_CTXT_TCAM_OT_HDR_TYPE_FLD = 12, + CFA_BLD_PROF_L2_CTXT_TCAM_T_HDR_TYPE_FLD = 13, + CFA_BLD_PROF_L2_CTXT_TCAM_ID_CTXT_FLD = 14, + CFA_BLD_PROF_L2_CTXT_TCAM_MAC0_FLD = 15, + CFA_BLD_PROF_L2_CTXT_TCAM_MAC1_FLD = 16, + CFA_BLD_PROF_L2_CTXT_TCAM_VTAG_PRESENT_FLD = 17, + CFA_BLD_PROF_L2_CTXT_TCAM_TWO_VTAGS_FLD = 18, + CFA_BLD_PROF_L2_CTXT_TCAM_OVLAN_VID_FLD = 19, + CFA_BLD_PROF_L2_CTXT_TCAM_OVLAN_TPID_SEL_FLD = 20, + CFA_BLD_PROF_L2_CTXT_TCAM_IVLAN_VID_FLD = 21, + CFA_BLD_PROF_L2_CTXT_TCAM_IVLAN_TPID_SEL_FLD = 22, + CFA_BLD_PROF_L2_CTXT_TCAM_ETYPE_FLD = 23, + CFA_BLD_PROF_L2_CTXT_TCAM_MAX_FLD +}; + +/** + * Profiler Profile Lookup TCAM Fields: + */ +enum cfa_bld_prof_profile_tcam_flds { + CFA_BLD_PROF_PROFILE_TCAM_VALID_FLD = 0, + CFA_BLD_PROF_PROFILE_TCAM_SPARE_FLD = 1, + CFA_BLD_PROF_PROFILE_TCAM_LOOPBACK_FLD = 2, + CFA_BLD_PROF_PROFILE_TCAM_PKT_TYPE_FLD = 3, + CFA_BLD_PROF_PROFILE_TCAM_RCYC_FLD = 4, + CFA_BLD_PROF_PROFILE_TCAM_METADATA_FLD = 5, + CFA_BLD_PROF_PROFILE_TCAM_AGG_ERROR_FLD = 6, + CFA_BLD_PROF_PROFILE_TCAM_L2_FUNC_FLD = 7, + CFA_BLD_PROF_PROFILE_TCAM_PROF_FUNC_FLD = 8, + CFA_BLD_PROF_PROFILE_TCAM_HREC_NEXT_FLD = 9, + CFA_BLD_PROF_PROFILE_TCAM_INT_HDR_TYPE_FLD = 10, + CFA_BLD_PROF_PROFILE_TCAM_INT_HDR_GROUP_FLD = 11, + CFA_BLD_PROF_PROFILE_TCAM_INT_IFA_TAIL_FLD = 12, + CFA_BLD_PROF_PROFILE_TCAM_OTL2_HDR_VALID_FLD = 13, + CFA_BLD_PROF_PROFILE_TCAM_OTL2_HDR_TYPE_FLD = 14, + CFA_BLD_PROF_PROFILE_TCAM_OTL2_UC_MC_BC_FLD = 15, + CFA_BLD_PROF_PROFILE_TCAM_OTL2_VTAG_PRESENT_FLD = 16, + CFA_BLD_PROF_PROFILE_TCAM_OTL2_TWO_VTAGS_FLD = 17, + CFA_BLD_PROF_PROFILE_TCAM_OTL3_HDR_VALID_FLD = 18, + CFA_BLD_PROF_PROFILE_TCAM_OTL3_HDR_ERROR_FLD = 19, + CFA_BLD_PROF_PROFILE_TCAM_OTL3_HDR_TYPE_FLD = 20, + CFA_BLD_PROF_PROFILE_TCAM_OTL3_HDR_ISIP_FLD = 21, + CFA_BLD_PROF_PROFILE_TCAM_OTL4_HDR_VALID_FLD = 22, + CFA_BLD_PROF_PROFILE_TCAM_OTL4_HDR_ERROR_FLD = 23, + CFA_BLD_PROF_PROFILE_TCAM_OTL4_HDR_TYPE_FLD = 24, + CFA_BLD_PROF_PROFILE_TCAM_OTL4_HDR_IS_UDP_TCP_FLD = 25, + CFA_BLD_PROF_PROFILE_TCAM_OT_HDR_VALID_FLD = 26, + CFA_BLD_PROF_PROFILE_TCAM_OT_HDR_ERROR_FLD = 27, + CFA_BLD_PROF_PROFILE_TCAM_OT_HDR_TYPE_FLD = 28, + CFA_BLD_PROF_PROFILE_TCAM_OT_HDR_FLAGS_FLD = 29, + CFA_BLD_PROF_PROFILE_TCAM_TL2_HDR_VALID_FLD = 30, + CFA_BLD_PROF_PROFILE_TCAM_TL2_HDR_TYPE_FLD = 31, + CFA_BLD_PROF_PROFILE_TCAM_TL2_UC_MC_BC_FLD = 32, + CFA_BLD_PROF_PROFILE_TCAM_TL2_VTAG_PRESENT_FLD = 33, + CFA_BLD_PROF_PROFILE_TCAM_TL2_TWO_VTAGS_FLD = 34, + CFA_BLD_PROF_PROFILE_TCAM_TL3_HDR_VALID_FLD = 35, + CFA_BLD_PROF_PROFILE_TCAM_TL3_HDR_ERROR_FLD = 36, + CFA_BLD_PROF_PROFILE_TCAM_TL3_HDR_TYPE_FLD = 37, + CFA_BLD_PROF_PROFILE_TCAM_TL3_HDR_ISIP_FLD = 38, + CFA_BLD_PROF_PROFILE_TCAM_TL4_HDR_VALID_FLD = 39, + CFA_BLD_PROF_PROFILE_TCAM_TL4_HDR_ERROR_FLD = 40, + CFA_BLD_PROF_PROFILE_TCAM_TL4_HDR_TYPE_FLD = 41, + CFA_BLD_PROF_PROFILE_TCAM_TL4_HDR_IS_UDP_TCP_FLD = 42, + CFA_BLD_PROF_PROFILE_TCAM_TUN_HDR_VALID_FLD = 43, + CFA_BLD_PROF_PROFILE_TCAM_TUN_HDR_ERROR_FLD = 44, + CFA_BLD_PROF_PROFILE_TCAM_TUN_HDR_TYPE_FLD = 45, + CFA_BLD_PROF_PROFILE_TCAM_TUN_HDR_FLAGS_FLD = 46, + CFA_BLD_PROF_PROFILE_TCAM_L2_HDR_VALID_FLD = 47, + CFA_BLD_PROF_PROFILE_TCAM_L2_HDR_ERROR_FLD = 48, + CFA_BLD_PROF_PROFILE_TCAM_L2_HDR_TYPE_FLD = 49, + CFA_BLD_PROF_PROFILE_TCAM_L2_UC_MC_BC_FLD = 50, + CFA_BLD_PROF_PROFILE_TCAM_L2_VTAG_PRESENT_FLD = 51, + CFA_BLD_PROF_PROFILE_TCAM_L2_TWO_VTAGS_FLD = 52, + CFA_BLD_PROF_PROFILE_TCAM_L3_HDR_VALID_FLD = 53, + CFA_BLD_PROF_PROFILE_TCAM_L3_HDR_ERROR_FLD = 54, + CFA_BLD_PROF_PROFILE_TCAM_L3_HDR_TYPE_FLD = 55, + CFA_BLD_PROF_PROFILE_TCAM_L3_HDR_ISIP_FLD = 56, + CFA_BLD_PROF_PROFILE_TCAM_L3_PROT_FLD = 57, + CFA_BLD_PROF_PROFILE_TCAM_L4_HDR_VALID_FLD = 58, + CFA_BLD_PROF_PROFILE_TCAM_L4_HDR_ERROR_FLD = 59, + CFA_BLD_PROF_PROFILE_TCAM_L4_HDR_TYPE_FLD = 60, + CFA_BLD_PROF_PROFILE_TCAM_L4_HDR_IS_UDP_TCP_FLD = 61, + CFA_BLD_PROF_PROFILE_TCAM_L4_HDR_SUBTYPE_FLD = 62, + CFA_BLD_PROF_PROFILE_TCAM_L4_HDR_FLAGS_FLD = 63, + CFA_BLD_PROF_PROFILE_TCAM_L4_DCN_PRESENT_FLD = 64, + CFA_BLD_PROF_PROFILE_TCAM_MAX_FLD +}; + +/** + * Action VEB TCAM. TX Fields (VEB Remap Mode): + */ +enum cfa_bld_act_veb_tcam_tx_flds { + CFA_BLD_ACT_VEB_TCAM_TX_VALID_FLD = 0, + CFA_BLD_ACT_VEB_TCAM_TX_PARIF_IN_FLD = 1, + CFA_BLD_ACT_VEB_TCAM_TX_NUM_VTAGS_FLD = 2, + CFA_BLD_ACT_VEB_TCAM_TX_DMAC_FLD = 3, + CFA_BLD_ACT_VEB_TCAM_TX_OVID_FLD = 4, + CFA_BLD_ACT_VEB_TCAM_TX_IVID_FLD = 5, + CFA_BLD_ACT_VEB_TCAM_TX_MAX_FLD +}; + +/** + * RX Fields (Source Knockout Mode): + */ +enum cfa_bld_act_veb_tcam_rx_flds { + CFA_BLD_ACT_VEB_TCAM_RX_VALID_FLD = 0, + CFA_BLD_ACT_VEB_TCAM_RX_SPARE_FLD = 1, + CFA_BLD_ACT_VEB_TCAM_RX_PADDING_FLD = 2, + CFA_BLD_ACT_VEB_TCAM_RX_UNICAST_FLD = 3, + CFA_BLD_ACT_VEB_TCAM_RX_MULTICAST_FLD = 4, + CFA_BLD_ACT_VEB_TCAM_RX_BROADCAST_FLD = 5, + CFA_BLD_ACT_VEB_TCAM_RX_PFID_FLD = 6, + CFA_BLD_ACT_VEB_TCAM_RX_VFID_FLD = 7, + CFA_BLD_ACT_VEB_TCAM_RX_SMAC_FLD = 8, + CFA_BLD_ACT_VEB_TCAM_RX_MAX_FLD +}; + +/** + * Action Feature Chaining TCAM. + */ +enum cfa_bld_act_fc_tcam_flds { + CFA_BLD_ACT_FC_TCAM_FC_VALID_FLD = 0, + CFA_BLD_ACT_FC_TCAM_FC_RSVD_FLD = 1, + CFA_BLD_ACT_FC_TCAM_FC_METADATA_FLD = 2, + CFA_BLD_ACT_FC_TCAM_MAX_FLD +}; + +/** + * Feature Chaining TCAM Remap Table Fields: + */ +enum cfa_bld_act_fc_rmp_dr_flds { + CFA_BLD_ACT_FC_RMP_DR_METADATA_FLD = 0, + CFA_BLD_ACT_FC_RMP_DR_METAMASK_FLD = 1, + CFA_BLD_ACT_FC_RMP_DR_L2_FUNC_FLD = 2, + CFA_BLD_ACT_FC_RMP_DR_RSVD_FLD = 3, + CFA_BLD_ACT_FC_RMP_DR_MAX_FLD +}; + +/** + * Profile Input Lookup Table Memory Fields: + */ +enum cfa_bld_prof_ilt_dr_flds { + CFA_BLD_PROF_ILT_DR_ILT_META_EN_FLD = 0, + CFA_BLD_PROF_ILT_DR_META_PROF_FLD = 1, + CFA_BLD_PROF_ILT_DR_METADATA_FLD = 2, + CFA_BLD_PROF_ILT_DR_PARIF_FLD = 3, + CFA_BLD_PROF_ILT_DR_L2_FUNC_FLD = 4, + CFA_BLD_PROF_ILT_DR_EN_BD_META_FLD = 5, + CFA_BLD_PROF_ILT_DR_EN_BD_ACTION_FLD = 6, + CFA_BLD_PROF_ILT_DR_EN_ILT_DEST_FLD = 7, + CFA_BLD_PROF_ILT_DR_ILT_FWD_OP_FLD = 8, + CFA_BLD_PROF_ILT_DR_ILT_ACT_HINT_FLD = 9, + CFA_BLD_PROF_ILT_DR_ILT_SCOPE_FLD = 10, + CFA_BLD_PROF_ILT_DR_ILT_ACT_REC_PTR_FLD = 11, + CFA_BLD_PROF_ILT_DR_ILT_DESTINATION_FLD = 12, + CFA_BLD_PROF_ILT_DR_MAX_FLD +}; + +/** + * Profile Lookup TCAM Remap Table Fields: + */ +enum cfa_bld_prof_profile_rmp_dr_flds { + CFA_BLD_PROF_PROFILE_RMP_DR_PL_BYP_LKUP_EN_FLD = 0, + CFA_BLD_PROF_PROFILE_RMP_DR_EM_SEARCH_EN_FLD = 1, + CFA_BLD_PROF_PROFILE_RMP_DR_EM_PROFILE_ID_FLD = 2, + CFA_BLD_PROF_PROFILE_RMP_DR_EM_KEY_ID_FLD = 3, + CFA_BLD_PROF_PROFILE_RMP_DR_EM_SCOPE_FLD = 4, + CFA_BLD_PROF_PROFILE_RMP_DR_TCAM_SEARCH_EN_FLD = 5, + CFA_BLD_PROF_PROFILE_RMP_DR_TCAM_PROFILE_ID_FLD = 6, + CFA_BLD_PROF_PROFILE_RMP_DR_TCAM_KEY_ID_FLD = 7, + CFA_BLD_PROF_PROFILE_RMP_DR_TCAM_SCOPE_FLD = 8, + CFA_BLD_PROF_PROFILE_RMP_DR_MAX_FLD +}; + +/** + * PROF_PROFILE_RMP_DR_BYP + */ +enum cfa_bld_prof_profile_rmp_dr_byp_flds { + CFA_BLD_PROF_PROFILE_RMP_DR_BYP_PL_BYP_LKUP_EN_FLD = 0, + CFA_BLD_PROF_PROFILE_RMP_DR_BYP_RESERVED_FLD = 1, + CFA_BLD_PROF_PROFILE_RMP_DR_BYP_BYPASS_OP_FLD = 2, + CFA_BLD_PROF_PROFILE_RMP_DR_BYP_PL_ACT_HINT_FLD = 3, + CFA_BLD_PROF_PROFILE_RMP_DR_BYP_PL_SCOPE_FLD = 4, + CFA_BLD_PROF_PROFILE_RMP_DR_BYP_PL_ACT_REC_PTR_FLD = 5, + CFA_BLD_PROF_PROFILE_RMP_DR_BYP_MAX_FLD +}; + +/** + * VNIC-SVIF Properties Table Fields: TX SVIF Properties Table + */ +enum cfa_bld_act_vspt_dr_tx_flds { + CFA_BLD_ACT_VSPT_DR_TX_TPID_AS_CTL_FLD = 0, + CFA_BLD_ACT_VSPT_DR_TX_ALWD_TPID_FLD = 1, + CFA_BLD_ACT_VSPT_DR_TX_DFLT_TPID_FLD = 2, + CFA_BLD_ACT_VSPT_DR_TX_PRI_AS_CTL_FLD = 3, + CFA_BLD_ACT_VSPT_DR_TX_ALWD_PRI_FLD = 4, + CFA_BLD_ACT_VSPT_DR_TX_DFLT_PRI_FLD = 5, + CFA_BLD_ACT_VSPT_DR_TX_MIR_FLD = 6, + CFA_BLD_ACT_VSPT_DR_TX_MAX_FLD +}; + +/** + * RX VNIC Properties Table + */ +enum cfa_bld_act_vspt_dr_rx_flds { + CFA_BLD_ACT_VSPT_DR_RX_RSVD_FLD = 0, + CFA_BLD_ACT_VSPT_DR_RX_METAFMT_FLD = 1, + CFA_BLD_ACT_VSPT_DR_RX_FID_FLD = 2, + CFA_BLD_ACT_VSPT_DR_RX_MIR_FLD = 3, + CFA_BLD_ACT_VSPT_DR_RX_MAX_FLD +}; + +/** + * LAG ID Balance Table Fields: + */ +enum cfa_bld_act_lbt_dr_flds { + CFA_BLD_ACT_LBT_DR_DST_BMP_FLD = 0, + CFA_BLD_ACT_LBT_DR_MAX_FLD +}; + +/** + * L2 Context Lookup Remap Table Fields: + */ +enum cfa_bld_prof_l2_ctxt_rmp_dr_flds { + CFA_BLD_PROF_L2_CTXT_RMP_DR_PRSV_PARIF_FLD = 0, + CFA_BLD_PROF_L2_CTXT_RMP_DR_PARIF_FLD = 1, + CFA_BLD_PROF_L2_CTXT_RMP_DR_PRSV_L2IP_CTXT_FLD = 2, + CFA_BLD_PROF_L2_CTXT_RMP_DR_L2IP_CTXT_FLD = 3, + CFA_BLD_PROF_L2_CTXT_RMP_DR_PRSV_PROF_FUNC_FLD = 4, + CFA_BLD_PROF_L2_CTXT_RMP_DR_PROF_FUNC_FLD = 5, + CFA_BLD_PROF_L2_CTXT_RMP_DR_CTXT_OPCODE_FLD = 6, + CFA_BLD_PROF_L2_CTXT_RMP_DR_L2IP_META_ENB_FLD = 7, + CFA_BLD_PROF_L2_CTXT_RMP_DR_L2IP_META_FLD = 8, + CFA_BLD_PROF_L2_CTXT_RMP_DR_L2IP_ACT_ENB_FLD = 9, + CFA_BLD_PROF_L2_CTXT_RMP_DR_L2IP_ACT_DATA_FLD = 10, + CFA_BLD_PROF_L2_CTXT_RMP_DR_L2IP_RFS_ENB_FLD = 11, + CFA_BLD_PROF_L2_CTXT_RMP_DR_L2IP_RFS_DATA_FLD = 12, + CFA_BLD_PROF_L2_CTXT_RMP_DR_L2IP_DEST_ENB_FLD = 13, + CFA_BLD_PROF_L2_CTXT_RMP_DR_L2IP_DEST_DATA_FLD = 14, + CFA_BLD_PROF_L2_CTXT_RMP_DR_MAX_FLD +}; + +/** + * Multi Field Register. + */ +enum cfa_bld_act_fc_tcam_result_flds { + CFA_BLD_ACT_FC_TCAM_RESULT_SEARCH_RESULT_FLD = 0, + CFA_BLD_ACT_FC_TCAM_RESULT_UNUSED_0_FLD = 1, + CFA_BLD_ACT_FC_TCAM_RESULT_SEARCH_HIT_FLD = 2, + CFA_BLD_ACT_FC_TCAM_RESULT_MAX_FLD +}; + +/** + * Multi Field Register. + */ +enum cfa_bld_act_mirror_flds { + CFA_BLD_ACT_MIRROR_UNUSED_0_FLD = 0, + CFA_BLD_ACT_MIRROR_RELATIVE_FLD = 1, + CFA_BLD_ACT_MIRROR_HINT_FLD = 2, + CFA_BLD_ACT_MIRROR_SAMP_FLD = 3, + CFA_BLD_ACT_MIRROR_TRUNC_FLD = 4, + CFA_BLD_ACT_MIRROR_IGN_DROP_FLD = 5, + CFA_BLD_ACT_MIRROR_MODE_FLD = 6, + CFA_BLD_ACT_MIRROR_COND_FLD = 7, + CFA_BLD_ACT_MIRROR_AR_PTR_FLD = 8, + CFA_BLD_ACT_MIRROR_SAMP_CFG_FLD = 9, + CFA_BLD_ACT_MIRROR_MAX_FLD +}; + +/** + * WC LREC Lookup Record + */ +enum cfa_bld_wc_lrec_flds { + CFA_BLD_WC_LREC_METADATA_FLD = 0, + CFA_BLD_WC_LREC_META_PROF_FLD = 1, + CFA_BLD_WC_LREC_PROF_FUNC_FLD = 2, + CFA_BLD_WC_LREC_RECYCLE_DEST_FLD = 3, + CFA_BLD_WC_LREC_FC_PTR_FLD = 4, + CFA_BLD_WC_LREC_FC_TYPE_FLD = 5, + CFA_BLD_WC_LREC_FC_OP_FLD = 6, + CFA_BLD_WC_LREC_PATHS_M1_FLD = 7, + CFA_BLD_WC_LREC_ACT_REC_SIZE_FLD = 8, + CFA_BLD_WC_LREC_RING_TABLE_IDX_FLD = 9, + CFA_BLD_WC_LREC_DESTINATION_FLD = 10, + CFA_BLD_WC_LREC_ACT_REC_PTR_FLD = 11, + CFA_BLD_WC_LREC_ACT_HINT_FLD = 12, + CFA_BLD_WC_LREC_STRENGTH_FLD = 13, + CFA_BLD_WC_LREC_OPCODE_FLD = 14, + CFA_BLD_WC_LREC_EPOCH1_FLD = 15, + CFA_BLD_WC_LREC_EPOCH0_FLD = 16, + CFA_BLD_WC_LREC_REC_SIZE_FLD = 17, + CFA_BLD_WC_LREC_VALID_FLD = 18, + CFA_BLD_WC_LREC_MAX_FLD +}; + +/** + * EM LREC Lookup Record + */ +enum cfa_bld_em_lrec_flds { + CFA_BLD_EM_LREC_RANGE_IDX_FLD = 0, + CFA_BLD_EM_LREC_RANGE_PROFILE_FLD = 1, + CFA_BLD_EM_LREC_CREC_TIMER_VALUE_FLD = 2, + CFA_BLD_EM_LREC_CREC_STATE_FLD = 3, + CFA_BLD_EM_LREC_CREC_TCP_MSB_OPP_INIT_FLD = 4, + CFA_BLD_EM_LREC_CREC_TCP_MSB_OPP_FLD = 5, + CFA_BLD_EM_LREC_CREC_TCP_MSB_LOC_FLD = 6, + CFA_BLD_EM_LREC_CREC_TCP_WIN_FLD = 7, + CFA_BLD_EM_LREC_CREC_TCP_UPDT_EN_FLD = 8, + CFA_BLD_EM_LREC_CREC_TCP_DIR_FLD = 9, + CFA_BLD_EM_LREC_METADATA_FLD = 10, + CFA_BLD_EM_LREC_PROF_FUNC_FLD = 11, + CFA_BLD_EM_LREC_META_PROF_FLD = 12, + CFA_BLD_EM_LREC_RECYCLE_DEST_FLD = 13, + CFA_BLD_EM_LREC_FC_PTR_FLD = 14, + CFA_BLD_EM_LREC_FC_TYPE_FLD = 15, + CFA_BLD_EM_LREC_FC_OP_FLD = 16, + CFA_BLD_EM_LREC_PATHS_M1_FLD = 17, + CFA_BLD_EM_LREC_ACT_REC_SIZE_FLD = 18, + CFA_BLD_EM_LREC_RING_TABLE_IDX_FLD = 19, + CFA_BLD_EM_LREC_DESTINATION_FLD = 20, + CFA_BLD_EM_LREC_ACT_REC_PTR_FLD = 21, + CFA_BLD_EM_LREC_ACT_HINT_FLD = 22, + CFA_BLD_EM_LREC_STRENGTH_FLD = 23, + CFA_BLD_EM_LREC_OPCODE_FLD = 24, + CFA_BLD_EM_LREC_EPOCH1_FLD = 25, + CFA_BLD_EM_LREC_EPOCH0_FLD = 26, + CFA_BLD_EM_LREC_REC_SIZE_FLD = 27, + CFA_BLD_EM_LREC_VALID_FLD = 28, + CFA_BLD_EM_LREC_MAX_FLD +}; + +/** + * EM Lookup Bucket Format + */ +enum cfa_bld_em_bucket_flds { + CFA_BLD_EM_BUCKET_BIN0_ENTRY_FLD = 0, + CFA_BLD_EM_BUCKET_BIN0_HASH_MSBS_FLD = 1, + CFA_BLD_EM_BUCKET_BIN1_ENTRY_FLD = 2, + CFA_BLD_EM_BUCKET_BIN1_HASH_MSBS_FLD = 3, + CFA_BLD_EM_BUCKET_BIN2_ENTRY_FLD = 4, + CFA_BLD_EM_BUCKET_BIN2_HASH_MSBS_FLD = 5, + CFA_BLD_EM_BUCKET_BIN3_ENTRY_FLD = 6, + CFA_BLD_EM_BUCKET_BIN3_HASH_MSBS_FLD = 7, + CFA_BLD_EM_BUCKET_BIN4_ENTRY_FLD = 8, + CFA_BLD_EM_BUCKET_BIN4_HASH_MSBS_FLD = 9, + CFA_BLD_EM_BUCKET_BIN5_ENTRY_FLD = 10, + CFA_BLD_EM_BUCKET_BIN5_HASH_MSBS_FLD = 11, + CFA_BLD_EM_BUCKET_CHAIN_POINTER_FLD = 12, + CFA_BLD_EM_BUCKET_CHAIN_VALID_FLD = 13, + CFA_BLD_EM_BUCKET_MAX_FLD +}; + +/** + * Compact Action Record. The compact action record uses relative + * pointers to access needed data. This keeps the compact action record + * down to 64b. + */ +enum cfa_bld_compact_action_flds { + CFA_BLD_COMPACT_ACTION_TYPE_FLD = 0, + CFA_BLD_COMPACT_ACTION_DROP_FLD = 1, + CFA_BLD_COMPACT_ACTION_VLAN_DELETE_FLD = 2, + CFA_BLD_COMPACT_ACTION_DEST_FLD = 3, + CFA_BLD_COMPACT_ACTION_DEST_OP_FLD = 4, + CFA_BLD_COMPACT_ACTION_DECAP_FLD = 5, + CFA_BLD_COMPACT_ACTION_MIRRORING_FLD = 6, + CFA_BLD_COMPACT_ACTION_METER_PTR_FLD = 7, + CFA_BLD_COMPACT_ACTION_STAT0_OFF_FLD = 8, + CFA_BLD_COMPACT_ACTION_STAT0_OP_FLD = 9, + CFA_BLD_COMPACT_ACTION_STAT0_CTR_TYPE_FLD = 10, + CFA_BLD_COMPACT_ACTION_MOD_OFF_FLD = 11, + CFA_BLD_COMPACT_ACTION_ENC_OFF_FLD = 12, + CFA_BLD_COMPACT_ACTION_SRC_OFF_FLD = 13, + CFA_BLD_COMPACT_ACTION_UNUSED_0_FLD = 14, + CFA_BLD_COMPACT_ACTION_MAX_FLD +}; + +/** + * Full Action Record. The full action record uses full pointers to + * access needed data. It also allows access to all the action features. + * The Full Action record is 192b. + */ +enum cfa_bld_full_action_flds { + CFA_BLD_FULL_ACTION_TYPE_FLD = 0, + CFA_BLD_FULL_ACTION_DROP_FLD = 1, + CFA_BLD_FULL_ACTION_VLAN_DELETE_FLD = 2, + CFA_BLD_FULL_ACTION_DEST_FLD = 3, + CFA_BLD_FULL_ACTION_DEST_OP_FLD = 4, + CFA_BLD_FULL_ACTION_DECAP_FLD = 5, + CFA_BLD_FULL_ACTION_MIRRORING_FLD = 6, + CFA_BLD_FULL_ACTION_METER_PTR_FLD = 7, + CFA_BLD_FULL_ACTION_STAT0_PTR_FLD = 8, + CFA_BLD_FULL_ACTION_STAT0_OP_FLD = 9, + CFA_BLD_FULL_ACTION_STAT0_CTR_TYPE_FLD = 10, + CFA_BLD_FULL_ACTION_STAT1_PTR_FLD = 11, + CFA_BLD_FULL_ACTION_STAT1_OP_FLD = 12, + CFA_BLD_FULL_ACTION_STAT1_CTR_TYPE_FLD = 13, + CFA_BLD_FULL_ACTION_MOD_PTR_FLD = 14, + CFA_BLD_FULL_ACTION_ENC_PTR_FLD = 15, + CFA_BLD_FULL_ACTION_SRC_PTR_FLD = 16, + CFA_BLD_FULL_ACTION_UNUSED_0_FLD = 17, + CFA_BLD_FULL_ACTION_MAX_FLD +}; + +/** + * Multicast Group Action Record. This action is used to send the packet + * to multiple destinations. The MGC Action record is 256b. + */ +enum cfa_bld_mcg_action_flds { + CFA_BLD_MCG_ACTION_TYPE_FLD = 0, + CFA_BLD_MCG_ACTION_SRC_KO_EN_FLD = 1, + CFA_BLD_MCG_ACTION_UNUSED_0_FLD = 2, + CFA_BLD_MCG_ACTION_NEXT_PTR_FLD = 3, + CFA_BLD_MCG_ACTION_PTR0_ACT_HINT_FLD = 4, + CFA_BLD_MCG_ACTION_PTR0_ACT_REC_PTR_FLD = 5, + CFA_BLD_MCG_ACTION_PTR1_ACT_HINT_FLD = 6, + CFA_BLD_MCG_ACTION_PTR1_ACT_REC_PTR_FLD = 7, + CFA_BLD_MCG_ACTION_PTR2_ACT_HINT_FLD = 8, + CFA_BLD_MCG_ACTION_PTR2_ACT_REC_PTR_FLD = 9, + CFA_BLD_MCG_ACTION_PTR3_ACT_HINT_FLD = 10, + CFA_BLD_MCG_ACTION_PTR3_ACT_REC_PTR_FLD = 11, + CFA_BLD_MCG_ACTION_PTR4_ACT_HINT_FLD = 12, + CFA_BLD_MCG_ACTION_PTR4_ACT_REC_PTR_FLD = 13, + CFA_BLD_MCG_ACTION_PTR5_ACT_HINT_FLD = 14, + CFA_BLD_MCG_ACTION_PTR5_ACT_REC_PTR_FLD = 15, + CFA_BLD_MCG_ACTION_PTR6_ACT_HINT_FLD = 16, + CFA_BLD_MCG_ACTION_PTR6_ACT_REC_PTR_FLD = 17, + CFA_BLD_MCG_ACTION_PTR7_ACT_HINT_FLD = 18, + CFA_BLD_MCG_ACTION_PTR7_ACT_REC_PTR_FLD = 19, + CFA_BLD_MCG_ACTION_MAX_FLD +}; + +/** + * Multicast Group Action Record. This action is used to send the packet + * to multiple destinations. The MGC Action record is 256b. + */ +enum cfa_bld_mcg_subseq_action_flds { + CFA_BLD_MCG_SUBSEQ_ACTION_TYPE_FLD = 0, + CFA_BLD_MCG_SUBSEQ_ACTION_UNUSED_0_FLD = 1, + CFA_BLD_MCG_SUBSEQ_ACTION_NEXT_PTR_FLD = 2, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR0_ACT_HINT_FLD = 3, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR0_ACT_REC_PTR_FLD = 4, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR1_ACT_HINT_FLD = 5, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR1_ACT_REC_PTR_FLD = 6, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR2_ACT_HINT_FLD = 7, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR2_ACT_REC_PTR_FLD = 8, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR3_ACT_HINT_FLD = 9, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR3_ACT_REC_PTR_FLD = 10, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR4_ACT_HINT_FLD = 11, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR4_ACT_REC_PTR_FLD = 12, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR5_ACT_HINT_FLD = 13, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR5_ACT_REC_PTR_FLD = 14, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR6_ACT_HINT_FLD = 15, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR6_ACT_REC_PTR_FLD = 16, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR7_ACT_HINT_FLD = 17, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR7_ACT_REC_PTR_FLD = 18, + CFA_BLD_MCG_SUBSEQ_ACTION_MAX_FLD +}; + +/** + * Action Meter Formats + */ +enum cfa_bld_meters_flds { + CFA_BLD_METERS_BKT_C_FLD = 0, + CFA_BLD_METERS_BKT_E_FLD = 1, + CFA_BLD_METERS_FLAGS_MTR_VAL_FLD = 2, + CFA_BLD_METERS_FLAGS_ECN_RMP_EN_FLD = 3, + CFA_BLD_METERS_FLAGS_CF_FLD = 4, + CFA_BLD_METERS_FLAGS_PM_FLD = 5, + CFA_BLD_METERS_FLAGS_RFC2698_FLD = 6, + CFA_BLD_METERS_FLAGS_CBSM_FLD = 7, + CFA_BLD_METERS_FLAGS_EBSM_FLD = 8, + CFA_BLD_METERS_FLAGS_CBND_FLD = 9, + CFA_BLD_METERS_FLAGS_EBND_FLD = 10, + CFA_BLD_METERS_CBS_FLD = 11, + CFA_BLD_METERS_EBS_FLD = 12, + CFA_BLD_METERS_CIR_FLD = 13, + CFA_BLD_METERS_EIR_FLD = 14, + CFA_BLD_METERS_PROTECTION_SCOPE_FLD = 15, + CFA_BLD_METERS_PROTECTION_RSVD_FLD = 16, + CFA_BLD_METERS_PROTECTION_ENABLE_FLD = 17, + CFA_BLD_METERS_MAX_FLD +}; + +/** + * Enumeration for fkb + */ +enum cfa_bld_fkb_flds { + CFA_BLD_FKB_PROF_ID_FLD = 0, + CFA_BLD_FKB_L2CTXT_FLD = 1, + CFA_BLD_FKB_L2FUNC_FLD = 2, + CFA_BLD_FKB_PARIF_FLD = 3, + CFA_BLD_FKB_SPIF_FLD = 4, + CFA_BLD_FKB_SVIF_FLD = 5, + CFA_BLD_FKB_LCOS_FLD = 6, + CFA_BLD_FKB_META_HI_FLD = 7, + CFA_BLD_FKB_META_LO_FLD = 8, + CFA_BLD_FKB_RCYC_CNT_FLD = 9, + CFA_BLD_FKB_LOOPBACK_FLD = 10, + CFA_BLD_FKB_OTL2_TYPE_FLD = 11, + CFA_BLD_FKB_OTL2_DMAC_FLD = 12, + CFA_BLD_FKB_OTL2_SMAC_FLD = 13, + CFA_BLD_FKB_OTL2_DT_FLD = 14, + CFA_BLD_FKB_OTL2_SA_FLD = 15, + CFA_BLD_FKB_OTL2_NVT_FLD = 16, + CFA_BLD_FKB_OTL2_OVP_FLD = 17, + CFA_BLD_FKB_OTL2_OVD_FLD = 18, + CFA_BLD_FKB_OTL2_OVV_FLD = 19, + CFA_BLD_FKB_OTL2_OVT_FLD = 20, + CFA_BLD_FKB_OTL2_IVP_FLD = 21, + CFA_BLD_FKB_OTL2_IVD_FLD = 22, + CFA_BLD_FKB_OTL2_IVV_FLD = 23, + CFA_BLD_FKB_OTL2_IVT_FLD = 24, + CFA_BLD_FKB_OTL2_ETYPE_FLD = 25, + CFA_BLD_FKB_OTL3_TYPE_FLD = 26, + CFA_BLD_FKB_OTL3_SIP3_FLD = 27, + CFA_BLD_FKB_OTL3_SIP2_FLD = 28, + CFA_BLD_FKB_OTL3_SIP1_FLD = 29, + CFA_BLD_FKB_OTL3_SIP0_FLD = 30, + CFA_BLD_FKB_OTL3_DIP3_FLD = 31, + CFA_BLD_FKB_OTL3_DIP2_FLD = 32, + CFA_BLD_FKB_OTL3_DIP1_FLD = 33, + CFA_BLD_FKB_OTL3_DIP0_FLD = 34, + CFA_BLD_FKB_OTL3_TTL_FLD = 35, + CFA_BLD_FKB_OTL3_PROT_FLD = 36, + CFA_BLD_FKB_OTL3_FID_FLD = 37, + CFA_BLD_FKB_OTL3_QOS_FLD = 38, + CFA_BLD_FKB_OTL3_IEH_NONEXT_FLD = 39, + CFA_BLD_FKB_OTL3_IEH_SEP_FLD = 40, + CFA_BLD_FKB_OTL3_IEH_AUTH_FLD = 41, + CFA_BLD_FKB_OTL3_IEH_DEST_FLD = 42, + CFA_BLD_FKB_OTL3_IEH_FRAG_FLD = 43, + CFA_BLD_FKB_OTL3_IEH_RTHDR_FLD = 44, + CFA_BLD_FKB_OTL3_IEH_HOP_FLD = 45, + CFA_BLD_FKB_OTL3_IEH_1FRAG_FLD = 46, + CFA_BLD_FKB_OTL3_DF_FLD = 47, + CFA_BLD_FKB_OTL3_L3ERR_FLD = 48, + CFA_BLD_FKB_OTL4_TYPE_FLD = 49, + CFA_BLD_FKB_OTL4_SRC_FLD = 50, + CFA_BLD_FKB_OTL4_DST_FLD = 51, + CFA_BLD_FKB_OTL4_FLAGS_FLD = 52, + CFA_BLD_FKB_OTL4_SEQ_FLD = 53, + CFA_BLD_FKB_OTL4_PA_FLD = 54, + CFA_BLD_FKB_OTL4_OPT_FLD = 55, + CFA_BLD_FKB_OTL4_TCPTS_FLD = 56, + CFA_BLD_FKB_OTL4_ERR_FLD = 57, + CFA_BLD_FKB_OT_TYPE_FLD = 58, + CFA_BLD_FKB_OT_FLAGS_FLD = 59, + CFA_BLD_FKB_OT_IDS_FLD = 60, + CFA_BLD_FKB_OT_ID_FLD = 61, + CFA_BLD_FKB_OT_CTXTS_FLD = 62, + CFA_BLD_FKB_OT_CTXT_FLD = 63, + CFA_BLD_FKB_OT_QOS_FLD = 64, + CFA_BLD_FKB_OT_ERR_FLD = 65, + CFA_BLD_FKB_TL2_TYPE_FLD = 66, + CFA_BLD_FKB_TL2_DMAC_FLD = 67, + CFA_BLD_FKB_TL2_SMAC_FLD = 68, + CFA_BLD_FKB_TL2_DT_FLD = 69, + CFA_BLD_FKB_TL2_SA_FLD = 70, + CFA_BLD_FKB_TL2_NVT_FLD = 71, + CFA_BLD_FKB_TL2_OVP_FLD = 72, + CFA_BLD_FKB_TL2_OVD_FLD = 73, + CFA_BLD_FKB_TL2_OVV_FLD = 74, + CFA_BLD_FKB_TL2_OVT_FLD = 75, + CFA_BLD_FKB_TL2_IVP_FLD = 76, + CFA_BLD_FKB_TL2_IVD_FLD = 77, + CFA_BLD_FKB_TL2_IVV_FLD = 78, + CFA_BLD_FKB_TL2_IVT_FLD = 79, + CFA_BLD_FKB_TL2_ETYPE_FLD = 80, + CFA_BLD_FKB_TL3_TYPE_FLD = 81, + CFA_BLD_FKB_TL3_SIP3_FLD = 82, + CFA_BLD_FKB_TL3_SIP2_FLD = 83, + CFA_BLD_FKB_TL3_SIP1_FLD = 84, + CFA_BLD_FKB_TL3_SIP0_FLD = 85, + CFA_BLD_FKB_TL3_DIP3_FLD = 86, + CFA_BLD_FKB_TL3_DIP2_FLD = 87, + CFA_BLD_FKB_TL3_DIP1_FLD = 88, + CFA_BLD_FKB_TL3_DIP0_FLD = 89, + CFA_BLD_FKB_TL3_TTL_FLD = 90, + CFA_BLD_FKB_TL3_PROT_FLD = 91, + CFA_BLD_FKB_TL3_FID_FLD = 92, + CFA_BLD_FKB_TL3_QOS_FLD = 93, + CFA_BLD_FKB_TL3_IEH_NONEXT_FLD = 94, + CFA_BLD_FKB_TL3_IEH_SEP_FLD = 95, + CFA_BLD_FKB_TL3_IEH_AUTH_FLD = 96, + CFA_BLD_FKB_TL3_IEH_DEST_FLD = 97, + CFA_BLD_FKB_TL3_IEH_FRAG_FLD = 98, + CFA_BLD_FKB_TL3_IEH_RTHDR_FLD = 99, + CFA_BLD_FKB_TL3_IEH_HOP_FLD = 100, + CFA_BLD_FKB_TL3_IEH_1FRAG_FLD = 101, + CFA_BLD_FKB_TL3_DF_FLD = 102, + CFA_BLD_FKB_TL3_L3ERR_FLD = 103, + CFA_BLD_FKB_TL4_TYPE_FLD = 104, + CFA_BLD_FKB_TL4_SRC_FLD = 105, + CFA_BLD_FKB_TL4_DST_FLD = 106, + CFA_BLD_FKB_TL4_FLAGS_FLD = 107, + CFA_BLD_FKB_TL4_SEQ_FLD = 108, + CFA_BLD_FKB_TL4_PA_FLD = 109, + CFA_BLD_FKB_TL4_OPT_FLD = 110, + CFA_BLD_FKB_TL4_TCPTS_FLD = 111, + CFA_BLD_FKB_TL4_ERR_FLD = 112, + CFA_BLD_FKB_T_TYPE_FLD = 113, + CFA_BLD_FKB_T_FLAGS_FLD = 114, + CFA_BLD_FKB_T_IDS_FLD = 115, + CFA_BLD_FKB_T_ID_FLD = 116, + CFA_BLD_FKB_T_CTXTS_FLD = 117, + CFA_BLD_FKB_T_CTXT_FLD = 118, + CFA_BLD_FKB_T_QOS_FLD = 119, + CFA_BLD_FKB_T_ERR_FLD = 120, + CFA_BLD_FKB_L2_TYPE_FLD = 121, + CFA_BLD_FKB_L2_DMAC_FLD = 122, + CFA_BLD_FKB_L2_SMAC_FLD = 123, + CFA_BLD_FKB_L2_DT_FLD = 124, + CFA_BLD_FKB_L2_SA_FLD = 125, + CFA_BLD_FKB_L2_NVT_FLD = 126, + CFA_BLD_FKB_L2_OVP_FLD = 127, + CFA_BLD_FKB_L2_OVD_FLD = 128, + CFA_BLD_FKB_L2_OVV_FLD = 129, + CFA_BLD_FKB_L2_OVT_FLD = 130, + CFA_BLD_FKB_L2_IVP_FLD = 131, + CFA_BLD_FKB_L2_IVD_FLD = 132, + CFA_BLD_FKB_L2_IVV_FLD = 133, + CFA_BLD_FKB_L2_IVT_FLD = 134, + CFA_BLD_FKB_L2_ETYPE_FLD = 135, + CFA_BLD_FKB_L3_TYPE_FLD = 136, + CFA_BLD_FKB_L3_SIP3_FLD = 137, + CFA_BLD_FKB_L3_SIP2_FLD = 138, + CFA_BLD_FKB_L3_SIP1_FLD = 139, + CFA_BLD_FKB_L3_SIP0_FLD = 140, + CFA_BLD_FKB_L3_DIP3_FLD = 141, + CFA_BLD_FKB_L3_DIP2_FLD = 142, + CFA_BLD_FKB_L3_DIP1_FLD = 143, + CFA_BLD_FKB_L3_DIP0_FLD = 144, + CFA_BLD_FKB_L3_TTL_FLD = 145, + CFA_BLD_FKB_L3_PROT_FLD = 146, + CFA_BLD_FKB_L3_FID_FLD = 147, + CFA_BLD_FKB_L3_QOS_FLD = 148, + CFA_BLD_FKB_L3_IEH_NONEXT_FLD = 149, + CFA_BLD_FKB_L3_IEH_SEP_FLD = 150, + CFA_BLD_FKB_L3_IEH_AUTH_FLD = 151, + CFA_BLD_FKB_L3_IEH_DEST_FLD = 152, + CFA_BLD_FKB_L3_IEH_FRAG_FLD = 153, + CFA_BLD_FKB_L3_IEH_RTHDR_FLD = 154, + CFA_BLD_FKB_L3_IEH_HOP_FLD = 155, + CFA_BLD_FKB_L3_IEH_1FRAG_FLD = 156, + CFA_BLD_FKB_L3_DF_FLD = 157, + CFA_BLD_FKB_L3_L3ERR_FLD = 158, + CFA_BLD_FKB_L4_TYPE_FLD = 159, + CFA_BLD_FKB_L4_SRC_FLD = 160, + CFA_BLD_FKB_L4_DST_FLD = 161, + CFA_BLD_FKB_L4_FLAGS_FLD = 162, + CFA_BLD_FKB_L4_SEQ_FLD = 163, + CFA_BLD_FKB_L4_ACK_FLD = 164, + CFA_BLD_FKB_L4_WIN_FLD = 165, + CFA_BLD_FKB_L4_PA_FLD = 166, + CFA_BLD_FKB_L4_OPT_FLD = 167, + CFA_BLD_FKB_L4_TCPTS_FLD = 168, + CFA_BLD_FKB_L4_TSVAL_FLD = 169, + CFA_BLD_FKB_L4_TXECR_FLD = 170, + CFA_BLD_FKB_L4_ERR_FLD = 171, + CFA_BLD_FKB_MAX_FLD +}; + +/** + * Enumeration for wc tcam fkb + */ +enum cfa_bld_wc_tcam_fkb_flds { + CFA_BLD_WC_TCAM_FKB_PROF_ID_FLD = 0, + CFA_BLD_WC_TCAM_FKB_L2CTXT_FLD = 1, + CFA_BLD_WC_TCAM_FKB_L2FUNC_FLD = 2, + CFA_BLD_WC_TCAM_FKB_PARIF_FLD = 3, + CFA_BLD_WC_TCAM_FKB_SPIF_FLD = 4, + CFA_BLD_WC_TCAM_FKB_SVIF_FLD = 5, + CFA_BLD_WC_TCAM_FKB_LCOS_FLD = 6, + CFA_BLD_WC_TCAM_FKB_META_HI_FLD = 7, + CFA_BLD_WC_TCAM_FKB_META_LO_FLD = 8, + CFA_BLD_WC_TCAM_FKB_RCYC_CNT_FLD = 9, + CFA_BLD_WC_TCAM_FKB_LOOPBACK_FLD = 10, + CFA_BLD_WC_TCAM_FKB_OTL2_TYPE_FLD = 11, + CFA_BLD_WC_TCAM_FKB_OTL2_DMAC_FLD = 12, + CFA_BLD_WC_TCAM_FKB_OTL2_SMAC_FLD = 13, + CFA_BLD_WC_TCAM_FKB_OTL2_DT_FLD = 14, + CFA_BLD_WC_TCAM_FKB_OTL2_SA_FLD = 15, + CFA_BLD_WC_TCAM_FKB_OTL2_NVT_FLD = 16, + CFA_BLD_WC_TCAM_FKB_OTL2_OVP_FLD = 17, + CFA_BLD_WC_TCAM_FKB_OTL2_OVD_FLD = 18, + CFA_BLD_WC_TCAM_FKB_OTL2_OVV_FLD = 19, + CFA_BLD_WC_TCAM_FKB_OTL2_OVT_FLD = 20, + CFA_BLD_WC_TCAM_FKB_OTL2_IVP_FLD = 21, + CFA_BLD_WC_TCAM_FKB_OTL2_IVD_FLD = 22, + CFA_BLD_WC_TCAM_FKB_OTL2_IVV_FLD = 23, + CFA_BLD_WC_TCAM_FKB_OTL2_IVT_FLD = 24, + CFA_BLD_WC_TCAM_FKB_OTL2_ETYPE_FLD = 25, + CFA_BLD_WC_TCAM_FKB_OTL3_TYPE_FLD = 26, + CFA_BLD_WC_TCAM_FKB_OTL3_SIP3_FLD = 27, + CFA_BLD_WC_TCAM_FKB_OTL3_SIP2_FLD = 28, + CFA_BLD_WC_TCAM_FKB_OTL3_SIP1_FLD = 29, + CFA_BLD_WC_TCAM_FKB_OTL3_SIP0_FLD = 30, + CFA_BLD_WC_TCAM_FKB_OTL3_DIP3_FLD = 31, + CFA_BLD_WC_TCAM_FKB_OTL3_DIP2_FLD = 32, + CFA_BLD_WC_TCAM_FKB_OTL3_DIP1_FLD = 33, + CFA_BLD_WC_TCAM_FKB_OTL3_DIP0_FLD = 34, + CFA_BLD_WC_TCAM_FKB_OTL3_TTL_FLD = 35, + CFA_BLD_WC_TCAM_FKB_OTL3_PROT_FLD = 36, + CFA_BLD_WC_TCAM_FKB_OTL3_FID_FLD = 37, + CFA_BLD_WC_TCAM_FKB_OTL3_QOS_FLD = 38, + CFA_BLD_WC_TCAM_FKB_OTL3_IEH_NONEXT_FLD = 39, + CFA_BLD_WC_TCAM_FKB_OTL3_IEH_SEP_FLD = 40, + CFA_BLD_WC_TCAM_FKB_OTL3_IEH_AUTH_FLD = 41, + CFA_BLD_WC_TCAM_FKB_OTL3_IEH_DEST_FLD = 42, + CFA_BLD_WC_TCAM_FKB_OTL3_IEH_FRAG_FLD = 43, + CFA_BLD_WC_TCAM_FKB_OTL3_IEH_RTHDR_FLD = 44, + CFA_BLD_WC_TCAM_FKB_OTL3_IEH_HOP_FLD = 45, + CFA_BLD_WC_TCAM_FKB_OTL3_IEH_1FRAG_FLD = 46, + CFA_BLD_WC_TCAM_FKB_OTL3_DF_FLD = 47, + CFA_BLD_WC_TCAM_FKB_OTL3_L3ERR_FLD = 48, + CFA_BLD_WC_TCAM_FKB_OTL4_TYPE_FLD = 49, + CFA_BLD_WC_TCAM_FKB_OTL4_SRC_FLD = 50, + CFA_BLD_WC_TCAM_FKB_OTL4_DST_FLD = 51, + CFA_BLD_WC_TCAM_FKB_OTL4_FLAGS_FLD = 52, + CFA_BLD_WC_TCAM_FKB_OTL4_SEQ_FLD = 53, + CFA_BLD_WC_TCAM_FKB_OTL4_PA_FLD = 54, + CFA_BLD_WC_TCAM_FKB_OTL4_OPT_FLD = 55, + CFA_BLD_WC_TCAM_FKB_OTL4_TCPTS_FLD = 56, + CFA_BLD_WC_TCAM_FKB_OTL4_ERR_FLD = 57, + CFA_BLD_WC_TCAM_FKB_OT_TYPE_FLD = 58, + CFA_BLD_WC_TCAM_FKB_OT_FLAGS_FLD = 59, + CFA_BLD_WC_TCAM_FKB_OT_IDS_FLD = 60, + CFA_BLD_WC_TCAM_FKB_OT_ID_FLD = 61, + CFA_BLD_WC_TCAM_FKB_OT_CTXTS_FLD = 62, + CFA_BLD_WC_TCAM_FKB_OT_CTXT_FLD = 63, + CFA_BLD_WC_TCAM_FKB_OT_QOS_FLD = 64, + CFA_BLD_WC_TCAM_FKB_OT_ERR_FLD = 65, + CFA_BLD_WC_TCAM_FKB_TL2_TYPE_FLD = 66, + CFA_BLD_WC_TCAM_FKB_TL2_DMAC_FLD = 67, + CFA_BLD_WC_TCAM_FKB_TL2_SMAC_FLD = 68, + CFA_BLD_WC_TCAM_FKB_TL2_DT_FLD = 69, + CFA_BLD_WC_TCAM_FKB_TL2_SA_FLD = 70, + CFA_BLD_WC_TCAM_FKB_TL2_NVT_FLD = 71, + CFA_BLD_WC_TCAM_FKB_TL2_OVP_FLD = 72, + CFA_BLD_WC_TCAM_FKB_TL2_OVD_FLD = 73, + CFA_BLD_WC_TCAM_FKB_TL2_OVV_FLD = 74, + CFA_BLD_WC_TCAM_FKB_TL2_OVT_FLD = 75, + CFA_BLD_WC_TCAM_FKB_TL2_IVP_FLD = 76, + CFA_BLD_WC_TCAM_FKB_TL2_IVD_FLD = 77, + CFA_BLD_WC_TCAM_FKB_TL2_IVV_FLD = 78, + CFA_BLD_WC_TCAM_FKB_TL2_IVT_FLD = 79, + CFA_BLD_WC_TCAM_FKB_TL2_ETYPE_FLD = 80, + CFA_BLD_WC_TCAM_FKB_TL3_TYPE_FLD = 81, + CFA_BLD_WC_TCAM_FKB_TL3_SIP3_FLD = 82, + CFA_BLD_WC_TCAM_FKB_TL3_SIP2_FLD = 83, + CFA_BLD_WC_TCAM_FKB_TL3_SIP1_FLD = 84, + CFA_BLD_WC_TCAM_FKB_TL3_SIP0_FLD = 85, + CFA_BLD_WC_TCAM_FKB_TL3_DIP3_FLD = 86, + CFA_BLD_WC_TCAM_FKB_TL3_DIP2_FLD = 87, + CFA_BLD_WC_TCAM_FKB_TL3_DIP1_FLD = 88, + CFA_BLD_WC_TCAM_FKB_TL3_DIP0_FLD = 89, + CFA_BLD_WC_TCAM_FKB_TL3_TTL_FLD = 90, + CFA_BLD_WC_TCAM_FKB_TL3_PROT_FLD = 91, + CFA_BLD_WC_TCAM_FKB_TL3_FID_FLD = 92, + CFA_BLD_WC_TCAM_FKB_TL3_QOS_FLD = 93, + CFA_BLD_WC_TCAM_FKB_TL3_IEH_NONEXT_FLD = 94, + CFA_BLD_WC_TCAM_FKB_TL3_IEH_SEP_FLD = 95, + CFA_BLD_WC_TCAM_FKB_TL3_IEH_AUTH_FLD = 96, + CFA_BLD_WC_TCAM_FKB_TL3_IEH_DEST_FLD = 97, + CFA_BLD_WC_TCAM_FKB_TL3_IEH_FRAG_FLD = 98, + CFA_BLD_WC_TCAM_FKB_TL3_IEH_RTHDR_FLD = 99, + CFA_BLD_WC_TCAM_FKB_TL3_IEH_HOP_FLD = 100, + CFA_BLD_WC_TCAM_FKB_TL3_IEH_1FRAG_FLD = 101, + CFA_BLD_WC_TCAM_FKB_TL3_DF_FLD = 102, + CFA_BLD_WC_TCAM_FKB_TL3_L3ERR_FLD = 103, + CFA_BLD_WC_TCAM_FKB_TL4_TYPE_FLD = 104, + CFA_BLD_WC_TCAM_FKB_TL4_SRC_FLD = 105, + CFA_BLD_WC_TCAM_FKB_TL4_DST_FLD = 106, + CFA_BLD_WC_TCAM_FKB_TL4_FLAGS_FLD = 107, + CFA_BLD_WC_TCAM_FKB_TL4_SEQ_FLD = 108, + CFA_BLD_WC_TCAM_FKB_TL4_PA_FLD = 109, + CFA_BLD_WC_TCAM_FKB_TL4_OPT_FLD = 110, + CFA_BLD_WC_TCAM_FKB_TL4_TCPTS_FLD = 111, + CFA_BLD_WC_TCAM_FKB_TL4_ERR_FLD = 112, + CFA_BLD_WC_TCAM_FKB_T_TYPE_FLD = 113, + CFA_BLD_WC_TCAM_FKB_T_FLAGS_FLD = 114, + CFA_BLD_WC_TCAM_FKB_T_IDS_FLD = 115, + CFA_BLD_WC_TCAM_FKB_T_ID_FLD = 116, + CFA_BLD_WC_TCAM_FKB_T_CTXTS_FLD = 117, + CFA_BLD_WC_TCAM_FKB_T_CTXT_FLD = 118, + CFA_BLD_WC_TCAM_FKB_T_QOS_FLD = 119, + CFA_BLD_WC_TCAM_FKB_T_ERR_FLD = 120, + CFA_BLD_WC_TCAM_FKB_L2_TYPE_FLD = 121, + CFA_BLD_WC_TCAM_FKB_L2_DMAC_FLD = 122, + CFA_BLD_WC_TCAM_FKB_L2_SMAC_FLD = 123, + CFA_BLD_WC_TCAM_FKB_L2_DT_FLD = 124, + CFA_BLD_WC_TCAM_FKB_L2_SA_FLD = 125, + CFA_BLD_WC_TCAM_FKB_L2_NVT_FLD = 126, + CFA_BLD_WC_TCAM_FKB_L2_OVP_FLD = 127, + CFA_BLD_WC_TCAM_FKB_L2_OVD_FLD = 128, + CFA_BLD_WC_TCAM_FKB_L2_OVV_FLD = 129, + CFA_BLD_WC_TCAM_FKB_L2_OVT_FLD = 130, + CFA_BLD_WC_TCAM_FKB_L2_IVP_FLD = 131, + CFA_BLD_WC_TCAM_FKB_L2_IVD_FLD = 132, + CFA_BLD_WC_TCAM_FKB_L2_IVV_FLD = 133, + CFA_BLD_WC_TCAM_FKB_L2_IVT_FLD = 134, + CFA_BLD_WC_TCAM_FKB_L2_ETYPE_FLD = 135, + CFA_BLD_WC_TCAM_FKB_L3_TYPE_FLD = 136, + CFA_BLD_WC_TCAM_FKB_L3_SIP3_FLD = 137, + CFA_BLD_WC_TCAM_FKB_L3_SIP2_FLD = 138, + CFA_BLD_WC_TCAM_FKB_L3_SIP1_FLD = 139, + CFA_BLD_WC_TCAM_FKB_L3_SIP0_FLD = 140, + CFA_BLD_WC_TCAM_FKB_L3_DIP3_FLD = 141, + CFA_BLD_WC_TCAM_FKB_L3_DIP2_FLD = 142, + CFA_BLD_WC_TCAM_FKB_L3_DIP1_FLD = 143, + CFA_BLD_WC_TCAM_FKB_L3_DIP0_FLD = 144, + CFA_BLD_WC_TCAM_FKB_L3_TTL_FLD = 145, + CFA_BLD_WC_TCAM_FKB_L3_PROT_FLD = 146, + CFA_BLD_WC_TCAM_FKB_L3_FID_FLD = 147, + CFA_BLD_WC_TCAM_FKB_L3_QOS_FLD = 148, + CFA_BLD_WC_TCAM_FKB_L3_IEH_NONEXT_FLD = 149, + CFA_BLD_WC_TCAM_FKB_L3_IEH_SEP_FLD = 150, + CFA_BLD_WC_TCAM_FKB_L3_IEH_AUTH_FLD = 151, + CFA_BLD_WC_TCAM_FKB_L3_IEH_DEST_FLD = 152, + CFA_BLD_WC_TCAM_FKB_L3_IEH_FRAG_FLD = 153, + CFA_BLD_WC_TCAM_FKB_L3_IEH_RTHDR_FLD = 154, + CFA_BLD_WC_TCAM_FKB_L3_IEH_HOP_FLD = 155, + CFA_BLD_WC_TCAM_FKB_L3_IEH_1FRAG_FLD = 156, + CFA_BLD_WC_TCAM_FKB_L3_DF_FLD = 157, + CFA_BLD_WC_TCAM_FKB_L3_L3ERR_FLD = 158, + CFA_BLD_WC_TCAM_FKB_L4_TYPE_FLD = 159, + CFA_BLD_WC_TCAM_FKB_L4_SRC_FLD = 160, + CFA_BLD_WC_TCAM_FKB_L4_DST_FLD = 161, + CFA_BLD_WC_TCAM_FKB_L4_FLAGS_FLD = 162, + CFA_BLD_WC_TCAM_FKB_L4_SEQ_FLD = 163, + CFA_BLD_WC_TCAM_FKB_L4_ACK_FLD = 164, + CFA_BLD_WC_TCAM_FKB_L4_WIN_FLD = 165, + CFA_BLD_WC_TCAM_FKB_L4_PA_FLD = 166, + CFA_BLD_WC_TCAM_FKB_L4_OPT_FLD = 167, + CFA_BLD_WC_TCAM_FKB_L4_TCPTS_FLD = 168, + CFA_BLD_WC_TCAM_FKB_L4_TSVAL_FLD = 169, + CFA_BLD_WC_TCAM_FKB_L4_TXECR_FLD = 170, + CFA_BLD_WC_TCAM_FKB_L4_ERR_FLD = 171, + CFA_BLD_WC_TCAM_FKB_MAX_FLD +}; + +/** + * Enumeration for em fkb + */ +enum cfa_bld_em_fkb_flds { + CFA_BLD_EM_FKB_PROF_ID_FLD = 0, + CFA_BLD_EM_FKB_L2CTXT_FLD = 1, + CFA_BLD_EM_FKB_L2FUNC_FLD = 2, + CFA_BLD_EM_FKB_PARIF_FLD = 3, + CFA_BLD_EM_FKB_SPIF_FLD = 4, + CFA_BLD_EM_FKB_SVIF_FLD = 5, + CFA_BLD_EM_FKB_LCOS_FLD = 6, + CFA_BLD_EM_FKB_META_HI_FLD = 7, + CFA_BLD_EM_FKB_META_LO_FLD = 8, + CFA_BLD_EM_FKB_RCYC_CNT_FLD = 9, + CFA_BLD_EM_FKB_LOOPBACK_FLD = 10, + CFA_BLD_EM_FKB_OTL2_TYPE_FLD = 11, + CFA_BLD_EM_FKB_OTL2_DMAC_FLD = 12, + CFA_BLD_EM_FKB_OTL2_SMAC_FLD = 13, + CFA_BLD_EM_FKB_OTL2_DT_FLD = 14, + CFA_BLD_EM_FKB_OTL2_SA_FLD = 15, + CFA_BLD_EM_FKB_OTL2_NVT_FLD = 16, + CFA_BLD_EM_FKB_OTL2_OVP_FLD = 17, + CFA_BLD_EM_FKB_OTL2_OVD_FLD = 18, + CFA_BLD_EM_FKB_OTL2_OVV_FLD = 19, + CFA_BLD_EM_FKB_OTL2_OVT_FLD = 20, + CFA_BLD_EM_FKB_OTL2_IVP_FLD = 21, + CFA_BLD_EM_FKB_OTL2_IVD_FLD = 22, + CFA_BLD_EM_FKB_OTL2_IVV_FLD = 23, + CFA_BLD_EM_FKB_OTL2_IVT_FLD = 24, + CFA_BLD_EM_FKB_OTL2_ETYPE_FLD = 25, + CFA_BLD_EM_FKB_OTL3_TYPE_FLD = 26, + CFA_BLD_EM_FKB_OTL3_SIP3_FLD = 27, + CFA_BLD_EM_FKB_OTL3_SIP2_FLD = 28, + CFA_BLD_EM_FKB_OTL3_SIP1_FLD = 29, + CFA_BLD_EM_FKB_OTL3_SIP0_FLD = 30, + CFA_BLD_EM_FKB_OTL3_DIP3_FLD = 31, + CFA_BLD_EM_FKB_OTL3_DIP2_FLD = 32, + CFA_BLD_EM_FKB_OTL3_DIP1_FLD = 33, + CFA_BLD_EM_FKB_OTL3_DIP0_FLD = 34, + CFA_BLD_EM_FKB_OTL3_TTL_FLD = 35, + CFA_BLD_EM_FKB_OTL3_PROT_FLD = 36, + CFA_BLD_EM_FKB_OTL3_FID_FLD = 37, + CFA_BLD_EM_FKB_OTL3_QOS_FLD = 38, + CFA_BLD_EM_FKB_OTL3_IEH_NONEXT_FLD = 39, + CFA_BLD_EM_FKB_OTL3_IEH_SEP_FLD = 40, + CFA_BLD_EM_FKB_OTL3_IEH_AUTH_FLD = 41, + CFA_BLD_EM_FKB_OTL3_IEH_DEST_FLD = 42, + CFA_BLD_EM_FKB_OTL3_IEH_FRAG_FLD = 43, + CFA_BLD_EM_FKB_OTL3_IEH_RTHDR_FLD = 44, + CFA_BLD_EM_FKB_OTL3_IEH_HOP_FLD = 45, + CFA_BLD_EM_FKB_OTL3_IEH_1FRAG_FLD = 46, + CFA_BLD_EM_FKB_OTL3_DF_FLD = 47, + CFA_BLD_EM_FKB_OTL3_L3ERR_FLD = 48, + CFA_BLD_EM_FKB_OTL4_TYPE_FLD = 49, + CFA_BLD_EM_FKB_OTL4_SRC_FLD = 50, + CFA_BLD_EM_FKB_OTL4_DST_FLD = 51, + CFA_BLD_EM_FKB_OTL4_FLAGS_FLD = 52, + CFA_BLD_EM_FKB_OTL4_SEQ_FLD = 53, + CFA_BLD_EM_FKB_OTL4_PA_FLD = 54, + CFA_BLD_EM_FKB_OTL4_OPT_FLD = 55, + CFA_BLD_EM_FKB_OTL4_TCPTS_FLD = 56, + CFA_BLD_EM_FKB_OTL4_ERR_FLD = 57, + CFA_BLD_EM_FKB_OT_TYPE_FLD = 58, + CFA_BLD_EM_FKB_OT_FLAGS_FLD = 59, + CFA_BLD_EM_FKB_OT_IDS_FLD = 60, + CFA_BLD_EM_FKB_OT_ID_FLD = 61, + CFA_BLD_EM_FKB_OT_CTXTS_FLD = 62, + CFA_BLD_EM_FKB_OT_CTXT_FLD = 63, + CFA_BLD_EM_FKB_OT_QOS_FLD = 64, + CFA_BLD_EM_FKB_OT_ERR_FLD = 65, + CFA_BLD_EM_FKB_TL2_TYPE_FLD = 66, + CFA_BLD_EM_FKB_TL2_DMAC_FLD = 67, + CFA_BLD_EM_FKB_TL2_SMAC_FLD = 68, + CFA_BLD_EM_FKB_TL2_DT_FLD = 69, + CFA_BLD_EM_FKB_TL2_SA_FLD = 70, + CFA_BLD_EM_FKB_TL2_NVT_FLD = 71, + CFA_BLD_EM_FKB_TL2_OVP_FLD = 72, + CFA_BLD_EM_FKB_TL2_OVD_FLD = 73, + CFA_BLD_EM_FKB_TL2_OVV_FLD = 74, + CFA_BLD_EM_FKB_TL2_OVT_FLD = 75, + CFA_BLD_EM_FKB_TL2_IVP_FLD = 76, + CFA_BLD_EM_FKB_TL2_IVD_FLD = 77, + CFA_BLD_EM_FKB_TL2_IVV_FLD = 78, + CFA_BLD_EM_FKB_TL2_IVT_FLD = 79, + CFA_BLD_EM_FKB_TL2_ETYPE_FLD = 80, + CFA_BLD_EM_FKB_TL3_TYPE_FLD = 81, + CFA_BLD_EM_FKB_TL3_SIP3_FLD = 82, + CFA_BLD_EM_FKB_TL3_SIP2_FLD = 83, + CFA_BLD_EM_FKB_TL3_SIP1_FLD = 84, + CFA_BLD_EM_FKB_TL3_SIP0_FLD = 85, + CFA_BLD_EM_FKB_TL3_DIP3_FLD = 86, + CFA_BLD_EM_FKB_TL3_DIP2_FLD = 87, + CFA_BLD_EM_FKB_TL3_DIP1_FLD = 88, + CFA_BLD_EM_FKB_TL3_DIP0_FLD = 89, + CFA_BLD_EM_FKB_TL3_TTL_FLD = 90, + CFA_BLD_EM_FKB_TL3_PROT_FLD = 91, + CFA_BLD_EM_FKB_TL3_FID_FLD = 92, + CFA_BLD_EM_FKB_TL3_QOS_FLD = 93, + CFA_BLD_EM_FKB_TL3_IEH_NONEXT_FLD = 94, + CFA_BLD_EM_FKB_TL3_IEH_SEP_FLD = 95, + CFA_BLD_EM_FKB_TL3_IEH_AUTH_FLD = 96, + CFA_BLD_EM_FKB_TL3_IEH_DEST_FLD = 97, + CFA_BLD_EM_FKB_TL3_IEH_FRAG_FLD = 98, + CFA_BLD_EM_FKB_TL3_IEH_RTHDR_FLD = 99, + CFA_BLD_EM_FKB_TL3_IEH_HOP_FLD = 100, + CFA_BLD_EM_FKB_TL3_IEH_1FRAG_FLD = 101, + CFA_BLD_EM_FKB_TL3_DF_FLD = 102, + CFA_BLD_EM_FKB_TL3_L3ERR_FLD = 103, + CFA_BLD_EM_FKB_TL4_TYPE_FLD = 104, + CFA_BLD_EM_FKB_TL4_SRC_FLD = 105, + CFA_BLD_EM_FKB_TL4_DST_FLD = 106, + CFA_BLD_EM_FKB_TL4_FLAGS_FLD = 107, + CFA_BLD_EM_FKB_TL4_SEQ_FLD = 108, + CFA_BLD_EM_FKB_TL4_PA_FLD = 109, + CFA_BLD_EM_FKB_TL4_OPT_FLD = 110, + CFA_BLD_EM_FKB_TL4_TCPTS_FLD = 111, + CFA_BLD_EM_FKB_TL4_ERR_FLD = 112, + CFA_BLD_EM_FKB_T_TYPE_FLD = 113, + CFA_BLD_EM_FKB_T_FLAGS_FLD = 114, + CFA_BLD_EM_FKB_T_IDS_FLD = 115, + CFA_BLD_EM_FKB_T_ID_FLD = 116, + CFA_BLD_EM_FKB_T_CTXTS_FLD = 117, + CFA_BLD_EM_FKB_T_CTXT_FLD = 118, + CFA_BLD_EM_FKB_T_QOS_FLD = 119, + CFA_BLD_EM_FKB_T_ERR_FLD = 120, + CFA_BLD_EM_FKB_L2_TYPE_FLD = 121, + CFA_BLD_EM_FKB_L2_DMAC_FLD = 122, + CFA_BLD_EM_FKB_L2_SMAC_FLD = 123, + CFA_BLD_EM_FKB_L2_DT_FLD = 124, + CFA_BLD_EM_FKB_L2_SA_FLD = 125, + CFA_BLD_EM_FKB_L2_NVT_FLD = 126, + CFA_BLD_EM_FKB_L2_OVP_FLD = 127, + CFA_BLD_EM_FKB_L2_OVD_FLD = 128, + CFA_BLD_EM_FKB_L2_OVV_FLD = 129, + CFA_BLD_EM_FKB_L2_OVT_FLD = 130, + CFA_BLD_EM_FKB_L2_IVP_FLD = 131, + CFA_BLD_EM_FKB_L2_IVD_FLD = 132, + CFA_BLD_EM_FKB_L2_IVV_FLD = 133, + CFA_BLD_EM_FKB_L2_IVT_FLD = 134, + CFA_BLD_EM_FKB_L2_ETYPE_FLD = 135, + CFA_BLD_EM_FKB_L3_TYPE_FLD = 136, + CFA_BLD_EM_FKB_L3_SIP3_FLD = 137, + CFA_BLD_EM_FKB_L3_SIP2_FLD = 138, + CFA_BLD_EM_FKB_L3_SIP1_FLD = 139, + CFA_BLD_EM_FKB_L3_SIP0_FLD = 140, + CFA_BLD_EM_FKB_L3_DIP3_FLD = 141, + CFA_BLD_EM_FKB_L3_DIP2_FLD = 142, + CFA_BLD_EM_FKB_L3_DIP1_FLD = 143, + CFA_BLD_EM_FKB_L3_DIP0_FLD = 144, + CFA_BLD_EM_FKB_L3_TTL_FLD = 145, + CFA_BLD_EM_FKB_L3_PROT_FLD = 146, + CFA_BLD_EM_FKB_L3_FID_FLD = 147, + CFA_BLD_EM_FKB_L3_QOS_FLD = 148, + CFA_BLD_EM_FKB_L3_IEH_NONEXT_FLD = 149, + CFA_BLD_EM_FKB_L3_IEH_SEP_FLD = 150, + CFA_BLD_EM_FKB_L3_IEH_AUTH_FLD = 151, + CFA_BLD_EM_FKB_L3_IEH_DEST_FLD = 152, + CFA_BLD_EM_FKB_L3_IEH_FRAG_FLD = 153, + CFA_BLD_EM_FKB_L3_IEH_RTHDR_FLD = 154, + CFA_BLD_EM_FKB_L3_IEH_HOP_FLD = 155, + CFA_BLD_EM_FKB_L3_IEH_1FRAG_FLD = 156, + CFA_BLD_EM_FKB_L3_DF_FLD = 157, + CFA_BLD_EM_FKB_L3_L3ERR_FLD = 158, + CFA_BLD_EM_FKB_L4_TYPE_FLD = 159, + CFA_BLD_EM_FKB_L4_SRC_FLD = 160, + CFA_BLD_EM_FKB_L4_DST_FLD = 161, + CFA_BLD_EM_FKB_L4_FLAGS_FLD = 162, + CFA_BLD_EM_FKB_L4_SEQ_FLD = 163, + CFA_BLD_EM_FKB_L4_ACK_FLD = 164, + CFA_BLD_EM_FKB_L4_WIN_FLD = 165, + CFA_BLD_EM_FKB_L4_PA_FLD = 166, + CFA_BLD_EM_FKB_L4_OPT_FLD = 167, + CFA_BLD_EM_FKB_L4_TCPTS_FLD = 168, + CFA_BLD_EM_FKB_L4_TSVAL_FLD = 169, + CFA_BLD_EM_FKB_L4_TXECR_FLD = 170, + CFA_BLD_EM_FKB_L4_ERR_FLD = 171, + CFA_BLD_EM_FKB_MAX_FLD +}; + +/** + * Enumeration for em key layout + */ +enum cfa_bld_em_key_layout_flds { + CFA_BLD_EM_KL_RANGE_IDX_FLD = 0, + CFA_BLD_EM_KL_RANGE_PROFILE_FLD = 1, + CFA_BLD_EM_KL_CREC_TIMER_VALUE_FLD = 2, + CFA_BLD_EM_KL_CREC_STATE_FLD = 3, + CFA_BLD_EM_KL_CREC_TCP_MSB_OPP_INIT_FLD = 4, + CFA_BLD_EM_KL_CREC_TCP_MSB_OPP_FLD = 5, + CFA_BLD_EM_KL_CREC_TCP_MSB_LOC_FLD = 6, + CFA_BLD_EM_KL_CREC_TCP_WIN_FLD = 7, + CFA_BLD_EM_KL_CREC_TCP_UPDT_EN_FLD = 8, + CFA_BLD_EM_KL_CREC_TCP_DIR_FLD = 9, + CFA_BLD_EM_KL_METADATA_FLD = 10, + CFA_BLD_EM_KL_PROF_FUNC_FLD = 11, + CFA_BLD_EM_KL_META_PROF_FLD = 12, + CFA_BLD_EM_KL_RECYCLE_DEST_FLD = 13, + CFA_BLD_EM_KL_FC_PTR_FLD = 14, + CFA_BLD_EM_KL_FC_TYPE_FLD = 15, + CFA_BLD_EM_KL_FC_OP_FLD = 16, + CFA_BLD_EM_KL_PATHS_M1_FLD = 17, + CFA_BLD_EM_KL_ACT_REC_SIZE_FLD = 18, + CFA_BLD_EM_KL_RING_TABLE_IDX_FLD = 19, + CFA_BLD_EM_KL_DESTINATION_FLD = 20, + CFA_BLD_EM_KL_ACT_REC_PTR_FLD = 21, + CFA_BLD_EM_KL_ACT_HINT_FLD = 22, + CFA_BLD_EM_KL_STRENGTH_FLD = 23, + CFA_BLD_EM_KL_OPCODE_FLD = 24, + CFA_BLD_EM_KL_EPOCH1_FLD = 25, + CFA_BLD_EM_KL_EPOCH0_FLD = 26, + CFA_BLD_EM_KL_REC_SIZE_FLD = 27, + CFA_BLD_EM_KL_VALID_FLD = 28, + CFA_BLD_EM_KL_PROF_ID_FLD = 29, + CFA_BLD_EM_KL_L2CTXT_FLD = 30, + CFA_BLD_EM_KL_L2FUNC_FLD = 31, + CFA_BLD_EM_KL_PARIF_FLD = 32, + CFA_BLD_EM_KL_SPIF_FLD = 33, + CFA_BLD_EM_KL_SVIF_FLD = 34, + CFA_BLD_EM_KL_LCOS_FLD = 35, + CFA_BLD_EM_KL_META_HI_FLD = 36, + CFA_BLD_EM_KL_META_LO_FLD = 37, + CFA_BLD_EM_KL_RCYC_CNT_FLD = 38, + CFA_BLD_EM_KL_LOOPBACK_FLD = 39, + CFA_BLD_EM_KL_OTL2_TYPE_FLD = 40, + CFA_BLD_EM_KL_OTL2_DMAC_FLD = 41, + CFA_BLD_EM_KL_OTL2_SMAC_FLD = 42, + CFA_BLD_EM_KL_OTL2_DT_FLD = 43, + CFA_BLD_EM_KL_OTL2_SA_FLD = 44, + CFA_BLD_EM_KL_OTL2_NVT_FLD = 45, + CFA_BLD_EM_KL_OTL2_OVP_FLD = 46, + CFA_BLD_EM_KL_OTL2_OVD_FLD = 47, + CFA_BLD_EM_KL_OTL2_OVV_FLD = 48, + CFA_BLD_EM_KL_OTL2_OVT_FLD = 49, + CFA_BLD_EM_KL_OTL2_IVP_FLD = 50, + CFA_BLD_EM_KL_OTL2_IVD_FLD = 51, + CFA_BLD_EM_KL_OTL2_IVV_FLD = 52, + CFA_BLD_EM_KL_OTL2_IVT_FLD = 53, + CFA_BLD_EM_KL_OTL2_ETYPE_FLD = 54, + CFA_BLD_EM_KL_OTL3_TYPE_FLD = 55, + CFA_BLD_EM_KL_OTL3_SIP3_FLD = 56, + CFA_BLD_EM_KL_OTL3_SIP2_FLD = 57, + CFA_BLD_EM_KL_OTL3_SIP1_FLD = 58, + CFA_BLD_EM_KL_OTL3_SIP0_FLD = 59, + CFA_BLD_EM_KL_OTL3_DIP3_FLD = 60, + CFA_BLD_EM_KL_OTL3_DIP2_FLD = 61, + CFA_BLD_EM_KL_OTL3_DIP1_FLD = 62, + CFA_BLD_EM_KL_OTL3_DIP0_FLD = 63, + CFA_BLD_EM_KL_OTL3_TTL_FLD = 64, + CFA_BLD_EM_KL_OTL3_PROT_FLD = 65, + CFA_BLD_EM_KL_OTL3_FID_FLD = 66, + CFA_BLD_EM_KL_OTL3_QOS_FLD = 67, + CFA_BLD_EM_KL_OTL3_IEH_NONEXT_FLD = 68, + CFA_BLD_EM_KL_OTL3_IEH_SEP_FLD = 69, + CFA_BLD_EM_KL_OTL3_IEH_AUTH_FLD = 70, + CFA_BLD_EM_KL_OTL3_IEH_DEST_FLD = 71, + CFA_BLD_EM_KL_OTL3_IEH_FRAG_FLD = 72, + CFA_BLD_EM_KL_OTL3_IEH_RTHDR_FLD = 73, + CFA_BLD_EM_KL_OTL3_IEH_HOP_FLD = 74, + CFA_BLD_EM_KL_OTL3_IEH_1FRAG_FLD = 75, + CFA_BLD_EM_KL_OTL3_DF_FLD = 76, + CFA_BLD_EM_KL_OTL3_L3ERR_FLD = 77, + CFA_BLD_EM_KL_OTL4_TYPE_FLD = 78, + CFA_BLD_EM_KL_OTL4_SRC_FLD = 79, + CFA_BLD_EM_KL_OTL4_DST_FLD = 80, + CFA_BLD_EM_KL_OTL4_FLAGS_FLD = 81, + CFA_BLD_EM_KL_OTL4_SEQ_FLD = 82, + CFA_BLD_EM_KL_OTL4_PA_FLD = 83, + CFA_BLD_EM_KL_OTL4_OPT_FLD = 84, + CFA_BLD_EM_KL_OTL4_TCPTS_FLD = 85, + CFA_BLD_EM_KL_OTL4_ERR_FLD = 86, + CFA_BLD_EM_KL_OT_TYPE_FLD = 87, + CFA_BLD_EM_KL_OT_FLAGS_FLD = 88, + CFA_BLD_EM_KL_OT_IDS_FLD = 89, + CFA_BLD_EM_KL_OT_ID_FLD = 90, + CFA_BLD_EM_KL_OT_CTXTS_FLD = 91, + CFA_BLD_EM_KL_OT_CTXT_FLD = 92, + CFA_BLD_EM_KL_OT_QOS_FLD = 93, + CFA_BLD_EM_KL_OT_ERR_FLD = 94, + CFA_BLD_EM_KL_TL2_TYPE_FLD = 95, + CFA_BLD_EM_KL_TL2_DMAC_FLD = 96, + CFA_BLD_EM_KL_TL2_SMAC_FLD = 97, + CFA_BLD_EM_KL_TL2_DT_FLD = 98, + CFA_BLD_EM_KL_TL2_SA_FLD = 99, + CFA_BLD_EM_KL_TL2_NVT_FLD = 100, + CFA_BLD_EM_KL_TL2_OVP_FLD = 101, + CFA_BLD_EM_KL_TL2_OVD_FLD = 102, + CFA_BLD_EM_KL_TL2_OVV_FLD = 103, + CFA_BLD_EM_KL_TL2_OVT_FLD = 104, + CFA_BLD_EM_KL_TL2_IVP_FLD = 105, + CFA_BLD_EM_KL_TL2_IVD_FLD = 106, + CFA_BLD_EM_KL_TL2_IVV_FLD = 107, + CFA_BLD_EM_KL_TL2_IVT_FLD = 108, + CFA_BLD_EM_KL_TL2_ETYPE_FLD = 109, + CFA_BLD_EM_KL_TL3_TYPE_FLD = 110, + CFA_BLD_EM_KL_TL3_SIP3_FLD = 111, + CFA_BLD_EM_KL_TL3_SIP2_FLD = 112, + CFA_BLD_EM_KL_TL3_SIP1_FLD = 113, + CFA_BLD_EM_KL_TL3_SIP0_FLD = 114, + CFA_BLD_EM_KL_TL3_DIP3_FLD = 115, + CFA_BLD_EM_KL_TL3_DIP2_FLD = 116, + CFA_BLD_EM_KL_TL3_DIP1_FLD = 117, + CFA_BLD_EM_KL_TL3_DIP0_FLD = 118, + CFA_BLD_EM_KL_TL3_TTL_FLD = 119, + CFA_BLD_EM_KL_TL3_PROT_FLD = 120, + CFA_BLD_EM_KL_TL3_FID_FLD = 121, + CFA_BLD_EM_KL_TL3_QOS_FLD = 122, + CFA_BLD_EM_KL_TL3_IEH_NONEXT_FLD = 123, + CFA_BLD_EM_KL_TL3_IEH_SEP_FLD = 124, + CFA_BLD_EM_KL_TL3_IEH_AUTH_FLD = 125, + CFA_BLD_EM_KL_TL3_IEH_DEST_FLD = 126, + CFA_BLD_EM_KL_TL3_IEH_FRAG_FLD = 127, + CFA_BLD_EM_KL_TL3_IEH_RTHDR_FLD = 128, + CFA_BLD_EM_KL_TL3_IEH_HOP_FLD = 129, + CFA_BLD_EM_KL_TL3_IEH_1FRAG_FLD = 130, + CFA_BLD_EM_KL_TL3_DF_FLD = 131, + CFA_BLD_EM_KL_TL3_L3ERR_FLD = 132, + CFA_BLD_EM_KL_TL4_TYPE_FLD = 133, + CFA_BLD_EM_KL_TL4_SRC_FLD = 134, + CFA_BLD_EM_KL_TL4_DST_FLD = 135, + CFA_BLD_EM_KL_TL4_FLAGS_FLD = 136, + CFA_BLD_EM_KL_TL4_SEQ_FLD = 137, + CFA_BLD_EM_KL_TL4_PA_FLD = 138, + CFA_BLD_EM_KL_TL4_OPT_FLD = 139, + CFA_BLD_EM_KL_TL4_TCPTS_FLD = 140, + CFA_BLD_EM_KL_TL4_ERR_FLD = 141, + CFA_BLD_EM_KL_T_TYPE_FLD = 142, + CFA_BLD_EM_KL_T_FLAGS_FLD = 143, + CFA_BLD_EM_KL_T_IDS_FLD = 144, + CFA_BLD_EM_KL_T_ID_FLD = 145, + CFA_BLD_EM_KL_T_CTXTS_FLD = 146, + CFA_BLD_EM_KL_T_CTXT_FLD = 147, + CFA_BLD_EM_KL_T_QOS_FLD = 148, + CFA_BLD_EM_KL_T_ERR_FLD = 149, + CFA_BLD_EM_KL_L2_TYPE_FLD = 150, + CFA_BLD_EM_KL_L2_DMAC_FLD = 151, + CFA_BLD_EM_KL_L2_SMAC_FLD = 152, + CFA_BLD_EM_KL_L2_DT_FLD = 153, + CFA_BLD_EM_KL_L2_SA_FLD = 154, + CFA_BLD_EM_KL_L2_NVT_FLD = 155, + CFA_BLD_EM_KL_L2_OVP_FLD = 156, + CFA_BLD_EM_KL_L2_OVD_FLD = 157, + CFA_BLD_EM_KL_L2_OVV_FLD = 158, + CFA_BLD_EM_KL_L2_OVT_FLD = 159, + CFA_BLD_EM_KL_L2_IVP_FLD = 160, + CFA_BLD_EM_KL_L2_IVD_FLD = 161, + CFA_BLD_EM_KL_L2_IVV_FLD = 162, + CFA_BLD_EM_KL_L2_IVT_FLD = 163, + CFA_BLD_EM_KL_L2_ETYPE_FLD = 164, + CFA_BLD_EM_KL_L3_TYPE_FLD = 165, + CFA_BLD_EM_KL_L3_SIP3_FLD = 166, + CFA_BLD_EM_KL_L3_SIP2_FLD = 167, + CFA_BLD_EM_KL_L3_SIP1_FLD = 168, + CFA_BLD_EM_KL_L3_SIP0_FLD = 169, + CFA_BLD_EM_KL_L3_DIP3_FLD = 170, + CFA_BLD_EM_KL_L3_DIP2_FLD = 171, + CFA_BLD_EM_KL_L3_DIP1_FLD = 172, + CFA_BLD_EM_KL_L3_DIP0_FLD = 173, + CFA_BLD_EM_KL_L3_TTL_FLD = 174, + CFA_BLD_EM_KL_L3_PROT_FLD = 175, + CFA_BLD_EM_KL_L3_FID_FLD = 176, + CFA_BLD_EM_KL_L3_QOS_FLD = 177, + CFA_BLD_EM_KL_L3_IEH_NONEXT_FLD = 178, + CFA_BLD_EM_KL_L3_IEH_SEP_FLD = 179, + CFA_BLD_EM_KL_L3_IEH_AUTH_FLD = 180, + CFA_BLD_EM_KL_L3_IEH_DEST_FLD = 181, + CFA_BLD_EM_KL_L3_IEH_FRAG_FLD = 182, + CFA_BLD_EM_KL_L3_IEH_RTHDR_FLD = 183, + CFA_BLD_EM_KL_L3_IEH_HOP_FLD = 184, + CFA_BLD_EM_KL_L3_IEH_1FRAG_FLD = 185, + CFA_BLD_EM_KL_L3_DF_FLD = 186, + CFA_BLD_EM_KL_L3_L3ERR_FLD = 187, + CFA_BLD_EM_KL_L4_TYPE_FLD = 188, + CFA_BLD_EM_KL_L4_SRC_FLD = 189, + CFA_BLD_EM_KL_L4_DST_FLD = 190, + CFA_BLD_EM_KL_L4_FLAGS_FLD = 191, + CFA_BLD_EM_KL_L4_SEQ_FLD = 192, + CFA_BLD_EM_KL_L4_ACK_FLD = 193, + CFA_BLD_EM_KL_L4_WIN_FLD = 194, + CFA_BLD_EM_KL_L4_PA_FLD = 195, + CFA_BLD_EM_KL_L4_OPT_FLD = 196, + CFA_BLD_EM_KL_L4_TCPTS_FLD = 197, + CFA_BLD_EM_KL_L4_TSVAL_FLD = 198, + CFA_BLD_EM_KL_L4_TXECR_FLD = 199, + CFA_BLD_EM_KL_L4_ERR_FLD = 200, + CFA_BLD_EM_KEY_LAYOUT_MAX_FLD = 201, +}; + +/** + * Enumeration for action + */ +enum cfa_bld_action_flds { + CFA_BLD_ACT_TYPE_FLD = 0, + CFA_BLD_ACT_DROP_FLD = 1, + CFA_BLD_ACT_VLAN_DELETE_FLD = 2, + CFA_BLD_ACT_DEST_FLD = 3, + CFA_BLD_ACT_DEST_OP_FLD = 4, + CFA_BLD_ACT_DECAP_FLD = 5, + CFA_BLD_ACT_MIRRORING_FLD = 6, + CFA_BLD_ACT_METER_PTR_FLD = 7, + CFA_BLD_ACT_STAT0_OFF_FLD = 8, + CFA_BLD_ACT_STAT0_OP_FLD = 9, + CFA_BLD_ACT_STAT0_CTR_TYPE_FLD = 10, + CFA_BLD_ACT_MOD_OFF_FLD = 11, + CFA_BLD_ACT_ENC_OFF_FLD = 12, + CFA_BLD_ACT_SRC_OFF_FLD = 13, + CFA_BLD_ACT_COMPACT_RSVD_0_FLD = 14, + CFA_BLD_ACT_STAT0_PTR_FLD = 15, + CFA_BLD_ACT_STAT1_PTR_FLD = 16, + CFA_BLD_ACT_STAT1_OP_FLD = 17, + CFA_BLD_ACT_STAT1_CTR_TYPE_FLD = 18, + CFA_BLD_ACT_MOD_PTR_FLD = 19, + CFA_BLD_ACT_ENC_PTR_FLD = 20, + CFA_BLD_ACT_SRC_PTR_FLD = 21, + CFA_BLD_ACT_FULL_RSVD_0_FLD = 22, + CFA_BLD_ACT_SRC_KO_EN_FLD = 23, + CFA_BLD_ACT_MCG_RSVD_0_FLD = 24, + CFA_BLD_ACT_NEXT_PTR_FLD = 25, + CFA_BLD_ACT_PTR0_ACT_HINT_FLD = 26, + CFA_BLD_ACT_PTR0_ACT_REC_PTR_FLD = 27, + CFA_BLD_ACT_PTR1_ACT_HINT_FLD = 28, + CFA_BLD_ACT_PTR1_ACT_REC_PTR_FLD = 29, + CFA_BLD_ACT_PTR2_ACT_HINT_FLD = 30, + CFA_BLD_ACT_PTR2_ACT_REC_PTR_FLD = 31, + CFA_BLD_ACT_PTR3_ACT_HINT_FLD = 32, + CFA_BLD_ACT_PTR3_ACT_REC_PTR_FLD = 33, + CFA_BLD_ACT_PTR4_ACT_HINT_FLD = 34, + CFA_BLD_ACT_PTR4_ACT_REC_PTR_FLD = 35, + CFA_BLD_ACT_PTR5_ACT_HINT_FLD = 36, + CFA_BLD_ACT_PTR5_ACT_REC_PTR_FLD = 37, + CFA_BLD_ACT_PTR6_ACT_HINT_FLD = 38, + CFA_BLD_ACT_PTR6_ACT_REC_PTR_FLD = 39, + CFA_BLD_ACT_PTR7_ACT_HINT_FLD = 40, + CFA_BLD_ACT_PTR7_ACT_REC_PTR_FLD = 41, + CFA_BLD_ACT_MCG_SUBSEQ_RSVD_0_FLD = 42, + CFA_BLD_ACT_MOD_MODIFY_ACT_HDR_FLD = 43, + CFA_BLD_ACT_MOD_MD_UPDT_DATA_FLD = 44, + CFA_BLD_ACT_MOD_MD_UPDT_PROF_FLD = 45, + CFA_BLD_ACT_MOD_MD_UPDT_OP_FLD = 46, + CFA_BLD_ACT_MOD_MD_UPDT_RSVD_0_FLD = 47, + CFA_BLD_ACT_MOD_MD_UPDT_TOP_FLD = 48, + CFA_BLD_ACT_MOD_RM_OVLAN_FLD = 49, + CFA_BLD_ACT_MOD_RM_IVLAN_FLD = 50, + CFA_BLD_ACT_MOD_RPL_IVLAN_FLD = 51, + CFA_BLD_ACT_MOD_RPL_OVLAN_FLD = 52, + CFA_BLD_ACT_MOD_TTL_UPDT_OP_FLD = 53, + CFA_BLD_ACT_MOD_TTL_UPDT_ALT_VID_FLD = 54, + CFA_BLD_ACT_MOD_TTL_UPDT_ALT_PFID_FLD = 55, + CFA_BLD_ACT_MOD_TTL_UPDT_TOP_FLD = 56, + CFA_BLD_ACT_MOD_TNL_MODIFY_DEL_FLD = 57, + CFA_BLD_ACT_MOD_TNL_MODIFY_8B_NEW_PROT_FLD = 58, + CFA_BLD_ACT_MOD_TNL_MODIFY_8B_EXIST_PROT_FLD = 59, + CFA_BLD_ACT_MOD_TNL_MODIFY_8B_VEC_FLD = 60, + CFA_BLD_ACT_MOD_TNL_MODIFY_8B_TOP_FLD = 61, + CFA_BLD_ACT_MOD_TNL_MODIFY_16B_NEW_PROT_FLD = 62, + CFA_BLD_ACT_MOD_TNL_MODIFY_16B_EXIST_PROT_FLD = 63, + CFA_BLD_ACT_MOD_TNL_MODIFY_16B_VEC_FLD = 64, + CFA_BLD_ACT_MOD_TNL_MODIFY_16B_TOP_FLD = 65, + CFA_BLD_ACT_MOD_UPDT_FIELD_DATA0_FLD = 66, + CFA_BLD_ACT_MOD_UPDT_FIELD_VEC_RSVD_FLD = 67, + CFA_BLD_ACT_MOD_UPDT_FIELD_VEC_KID_FLD = 68, + CFA_BLD_ACT_MOD_UPDT_FIELD_TOP_FLD = 69, + CFA_BLD_ACT_MOD_SMAC_FLD = 70, + CFA_BLD_ACT_MOD_DMAC_FLD = 71, + CFA_BLD_ACT_MOD_SIPV6_FLD = 72, + CFA_BLD_ACT_MOD_DIPV6_FLD = 73, + CFA_BLD_ACT_MOD_SIPV4_FLD = 74, + CFA_BLD_ACT_MOD_DIPV4_FLD = 75, + CFA_BLD_ACT_MOD_SPORT_FLD = 76, + CFA_BLD_ACT_MOD_DPORT_FLD = 77, + CFA_BLD_ACT_ENC_ECV_TNL_FLD = 78, + CFA_BLD_ACT_ENC_ECV_L4_FLD = 79, + CFA_BLD_ACT_ENC_ECV_L3_FLD = 80, + CFA_BLD_ACT_ENC_ECV_L2_FLD = 81, + CFA_BLD_ACT_ENC_ECV_VTAG_FLD = 82, + CFA_BLD_ACT_ENC_ECV_EC_FLD = 83, + CFA_BLD_ACT_ENC_ECV_VALID_FLD = 84, + CFA_BLD_ACT_ENC_EC_IP_TTL_IH_FLD = 85, + CFA_BLD_ACT_ENC_EC_IP_TOS_IH_FLD = 86, + CFA_BLD_ACT_ENC_EC_TUN_QOS_FLD = 87, + CFA_BLD_ACT_ENC_EC_GRE_SET_K_FLD = 88, + CFA_BLD_ACT_ENC_EC_DMAC_OVR_FLD = 89, + CFA_BLD_ACT_ENC_EC_VLAN_OVR_FLD = 90, + CFA_BLD_ACT_ENC_EC_SMAC_OVR_FLD = 91, + CFA_BLD_ACT_ENC_EC_IPV4_ID_CTRL_FLD = 92, + CFA_BLD_ACT_ENC_L2_DMAC_FLD = 93, + CFA_BLD_ACT_ENC_VLAN1_TAG_VID_FLD = 94, + CFA_BLD_ACT_ENC_VLAN1_TAG_DE_FLD = 95, + CFA_BLD_ACT_ENC_VLAN1_TAG_PRI_FLD = 96, + CFA_BLD_ACT_ENC_VLAN1_TAG_TPID_FLD = 97, + CFA_BLD_ACT_ENC_VLAN2_IT_VID_FLD = 98, + CFA_BLD_ACT_ENC_VLAN2_IT_DE_FLD = 99, + CFA_BLD_ACT_ENC_VLAN2_IT_PRI_FLD = 100, + CFA_BLD_ACT_ENC_VLAN2_IT_TPID_FLD = 101, + CFA_BLD_ACT_ENC_VLAN2_OT_VID_FLD = 102, + CFA_BLD_ACT_ENC_VLAN2_OT_DE_FLD = 103, + CFA_BLD_ACT_ENC_VLAN2_OT_PRI_FLD = 104, + CFA_BLD_ACT_ENC_VLAN2_OT_TPID_FLD = 105, + CFA_BLD_ACT_ENC_IPV4_ID_FLD = 106, + CFA_BLD_ACT_ENC_IPV4_TOS_FLD = 107, + CFA_BLD_ACT_ENC_IPV4_HLEN_FLD = 108, + CFA_BLD_ACT_ENC_IPV4_VER_FLD = 109, + CFA_BLD_ACT_ENC_IPV4_PROT_FLD = 110, + CFA_BLD_ACT_ENC_IPV4_TTL_FLD = 111, + CFA_BLD_ACT_ENC_IPV4_FRAG_FLD = 112, + CFA_BLD_ACT_ENC_IPV4_FLAGS_FLD = 113, + CFA_BLD_ACT_ENC_IPV4_DEST_FLD = 114, + CFA_BLD_ACT_ENC_IPV6_FLOW_LABEL_FLD = 115, + CFA_BLD_ACT_ENC_IPV6_TRAFFIC_CLASS_FLD = 116, + CFA_BLD_ACT_ENC_IPV6_VER_FLD = 117, + CFA_BLD_ACT_ENC_IPV6_HOP_LIMIT_FLD = 118, + CFA_BLD_ACT_ENC_IPV6_NEXT_HEADER_FLD = 119, + CFA_BLD_ACT_ENC_IPV6_PAYLOAD_LENGTH_FLD = 120, + CFA_BLD_ACT_ENC_IPV6_DEST_FLD = 121, + CFA_BLD_ACT_ENC_MPLS_TAG1_FLD = 122, + CFA_BLD_ACT_ENC_MPLS_TAG2_FLD = 123, + CFA_BLD_ACT_ENC_MPLS_TAG3_FLD = 124, + CFA_BLD_ACT_ENC_MPLS_TAG4_FLD = 125, + CFA_BLD_ACT_ENC_MPLS_TAG5_FLD = 126, + CFA_BLD_ACT_ENC_MPLS_TAG6_FLD = 127, + CFA_BLD_ACT_ENC_MPLS_TAG7_FLD = 128, + CFA_BLD_ACT_ENC_MPLS_TAG8_FLD = 129, + CFA_BLD_ACT_ENC_L4_DEST_PORT_FLD = 130, + CFA_BLD_ACT_ENC_L4_SRC_PORT_FLD = 131, + CFA_BLD_ACT_ENC_TNL_VXLAN_NEXT_PROT_FLD = 132, + CFA_BLD_ACT_ENC_TNL_VXLAN_RSVD_0_FLD = 133, + CFA_BLD_ACT_ENC_TNL_VXLAN_FLAGS_FLD = 134, + CFA_BLD_ACT_ENC_TNL_VXLAN_RSVD_1_FLD = 135, + CFA_BLD_ACT_ENC_TNL_VXLAN_VNI_FLD = 136, + CFA_BLD_ACT_ENC_TNL_NGE_PROT_TYPE_FLD = 137, + CFA_BLD_ACT_ENC_TNL_NGE_RSVD_0_FLD = 138, + CFA_BLD_ACT_ENC_TNL_NGE_FLAGS_C_FLD = 139, + CFA_BLD_ACT_ENC_TNL_NGE_FLAGS_O_FLD = 140, + CFA_BLD_ACT_ENC_TNL_NGE_FLAGS_OPT_LEN_FLD = 141, + CFA_BLD_ACT_ENC_TNL_NGE_FLAGS_VER_FLD = 142, + CFA_BLD_ACT_ENC_TNL_NGE_RSVD_1_FLD = 143, + CFA_BLD_ACT_ENC_TNL_NGE_VNI_FLD = 144, + CFA_BLD_ACT_ENC_TNL_NGE_OPTIONS_FLD = 145, + CFA_BLD_ACT_ENC_TNL_NVGRE_FLOW_ID_FLD = 146, + CFA_BLD_ACT_ENC_TNL_NVGRE_VSID_FLD = 147, + CFA_BLD_ACT_ENC_TNL_GRE_KEY_FLD = 148, + CFA_BLD_ACT_ENC_TNL_GENERIC_TID_FLD = 149, + CFA_BLD_ACT_ENC_TNL_GENERIC_LENGTH_FLD = 150, + CFA_BLD_ACT_ENC_TNL_GENERIC_HEADER_FLD = 151, + CFA_BLD_ACT_ENC_SPDNIC_SIZE_FLD = 152, + CFA_BLD_ACT_ENC_SPDNIC_TID_FLD = 153, + CFA_BLD_ACT_ENC_SPDNIC_FLAGS_FLD = 154, + CFA_BLD_ACT_ENC_SPDNIC_RSVD_FLD = 155, + CFA_BLD_ACT_SRC_MAC_FLD = 156, + CFA_BLD_ACT_SRC_IPV4_ADDR_FLD = 157, + CFA_BLD_ACT_SRC_IPV6_ADDR_FLD = 158, + CFA_BLD_ACT_STAT0_B16_FPC_FLD = 159, + CFA_BLD_ACT_STAT1_B16_FPC_FLD = 160, + CFA_BLD_ACT_STAT0_B16_FBC_FLD = 161, + CFA_BLD_ACT_STAT1_B16_FBC_FLD = 162, + CFA_BLD_ACT_STAT0_B24_FPC_FLD = 163, + CFA_BLD_ACT_STAT1_B24_FPC_FLD = 164, + CFA_BLD_ACT_STAT0_B24_FBC_FLD = 165, + CFA_BLD_ACT_STAT1_B24_FBC_FLD = 166, + CFA_BLD_ACT_STAT0_B24_TIMESTAMP_FLD = 167, + CFA_BLD_ACT_STAT1_B24_TIMESTAMP_FLD = 168, + CFA_BLD_ACT_STAT0_B24_TCP_FLAGS_FLD = 169, + CFA_BLD_ACT_STAT1_B24_TCP_FLAGS_FLD = 170, + CFA_BLD_ACT_STAT0_B24_UNUSED_0_FLD = 171, + CFA_BLD_ACT_STAT1_B24_UNUSED_0_FLD = 172, + CFA_BLD_ACT_STAT0_B32A_FPC_FLD = 173, + CFA_BLD_ACT_STAT1_B32A_FPC_FLD = 174, + CFA_BLD_ACT_STAT0_B32A_FBC_FLD = 175, + CFA_BLD_ACT_STAT1_B32A_FBC_FLD = 176, + CFA_BLD_ACT_STAT0_B32A_MPC_FLD = 177, + CFA_BLD_ACT_STAT1_B32A_MPC_FLD = 178, + CFA_BLD_ACT_STAT0_B32A_MBC_FLD = 179, + CFA_BLD_ACT_STAT1_B32A_MBC_FLD = 180, + CFA_BLD_ACT_STAT0_B32B_FPC_FLD = 181, + CFA_BLD_ACT_STAT1_B32B_FPC_FLD = 182, + CFA_BLD_ACT_STAT0_B32B_FBC_FLD = 183, + CFA_BLD_ACT_STAT1_B32B_FBC_FLD = 184, + CFA_BLD_ACT_STAT0_B32B_TIMESTAMP_FLD = 185, + CFA_BLD_ACT_STAT1_B32B_TIMESTAMP_FLD = 186, + CFA_BLD_ACT_STAT0_B32B_TCP_FLAGS_FLD = 187, + CFA_BLD_ACT_STAT1_B32B_TCP_FLAGS_FLD = 188, + CFA_BLD_ACT_STAT0_B32B_UNUSED_0_FLD = 189, + CFA_BLD_ACT_STAT1_B32B_UNUSED_0_FLD = 190, + CFA_BLD_ACT_STAT0_B32B_MPC15_0_FLD = 191, + CFA_BLD_ACT_STAT1_B32B_MPC15_0_FLD = 192, + CFA_BLD_ACT_STAT0_B32B_MPC37_16_FLD = 193, + CFA_BLD_ACT_STAT1_B32B_MPC37_16_FLD = 194, + CFA_BLD_ACT_STAT0_B32B_MBC_FLD = 195, + CFA_BLD_ACT_STAT1_B32B_MBC_FLD = 196, + CFA_BLD_ACTION_MAX_FLD = 197, +}; + +#endif /* _CFA_BLD_FIELD_IDS_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_mpc_field_ids.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_mpc_field_ids.h new file mode 100644 index 0000000000..b546366127 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_mpc_field_ids.h @@ -0,0 +1,1286 @@ +/**************************************************************************** + * Copyright(c) 2001-2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * Name: cfa_bld_mpc_field_ids.h + * + * Description: Enumeration definitions for the MPC command/response fields + * across multiple hw versions of CFA. + * + * This file is independent of the CFA HW version and defines the + * superset of the enumeration values for MPC command/response + * structure fields. This file is meant for use by host applications + * that support multiple devices with different CFA Hw versions. + * + * These enum definitions should be updated whenever any of the + * definitions in the auto-generated header 'cfa_bld_pxx_field_ids.h' + * file gets any new enum values. + * + ****************************************************************************/ +#ifndef _CFA_BLD_MPC_FIELD_IDS_H_ +#define _CFA_BLD_MPC_FIELD_IDS_H_ + +/** + * CFA Hardware Cache Table Type + */ +enum cfa_bld_mpc_hw_table_type { + CFA_BLD_MPC_HW_TABLE_TYPE_ACTION, /**< CFA Action Record Table */ + CFA_BLD_MPC_HW_TABLE_TYPE_LOOKUP, /**< CFA EM Lookup Record Table */ + CFA_BLD_MPC_HW_TABLE_TYPE_MAX +}; + +/* + * CFA MPC Cache access reading mode + * To be used as a value for CFA_BLD_MPC_READ_CMD_CACHE_OPTION_FLD + */ +enum cfa_bld_mpc_read_mode { + CFA_BLD_MPC_RD_NORMAL, /**< Normal read mode */ + CFA_BLD_MPC_RD_EVICT, /**< Read the cache and evict the cache line */ + CFA_BLD_MPC_RD_DEBUG_LINE, /**< Debug read line mode */ + CFA_BLD_MPC_RD_DEBUG_TAG, /**< Debug read tag mode */ + CFA_BLD_MPC_RD_MODE_MAX +}; + +/** + * CFA MPC Cache access writing mode + * To be used as a value for CFA_BLD_MPC_WRITE_CMD_CACHE_OPTION_FLD + */ +enum cfa_bld_mpc_write_mode { + CFA_BLD_MPC_WR_WRITE_THRU, /**< Write to cache in Write through mode */ + CFA_BLD_MPC_WR_WRITE_BACK, /**< Write to cache in Write back mode */ + CFA_BLD_MPC_WR_MODE_MAX +}; + +/** + * CFA MPC Cache access eviction mode + * To be used as a value for CFA_BLD_MPC_INVALIDATE_CMD_CACHE_OPTION_FLD + */ +enum cfa_bld_mpc_evict_mode { + /** + * Line evict: These modes evict a single cache line + * In these modes, the eviction occurs regardless of the cache line + * state (CLEAN/CLEAN_FAST_EVICT/DIRTY) + */ + /* Cache line addressed by set/way is evicted */ + CFA_BLD_MPC_EV_EVICT_LINE, + /* Cache line hit with the table scope/address tuple is evicted */ + CFA_BLD_MPC_EV_EVICT_SCOPE_ADDRESS, + + /** + * Set Evict: These modes evict cache lines that meet certain criteria + * from the entire cache set. + */ + /* + * Cache lines only in CLEAN state are evicted from the set + * derived from the address + */ + CFA_BLD_MPC_EV_EVICT_CLEAN_LINES, + /* + * Cache lines only in CLEAN_FAST_EVICT state are evicted from + * the set derived from the address + */ + CFA_BLD_MPC_EV_EVICT_CLEAN_FAST_EVICT_LINES, + /* + * Cache lines in both CLEAN and CLEAN_FAST_EVICT states are + * evicted from the set derived from the address + */ + CFA_BLD_MPC_EV_EVICT_CLEAN_AND_CLEAN_FAST_EVICT_LINES, + /* + * All Cache lines in the set identified by the address and + * belonging to the table scope are evicted. + */ + CFA_BLD_MPC_EV_EVICT_TABLE_SCOPE, + CFA_BLD_MPC_EV_MODE_MAX, +}; + +/** + * MPC CFA Command completion status + */ +enum cfa_bld_mpc_cmpl_status { + /* Command success */ + CFA_BLD_MPC_OK, + /* Unsupported CFA opcode */ + CFA_BLD_MPC_UNSPRT_ERR, + /* CFA command format error */ + CFA_BLD_MPC_FMT_ERR, + /* SVIF-Table Scope error */ + CFA_BLD_MPC_SCOPE_ERR, + /* Address error: Only used if EM command or TABLE_TYPE=EM */ + CFA_BLD_MPC_ADDR_ERR, + /* Cache operation error */ + CFA_BLD_MPC_CACHE_ERR, + /* EM_SEARCH or EM_DELETE did not find a matching EM entry */ + CFA_BLD_MPC_EM_MISS, + /* EM_INSERT found a matching EM entry and REPLACE=0 in the command */ + CFA_BLD_MPC_EM_DUPLICATE, + /* EM_EVENT_COLLECTION_FAIL no events to return */ + CFA_BLD_MPC_EM_EVENT_COLLECTION_FAIL, + /* + * EM_INSERT required a dynamic bucket to be added to the chain + * to successfully insert the EM entry, but the entry provided + * for use as dynamic bucket was invalid. (bucket_idx == 0) + */ + CFA_BLD_MPC_EM_ABORT, +}; + +/** + * Field IDS for READ_CMD: This command reads 1-4 consecutive 32B words + * from the specified address within a table scope. + */ +enum cfa_bld_mpc_read_cmd_fields { + CFA_BLD_MPC_READ_CMD_OPAQUE_FLD = 0, + /* This value selects the table type to be acted upon. */ + CFA_BLD_MPC_READ_CMD_TABLE_TYPE_FLD = 1, + /* Table scope to access. */ + CFA_BLD_MPC_READ_CMD_TABLE_SCOPE_FLD = 2, + /* + * Number of 32B units in access. If value is outside the range [1, 4], + * CFA aborts processing and reports FMT_ERR status. + */ + CFA_BLD_MPC_READ_CMD_DATA_SIZE_FLD = 3, + /* + * Test field for CFA MPC builder validation, added to introduce + * a hold in the field mapping array + */ + CFA_BLD_MPC_READ_CMD_RANDOM_TEST_FLD = 4, + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + CFA_BLD_MPC_READ_CMD_CACHE_OPTION_FLD = 5, + /* + * A 32B index into the table identified by (TABLE_TYPE, TABLE_SCOPE): + */ + CFA_BLD_MPC_READ_CMD_TABLE_INDEX_FLD = 6, + /* + * The 64-bit host address to which to write the DMA data returned in + * the completion. The data will be written to the same function as the + * one that owns the SQ this command is read from. DATA_SIZE determines + * the maximum size of the data written. If HOST_ADDRESS[1:0] is not 0, + * CFA aborts processing and reports FMT_ERR status. + */ + CFA_BLD_MPC_READ_CMD_HOST_ADDRESS_FLD = 7, + CFA_BLD_MPC_READ_CMD_MAX_FLD = 8, +}; + +/** + * Field IDS for WRITE_CMD: This command writes 1-4 consecutive 32B + * words to the specified address within a table scope. + */ +enum cfa_bld_mpc_write_cmd_fields { + CFA_BLD_MPC_WRITE_CMD_OPAQUE_FLD = 0, + /* This value selects the table type to be acted upon. */ + CFA_BLD_MPC_WRITE_CMD_TABLE_TYPE_FLD = 1, + /* + * Sets the OPTION field on the cache interface to use write-through for + * EM entry writes while processing EM_INSERT commands. For all other + * cases (inluding EM_INSERT bucket writes), the OPTION field is set by + * the CACHE_OPTION and CACHE_OPTION2 fields. + */ + CFA_BLD_MPC_WRITE_CMD_WRITE_THROUGH_FLD = 2, + /* Table scope to access. */ + CFA_BLD_MPC_WRITE_CMD_TABLE_SCOPE_FLD = 3, + /* + * Number of 32B units in access. If value is outside the range [1, 4], + * CFA aborts processing and reports FMT_ERR status. + */ + CFA_BLD_MPC_WRITE_CMD_DATA_SIZE_FLD = 4, + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + CFA_BLD_MPC_WRITE_CMD_CACHE_OPTION_FLD = 5, + /* + * A 32B index into the table identified by (TABLE_TYPE, TABLE_SCOPE): + */ + CFA_BLD_MPC_WRITE_CMD_TABLE_INDEX_FLD = 6, + CFA_BLD_MPC_WRITE_CMD_MAX_FLD = 7, +}; + +/** + * Field IDS for READ_CLR_CMD: This command performs a read-modify-write + * to the specified 32B address using a 16b mask that specifies up to 16 + * 16b words to clear before writing the data back. It returns the 32B + * data word read from cache (not the value written after the clear + * operation). + */ +enum cfa_bld_mpc_read_clr_cmd_fields { + CFA_BLD_MPC_READ_CLR_CMD_OPAQUE_FLD = 0, + /* This value selects the table type to be acted upon. */ + CFA_BLD_MPC_READ_CLR_CMD_TABLE_TYPE_FLD = 1, + /* Table scope to access. */ + CFA_BLD_MPC_READ_CLR_CMD_TABLE_SCOPE_FLD = 2, + /* + * This field is no longer used. The READ_CLR command always reads (and + * does a mask-clear) on a single cache line. This field was added for + * SR2 A0 to avoid an ADDR_ERR when TABLE_INDEX=0 and TABLE_TYPE=EM (see + * CUMULUS-17872). That issue was fixed in SR2 B0. + */ + CFA_BLD_MPC_READ_CLR_CMD_DATA_SIZE_FLD = 3, + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + CFA_BLD_MPC_READ_CLR_CMD_CACHE_OPTION_FLD = 4, + /* + * A 32B index into the table identified by (TABLE_TYPE, TABLE_SCOPE): + */ + CFA_BLD_MPC_READ_CLR_CMD_TABLE_INDEX_FLD = 5, + /* + * The 64-bit host address to which to write the DMA data returned in + * the completion. The data will be written to the same function as the + * one that owns the SQ this command is read from. DATA_SIZE determines + * the maximum size of the data written. If HOST_ADDRESS[1:0] is not 0, + * CFA aborts processing and reports FMT_ERR status. + */ + CFA_BLD_MPC_READ_CLR_CMD_HOST_ADDRESS_FLD = 6, + /* + * Specifies bits in 32B data word to clear. For x=0..15, when + * clear_mask[x]=1, data[x*16+15:x*16] is set to 0. + */ + CFA_BLD_MPC_READ_CLR_CMD_CLEAR_MASK_FLD = 7, + CFA_BLD_MPC_READ_CLR_CMD_MAX_FLD = 8, +}; + +/** + * Field IDS for INVALIDATE_CMD: This command forces an explicit evict + * of 1-4 consecutive cache lines such that the next time the structure + * is used it will be re-read from its backing store location. + */ +enum cfa_bld_mpc_invalidate_cmd_fields { + CFA_BLD_MPC_INVALIDATE_CMD_OPAQUE_FLD = 0, + /* This value selects the table type to be acted upon. */ + CFA_BLD_MPC_INVALIDATE_CMD_TABLE_TYPE_FLD = 1, + /* Table scope to access. */ + CFA_BLD_MPC_INVALIDATE_CMD_TABLE_SCOPE_FLD = 2, + /* + * This value identifies the number of cache lines to invalidate. A + * FMT_ERR is reported if the value is not in the range of [1, 4]. + */ + CFA_BLD_MPC_INVALIDATE_CMD_DATA_SIZE_FLD = 3, + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + CFA_BLD_MPC_INVALIDATE_CMD_CACHE_OPTION_FLD = 4, + /* + * A 32B index into the table identified by (TABLE_TYPE, TABLE_SCOPE): + */ + CFA_BLD_MPC_INVALIDATE_CMD_TABLE_INDEX_FLD = 5, + CFA_BLD_MPC_INVALIDATE_CMD_MAX_FLD = 6, +}; + +/** + * Field IDS for EM_SEARCH_CMD: This command supplies an exact match + * entry of 1-4 32B words to search for in the exact match table. CFA + * first computes the hash value of the key in the entry, and determines + * the static bucket address to search from the hash and the + * (EM_BUCKETS, EM_SIZE) for TABLE_SCOPE. It then searches that static + * bucket chain for an entry with a matching key (the LREC in the + * command entry is ignored). If a matching entry is found, CFA reports + * OK status in the completion. Otherwise, assuming no errors abort the + * search before it completes, it reports EM_MISS status. + */ +enum cfa_bld_mpc_em_search_cmd_fields { + CFA_BLD_MPC_EM_SEARCH_CMD_OPAQUE_FLD = 0, + /* Table scope to access. */ + CFA_BLD_MPC_EM_SEARCH_CMD_TABLE_SCOPE_FLD = 1, + /* + * Number of 32B units in access. If value is outside the range [1, 4], + * CFA aborts processing and reports FMT_ERR status. + */ + CFA_BLD_MPC_EM_SEARCH_CMD_DATA_SIZE_FLD = 2, + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + CFA_BLD_MPC_EM_SEARCH_CMD_CACHE_OPTION_FLD = 3, + CFA_BLD_MPC_EM_SEARCH_CMD_MAX_FLD = 4, +}; + +/** + * Field IDS for EM_INSERT_CMD: This command supplies an exact match + * entry of 1-4 32B words to insert in the exact match table. CFA first + * computes the hash value of the key in the entry, and determines the + * static bucket address to search from the hash and the (EM_BUCKETS, + * EM_SIZE) for TABLE_SCOPE. It then writes the 1-4 32B words of the + * exact match entry starting at the TABLE_INDEX location in the + * command. When the entry write completes, it searches the static + * bucket chain for an existing entry with a key matching the key in the + * insert entry (the LREC does not need to match). If a matching entry + * is found: * If REPLACE=0, the CFA aborts the insert and returns + * EM_DUPLICATE status. * If REPLACE=1, the CFA overwrites the matching + * entry with the new entry. REPLACED_ENTRY=1 in the completion in this + * case to signal that an entry was replaced. The location of the entry + * is provided in the completion. If no match is found, CFA adds the new + * entry to the lowest unused entry in the tail bucket. If the current + * tail bucket is full, this requires adding a new bucket to the tail. + * Then entry is then inserted at entry number 0. TABLE_INDEX2 provides + * the address of the new tail bucket, if needed. If set to 0, the + * insert is aborted and returns EM_ABORT status instead of adding a new + * bucket to the tail. CHAIN_UPD in the completion indicates whether a + * new bucket was added (1) or not (0). For locked scopes, if the read + * of the static bucket gives a locked scope miss error, indicating that + * the address is not in the cache, the static bucket is assumed empty. + * In this case, TAI creates a new bucket, setting entry 0 to the new + * entry fields and initializing all other fields to 0. It writes this + * new bucket to the static bucket address, which installs it in the + * cache. + */ +enum cfa_bld_mpc_em_insert_cmd_fields { + CFA_BLD_MPC_EM_INSERT_CMD_OPAQUE_FLD = 0, + /* + * Sets the OPTION field on the cache interface to use write-through for + * EM entry writes while processing EM_INSERT commands. For all other + * cases (inluding EM_INSERT bucket writes), the OPTION field is set by + * the CACHE_OPTION and CACHE_OPTION2 fields. + */ + CFA_BLD_MPC_EM_INSERT_CMD_WRITE_THROUGH_FLD = 1, + /* Table scope to access. */ + CFA_BLD_MPC_EM_INSERT_CMD_TABLE_SCOPE_FLD = 2, + /* + * Number of 32B units in access. If value is outside the range [1, 4], + * CFA aborts processing and reports FMT_ERR status. + */ + CFA_BLD_MPC_EM_INSERT_CMD_DATA_SIZE_FLD = 3, + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + CFA_BLD_MPC_EM_INSERT_CMD_CACHE_OPTION_FLD = 4, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. Starting + * address to write exact match entry being inserted. + */ + CFA_BLD_MPC_EM_INSERT_CMD_TABLE_INDEX_FLD = 5, + /* + * Determines setting of OPTION field for all cache write requests for + * EM_INSERT, EM_DELETE, and EM_CHAIN commands. CFA does not support + * posted write requests. Therefore, CACHE_OPTION2[1] must be set to 0. + */ + CFA_BLD_MPC_EM_INSERT_CMD_CACHE_OPTION2_FLD = 6, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. Only used + * when no duplicate entry is found and the tail bucket in the chain + * searched has no unused entries. In this case, TABLE_INDEX2 provides + * the index to the 32B dynamic bucket to add to the tail of the chain + * (it is the new tail bucket). In this case, the CFA first writes + * TABLE_INDEX2 with a new bucket: * Entry 0 of the bucket sets the + * HASH_MSBS computed from the hash and ENTRY_PTR to TABLE_INDEX. * + * Entries 1-5 of the bucket set HASH_MSBS and ENTRY_PTR to 0. * CHAIN=0 + * and CHAIN_PTR is set to CHAIN_PTR from to original tail bucket to + * maintain the background chaining. CFA then sets CHAIN=1 and + * CHAIN_PTR=TABLE_INDEX2 in the original tail bucket to link the new + * bucket to the chain. CHAIN_UPD=1 in the completion to signal that the + * new bucket at TABLE_INDEX2 was added to the tail of the chain. + */ + CFA_BLD_MPC_EM_INSERT_CMD_TABLE_INDEX2_FLD = 7, + /* + * Only used if an entry is found whose key matches the exact match + * entry key in the command: * REPLACE=0: The insert is aborted and + * EM_DUPLICATE status is returned, signaling that the insert failed. + * The index of the matching entry that blocked the insertion is + * returned in the completion. * REPLACE=1: The matching entry is + * replaced with that from the command (ENTRY_PTR in the bucket is + * overwritten with TABLE_INDEX from the command). HASH_MSBS for the + * entry number never changes in this case since it had to match the new + * entry key HASH_MSBS to match. When an entry is replaced, + * REPLACED_ENTRY=1 in the completion and the index of the matching + * entry is returned in the completion so that software can de-allocate + * the entry. + */ + CFA_BLD_MPC_EM_INSERT_CMD_REPLACE_FLD = 8, + CFA_BLD_MPC_EM_INSERT_CMD_MAX_FLD = 9, +}; + +/** + * Field IDS for EM_DELETE_CMD: This command searches for an exact match + * entry index in the static bucket chain and deletes it if found. + * TABLE_INDEX give the entry index to delete and TABLE_INDEX2 gives the + * static bucket index. If a matching entry is found: * If the matching + * entry is the last valid entry in the tail bucket, its entry fields + * (HASH_MSBS and ENTRY_PTR) are set to 0 to delete the entry. * If the + * matching entry is not the last valid entry in the tail bucket, the + * entry fields from that last entry are moved to the matching entry, + * and the fields of that last entry are set to 0. * If any of the + * previous processing results in the tail bucket not having any valid + * entries, the tail bucket is the static bucket, the scope is a locked + * scope, and CHAIN_PTR=0, hardware evicts the static bucket from the + * cache and the completion signals this case with CHAIN_UPD=1. * If any + * of the previous processing results in the tail bucket not having any + * valid entries, and the tail bucket is not the static bucket, the tail + * bucket is removed from the chain. In this case, the penultimate + * bucket in the chain becomes the tail bucket. It has CHAIN set to 0 to + * unlink the tail bucket, and CHAIN_PTR set to that from the original + * tail bucket to preserve background chaining. The completion signals + * this case with CHAIN_UPD=1 and returns the index to the bucket + * removed so that software can de-allocate it. CFA returns OK status if + * the entry was successfully deleted. Otherwise, it returns EM_MISS + * status assuming there were no errors that caused processing to be + * aborted. + */ +enum cfa_bld_mpc_em_delete_cmd_fields { + CFA_BLD_MPC_EM_DELETE_CMD_OPAQUE_FLD = 0, + /* + * Sets the OPTION field on the cache interface to use write-through for + * EM entry writes while processing EM_INSERT commands. For all other + * cases (inluding EM_INSERT bucket writes), the OPTION field is set by + * the CACHE_OPTION and CACHE_OPTION2 fields. + */ + CFA_BLD_MPC_EM_DELETE_CMD_WRITE_THROUGH_FLD = 1, + /* Table scope to access. */ + CFA_BLD_MPC_EM_DELETE_CMD_TABLE_SCOPE_FLD = 2, + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + CFA_BLD_MPC_EM_DELETE_CMD_CACHE_OPTION_FLD = 3, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. Entry index + * to delete. + */ + CFA_BLD_MPC_EM_DELETE_CMD_TABLE_INDEX_FLD = 4, + /* + * Determines setting of OPTION field for all cache write requests for + * EM_INSERT, EM_DELETE, and EM_CHAIN commands. CFA does not support + * posted write requests. Therefore, CACHE_OPTION2[1] must be set to 0. + */ + CFA_BLD_MPC_EM_DELETE_CMD_CACHE_OPTION2_FLD = 5, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. Static + * bucket address for bucket chain. + */ + CFA_BLD_MPC_EM_DELETE_CMD_TABLE_INDEX2_FLD = 6, + CFA_BLD_MPC_EM_DELETE_CMD_MAX_FLD = 7, +}; + +/** + * Field IDS for EM_CHAIN_CMD: This command updates CHAIN_PTR in the + * tail bucket of a static bucket chain, supplying both the static + * bucket and the new CHAIN_PTR value. TABLE_INDEX is the new CHAIN_PTR + * value and TABLE_INDEX2[23:0] is the static bucket. This command + * provides software a means to update background chaining coherently + * with other bucket updates. The value of CHAIN is unaffected (stays at + * 0). For locked scopes, if the static bucket is the tail bucket, it is + * empty (all of its ENTRY_PTR values are 0), and TABLE_INDEX=0 (the + * CHAIN_PTR is being set to 0), instead of updating the static bucket + * it is evicted from the cache. In this case, CHAIN_UPD=1 in the + * completion. + */ +enum cfa_bld_mpc_em_chain_cmd_fields { + CFA_BLD_MPC_EM_CHAIN_CMD_OPAQUE_FLD = 0, + /* + * Sets the OPTION field on the cache interface to use write-through for + * EM entry writes while processing EM_INSERT commands. For all other + * cases (inluding EM_INSERT bucket writes), the OPTION field is set by + * the CACHE_OPTION and CACHE_OPTION2 fields. + */ + CFA_BLD_MPC_EM_CHAIN_CMD_WRITE_THROUGH_FLD = 1, + /* Table scope to access. */ + CFA_BLD_MPC_EM_CHAIN_CMD_TABLE_SCOPE_FLD = 2, + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + CFA_BLD_MPC_EM_CHAIN_CMD_CACHE_OPTION_FLD = 3, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. New + * CHAIN_PTR to write to tail bucket. + */ + CFA_BLD_MPC_EM_CHAIN_CMD_TABLE_INDEX_FLD = 4, + /* + * Determines setting of OPTION field for all cache write requests for + * EM_INSERT, EM_DELETE, and EM_CHAIN commands. CFA does not support + * posted write requests. Therefore, CACHE_OPTION2[1] must be set to 0. + */ + CFA_BLD_MPC_EM_CHAIN_CMD_CACHE_OPTION2_FLD = 5, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. Static + * bucket address for bucket chain. + */ + CFA_BLD_MPC_EM_CHAIN_CMD_TABLE_INDEX2_FLD = 6, + CFA_BLD_MPC_EM_CHAIN_CMD_MAX_FLD = 7, +}; + +/** + * Field IDS for READ_CMP: When no errors, teturns 1-4 consecutive 32B + * words from the TABLE_INDEX within the TABLE_SCOPE specified in the + * command, writing them to HOST_ADDRESS from the command. + */ +enum cfa_bld_mpc_read_cmp_fields { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + CFA_BLD_MPC_READ_CMP_TYPE_FLD = 0, + /* The command processing status. */ + CFA_BLD_MPC_READ_CMP_STATUS_FLD = 1, + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + CFA_BLD_MPC_READ_CMP_MP_CLIENT_FLD = 2, + /* OPCODE from the command. */ + CFA_BLD_MPC_READ_CMP_OPCODE_FLD = 3, + /* + * The length of the DMA that accompanies the completion in units of + * DWORDs (32b). Valid values are [0, 128]. A value of zero indicates + * that there is no DMA that accompanies the completion. + */ + CFA_BLD_MPC_READ_CMP_DMA_LENGTH_FLD = 4, + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + CFA_BLD_MPC_READ_CMP_OPAQUE_FLD = 5, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_BLD_MPC_READ_CMP_V_FLD = 6, + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + CFA_BLD_MPC_READ_CMP_HASH_MSB_FLD = 7, + /* TABLE_TYPE from the command. */ + CFA_BLD_MPC_READ_CMP_TABLE_TYPE_FLD = 8, + /* TABLE_SCOPE from the command. */ + CFA_BLD_MPC_READ_CMP_TABLE_SCOPE_FLD = 9, + /* TABLE_INDEX from the command. */ + CFA_BLD_MPC_READ_CMP_TABLE_INDEX_FLD = 10, + CFA_BLD_MPC_READ_CMP_MAX_FLD = 11, +}; + +/** + * Field IDS for WRITE_CMP: Returns status of the write of 1-4 + * consecutive 32B words starting at TABLE_INDEX in the table specified + * by (TABLE_TYPE, TABLE_SCOPE). + */ +enum cfa_bld_mpc_write_cmp_fields { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + CFA_BLD_MPC_WRITE_CMP_TYPE_FLD = 0, + /* The command processing status. */ + CFA_BLD_MPC_WRITE_CMP_STATUS_FLD = 1, + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + CFA_BLD_MPC_WRITE_CMP_MP_CLIENT_FLD = 2, + /* OPCODE from the command. */ + CFA_BLD_MPC_WRITE_CMP_OPCODE_FLD = 3, + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + CFA_BLD_MPC_WRITE_CMP_OPAQUE_FLD = 4, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_BLD_MPC_WRITE_CMP_V_FLD = 5, + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + CFA_BLD_MPC_WRITE_CMP_HASH_MSB_FLD = 6, + /* TABLE_TYPE from the command. */ + CFA_BLD_MPC_WRITE_CMP_TABLE_TYPE_FLD = 7, + /* TABLE_SCOPE from the command. */ + CFA_BLD_MPC_WRITE_CMP_TABLE_SCOPE_FLD = 8, + /* TABLE_INDEX from the command. */ + CFA_BLD_MPC_WRITE_CMP_TABLE_INDEX_FLD = 9, + CFA_BLD_MPC_WRITE_CMP_MAX_FLD = 10, +}; + +/** + * Field IDS for READ_CLR_CMP: When no errors, returns 1 32B word from + * TABLE_INDEX in the table specified by (TABLE_TYPE, TABLE_SCOPE). The + * data returned is the value prior to the clear. + */ +enum cfa_bld_mpc_read_clr_cmp_fields { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + CFA_BLD_MPC_READ_CLR_CMP_TYPE_FLD = 0, + /* The command processing status. */ + CFA_BLD_MPC_READ_CLR_CMP_STATUS_FLD = 1, + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + CFA_BLD_MPC_READ_CLR_CMP_MP_CLIENT_FLD = 2, + /* OPCODE from the command. */ + CFA_BLD_MPC_READ_CLR_CMP_OPCODE_FLD = 3, + /* + * The length of the DMA that accompanies the completion in units of + * DWORDs (32b). Valid values are [0, 128]. A value of zero indicates + * that there is no DMA that accompanies the completion. + */ + CFA_BLD_MPC_READ_CLR_CMP_DMA_LENGTH_FLD = 4, + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + CFA_BLD_MPC_READ_CLR_CMP_OPAQUE_FLD = 5, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_BLD_MPC_READ_CLR_CMP_V_FLD = 6, + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + CFA_BLD_MPC_READ_CLR_CMP_HASH_MSB_FLD = 7, + /* TABLE_TYPE from the command. */ + CFA_BLD_MPC_READ_CLR_CMP_TABLE_TYPE_FLD = 8, + /* TABLE_SCOPE from the command. */ + CFA_BLD_MPC_READ_CLR_CMP_TABLE_SCOPE_FLD = 9, + /* TABLE_INDEX from the command. */ + CFA_BLD_MPC_READ_CLR_CMP_TABLE_INDEX_FLD = 10, + CFA_BLD_MPC_READ_CLR_CMP_MAX_FLD = 11, +}; + +/** + * Field IDS for INVALIDATE_CMP: Returns status for INVALIDATE commands. + */ +enum cfa_bld_mpc_invalidate_cmp_fields { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + CFA_BLD_MPC_INVALIDATE_CMP_TYPE_FLD = 0, + /* The command processing status. */ + CFA_BLD_MPC_INVALIDATE_CMP_STATUS_FLD = 1, + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + CFA_BLD_MPC_INVALIDATE_CMP_MP_CLIENT_FLD = 2, + /* OPCODE from the command. */ + CFA_BLD_MPC_INVALIDATE_CMP_OPCODE_FLD = 3, + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + CFA_BLD_MPC_INVALIDATE_CMP_OPAQUE_FLD = 4, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_BLD_MPC_INVALIDATE_CMP_V_FLD = 5, + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + CFA_BLD_MPC_INVALIDATE_CMP_HASH_MSB_FLD = 6, + /* TABLE_TYPE from the command. */ + CFA_BLD_MPC_INVALIDATE_CMP_TABLE_TYPE_FLD = 7, + /* TABLE_SCOPE from the command. */ + CFA_BLD_MPC_INVALIDATE_CMP_TABLE_SCOPE_FLD = 8, + /* TABLE_INDEX from the command. */ + CFA_BLD_MPC_INVALIDATE_CMP_TABLE_INDEX_FLD = 9, + CFA_BLD_MPC_INVALIDATE_CMP_MAX_FLD = 10, +}; + +/** + * Field IDS for EM_SEARCH_CMP: For OK status, returns the index of the + * matching entry found for the EM key supplied in the command. Returns + * EM_MISS status if no match was found. + */ +enum cfa_bld_mpc_em_search_cmp_fields { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + CFA_BLD_MPC_EM_SEARCH_CMP_TYPE_FLD = 0, + /* The command processing status. */ + CFA_BLD_MPC_EM_SEARCH_CMP_STATUS_FLD = 1, + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + CFA_BLD_MPC_EM_SEARCH_CMP_MP_CLIENT_FLD = 2, + /* OPCODE from the command. */ + CFA_BLD_MPC_EM_SEARCH_CMP_OPCODE_FLD = 3, + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + CFA_BLD_MPC_EM_SEARCH_CMP_OPAQUE_FLD = 4, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_BLD_MPC_EM_SEARCH_CMP_V1_FLD = 5, + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + CFA_BLD_MPC_EM_SEARCH_CMP_HASH_MSB_FLD = 6, + /* TABLE_SCOPE from the command. */ + CFA_BLD_MPC_EM_SEARCH_CMP_TABLE_SCOPE_FLD = 7, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. For OK + * status, gives ENTRY_PTR[25:0] of the matching entry found. Otherwise, + * set to 0. + */ + CFA_BLD_MPC_EM_SEARCH_CMP_TABLE_INDEX_FLD = 8, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. If the hash + * is computed (no errors during initial processing of the command), + * TABLE_INDEX2[23:0] is the static bucket address determined from the + * hash of the exact match entry key in the command and the (EM_SIZE, + * EM_BUCKETS) configuration for TABLE_SCOPE of the command. Bits 25:24 + * in this case are set to 0. For any other status, it is always 0. + */ + CFA_BLD_MPC_EM_SEARCH_CMP_TABLE_INDEX2_FLD = 9, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_BLD_MPC_EM_SEARCH_CMP_V2_FLD = 10, + /* + * BKT_NUM is the bucket number in chain of the tail bucket after + * finishing processing the command, except when the command stops + * processing before the tail bucket. NUM_ENTRIES is the number of valid + * entries in the BKT_NUM bucket. The following describes the cases + * where BKT_NUM and NUM_ENTRIES are not for the tail bucket after + * finishing processing of the command: * For UNSPRT_ERR, FMT_ERR, + * SCOPE_ERR, or ADDR_ERR completion status, BKT_NUM will be set to 0. * + * For CACHE_ERR completion status, BKT_NUM will be set to the bucket + * number that was last read without error. If ERR=1 in the response to + * the static bucket read, BKT_NUM and NUM_ENTRIES are set to 0. The + * static bucket is number 0, BKT_NUM increments for each new bucket in + * the chain, and saturates at 255. Therefore, if the value is 255, + * BKT_NUM may or may not be accurate. In this case, though, NUM_ENTRIES + * will still be the correct value as described above for the bucket. + */ + CFA_BLD_MPC_EM_SEARCH_CMP_BKT_NUM_FLD = 11, + /* See BKT_NUM description. */ + CFA_BLD_MPC_EM_SEARCH_CMP_NUM_ENTRIES_FLD = 12, + CFA_BLD_MPC_EM_SEARCH_CMP_MAX_FLD = 13, +}; + +/** + * Field IDS for EM_INSERT_CMP: OK status indicates that the exact match + * entry from the command was successfully inserted. EM_DUPLICATE status + * indicates that the insert was aborted because an entry with the same + * exact match key was found and REPLACE=0 in the command. EM_ABORT + * status indicates that no duplicate was found, the tail bucket in the + * chain was full, and TABLE_INDEX2=0. No changes are made to the + * database in this case. TABLE_INDEX is the starting address at which + * to insert the exact match entry (from the command). TABLE_INDEX2 is + * the address at which to insert a new bucket at the tail of the static + * bucket chain if needed (from the command). CHAIN_UPD=1 if a new + * bucket was added at this address. TABLE_INDEX3 is the static bucket + * address for the chain, determined from hashing the exact match entry. + * Software needs this address and TABLE_INDEX in order to delete the + * entry using an EM_DELETE command. TABLE_INDEX4 is the index of an + * entry found that had a matching exact match key to the command entry + * key. If no matching entry was found, it is set to 0. There are two + * cases when there is a matching entry, depending on REPLACE from the + * command: * REPLACE=0: EM_DUPLICATE status is reported and the insert + * is aborted. Software can use the static bucket address + * (TABLE_INDEX3[23:0]) and the matching entry (TABLE_INDEX4) in an + * EM_DELETE command if it wishes to explicity delete the matching + * entry. * REPLACE=1: REPLACED_ENTRY=1 to signal that the entry at + * TABLE_INDEX4 was replaced by the insert entry. REPLACED_ENTRY will + * only be 1 if reporting OK status in this case. Software can de- + * allocate the entry at TABLE_INDEX4. + */ +enum cfa_bld_mpc_em_insert_cmp_fields { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + CFA_BLD_MPC_EM_INSERT_CMP_TYPE_FLD = 0, + /* The command processing status. */ + CFA_BLD_MPC_EM_INSERT_CMP_STATUS_FLD = 1, + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + CFA_BLD_MPC_EM_INSERT_CMP_MP_CLIENT_FLD = 2, + /* OPCODE from the command. */ + CFA_BLD_MPC_EM_INSERT_CMP_OPCODE_FLD = 3, + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + CFA_BLD_MPC_EM_INSERT_CMP_OPAQUE_FLD = 4, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_BLD_MPC_EM_INSERT_CMP_V1_FLD = 5, + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + CFA_BLD_MPC_EM_INSERT_CMP_HASH_MSB_FLD = 6, + /* TABLE_SCOPE from the command. */ + CFA_BLD_MPC_EM_INSERT_CMP_TABLE_SCOPE_FLD = 7, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX + * from the command, which is the starting address at which to insert + * the exact match entry. + */ + CFA_BLD_MPC_EM_INSERT_CMP_TABLE_INDEX_FLD = 8, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX2 + * from the command, which is the index for the new tail bucket to add + * if needed (CHAIN_UPD=1 if it was used). + */ + CFA_BLD_MPC_EM_INSERT_CMP_TABLE_INDEX2_FLD = 9, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. If the hash + * is computed (no errors during initial processing of the command), + * TABLE_INDEX2[23:0] is the static bucket address determined from the + * hash of the exact match entry key in the command and the (EM_SIZE, + * EM_BUCKETS) configuration for TABLE_SCOPE of the command. Bits 25:24 + * in this case are set to 0. For any other status, it is always 0. + */ + CFA_BLD_MPC_EM_INSERT_CMP_TABLE_INDEX3_FLD = 10, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_BLD_MPC_EM_INSERT_CMP_V2_FLD = 11, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. ENTRY_PTR of + * matching entry found. Set to 0 if no matching entry found. If + * REPLACED_ENTRY=1, that indicates a matching entry was found and + * REPLACE=1 in the command. In this case, the matching entry was + * replaced by the new entry in the command and this index can therefore + * by de-allocated. + */ + CFA_BLD_MPC_EM_INSERT_CMP_TABLE_INDEX4_FLD = 12, + /* + * BKT_NUM is the bucket number in chain of the tail bucket after + * finishing processing the command, except when the command stops + * processing before the tail bucket. NUM_ENTRIES is the number of valid + * entries in the BKT_NUM bucket. The following describes the cases + * where BKT_NUM and NUM_ENTRIES are not for the tail bucket after + * finishing processing of the command: * For UNSPRT_ERR, FMT_ERR, + * SCOPE_ERR, or ADDR_ERR completion status, BKT_NUM will be set to 0. * + * For CACHE_ERR completion status, BKT_NUM will be set to the bucket + * number that was last read without error. If ERR=1 in the response to + * the static bucket read, BKT_NUM and NUM_ENTRIES are set to 0. The + * static bucket is number 0, BKT_NUM increments for each new bucket in + * the chain, and saturates at 255. Therefore, if the value is 255, + * BKT_NUM may or may not be accurate. In this case, though, NUM_ENTRIES + * will still be the correct value as described above for the bucket. + */ + CFA_BLD_MPC_EM_INSERT_CMP_BKT_NUM_FLD = 13, + /* See BKT_NUM description. */ + CFA_BLD_MPC_EM_INSERT_CMP_NUM_ENTRIES_FLD = 14, + /* + * Specifies if the chain was updated while processing the command: Set + * to 1 when a new bucket is added to the tail of the static bucket + * chain at TABLE_INDEX2. This occurs if and only if the insert requires + * adding a new entry and the tail bucket is full. If set to 0, + * TABLE_INDEX2 was not used and is therefore still free. + */ + CFA_BLD_MPC_EM_INSERT_CMP_CHAIN_UPD_FLD = 15, + /* + * Set to 1 if a matching entry was found and REPLACE=1 in command. In + * the case, the entry starting at TABLE_INDEX4 was replaced and can + * therefore be de-allocated. Otherwise, this flag is set to 0. + */ + CFA_BLD_MPC_EM_INSERT_CMP_REPLACED_ENTRY_FLD = 16, + CFA_BLD_MPC_EM_INSERT_CMP_MAX_FLD = 17, +}; + +/** + * Field IDS for EM_DELETE_CMP: OK status indicates that an ENTRY_PTR + * matching TABLE_INDEX was found in the static bucket chain specified + * and was therefore deleted. EM_MISS status indicates that no match was + * found. TABLE_INDEX is from the command. It is the index of the entry + * to delete. TABLE_INDEX2 is from the command. It is the static bucket + * address. TABLE_INDEX3 is the index of the tail bucket of the static + * bucket chain prior to processing the command. TABLE_INDEX4 is the + * index of the tail bucket of the static bucket chain after processing + * the command. If CHAIN_UPD=1 and TABLE_INDEX4==TABLE_INDEX2, the + * static bucket was the tail bucket, it became empty after the delete, + * the scope is a locked scope, and CHAIN_PTR was 0. In this case, the + * static bucket has been evicted from the cache. Otherwise, if + * CHAIN_UPD=1, the original tail bucket given by TABLE_INDEX3 was + * removed from the chain because it went empty. It can therefore be de- + * allocated. + */ +enum cfa_bld_mpc_em_delete_cmp_fields { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + CFA_BLD_MPC_EM_DELETE_CMP_TYPE_FLD = 0, + /* The command processing status. */ + CFA_BLD_MPC_EM_DELETE_CMP_STATUS_FLD = 1, + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + CFA_BLD_MPC_EM_DELETE_CMP_MP_CLIENT_FLD = 2, + /* OPCODE from the command. */ + CFA_BLD_MPC_EM_DELETE_CMP_OPCODE_FLD = 3, + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + CFA_BLD_MPC_EM_DELETE_CMP_OPAQUE_FLD = 4, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_BLD_MPC_EM_DELETE_CMP_V1_FLD = 5, + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + CFA_BLD_MPC_EM_DELETE_CMP_HASH_MSB_FLD = 6, + /* TABLE_SCOPE from the command. */ + CFA_BLD_MPC_EM_DELETE_CMP_TABLE_SCOPE_FLD = 7, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX + * from the command, which is the index of the entry to delete. + */ + CFA_BLD_MPC_EM_DELETE_CMP_TABLE_INDEX_FLD = 8, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX2 + * from the command. + */ + CFA_BLD_MPC_EM_DELETE_CMP_TABLE_INDEX2_FLD = 9, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. For OK or + * EM_MISS status, the index of the tail bucket of the chain prior to + * processing the command. If CHAIN_UPD=1, the bucket was removed and + * this index can be de-allocated. For other status values, it is set to + * 0. + */ + CFA_BLD_MPC_EM_DELETE_CMP_TABLE_INDEX3_FLD = 10, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_BLD_MPC_EM_DELETE_CMP_V2_FLD = 11, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. For OK or + * EM_MISS status, the index of the tail bucket of the chain prior to + * after the command. If CHAIN_UPD=0 (always for EM_MISS status), it is + * always equal to TABLE_INDEX3 as the chain was not updated. For other + * status values, it is set to 0. + */ + CFA_BLD_MPC_EM_DELETE_CMP_TABLE_INDEX4_FLD = 12, + /* + * BKT_NUM is the bucket number in chain of the tail bucket after + * finishing processing the command, except when the command stops + * processing before the tail bucket. NUM_ENTRIES is the number of valid + * entries in the BKT_NUM bucket. The following describes the cases + * where BKT_NUM and NUM_ENTRIES are not for the tail bucket after + * finishing processing of the command: * For UNSPRT_ERR, FMT_ERR, + * SCOPE_ERR, or ADDR_ERR completion status, BKT_NUM will be set to 0. * + * For CACHE_ERR completion status, BKT_NUM will be set to the bucket + * number that was last read without error. If ERR=1 in the response to + * the static bucket read, BKT_NUM and NUM_ENTRIES are set to 0. The + * static bucket is number 0, BKT_NUM increments for each new bucket in + * the chain, and saturates at 255. Therefore, if the value is 255, + * BKT_NUM may or may not be accurate. In this case, though, NUM_ENTRIES + * will still be the correct value as described above for the bucket. + */ + CFA_BLD_MPC_EM_DELETE_CMP_BKT_NUM_FLD = 13, + /* See BKT_NUM description. */ + CFA_BLD_MPC_EM_DELETE_CMP_NUM_ENTRIES_FLD = 14, + /* + * Specifies if the chain was updated while processing the command: Set + * to 1 when a bucket is removed from the static bucket chain. This + * occurs if after the delete, the tail bucket is a dynamic bucket and + * no longer has any valid entries. In this case, software should de- + * allocate the dynamic bucket at TABLE_INDEX3. It is also set to 1 when + * the static bucket is evicted, which only occurs for locked scopes. + * See the EM_DELETE command description for details. + */ + CFA_BLD_MPC_EM_DELETE_CMP_CHAIN_UPD_FLD = 15, + CFA_BLD_MPC_EM_DELETE_CMP_MAX_FLD = 16, +}; + +/** + * Field IDS for EM_CHAIN_CMP: OK status indicates that the CHAIN_PTR of + * the tail bucket was successfully updated. TABLE_INDEX is from the + * command. It is the value of the new CHAIN_PTR. TABLE_INDEX2 is from + * the command. TABLE_INDEX3 is the index of the tail bucket of the + * static bucket chain. + */ +enum cfa_bld_mpc_em_chain_cmp_fields { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + CFA_BLD_MPC_EM_CHAIN_CMP_TYPE_FLD = 0, + /* The command processing status. */ + CFA_BLD_MPC_EM_CHAIN_CMP_STATUS_FLD = 1, + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + CFA_BLD_MPC_EM_CHAIN_CMP_MP_CLIENT_FLD = 2, + /* OPCODE from the command. */ + CFA_BLD_MPC_EM_CHAIN_CMP_OPCODE_FLD = 3, + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + CFA_BLD_MPC_EM_CHAIN_CMP_OPAQUE_FLD = 4, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_BLD_MPC_EM_CHAIN_CMP_V1_FLD = 5, + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + CFA_BLD_MPC_EM_CHAIN_CMP_HASH_MSB_FLD = 6, + /* TABLE_SCOPE from the command. */ + CFA_BLD_MPC_EM_CHAIN_CMP_TABLE_SCOPE_FLD = 7, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX + * from the command, which is the new CHAIN_PTR for the tail bucket of + * the static bucket chain. + */ + CFA_BLD_MPC_EM_CHAIN_CMP_TABLE_INDEX_FLD = 8, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX2 + * from the command. + */ + CFA_BLD_MPC_EM_CHAIN_CMP_TABLE_INDEX2_FLD = 9, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. For OK + * status, the index of the tail bucket of the chain. Otherwise, set to + * 0. + */ + CFA_BLD_MPC_EM_CHAIN_CMP_TABLE_INDEX3_FLD = 10, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_BLD_MPC_EM_CHAIN_CMP_V2_FLD = 11, + /* + * BKT_NUM is the bucket number in chain of the tail bucket after + * finishing processing the command, except when the command stops + * processing before the tail bucket. NUM_ENTRIES is the number of valid + * entries in the BKT_NUM bucket. The following describes the cases + * where BKT_NUM and NUM_ENTRIES are not for the tail bucket after + * finishing processing of the command: * For UNSPRT_ERR, FMT_ERR, + * SCOPE_ERR, or ADDR_ERR completion status, BKT_NUM will be set to 0. * + * For CACHE_ERR completion status, BKT_NUM will be set to the bucket + * number that was last read without error. If ERR=1 in the response to + * the static bucket read, BKT_NUM and NUM_ENTRIES are set to 0. The + * static bucket is number 0, BKT_NUM increments for each new bucket in + * the chain, and saturates at 255. Therefore, if the value is 255, + * BKT_NUM may or may not be accurate. In this case, though, NUM_ENTRIES + * will still be the correct value as described above for the bucket. + */ + CFA_BLD_MPC_EM_CHAIN_CMP_BKT_NUM_FLD = 12, + /* See BKT_NUM description. */ + CFA_BLD_MPC_EM_CHAIN_CMP_NUM_ENTRIES_FLD = 13, + /* + * Set to 1 when the scope is a locked scope, the tail bucket is the + * static bucket, the bucket is empty (all of its ENTRY_PTR values are + * 0), and TABLE_INDEX=0 in the command. In this case, the static bucket + * is evicted. For all other cases, it is set to 0. + */ + CFA_BLD_MPC_EM_CHAIN_CMP_CHAIN_UPD_FLD = 14, + CFA_BLD_MPC_EM_CHAIN_CMP_MAX_FLD = 15, +}; + +#endif /* _CFA_BLD_MPC_FIELD_IDS_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_mpcops.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_mpcops.h new file mode 100644 index 0000000000..5f607e0caa --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_mpcops.h @@ -0,0 +1,598 @@ +/**************************************************************************** + * Copyright(c) 2021 - 2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_bld_mpcops.h + * + * @brief CFA Builder MPC ops interface for host applications + */ + +#ifndef _CFA_BLD_MPCOPS_H_ +#define _CFA_BLD_MPCOPS_H_ + +#include +#include "cfa_types.h" + +/** + * CFA HW data object definition + */ +struct cfa_mpc_data_obj { + /** [in] MPC field identifier */ + uint16_t field_id; + /** [in] Value of the HW field */ + uint64_t val; +}; + +struct cfa_bld_mpcops; + +/** + * @addtogroup CFA_BLD CFA Builder Library + * \ingroup CFA_V3 + * @{ + */ + +/** + * CFA MPC ops interface + */ +struct cfa_bld_mpcinfo { + /** [out] CFA MPC Builder operations function pointer table */ + const struct cfa_bld_mpcops *mpcops; +}; + +/** + * @name CFA_BLD_MPC CFA Builder Host MPC OPS API + * CFA builder host specific API used by host CFA application to bind + * to different CFA devices and access device by using MPC OPS. + */ + +/**@{*/ +/** CFA builder MPC bind API + * + * This API retrieves the CFA global MPC configuration. + * + * @param[in] hw_ver + * hardware version of the CFA + * + * @param[out] mpc_info + * CFA MPC interface + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int cfa_bld_mpc_bind(enum cfa_ver hw_ver, struct cfa_bld_mpcinfo *mpc_info); + +/** CFA device specific function hooks for CFA MPC command composition + * and response parsing + * + * The following device hooks can be defined; unless noted otherwise, they are + * optional and can be filled with a null pointer. The pupose of these hooks + * to support CFA device operations for different device variants. + */ +struct cfa_bld_mpcops { + /** Build MPC Cache read command + * + * This API composes the MPC cache read command given the list + * of read parameters specified as an array of cfa_mpc_data_obj objects. + * + * @param[in] cmd + * MPC command buffer to compose the cache read command into. + * + * @param[in,out] cmd_buff_len + * Pointer to command buffer length variable. The caller sets this + * to the size of the 'cmd' buffer in byes. The api updates this to + * the actual size of the composed command. If the buffer length + * passed is not large enough to hold the composed command, an error + * is returned by the api. + * + * @param[in] fields + * Array of CFA data objects indexed by CFA_BLD_MPC_READ_CMD_XXX_FLD + * enum values. The size of this array shall be + * CFA_BLD_MPC_READ_CMD_MAX_FLD. If the caller intends to set a + * specific field in the MPC command, the caller should set the + * field_id in cfa_mpc_data_obj to the array index itself (See example + * below). Otherwise set the field_id to INVALID_U16. If the caller + * sets the field_id for a field that is not valid for the device + * an error is returned. + * + * To set the table type to EM: + * fields[CFA_BLD_MPC_READ_CMD_TABLE_TYPE_FLD].field_id = + * CFA_BLD_MPC_READ_CMD_TABLE_TYPE_FLD; + * fields[CFA_BLD_MPC_READ_CMD_TABLE_TYPE_FLD].val = + * CFA_HW_TABLE_LOOKUP; + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_build_cache_read)(uint8_t *cmd, + uint32_t *cmd_buff_len, + struct cfa_mpc_data_obj *fields); + + /** Build MPC Cache Write command + * + * This API composes the MPC cache write command given the list + * of write parameters specified as an array of cfa_mpc_data_obj + * objects. + * + * @param[in] cmd + * MPC command buffer to compose the cache write command into. + * + * @param[in,out] cmd_buff_len + * Pointer to command buffer length variable. The caller sets this + * to the size of the 'cmd' buffer in byes. The api updates this to + * the actual size of the composed command. If the buffer length + * passed is not large enough to hold the composed command, an error + * is returned by the api. + * + * @param[in] data + * Pointer to the data to be written. Note that this data is just + * copied at the right offset into the command buffer. The actual MPC + * write happens when the command is issued over the MPC interface. + * + * @param[in] fields + * Array of CFA data objects indexed by CFA_BLD_MPC_WRITE_CMD_XXX_FLD + * enum values. The size of this array shall be + * CFA_BLD_MPC_WRITE_CMD_MAX_FLD. If the caller intends to set a + * specific field in the MPC command, the caller should set the + * field_id in cfa_mpc_data_obj to the array index itself. Otherwise + * set the field_id to INVALID_U16. If the caller sets the field_id for + * a field that is not valid for the device an error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_build_cache_write)(uint8_t *cmd, + uint32_t *cmd_buff_len, + const uint8_t *data, + struct cfa_mpc_data_obj *fields); + + /** Build MPC Cache Invalidate (Evict) command + * + * This API composes the MPC cache evict command given the list + * of evict parameters specified as an array of cfa_mpc_data_obj + * objects. + * + * @param[in] cmd + * MPC command buffer to compose the cache evict command into. + * + * @param[in,out] cmd_buff_len + * Pointer to command buffer length variable. The caller sets this + * to the size of the 'cmd' buffer in byes. The api updates this to + * the actual size of the composed command. If the buffer length + * passed is not large enough to hold the composed command, an error + * is returned by the api. + * + * @param[in] fields + * Array of cfa_mpc_data_obj indexed by + * CFA_BLD_MPC_INVALIDATE_CMD_XXX_FLD enum values. The size of this + * array shall be CFA_BLD_MPC_INVALIDATE_CMD_MAX_FLD. If the caller + * intends to set a specific field in the MPC command, the caller + * should set the field_id in cfa_mpc_data_obj to the array index + * itself. Otherwise set the field_id to INVALID_U16. If the caller + * sets the field_id for a field that is not valid for the device an + * error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_build_cache_evict)(uint8_t *cmd, + uint32_t *cmd_buff_len, + struct cfa_mpc_data_obj *fields); + + /** Build MPC Cache read and clear command + * + * This API composes the MPC cache read-n-clear command given the list + * of read parameters specified as an array of cfa_mpc_data_obj objects. + * + * @param[in] cmd + * MPC command buffer to compose the cache read-n-clear command into. + * + * @param[in,out] cmd_buff_len + * Pointer to command buffer length variable. The caller sets this + * to the size of the 'cmd' buffer in byes. The api updates this to + * the actual size of the composed command. If the buffer length + * passed is not large enough to hold the composed command, an error + * is returned by the api. + * + * @param[in] fields + * Array of cfa_mpc_data_obj indexed by + * CFA_BLD_MPC_READ_CLR_CMD_XXX_FLD enum values. The size of this + * array shall be CFA_BLD_MPC_READ_CLR_CMD_MAX_FLD. If the caller + * intends to set a specific field in the MPC command, the caller + * should set the field_id in cfa_mpc_data_obj to the array index + * itself. Otherwise set the field_id to INVALID_U16. If the caller + * sets the field_id for a field that is not valid for the device + * an error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_build_cache_read_clr)(uint8_t *cmd, + uint32_t *cmd_buff_len, + struct cfa_mpc_data_obj *fields); + + /** Build MPC EM search command + * + * This API composes the MPC EM search command given the list + * of EM search parameters specified as an array of cfa_mpc_data_obj + * objects + * + * @param[in] cmd + * MPC command buffer to compose the EM search command into. + * + * @param[in,out] cmd_buff_len + * Pointer to command buffer length variable. The caller sets this + * to the size of the 'cmd' buffer in byes. The api updates this to + * the actual size of the composed command. If the buffer length + * passed is not large enough to hold the composed command, an error + * is returned by the api. + * + * @param[in] em_entry + * Pointer to the em_entry to be searched. + * + * @param[in] fields + * Array of cfa_mpc_data_obj indexed by + * CFA_BLD_MPC_EM_SEARCH_CMD_XXX_FLD enum values. The size of this + * array shall be CFA_BLD_MPC_EM_SEARCH_CMD_MAX_FLD. If the caller + * intends to set a specific field in the MPC command, the caller + * should set the field_id in cfa_mpc_data_obj to the array index + * itself. Otherwise set the field_id to INVALID_U16. If the caller + * sets the field_id for a field that is not valid for the device an + * error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_build_em_search)(uint8_t *cmd, uint32_t *cmd_buff_len, + uint8_t *em_entry, + struct cfa_mpc_data_obj *fields); + + /** Build MPC EM insert command + * + * This API composes the MPC EM insert command given the list + * of EM insert parameters specified as an array of cfa_mpc_data_obj objects + * + * @param[in] cmd + * MPC command buffer to compose the EM insert command into. + * + * @param[in,out] cmd_buff_len + * Pointer to command buffer length variable. The caller sets this + * to the size of the 'cmd' buffer in bytes. The api updates this to + * the actual size of the composed command. If the buffer length + * passed is not large enough to hold the composed command, an error + * is returned by the api. + * + * @param[in] em_entry + * Pointer to the em_entry to be inserted. + * + * @param[in] fields + * Array of cfa_mpc_data_obj indexed by CFA_BLD_MPC_EM_INSERT_CMD_XXX_FLD + * enum values. The size of this array shall be + * CFA_BLD_MPC_EM_INSERT_CMD_MAX_FLD. If the caller intends to set a + * specific field in the MPC command, the caller should set the + * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set + * the field_id to INVALID_U16. If the caller sets the field_id for a + * field that is not valid for the device an error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_build_em_insert)(uint8_t *cmd, uint32_t *cmd_buff_len, + const uint8_t *em_entry, + struct cfa_mpc_data_obj *fields); + + /** Build MPC EM delete command + * + * This API composes the MPC EM delete command given the list + * of EM delete parameters specified as an array of cfa_mpc_data_obj objects + * + * @param[in] cmd + * MPC command buffer to compose the EM delete command into. + * + * @param[in,out] cmd_buff_len + * Pointer to command buffer length variable. The caller sets this + * to the size of the 'cmd' buffer in byes. The api updates this to + * the actual size of the composed command. If the buffer length + * passed is not large enough to hold the composed command, an error + * is returned by the api. + * + * @param[in] fields + * Array of cfa_mpc_data_obj indexed by CFA_BLD_MPC_EM_DELETE_CMD_XXX_FLD + * enum values. The size of this array shall be + * CFA_BLD_MPC_EM_DELETE_CMD_MAX_FLD. If the caller intends to set a + * specific field in the MPC command, the caller should set the + * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set + * the field_id to INVALID_U16. If the caller sets the field_id for a + * field that is not valid for the device an error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_build_em_delete)(uint8_t *cmd, uint32_t *cmd_buff_len, + struct cfa_mpc_data_obj *fields); + + /** Build MPC EM chain command + * + * This API composes the MPC EM chain command given the list + * of EM chain parameters specified as an array of cfa_mpc_data_obj objects + * + * @param[in] cmd + * MPC command buffer to compose the EM chain command into. + * + * @param[in,out] cmd_buff_len + * Pointer to command buffer length variable. The caller sets this + * to the size of the 'cmd' buffer in byes. The api updates this to + * the actual size of the composed command. If the buffer length + * passed is not large enough to hold the composed command, an error + * is returned by the api. + * + * @param[in] fields + * Array of cfa_mpc_data_obj indexed by CFA_BLD_MPC_EM_CHAIN_CMD_XXX_FLD + * enum values. The size of this array shall be + * CFA_BLD_MPC_EM_CHAIN_CMD_MAX_FLD. If the caller intends to set a + * specific field in the MPC command, the caller should set the + * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set + * the field_id to INVALID_U16. If the caller sets the field_id for a + * field that is not valid for the device an error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_build_em_chain)(uint8_t *cmd, uint32_t *cmd_buff_len, + struct cfa_mpc_data_obj *fields); + + /** Parse MPC Cache read response + * + * This API parses the MPC cache read response message and returns + * the read parameters as an array of cfa_mpc_data_obj objects. + * + * @param[in] resp + * MPC response buffer containing the cache read response. + * + * @param[in] resp_buff_len + * Response buffer length in bytes + * + * @param[in] rd_data + * Buffer to copy the MPC read data into + * + * @param[in] rd_data_len + * Size of the rd_data buffer in bytes + * + * @param[out] fields + * Array of CFA data objects indexed by CFA_BLD_MPC_READ_CMP_XXX_FLD + * enum values. The size of this array shall be + * CFA_BLD_MPC_READ_CMP_MAX_FLD. If the caller intends to retrieve a + * specific field in the MPC response, the caller should set the + * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set + * the field_id to INVALID_U16. If the caller sets the field_id for a + * field that is not valid for the device an error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_parse_cache_read)(uint8_t *resp, + uint32_t resp_buff_len, + uint8_t *rd_data, + uint32_t rd_data_len, + struct cfa_mpc_data_obj *fields); + + /** Parse MPC Cache Write response + * + * This API parses the MPC cache write response message and returns + * the write response fields as an array of cfa_mpc_data_obj objects. + * + * @param[in] resp + * MPC response buffer containing the cache write response. + * + * @param[in] resp_buff_len + * Response buffer length in bytes + * + * @param[out] fields + * Array of CFA data objects indexed by CFA_BLD_MPC_WRITE_CMP_XXX_FLD + * enum values. The size of this array shall be + * CFA_BLD_MPC_WRITE_CMP_MAX_FLD. If the caller intends to retrieve a + * specific field in the MPC response, the caller should set the + * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set + * the field_id to INVALID_U16. If the caller sets the field_id for a + * field that is not valid for the device an error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_parse_cache_write)(uint8_t *resp, + uint32_t resp_buff_len, + struct cfa_mpc_data_obj *fields); + + /** Parse MPC Cache Invalidate (Evict) response + * + * This API parses the MPC cache evict response message and returns + * the evict response fields as an array of cfa_mpc_data_obj objects. + * + * @param[in] resp + * MPC response buffer containing the cache evict response. + * + * @param[in] resp_buff_len + * Response buffer length in bytes + * + * @param[out] fields + * Array of cfa_mpc_data_obj indexed by CFA_BLD_MPC_INVALIDATE_CMP_XXX_FLD + * enum values. The size of this array shall be + * CFA_BLD_MPC_INVALIDATE_CMP_MAX_FLD. If the caller intends to get a + * specific field in the MPC response, the caller should set the + * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set + * the field_id to INVALID_U16. If the caller sets the field_id for a + * field that is not valid for the device an error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_parse_cache_evict)(uint8_t *resp, + uint32_t resp_buff_len, + struct cfa_mpc_data_obj *fields); + + /* clang-format off */ + /** Parse MPC Cache read and clear response + * + * This API parses the MPC cache read-n-clear response message and + * returns the read response fields as an array of cfa_mpc_data_obj objects. + * + * @param[in] resp + * MPC response buffer containing the cache read-n-clear response. + * + * @param[in] resp_buff_len + * Response buffer length in bytes + * + * @param[in] rd_data + * Buffer to copy the MPC read data into + * + * @param[in] rd_data_len + * Size of the rd_data buffer in bytes + * + * @param[out] fields + * Array of cfa_mpc_data_obj indexed by CFA_BLD_MPC_READ_CLR_CMP_XXX_FLD + * enum values. The size of this array shall be + * CFA_BLD_MPC_READ_CLR_CMP_MAX_FLD. If the caller intends to get a + * specific field in the MPC response, the caller should set the + * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set + * the field_id to INVALID_U16. If the caller sets the field_id for a + * field that is not valid for the device an error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_parse_cache_read_clr)(uint8_t *resp, + uint32_t resp_buff_len, uint8_t *rd_data, + uint32_t rd_data_len, struct cfa_mpc_data_obj *fields); + + /* clang-format on */ + /** Parse MPC EM search response + * + * This API parses the MPC EM search response message and returns + * the EM search response fields as an array of cfa_mpc_data_obj objects + * + * @param[in] resp + * MPC response buffer containing the EM search response. + * + * @param[in] resp_buff_len + * Response buffer length in bytes + * + * @param[out] fields + * Array of cfa_mpc_data_obj indexed by CFA_BLD_MPC_EM_SEARCH_CMP_XXX_FLD + * enum values. The size of this array shall be + * CFA_BLD_MPC_EM_SEARCH_CMP_MAX_FLD. If the caller intends to get a + * specific field in the MPC response, the caller should set the + * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set + * the field_id to INVALID_U16. If the caller sets the field_id for a + * field that is not valid for the device an error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_parse_em_search)(uint8_t *resp, + uint32_t resp_buff_len, + struct cfa_mpc_data_obj *fields); + + /** Parse MPC EM insert response + * + * This API parses the MPC EM insert response message and returns + * the EM insert response fields as an array of cfa_mpc_data_obj objects + * + * @param[in] resp + * MPC response buffer containing the EM insert response. + * + * @param[in] resp_buff_len + * Response buffer length in bytes + * + * @param[out] fields + * Array of cfa_mpc_data_obj indexed by CFA_BLD_MPC_EM_INSERT_CMP_XXX_FLD + * enum values. The size of this array shall be + * CFA_BLD_MPC_EM_INSERT_CMP_MAX_FLD. If the caller intends to get a + * specific field in the MPC response, the caller should set the + * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set + * the field_id to INVALID_U16. If the caller sets the field_id for a + * field that is not valid for the device an error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_parse_em_insert)(uint8_t *resp, + uint32_t resp_buff_len, + struct cfa_mpc_data_obj *fields); + + /** Parse MPC EM delete response + * + * This API parses the MPC EM delete response message and returns + * the EM delete response fields as an array of cfa_mpc_data_obj objects + * + * @param[in] resp + * MPC response buffer containing the EM delete response. + * + * @param[in] resp_buff_len + * Response buffer length in bytes + * + * @param[out] fields + * Array of cfa_mpc_data_obj indexed by CFA_BLD_MPC_EM_DELETE_CMP_XXX_FLD + * enum values. The size of this array shall be + * CFA_BLD_MPC_EM_DELETE_CMP_MAX_FLD. If the caller intends to get a + * specific field in the MPC response, the caller should set the + * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set + * the field_id to INVALID_U16. If the caller sets the field_id for a + * field that is not valid for the device an error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_parse_em_delete)(uint8_t *resp, + uint32_t resp_buff_len, + struct cfa_mpc_data_obj *fields); + + /** Parse MPC EM chain response + * + * This API parses the MPC EM chain response message and returns + * the EM chain response fields as an array of cfa_mpc_data_obj objects + * + * @param[in] resp + * MPC response buffer containing the EM chain response. + * + * @param[in] resp_buff_len + * Response buffer length in bytes + * + * @param[out] fields + * Array of cfa_mpc_data_obj indexed by CFA_BLD_MPC_EM_CHAIN_CMP_XXX_FLD + * enum values. The size of this array shall be + * CFA_BLD_MPC_EM_CHAIN_CMP_MAX_FLD. If the caller intends to get a + * specific field in the MPC response, the caller should set the + * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set + * the field_id to INVALID_U16. If the caller sets the field_id for a + * field that is not valid for the device an error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_parse_em_chain)(uint8_t *resp, uint32_t resp_buff_len, + struct cfa_mpc_data_obj *fields); +}; + +/**@}*/ + +/**@}*/ +#endif /* _CFA_BLD_DEVOPS_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_bld_p70_defs.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_bld_p70_defs.h new file mode 100644 index 0000000000..b2e3cf14f7 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_bld_p70_defs.h @@ -0,0 +1,543 @@ +/**************************************************************************** + * Copyright(c) 2021 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_bld_p70.h + * + * @brief CFA Phase 7.0 specific Builder public definitions + */ + +#ifndef _CFA_BLD_P70_H_ +#define _CFA_BLD_P70_H_ + +#include "sys_util.h" +#include "cfa_bld_defs.h" +#include "cfa_bld_p70_field_ids.h" + +/** + * Maximum key array size + */ +#define CFA_P70_KEY_MAX_FIELD_CNT \ + MAX((uint16_t)CFA_P70_EM_KEY_LAYOUT_MAX_FLD, \ + (uint16_t)CFA_P70_WC_TCAM_FKB_MAX_FLD) +#define CFA_P70_ACT_MAX_TEMPLATE_SZ sizeof(struct cfa_bld_p70_action_template) + +#define CFA_P70_PROF_MAX_KEYS 4 +enum cfa_p70_mac_sel_mode { + CFA_P70_MAC_SEL_MODE_FIRST = 0, + CFA_P70_MAC_SEL_MODE_LOWEST = 1 +}; + +struct cfa_p70_prof_key_cfg { + uint8_t mac_sel[CFA_P70_PROF_MAX_KEYS]; +#define CFA_PROF_P70_MAC_SEL_DMAC0 (1 << 0) +#define CFA_PROF_P70_MAC_SEL_T_MAC0 (1 << 1) +#define CFA_PROF_P70_MAC_SEL_OUTERMOST_MAC0 (1 << 2) +#define CFA_PROF_P70_MAC_SEL_DMAC1 (1 << 3) +#define CFA_PROF_P70_MAC_SEL_T_MAC1 (1 << 4) +#define CFA_PROF_P70_MAC_OUTERMOST_MAC1 (1 << 5) + uint8_t vlan_sel[CFA_P70_PROF_MAX_KEYS]; +#define CFA_PROF_P70_VLAN_SEL_INNER_HDR 0 +#define CFA_PROF_P70_VLAN_SEL_TUNNEL_HDR 1 +#define CFA_PROF_P70_VLAN_SEL_OUTERMOST_HDR 2 + uint8_t pass_cnt; + enum cfa_p70_mac_sel_mode mode; +}; + +/* + * Field id remap function pointer. Passed by cfa-v3 caller + * to builder apis if the caller requires the apis to remap + * the field ids before using them to update key/action layout + * objects. An example of one such api is action_compute_ptr() + * which updates the offsets for the modify/encap/source/stat + * records in the action record. If the caller is remapping + * the field ids (to save memory in fw builds for example), then + * this remap api is required to be passed. If passed as NULL, + * the field ids are not remapped and used directly to index + * into the layout. + * + * @param Input field id + * + * @return Remapped field id on success, UNIT16_MAX on failure. + */ +typedef uint16_t(cfa_fld_remap)(uint16_t); + +/** + * CFA P70 action layout definition + */ + +enum action_type_p70 { + /** Select this type to build an Full Action Record Object + */ + CFA_P70_ACT_OBJ_TYPE_FULL_ACT, + /** Select this type to build an Compact Action Record Object + */ + CFA_P70_ACT_OBJ_TYPE_COMPACT_ACT, + /** Select this type to build an MCG Action Record Object + */ + CFA_P70_ACT_OBJ_TYPE_MCG_ACT, + /** Select this type to build Standalone Modify Action Record Object */ + CFA_P70_ACT_OBJ_TYPE_MODIFY, + /** Select this type to build Standalone Stat Action Record Object */ + CFA_P70_ACT_OBJ_TYPE_STAT, + /** Select this type to build Standalone Source Action Record Object */ + CFA_P70_ACT_OBJ_TYPE_SRC_PROP, + /** Select this type to build Standalone Encap Action Record Object */ + CFA_P70_ACT_OBJ_TYPE_ENCAP, +}; + +enum stat_op_p70 { + /** Set to statistic to ingress to CFA + */ + CFA_P70_STAT_OP_INGRESS = 0, + /** Set to statistic to egress from CFA + */ + CFA_P70_STAT_OP_EGRESS = 1, +}; + +enum stat_type_p70 { + /** Set to statistic to Foward packet count(64b)/Foward byte + * count(64b) + */ + CFA_P70_STAT_COUNTER_SIZE_16B = 0, + /** Set to statistic to Forward packet count(64b)/Forward byte + * count(64b)/ TCP Flags(16b)/Timestamp(32b) + */ + CFA_P70_STAT_COUNTER_SIZE_24B = 1, + /** Set to statistic to Forward packet count(64b)/Forward byte + * count(64b)/Meter(drop or red) packet count(64b)/Meter(drop + * or red) byte count(64b) + */ + CFA_P70_STAT_COUNTER_SIZE_32B = 2, + /** Set to statistic to Forward packet count(64b)/Forward byte + * count(64b)/Meter(drop or red) packet count(38b)/Meter(drop + * or red) byte count(42b)/TCP Flags(16b)/Timestamp(32b) + */ + CFA_P70_STAT_COUNTER_SIZE_32B_ALL = 3, +}; + +enum encap_vtag_p70 { + CFA_P70_ACT_ENCAP_VTAGS_PUSH_0 = 0, + CFA_P70_ACT_ENCAP_VTAGS_PUSH_1, + CFA_P70_ACT_ENCAP_VTAGS_PUSH_2 +}; + +enum encap_l3_p70 { + /** Set to disable any L3 encapsulation + * processing, default + */ + CFA_P70_ACT_ENCAP_L3_NONE = 0, + /** Set to enable L3 IPv4 encapsulation + */ + CFA_P70_ACT_ENCAP_L3_IPV4 = 4, + /** Set to enable L3 IPv6 encapsulation + */ + CFA_P70_ACT_ENCAP_L3_IPV6 = 5, + /** Set to enable L3 MPLS 8847 encapsulation + */ + CFA_P70_ACT_ENCAP_L3_MPLS_8847 = 6, + /** Set to enable L3 MPLS 8848 encapsulation + */ + CFA_P70_ACT_ENCAP_L3_MPLS_8848 = 7 +}; + +enum encap_tunnel_p70 { + /** Set to disable Tunnel header encapsulation + * processing, default + */ + CFA_P70_ACT_ENCAP_TNL_NONE = 0, + /** Set to enable Tunnel Generic Full header + * encapsulation + */ + CFA_P70_ACT_ENCAP_TNL_GENERIC_FULL, + /** Set to enable VXLAN header encapsulation + */ + CFA_P70_ACT_ENCAP_TNL_VXLAN, + /** Set to enable NGE (VXLAN2) header encapsulation + */ + CFA_P70_ACT_ENCAP_TNL_NGE, + /** Set to enable NVGRE header encapsulation + */ + CFA_P70_ACT_ENCAP_TNL_NVGRE, + /** Set to enable GRE header encapsulation + */ + CFA_P70_ACT_ENCAP_TNL_GRE, + /** Set to enable Generic header after Tunnel + * L4 encapsulation + */ + CFA_P70_ACT_ENCAP_TNL_GENERIC_AFTER_TL4, + /** Set to enable Generic header after Tunnel + * encapsulation + */ + CFA_P70_ACT_ENCAP_TNL_GENERIC_AFTER_TNL +}; + +enum source_rec_type_p70 { + /** Set to Source MAC Address + */ + CFA_P70_SOURCE_MAC = 0, + /** Set to Source MAC and IPv4 Addresses + */ + CFA_P70_SOURCE_MAC_IPV4 = 1, + /** Set to Source MAC and IPv6 Addresses + */ + CFA_P70_SOURCE_MAC_IPV6 = 2, +}; + +/** + * From CFA phase 7.0 onwards, setting the modify vector bit + * 'ACT_MODIFY_TUNNEL_MODIFY' requires corresponding data fields to be + * set. This enum defines the parameters that determine the + * layout of this associated data fields. This structure + * is not used for versions older than CFA Phase 7.0 and setting + * the 'ACT_MODIFY_TUNNEL_MODIFY' bit will just delete the internal tunnel + */ +enum tunnel_modify_mode_p70 { + /* No change to tunnel protocol */ + CFA_P70_ACT_MOD_TNL_NO_PROTO_CHANGE = 0, + /* 8-bit tunnel protocol change */ + CFA_P70_ACT_MOD_TNL_8B_PROTO_CHANGE = 1, + /* 16-bit tunnel protocol change */ + CFA_P70_ACT_MOD_TNL_16B_PROTO_CHANGE = 2, + CFA_P70_ACT_MOD_TNL_MAX +}; + +/** + * Action object template structure + * + * Template structure presents data fields that are necessary to know + * at the beginning of Action Builder (AB) processing. Like before the + * AB compilation. One such example could be a template that is + * flexible in size (Encap Record) and the presence of these fields + * allows for determining the template size as well as where the + * fields are located in the record. + * + * The template may also present fields that are not made visible to + * the caller by way of the action fields. + * + * Template fields also allow for additional checking on user visible + * fields. One such example could be the encap pointer behavior on a + * CFA_P70_ACT_OBJ_TYPE_ACT or CFA_P70_ACT_OBJ_TYPE_ACT_SRAM. + */ +struct cfa_bld_p70_action_template { + /** Action Object type + * + * Controls the type of the Action Template + */ + enum action_type_p70 obj_type; + + /** Action Control + * + * Controls the internals of the Action Template + * + * act is valid when: + * ((obj_type == CFA_P70_ACT_OBJ_TYPE_FULL_ACT) + * || + * (obj_type == CFA_P70_ACT_OBJ_TYPE_COMPACT_ACT)) + * + * Specifies whether each action is to be in-line or not. + */ + struct { + /** Set to true to enable statistics + */ + uint8_t stat_enable; + /** Set to true to enable statistics to be inlined + */ + uint8_t stat_inline; + /** Set to true to enable statistics 1 + */ + uint8_t stat1_enable; + /** Set to true to enable statistics 1 to be inlined + */ + uint8_t stat1_inline; + /** Set to true to enable encapsulation + */ + uint8_t encap_enable; + /** Set to true to enable encapsulation to be inlined + */ + uint8_t encap_inline; + /** Set to true to align the encap record to cache + * line + */ + uint8_t encap_align; + /** Set to true to source + */ + uint8_t source_enable; + /** Set to true to enable source to be inlined + */ + uint8_t source_inline; + /** Set to true to enable modfication + */ + uint8_t mod_enable; + /** Set to true to enable modify to be inlined + */ + uint8_t mod_inline; + /** Set to true to enable subsequent MCGs + */ + uint8_t mcg_subseq_enable; + } act; + + /** Statistic Control + * Controls the type of statistic the template is describing + * + * stat is valid when: + * ((obj_type == CFA_P70_ACT_OBJ_TYPE_FULL_ACT) || + * (obj_type == CFA_P70_ACT_OBJ_TYPE_COMPACT_ACT)) && + * act.stat_enable || act.stat_inline) + */ + struct { + enum stat_op_p70 op; + enum stat_type_p70 type; + } stat; + + /** Encap Control + * Controls the type of encapsulation the template is + * describing + * + * encap is valid when: + * ((obj_type == CFA_P70_ACT_OBJ_TYPE_FULL_ACT) || + * (obj_type == CFA_P70_ACT_OBJ_TYPE_COMPACT_ACT) && + * act.encap_enable || act.encap_inline) + */ + struct { + /** Set to true to enable L2 capability in the + * template + */ + uint8_t l2_enable; + /** vtag controls the Encap Vector - VTAG Encoding, 4 bits + * + *
    + *
  • CFA_P70_ACT_ENCAP_VTAGS_PUSH_0, default, no VLAN + * Tags applied + *
  • CFA_P70_ACT_ENCAP_VTAGS_PUSH_1, adds capability to + * set 1 VLAN Tag. Action Template compile adds + * the following field to the action object + * TF_ER_VLAN1 + *
  • CFA_P70_ACT_ENCAP_VTAGS_PUSH_2, adds capability to + * set 2 VLAN Tags. Action Template compile adds + * the following fields to the action object + * TF_ER_VLAN1 and TF_ER_VLAN2 + *
+ */ + enum encap_vtag_p70 vtag; + + /* + * The remaining fields are NOT supported when + * direction is RX and ((obj_type == + * CFA_P70_ACT_OBJ_TYPE_ACT) && act.encap_enable). + * cfa_bld_p70_action_compile_layout will perform the + * checking and skip remaining fields. + */ + /** L3 Encap controls the Encap Vector - L3 Encoding, + * 3 bits. Defines the type of L3 Encapsulation the + * template is describing. + *
    + *
  • CFA_P70_ACT_ENCAP_L3_NONE, default, no L3 + * Encapsulation processing. + *
  • CFA_P70_ACT_ENCAP_L3_IPV4, enables L3 IPv4 + * Encapsulation. + *
  • CFA_P70_ACT_ENCAP_L3_IPV6, enables L3 IPv6 + * Encapsulation. + *
  • CFA_P70_ACT_ENCAP_L3_MPLS_8847, enables L3 MPLS + * 8847 Encapsulation. + *
  • CFA_P70_ACT_ENCAP_L3_MPLS_8848, enables L3 MPLS + * 8848 Encapsulation. + *
+ */ + enum encap_l3_p70 l3; + +#define CFA_P70_ACT_ENCAP_MAX_MPLS_LABELS 8 + /** 1-8 labels, valid when + * (l3 == CFA_P70_ACT_ENCAP_L3_MPLS_8847) || + * (l3 == CFA_P70_ACT_ENCAP_L3_MPLS_8848) + * + * MAX number of MPLS Labels 8. + */ + uint8_t l3_num_mpls_labels; + + /** Set to true to enable L4 capability in the + * template. + * + * true adds TF_EN_UDP_SRC_PORT and + * TF_EN_UDP_DST_PORT to the template. + */ + uint8_t l4_enable; + + /** Tunnel Encap controls the Encap Vector - Tunnel + * Encap, 3 bits. Defines the type of Tunnel + * encapsulation the template is describing + *
    + *
  • CFA_P70_ACT_ENCAP_TNL_NONE, default, no Tunnel + * Encapsulation processing. + *
  • CFA_P70_ACT_ENCAP_TNL_GENERIC_FULL + *
  • CFA_P70_ACT_ENCAP_TNL_VXLAN. NOTE: Expects + * l4_enable set to true; + *
  • CFA_P70_ACT_ENCAP_TNL_NGE. NOTE: Expects l4_enable + * set to true; + *
  • CFA_P70_ACT_ENCAP_TNL_NVGRE. NOTE: only valid if + * l4_enable set to false. + *
  • CFA_P70_ACT_ENCAP_TNL_GRE.NOTE: only valid if + * l4_enable set to false. + *
  • CFA_P70_ACT_ENCAP_TNL_GENERIC_AFTER_TL4 + *
  • CFA_P70_ACT_ENCAP_TNL_GENERIC_AFTER_TNL + *
+ */ + enum encap_tunnel_p70 tnl; + +#define CFA_P70_ACT_ENCAP_MAX_TUNNEL_GENERIC_SIZE 128 + /** Number of bytes of generic tunnel header, + * valid when + * (tnl == CFA_P70_ACT_ENCAP_TNL_GENERIC_FULL) || + * (tnl == CFA_P70_ACT_ENCAP_TNL_GENERIC_AFTER_TL4) || + * (tnl == CFA_P70_ACT_ENCAP_TNL_GENERIC_AFTER_TNL) + */ + uint8_t tnl_generic_size; + +#define CFA_P70_ACT_ENCAP_MAX_OPLEN 15 + /** Number of 32b words of nge options, + * valid when + * (tnl == CFA_P70_ACT_ENCAP_TNL_NGE) + */ + uint8_t tnl_nge_op_len; + + /** Set to true to enable MAC/VLAN/IP/TNL overrides in the + * template + */ + bool encap_override; + /* Currently not planned */ + /* Custom Header */ + /* uint8_t custom_enable; */ + } encap; + + /** Modify Control + * + * Controls the type of the Modify Action the template is + * describing + * + * modify is valid when: + * ((obj_type == CFA_P70_ACT_OBJ_TYPE_FULL_ACT) || + * (obj_type == CFA_P70_ACT_OBJ_TYPE_COMPACT_ACT) && + * act.modify_enable || act.modify_inline) + */ +/** Set to enable Modify of Metadata + */ +#define CFA_P70_ACT_MODIFY_META 0x1 +/** Set to enable Delete of Outer VLAN + */ +#define CFA_P70_ACT_MODIFY_DEL_OVLAN 0x2 +/** Set to enable Delete of Inner VLAN + */ +#define CFA_P70_ACT_MODIFY_DEL_IVLAN 0x4 +/** Set to enable Replace or Add of Outer VLAN + */ +#define CFA_P70_ACT_MODIFY_REPL_ADD_OVLAN 0x8 +/** Set to enable Replace or Add of Inner VLAN + */ +#define CFA_P70_ACT_MODIFY_REPL_ADD_IVLAN 0x10 +/** Set to enable Modify of TTL + */ +#define CFA_P70_ACT_MODIFY_TTL_UPDATE 0x20 +/** Set to enable delete of INT Tunnel + */ +#define CFA_P70_ACT_MODIFY_DEL_INT_TNL 0x40 +/** For phase 7.0 this bit can be used to modify the + * tunnel protocol in addition to deleting internal + * or outer tunnel + */ +#define CFA_P70_ACT_MODIFY_TUNNEL_MODIFY CFA_P70_ACT_MODIFY_DEL_INT_TNL +/** Set to enable Modify of Field + */ +#define CFA_P70_ACT_MODIFY_FIELD 0x80 +/** Set to enable Modify of Destination MAC + */ +#define CFA_P70_ACT_MODIFY_DMAC 0x100 +/** Set to enable Modify of Source MAC + */ +#define CFA_P70_ACT_MODIFY_SMAC 0x200 +/** Set to enable Modify of Source IPv6 Address + */ +#define CFA_P70_ACT_MODIFY_SRC_IPV6 0x400 +/** Set to enable Modify of Destination IPv6 Address + */ +#define CFA_P70_ACT_MODIFY_DST_IPV6 0x800 +/** Set to enable Modify of Source IPv4 Address + */ +#define CFA_P70_ACT_MODIFY_SRC_IPV4 0x1000 +/** Set to enable Modify of Destination IPv4 Address + */ +#define CFA_P70_ACT_MODIFY_DST_IPV4 0x2000 +/** Set to enable Modify of L4 Source Port + */ +#define CFA_P70_ACT_MODIFY_SRC_PORT 0x4000 +/** Set to enable Modify of L4 Destination Port + */ +#define CFA_P70_ACT_MODIFY_DST_PORT 0x8000 + uint16_t modify; + +/** Set to enable Modify of KID + */ +#define CFA_P70_ACT_MODIFY_FIELD_KID 0x1 + uint16_t field_modify; + + /* Valid for phase 7.0 or higher */ + enum tunnel_modify_mode_p70 tnl_mod_mode; + + /** Source Control + * + * Controls the type of the Source Action the template is + * describing + * + * source is valid when: + * ((obj_type == CFA_P70_ACT_OBJ_TYPE_FULL_ACT) || + * (obj_type == CFA_P70_ACT_OBJ_TYPE_COMPACT_ACT) && + * act.source_enable || act.source_inline) + */ + enum source_rec_type_p70 source; +}; + +/** + * Key template consists of key fields that can be enabled/disabled + * individually. + */ +struct cfa_p70_key_template { + /** [in] Identify if the key template is for TCAM. If false, the + * key template is for EM. This field is mandantory for device that + * only support fix key formats. + */ + bool is_wc_tcam_key; + /** [in] Identify if the key template will be use for IPv6 Keys. + * + * Note: This is important for SR2 as the field length for the Flow Id + * is dependent on the L3 flow type. For SR2 for IPv4 Keys, the Flow + * Id field is 16 bits, for all other types (IPv6, ARP, PTP, EAP, RoCE, + * FCoE, UPAR), the Flow Id field length is 20 bits. + */ + bool is_ipv6_key; + /** [in] key field enable field array, set 1 to the correspeonding + * field enable to make a field valid + */ + uint8_t field_en[CFA_P70_KEY_MAX_FIELD_CNT]; +}; + +/** + * Action template consists of action fields that can be enabled/disabled + * individually. + */ +struct cfa_p70_action_template { + /** [in] CFA version for the action template */ + enum cfa_ver hw_ver; + /** [in] action field enable field array, set 1 to the correspeonding + * field enable to make a field valid + */ + uint8_t data[CFA_P70_ACT_MAX_TEMPLATE_SZ]; +}; + +#define CFA_PROF_L2CTXT_TCAM_MAX_FIELD_CNT CFA_P70_PROF_L2_CTXT_TCAM_MAX_FLD +#define CFA_PROF_L2CTXT_REMAP_MAX_FIELD_CNT CFA_P70_PROF_L2_CTXT_RMP_DR_MAX_FLD +#define CFA_PROF_MAX_KEY_CFG_SZ sizeof(struct cfa_p70_prof_key_cfg) + +#endif /* _CFA_BLD_P70_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_bld_p70_field_ids.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_bld_p70_field_ids.h new file mode 100644 index 0000000000..8fd04f6cf9 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_bld_p70_field_ids.h @@ -0,0 +1,1542 @@ +/**************************************************************************** + * Copyright(c) 2001-2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * Name: cfa_bld_p70_field_ids.h + * + * Description: Enumerations definitions for CFA phase 7.0 HW table fields + * Action record fields and Lookup Key (EM/WC-TCAM) fields. + * + * Date: 09/29/22 11:50:37 + * + * Note: This file is scripted generated by ./cfa_header_gen.py. + * DO NOT modify this file manually !!!! + * + ****************************************************************************/ +#ifndef _CFA_BLD_P70_FIELD_IDS_H_ +#define _CFA_BLD_P70_FIELD_IDS_H_ + +/* clang-format off */ + +/** + * Lookup Field Range Check Range Memory Fields: + */ +enum cfa_p70_lkup_frc_profile_flds { + CFA_P70_LKUP_FRC_PROFILE_FIELD_SEL_1_FLD = 0, + CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_1_FLD = 1, + CFA_P70_LKUP_FRC_PROFILE_FIELD_SEL_0_FLD = 2, + CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_FLD = 3, + CFA_P70_LKUP_FRC_PROFILE_MAX_FLD +}; + +/** + * Lookup Connection Tracking State Memory Fields: + */ +enum cfa_p70_lkup_ct_state_flds { + CFA_P70_LKUP_CT_STATE_NOTIFY_FLD = 0, + CFA_P70_LKUP_CT_STATE_NOTIFY_STATE_FLD = 1, + CFA_P70_LKUP_CT_STATE_ACTION_FLD = 2, + CFA_P70_LKUP_CT_STATE_TIMER_SELECT_FLD = 3, + CFA_P70_LKUP_CT_STATE_TIMER_PRELOAD_FLD = 4, + CFA_P70_LKUP_CT_STATE_MAX_FLD +}; + +/** + * Lookup Connection Tracking State Machine Rule Memory Fields: + */ +enum cfa_p70_lkup_ct_rule_flds { + CFA_P70_LKUP_CT_RULE_VALID_FLD = 0, + CFA_P70_LKUP_CT_RULE_MASK_FLD = 1, + CFA_P70_LKUP_CT_RULE_PKT_NOT_BG_FLD = 2, + CFA_P70_LKUP_CT_RULE_STATE_FLD = 3, + CFA_P70_LKUP_CT_RULE_TCP_FLAGS_FLD = 4, + CFA_P70_LKUP_CT_RULE_PROT_IS_TCP_FLD = 5, + CFA_P70_LKUP_CT_RULE_MSB_UPDT_FLD = 6, + CFA_P70_LKUP_CT_RULE_FLAGS_FAILED_FLD = 7, + CFA_P70_LKUP_CT_RULE_WIN_FAILED_FLD = 8, + CFA_P70_LKUP_CT_RULE_MAX_FLD +}; + +/** + * Lookup Connection Tracking State Machine Rule Record Memory Fields: + */ +enum cfa_p70_lkup_ct_rule_record_flds { + CFA_P70_LKUP_CT_RULE_RECORD_ACTION_FLD = 0, + CFA_P70_LKUP_CT_RULE_RECORD_NEXT_STATE_FLD = 1, + CFA_P70_LKUP_CT_RULE_RECORD_SEND_FLD = 2, + CFA_P70_LKUP_CT_RULE_RECORD_MAX_FLD +}; + +/** + * VEB Destination Bitmap Remap Table. Fields: + */ +enum cfa_p70_act_veb_rmp_flds { + CFA_P70_ACT_VEB_RMP_MODE_FLD = 0, + CFA_P70_ACT_VEB_RMP_ENABLE_FLD = 1, + CFA_P70_ACT_VEB_RMP_BITMAP_FLD = 2, + CFA_P70_ACT_VEB_RMP_MAX_FLD +}; + +/** + * Lookup Field Range Check Range Memory Fields: + */ +enum cfa_p70_lkup_frc_range_flds { + CFA_P70_LKUP_FRC_RANGE_RANGE_LO_FLD = 0, + CFA_P70_LKUP_FRC_RANGE_RANGE_HI_FLD = 1, + CFA_P70_LKUP_FRC_RANGE_MAX_FLD +}; + +/** + * L2 Context TCAM. Fields: + */ +enum cfa_p70_prof_l2_ctxt_tcam_flds { + CFA_P70_PROF_L2_CTXT_TCAM_VALID_FLD = 0, + CFA_P70_PROF_L2_CTXT_TCAM_SPARE_FLD = 1, + CFA_P70_PROF_L2_CTXT_TCAM_MPASS_CNT_FLD = 2, + CFA_P70_PROF_L2_CTXT_TCAM_RCYC_FLD = 3, + CFA_P70_PROF_L2_CTXT_TCAM_LOOPBACK_FLD = 4, + CFA_P70_PROF_L2_CTXT_TCAM_SPIF_FLD = 5, + CFA_P70_PROF_L2_CTXT_TCAM_PARIF_FLD = 6, + CFA_P70_PROF_L2_CTXT_TCAM_SVIF_FLD = 7, + CFA_P70_PROF_L2_CTXT_TCAM_METADATA_FLD = 8, + CFA_P70_PROF_L2_CTXT_TCAM_L2_FUNC_FLD = 9, + CFA_P70_PROF_L2_CTXT_TCAM_ROCE_FLD = 10, + CFA_P70_PROF_L2_CTXT_TCAM_PURE_LLC_FLD = 11, + CFA_P70_PROF_L2_CTXT_TCAM_OT_HDR_TYPE_FLD = 12, + CFA_P70_PROF_L2_CTXT_TCAM_T_HDR_TYPE_FLD = 13, + CFA_P70_PROF_L2_CTXT_TCAM_ID_CTXT_FLD = 14, + CFA_P70_PROF_L2_CTXT_TCAM_MAC0_FLD = 15, + CFA_P70_PROF_L2_CTXT_TCAM_MAC1_FLD = 16, + CFA_P70_PROF_L2_CTXT_TCAM_VTAG_PRESENT_FLD = 17, + CFA_P70_PROF_L2_CTXT_TCAM_TWO_VTAGS_FLD = 18, + CFA_P70_PROF_L2_CTXT_TCAM_OVLAN_VID_FLD = 19, + CFA_P70_PROF_L2_CTXT_TCAM_OVLAN_TPID_SEL_FLD = 20, + CFA_P70_PROF_L2_CTXT_TCAM_IVLAN_VID_FLD = 21, + CFA_P70_PROF_L2_CTXT_TCAM_IVLAN_TPID_SEL_FLD = 22, + CFA_P70_PROF_L2_CTXT_TCAM_ETYPE_FLD = 23, + CFA_P70_PROF_L2_CTXT_TCAM_MAX_FLD +}; + +/** + * Profiler Profile Lookup TCAM Fields: + */ +enum cfa_p70_prof_profile_tcam_flds { + CFA_P70_PROF_PROFILE_TCAM_VALID_FLD = 0, + CFA_P70_PROF_PROFILE_TCAM_SPARE_FLD = 1, + CFA_P70_PROF_PROFILE_TCAM_LOOPBACK_FLD = 2, + CFA_P70_PROF_PROFILE_TCAM_PKT_TYPE_FLD = 3, + CFA_P70_PROF_PROFILE_TCAM_RCYC_FLD = 4, + CFA_P70_PROF_PROFILE_TCAM_METADATA_FLD = 5, + CFA_P70_PROF_PROFILE_TCAM_AGG_ERROR_FLD = 6, + CFA_P70_PROF_PROFILE_TCAM_L2_FUNC_FLD = 7, + CFA_P70_PROF_PROFILE_TCAM_PROF_FUNC_FLD = 8, + CFA_P70_PROF_PROFILE_TCAM_HREC_NEXT_FLD = 9, + CFA_P70_PROF_PROFILE_TCAM_INT_HDR_TYPE_FLD = 10, + CFA_P70_PROF_PROFILE_TCAM_INT_HDR_GROUP_FLD = 11, + CFA_P70_PROF_PROFILE_TCAM_INT_IFA_TAIL_FLD = 12, + CFA_P70_PROF_PROFILE_TCAM_OTL2_HDR_VALID_FLD = 13, + CFA_P70_PROF_PROFILE_TCAM_OTL2_HDR_TYPE_FLD = 14, + CFA_P70_PROF_PROFILE_TCAM_OTL2_UC_MC_BC_FLD = 15, + CFA_P70_PROF_PROFILE_TCAM_OTL2_VTAG_PRESENT_FLD = 16, + CFA_P70_PROF_PROFILE_TCAM_OTL2_TWO_VTAGS_FLD = 17, + CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_VALID_FLD = 18, + CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_ERROR_FLD = 19, + CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_TYPE_FLD = 20, + CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_ISIP_FLD = 21, + CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_VALID_FLD = 22, + CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_ERROR_FLD = 23, + CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_TYPE_FLD = 24, + CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_IS_UDP_TCP_FLD = 25, + CFA_P70_PROF_PROFILE_TCAM_OT_HDR_VALID_FLD = 26, + CFA_P70_PROF_PROFILE_TCAM_OT_HDR_ERROR_FLD = 27, + CFA_P70_PROF_PROFILE_TCAM_OT_HDR_TYPE_FLD = 28, + CFA_P70_PROF_PROFILE_TCAM_OT_HDR_FLAGS_FLD = 29, + CFA_P70_PROF_PROFILE_TCAM_TL2_HDR_VALID_FLD = 30, + CFA_P70_PROF_PROFILE_TCAM_TL2_HDR_TYPE_FLD = 31, + CFA_P70_PROF_PROFILE_TCAM_TL2_UC_MC_BC_FLD = 32, + CFA_P70_PROF_PROFILE_TCAM_TL2_VTAG_PRESENT_FLD = 33, + CFA_P70_PROF_PROFILE_TCAM_TL2_TWO_VTAGS_FLD = 34, + CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_VALID_FLD = 35, + CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_ERROR_FLD = 36, + CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_TYPE_FLD = 37, + CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_ISIP_FLD = 38, + CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_VALID_FLD = 39, + CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_ERROR_FLD = 40, + CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_TYPE_FLD = 41, + CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_IS_UDP_TCP_FLD = 42, + CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_VALID_FLD = 43, + CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_ERROR_FLD = 44, + CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_TYPE_FLD = 45, + CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_FLAGS_FLD = 46, + CFA_P70_PROF_PROFILE_TCAM_L2_HDR_VALID_FLD = 47, + CFA_P70_PROF_PROFILE_TCAM_L2_HDR_ERROR_FLD = 48, + CFA_P70_PROF_PROFILE_TCAM_L2_HDR_TYPE_FLD = 49, + CFA_P70_PROF_PROFILE_TCAM_L2_UC_MC_BC_FLD = 50, + CFA_P70_PROF_PROFILE_TCAM_L2_VTAG_PRESENT_FLD = 51, + CFA_P70_PROF_PROFILE_TCAM_L2_TWO_VTAGS_FLD = 52, + CFA_P70_PROF_PROFILE_TCAM_L3_HDR_VALID_FLD = 53, + CFA_P70_PROF_PROFILE_TCAM_L3_HDR_ERROR_FLD = 54, + CFA_P70_PROF_PROFILE_TCAM_L3_HDR_TYPE_FLD = 55, + CFA_P70_PROF_PROFILE_TCAM_L3_HDR_ISIP_FLD = 56, + CFA_P70_PROF_PROFILE_TCAM_L3_PROT_FLD = 57, + CFA_P70_PROF_PROFILE_TCAM_L4_HDR_VALID_FLD = 58, + CFA_P70_PROF_PROFILE_TCAM_L4_HDR_ERROR_FLD = 59, + CFA_P70_PROF_PROFILE_TCAM_L4_HDR_TYPE_FLD = 60, + CFA_P70_PROF_PROFILE_TCAM_L4_HDR_IS_UDP_TCP_FLD = 61, + CFA_P70_PROF_PROFILE_TCAM_L4_HDR_SUBTYPE_FLD = 62, + CFA_P70_PROF_PROFILE_TCAM_L4_HDR_FLAGS_FLD = 63, + CFA_P70_PROF_PROFILE_TCAM_L4_DCN_PRESENT_FLD = 64, + CFA_P70_PROF_PROFILE_TCAM_MAX_FLD +}; + +/** + * Action VEB TCAM. TX Fields (VEB Remap Mode): + */ +enum cfa_p70_act_veb_tcam_tx_flds { + CFA_P70_ACT_VEB_TCAM_TX_VALID_FLD = 0, + CFA_P70_ACT_VEB_TCAM_TX_PARIF_IN_FLD = 1, + CFA_P70_ACT_VEB_TCAM_TX_NUM_VTAGS_FLD = 2, + CFA_P70_ACT_VEB_TCAM_TX_DMAC_FLD = 3, + CFA_P70_ACT_VEB_TCAM_TX_OVID_FLD = 4, + CFA_P70_ACT_VEB_TCAM_TX_IVID_FLD = 5, + CFA_P70_ACT_VEB_TCAM_TX_MAX_FLD +}; + +/** + * RX Fields (Source Knockout Mode): + */ +enum cfa_p70_act_veb_tcam_rx_flds { + CFA_P70_ACT_VEB_TCAM_RX_VALID_FLD = 0, + CFA_P70_ACT_VEB_TCAM_RX_SPARE_FLD = 1, + CFA_P70_ACT_VEB_TCAM_RX_PADDING_FLD = 2, + CFA_P70_ACT_VEB_TCAM_RX_UNICAST_FLD = 3, + CFA_P70_ACT_VEB_TCAM_RX_MULTICAST_FLD = 4, + CFA_P70_ACT_VEB_TCAM_RX_BROADCAST_FLD = 5, + CFA_P70_ACT_VEB_TCAM_RX_PFID_FLD = 6, + CFA_P70_ACT_VEB_TCAM_RX_VFID_FLD = 7, + CFA_P70_ACT_VEB_TCAM_RX_SMAC_FLD = 8, + CFA_P70_ACT_VEB_TCAM_RX_MAX_FLD +}; + +/** + * Action Feature Chaining TCAM. + */ +enum cfa_p70_act_fc_tcam_flds { + CFA_P70_ACT_FC_TCAM_FC_VALID_FLD = 0, + CFA_P70_ACT_FC_TCAM_FC_RSVD_FLD = 1, + CFA_P70_ACT_FC_TCAM_FC_METADATA_FLD = 2, + CFA_P70_ACT_FC_TCAM_MAX_FLD +}; + +/** + * Feature Chaining TCAM Remap Table Fields: + */ +enum cfa_p70_act_fc_rmp_dr_flds { + CFA_P70_ACT_FC_RMP_DR_METADATA_FLD = 0, + CFA_P70_ACT_FC_RMP_DR_METAMASK_FLD = 1, + CFA_P70_ACT_FC_RMP_DR_L2_FUNC_FLD = 2, + CFA_P70_ACT_FC_RMP_DR_MAX_FLD +}; + +/** + * Profile Input Lookup Table Memory Fields: + */ +enum cfa_p70_prof_ilt_dr_flds { + CFA_P70_PROF_ILT_DR_ILT_META_EN_FLD = 0, + CFA_P70_PROF_ILT_DR_META_PROF_FLD = 1, + CFA_P70_PROF_ILT_DR_METADATA_FLD = 2, + CFA_P70_PROF_ILT_DR_PARIF_FLD = 3, + CFA_P70_PROF_ILT_DR_L2_FUNC_FLD = 4, + CFA_P70_PROF_ILT_DR_EN_BD_META_FLD = 5, + CFA_P70_PROF_ILT_DR_EN_BD_ACTION_FLD = 6, + CFA_P70_PROF_ILT_DR_EN_ILT_DEST_FLD = 7, + CFA_P70_PROF_ILT_DR_ILT_FWD_OP_FLD = 8, + CFA_P70_PROF_ILT_DR_ILT_ACT_HINT_FLD = 9, + CFA_P70_PROF_ILT_DR_ILT_SCOPE_FLD = 10, + CFA_P70_PROF_ILT_DR_ILT_ACT_REC_PTR_FLD = 11, + CFA_P70_PROF_ILT_DR_ILT_DESTINATION_FLD = 12, + CFA_P70_PROF_ILT_DR_MAX_FLD +}; + +/** + * Profile Lookup TCAM Remap Table Fields: + */ +enum cfa_p70_prof_profile_rmp_dr_flds { + CFA_P70_PROF_PROFILE_RMP_DR_PL_BYP_LKUP_EN_FLD = 0, + CFA_P70_PROF_PROFILE_RMP_DR_EM_SEARCH_EN_FLD = 1, + CFA_P70_PROF_PROFILE_RMP_DR_EM_PROFILE_ID_FLD = 2, + CFA_P70_PROF_PROFILE_RMP_DR_EM_KEY_ID_FLD = 3, + CFA_P70_PROF_PROFILE_RMP_DR_EM_SCOPE_FLD = 4, + CFA_P70_PROF_PROFILE_RMP_DR_TCAM_SEARCH_EN_FLD = 5, + CFA_P70_PROF_PROFILE_RMP_DR_TCAM_PROFILE_ID_FLD = 6, + CFA_P70_PROF_PROFILE_RMP_DR_TCAM_KEY_ID_FLD = 7, + CFA_P70_PROF_PROFILE_RMP_DR_TCAM_SCOPE_FLD = 8, + CFA_P70_PROF_PROFILE_RMP_DR_MAX_FLD +}; + +/** + * PROF_PROFILE_RMP_DR_BYP + */ +enum cfa_p70_prof_profile_rmp_dr_byp_flds { + CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_BYP_LKUP_EN_FLD = 0, + CFA_P70_PROF_PROFILE_RMP_DR_BYP_RESERVED_FLD = 1, + CFA_P70_PROF_PROFILE_RMP_DR_BYP_BYPASS_OP_FLD = 2, + CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_ACT_HINT_FLD = 3, + CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_SCOPE_FLD = 4, + CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_ACT_REC_PTR_FLD = 5, + CFA_P70_PROF_PROFILE_RMP_DR_BYP_MAX_FLD +}; + +/** + * VNIC-SVIF Properties Table Fields: TX SVIF Properties Table + */ +enum cfa_p70_act_vspt_dr_tx_flds { + CFA_P70_ACT_VSPT_DR_TX_TPID_AS_CTL_FLD = 0, + CFA_P70_ACT_VSPT_DR_TX_ALWD_TPID_FLD = 1, + CFA_P70_ACT_VSPT_DR_TX_DFLT_TPID_FLD = 2, + CFA_P70_ACT_VSPT_DR_TX_PRI_AS_CTL_FLD = 3, + CFA_P70_ACT_VSPT_DR_TX_ALWD_PRI_FLD = 4, + CFA_P70_ACT_VSPT_DR_TX_DFLT_PRI_FLD = 5, + CFA_P70_ACT_VSPT_DR_TX_MIR_FLD = 6, + CFA_P70_ACT_VSPT_DR_TX_MAX_FLD +}; + +/** + * RX VNIC Properties Table + */ +enum cfa_p70_act_vspt_dr_rx_flds { + CFA_P70_ACT_VSPT_DR_RX_RSVD_FLD = 0, + CFA_P70_ACT_VSPT_DR_RX_METAFMT_FLD = 1, + CFA_P70_ACT_VSPT_DR_RX_FID_FLD = 2, + CFA_P70_ACT_VSPT_DR_RX_MIR_FLD = 3, + CFA_P70_ACT_VSPT_DR_RX_MAX_FLD +}; + +/** + * LAG ID Balance Table Fields: + */ +enum cfa_p70_act_lbt_dr_flds { + CFA_P70_ACT_LBT_DR_DST_BMP_FLD = 0, + CFA_P70_ACT_LBT_DR_MAX_FLD +}; + +/** + * L2 Context Lookup Remap Table Fields: + */ +enum cfa_p70_prof_l2_ctxt_rmp_dr_flds { + CFA_P70_PROF_L2_CTXT_RMP_DR_PRSV_PARIF_FLD = 0, + CFA_P70_PROF_L2_CTXT_RMP_DR_PARIF_FLD = 1, + CFA_P70_PROF_L2_CTXT_RMP_DR_PRSV_L2IP_CTXT_FLD = 2, + CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_CTXT_FLD = 3, + CFA_P70_PROF_L2_CTXT_RMP_DR_PRSV_PROF_FUNC_FLD = 4, + CFA_P70_PROF_L2_CTXT_RMP_DR_PROF_FUNC_FLD = 5, + CFA_P70_PROF_L2_CTXT_RMP_DR_CTXT_OPCODE_FLD = 6, + CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_META_ENB_FLD = 7, + CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_META_FLD = 8, + CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_ACT_ENB_FLD = 9, + CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_ACT_DATA_FLD = 10, + CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_RFS_ENB_FLD = 11, + CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_RFS_DATA_FLD = 12, + CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_DEST_ENB_FLD = 13, + CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_DEST_DATA_FLD = 14, + CFA_P70_PROF_L2_CTXT_RMP_DR_MAX_FLD +}; + +/** + * Multi Field Register. + */ +enum cfa_p70_act_fc_tcam_result_flds { + CFA_P70_ACT_FC_TCAM_RESULT_SEARCH_RESULT_FLD = 0, + CFA_P70_ACT_FC_TCAM_RESULT_UNUSED_0_FLD = 1, + CFA_P70_ACT_FC_TCAM_RESULT_SEARCH_HIT_FLD = 2, + CFA_P70_ACT_FC_TCAM_RESULT_MAX_FLD +}; + +/** + * Multi Field Register. + */ +enum cfa_p70_act_mirror_flds { + CFA_P70_ACT_MIRROR_UNUSED_0_FLD = 0, + CFA_P70_ACT_MIRROR_RELATIVE_FLD = 1, + CFA_P70_ACT_MIRROR_HINT_FLD = 2, + CFA_P70_ACT_MIRROR_SAMP_FLD = 3, + CFA_P70_ACT_MIRROR_TRUNC_FLD = 4, + CFA_P70_ACT_MIRROR_IGN_DROP_FLD = 5, + CFA_P70_ACT_MIRROR_MODE_FLD = 6, + CFA_P70_ACT_MIRROR_COND_FLD = 7, + CFA_P70_ACT_MIRROR_AR_PTR_FLD = 8, + CFA_P70_ACT_MIRROR_SAMP_CFG_FLD = 9, + CFA_P70_ACT_MIRROR_MAX_FLD +}; + +/** + * WC LREC Lookup Record + */ +enum cfa_p70_wc_lrec_flds { + CFA_P70_WC_LREC_METADATA_FLD = 0, + CFA_P70_WC_LREC_META_PROF_FLD = 1, + CFA_P70_WC_LREC_PROF_FUNC_FLD = 2, + CFA_P70_WC_LREC_RECYCLE_DEST_FLD = 3, + CFA_P70_WC_LREC_FC_PTR_FLD = 4, + CFA_P70_WC_LREC_FC_TYPE_FLD = 5, + CFA_P70_WC_LREC_FC_OP_FLD = 6, + CFA_P70_WC_LREC_PATHS_M1_FLD = 7, + CFA_P70_WC_LREC_ACT_REC_SIZE_FLD = 8, + CFA_P70_WC_LREC_RING_TABLE_IDX_FLD = 9, + CFA_P70_WC_LREC_DESTINATION_FLD = 10, + CFA_P70_WC_LREC_ACT_REC_PTR_FLD = 11, + CFA_P70_WC_LREC_ACT_HINT_FLD = 12, + CFA_P70_WC_LREC_STRENGTH_FLD = 13, + CFA_P70_WC_LREC_OPCODE_FLD = 14, + CFA_P70_WC_LREC_EPOCH1_FLD = 15, + CFA_P70_WC_LREC_EPOCH0_FLD = 16, + CFA_P70_WC_LREC_REC_SIZE_FLD = 17, + CFA_P70_WC_LREC_VALID_FLD = 18, + CFA_P70_WC_LREC_MAX_FLD +}; + +/** + * EM LREC Lookup Record + */ +enum cfa_p70_em_lrec_flds { + CFA_P70_EM_LREC_RANGE_IDX_FLD = 0, + CFA_P70_EM_LREC_RANGE_PROFILE_FLD = 1, + CFA_P70_EM_LREC_CREC_TIMER_VALUE_FLD = 2, + CFA_P70_EM_LREC_CREC_STATE_FLD = 3, + CFA_P70_EM_LREC_CREC_TCP_MSB_OPP_INIT_FLD = 4, + CFA_P70_EM_LREC_CREC_TCP_MSB_OPP_FLD = 5, + CFA_P70_EM_LREC_CREC_TCP_MSB_LOC_FLD = 6, + CFA_P70_EM_LREC_CREC_TCP_WIN_FLD = 7, + CFA_P70_EM_LREC_CREC_TCP_UPDT_EN_FLD = 8, + CFA_P70_EM_LREC_CREC_TCP_DIR_FLD = 9, + CFA_P70_EM_LREC_METADATA_FLD = 10, + CFA_P70_EM_LREC_PROF_FUNC_FLD = 11, + CFA_P70_EM_LREC_META_PROF_FLD = 12, + CFA_P70_EM_LREC_RECYCLE_DEST_FLD = 13, + CFA_P70_EM_LREC_FC_PTR_FLD = 14, + CFA_P70_EM_LREC_FC_TYPE_FLD = 15, + CFA_P70_EM_LREC_FC_OP_FLD = 16, + CFA_P70_EM_LREC_PATHS_M1_FLD = 17, + CFA_P70_EM_LREC_ACT_REC_SIZE_FLD = 18, + CFA_P70_EM_LREC_RING_TABLE_IDX_FLD = 19, + CFA_P70_EM_LREC_DESTINATION_FLD = 20, + CFA_P70_EM_LREC_ACT_REC_PTR_FLD = 21, + CFA_P70_EM_LREC_ACT_HINT_FLD = 22, + CFA_P70_EM_LREC_STRENGTH_FLD = 23, + CFA_P70_EM_LREC_OPCODE_FLD = 24, + CFA_P70_EM_LREC_EPOCH1_FLD = 25, + CFA_P70_EM_LREC_EPOCH0_FLD = 26, + CFA_P70_EM_LREC_REC_SIZE_FLD = 27, + CFA_P70_EM_LREC_VALID_FLD = 28, + CFA_P70_EM_LREC_MAX_FLD +}; + +/** + * EM Lookup Bucket Format + */ +enum cfa_p70_em_bucket_flds { + CFA_P70_EM_BUCKET_BIN0_ENTRY_FLD = 0, + CFA_P70_EM_BUCKET_BIN0_HASH_MSBS_FLD = 1, + CFA_P70_EM_BUCKET_BIN1_ENTRY_FLD = 2, + CFA_P70_EM_BUCKET_BIN1_HASH_MSBS_FLD = 3, + CFA_P70_EM_BUCKET_BIN2_ENTRY_FLD = 4, + CFA_P70_EM_BUCKET_BIN2_HASH_MSBS_FLD = 5, + CFA_P70_EM_BUCKET_BIN3_ENTRY_FLD = 6, + CFA_P70_EM_BUCKET_BIN3_HASH_MSBS_FLD = 7, + CFA_P70_EM_BUCKET_BIN4_ENTRY_FLD = 8, + CFA_P70_EM_BUCKET_BIN4_HASH_MSBS_FLD = 9, + CFA_P70_EM_BUCKET_BIN5_ENTRY_FLD = 10, + CFA_P70_EM_BUCKET_BIN5_HASH_MSBS_FLD = 11, + CFA_P70_EM_BUCKET_CHAIN_POINTER_FLD = 12, + CFA_P70_EM_BUCKET_CHAIN_VALID_FLD = 13, + CFA_P70_EM_BUCKET_MAX_FLD +}; + +/** + * Compact Action Record. The compact action record uses relative + * pointers to access needed data. This keeps the compact action record + * down to 64b. + */ +enum cfa_p70_compact_action_flds { + CFA_P70_COMPACT_ACTION_TYPE_FLD = 0, + CFA_P70_COMPACT_ACTION_DROP_FLD = 1, + CFA_P70_COMPACT_ACTION_VLAN_DELETE_FLD = 2, + CFA_P70_COMPACT_ACTION_DEST_FLD = 3, + CFA_P70_COMPACT_ACTION_DEST_OP_FLD = 4, + CFA_P70_COMPACT_ACTION_DECAP_FLD = 5, + CFA_P70_COMPACT_ACTION_MIRRORING_FLD = 6, + CFA_P70_COMPACT_ACTION_METER_PTR_FLD = 7, + CFA_P70_COMPACT_ACTION_STAT0_OFF_FLD = 8, + CFA_P70_COMPACT_ACTION_STAT0_OP_FLD = 9, + CFA_P70_COMPACT_ACTION_STAT0_CTR_TYPE_FLD = 10, + CFA_P70_COMPACT_ACTION_MOD_OFF_FLD = 11, + CFA_P70_COMPACT_ACTION_ENC_OFF_FLD = 12, + CFA_P70_COMPACT_ACTION_SRC_OFF_FLD = 13, + CFA_P70_COMPACT_ACTION_UNUSED_0_FLD = 14, + CFA_P70_COMPACT_ACTION_MAX_FLD +}; + +/** + * Full Action Record. The full action record uses full pointers to + * access needed data. It also allows access to all the action features. + * The Full Action record is 192b. + */ +enum cfa_p70_full_action_flds { + CFA_P70_FULL_ACTION_TYPE_FLD = 0, + CFA_P70_FULL_ACTION_DROP_FLD = 1, + CFA_P70_FULL_ACTION_VLAN_DELETE_FLD = 2, + CFA_P70_FULL_ACTION_DEST_FLD = 3, + CFA_P70_FULL_ACTION_DEST_OP_FLD = 4, + CFA_P70_FULL_ACTION_DECAP_FLD = 5, + CFA_P70_FULL_ACTION_MIRRORING_FLD = 6, + CFA_P70_FULL_ACTION_METER_PTR_FLD = 7, + CFA_P70_FULL_ACTION_STAT0_PTR_FLD = 8, + CFA_P70_FULL_ACTION_STAT0_OP_FLD = 9, + CFA_P70_FULL_ACTION_STAT0_CTR_TYPE_FLD = 10, + CFA_P70_FULL_ACTION_STAT1_PTR_FLD = 11, + CFA_P70_FULL_ACTION_STAT1_OP_FLD = 12, + CFA_P70_FULL_ACTION_STAT1_CTR_TYPE_FLD = 13, + CFA_P70_FULL_ACTION_MOD_PTR_FLD = 14, + CFA_P70_FULL_ACTION_ENC_PTR_FLD = 15, + CFA_P70_FULL_ACTION_SRC_PTR_FLD = 16, + CFA_P70_FULL_ACTION_UNUSED_0_FLD = 17, + CFA_P70_FULL_ACTION_MAX_FLD +}; + +/** + * Multicast Group Action Record. This action is used to send the packet + * to multiple destinations. The MGC Action record is 256b. + */ +enum cfa_p70_mcg_action_flds { + CFA_P70_MCG_ACTION_TYPE_FLD = 0, + CFA_P70_MCG_ACTION_SRC_KO_EN_FLD = 1, + CFA_P70_MCG_ACTION_UNUSED_0_FLD = 2, + CFA_P70_MCG_ACTION_NEXT_PTR_FLD = 3, + CFA_P70_MCG_ACTION_PTR0_ACT_HINT_FLD = 4, + CFA_P70_MCG_ACTION_PTR0_ACT_REC_PTR_FLD = 5, + CFA_P70_MCG_ACTION_PTR1_ACT_HINT_FLD = 6, + CFA_P70_MCG_ACTION_PTR1_ACT_REC_PTR_FLD = 7, + CFA_P70_MCG_ACTION_PTR2_ACT_HINT_FLD = 8, + CFA_P70_MCG_ACTION_PTR2_ACT_REC_PTR_FLD = 9, + CFA_P70_MCG_ACTION_PTR3_ACT_HINT_FLD = 10, + CFA_P70_MCG_ACTION_PTR3_ACT_REC_PTR_FLD = 11, + CFA_P70_MCG_ACTION_PTR4_ACT_HINT_FLD = 12, + CFA_P70_MCG_ACTION_PTR4_ACT_REC_PTR_FLD = 13, + CFA_P70_MCG_ACTION_PTR5_ACT_HINT_FLD = 14, + CFA_P70_MCG_ACTION_PTR5_ACT_REC_PTR_FLD = 15, + CFA_P70_MCG_ACTION_PTR6_ACT_HINT_FLD = 16, + CFA_P70_MCG_ACTION_PTR6_ACT_REC_PTR_FLD = 17, + CFA_P70_MCG_ACTION_PTR7_ACT_HINT_FLD = 18, + CFA_P70_MCG_ACTION_PTR7_ACT_REC_PTR_FLD = 19, + CFA_P70_MCG_ACTION_MAX_FLD +}; + +/** + * Multicast Group Action Record. This action is used to send the packet + * to multiple destinations. The MGC Action record is 256b. + */ +enum cfa_p70_mcg_subseq_action_flds { + CFA_P70_MCG_SUBSEQ_ACTION_TYPE_FLD = 0, + CFA_P70_MCG_SUBSEQ_ACTION_UNUSED_0_FLD = 1, + CFA_P70_MCG_SUBSEQ_ACTION_NEXT_PTR_FLD = 2, + CFA_P70_MCG_SUBSEQ_ACTION_PTR0_ACT_HINT_FLD = 3, + CFA_P70_MCG_SUBSEQ_ACTION_PTR0_ACT_REC_PTR_FLD = 4, + CFA_P70_MCG_SUBSEQ_ACTION_PTR1_ACT_HINT_FLD = 5, + CFA_P70_MCG_SUBSEQ_ACTION_PTR1_ACT_REC_PTR_FLD = 6, + CFA_P70_MCG_SUBSEQ_ACTION_PTR2_ACT_HINT_FLD = 7, + CFA_P70_MCG_SUBSEQ_ACTION_PTR2_ACT_REC_PTR_FLD = 8, + CFA_P70_MCG_SUBSEQ_ACTION_PTR3_ACT_HINT_FLD = 9, + CFA_P70_MCG_SUBSEQ_ACTION_PTR3_ACT_REC_PTR_FLD = 10, + CFA_P70_MCG_SUBSEQ_ACTION_PTR4_ACT_HINT_FLD = 11, + CFA_P70_MCG_SUBSEQ_ACTION_PTR4_ACT_REC_PTR_FLD = 12, + CFA_P70_MCG_SUBSEQ_ACTION_PTR5_ACT_HINT_FLD = 13, + CFA_P70_MCG_SUBSEQ_ACTION_PTR5_ACT_REC_PTR_FLD = 14, + CFA_P70_MCG_SUBSEQ_ACTION_PTR6_ACT_HINT_FLD = 15, + CFA_P70_MCG_SUBSEQ_ACTION_PTR6_ACT_REC_PTR_FLD = 16, + CFA_P70_MCG_SUBSEQ_ACTION_PTR7_ACT_HINT_FLD = 17, + CFA_P70_MCG_SUBSEQ_ACTION_PTR7_ACT_REC_PTR_FLD = 18, + CFA_P70_MCG_SUBSEQ_ACTION_MAX_FLD +}; + +/** + * Action Meter Formats + */ +enum cfa_p70_meters_flds { + CFA_P70_METERS_BKT_C_FLD = 0, + CFA_P70_METERS_BKT_E_FLD = 1, + CFA_P70_METERS_FLAGS_MTR_VAL_FLD = 2, + CFA_P70_METERS_FLAGS_ECN_RMP_EN_FLD = 3, + CFA_P70_METERS_FLAGS_CF_FLD = 4, + CFA_P70_METERS_FLAGS_PM_FLD = 5, + CFA_P70_METERS_FLAGS_RFC2698_FLD = 6, + CFA_P70_METERS_FLAGS_CBSM_FLD = 7, + CFA_P70_METERS_FLAGS_EBSM_FLD = 8, + CFA_P70_METERS_FLAGS_CBND_FLD = 9, + CFA_P70_METERS_FLAGS_EBND_FLD = 10, + CFA_P70_METERS_CBS_FLD = 11, + CFA_P70_METERS_EBS_FLD = 12, + CFA_P70_METERS_CIR_FLD = 13, + CFA_P70_METERS_EIR_FLD = 14, + CFA_P70_METERS_PROTECTION_SCOPE_FLD = 15, + CFA_P70_METERS_PROTECTION_RSVD_FLD = 16, + CFA_P70_METERS_PROTECTION_ENABLE_FLD = 17, + CFA_P70_METERS_MAX_FLD +}; + +/** + * Enumeration for fkb + */ +enum cfa_p70_fkb_flds { + CFA_P70_FKB_PROF_ID_FLD = 0, + CFA_P70_FKB_L2CTXT_FLD = 1, + CFA_P70_FKB_L2FUNC_FLD = 2, + CFA_P70_FKB_PARIF_FLD = 3, + CFA_P70_FKB_SPIF_FLD = 4, + CFA_P70_FKB_SVIF_FLD = 5, + CFA_P70_FKB_LCOS_FLD = 6, + CFA_P70_FKB_META_HI_FLD = 7, + CFA_P70_FKB_META_LO_FLD = 8, + CFA_P70_FKB_RCYC_CNT_FLD = 9, + CFA_P70_FKB_LOOPBACK_FLD = 10, + CFA_P70_FKB_OTL2_TYPE_FLD = 11, + CFA_P70_FKB_OTL2_DMAC_FLD = 12, + CFA_P70_FKB_OTL2_SMAC_FLD = 13, + CFA_P70_FKB_OTL2_DT_FLD = 14, + CFA_P70_FKB_OTL2_SA_FLD = 15, + CFA_P70_FKB_OTL2_NVT_FLD = 16, + CFA_P70_FKB_OTL2_OVP_FLD = 17, + CFA_P70_FKB_OTL2_OVD_FLD = 18, + CFA_P70_FKB_OTL2_OVV_FLD = 19, + CFA_P70_FKB_OTL2_OVT_FLD = 20, + CFA_P70_FKB_OTL2_IVP_FLD = 21, + CFA_P70_FKB_OTL2_IVD_FLD = 22, + CFA_P70_FKB_OTL2_IVV_FLD = 23, + CFA_P70_FKB_OTL2_IVT_FLD = 24, + CFA_P70_FKB_OTL2_ETYPE_FLD = 25, + CFA_P70_FKB_OTL3_TYPE_FLD = 26, + CFA_P70_FKB_OTL3_SIP3_FLD = 27, + CFA_P70_FKB_OTL3_SIP2_FLD = 28, + CFA_P70_FKB_OTL3_SIP1_FLD = 29, + CFA_P70_FKB_OTL3_SIP0_FLD = 30, + CFA_P70_FKB_OTL3_DIP3_FLD = 31, + CFA_P70_FKB_OTL3_DIP2_FLD = 32, + CFA_P70_FKB_OTL3_DIP1_FLD = 33, + CFA_P70_FKB_OTL3_DIP0_FLD = 34, + CFA_P70_FKB_OTL3_TTL_FLD = 35, + CFA_P70_FKB_OTL3_PROT_FLD = 36, + CFA_P70_FKB_OTL3_FID_FLD = 37, + CFA_P70_FKB_OTL3_QOS_FLD = 38, + CFA_P70_FKB_OTL3_IEH_NONEXT_FLD = 39, + CFA_P70_FKB_OTL3_IEH_SEP_FLD = 40, + CFA_P70_FKB_OTL3_IEH_AUTH_FLD = 41, + CFA_P70_FKB_OTL3_IEH_DEST_FLD = 42, + CFA_P70_FKB_OTL3_IEH_FRAG_FLD = 43, + CFA_P70_FKB_OTL3_IEH_RTHDR_FLD = 44, + CFA_P70_FKB_OTL3_IEH_HOP_FLD = 45, + CFA_P70_FKB_OTL3_IEH_1FRAG_FLD = 46, + CFA_P70_FKB_OTL3_DF_FLD = 47, + CFA_P70_FKB_OTL3_L3ERR_FLD = 48, + CFA_P70_FKB_OTL4_TYPE_FLD = 49, + CFA_P70_FKB_OTL4_SRC_FLD = 50, + CFA_P70_FKB_OTL4_DST_FLD = 51, + CFA_P70_FKB_OTL4_FLAGS_FLD = 52, + CFA_P70_FKB_OTL4_SEQ_FLD = 53, + CFA_P70_FKB_OTL4_PA_FLD = 54, + CFA_P70_FKB_OTL4_OPT_FLD = 55, + CFA_P70_FKB_OTL4_TCPTS_FLD = 56, + CFA_P70_FKB_OTL4_ERR_FLD = 57, + CFA_P70_FKB_OT_TYPE_FLD = 58, + CFA_P70_FKB_OT_FLAGS_FLD = 59, + CFA_P70_FKB_OT_IDS_FLD = 60, + CFA_P70_FKB_OT_ID_FLD = 61, + CFA_P70_FKB_OT_CTXTS_FLD = 62, + CFA_P70_FKB_OT_CTXT_FLD = 63, + CFA_P70_FKB_OT_QOS_FLD = 64, + CFA_P70_FKB_OT_ERR_FLD = 65, + CFA_P70_FKB_TL2_TYPE_FLD = 66, + CFA_P70_FKB_TL2_DMAC_FLD = 67, + CFA_P70_FKB_TL2_SMAC_FLD = 68, + CFA_P70_FKB_TL2_DT_FLD = 69, + CFA_P70_FKB_TL2_SA_FLD = 70, + CFA_P70_FKB_TL2_NVT_FLD = 71, + CFA_P70_FKB_TL2_OVP_FLD = 72, + CFA_P70_FKB_TL2_OVD_FLD = 73, + CFA_P70_FKB_TL2_OVV_FLD = 74, + CFA_P70_FKB_TL2_OVT_FLD = 75, + CFA_P70_FKB_TL2_IVP_FLD = 76, + CFA_P70_FKB_TL2_IVD_FLD = 77, + CFA_P70_FKB_TL2_IVV_FLD = 78, + CFA_P70_FKB_TL2_IVT_FLD = 79, + CFA_P70_FKB_TL2_ETYPE_FLD = 80, + CFA_P70_FKB_TL3_TYPE_FLD = 81, + CFA_P70_FKB_TL3_SIP3_FLD = 82, + CFA_P70_FKB_TL3_SIP2_FLD = 83, + CFA_P70_FKB_TL3_SIP1_FLD = 84, + CFA_P70_FKB_TL3_SIP0_FLD = 85, + CFA_P70_FKB_TL3_DIP3_FLD = 86, + CFA_P70_FKB_TL3_DIP2_FLD = 87, + CFA_P70_FKB_TL3_DIP1_FLD = 88, + CFA_P70_FKB_TL3_DIP0_FLD = 89, + CFA_P70_FKB_TL3_TTL_FLD = 90, + CFA_P70_FKB_TL3_PROT_FLD = 91, + CFA_P70_FKB_TL3_FID_FLD = 92, + CFA_P70_FKB_TL3_QOS_FLD = 93, + CFA_P70_FKB_TL3_IEH_NONEXT_FLD = 94, + CFA_P70_FKB_TL3_IEH_SEP_FLD = 95, + CFA_P70_FKB_TL3_IEH_AUTH_FLD = 96, + CFA_P70_FKB_TL3_IEH_DEST_FLD = 97, + CFA_P70_FKB_TL3_IEH_FRAG_FLD = 98, + CFA_P70_FKB_TL3_IEH_RTHDR_FLD = 99, + CFA_P70_FKB_TL3_IEH_HOP_FLD = 100, + CFA_P70_FKB_TL3_IEH_1FRAG_FLD = 101, + CFA_P70_FKB_TL3_DF_FLD = 102, + CFA_P70_FKB_TL3_L3ERR_FLD = 103, + CFA_P70_FKB_TL4_TYPE_FLD = 104, + CFA_P70_FKB_TL4_SRC_FLD = 105, + CFA_P70_FKB_TL4_DST_FLD = 106, + CFA_P70_FKB_TL4_FLAGS_FLD = 107, + CFA_P70_FKB_TL4_SEQ_FLD = 108, + CFA_P70_FKB_TL4_PA_FLD = 109, + CFA_P70_FKB_TL4_OPT_FLD = 110, + CFA_P70_FKB_TL4_TCPTS_FLD = 111, + CFA_P70_FKB_TL4_ERR_FLD = 112, + CFA_P70_FKB_T_TYPE_FLD = 113, + CFA_P70_FKB_T_FLAGS_FLD = 114, + CFA_P70_FKB_T_IDS_FLD = 115, + CFA_P70_FKB_T_ID_FLD = 116, + CFA_P70_FKB_T_CTXTS_FLD = 117, + CFA_P70_FKB_T_CTXT_FLD = 118, + CFA_P70_FKB_T_QOS_FLD = 119, + CFA_P70_FKB_T_ERR_FLD = 120, + CFA_P70_FKB_L2_TYPE_FLD = 121, + CFA_P70_FKB_L2_DMAC_FLD = 122, + CFA_P70_FKB_L2_SMAC_FLD = 123, + CFA_P70_FKB_L2_DT_FLD = 124, + CFA_P70_FKB_L2_SA_FLD = 125, + CFA_P70_FKB_L2_NVT_FLD = 126, + CFA_P70_FKB_L2_OVP_FLD = 127, + CFA_P70_FKB_L2_OVD_FLD = 128, + CFA_P70_FKB_L2_OVV_FLD = 129, + CFA_P70_FKB_L2_OVT_FLD = 130, + CFA_P70_FKB_L2_IVP_FLD = 131, + CFA_P70_FKB_L2_IVD_FLD = 132, + CFA_P70_FKB_L2_IVV_FLD = 133, + CFA_P70_FKB_L2_IVT_FLD = 134, + CFA_P70_FKB_L2_ETYPE_FLD = 135, + CFA_P70_FKB_L3_TYPE_FLD = 136, + CFA_P70_FKB_L3_SIP3_FLD = 137, + CFA_P70_FKB_L3_SIP2_FLD = 138, + CFA_P70_FKB_L3_SIP1_FLD = 139, + CFA_P70_FKB_L3_SIP0_FLD = 140, + CFA_P70_FKB_L3_DIP3_FLD = 141, + CFA_P70_FKB_L3_DIP2_FLD = 142, + CFA_P70_FKB_L3_DIP1_FLD = 143, + CFA_P70_FKB_L3_DIP0_FLD = 144, + CFA_P70_FKB_L3_TTL_FLD = 145, + CFA_P70_FKB_L3_PROT_FLD = 146, + CFA_P70_FKB_L3_FID_FLD = 147, + CFA_P70_FKB_L3_QOS_FLD = 148, + CFA_P70_FKB_L3_IEH_NONEXT_FLD = 149, + CFA_P70_FKB_L3_IEH_SEP_FLD = 150, + CFA_P70_FKB_L3_IEH_AUTH_FLD = 151, + CFA_P70_FKB_L3_IEH_DEST_FLD = 152, + CFA_P70_FKB_L3_IEH_FRAG_FLD = 153, + CFA_P70_FKB_L3_IEH_RTHDR_FLD = 154, + CFA_P70_FKB_L3_IEH_HOP_FLD = 155, + CFA_P70_FKB_L3_IEH_1FRAG_FLD = 156, + CFA_P70_FKB_L3_DF_FLD = 157, + CFA_P70_FKB_L3_L3ERR_FLD = 158, + CFA_P70_FKB_L4_TYPE_FLD = 159, + CFA_P70_FKB_L4_SRC_FLD = 160, + CFA_P70_FKB_L4_DST_FLD = 161, + CFA_P70_FKB_L4_FLAGS_FLD = 162, + CFA_P70_FKB_L4_SEQ_FLD = 163, + CFA_P70_FKB_L4_ACK_FLD = 164, + CFA_P70_FKB_L4_WIN_FLD = 165, + CFA_P70_FKB_L4_PA_FLD = 166, + CFA_P70_FKB_L4_OPT_FLD = 167, + CFA_P70_FKB_L4_TCPTS_FLD = 168, + CFA_P70_FKB_L4_TSVAL_FLD = 169, + CFA_P70_FKB_L4_TXECR_FLD = 170, + CFA_P70_FKB_L4_ERR_FLD = 171, + CFA_P70_FKB_MAX_FLD = 172, +}; + +/** + * Enumeration for wc tcam fkb + */ +enum cfa_p70_wc_tcam_fkb_flds { + CFA_P70_WC_TCAM_FKB_PROF_ID_FLD = 0, + CFA_P70_WC_TCAM_FKB_L2CTXT_FLD = 1, + CFA_P70_WC_TCAM_FKB_L2FUNC_FLD = 2, + CFA_P70_WC_TCAM_FKB_PARIF_FLD = 3, + CFA_P70_WC_TCAM_FKB_SPIF_FLD = 4, + CFA_P70_WC_TCAM_FKB_SVIF_FLD = 5, + CFA_P70_WC_TCAM_FKB_LCOS_FLD = 6, + CFA_P70_WC_TCAM_FKB_META_HI_FLD = 7, + CFA_P70_WC_TCAM_FKB_META_LO_FLD = 8, + CFA_P70_WC_TCAM_FKB_RCYC_CNT_FLD = 9, + CFA_P70_WC_TCAM_FKB_LOOPBACK_FLD = 10, + CFA_P70_WC_TCAM_FKB_OTL2_TYPE_FLD = 11, + CFA_P70_WC_TCAM_FKB_OTL2_DMAC_FLD = 12, + CFA_P70_WC_TCAM_FKB_OTL2_SMAC_FLD = 13, + CFA_P70_WC_TCAM_FKB_OTL2_DT_FLD = 14, + CFA_P70_WC_TCAM_FKB_OTL2_SA_FLD = 15, + CFA_P70_WC_TCAM_FKB_OTL2_NVT_FLD = 16, + CFA_P70_WC_TCAM_FKB_OTL2_OVP_FLD = 17, + CFA_P70_WC_TCAM_FKB_OTL2_OVD_FLD = 18, + CFA_P70_WC_TCAM_FKB_OTL2_OVV_FLD = 19, + CFA_P70_WC_TCAM_FKB_OTL2_OVT_FLD = 20, + CFA_P70_WC_TCAM_FKB_OTL2_IVP_FLD = 21, + CFA_P70_WC_TCAM_FKB_OTL2_IVD_FLD = 22, + CFA_P70_WC_TCAM_FKB_OTL2_IVV_FLD = 23, + CFA_P70_WC_TCAM_FKB_OTL2_IVT_FLD = 24, + CFA_P70_WC_TCAM_FKB_OTL2_ETYPE_FLD = 25, + CFA_P70_WC_TCAM_FKB_OTL3_TYPE_FLD = 26, + CFA_P70_WC_TCAM_FKB_OTL3_SIP3_FLD = 27, + CFA_P70_WC_TCAM_FKB_OTL3_SIP2_FLD = 28, + CFA_P70_WC_TCAM_FKB_OTL3_SIP1_FLD = 29, + CFA_P70_WC_TCAM_FKB_OTL3_SIP0_FLD = 30, + CFA_P70_WC_TCAM_FKB_OTL3_DIP3_FLD = 31, + CFA_P70_WC_TCAM_FKB_OTL3_DIP2_FLD = 32, + CFA_P70_WC_TCAM_FKB_OTL3_DIP1_FLD = 33, + CFA_P70_WC_TCAM_FKB_OTL3_DIP0_FLD = 34, + CFA_P70_WC_TCAM_FKB_OTL3_TTL_FLD = 35, + CFA_P70_WC_TCAM_FKB_OTL3_PROT_FLD = 36, + CFA_P70_WC_TCAM_FKB_OTL3_FID_FLD = 37, + CFA_P70_WC_TCAM_FKB_OTL3_QOS_FLD = 38, + CFA_P70_WC_TCAM_FKB_OTL3_IEH_NONEXT_FLD = 39, + CFA_P70_WC_TCAM_FKB_OTL3_IEH_SEP_FLD = 40, + CFA_P70_WC_TCAM_FKB_OTL3_IEH_AUTH_FLD = 41, + CFA_P70_WC_TCAM_FKB_OTL3_IEH_DEST_FLD = 42, + CFA_P70_WC_TCAM_FKB_OTL3_IEH_FRAG_FLD = 43, + CFA_P70_WC_TCAM_FKB_OTL3_IEH_RTHDR_FLD = 44, + CFA_P70_WC_TCAM_FKB_OTL3_IEH_HOP_FLD = 45, + CFA_P70_WC_TCAM_FKB_OTL3_IEH_1FRAG_FLD = 46, + CFA_P70_WC_TCAM_FKB_OTL3_DF_FLD = 47, + CFA_P70_WC_TCAM_FKB_OTL3_L3ERR_FLD = 48, + CFA_P70_WC_TCAM_FKB_OTL4_TYPE_FLD = 49, + CFA_P70_WC_TCAM_FKB_OTL4_SRC_FLD = 50, + CFA_P70_WC_TCAM_FKB_OTL4_DST_FLD = 51, + CFA_P70_WC_TCAM_FKB_OTL4_FLAGS_FLD = 52, + CFA_P70_WC_TCAM_FKB_OTL4_SEQ_FLD = 53, + CFA_P70_WC_TCAM_FKB_OTL4_PA_FLD = 54, + CFA_P70_WC_TCAM_FKB_OTL4_OPT_FLD = 55, + CFA_P70_WC_TCAM_FKB_OTL4_TCPTS_FLD = 56, + CFA_P70_WC_TCAM_FKB_OTL4_ERR_FLD = 57, + CFA_P70_WC_TCAM_FKB_OT_TYPE_FLD = 58, + CFA_P70_WC_TCAM_FKB_OT_FLAGS_FLD = 59, + CFA_P70_WC_TCAM_FKB_OT_IDS_FLD = 60, + CFA_P70_WC_TCAM_FKB_OT_ID_FLD = 61, + CFA_P70_WC_TCAM_FKB_OT_CTXTS_FLD = 62, + CFA_P70_WC_TCAM_FKB_OT_CTXT_FLD = 63, + CFA_P70_WC_TCAM_FKB_OT_QOS_FLD = 64, + CFA_P70_WC_TCAM_FKB_OT_ERR_FLD = 65, + CFA_P70_WC_TCAM_FKB_TL2_TYPE_FLD = 66, + CFA_P70_WC_TCAM_FKB_TL2_DMAC_FLD = 67, + CFA_P70_WC_TCAM_FKB_TL2_SMAC_FLD = 68, + CFA_P70_WC_TCAM_FKB_TL2_DT_FLD = 69, + CFA_P70_WC_TCAM_FKB_TL2_SA_FLD = 70, + CFA_P70_WC_TCAM_FKB_TL2_NVT_FLD = 71, + CFA_P70_WC_TCAM_FKB_TL2_OVP_FLD = 72, + CFA_P70_WC_TCAM_FKB_TL2_OVD_FLD = 73, + CFA_P70_WC_TCAM_FKB_TL2_OVV_FLD = 74, + CFA_P70_WC_TCAM_FKB_TL2_OVT_FLD = 75, + CFA_P70_WC_TCAM_FKB_TL2_IVP_FLD = 76, + CFA_P70_WC_TCAM_FKB_TL2_IVD_FLD = 77, + CFA_P70_WC_TCAM_FKB_TL2_IVV_FLD = 78, + CFA_P70_WC_TCAM_FKB_TL2_IVT_FLD = 79, + CFA_P70_WC_TCAM_FKB_TL2_ETYPE_FLD = 80, + CFA_P70_WC_TCAM_FKB_TL3_TYPE_FLD = 81, + CFA_P70_WC_TCAM_FKB_TL3_SIP3_FLD = 82, + CFA_P70_WC_TCAM_FKB_TL3_SIP2_FLD = 83, + CFA_P70_WC_TCAM_FKB_TL3_SIP1_FLD = 84, + CFA_P70_WC_TCAM_FKB_TL3_SIP0_FLD = 85, + CFA_P70_WC_TCAM_FKB_TL3_DIP3_FLD = 86, + CFA_P70_WC_TCAM_FKB_TL3_DIP2_FLD = 87, + CFA_P70_WC_TCAM_FKB_TL3_DIP1_FLD = 88, + CFA_P70_WC_TCAM_FKB_TL3_DIP0_FLD = 89, + CFA_P70_WC_TCAM_FKB_TL3_TTL_FLD = 90, + CFA_P70_WC_TCAM_FKB_TL3_PROT_FLD = 91, + CFA_P70_WC_TCAM_FKB_TL3_FID_FLD = 92, + CFA_P70_WC_TCAM_FKB_TL3_QOS_FLD = 93, + CFA_P70_WC_TCAM_FKB_TL3_IEH_NONEXT_FLD = 94, + CFA_P70_WC_TCAM_FKB_TL3_IEH_SEP_FLD = 95, + CFA_P70_WC_TCAM_FKB_TL3_IEH_AUTH_FLD = 96, + CFA_P70_WC_TCAM_FKB_TL3_IEH_DEST_FLD = 97, + CFA_P70_WC_TCAM_FKB_TL3_IEH_FRAG_FLD = 98, + CFA_P70_WC_TCAM_FKB_TL3_IEH_RTHDR_FLD = 99, + CFA_P70_WC_TCAM_FKB_TL3_IEH_HOP_FLD = 100, + CFA_P70_WC_TCAM_FKB_TL3_IEH_1FRAG_FLD = 101, + CFA_P70_WC_TCAM_FKB_TL3_DF_FLD = 102, + CFA_P70_WC_TCAM_FKB_TL3_L3ERR_FLD = 103, + CFA_P70_WC_TCAM_FKB_TL4_TYPE_FLD = 104, + CFA_P70_WC_TCAM_FKB_TL4_SRC_FLD = 105, + CFA_P70_WC_TCAM_FKB_TL4_DST_FLD = 106, + CFA_P70_WC_TCAM_FKB_TL4_FLAGS_FLD = 107, + CFA_P70_WC_TCAM_FKB_TL4_SEQ_FLD = 108, + CFA_P70_WC_TCAM_FKB_TL4_PA_FLD = 109, + CFA_P70_WC_TCAM_FKB_TL4_OPT_FLD = 110, + CFA_P70_WC_TCAM_FKB_TL4_TCPTS_FLD = 111, + CFA_P70_WC_TCAM_FKB_TL4_ERR_FLD = 112, + CFA_P70_WC_TCAM_FKB_T_TYPE_FLD = 113, + CFA_P70_WC_TCAM_FKB_T_FLAGS_FLD = 114, + CFA_P70_WC_TCAM_FKB_T_IDS_FLD = 115, + CFA_P70_WC_TCAM_FKB_T_ID_FLD = 116, + CFA_P70_WC_TCAM_FKB_T_CTXTS_FLD = 117, + CFA_P70_WC_TCAM_FKB_T_CTXT_FLD = 118, + CFA_P70_WC_TCAM_FKB_T_QOS_FLD = 119, + CFA_P70_WC_TCAM_FKB_T_ERR_FLD = 120, + CFA_P70_WC_TCAM_FKB_L2_TYPE_FLD = 121, + CFA_P70_WC_TCAM_FKB_L2_DMAC_FLD = 122, + CFA_P70_WC_TCAM_FKB_L2_SMAC_FLD = 123, + CFA_P70_WC_TCAM_FKB_L2_DT_FLD = 124, + CFA_P70_WC_TCAM_FKB_L2_SA_FLD = 125, + CFA_P70_WC_TCAM_FKB_L2_NVT_FLD = 126, + CFA_P70_WC_TCAM_FKB_L2_OVP_FLD = 127, + CFA_P70_WC_TCAM_FKB_L2_OVD_FLD = 128, + CFA_P70_WC_TCAM_FKB_L2_OVV_FLD = 129, + CFA_P70_WC_TCAM_FKB_L2_OVT_FLD = 130, + CFA_P70_WC_TCAM_FKB_L2_IVP_FLD = 131, + CFA_P70_WC_TCAM_FKB_L2_IVD_FLD = 132, + CFA_P70_WC_TCAM_FKB_L2_IVV_FLD = 133, + CFA_P70_WC_TCAM_FKB_L2_IVT_FLD = 134, + CFA_P70_WC_TCAM_FKB_L2_ETYPE_FLD = 135, + CFA_P70_WC_TCAM_FKB_L3_TYPE_FLD = 136, + CFA_P70_WC_TCAM_FKB_L3_SIP3_FLD = 137, + CFA_P70_WC_TCAM_FKB_L3_SIP2_FLD = 138, + CFA_P70_WC_TCAM_FKB_L3_SIP1_FLD = 139, + CFA_P70_WC_TCAM_FKB_L3_SIP0_FLD = 140, + CFA_P70_WC_TCAM_FKB_L3_DIP3_FLD = 141, + CFA_P70_WC_TCAM_FKB_L3_DIP2_FLD = 142, + CFA_P70_WC_TCAM_FKB_L3_DIP1_FLD = 143, + CFA_P70_WC_TCAM_FKB_L3_DIP0_FLD = 144, + CFA_P70_WC_TCAM_FKB_L3_TTL_FLD = 145, + CFA_P70_WC_TCAM_FKB_L3_PROT_FLD = 146, + CFA_P70_WC_TCAM_FKB_L3_FID_FLD = 147, + CFA_P70_WC_TCAM_FKB_L3_QOS_FLD = 148, + CFA_P70_WC_TCAM_FKB_L3_IEH_NONEXT_FLD = 149, + CFA_P70_WC_TCAM_FKB_L3_IEH_SEP_FLD = 150, + CFA_P70_WC_TCAM_FKB_L3_IEH_AUTH_FLD = 151, + CFA_P70_WC_TCAM_FKB_L3_IEH_DEST_FLD = 152, + CFA_P70_WC_TCAM_FKB_L3_IEH_FRAG_FLD = 153, + CFA_P70_WC_TCAM_FKB_L3_IEH_RTHDR_FLD = 154, + CFA_P70_WC_TCAM_FKB_L3_IEH_HOP_FLD = 155, + CFA_P70_WC_TCAM_FKB_L3_IEH_1FRAG_FLD = 156, + CFA_P70_WC_TCAM_FKB_L3_DF_FLD = 157, + CFA_P70_WC_TCAM_FKB_L3_L3ERR_FLD = 158, + CFA_P70_WC_TCAM_FKB_L4_TYPE_FLD = 159, + CFA_P70_WC_TCAM_FKB_L4_SRC_FLD = 160, + CFA_P70_WC_TCAM_FKB_L4_DST_FLD = 161, + CFA_P70_WC_TCAM_FKB_L4_FLAGS_FLD = 162, + CFA_P70_WC_TCAM_FKB_L4_SEQ_FLD = 163, + CFA_P70_WC_TCAM_FKB_L4_ACK_FLD = 164, + CFA_P70_WC_TCAM_FKB_L4_WIN_FLD = 165, + CFA_P70_WC_TCAM_FKB_L4_PA_FLD = 166, + CFA_P70_WC_TCAM_FKB_L4_OPT_FLD = 167, + CFA_P70_WC_TCAM_FKB_L4_TCPTS_FLD = 168, + CFA_P70_WC_TCAM_FKB_L4_TSVAL_FLD = 169, + CFA_P70_WC_TCAM_FKB_L4_TXECR_FLD = 170, + CFA_P70_WC_TCAM_FKB_L4_ERR_FLD = 171, + CFA_P70_WC_TCAM_FKB_MAX_FLD = 172, +}; + +/** + * Enumeration for em fkb + */ +enum cfa_p70_em_fkb_flds { + CFA_P70_EM_FKB_PROF_ID_FLD = 0, + CFA_P70_EM_FKB_L2CTXT_FLD = 1, + CFA_P70_EM_FKB_L2FUNC_FLD = 2, + CFA_P70_EM_FKB_PARIF_FLD = 3, + CFA_P70_EM_FKB_SPIF_FLD = 4, + CFA_P70_EM_FKB_SVIF_FLD = 5, + CFA_P70_EM_FKB_LCOS_FLD = 6, + CFA_P70_EM_FKB_META_HI_FLD = 7, + CFA_P70_EM_FKB_META_LO_FLD = 8, + CFA_P70_EM_FKB_RCYC_CNT_FLD = 9, + CFA_P70_EM_FKB_LOOPBACK_FLD = 10, + CFA_P70_EM_FKB_OTL2_TYPE_FLD = 11, + CFA_P70_EM_FKB_OTL2_DMAC_FLD = 12, + CFA_P70_EM_FKB_OTL2_SMAC_FLD = 13, + CFA_P70_EM_FKB_OTL2_DT_FLD = 14, + CFA_P70_EM_FKB_OTL2_SA_FLD = 15, + CFA_P70_EM_FKB_OTL2_NVT_FLD = 16, + CFA_P70_EM_FKB_OTL2_OVP_FLD = 17, + CFA_P70_EM_FKB_OTL2_OVD_FLD = 18, + CFA_P70_EM_FKB_OTL2_OVV_FLD = 19, + CFA_P70_EM_FKB_OTL2_OVT_FLD = 20, + CFA_P70_EM_FKB_OTL2_IVP_FLD = 21, + CFA_P70_EM_FKB_OTL2_IVD_FLD = 22, + CFA_P70_EM_FKB_OTL2_IVV_FLD = 23, + CFA_P70_EM_FKB_OTL2_IVT_FLD = 24, + CFA_P70_EM_FKB_OTL2_ETYPE_FLD = 25, + CFA_P70_EM_FKB_OTL3_TYPE_FLD = 26, + CFA_P70_EM_FKB_OTL3_SIP3_FLD = 27, + CFA_P70_EM_FKB_OTL3_SIP2_FLD = 28, + CFA_P70_EM_FKB_OTL3_SIP1_FLD = 29, + CFA_P70_EM_FKB_OTL3_SIP0_FLD = 30, + CFA_P70_EM_FKB_OTL3_DIP3_FLD = 31, + CFA_P70_EM_FKB_OTL3_DIP2_FLD = 32, + CFA_P70_EM_FKB_OTL3_DIP1_FLD = 33, + CFA_P70_EM_FKB_OTL3_DIP0_FLD = 34, + CFA_P70_EM_FKB_OTL3_TTL_FLD = 35, + CFA_P70_EM_FKB_OTL3_PROT_FLD = 36, + CFA_P70_EM_FKB_OTL3_FID_FLD = 37, + CFA_P70_EM_FKB_OTL3_QOS_FLD = 38, + CFA_P70_EM_FKB_OTL3_IEH_NONEXT_FLD = 39, + CFA_P70_EM_FKB_OTL3_IEH_SEP_FLD = 40, + CFA_P70_EM_FKB_OTL3_IEH_AUTH_FLD = 41, + CFA_P70_EM_FKB_OTL3_IEH_DEST_FLD = 42, + CFA_P70_EM_FKB_OTL3_IEH_FRAG_FLD = 43, + CFA_P70_EM_FKB_OTL3_IEH_RTHDR_FLD = 44, + CFA_P70_EM_FKB_OTL3_IEH_HOP_FLD = 45, + CFA_P70_EM_FKB_OTL3_IEH_1FRAG_FLD = 46, + CFA_P70_EM_FKB_OTL3_DF_FLD = 47, + CFA_P70_EM_FKB_OTL3_L3ERR_FLD = 48, + CFA_P70_EM_FKB_OTL4_TYPE_FLD = 49, + CFA_P70_EM_FKB_OTL4_SRC_FLD = 50, + CFA_P70_EM_FKB_OTL4_DST_FLD = 51, + CFA_P70_EM_FKB_OTL4_FLAGS_FLD = 52, + CFA_P70_EM_FKB_OTL4_SEQ_FLD = 53, + CFA_P70_EM_FKB_OTL4_PA_FLD = 54, + CFA_P70_EM_FKB_OTL4_OPT_FLD = 55, + CFA_P70_EM_FKB_OTL4_TCPTS_FLD = 56, + CFA_P70_EM_FKB_OTL4_ERR_FLD = 57, + CFA_P70_EM_FKB_OT_TYPE_FLD = 58, + CFA_P70_EM_FKB_OT_FLAGS_FLD = 59, + CFA_P70_EM_FKB_OT_IDS_FLD = 60, + CFA_P70_EM_FKB_OT_ID_FLD = 61, + CFA_P70_EM_FKB_OT_CTXTS_FLD = 62, + CFA_P70_EM_FKB_OT_CTXT_FLD = 63, + CFA_P70_EM_FKB_OT_QOS_FLD = 64, + CFA_P70_EM_FKB_OT_ERR_FLD = 65, + CFA_P70_EM_FKB_TL2_TYPE_FLD = 66, + CFA_P70_EM_FKB_TL2_DMAC_FLD = 67, + CFA_P70_EM_FKB_TL2_SMAC_FLD = 68, + CFA_P70_EM_FKB_TL2_DT_FLD = 69, + CFA_P70_EM_FKB_TL2_SA_FLD = 70, + CFA_P70_EM_FKB_TL2_NVT_FLD = 71, + CFA_P70_EM_FKB_TL2_OVP_FLD = 72, + CFA_P70_EM_FKB_TL2_OVD_FLD = 73, + CFA_P70_EM_FKB_TL2_OVV_FLD = 74, + CFA_P70_EM_FKB_TL2_OVT_FLD = 75, + CFA_P70_EM_FKB_TL2_IVP_FLD = 76, + CFA_P70_EM_FKB_TL2_IVD_FLD = 77, + CFA_P70_EM_FKB_TL2_IVV_FLD = 78, + CFA_P70_EM_FKB_TL2_IVT_FLD = 79, + CFA_P70_EM_FKB_TL2_ETYPE_FLD = 80, + CFA_P70_EM_FKB_TL3_TYPE_FLD = 81, + CFA_P70_EM_FKB_TL3_SIP3_FLD = 82, + CFA_P70_EM_FKB_TL3_SIP2_FLD = 83, + CFA_P70_EM_FKB_TL3_SIP1_FLD = 84, + CFA_P70_EM_FKB_TL3_SIP0_FLD = 85, + CFA_P70_EM_FKB_TL3_DIP3_FLD = 86, + CFA_P70_EM_FKB_TL3_DIP2_FLD = 87, + CFA_P70_EM_FKB_TL3_DIP1_FLD = 88, + CFA_P70_EM_FKB_TL3_DIP0_FLD = 89, + CFA_P70_EM_FKB_TL3_TTL_FLD = 90, + CFA_P70_EM_FKB_TL3_PROT_FLD = 91, + CFA_P70_EM_FKB_TL3_FID_FLD = 92, + CFA_P70_EM_FKB_TL3_QOS_FLD = 93, + CFA_P70_EM_FKB_TL3_IEH_NONEXT_FLD = 94, + CFA_P70_EM_FKB_TL3_IEH_SEP_FLD = 95, + CFA_P70_EM_FKB_TL3_IEH_AUTH_FLD = 96, + CFA_P70_EM_FKB_TL3_IEH_DEST_FLD = 97, + CFA_P70_EM_FKB_TL3_IEH_FRAG_FLD = 98, + CFA_P70_EM_FKB_TL3_IEH_RTHDR_FLD = 99, + CFA_P70_EM_FKB_TL3_IEH_HOP_FLD = 100, + CFA_P70_EM_FKB_TL3_IEH_1FRAG_FLD = 101, + CFA_P70_EM_FKB_TL3_DF_FLD = 102, + CFA_P70_EM_FKB_TL3_L3ERR_FLD = 103, + CFA_P70_EM_FKB_TL4_TYPE_FLD = 104, + CFA_P70_EM_FKB_TL4_SRC_FLD = 105, + CFA_P70_EM_FKB_TL4_DST_FLD = 106, + CFA_P70_EM_FKB_TL4_FLAGS_FLD = 107, + CFA_P70_EM_FKB_TL4_SEQ_FLD = 108, + CFA_P70_EM_FKB_TL4_PA_FLD = 109, + CFA_P70_EM_FKB_TL4_OPT_FLD = 110, + CFA_P70_EM_FKB_TL4_TCPTS_FLD = 111, + CFA_P70_EM_FKB_TL4_ERR_FLD = 112, + CFA_P70_EM_FKB_T_TYPE_FLD = 113, + CFA_P70_EM_FKB_T_FLAGS_FLD = 114, + CFA_P70_EM_FKB_T_IDS_FLD = 115, + CFA_P70_EM_FKB_T_ID_FLD = 116, + CFA_P70_EM_FKB_T_CTXTS_FLD = 117, + CFA_P70_EM_FKB_T_CTXT_FLD = 118, + CFA_P70_EM_FKB_T_QOS_FLD = 119, + CFA_P70_EM_FKB_T_ERR_FLD = 120, + CFA_P70_EM_FKB_L2_TYPE_FLD = 121, + CFA_P70_EM_FKB_L2_DMAC_FLD = 122, + CFA_P70_EM_FKB_L2_SMAC_FLD = 123, + CFA_P70_EM_FKB_L2_DT_FLD = 124, + CFA_P70_EM_FKB_L2_SA_FLD = 125, + CFA_P70_EM_FKB_L2_NVT_FLD = 126, + CFA_P70_EM_FKB_L2_OVP_FLD = 127, + CFA_P70_EM_FKB_L2_OVD_FLD = 128, + CFA_P70_EM_FKB_L2_OVV_FLD = 129, + CFA_P70_EM_FKB_L2_OVT_FLD = 130, + CFA_P70_EM_FKB_L2_IVP_FLD = 131, + CFA_P70_EM_FKB_L2_IVD_FLD = 132, + CFA_P70_EM_FKB_L2_IVV_FLD = 133, + CFA_P70_EM_FKB_L2_IVT_FLD = 134, + CFA_P70_EM_FKB_L2_ETYPE_FLD = 135, + CFA_P70_EM_FKB_L3_TYPE_FLD = 136, + CFA_P70_EM_FKB_L3_SIP3_FLD = 137, + CFA_P70_EM_FKB_L3_SIP2_FLD = 138, + CFA_P70_EM_FKB_L3_SIP1_FLD = 139, + CFA_P70_EM_FKB_L3_SIP0_FLD = 140, + CFA_P70_EM_FKB_L3_DIP3_FLD = 141, + CFA_P70_EM_FKB_L3_DIP2_FLD = 142, + CFA_P70_EM_FKB_L3_DIP1_FLD = 143, + CFA_P70_EM_FKB_L3_DIP0_FLD = 144, + CFA_P70_EM_FKB_L3_TTL_FLD = 145, + CFA_P70_EM_FKB_L3_PROT_FLD = 146, + CFA_P70_EM_FKB_L3_FID_FLD = 147, + CFA_P70_EM_FKB_L3_QOS_FLD = 148, + CFA_P70_EM_FKB_L3_IEH_NONEXT_FLD = 149, + CFA_P70_EM_FKB_L3_IEH_SEP_FLD = 150, + CFA_P70_EM_FKB_L3_IEH_AUTH_FLD = 151, + CFA_P70_EM_FKB_L3_IEH_DEST_FLD = 152, + CFA_P70_EM_FKB_L3_IEH_FRAG_FLD = 153, + CFA_P70_EM_FKB_L3_IEH_RTHDR_FLD = 154, + CFA_P70_EM_FKB_L3_IEH_HOP_FLD = 155, + CFA_P70_EM_FKB_L3_IEH_1FRAG_FLD = 156, + CFA_P70_EM_FKB_L3_DF_FLD = 157, + CFA_P70_EM_FKB_L3_L3ERR_FLD = 158, + CFA_P70_EM_FKB_L4_TYPE_FLD = 159, + CFA_P70_EM_FKB_L4_SRC_FLD = 160, + CFA_P70_EM_FKB_L4_DST_FLD = 161, + CFA_P70_EM_FKB_L4_FLAGS_FLD = 162, + CFA_P70_EM_FKB_L4_SEQ_FLD = 163, + CFA_P70_EM_FKB_L4_ACK_FLD = 164, + CFA_P70_EM_FKB_L4_WIN_FLD = 165, + CFA_P70_EM_FKB_L4_PA_FLD = 166, + CFA_P70_EM_FKB_L4_OPT_FLD = 167, + CFA_P70_EM_FKB_L4_TCPTS_FLD = 168, + CFA_P70_EM_FKB_L4_TSVAL_FLD = 169, + CFA_P70_EM_FKB_L4_TXECR_FLD = 170, + CFA_P70_EM_FKB_L4_ERR_FLD = 171, + CFA_P70_EM_FKB_MAX_FLD = 172, +}; + +/** + * Enumeration for em key layout + */ +enum cfa_p70_em_key_layout_flds { + CFA_P70_EM_KL_RANGE_IDX_FLD = 0, + CFA_P70_EM_KL_RANGE_PROFILE_FLD = 1, + CFA_P70_EM_KL_CREC_TIMER_VALUE_FLD = 2, + CFA_P70_EM_KL_CREC_STATE_FLD = 3, + CFA_P70_EM_KL_CREC_TCP_MSB_OPP_INIT_FLD = 4, + CFA_P70_EM_KL_CREC_TCP_MSB_OPP_FLD = 5, + CFA_P70_EM_KL_CREC_TCP_MSB_LOC_FLD = 6, + CFA_P70_EM_KL_CREC_TCP_WIN_FLD = 7, + CFA_P70_EM_KL_CREC_TCP_UPDT_EN_FLD = 8, + CFA_P70_EM_KL_CREC_TCP_DIR_FLD = 9, + CFA_P70_EM_KL_METADATA_FLD = 10, + CFA_P70_EM_KL_PROF_FUNC_FLD = 11, + CFA_P70_EM_KL_META_PROF_FLD = 12, + CFA_P70_EM_KL_RECYCLE_DEST_FLD = 13, + CFA_P70_EM_KL_FC_PTR_FLD = 14, + CFA_P70_EM_KL_FC_TYPE_FLD = 15, + CFA_P70_EM_KL_FC_OP_FLD = 16, + CFA_P70_EM_KL_PATHS_M1_FLD = 17, + CFA_P70_EM_KL_ACT_REC_SIZE_FLD = 18, + CFA_P70_EM_KL_RING_TABLE_IDX_FLD = 19, + CFA_P70_EM_KL_DESTINATION_FLD = 20, + CFA_P70_EM_KL_ACT_REC_PTR_FLD = 21, + CFA_P70_EM_KL_ACT_HINT_FLD = 22, + CFA_P70_EM_KL_STRENGTH_FLD = 23, + CFA_P70_EM_KL_OPCODE_FLD = 24, + CFA_P70_EM_KL_EPOCH1_FLD = 25, + CFA_P70_EM_KL_EPOCH0_FLD = 26, + CFA_P70_EM_KL_REC_SIZE_FLD = 27, + CFA_P70_EM_KL_VALID_FLD = 28, + CFA_P70_EM_KL_PROF_ID_FLD = 29, + CFA_P70_EM_KL_L2CTXT_FLD = 30, + CFA_P70_EM_KL_L2FUNC_FLD = 31, + CFA_P70_EM_KL_PARIF_FLD = 32, + CFA_P70_EM_KL_SPIF_FLD = 33, + CFA_P70_EM_KL_SVIF_FLD = 34, + CFA_P70_EM_KL_LCOS_FLD = 35, + CFA_P70_EM_KL_META_HI_FLD = 36, + CFA_P70_EM_KL_META_LO_FLD = 37, + CFA_P70_EM_KL_RCYC_CNT_FLD = 38, + CFA_P70_EM_KL_LOOPBACK_FLD = 39, + CFA_P70_EM_KL_OTL2_TYPE_FLD = 40, + CFA_P70_EM_KL_OTL2_DMAC_FLD = 41, + CFA_P70_EM_KL_OTL2_SMAC_FLD = 42, + CFA_P70_EM_KL_OTL2_DT_FLD = 43, + CFA_P70_EM_KL_OTL2_SA_FLD = 44, + CFA_P70_EM_KL_OTL2_NVT_FLD = 45, + CFA_P70_EM_KL_OTL2_OVP_FLD = 46, + CFA_P70_EM_KL_OTL2_OVD_FLD = 47, + CFA_P70_EM_KL_OTL2_OVV_FLD = 48, + CFA_P70_EM_KL_OTL2_OVT_FLD = 49, + CFA_P70_EM_KL_OTL2_IVP_FLD = 50, + CFA_P70_EM_KL_OTL2_IVD_FLD = 51, + CFA_P70_EM_KL_OTL2_IVV_FLD = 52, + CFA_P70_EM_KL_OTL2_IVT_FLD = 53, + CFA_P70_EM_KL_OTL2_ETYPE_FLD = 54, + CFA_P70_EM_KL_OTL3_TYPE_FLD = 55, + CFA_P70_EM_KL_OTL3_SIP3_FLD = 56, + CFA_P70_EM_KL_OTL3_SIP2_FLD = 57, + CFA_P70_EM_KL_OTL3_SIP1_FLD = 58, + CFA_P70_EM_KL_OTL3_SIP0_FLD = 59, + CFA_P70_EM_KL_OTL3_DIP3_FLD = 60, + CFA_P70_EM_KL_OTL3_DIP2_FLD = 61, + CFA_P70_EM_KL_OTL3_DIP1_FLD = 62, + CFA_P70_EM_KL_OTL3_DIP0_FLD = 63, + CFA_P70_EM_KL_OTL3_TTL_FLD = 64, + CFA_P70_EM_KL_OTL3_PROT_FLD = 65, + CFA_P70_EM_KL_OTL3_FID_FLD = 66, + CFA_P70_EM_KL_OTL3_QOS_FLD = 67, + CFA_P70_EM_KL_OTL3_IEH_NONEXT_FLD = 68, + CFA_P70_EM_KL_OTL3_IEH_SEP_FLD = 69, + CFA_P70_EM_KL_OTL3_IEH_AUTH_FLD = 70, + CFA_P70_EM_KL_OTL3_IEH_DEST_FLD = 71, + CFA_P70_EM_KL_OTL3_IEH_FRAG_FLD = 72, + CFA_P70_EM_KL_OTL3_IEH_RTHDR_FLD = 73, + CFA_P70_EM_KL_OTL3_IEH_HOP_FLD = 74, + CFA_P70_EM_KL_OTL3_IEH_1FRAG_FLD = 75, + CFA_P70_EM_KL_OTL3_DF_FLD = 76, + CFA_P70_EM_KL_OTL3_L3ERR_FLD = 77, + CFA_P70_EM_KL_OTL4_TYPE_FLD = 78, + CFA_P70_EM_KL_OTL4_SRC_FLD = 79, + CFA_P70_EM_KL_OTL4_DST_FLD = 80, + CFA_P70_EM_KL_OTL4_FLAGS_FLD = 81, + CFA_P70_EM_KL_OTL4_SEQ_FLD = 82, + CFA_P70_EM_KL_OTL4_PA_FLD = 83, + CFA_P70_EM_KL_OTL4_OPT_FLD = 84, + CFA_P70_EM_KL_OTL4_TCPTS_FLD = 85, + CFA_P70_EM_KL_OTL4_ERR_FLD = 86, + CFA_P70_EM_KL_OT_TYPE_FLD = 87, + CFA_P70_EM_KL_OT_FLAGS_FLD = 88, + CFA_P70_EM_KL_OT_IDS_FLD = 89, + CFA_P70_EM_KL_OT_ID_FLD = 90, + CFA_P70_EM_KL_OT_CTXTS_FLD = 91, + CFA_P70_EM_KL_OT_CTXT_FLD = 92, + CFA_P70_EM_KL_OT_QOS_FLD = 93, + CFA_P70_EM_KL_OT_ERR_FLD = 94, + CFA_P70_EM_KL_TL2_TYPE_FLD = 95, + CFA_P70_EM_KL_TL2_DMAC_FLD = 96, + CFA_P70_EM_KL_TL2_SMAC_FLD = 97, + CFA_P70_EM_KL_TL2_DT_FLD = 98, + CFA_P70_EM_KL_TL2_SA_FLD = 99, + CFA_P70_EM_KL_TL2_NVT_FLD = 100, + CFA_P70_EM_KL_TL2_OVP_FLD = 101, + CFA_P70_EM_KL_TL2_OVD_FLD = 102, + CFA_P70_EM_KL_TL2_OVV_FLD = 103, + CFA_P70_EM_KL_TL2_OVT_FLD = 104, + CFA_P70_EM_KL_TL2_IVP_FLD = 105, + CFA_P70_EM_KL_TL2_IVD_FLD = 106, + CFA_P70_EM_KL_TL2_IVV_FLD = 107, + CFA_P70_EM_KL_TL2_IVT_FLD = 108, + CFA_P70_EM_KL_TL2_ETYPE_FLD = 109, + CFA_P70_EM_KL_TL3_TYPE_FLD = 110, + CFA_P70_EM_KL_TL3_SIP3_FLD = 111, + CFA_P70_EM_KL_TL3_SIP2_FLD = 112, + CFA_P70_EM_KL_TL3_SIP1_FLD = 113, + CFA_P70_EM_KL_TL3_SIP0_FLD = 114, + CFA_P70_EM_KL_TL3_DIP3_FLD = 115, + CFA_P70_EM_KL_TL3_DIP2_FLD = 116, + CFA_P70_EM_KL_TL3_DIP1_FLD = 117, + CFA_P70_EM_KL_TL3_DIP0_FLD = 118, + CFA_P70_EM_KL_TL3_TTL_FLD = 119, + CFA_P70_EM_KL_TL3_PROT_FLD = 120, + CFA_P70_EM_KL_TL3_FID_FLD = 121, + CFA_P70_EM_KL_TL3_QOS_FLD = 122, + CFA_P70_EM_KL_TL3_IEH_NONEXT_FLD = 123, + CFA_P70_EM_KL_TL3_IEH_SEP_FLD = 124, + CFA_P70_EM_KL_TL3_IEH_AUTH_FLD = 125, + CFA_P70_EM_KL_TL3_IEH_DEST_FLD = 126, + CFA_P70_EM_KL_TL3_IEH_FRAG_FLD = 127, + CFA_P70_EM_KL_TL3_IEH_RTHDR_FLD = 128, + CFA_P70_EM_KL_TL3_IEH_HOP_FLD = 129, + CFA_P70_EM_KL_TL3_IEH_1FRAG_FLD = 130, + CFA_P70_EM_KL_TL3_DF_FLD = 131, + CFA_P70_EM_KL_TL3_L3ERR_FLD = 132, + CFA_P70_EM_KL_TL4_TYPE_FLD = 133, + CFA_P70_EM_KL_TL4_SRC_FLD = 134, + CFA_P70_EM_KL_TL4_DST_FLD = 135, + CFA_P70_EM_KL_TL4_FLAGS_FLD = 136, + CFA_P70_EM_KL_TL4_SEQ_FLD = 137, + CFA_P70_EM_KL_TL4_PA_FLD = 138, + CFA_P70_EM_KL_TL4_OPT_FLD = 139, + CFA_P70_EM_KL_TL4_TCPTS_FLD = 140, + CFA_P70_EM_KL_TL4_ERR_FLD = 141, + CFA_P70_EM_KL_T_TYPE_FLD = 142, + CFA_P70_EM_KL_T_FLAGS_FLD = 143, + CFA_P70_EM_KL_T_IDS_FLD = 144, + CFA_P70_EM_KL_T_ID_FLD = 145, + CFA_P70_EM_KL_T_CTXTS_FLD = 146, + CFA_P70_EM_KL_T_CTXT_FLD = 147, + CFA_P70_EM_KL_T_QOS_FLD = 148, + CFA_P70_EM_KL_T_ERR_FLD = 149, + CFA_P70_EM_KL_L2_TYPE_FLD = 150, + CFA_P70_EM_KL_L2_DMAC_FLD = 151, + CFA_P70_EM_KL_L2_SMAC_FLD = 152, + CFA_P70_EM_KL_L2_DT_FLD = 153, + CFA_P70_EM_KL_L2_SA_FLD = 154, + CFA_P70_EM_KL_L2_NVT_FLD = 155, + CFA_P70_EM_KL_L2_OVP_FLD = 156, + CFA_P70_EM_KL_L2_OVD_FLD = 157, + CFA_P70_EM_KL_L2_OVV_FLD = 158, + CFA_P70_EM_KL_L2_OVT_FLD = 159, + CFA_P70_EM_KL_L2_IVP_FLD = 160, + CFA_P70_EM_KL_L2_IVD_FLD = 161, + CFA_P70_EM_KL_L2_IVV_FLD = 162, + CFA_P70_EM_KL_L2_IVT_FLD = 163, + CFA_P70_EM_KL_L2_ETYPE_FLD = 164, + CFA_P70_EM_KL_L3_TYPE_FLD = 165, + CFA_P70_EM_KL_L3_SIP3_FLD = 166, + CFA_P70_EM_KL_L3_SIP2_FLD = 167, + CFA_P70_EM_KL_L3_SIP1_FLD = 168, + CFA_P70_EM_KL_L3_SIP0_FLD = 169, + CFA_P70_EM_KL_L3_DIP3_FLD = 170, + CFA_P70_EM_KL_L3_DIP2_FLD = 171, + CFA_P70_EM_KL_L3_DIP1_FLD = 172, + CFA_P70_EM_KL_L3_DIP0_FLD = 173, + CFA_P70_EM_KL_L3_TTL_FLD = 174, + CFA_P70_EM_KL_L3_PROT_FLD = 175, + CFA_P70_EM_KL_L3_FID_FLD = 176, + CFA_P70_EM_KL_L3_QOS_FLD = 177, + CFA_P70_EM_KL_L3_IEH_NONEXT_FLD = 178, + CFA_P70_EM_KL_L3_IEH_SEP_FLD = 179, + CFA_P70_EM_KL_L3_IEH_AUTH_FLD = 180, + CFA_P70_EM_KL_L3_IEH_DEST_FLD = 181, + CFA_P70_EM_KL_L3_IEH_FRAG_FLD = 182, + CFA_P70_EM_KL_L3_IEH_RTHDR_FLD = 183, + CFA_P70_EM_KL_L3_IEH_HOP_FLD = 184, + CFA_P70_EM_KL_L3_IEH_1FRAG_FLD = 185, + CFA_P70_EM_KL_L3_DF_FLD = 186, + CFA_P70_EM_KL_L3_L3ERR_FLD = 187, + CFA_P70_EM_KL_L4_TYPE_FLD = 188, + CFA_P70_EM_KL_L4_SRC_FLD = 189, + CFA_P70_EM_KL_L4_DST_FLD = 190, + CFA_P70_EM_KL_L4_FLAGS_FLD = 191, + CFA_P70_EM_KL_L4_SEQ_FLD = 192, + CFA_P70_EM_KL_L4_ACK_FLD = 193, + CFA_P70_EM_KL_L4_WIN_FLD = 194, + CFA_P70_EM_KL_L4_PA_FLD = 195, + CFA_P70_EM_KL_L4_OPT_FLD = 196, + CFA_P70_EM_KL_L4_TCPTS_FLD = 197, + CFA_P70_EM_KL_L4_TSVAL_FLD = 198, + CFA_P70_EM_KL_L4_TXECR_FLD = 199, + CFA_P70_EM_KL_L4_ERR_FLD = 200, + CFA_P70_EM_KEY_LAYOUT_MAX_FLD = 201, + CFA_P70_EM_KL_MAX_FLD = CFA_P70_EM_KEY_LAYOUT_MAX_FLD, +}; + +/** + * Enumeration for action + */ +enum cfa_p70_action_flds { + CFA_P70_ACT_TYPE_FLD = 0, + CFA_P70_ACT_DROP_FLD = 1, + CFA_P70_ACT_VLAN_DELETE_FLD = 2, + CFA_P70_ACT_DEST_FLD = 3, + CFA_P70_ACT_DEST_OP_FLD = 4, + CFA_P70_ACT_DECAP_FLD = 5, + CFA_P70_ACT_MIRRORING_FLD = 6, + CFA_P70_ACT_METER_PTR_FLD = 7, + CFA_P70_ACT_STAT0_OFF_FLD = 8, + CFA_P70_ACT_STAT0_OP_FLD = 9, + CFA_P70_ACT_STAT0_CTR_TYPE_FLD = 10, + CFA_P70_ACT_MOD_OFF_FLD = 11, + CFA_P70_ACT_ENC_OFF_FLD = 12, + CFA_P70_ACT_SRC_OFF_FLD = 13, + CFA_P70_ACT_COMPACT_RSVD_0_FLD = 14, + CFA_P70_ACT_STAT0_PTR_FLD = 15, + CFA_P70_ACT_STAT1_PTR_FLD = 16, + CFA_P70_ACT_STAT1_OP_FLD = 17, + CFA_P70_ACT_STAT1_CTR_TYPE_FLD = 18, + CFA_P70_ACT_MOD_PTR_FLD = 19, + CFA_P70_ACT_ENC_PTR_FLD = 20, + CFA_P70_ACT_SRC_PTR_FLD = 21, + CFA_P70_ACT_FULL_RSVD_0_FLD = 22, + CFA_P70_ACT_SRC_KO_EN_FLD = 23, + CFA_P70_ACT_MCG_RSVD_0_FLD = 24, + CFA_P70_ACT_NEXT_PTR_FLD = 25, + CFA_P70_ACT_PTR0_ACT_HINT_FLD = 26, + CFA_P70_ACT_PTR0_ACT_REC_PTR_FLD = 27, + CFA_P70_ACT_PTR1_ACT_HINT_FLD = 28, + CFA_P70_ACT_PTR1_ACT_REC_PTR_FLD = 29, + CFA_P70_ACT_PTR2_ACT_HINT_FLD = 30, + CFA_P70_ACT_PTR2_ACT_REC_PTR_FLD = 31, + CFA_P70_ACT_PTR3_ACT_HINT_FLD = 32, + CFA_P70_ACT_PTR3_ACT_REC_PTR_FLD = 33, + CFA_P70_ACT_PTR4_ACT_HINT_FLD = 34, + CFA_P70_ACT_PTR4_ACT_REC_PTR_FLD = 35, + CFA_P70_ACT_PTR5_ACT_HINT_FLD = 36, + CFA_P70_ACT_PTR5_ACT_REC_PTR_FLD = 37, + CFA_P70_ACT_PTR6_ACT_HINT_FLD = 38, + CFA_P70_ACT_PTR6_ACT_REC_PTR_FLD = 39, + CFA_P70_ACT_PTR7_ACT_HINT_FLD = 40, + CFA_P70_ACT_PTR7_ACT_REC_PTR_FLD = 41, + CFA_P70_ACT_MCG_SUBSEQ_RSVD_0_FLD = 42, + CFA_P70_ACT_MOD_MODIFY_ACT_HDR_FLD = 43, + CFA_P70_ACT_MOD_MD_UPDT_DATA_FLD = 44, + CFA_P70_ACT_MOD_MD_UPDT_PROF_FLD = 45, + CFA_P70_ACT_MOD_MD_UPDT_OP_FLD = 46, + CFA_P70_ACT_MOD_MD_UPDT_RSVD_0_FLD = 47, + CFA_P70_ACT_MOD_MD_UPDT_TOP_FLD = 48, + CFA_P70_ACT_MOD_RM_OVLAN_FLD = 49, + CFA_P70_ACT_MOD_RM_IVLAN_FLD = 50, + CFA_P70_ACT_MOD_RPL_IVLAN_FLD = 51, + CFA_P70_ACT_MOD_RPL_OVLAN_FLD = 52, + CFA_P70_ACT_MOD_TTL_UPDT_OP_FLD = 53, + CFA_P70_ACT_MOD_TTL_UPDT_ALT_VID_FLD = 54, + CFA_P70_ACT_MOD_TTL_UPDT_ALT_PFID_FLD = 55, + CFA_P70_ACT_MOD_TTL_UPDT_TOP_FLD = 56, + CFA_P70_ACT_MOD_TNL_MODIFY_DEL_FLD = 57, + CFA_P70_ACT_MOD_TNL_MODIFY_8B_NEW_PROT_FLD = 58, + CFA_P70_ACT_MOD_TNL_MODIFY_8B_EXIST_PROT_FLD = 59, + CFA_P70_ACT_MOD_TNL_MODIFY_8B_VEC_FLD = 60, + CFA_P70_ACT_MOD_TNL_MODIFY_8B_TOP_FLD = 61, + CFA_P70_ACT_MOD_TNL_MODIFY_16B_NEW_PROT_FLD = 62, + CFA_P70_ACT_MOD_TNL_MODIFY_16B_EXIST_PROT_FLD = 63, + CFA_P70_ACT_MOD_TNL_MODIFY_16B_VEC_FLD = 64, + CFA_P70_ACT_MOD_TNL_MODIFY_16B_TOP_FLD = 65, + CFA_P70_ACT_MOD_UPDT_FIELD_DATA0_FLD = 66, + CFA_P70_ACT_MOD_UPDT_FIELD_VEC_RSVD_FLD = 67, + CFA_P70_ACT_MOD_UPDT_FIELD_VEC_KID_FLD = 68, + CFA_P70_ACT_MOD_UPDT_FIELD_TOP_FLD = 69, + CFA_P70_ACT_MOD_SMAC_FLD = 70, + CFA_P70_ACT_MOD_DMAC_FLD = 71, + CFA_P70_ACT_MOD_SIPV6_FLD = 72, + CFA_P70_ACT_MOD_DIPV6_FLD = 73, + CFA_P70_ACT_MOD_SIPV4_FLD = 74, + CFA_P70_ACT_MOD_DIPV4_FLD = 75, + CFA_P70_ACT_MOD_SPORT_FLD = 76, + CFA_P70_ACT_MOD_DPORT_FLD = 77, + CFA_P70_ACT_ENC_ECV_TNL_FLD = 78, + CFA_P70_ACT_ENC_ECV_L4_FLD = 79, + CFA_P70_ACT_ENC_ECV_L3_FLD = 80, + CFA_P70_ACT_ENC_ECV_L2_FLD = 81, + CFA_P70_ACT_ENC_ECV_VTAG_FLD = 82, + CFA_P70_ACT_ENC_ECV_EC_FLD = 83, + CFA_P70_ACT_ENC_ECV_VALID_FLD = 84, + CFA_P70_ACT_ENC_EC_IP_TTL_IH_FLD = 85, + CFA_P70_ACT_ENC_EC_IP_TOS_IH_FLD = 86, + CFA_P70_ACT_ENC_EC_TUN_QOS_FLD = 87, + CFA_P70_ACT_ENC_EC_GRE_SET_K_FLD = 88, + CFA_P70_ACT_ENC_EC_DMAC_OVR_FLD = 89, + CFA_P70_ACT_ENC_EC_VLAN_OVR_FLD = 90, + CFA_P70_ACT_ENC_EC_SMAC_OVR_FLD = 91, + CFA_P70_ACT_ENC_EC_IPV4_ID_CTRL_FLD = 92, + CFA_P70_ACT_ENC_L2_DMAC_FLD = 93, + CFA_P70_ACT_ENC_VLAN1_TAG_VID_FLD = 94, + CFA_P70_ACT_ENC_VLAN1_TAG_DE_FLD = 95, + CFA_P70_ACT_ENC_VLAN1_TAG_PRI_FLD = 96, + CFA_P70_ACT_ENC_VLAN1_TAG_TPID_FLD = 97, + CFA_P70_ACT_ENC_VLAN2_IT_VID_FLD = 98, + CFA_P70_ACT_ENC_VLAN2_IT_DE_FLD = 99, + CFA_P70_ACT_ENC_VLAN2_IT_PRI_FLD = 100, + CFA_P70_ACT_ENC_VLAN2_IT_TPID_FLD = 101, + CFA_P70_ACT_ENC_VLAN2_OT_VID_FLD = 102, + CFA_P70_ACT_ENC_VLAN2_OT_DE_FLD = 103, + CFA_P70_ACT_ENC_VLAN2_OT_PRI_FLD = 104, + CFA_P70_ACT_ENC_VLAN2_OT_TPID_FLD = 105, + CFA_P70_ACT_ENC_IPV4_ID_FLD = 106, + CFA_P70_ACT_ENC_IPV4_TOS_FLD = 107, + CFA_P70_ACT_ENC_IPV4_HLEN_FLD = 108, + CFA_P70_ACT_ENC_IPV4_VER_FLD = 109, + CFA_P70_ACT_ENC_IPV4_PROT_FLD = 110, + CFA_P70_ACT_ENC_IPV4_TTL_FLD = 111, + CFA_P70_ACT_ENC_IPV4_FRAG_FLD = 112, + CFA_P70_ACT_ENC_IPV4_FLAGS_FLD = 113, + CFA_P70_ACT_ENC_IPV4_DEST_FLD = 114, + CFA_P70_ACT_ENC_IPV6_FLOW_LABEL_FLD = 115, + CFA_P70_ACT_ENC_IPV6_TRAFFIC_CLASS_FLD = 116, + CFA_P70_ACT_ENC_IPV6_VER_FLD = 117, + CFA_P70_ACT_ENC_IPV6_HOP_LIMIT_FLD = 118, + CFA_P70_ACT_ENC_IPV6_NEXT_HEADER_FLD = 119, + CFA_P70_ACT_ENC_IPV6_PAYLOAD_LENGTH_FLD = 120, + CFA_P70_ACT_ENC_IPV6_DEST_FLD = 121, + CFA_P70_ACT_ENC_MPLS_TAG1_FLD = 122, + CFA_P70_ACT_ENC_MPLS_TAG2_FLD = 123, + CFA_P70_ACT_ENC_MPLS_TAG3_FLD = 124, + CFA_P70_ACT_ENC_MPLS_TAG4_FLD = 125, + CFA_P70_ACT_ENC_MPLS_TAG5_FLD = 126, + CFA_P70_ACT_ENC_MPLS_TAG6_FLD = 127, + CFA_P70_ACT_ENC_MPLS_TAG7_FLD = 128, + CFA_P70_ACT_ENC_MPLS_TAG8_FLD = 129, + CFA_P70_ACT_ENC_L4_DEST_PORT_FLD = 130, + CFA_P70_ACT_ENC_L4_SRC_PORT_FLD = 131, + CFA_P70_ACT_ENC_TNL_VXLAN_NEXT_PROT_FLD = 132, + CFA_P70_ACT_ENC_TNL_VXLAN_RSVD_0_FLD = 133, + CFA_P70_ACT_ENC_TNL_VXLAN_FLAGS_FLD = 134, + CFA_P70_ACT_ENC_TNL_VXLAN_RSVD_1_FLD = 135, + CFA_P70_ACT_ENC_TNL_VXLAN_VNI_FLD = 136, + CFA_P70_ACT_ENC_TNL_NGE_PROT_TYPE_FLD = 137, + CFA_P70_ACT_ENC_TNL_NGE_RSVD_0_FLD = 138, + CFA_P70_ACT_ENC_TNL_NGE_FLAGS_C_FLD = 139, + CFA_P70_ACT_ENC_TNL_NGE_FLAGS_O_FLD = 140, + CFA_P70_ACT_ENC_TNL_NGE_FLAGS_OPT_LEN_FLD = 141, + CFA_P70_ACT_ENC_TNL_NGE_FLAGS_VER_FLD = 142, + CFA_P70_ACT_ENC_TNL_NGE_RSVD_1_FLD = 143, + CFA_P70_ACT_ENC_TNL_NGE_VNI_FLD = 144, + CFA_P70_ACT_ENC_TNL_NGE_OPTIONS_FLD = 145, + CFA_P70_ACT_ENC_TNL_NVGRE_FLOW_ID_FLD = 146, + CFA_P70_ACT_ENC_TNL_NVGRE_VSID_FLD = 147, + CFA_P70_ACT_ENC_TNL_GRE_KEY_FLD = 148, + CFA_P70_ACT_ENC_TNL_GENERIC_TID_FLD = 149, + CFA_P70_ACT_ENC_TNL_GENERIC_LENGTH_FLD = 150, + CFA_P70_ACT_ENC_TNL_GENERIC_HEADER_FLD = 151, + CFA_P70_ACT_SRC_MAC_FLD = 152, + CFA_P70_ACT_SRC_IPV4_ADDR_FLD = 153, + CFA_P70_ACT_SRC_IPV6_ADDR_FLD = 154, + CFA_P70_ACT_STAT0_B16_FPC_FLD = 155, + CFA_P70_ACT_STAT1_B16_FPC_FLD = 156, + CFA_P70_ACT_STAT0_B16_FBC_FLD = 157, + CFA_P70_ACT_STAT1_B16_FBC_FLD = 158, + CFA_P70_ACT_STAT0_B24_FPC_FLD = 159, + CFA_P70_ACT_STAT1_B24_FPC_FLD = 160, + CFA_P70_ACT_STAT0_B24_FBC_FLD = 161, + CFA_P70_ACT_STAT1_B24_FBC_FLD = 162, + CFA_P70_ACT_STAT0_B24_TIMESTAMP_FLD = 163, + CFA_P70_ACT_STAT1_B24_TIMESTAMP_FLD = 164, + CFA_P70_ACT_STAT0_B24_TCP_FLAGS_FLD = 165, + CFA_P70_ACT_STAT1_B24_TCP_FLAGS_FLD = 166, + CFA_P70_ACT_STAT0_B24_UNUSED_0_FLD = 167, + CFA_P70_ACT_STAT1_B24_UNUSED_0_FLD = 168, + CFA_P70_ACT_STAT0_B32A_FPC_FLD = 169, + CFA_P70_ACT_STAT1_B32A_FPC_FLD = 170, + CFA_P70_ACT_STAT0_B32A_FBC_FLD = 171, + CFA_P70_ACT_STAT1_B32A_FBC_FLD = 172, + CFA_P70_ACT_STAT0_B32A_MPC_FLD = 173, + CFA_P70_ACT_STAT1_B32A_MPC_FLD = 174, + CFA_P70_ACT_STAT0_B32A_MBC_FLD = 175, + CFA_P70_ACT_STAT1_B32A_MBC_FLD = 176, + CFA_P70_ACT_STAT0_B32B_FPC_FLD = 177, + CFA_P70_ACT_STAT1_B32B_FPC_FLD = 178, + CFA_P70_ACT_STAT0_B32B_FBC_FLD = 179, + CFA_P70_ACT_STAT1_B32B_FBC_FLD = 180, + CFA_P70_ACT_STAT0_B32B_TIMESTAMP_FLD = 181, + CFA_P70_ACT_STAT1_B32B_TIMESTAMP_FLD = 182, + CFA_P70_ACT_STAT0_B32B_TCP_FLAGS_FLD = 183, + CFA_P70_ACT_STAT1_B32B_TCP_FLAGS_FLD = 184, + CFA_P70_ACT_STAT0_B32B_UNUSED_0_FLD = 185, + CFA_P70_ACT_STAT1_B32B_UNUSED_0_FLD = 186, + CFA_P70_ACT_STAT0_B32B_MPC15_0_FLD = 187, + CFA_P70_ACT_STAT1_B32B_MPC15_0_FLD = 188, + CFA_P70_ACT_STAT0_B32B_MPC37_16_FLD = 189, + CFA_P70_ACT_STAT1_B32B_MPC37_16_FLD = 190, + CFA_P70_ACT_STAT0_B32B_MBC_FLD = 191, + CFA_P70_ACT_STAT1_B32B_MBC_FLD = 192, + CFA_P70_ACTION_MAX_FLD = 193, + CFA_P70_ACT_MAX_FLD = CFA_P70_ACTION_MAX_FLD, +}; + +#define CFA_P70_EM_KEY_LAYOUT_2_BASE_FLD(FLD) \ + ((FLD) - CFA_P70_EM_LREC_MAX_FLD) + +/* clang-format on */ + +#endif /* _CFA_BLD_P70_FIELD_IDS_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_bld_p70_mpc.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_bld_p70_mpc.h new file mode 100644 index 0000000000..21d79ab5f5 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_bld_p70_mpc.h @@ -0,0 +1,548 @@ +/**************************************************************************** + * Copyright(c) 2021 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_bld_p70_mpc.h + * + * @brief CFA 7.0 Public api definitions to build CFA Mid-path commands and + * Parse CFA Mid-path Command completions + */ + +#ifndef _CFA_BLD_P70_MPC_H_ +#define _CFA_BLD_P70_MPC_H_ + +#include +#include + +/** + * CFA Mid-Path Command (MPC) opcodes. The MPC CFA operations + * are divided into 2 sub groups. Cache access operations + * and EM update operations. + */ +enum cfa_mpc_opcode { + /** + * MPC Cache access commands + */ + /* MPC Command to read Action/Lookup cache (up to 4 lines) */ + CFA_MPC_READ, + /* MPC Command to write to Action/Lookup cache (up to 4 lines) */ + CFA_MPC_WRITE, + /* MPC Cmd to Read and Clear Action/Lookup cache line (max 1 line) */ + CFA_MPC_READ_CLR, + /* MPC Cmd to Invalidate Action/Lkup cache lines (up to 4 lines) */ + CFA_MPC_INVALIDATE, + + /** + * MPC EM update commands + */ + /** + * MPC Command to search for an EM entry by its key in the + * EM bucket chain + */ + CFA_MPC_EM_SEARCH, + /* MPC command to insert a new EM entry to the EM bucket chain */ + CFA_MPC_EM_INSERT, + /* MPC Command to delete an EM entry from the EM bucket chain */ + CFA_MPC_EM_DELETE, + /* MPC Command to add an EM bucket to the tail of EM bucket chain */ + CFA_MPC_EM_CHAIN, + CFA_MPC_OPC_MAX, +}; + +/** + * CFA MPC Cache access reading mode + */ +enum cfa_mpc_read_mode { + CFA_MPC_RD_NORMAL, /**< Normal read mode */ + CFA_MPC_RD_EVICT, /**< Read the cache and evict the cache line */ + CFA_MPC_RD_DEBUG_LINE, /**< Debug read mode line */ + CFA_MPC_RD_DEBUG_TAG, /**< Debug read mode tag */ + CFA_MPC_RD_MODE_MAX +}; + +/** + * CFA MPC Cache access writing mode + */ +enum cfa_mpc_write_mode { + CFA_MPC_WR_WRITE_THRU, /**< Write to cache in Write through mode */ + CFA_MPC_WR_WRITE_BACK, /**< Write to cache in Write back mode */ + CFA_MPC_WR_MODE_MAX +}; + +/** + * CFA MPC Cache access eviction mode + */ +enum cfa_mpc_evict_mode { + /** + * Line evict: These modes evict a single cache line + * In these modes, the eviction occurs regardless of the cache line + * state (CLEAN/CLEAN_FAST_EVICT/DIRTY) + */ + /* Cache line addressed by set/way is evicted */ + CFA_MPC_EV_EVICT_LINE, + /* Cache line hit with the table scope/address tuple is evicted */ + CFA_MPC_EV_EVICT_SCOPE_ADDRESS, + + /** + * Set Evict: These modes evict cache lines that meet certain criteria + * from the entire cache set. + */ + /* + * Cache lines only in CLEAN state are evicted from the set + * derived from the address + */ + CFA_MPC_EV_EVICT_CLEAN_LINES, + /* + * Cache lines only in CLEAN_FAST_EVICT state are evicted from + * the set derived from the address + */ + CFA_MPC_EV_EVICT_CLEAN_FAST_EVICT_LINES, + /* + * Cache lines in both CLEAN and CLEAN_FAST_EVICT states are + * evicted from the set derived from the address + */ + CFA_MPC_EV_EVICT_CLEAN_AND_CLEAN_FAST_EVICT_LINES, + /* + * All Cache lines in the set identified by the address and + * belonging to the table scope are evicted. + */ + CFA_MPC_EV_EVICT_TABLE_SCOPE, + CFA_MPC_EV_MODE_MAX, +}; + +/** + * CFA Hardware Cache Table Type + */ +enum cfa_hw_table_type { + CFA_HW_TABLE_ACTION, /**< CFA Action Record Table */ + CFA_HW_TABLE_LOOKUP, /**< CFA EM Lookup Record Table */ + CFA_HW_TABLE_MAX +}; + +/** + * MPC Command parameters specific to Cache read operations + */ +struct cfa_mpc_cache_read_params { + /* Specifies the cache option for reading the cache lines */ + enum cfa_mpc_read_mode mode; + /** + * Clear mask to use for the Read-Clear operation + * Each bit in the mask correspond to 2 bytes in the + * cache line. Setting the corresponding mask bit, clears + * the corresponding data bytes in the cache line AFTER + * the read. This field is ignored for Read CMD. + */ + uint16_t clear_mask; + /** + * External host memory address + * + * The 64-bit IOVA host address to which to write the DMA data returned + * in the completion. The data will be written to the same function as + * the one that owns the queue this command is read from. Address must + * be 4 byte aligned. + */ + uint64_t host_address; +}; + +/** + * MPC Command parameters specific to Cache write operation + */ +struct cfa_mpc_cache_write_params { + /* Specifies the cache option for the write access */ + enum cfa_mpc_write_mode mode; + /* Pointer to data to be written to cache */ + const uint8_t *data_ptr; +}; + +/** + * MPC Command parameters specific to Cache evict/invalidate operation + */ +struct cfa_mpc_cache_evict_params { + /* Specifies the cache option for Invalidation operation */ + enum cfa_mpc_evict_mode mode; +}; + +/** + * MPC CFA Command parameters for cache related operations + */ +struct cfa_mpc_cache_axs_params { + /** Common parameters for cache operations */ + /* + * Opaque value that will be returned in the MPC CFA + * Completion message. This can be used by the caller to associate + * completions with commands. + */ + uint32_t opaque; + /* + * Table Scope to address the cache line. For Thor2 + * the table scope goes for 0 - 31. + */ + uint8_t tbl_scope; + /* + * Table Index to address the cache line. Note that + * this is the offset to the 32B record in the table + * scope backing store, expressed in 32B units. + */ + uint32_t tbl_index; + /* + * Number of cache lines (32B word) in the access + * This should be set to 1 for READ-CLEAR command and between 1 and + * 4 for all other cache access commands (READ/WRITE/INVALIDATE) + */ + uint8_t data_size; + /* CFA table type for which this Host IF hw operation is intended for */ + enum cfa_hw_table_type tbl_type; + + /* Cache operation specific params */ + union { + /** Read and Read clear specific parameters */ + struct cfa_mpc_cache_read_params read; + /** Cache write specific parameters */ + struct cfa_mpc_cache_write_params write; + /** Cache invalidate operation specific parameters */ + struct cfa_mpc_cache_evict_params evict; + }; +}; + +/** + * MPC CFA command parameters specific to EM insert operation + */ +struct cfa_mpc_em_insert_params { + /* + * Pointer to the Exact Match entry to search. The + * EM Key in the entry is used to for the search + */ + const uint8_t *em_entry; + /* Size of the EM entry in 32B words (1- 4) */ + uint8_t data_size; + /* Flag to indicate if a matching entry (if found) should be replaced */ + bool replace; + /* Table index to write the EM entry being inserted */ + uint32_t entry_idx; + /* + * Table index to the EM record that can be used to + * create a new EM bucket, if the insertion results + * in a EM bucket chain's tail update. + */ + uint32_t bucket_idx; +}; + +/** + * MPC CFA command parameters specific to EM search operation + */ +struct cfa_mpc_em_search_params { + /* + * Pointer to the Exact Match entry to search. The + * EM Key in the entry is used to for the search + */ + uint8_t *em_entry; + /* Size of the EM entry in 32B words (1- 4) */ + uint8_t data_size; +}; + +/** + * MPC CFA command parameters specific to EM delete operation + */ +struct cfa_mpc_em_delete_params { + /* Table index to the EM record to delete */ + uint32_t entry_idx; + /* + * Table index to the static bucket for the EM bucket chain. + * As part of EM Delete processing, the hw walks the EM bucket + * chain to determine if the entry_idx is part of the chain. + * If the entry_idx is found to be a part of the chain, it is + * deleted from the chain and the EM bucket is repacked. If the + * tail of the bucket has only one valid entry, then the delete + * operation results in a tail update and one free EM entry + */ + uint32_t bucket_idx; +}; + +/** + * MPC CFA command parameters specific to EM chain operation + */ +struct cfa_mpc_em_chain_params { + /* + * Table index that will form the chain + * pointer to the tail bucket in the EM bucket chain + */ + uint32_t entry_idx; + /* + * Table index to the static bucket for + * EM bucket chain to be updated. + */ + uint32_t bucket_idx; +}; + +/** + * MPC CFA Command parameters for EM operations + */ +struct cfa_mpc_em_op_params { + /** Common parameters for EM update operations */ + /* + * Opaque value that will be returned in the MPC CFA + * Completion message. This can be used by the caller to associate + * completions with commands. + */ + uint32_t opaque; + /* + * Table Scope to address the cache line. For Thor2 + * the table scope goes for 0 - 31. + */ + uint8_t tbl_scope; + /** EM update operation specific params */ + union { + /** EM Search operation params */ + struct cfa_mpc_em_search_params search; + /** EM Insert operation params */ + struct cfa_mpc_em_insert_params insert; + /** EM Delete operation params */ + struct cfa_mpc_em_delete_params del; + /** EM Chain operation params */ + struct cfa_mpc_em_chain_params chain; + }; +}; + +/** + * MPC CFA Command completion status + */ +enum cfa_mpc_cmpl_status { + /* Command success */ + CFA_MPC_OK = 0, + /* Unsupported CFA opcode */ + CFA_MPC_UNSPRT_ERR = 1, + /* CFA command format error */ + CFA_MPC_FMT_ERR = 2, + /* SVIF-Table Scope error */ + CFA_MPC_SCOPE_ERR = 3, + /* Address error: Only used if EM command or TABLE_TYPE=EM */ + CFA_MPC_ADDR_ERR = 4, + /* Cache operation error */ + CFA_MPC_CACHE_ERR = 5, + /* EM_SEARCH or EM_DELETE did not find a matching EM entry */ + CFA_MPC_EM_MISS = 6, + /* EM_INSERT found a matching EM entry and REPLACE=0 in the command */ + CFA_MPC_EM_DUPLICATE = 7, + /* EM_EVENT_COLLECTION_FAIL no events to return */ + CFA_MPC_EM_EVENT_COLLECTION_FAIL = 8, + /* + * EM_INSERT required a dynamic bucket to be added to the chain + * to successfully insert the EM entry, but the entry provided + * for use as dynamic bucket was invalid. (bucket_idx == 0) + */ + CFA_MPC_EM_ABORT = 9, +}; + +/** + * MPC Cache access command completion result + */ +struct cfa_mpc_cache_axs_result { + /* + * Opaque value returned in the completion message. This can + * be used by the caller to associate completions with commands. + */ + uint32_t opaque; + /* MPC Command completion status code */ + enum cfa_mpc_cmpl_status status; + /* + * Additional error information + * when status code is one of FMT, SCOPE, ADDR or CACHE error + */ + uint32_t error_data; + /* + * Pointer to buffer to copy read data to. + * Needs to be valid for READ, READ-CLEAR operations + * Not set for write and evict operations + */ + uint8_t *rd_data; + /* + * Size of the data buffer in Bytes. Should be at least + * be data_size * 32 for MPC cache reads + */ + uint16_t data_len; +}; + +/** + * MPC EM search operation result + */ +struct cfa_mpc_em_search_result { + uint32_t bucket_num; /**< See CFA EAS */ + uint32_t num_entries; /**< See CFA EAS */ + /* Set to HASH[35:24] of the hash computed from the EM entry key. */ + uint32_t hash_msb; + /* + * IF a match is found, this field is set + * to the table index of the matching EM entry + */ + uint32_t match_idx; + /* + * Table index to the static bucket determined by hashing the EM entry + * key + */ + uint32_t bucket_idx; +}; + +/** + * MPC EM insert operation result + */ +struct cfa_mpc_em_insert_result { + uint32_t bucket_num; /**< See CFA EAS */ + uint32_t num_entries; /**< See CFA EAS */ + /* Set to HASH[35:24] of the hash computed from the EM entry key. */ + uint32_t hash_msb; + /* + * If replace = 1 and a matchng entry is found, this field is + * updated with the table index of the replaced entry. This table + * index is therefore free for use. + */ + uint32_t match_idx; + /* + * Table index to the static bucket determined by hashing the EM entry + * key + */ + uint32_t bucket_idx; + /* Flag: Matching entry was found and replace */ + uint8_t replaced : 1; + /* Flag: EM bucket chain was updated */ + uint8_t chain_update : 1; +}; + +/** + * MPC EM delete operation result + */ +struct cfa_mpc_em_delete_result { + uint32_t bucket_num; /**< See CFA EAS */ + uint32_t num_entries; /**< See CFA EAS */ + /* + * Table index to EM bucket tail BEFORE the delete command + * was processed with a OK or EM_MISS status. If chain update = 1, then + * this bucket can be freed + */ + uint32_t prev_tail; + /* + * Table index to EM bucket tail AFTER the delete command + * was processed with a OK or EM_MISS status. Same as prev_tail + * if chain_update = 0. + */ + uint32_t new_tail; + /* Flag: EM bucket chain was updated */ + uint8_t chain_update : 1; +}; + +/** + * MPC EM chain operation result + */ +struct cfa_mpc_em_chain_result { + uint32_t bucket_num; /**< See CFA EAS */ + uint32_t num_entries; /**< See CFA EAS */ +}; + +/** + * MPC EM operation completion result + */ +struct cfa_mpc_em_op_result { + /* + * Opaque value returned in the completion message. This can + * be used by the caller to associate completions with commands. + */ + uint32_t opaque; + /* MPC Command completion status code */ + enum cfa_mpc_cmpl_status status; + /* + * Additional error information + * when status code is one of FMT, SCOPE, ADDR or CACHE error + */ + uint32_t error_data; + union { + /** EM Search specific results */ + struct cfa_mpc_em_search_result search; + /** EM Insert specific results */ + struct cfa_mpc_em_insert_result insert; + /** EM Delete specific results */ + struct cfa_mpc_em_delete_result del; + /** EM Chain specific results */ + struct cfa_mpc_em_chain_result chain; + }; +}; + +/** + * Build MPC CFA Cache access command + * + * @param [in] opc MPC opcode + * + * @param [out] cmd_buff Command data buffer to write the command to + * + * @param [in/out] cmd_buff_len Pointer to command buffer size param + * Set by caller to indicate the input cmd_buff size. + * Set to the actual size of the command generated by the api. + * + * @param [in] parms Pointer to MPC cache access command parameters + * + * @return 0 on Success, negative errno on failure + */ +int cfa_mpc_build_cache_axs_cmd(enum cfa_mpc_opcode opc, uint8_t *cmd_buff, + uint32_t *cmd_buff_len, + struct cfa_mpc_cache_axs_params *parms); + +/** + * Parse MPC CFA Cache access command completion result + * + * @param [in] opc MPC cache access opcode + * + * @param [in] resp_buff Data buffer containing the response to parse + * + * @param [in] resp_buff_len Response buffer size + * + * @param [out] result Pointer to MPC cache access result object. This + * object will contain the fields parsed and extracted from the + * response buffer. + * + * @return 0 on Success, negative errno on failure + */ +int cfa_mpc_parse_cache_axs_resp(enum cfa_mpc_opcode opc, uint8_t *resp_buff, + uint32_t resp_buff_len, + struct cfa_mpc_cache_axs_result *result); + +/** + * Build MPC CFA EM operation command + * + * @param [in] opc MPC EM opcode + * + * @param [in] cmd_buff Command data buffer to write the command to + * + * @param [in/out] cmd_buff_len Pointer to command buffer size param + * Set by caller to indicate the input cmd_buff size. + * Set to the actual size of the command generated by the api. + * + * @param [in] parms Pointer to MPC cache access command parameters + * + * @return 0 on Success, negative errno on failure + */ +int cfa_mpc_build_em_op_cmd(enum cfa_mpc_opcode opc, uint8_t *cmd_buff, + uint32_t *cmd_buff_len, + struct cfa_mpc_em_op_params *parms); + +/** + * Parse MPC CFA EM operation command completion result + * + * @param [in] opc MPC cache access opcode + * + * @param [in] resp_buff Data buffer containing the response to parse + * + * @param [in] resp_buff_len Response buffer size + * + * @param [out] result Pointer to MPC EM operation result object. This + * object will contain the fields parsed and extracted from the + * response buffer. + * + * @return 0 on Success, negative errno on failure + */ +int cfa_mpc_parse_em_op_resp(enum cfa_mpc_opcode opc, uint8_t *resp_buff, + uint32_t resp_buff_len, + struct cfa_mpc_em_op_result *result); + +#endif /* _CFA_BLD_P70_MPC_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_p70.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_p70.h new file mode 100644 index 0000000000..5119813cc5 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_p70.h @@ -0,0 +1,164 @@ +/**************************************************************************** + * Copyright(c) 2021 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file + * + * @brief + */ + +#ifndef _CFA_P70_H_ +#define _CFA_P70_H_ + +#include "sys_util.h" +#include "cfa_p70_hw.h" + +#define BITS_TO_BYTES(n) (((n) + 7) / 8) +#define BYTES_TO_WORDS(n) (((n) + 3) / 4) + +/* EM Lrec size */ +#define CFA_P70_EM_LREC_SZ CFA_P70_EM_LREC_TOTAL_NUM_BITS +/* Encap header length */ +#define CFA_P70_ACT_ENCAP_MIN_HDR_LEN 64 +/* Max AR pointers per MCG record */ +#define CFA_P70_ACT_MCG_MAX_AR_PTR 8 +/* Max Key fields */ +#define CFA_P70_KEY_FLD_ID_MAX CFA_P70_EM_KEY_LAYOUT_MAX_FLD + +/* profiler ILT, l2ctxt remap, and profile remap are 32-bit accessed */ +#define CFA_PROF_P7P0_ILT_NUM_WORDS \ + NUM_WORDS_ALIGN_32BIT(CFA_P70_PROF_ILT_DR_TOTAL_NUM_BITS) +#define CFA_PROF_P7P0_L2_CTXT_RMP_NUM_WORDS \ + NUM_WORDS_ALIGN_32BIT(CFA_P70_PROF_L2_CTXT_RMP_DR_TOTAL_NUM_BITS) +#define CFA_PROF_P7P0_PROFILE_RMP_NUM_WORDS \ + NUM_WORDS_ALIGN_32BIT(CFA_P70_PROF_PROFILE_RMP_DR_TOTAL_NUM_BITS) +/* profiler TCAM and L2 ctxt TCAM are accessed via Wide-bus */ +#define CFA_PROF_P7P0_PROFILE_TCAM_NUM_WORDS \ + NUM_WORDS_ALIGN_128BIT(CFA_P70_PROF_PROFILE_TCAM_TOTAL_NUM_BITS) +#define CFA_PROF_P7P0_L2_CTXT_TCAM_NUM_WORDS \ + NUM_WORDS_ALIGN_128BIT(CFA_P70_PROF_L2_CTXT_TCAM_TOTAL_NUM_BITS) +/* FKB are accessed via Wide-bus */ +#define CFA_P70_EM_FKB_NUM_WORDS NUM_WORDS_ALIGN_128BIT(CFA_P70_EM_FKB_MAX_FLD) +#define CFA_P70_EM_FKB_NUM_ENTRIES 128 + +/* EM FKB Mask */ +/* EM_FKB_MASK total num bits defined in CFA EAS section 3.3.9.2.2 EM Key */ +#define CFA_P70_EM_FKB_MASK_TOTAL_NUM_BITS 896 +#define CFA_P70_EM_FKB_MASK_NUM_WORDS \ + NUM_WORDS_ALIGN_128BIT(CFA_P70_EM_FKB_MASK_TOTAL_NUM_BITS) +#define CFA_P70_EM_FKB_MASK_NUM_ENTRIES 128 + +#define CFA_P70_WC_TCAM_FKB_NUM_WORDS \ + NUM_WORDS_ALIGN_128BIT(CFA_P70_WC_TCAM_FKB_MAX_FLD) +#define CFA_P70_WC_TCAM_FKB_NUM_ENTRIES 128 +/* VNIC-SVIF Properties Table are accessed via Wide-bus */ +#define CFA_ACT_P7P0_VSPT_NUM_WORDS \ + NUM_WORDS_ALIGN_32BIT(CFA_P70_ACT_VSPT_DR_TX_TOTAL_NUM_BITS) +#define CFA_P70_ACT_VEB_TCAM_NUM_WORDS \ + NUM_WORDS_ALIGN_128BIT(CFA_P70_ACT_VEB_TCAM_RX_TOTAL_NUM_BITS) +#define CFA_P70_ACT_MIRROR_NUM_WORDS \ + NUM_WORDS_ALIGN_128BIT(CFA_P70_ACT_MIRROR_TOTAL_NUM_BITS) +#define CFA_P7P0_ACT_VEB_RMP_NUM_WORDS \ + NUM_WORDS_ALIGN_32BIT(CFA_P70_ACT_VEB_RMP_TOTAL_NUM_BITS) +#define CFA_P7P0_ACT_LBT_NUM_WORDS \ + NUM_WORDS_ALIGN_32BIT(CFA_P70_ACT_LBT_DR_TOTAL_NUM_BITS) +#define CFA_P70_LKUP_EM_ENTRY_SIZE_IN_BITS 256 +#define CFA_P70_LKUP_EM_MAX_ENTRIES 4 +#define CFA_P70_LKUP_EM_MAX_ENTRY_SIZE_IN_BITS \ + (CFA_P70_LKUP_EM_ENTRY_SIZE_IN_BITS * CFA_P70_LKUP_EM_MAX_ENTRIES) +/* Maximum EM key size in bits */ +#define CFA_P70_LKUP_EM_DATA_SIZE_IN_BITS \ + (CFA_P70_LKUP_EM_MAX_ENTRY_SIZE_IN_BITS - CFA_P70_EM_LREC_SZ) +#define CFA_P70_LKUP_WC_DATA_SIZE_IN_BITS 688 +#define CFA_P70_LKUP_WC_DATA_SIZE_WITH_CTRL_INFO_IN_BITS 700 +#define CFA_P70_LKUP_WC_DATA_SIZE \ + (BITS_TO_BYTES(CFA_P70_LKUP_WC_DATA_SIZE_IN_BITS)) +#define CFA_P70_LKUP_WC_MAX_DATA_SIZE \ + (BITS_TO_BYTES(CFA_P70_LKUP_WC_DATA_SIZE_WITH_CTRL_INFO_IN_BITS)) +#define CFA_P70_LKUP_WC_NUM_WORDS (BYTES_TO_WORDS(CFA_P70_LKUP_WC_DATA_SIZE)) +#define CFA_P70_LKUP_WC_NUM_WORDS_PER_BANK (CFA_P70_LKUP_WC_NUM_WORDS / 2) +#define CFA_P70_LKUP_WC_LREC_DATA_SIZE \ + (BITS_TO_BYTES(CFA_P70_WC_LREC_TOTAL_NUM_BITS)) +#define CFA_P70_LKUP_WC_LREC_NUM_WORDS \ + (BYTES_TO_WORDS(CFA_P70_LKUP_WC_LREC_DATA_SIZE)) +#define CFA_P70_LKUP_WC_SLICE_LEN_WITH_CTRL_INFO 175 +#define CFA_P70_LKUP_WC_SLICE_LEN 172 +#define CFA_P70_LKUP_WC_TCAM_IDX_MASK 0x1fff +#define CFA_P70_LKUP_WC_ROW_IDX_SFT 2 +#define CFA_P70_LKUP_WC_SLICE_IDX_MASK 0x3 +#define CFA_P70_LKUP_WC_NUM_SLICES 4 +#define CFA_P70_LKUP_WC_NUM_SLICES_PER_BANK 2 +#define CFA_P70_LKUP_WC_TCAM_CTRL_172B_KEY 0 +#define CFA_P70_LKUP_WC_TCAM_CTRL_344B_KEY 1 +#define CFA_P70_LKUP_WC_TCAM_CTRL_688B_KEY 2 +#define CFA_P70_LKUP_WC_TCAM_CTRL_MODE_SFT 29 +#define CFA_P70_LKUP_WC_TCAM_CTRL_MODE_MASK 0x3 +#define CFA_P70_LKUP_WC_TCAM_CTRL_VALID_SFT 31 +#define CFA_P70_LKUP_WC_TCAM_CTRL_VALID_MASK 0x1 +#define CFA_P70_LKUP_WC_TCAM_CTRL_NUM_BITS 3 +#define CFA_P70_LKUP_WC_TCAM_CTRL_MODE_NUM_BITS 2 +#define GET_NUM_SLICES_FROM_MODE(mode) (1 << (mode)) +#define CFA_P70_LKUP_WC_SLICE_NUM_BYTES \ + (BITS_TO_BYTES(CFA_P70_LKUP_WC_SLICE_LEN_WITH_CTRL_INFO)) +#define CFA_P70_LKUP_WC_SLICE_NUM_WORDS \ + (BYTES_TO_WORDS(CFA_P70_LKUP_WC_SLICE_NUM_BYTES)) +#define CFA_P70_WC_TCAM_GET_NUM_SLICES_FROM_NUM_BYTES(n) \ + ((((n) << 3) + CFA_P70_LKUP_WC_SLICE_LEN_WITH_CTRL_INFO - 1) / \ + CFA_P70_LKUP_WC_SLICE_LEN_WITH_CTRL_INFO) +#define CFA_MASK32(N) (((N) < 32) ? ((1U << (N)) - 1) : 0xffffffff) +#define CFA_P70_ECV_VTAG_ADD0_IMMED CFA_P70_ECV_VTAG_ADD0_IMMED_PRI0 +#define CFA_P70_ECV_VTAG_PRI_MASK \ + (~CFA_P70_ECV_VTAG_ADD0_IMMED & \ + CFA_MASK32(CFA_P70_ACT_ENC_ECV_VTAG_NUM_BITS)) + +#define CFA_P70_LKUP_EPOCH0_NUM_WORDS 1 +#define CFA_P70_LKUP_EPOCH1_NUM_WORDS 1 +#define CFA_P70_LKUP_EPOCH0_ENTRIES 4096 +#define CFA_P70_LKUP_EPOCH1_ENTRIES 256 + +/* Field range check table register widths */ +#define CFA_P70_FRC_PROF_NUM_WORDS \ + NUM_WORDS_ALIGN_32BIT(CFA_P70_LKUP_FRC_PROFILE_TOTAL_NUM_BITS) +#define CFA_P70_FRC_ENTRY_NUM_WORDS \ + NUM_WORDS_ALIGN_32BIT(CFA_P70_LKUP_FRC_RANGE_TOTAL_NUM_BITS) + +/* Connection tracking table register widths */ +#define CFA_P70_CT_STATE_NUM_WORDS \ + NUM_WORDS_ALIGN_32BIT(CFA_P70_LKUP_CT_STATE_TOTAL_NUM_BITS) +#define CFA_P70_CT_RULE_TCAM_NUM_WORDS \ + NUM_WORDS_ALIGN_32BIT(CFA_P70_LKUP_CT_RULE_TOTAL_NUM_BITS) +#define CFA_P70_CT_RULE_TCAM_RMP_NUM_WORDS \ + NUM_WORDS_ALIGN_32BIT(CFA_P70_LKUP_CT_RULE_RECORD_TOTAL_NUM_BITS) + +/* Feature Chain table register widths */ +#define CFA_P70_ACT_FC_TCAM_NUM_WORDS \ + NUM_WORDS_ALIGN_32BIT(CFA_P70_ACT_FC_TCAM_TOTAL_NUM_BITS) +#define CFA_P70_ACT_FC_TCAM_RMP_NUM_WORDS \ + NUM_WORDS_ALIGN_32BIT(CFA_P70_ACT_FC_TCAM_RESULT_TOTAL_NUM_BITS) +/* Feature Context table register width */ +#define CFA_P70_ACT_FC_NUM_WORDS \ + NUM_WORDS_ALIGN_128BIT(CFA_P70_ACT_FC_RMP_DR_TOTAL_NUM_BITS) + +/* Meter instance table register width */ +#define CFA_P70_ACT_METER_NUM_WORDS \ + NUM_WORDS_ALIGN_128BIT(CFA_P70_METERS_TOTAL_NUM_BITS) + +/* Metadata Mask table register widths */ +#define CFA_P70_METAMASK_PROF_NUM_WORDS 1 +#define CFA_P70_METAMASK_LKUP_NUM_WORDS 1 +#define CFA_P70_METAMASK_ACT_NUM_WORDS 1 +#define MAX_METAMASK_PROF(chip_cfg) 8 +#define MAX_METAMASK_LKUP(chip_cfg) 8 +#define MAX_METAMASK_ACT(chip_cfg) 16 + +#define CFA_P70_VEB_TCAM_NUM_SLICES 1 +#define CFA_P70_CT_TCAM_NUM_SLICES 1 +#define CFA_P70_FC_TCAM_NUM_SLICES 1 +#define CFA_P70_L2CTXT_TCAM_NUM_SLICES 1 +#define CFA_P70_PROF_TCAM_NUM_SLICES 1 + +#endif /* _CFA_P70_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_p70_hw.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_p70_hw.h new file mode 100644 index 0000000000..a6df5be179 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_p70_hw.h @@ -0,0 +1,4286 @@ +/**************************************************************************** + * Copyright(c) 2001-2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * Name: cfa_p70_hw.h + * + * Description: CFA HW table layout field position/length definitions + * + * Date: 09/29/22 11:50:37 + * + * Note: This file is scripted generated by ./cfa_header_gen.py. + * DO NOT modify this file manually !!!! + * + ****************************************************************************/ +#ifndef _CFA_P70_HW_H_ +#define _CFA_P70_HW_H_ + +/* clang-format off */ +#include "cfa_bld_p70_field_ids.h" + + +/** + * Field code selection 1 for range checking (for idx 1 ...) + */ +#define CFA_P70_LKUP_FRC_PROFILE_FIELD_SEL_1_BITPOS 36 +#define CFA_P70_LKUP_FRC_PROFILE_FIELD_SEL_1_NUM_BITS 4 + +/** + * Mask of ranges to check against FIELD_SEL_1 + */ +#define CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_1_BITPOS 20 +#define CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_1_NUM_BITS 16 + +/** + * Field code selection 0 for range checking + */ +#define CFA_P70_LKUP_FRC_PROFILE_FIELD_SEL_0_BITPOS 16 +#define CFA_P70_LKUP_FRC_PROFILE_FIELD_SEL_0_NUM_BITS 4 + +/** + * Mask of ranges to check against FIELD_SEL_0 The following shows the + * FIELD_SEL code points: + */ +#define CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_BITPOS 0 +#define CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_NUM_BITS 16 +/** + * Mask of ranges to check against FIELD_SEL_0 The following shows the + * FIELD_SEL code points: + */ +enum cfa_p70_lkup_frc_profile_range_check_0 { + CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_TL2_OVLAN_VID = 0, + CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_TL2_IVLAN_VID = 1, + CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_TL4_SRC = 2, + CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_TL4_DEST = 3, + CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_L2_OVLAN_VID = 4, + CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_L2_IVLAN_VID = 5, + CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_IP_LENGTH = 6, + CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_L4_SRC = 7, + CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_L4_DEST = 8, + CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_TUN_ID = 9, + CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_TUN_CTXT = 10, + CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_0 = 15, +}; + +/** + * Total number of bits for LKUP_FRC_PROFILE + */ +#define CFA_P70_LKUP_FRC_PROFILE_TOTAL_NUM_BITS 40 + +/** + * When 1, block rule searches and do host notify during background + * visit + */ +#define CFA_P70_LKUP_CT_STATE_NOTIFY_BITPOS 13 +#define CFA_P70_LKUP_CT_STATE_NOTIFY_NUM_BITS 1 + +/** + * Next state to go to after host notify (only used when NOTIFY=1) + */ +#define CFA_P70_LKUP_CT_STATE_NOTIFY_STATE_BITPOS 8 +#define CFA_P70_LKUP_CT_STATE_NOTIFY_STATE_NUM_BITS 5 + +/** + * Default forwarding action (0=fwd, 1=miss, 2/3=copy) + */ +#define CFA_P70_LKUP_CT_STATE_ACTION_BITPOS 6 +#define CFA_P70_LKUP_CT_STATE_ACTION_NUM_BITS 2 + +/** + * Specifies timer (0=disabled, 1-3=timers 1-3) + */ +#define CFA_P70_LKUP_CT_STATE_TIMER_SELECT_BITPOS 4 +#define CFA_P70_LKUP_CT_STATE_TIMER_SELECT_NUM_BITS 2 + +/** + * Timer preload value for connections in this state + */ +#define CFA_P70_LKUP_CT_STATE_TIMER_PRELOAD_BITPOS 0 +#define CFA_P70_LKUP_CT_STATE_TIMER_PRELOAD_NUM_BITS 4 + +/** + * Total number of bits for LKUP_CT_STATE + */ +#define CFA_P70_LKUP_CT_STATE_TOTAL_NUM_BITS 14 + +/** + * Rule only used if VALID=1 (for idx 1 ...) + */ +#define CFA_P70_LKUP_CT_RULE_VALID_BITPOS 38 +#define CFA_P70_LKUP_CT_RULE_VALID_NUM_BITS 1 + +/** + * Mask + */ +#define CFA_P70_LKUP_CT_RULE_MASK_BITPOS 19 +#define CFA_P70_LKUP_CT_RULE_MASK_NUM_BITS 19 + +/** + * Rule for packet (1) or background (0) + */ +#define CFA_P70_LKUP_CT_RULE_PKT_NOT_BG_BITPOS 18 +#define CFA_P70_LKUP_CT_RULE_PKT_NOT_BG_NUM_BITS 1 + +/** + * Current connection state + */ +#define CFA_P70_LKUP_CT_RULE_STATE_BITPOS 13 +#define CFA_P70_LKUP_CT_RULE_STATE_NUM_BITS 5 + +/** + * TCP packet flags + */ +#define CFA_P70_LKUP_CT_RULE_TCP_FLAGS_BITPOS 4 +#define CFA_P70_LKUP_CT_RULE_TCP_FLAGS_NUM_BITS 9 + +/** + * Packet protocol is TCP + */ +#define CFA_P70_LKUP_CT_RULE_PROT_IS_TCP_BITPOS 3 +#define CFA_P70_LKUP_CT_RULE_PROT_IS_TCP_NUM_BITS 1 + +/** + * Updating tcp_msb_loc + */ +#define CFA_P70_LKUP_CT_RULE_MSB_UPDT_BITPOS 2 +#define CFA_P70_LKUP_CT_RULE_MSB_UPDT_NUM_BITS 1 + +/** + * Packet flag error + */ +#define CFA_P70_LKUP_CT_RULE_FLAGS_FAILED_BITPOS 1 +#define CFA_P70_LKUP_CT_RULE_FLAGS_FAILED_NUM_BITS 1 + +/** + * Packet failed TCP window check If VALID=0, the rule is ignored during + * searches. When VALID=1, MASK[18:0] provides a mask for bits 18:0. If + * the mask bit is set to 0, the corresponding bit is ignored during + * searches (does not need to match for the rule to match). During + * background updates, all fields in the search key other than STATE are + * always 0 (PKT_NOT_BG=0 and the other fields are unused). During + * packet updates when PROT_IS_TCP=0, PKT_NOT_BG=1 and STATE is set to + * the current state but the other fields will always be 0. If there is + * a matching rule found, the record in LKUP_CT_RULE_RECORD for that + * rule number is used. + */ +#define CFA_P70_LKUP_CT_RULE_WIN_FAILED_BITPOS 0 +#define CFA_P70_LKUP_CT_RULE_WIN_FAILED_NUM_BITS 1 + +/** + * Total number of bits for LKUP_CT_RULE + */ +#define CFA_P70_LKUP_CT_RULE_TOTAL_NUM_BITS 39 + +/** + * Forward action (packet only): 0=fwd, 1=miss, 2/3=copy + */ +#define CFA_P70_LKUP_CT_RULE_RECORD_ACTION_BITPOS 7 +#define CFA_P70_LKUP_CT_RULE_RECORD_ACTION_NUM_BITS 2 + +/** + * Next state for the connection + */ +#define CFA_P70_LKUP_CT_RULE_RECORD_NEXT_STATE_BITPOS 2 +#define CFA_P70_LKUP_CT_RULE_RECORD_NEXT_STATE_NUM_BITS 5 + +/** + * Signals whether to send message to other CFA.k When SEND=0, no + * message is sent. Otherwise, SEND[1] indicates that TCP_MSB_LOC in the + * message is valid and SEND[0] that STATE is valid. + */ +#define CFA_P70_LKUP_CT_RULE_RECORD_SEND_BITPOS 0 +#define CFA_P70_LKUP_CT_RULE_RECORD_SEND_NUM_BITS 2 + +/** + * Total number of bits for LKUP_CT_RULE_RECORD + */ +#define CFA_P70_LKUP_CT_RULE_RECORD_TOTAL_NUM_BITS 9 + +/** + * destination remap mode when enabled + */ +#define CFA_P70_ACT_VEB_RMP_MODE_BITPOS 6 +#define CFA_P70_ACT_VEB_RMP_MODE_NUM_BITS 1 +/** + * destination remap mode when enabled + */ +enum cfa_p70_act_veb_rmp_mode { + /* over write existing bitmap with entry */ + CFA_P70_ACT_VEB_RMP_MODE_OVRWRT = 0, + /* or entry bit map with existing */ + CFA_P70_ACT_VEB_RMP_MODE_ORTGTHR = 1, +}; + +/** + * enable remap the bitmap + */ +#define CFA_P70_ACT_VEB_RMP_ENABLE_BITPOS 5 +#define CFA_P70_ACT_VEB_RMP_ENABLE_NUM_BITS 1 + +/** + * destination bitmap #CAS_SW_REF + * Action.CFA.VEB.Remap.tx.veb.remap.entry + */ +#define CFA_P70_ACT_VEB_RMP_BITMAP_BITPOS 0 +#define CFA_P70_ACT_VEB_RMP_BITMAP_NUM_BITS 5 + +/** + * Total number of bits for ACT_VEB_RMP + */ +#define CFA_P70_ACT_VEB_RMP_TOTAL_NUM_BITS 7 + +/** + * Range low + */ +#define CFA_P70_LKUP_FRC_RANGE_RANGE_LO_BITPOS 16 +#define CFA_P70_LKUP_FRC_RANGE_RANGE_LO_NUM_BITS 16 + +/** + * Range high Field matches range when in [range_lo, range_hi] + * (inclusive). A read/write to this register causes a read/write to the + * LKUP_FRC_RANGE memory at address LKUP_FRC_RANGE_ADDR. + */ +#define CFA_P70_LKUP_FRC_RANGE_RANGE_HI_BITPOS 0 +#define CFA_P70_LKUP_FRC_RANGE_RANGE_HI_NUM_BITS 16 + +/** + * Total number of bits for LKUP_FRC_RANGE + */ +#define CFA_P70_LKUP_FRC_RANGE_TOTAL_NUM_BITS 32 + +/** + * TCAM entry is valid (for idx 7 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_VALID_BITPOS 255 +#define CFA_P70_PROF_L2_CTXT_TCAM_VALID_NUM_BITS 1 + +/** + * spare bits (for idx 7 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_SPARE_BITPOS 253 +#define CFA_P70_PROF_L2_CTXT_TCAM_SPARE_NUM_BITS 2 + +/** + * Multi-pass cycle count (for idx 7 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_MPASS_CNT_BITPOS 251 +#define CFA_P70_PROF_L2_CTXT_TCAM_MPASS_CNT_NUM_BITS 2 + +/** + * Recycle count from prof_in (for idx 7 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_RCYC_BITPOS 247 +#define CFA_P70_PROF_L2_CTXT_TCAM_RCYC_NUM_BITS 4 + +/** + * loopback input from prof_in (for idx 7 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_LOOPBACK_BITPOS 246 +#define CFA_P70_PROF_L2_CTXT_TCAM_LOOPBACK_NUM_BITS 1 + +/** + * Source network port from prof_in (for idx 7 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_SPIF_BITPOS 244 +#define CFA_P70_PROF_L2_CTXT_TCAM_SPIF_NUM_BITS 2 + +/** + * Partition provided by input block (for idx 7 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_PARIF_BITPOS 239 +#define CFA_P70_PROF_L2_CTXT_TCAM_PARIF_NUM_BITS 5 + +/** + * Source network port or vnic (for idx 7 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_SVIF_BITPOS 228 +#define CFA_P70_PROF_L2_CTXT_TCAM_SVIF_NUM_BITS 11 + +/** + * Metadata provided by Input block + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_METADATA_BITPOS 196 +#define CFA_P70_PROF_L2_CTXT_TCAM_METADATA_NUM_BITS 32 + +/** + * L2 function + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_L2_FUNC_BITPOS 188 +#define CFA_P70_PROF_L2_CTXT_TCAM_L2_FUNC_NUM_BITS 8 + +/** + * ROCE Packet detected by the Parser (for idx 5 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_ROCE_BITPOS 187 +#define CFA_P70_PROF_L2_CTXT_TCAM_ROCE_NUM_BITS 1 + +/** + * Pure LLC Packet detected by the Parser. (for idx 5 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_PURE_LLC_BITPOS 186 +#define CFA_P70_PROF_L2_CTXT_TCAM_PURE_LLC_NUM_BITS 1 + +/** + * 5b enc Outer Tunnel Type (for idx 5 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_OT_HDR_TYPE_BITPOS 181 +#define CFA_P70_PROF_L2_CTXT_TCAM_OT_HDR_TYPE_NUM_BITS 5 + +/** + * 5b enc Tunnel Type The id_ctxt field is tunnel id or tunnel context + * selected from outer tunnel header or tunnel header. (for idx 5 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_T_HDR_TYPE_BITPOS 176 +#define CFA_P70_PROF_L2_CTXT_TCAM_T_HDR_TYPE_NUM_BITS 5 + +/** + * FLDS Tunnel Status ID or Context. Each of these fields are from the + * selected outer tunnel, tunnel, inner, or outermost L2 header + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_ID_CTXT_BITPOS 144 +#define CFA_P70_PROF_L2_CTXT_TCAM_ID_CTXT_NUM_BITS 32 + +/** + * Selected DMAC/SMAC + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_MAC0_BITPOS 96 +#define CFA_P70_PROF_L2_CTXT_TCAM_MAC0_NUM_BITS 48 + +/** + * Selected DMAC/SMAC + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_MAC1_BITPOS 48 +#define CFA_P70_PROF_L2_CTXT_TCAM_MAC1_NUM_BITS 48 + +/** + * 1+ VLAN tags present (for idx 1 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_VTAG_PRESENT_BITPOS 47 +#define CFA_P70_PROF_L2_CTXT_TCAM_VTAG_PRESENT_NUM_BITS 1 + +/** + * 2 VLAN tags present (for idx 1 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_TWO_VTAGS_BITPOS 46 +#define CFA_P70_PROF_L2_CTXT_TCAM_TWO_VTAGS_NUM_BITS 1 + +/** + * Outer VLAN VID (for idx 1 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_OVLAN_VID_BITPOS 34 +#define CFA_P70_PROF_L2_CTXT_TCAM_OVLAN_VID_NUM_BITS 12 + +/** + * Outer VLAN TPID, 3b encoded + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_OVLAN_TPID_SEL_BITPOS 31 +#define CFA_P70_PROF_L2_CTXT_TCAM_OVLAN_TPID_SEL_NUM_BITS 3 + +/** + * Inner VLAN VID + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_IVLAN_VID_BITPOS 19 +#define CFA_P70_PROF_L2_CTXT_TCAM_IVLAN_VID_NUM_BITS 12 + +/** + * Inner VLAN TPID, 3b encoded + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_IVLAN_TPID_SEL_BITPOS 16 +#define CFA_P70_PROF_L2_CTXT_TCAM_IVLAN_TPID_SEL_NUM_BITS 3 + +/** + * Ethertype. #CAS_SW_REF Profiler.l2ip.context.tcam.key #CAS_SW_REF + * Profiler.l2ip.context.ipv6.tcam.key + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_ETYPE_BITPOS 0 +#define CFA_P70_PROF_L2_CTXT_TCAM_ETYPE_NUM_BITS 16 + +/** + * Total number of bits for PROF_L2_CTXT_TCAM + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_TOTAL_NUM_BITS 256 + +/** + * Valid(1)/Invalid(0) TCAM entry. (for idx 5 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_VALID_BITPOS 183 +#define CFA_P70_PROF_PROFILE_TCAM_VALID_NUM_BITS 1 + +/** + * spare bits. (for idx 5 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_SPARE_BITPOS 181 +#define CFA_P70_PROF_PROFILE_TCAM_SPARE_NUM_BITS 2 + +/** + * Loopback bit. (for idx 5 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_LOOPBACK_BITPOS 180 +#define CFA_P70_PROF_PROFILE_TCAM_LOOPBACK_NUM_BITS 1 + +/** + * Packet type directly from prof_in (for idx 5 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_PKT_TYPE_BITPOS 176 +#define CFA_P70_PROF_PROFILE_TCAM_PKT_TYPE_NUM_BITS 4 + +/** + * Recycle count from prof_in (for idx 5 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_RCYC_BITPOS 172 +#define CFA_P70_PROF_PROFILE_TCAM_RCYC_NUM_BITS 4 + +/** + * From L2 Context Lookup stage. + */ +#define CFA_P70_PROF_PROFILE_TCAM_METADATA_BITPOS 140 +#define CFA_P70_PROF_PROFILE_TCAM_METADATA_NUM_BITS 32 + +/** + * Aggregate error flag from Input stage. (for idx 4 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_AGG_ERROR_BITPOS 139 +#define CFA_P70_PROF_PROFILE_TCAM_AGG_ERROR_NUM_BITS 1 + +/** + * L2 function (for idx 4 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_L2_FUNC_BITPOS 131 +#define CFA_P70_PROF_PROFILE_TCAM_L2_FUNC_NUM_BITS 8 + +/** + * Profile function from L2 Context Lookup stage. + */ +#define CFA_P70_PROF_PROFILE_TCAM_PROF_FUNC_BITPOS 123 +#define CFA_P70_PROF_PROFILE_TCAM_PROF_FUNC_NUM_BITS 8 + +/** + * From FLDS Input General Status tunnel(1)/no tunnel(0) (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_HREC_NEXT_BITPOS 121 +#define CFA_P70_PROF_PROFILE_TCAM_HREC_NEXT_NUM_BITS 2 + +/** + * INT header type. (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_INT_HDR_TYPE_BITPOS 119 +#define CFA_P70_PROF_PROFILE_TCAM_INT_HDR_TYPE_NUM_BITS 2 + +/** + * INT header group. (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_INT_HDR_GROUP_BITPOS 117 +#define CFA_P70_PROF_PROFILE_TCAM_INT_HDR_GROUP_NUM_BITS 2 + +/** + * INT metadata is tail stamp. (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_INT_IFA_TAIL_BITPOS 116 +#define CFA_P70_PROF_PROFILE_TCAM_INT_IFA_TAIL_NUM_BITS 1 + +/** + * resolved flds_otl2_hdr_valid. (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OTL2_HDR_VALID_BITPOS 115 +#define CFA_P70_PROF_PROFILE_TCAM_OTL2_HDR_VALID_NUM_BITS 1 + +/** + * Outer Tunnel L2 header type. (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OTL2_HDR_TYPE_BITPOS 113 +#define CFA_P70_PROF_PROFILE_TCAM_OTL2_HDR_TYPE_NUM_BITS 2 + +/** + * flds_otl2_dst_type remapped: UC(0)/MC(2)/BC(3) (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OTL2_UC_MC_BC_BITPOS 111 +#define CFA_P70_PROF_PROFILE_TCAM_OTL2_UC_MC_BC_NUM_BITS 2 + +/** + * 1+ VLAN tags present in Outer Tunnel L2 header (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OTL2_VTAG_PRESENT_BITPOS 110 +#define CFA_P70_PROF_PROFILE_TCAM_OTL2_VTAG_PRESENT_NUM_BITS 1 + +/** + * 2 VLAN tags present in Outer Tunnel L2 header (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OTL2_TWO_VTAGS_BITPOS 109 +#define CFA_P70_PROF_PROFILE_TCAM_OTL2_TWO_VTAGS_NUM_BITS 1 + +/** + * resolved flds_otl3_hdr_valid. (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_VALID_BITPOS 108 +#define CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_VALID_NUM_BITS 1 + +/** + * flds_otl3_hdr_valid is stop_w_error. (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_ERROR_BITPOS 107 +#define CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_ERROR_NUM_BITS 1 + +/** + * Outer Tunnel L3 header type directly from FLDS. (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_TYPE_BITPOS 103 +#define CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_TYPE_NUM_BITS 4 + +/** + * Outer Tunnel L3 header is IPV4 or IPV6. (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_ISIP_BITPOS 102 +#define CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_ISIP_NUM_BITS 1 + +/** + * resolved flds_otl4_hdr_valid. (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_VALID_BITPOS 101 +#define CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_VALID_NUM_BITS 1 + +/** + * flds_otl4_hdr_valid is stop_w_error. (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_ERROR_BITPOS 100 +#define CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_ERROR_NUM_BITS 1 + +/** + * Outer Tunnel L4 header type. (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_TYPE_BITPOS 96 +#define CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_TYPE_NUM_BITS 4 + +/** + * OTL4 header is UDP or TCP. (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_IS_UDP_TCP_BITPOS 95 +#define CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_IS_UDP_TCP_NUM_BITS 1 + +/** + * resolved flds_ot_hdr_valid. (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OT_HDR_VALID_BITPOS 94 +#define CFA_P70_PROF_PROFILE_TCAM_OT_HDR_VALID_NUM_BITS 1 + +/** + * flds_ot_hdr_valid is stop_w_error. (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OT_HDR_ERROR_BITPOS 93 +#define CFA_P70_PROF_PROFILE_TCAM_OT_HDR_ERROR_NUM_BITS 1 + +/** + * Outer Tunnel header type. (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OT_HDR_TYPE_BITPOS 88 +#define CFA_P70_PROF_PROFILE_TCAM_OT_HDR_TYPE_NUM_BITS 5 + +/** + * Outer Tunnel header flags. (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OT_HDR_FLAGS_BITPOS 80 +#define CFA_P70_PROF_PROFILE_TCAM_OT_HDR_FLAGS_NUM_BITS 8 + +/** + * resolved flds_tl2_hdr_valid. (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TL2_HDR_VALID_BITPOS 79 +#define CFA_P70_PROF_PROFILE_TCAM_TL2_HDR_VALID_NUM_BITS 1 + +/** + * Tunnel L2 header type directly from FLDS. (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TL2_HDR_TYPE_BITPOS 77 +#define CFA_P70_PROF_PROFILE_TCAM_TL2_HDR_TYPE_NUM_BITS 2 + +/** + * flds_tl2_dst_type remapped: UC(0)/MC(2)/BC(3) (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TL2_UC_MC_BC_BITPOS 75 +#define CFA_P70_PROF_PROFILE_TCAM_TL2_UC_MC_BC_NUM_BITS 2 + +/** + * 1+ VLAN tags present in Tunnel L2 header (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TL2_VTAG_PRESENT_BITPOS 74 +#define CFA_P70_PROF_PROFILE_TCAM_TL2_VTAG_PRESENT_NUM_BITS 1 + +/** + * 2 VLAN tags present in Tunnel L2 header (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TL2_TWO_VTAGS_BITPOS 73 +#define CFA_P70_PROF_PROFILE_TCAM_TL2_TWO_VTAGS_NUM_BITS 1 + +/** + * resolved flds_tl3_hdr_valid. (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_VALID_BITPOS 72 +#define CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_VALID_NUM_BITS 1 + +/** + * flds_tl3_hdr_valid is stop_w_error. (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_ERROR_BITPOS 71 +#define CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_ERROR_NUM_BITS 1 + +/** + * Tunnel L3 header type directly from FLDS. (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_TYPE_BITPOS 67 +#define CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_TYPE_NUM_BITS 4 + +/** + * Tunnel L3 header is IPV4 or IPV6. (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_ISIP_BITPOS 66 +#define CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_ISIP_NUM_BITS 1 + +/** + * resolved flds_tl4_hdr_valid. (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_VALID_BITPOS 65 +#define CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_VALID_NUM_BITS 1 + +/** + * flds_tl4_hdr_valid is stop_w_error. (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_ERROR_BITPOS 64 +#define CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_ERROR_NUM_BITS 1 + +/** + * Tunnel L4 header type directly from FLDS. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_TYPE_BITPOS 60 +#define CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_TYPE_NUM_BITS 4 + +/** + * TL4 header is UDP or TCP. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_IS_UDP_TCP_BITPOS 59 +#define CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_IS_UDP_TCP_NUM_BITS 1 + +/** + * resolved flds_tun_hdr_valid. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_VALID_BITPOS 58 +#define CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_VALID_NUM_BITS 1 + +/** + * flds_tun_hdr_valid is stop_w_error. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_ERROR_BITPOS 57 +#define CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_ERROR_NUM_BITS 1 + +/** + * Tunnel header type directly from FLDS. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_TYPE_BITPOS 52 +#define CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_TYPE_NUM_BITS 5 + +/** + * Tunnel header flags directly from FLDS. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_FLAGS_BITPOS 44 +#define CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_FLAGS_NUM_BITS 8 + +/** + * resolved flds_l2_hdr_valid. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_L2_HDR_VALID_BITPOS 43 +#define CFA_P70_PROF_PROFILE_TCAM_L2_HDR_VALID_NUM_BITS 1 + +/** + * flds_l2_hdr_valid is stop_w_error. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_L2_HDR_ERROR_BITPOS 42 +#define CFA_P70_PROF_PROFILE_TCAM_L2_HDR_ERROR_NUM_BITS 1 + +/** + * L2 header type directly from FLDS. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_L2_HDR_TYPE_BITPOS 40 +#define CFA_P70_PROF_PROFILE_TCAM_L2_HDR_TYPE_NUM_BITS 2 + +/** + * flds_l2_dst_type remapped: UC(0)/MC(2)/BC(3). (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_L2_UC_MC_BC_BITPOS 38 +#define CFA_P70_PROF_PROFILE_TCAM_L2_UC_MC_BC_NUM_BITS 2 + +/** + * 1+ VLAN tags present in inner L2 header. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_L2_VTAG_PRESENT_BITPOS 37 +#define CFA_P70_PROF_PROFILE_TCAM_L2_VTAG_PRESENT_NUM_BITS 1 + +/** + * 2 VLAN tags present in inner L2 header. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_L2_TWO_VTAGS_BITPOS 36 +#define CFA_P70_PROF_PROFILE_TCAM_L2_TWO_VTAGS_NUM_BITS 1 + +/** + * resolved flds_l3_hdr_valid. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_L3_HDR_VALID_BITPOS 35 +#define CFA_P70_PROF_PROFILE_TCAM_L3_HDR_VALID_NUM_BITS 1 + +/** + * flds_l3_hdr_valid is stop_w_error. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_L3_HDR_ERROR_BITPOS 34 +#define CFA_P70_PROF_PROFILE_TCAM_L3_HDR_ERROR_NUM_BITS 1 + +/** + * L3 header type directly from FLDS. + */ +#define CFA_P70_PROF_PROFILE_TCAM_L3_HDR_TYPE_BITPOS 30 +#define CFA_P70_PROF_PROFILE_TCAM_L3_HDR_TYPE_NUM_BITS 4 + +/** + * L3 header is IPV4 or IPV6. + */ +#define CFA_P70_PROF_PROFILE_TCAM_L3_HDR_ISIP_BITPOS 29 +#define CFA_P70_PROF_PROFILE_TCAM_L3_HDR_ISIP_NUM_BITS 1 + +/** + * L3 header next protocol directly from FLDS. + */ +#define CFA_P70_PROF_PROFILE_TCAM_L3_PROT_BITPOS 21 +#define CFA_P70_PROF_PROFILE_TCAM_L3_PROT_NUM_BITS 8 + +/** + * resolved flds_l4_hdr_valid. + */ +#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_VALID_BITPOS 20 +#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_VALID_NUM_BITS 1 + +/** + * flds_l4_hdr_valid is stop_w_error. + */ +#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_ERROR_BITPOS 19 +#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_ERROR_NUM_BITS 1 + +/** + * L4 header type directly from FLDS. + */ +#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_TYPE_BITPOS 15 +#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_TYPE_NUM_BITS 4 + +/** + * L4 header is UDP or TCP.2 + */ +#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_IS_UDP_TCP_BITPOS 14 +#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_IS_UDP_TCP_NUM_BITS 1 + +/** + * L4 header subtype directly from FLDS. + */ +#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_SUBTYPE_BITPOS 11 +#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_SUBTYPE_NUM_BITS 3 + +/** + * L4 header flags directly from FLDS. + */ +#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_FLAGS_BITPOS 2 +#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_FLAGS_NUM_BITS 9 + +/** + * DCN present bits directly from FLDS. #CAS_SW_REF + * Profiler.profile.lookup.tcam.key + */ +#define CFA_P70_PROF_PROFILE_TCAM_L4_DCN_PRESENT_BITPOS 0 +#define CFA_P70_PROF_PROFILE_TCAM_L4_DCN_PRESENT_NUM_BITS 2 + +/** + * Total number of bits for PROF_PROFILE_TCAM + */ +#define CFA_P70_PROF_PROFILE_TCAM_TOTAL_NUM_BITS 184 + +/** + * Valid entry (for idx 2 ...) + */ +#define CFA_P70_ACT_VEB_TCAM_TX_VALID_BITPOS 79 +#define CFA_P70_ACT_VEB_TCAM_TX_VALID_NUM_BITS 1 + +/** + * PF Parif Number (for idx 2 ...) + */ +#define CFA_P70_ACT_VEB_TCAM_TX_PARIF_IN_BITPOS 74 +#define CFA_P70_ACT_VEB_TCAM_TX_PARIF_IN_NUM_BITS 5 + +/** + * Number of VLAN Tags. (for idx 2 ...) + */ +#define CFA_P70_ACT_VEB_TCAM_TX_NUM_VTAGS_BITPOS 72 +#define CFA_P70_ACT_VEB_TCAM_TX_NUM_VTAGS_NUM_BITS 2 + +/** + * Dest. MAC Address + */ +#define CFA_P70_ACT_VEB_TCAM_TX_DMAC_BITPOS 24 +#define CFA_P70_ACT_VEB_TCAM_TX_DMAC_NUM_BITS 48 + +/** + * Outer VLAN Tag ID + */ +#define CFA_P70_ACT_VEB_TCAM_TX_OVID_BITPOS 12 +#define CFA_P70_ACT_VEB_TCAM_TX_OVID_NUM_BITS 12 + +/** + * Inner VLAN Tag ID #CAS_SW_REF Action.CFA.VEB.TCAM.tx.veb.tcam.entry + */ +#define CFA_P70_ACT_VEB_TCAM_TX_IVID_BITPOS 0 +#define CFA_P70_ACT_VEB_TCAM_TX_IVID_NUM_BITS 12 + +/** + * Total number of bits for ACT_VEB_TCAM_TX + */ +#define CFA_P70_ACT_VEB_TCAM_TX_TOTAL_NUM_BITS 80 + +/** + * Valid entry (for idx 2 ...) + */ +#define CFA_P70_ACT_VEB_TCAM_RX_VALID_BITPOS 79 +#define CFA_P70_ACT_VEB_TCAM_RX_VALID_NUM_BITS 1 + +/** + * spare (for idx 2 ...) + */ +#define CFA_P70_ACT_VEB_TCAM_RX_SPARE_BITPOS 78 +#define CFA_P70_ACT_VEB_TCAM_RX_SPARE_NUM_BITS 1 + +/** + * program to zero (for idx 2 ...) + */ +#define CFA_P70_ACT_VEB_TCAM_RX_PADDING_BITPOS 68 +#define CFA_P70_ACT_VEB_TCAM_RX_PADDING_NUM_BITS 10 + +/** + * DMAC is unicast address (for idx 2 ...) + */ +#define CFA_P70_ACT_VEB_TCAM_RX_UNICAST_BITPOS 67 +#define CFA_P70_ACT_VEB_TCAM_RX_UNICAST_NUM_BITS 1 + +/** + * DMAC is multicast address (for idx 2 ...) + */ +#define CFA_P70_ACT_VEB_TCAM_RX_MULTICAST_BITPOS 66 +#define CFA_P70_ACT_VEB_TCAM_RX_MULTICAST_NUM_BITS 1 + +/** + * DMAC is broadcast address (for idx 2 ...) + */ +#define CFA_P70_ACT_VEB_TCAM_RX_BROADCAST_BITPOS 65 +#define CFA_P70_ACT_VEB_TCAM_RX_BROADCAST_NUM_BITS 1 + +/** + * pfid + */ +#define CFA_P70_ACT_VEB_TCAM_RX_PFID_BITPOS 60 +#define CFA_P70_ACT_VEB_TCAM_RX_PFID_NUM_BITS 5 + +/** + * vfid (for idx 1 ...) + */ +#define CFA_P70_ACT_VEB_TCAM_RX_VFID_BITPOS 48 +#define CFA_P70_ACT_VEB_TCAM_RX_VFID_NUM_BITS 12 + +/** + * source mac #CAS_SW_REF AAction.CFA.VEB.TCAM.rx.veb.tcam.entry + */ +#define CFA_P70_ACT_VEB_TCAM_RX_SMAC_BITPOS 0 +#define CFA_P70_ACT_VEB_TCAM_RX_SMAC_NUM_BITS 48 + +/** + * Total number of bits for ACT_VEB_TCAM_RX + */ +#define CFA_P70_ACT_VEB_TCAM_RX_TOTAL_NUM_BITS 80 + +/** + * Valid entry (for idx 1 ...) + */ +#define CFA_P70_ACT_FC_TCAM_FC_VALID_BITPOS 33 +#define CFA_P70_ACT_FC_TCAM_FC_VALID_NUM_BITS 1 + +/** + * Reserved (for idx 1 ...) + */ +#define CFA_P70_ACT_FC_TCAM_FC_RSVD_BITPOS 32 +#define CFA_P70_ACT_FC_TCAM_FC_RSVD_NUM_BITS 1 + +/** + * Updated metadata. #CAS_SW_REF Action.CFA.FC.TCAM.fc.tcam.meta.entry + * #CAS_SW_REF Action.CFA.FC.TCAM.fc.tcam.l2ip.func.entry #CAS_SW_REF + * Action.CFA.FC.TCAM.fc.tcam.l2.ctxt.entry #CAS_SW_REF + * Action.CFA.FC.TCAM.fc.tcam.l2ipf.ctxt.entry + */ +#define CFA_P70_ACT_FC_TCAM_FC_METADATA_BITPOS 0 +#define CFA_P70_ACT_FC_TCAM_FC_METADATA_NUM_BITS 32 + +/** + * Total number of bits for ACT_FC_TCAM + */ +#define CFA_P70_ACT_FC_TCAM_TOTAL_NUM_BITS 34 + +/** + * New metadata. + */ +#define CFA_P70_ACT_FC_RMP_DR_METADATA_BITPOS 40 +#define CFA_P70_ACT_FC_RMP_DR_METADATA_NUM_BITS 32 + +/** + * Metadata merge control mask. + */ +#define CFA_P70_ACT_FC_RMP_DR_METAMASK_BITPOS 8 +#define CFA_P70_ACT_FC_RMP_DR_METAMASK_NUM_BITS 32 + +/** + * New L2 function. #CAS_SW_REF Action.CFA.FC.Remap.fc.remap.entry + */ +#define CFA_P70_ACT_FC_RMP_DR_L2_FUNC_BITPOS 0 +#define CFA_P70_ACT_FC_RMP_DR_L2_FUNC_NUM_BITS 8 + +/** + * Total number of bits for ACT_FC_RMP_DR + */ +#define CFA_P70_ACT_FC_RMP_DR_TOTAL_NUM_BITS 72 + +/** + * enables ilt metadata (for idx 3 ...) + */ +#define CFA_P70_PROF_ILT_DR_ILT_META_EN_BITPOS 104 +#define CFA_P70_PROF_ILT_DR_ILT_META_EN_NUM_BITS 1 + +/** + * meta profile register index (for idx 3 ...) + */ +#define CFA_P70_PROF_ILT_DR_META_PROF_BITPOS 101 +#define CFA_P70_PROF_ILT_DR_META_PROF_NUM_BITS 3 + +/** + * ilt metadata, used when ilt_meta_en is set + */ +#define CFA_P70_PROF_ILT_DR_METADATA_BITPOS 69 +#define CFA_P70_PROF_ILT_DR_METADATA_NUM_BITS 32 + +/** + * Partition (for idx 2 ...) + */ +#define CFA_P70_PROF_ILT_DR_PARIF_BITPOS 64 +#define CFA_P70_PROF_ILT_DR_PARIF_NUM_BITS 5 + +/** + * L2 function (for idx 1 ...) + */ +#define CFA_P70_PROF_ILT_DR_L2_FUNC_BITPOS 56 +#define CFA_P70_PROF_ILT_DR_L2_FUNC_NUM_BITS 8 + +/** + * When set cfa_meta opcode is allowed (for idx 1 ...) + */ +#define CFA_P70_PROF_ILT_DR_EN_BD_META_BITPOS 55 +#define CFA_P70_PROF_ILT_DR_EN_BD_META_NUM_BITS 1 + +/** + * When set act_rec_ptr is set to cfa_action if it is non-zero. + * Otherwise act_rec_ptr is set to act_rec_ptr from this table. (for idx + * 1 ...) + */ +#define CFA_P70_PROF_ILT_DR_EN_BD_ACTION_BITPOS 54 +#define CFA_P70_PROF_ILT_DR_EN_BD_ACTION_NUM_BITS 1 + +/** + * When set destination is set to destination from this table. Otherwise + * it is set to est_dest. (for idx 1 ...) + */ +#define CFA_P70_PROF_ILT_DR_EN_ILT_DEST_BITPOS 53 +#define CFA_P70_PROF_ILT_DR_EN_ILT_DEST_NUM_BITS 1 + +/** + * ILT opcode (for idx 1 ...) + */ +#define CFA_P70_PROF_ILT_DR_ILT_FWD_OP_BITPOS 50 +#define CFA_P70_PROF_ILT_DR_ILT_FWD_OP_NUM_BITS 3 +/** + * ILT opcode (for idx 1 ...) + */ +enum cfa_p70_prof_ilt_dr_ilt_fwd_op { + /* cfa is bypassed */ + CFA_P70_PROF_ILT_DR_ILT_FWD_OP_BYPASS_CFA = 0, + /* cfa is bypassed if packet is ROCE */ + CFA_P70_PROF_ILT_DR_ILT_FWD_OP_BYPASS_CFA_ROCE = 1, + /* profiler and lookup blocks are bypassed */ + CFA_P70_PROF_ILT_DR_ILT_FWD_OP_BYPASS_LKUP = 2, + /* packet proceeds to L2 Context Stage */ + CFA_P70_PROF_ILT_DR_ILT_FWD_OP_NORMAL_FLOW = 3, + /* mark packet for drop */ + CFA_P70_PROF_ILT_DR_ILT_FWD_OP_DROP = 4, +}; + +/** + * action hint used with act_rec_ptr (for idx 1 ...) + */ +#define CFA_P70_PROF_ILT_DR_ILT_ACT_HINT_BITPOS 48 +#define CFA_P70_PROF_ILT_DR_ILT_ACT_HINT_NUM_BITS 2 + +/** + * table scope used with act_rec_ptr (for idx 1 ...) + */ +#define CFA_P70_PROF_ILT_DR_ILT_SCOPE_BITPOS 43 +#define CFA_P70_PROF_ILT_DR_ILT_SCOPE_NUM_BITS 5 + +/** + * Default act_rec_ptr or explicit on Lookup Bypass. + */ +#define CFA_P70_PROF_ILT_DR_ILT_ACT_REC_PTR_BITPOS 17 +#define CFA_P70_PROF_ILT_DR_ILT_ACT_REC_PTR_NUM_BITS 26 + +/** + * used for destination #CAS_SW_REF Profiler.input.lookup.table.entry + */ +#define CFA_P70_PROF_ILT_DR_ILT_DESTINATION_BITPOS 0 +#define CFA_P70_PROF_ILT_DR_ILT_DESTINATION_NUM_BITS 17 + +/** + * Total number of bits for PROF_ILT_DR + */ +#define CFA_P70_PROF_ILT_DR_TOTAL_NUM_BITS 105 + +/** + * Normal operation. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_PL_BYP_LKUP_EN_BITPOS 42 +#define CFA_P70_PROF_PROFILE_RMP_DR_PL_BYP_LKUP_EN_NUM_BITS 1 + +/** + * Enable search in EM database. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_EM_SEARCH_EN_BITPOS 41 +#define CFA_P70_PROF_PROFILE_RMP_DR_EM_SEARCH_EN_NUM_BITS 1 + +/** + * ID to differentiate common EM keys. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_EM_PROFILE_ID_BITPOS 33 +#define CFA_P70_PROF_PROFILE_RMP_DR_EM_PROFILE_ID_NUM_BITS 8 + +/** + * Exact match key template select. + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_EM_KEY_ID_BITPOS 26 +#define CFA_P70_PROF_PROFILE_RMP_DR_EM_KEY_ID_NUM_BITS 7 + +/** + * Exact Match Lookup table scope. + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_EM_SCOPE_BITPOS 21 +#define CFA_P70_PROF_PROFILE_RMP_DR_EM_SCOPE_NUM_BITS 5 + +/** + * Enable search in TCAM database. + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_TCAM_SEARCH_EN_BITPOS 20 +#define CFA_P70_PROF_PROFILE_RMP_DR_TCAM_SEARCH_EN_NUM_BITS 1 + +/** + * ID to differentiate common TCAM keys. + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_TCAM_PROFILE_ID_BITPOS 12 +#define CFA_P70_PROF_PROFILE_RMP_DR_TCAM_PROFILE_ID_NUM_BITS 8 + +/** + * TCAM key template select. + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_TCAM_KEY_ID_BITPOS 5 +#define CFA_P70_PROF_PROFILE_RMP_DR_TCAM_KEY_ID_NUM_BITS 7 + +/** + * Wild-card TCAM Lookup table scope. + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_TCAM_SCOPE_BITPOS 0 +#define CFA_P70_PROF_PROFILE_RMP_DR_TCAM_SCOPE_NUM_BITS 5 + +/** + * Total number of bits for PROF_PROFILE_RMP_DR + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_TOTAL_NUM_BITS 43 + +/** + * Bypass operation. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_BYP_LKUP_EN_BITPOS 42 +#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_BYP_LKUP_EN_NUM_BITS 1 + +/** + * Reserved for future use. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_RESERVED_BITPOS 36 +#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_RESERVED_NUM_BITS 6 + +/** + * Bypass operations. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_BYPASS_OP_BITPOS 33 +#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_BYPASS_OP_NUM_BITS 3 +/** + * Bypass operations. (for idx 1 ...) + */ +enum cfa_p70_prof_profile_rmp_dr_byp_bypass_op { + /* cfa is bypassed */ + CFA_P70_PROF_PROFILE_RMP_DR_BYP_BYPASS_OP_BYPASS_CFA = 0, + /* Byass lookup use act_record_ptr from this table. */ + CFA_P70_PROF_PROFILE_RMP_DR_BYP_BYPASS_OP_BYPASS_LKUP = 1, + /* Byass lookup use Partition Default Action Record Pointer Table */ + CFA_P70_PROF_PROFILE_RMP_DR_BYP_BYPASS_OP_BYPASS_DEFAULT = 2, + /* Byass lookup use Partition Error Action Record Pointer Table. */ + CFA_P70_PROF_PROFILE_RMP_DR_BYP_BYPASS_OP_BYPASS_ERROR = 3, + /* set the drop flag. */ + CFA_P70_PROF_PROFILE_RMP_DR_BYP_BYPASS_OP_DROP = 4, +}; + +/** + * action hint used with plact_rec_ptr + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_ACT_HINT_BITPOS 31 +#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_ACT_HINT_NUM_BITS 2 + +/** + * table scope used with pl_act_rec_ptr + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_SCOPE_BITPOS 26 +#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_SCOPE_NUM_BITS 5 + +/** + * Used for BYPASS_LKUP. #CAS_SW_REF Profiler.profile.remap.entry.build + * #CAS_SW_REF Profiler.profile.remap.entry.bypass.cfa #CAS_SW_REF + * Profiler.profile.remap.entry.bypass.lkup #CAS_SW_REF + * Profiler.profile.remap.entry.other + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_ACT_REC_PTR_BITPOS 0 +#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_ACT_REC_PTR_NUM_BITS 26 + +/** + * Total number of bits for PROF_PROFILE_RMP_DR_BYP + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_TOTAL_NUM_BITS 43 + +/** + * VLAN TPID anti-spoofing control. + */ +#define CFA_P70_ACT_VSPT_DR_TX_TPID_AS_CTL_BITPOS 29 +#define CFA_P70_ACT_VSPT_DR_TX_TPID_AS_CTL_NUM_BITS 2 +/** + * VLAN TPID anti-spoofing control. + */ +enum cfa_p70_act_vspt_dr_tx_tpid_as_ctl { + CFA_P70_ACT_VSPT_DR_TX_TPID_IGNORE = 0, + CFA_P70_ACT_VSPT_DR_TX_TPID_DEFAULT = 1, + CFA_P70_ACT_VSPT_DR_TX_TPID_DROP = 2, +}; + +/** + * VLAN allowed TPID bit map. + */ +#define CFA_P70_ACT_VSPT_DR_TX_ALWD_TPID_BITPOS 21 +#define CFA_P70_ACT_VSPT_DR_TX_ALWD_TPID_NUM_BITS 8 + +/** + * VLAN encoded default TPID. + */ +#define CFA_P70_ACT_VSPT_DR_TX_DFLT_TPID_BITPOS 18 +#define CFA_P70_ACT_VSPT_DR_TX_DFLT_TPID_NUM_BITS 3 + +/** + * VLAN PRIority anti-spoofing control. + */ +#define CFA_P70_ACT_VSPT_DR_TX_PRI_AS_CTL_BITPOS 16 +#define CFA_P70_ACT_VSPT_DR_TX_PRI_AS_CTL_NUM_BITS 2 +/** + * VLAN PRIority anti-spoofing control. + */ +enum cfa_p70_act_vspt_dr_tx_pri_as_ctl { + CFA_P70_ACT_VSPT_DR_TX_PRI_IGNORE = 0, + CFA_P70_ACT_VSPT_DR_TX_PRI_DEFAULT = 1, + CFA_P70_ACT_VSPT_DR_TX_PRI_DROP = 2, +}; + +/** + * VLAN allowed PRIority bit map. + */ +#define CFA_P70_ACT_VSPT_DR_TX_ALWD_PRI_BITPOS 8 +#define CFA_P70_ACT_VSPT_DR_TX_ALWD_PRI_NUM_BITS 8 + +/** + * VLAN default PRIority. + */ +#define CFA_P70_ACT_VSPT_DR_TX_DFLT_PRI_BITPOS 5 +#define CFA_P70_ACT_VSPT_DR_TX_DFLT_PRI_NUM_BITS 3 + +/** + * Mirror destination (1..31) or 5'h0=NO_MIRROR #CAS_SW_REF + * Action.CFA.DEST.SVIF.Property.Tables.tx.svif.property.entry + */ +#define CFA_P70_ACT_VSPT_DR_TX_MIR_BITPOS 0 +#define CFA_P70_ACT_VSPT_DR_TX_MIR_NUM_BITS 5 + +/** + * Total number of bits for ACT_VSPT_DR_TX + */ +#define CFA_P70_ACT_VSPT_DR_TX_TOTAL_NUM_BITS 31 + +/** + * Reserved for future use. + */ +#define CFA_P70_ACT_VSPT_DR_RX_RSVD_BITPOS 24 +#define CFA_P70_ACT_VSPT_DR_RX_RSVD_NUM_BITS 7 + +/** + * Output metadata format select. + */ +#define CFA_P70_ACT_VSPT_DR_RX_METAFMT_BITPOS 22 +#define CFA_P70_ACT_VSPT_DR_RX_METAFMT_NUM_BITS 2 +/** + * Output metadata format select. + */ +enum cfa_p70_act_vspt_dr_rx_metafmt { + CFA_P70_ACT_VSPT_DR_RX_METAFMT_ACT_REC_PTR = 0, + CFA_P70_ACT_VSPT_DR_RX_METAFMT_TUNNEL_ID = 1, + CFA_P70_ACT_VSPT_DR_RX_METAFMT_CSTM_HDR_DATA = 2, + CFA_P70_ACT_VSPT_DR_RX_METAFMT_HDR_OFFSETS = 3, +}; + +/** + * Function ID: 4 bit PF and 12 bit VID (VNIC ID) + */ +#define CFA_P70_ACT_VSPT_DR_RX_FID_BITPOS 5 +#define CFA_P70_ACT_VSPT_DR_RX_FID_NUM_BITS 17 + +/** + * Mirror destination (1..31) or 5'h0=NO_MIRROR #CAS_SW_REF + * Action.CFA.DEST.SVIF.Property.Tables.rx.destination.property.entry + */ +#define CFA_P70_ACT_VSPT_DR_RX_MIR_BITPOS 0 +#define CFA_P70_ACT_VSPT_DR_RX_MIR_NUM_BITS 5 + +/** + * Total number of bits for ACT_VSPT_DR_RX + */ +#define CFA_P70_ACT_VSPT_DR_RX_TOTAL_NUM_BITS 31 + +/** + * LAG destination bit map. + */ +#define CFA_P70_ACT_LBT_DR_DST_BMP_BITPOS 0 +#define CFA_P70_ACT_LBT_DR_DST_BMP_NUM_BITS 5 + +/** + * Total number of bits for ACT_LBT_DR + */ +#define CFA_P70_ACT_LBT_DR_TOTAL_NUM_BITS 5 + +/** + * Preserve incoming partition, don't remap (for idx 3 ...) + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_PRSV_PARIF_BITPOS 126 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_PRSV_PARIF_NUM_BITS 1 + +/** + * Partition, replaces parif from input block (for idx 3 ...) + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_PARIF_BITPOS 121 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_PARIF_NUM_BITS 5 + +/** + * Preserve incoming L2_CTXT (for idx 3 ...) + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_PRSV_L2IP_CTXT_BITPOS 120 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_PRSV_L2IP_CTXT_NUM_BITS 1 + +/** + * L2 logical id which may be used in EM and WC Lookups. (for idx 3 ...) + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_CTXT_BITPOS 109 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_CTXT_NUM_BITS 11 + +/** + * Preserve incoming PROF_FUNC (for idx 3 ...) + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_PRSV_PROF_FUNC_BITPOS 108 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_PRSV_PROF_FUNC_NUM_BITS 1 + +/** + * Allow Profile TCAM Lookup Table to be logically partitioned. (for idx + * 3 ...) + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_PROF_FUNC_BITPOS 100 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_PROF_FUNC_NUM_BITS 8 + +/** + * Context operation code. (for idx 3 ...) + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_CTXT_OPCODE_BITPOS 98 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_CTXT_OPCODE_NUM_BITS 2 +/** + * Context operation code. (for idx 3 ...) + */ +enum cfa_p70_prof_l2_ctxt_rmp_dr_ctxt_opcode { + /* def_ctxt_data provides destination */ + CFA_P70_PROF_L2_CTXT_RMP_DR_CTXT_OPCODE_BYPASS_CFA = 0, + /* def_ctxt_data provides act_rec_ptr */ + CFA_P70_PROF_L2_CTXT_RMP_DR_CTXT_OPCODE_BYPASS_LKUP = 1, + /* continue normal flow */ + CFA_P70_PROF_L2_CTXT_RMP_DR_CTXT_OPCODE_NORMAL_FLOW = 2, + /* mark packet for drop */ + CFA_P70_PROF_L2_CTXT_RMP_DR_CTXT_OPCODE_DROP = 3, +}; + +/** + * Enables remap of meta_data from Input block (for idx 3 ...) + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_META_ENB_BITPOS 97 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_META_ENB_NUM_BITS 1 + +/** + * l2ip_meta_prof[2:0] = l2ip_meta[34:32], l2ip_meta_data[31:0] = + * l2ip_meta[31:0] + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_META_BITPOS 62 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_META_NUM_BITS 35 + +/** + * Enables remap of action record pointer from Input block (for idx 1 + * ...) + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_ACT_ENB_BITPOS 61 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_ACT_ENB_NUM_BITS 1 + +/** + * l2ip_act_hint[1:0] = l2ip_act_data[32:31], l2ip_act_scope[4:0] = + * l2ip_act_data[30:26], l2ip_act_rec_ptr[25:0] = l2ip_act_data[25:0] + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_ACT_DATA_BITPOS 28 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_ACT_DATA_NUM_BITS 33 + +/** + * Enables remap of ring_table_idx + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_RFS_ENB_BITPOS 27 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_RFS_ENB_NUM_BITS 1 + +/** + * ring_table_idx[8:0] = l2ip_rfs_data[8:0] (rx only) + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_RFS_DATA_BITPOS 18 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_RFS_DATA_NUM_BITS 9 + +/** + * Enables remap of destination from input block + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_DEST_ENB_BITPOS 17 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_DEST_ENB_NUM_BITS 1 + +/** + * destination[16:0] = l2ip_dest_data[16:0] #CAS_SW_REF + * Profiler.l2ip.context.remap.table + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_DEST_DATA_BITPOS 0 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_DEST_DATA_NUM_BITS 17 + +/** + * Total number of bits for PROF_L2_CTXT_RMP_DR + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_TOTAL_NUM_BITS 127 + +/** + * FC TCAM Search Result. + */ +#define CFA_P70_ACT_FC_TCAM_RESULT_SEARCH_RESULT_BITPOS 0 +#define CFA_P70_ACT_FC_TCAM_RESULT_SEARCH_RESULT_NUM_BITS 6 + +/** + * Unused Field. + */ +#define CFA_P70_ACT_FC_TCAM_RESULT_UNUSED_0_BITPOS 6 +#define CFA_P70_ACT_FC_TCAM_RESULT_UNUSED_0_NUM_BITS 25 + +/** + * FC TCAM Search Hit. + */ +#define CFA_P70_ACT_FC_TCAM_RESULT_SEARCH_HIT_BITPOS 31 +#define CFA_P70_ACT_FC_TCAM_RESULT_SEARCH_HIT_NUM_BITS 1 + +/** + * Total number of bits for ACT_FC_TCAM_RESULT + */ +#define CFA_P70_ACT_FC_TCAM_RESULT_TOTAL_NUM_BITS 32 + +/** + * Unused Field. + */ +#define CFA_P70_ACT_MIRROR_UNUSED_0_BITPOS 0 +#define CFA_P70_ACT_MIRROR_UNUSED_0_NUM_BITS 21 +#define CFA_P70_ACT_MIRROR_RELATIVE_BITPOS 21 +#define CFA_P70_ACT_MIRROR_RELATIVE_NUM_BITS 1 +/** + * RELATIVE + */ +enum cfa_p70_act_mirror_relative { + /* act_rec_ptr field is absolute. */ + CFA_P70_ACT_MIRROR_RELATIVE_ABSOLUTE = 0, + /* + * act_rec_ptr field is relative to the original action record pointer. + */ + CFA_P70_ACT_MIRROR_RELATIVE_RELATIVE = 1, +}; + +/** + * micr1_act_hint[1:0] - action hint used with act_rec_ptr. + */ +#define CFA_P70_ACT_MIRROR_HINT_BITPOS 22 +#define CFA_P70_ACT_MIRROR_HINT_NUM_BITS 2 + +/** + * Sampling mode. + */ +#define CFA_P70_ACT_MIRROR_SAMP_BITPOS 24 +#define CFA_P70_ACT_MIRROR_SAMP_NUM_BITS 2 +/** + * Sampling mode. + */ +enum cfa_p70_act_mirror_samp { + /* PRNG based. */ + CFA_P70_ACT_MIRROR_SAMP_STAT = 0, + /* packet count based. */ + CFA_P70_ACT_MIRROR_SAMP_PACKET = 1, + /* packet count w/jitter based. */ + CFA_P70_ACT_MIRROR_SAMP_JITTER = 2, + /* timer based. */ + CFA_P70_ACT_MIRROR_SAMP_TIMER = 3, +}; + +/** + * Truncation mode. + */ +#define CFA_P70_ACT_MIRROR_TRUNC_BITPOS 26 +#define CFA_P70_ACT_MIRROR_TRUNC_NUM_BITS 2 +/** + * Truncation mode. + */ +enum cfa_p70_act_mirror_trunc { + /* No Truncation. */ + CFA_P70_ACT_MIRROR_TRUNC_DISABLED = 0, + /* RFFU. */ + CFA_P70_ACT_MIRROR_TRUNC_RSVD = 1, + /* mirror copy will restrict outermost tunnel payload to 128B. */ + CFA_P70_ACT_MIRROR_TRUNC_B128 = 2, + /* mirror copy will restrict outermost tunnel payload to 256B. */ + CFA_P70_ACT_MIRROR_TRUNC_B256 = 3, +}; +#define CFA_P70_ACT_MIRROR_IGN_DROP_BITPOS 28 +#define CFA_P70_ACT_MIRROR_IGN_DROP_NUM_BITS 1 +/** + * IGN_DROP + */ +enum cfa_p70_act_mirror_ign_drop { + /* + * Honor Drop When set the mirror copy is made regardless if the initial + * action is to drop the packet or not. + */ + CFA_P70_ACT_MIRROR_IGN_DROP_HONOR = 0, + /* Ignore Drop */ + CFA_P70_ACT_MIRROR_IGN_DROP_IGNORE = 1, +}; +#define CFA_P70_ACT_MIRROR_MODE_BITPOS 29 +#define CFA_P70_ACT_MIRROR_MODE_NUM_BITS 2 +/** + * MODE + */ +enum cfa_p70_act_mirror_mode { + /* No Copy. */ + CFA_P70_ACT_MIRROR_MODE_DISABLED = 0, + /* Override AR. */ + CFA_P70_ACT_MIRROR_MODE_OVERRIDE = 1, + /* Ingress Copy. */ + CFA_P70_ACT_MIRROR_MODE_INGRESS = 2, + /* Egress Copy. */ + CFA_P70_ACT_MIRROR_MODE_EGRESS = 3, +}; +#define CFA_P70_ACT_MIRROR_COND_BITPOS 31 +#define CFA_P70_ACT_MIRROR_COND_NUM_BITS 1 +/** + * COND + */ +enum cfa_p70_act_mirror_cond { + /* mirror is only processed if Lookup copy bit is set */ + CFA_P70_ACT_MIRROR_COND_UNCONDITIONAL = 0, + /* mirror is processed unconditionally. */ + CFA_P70_ACT_MIRROR_COND_CONDITIONAL = 1, +}; + +/** + * Mirror Destination 1 Action Record Pointer. + */ +#define CFA_P70_ACT_MIRROR_AR_PTR_BITPOS 32 +#define CFA_P70_ACT_MIRROR_AR_PTR_NUM_BITS 26 + +/** + * Mirror Destination 1 Sampling Conifiguration. + */ +#define CFA_P70_ACT_MIRROR_SAMP_CFG_BITPOS 64 +#define CFA_P70_ACT_MIRROR_SAMP_CFG_NUM_BITS 32 + +/** + * Total number of bits for ACT_MIRROR + */ +#define CFA_P70_ACT_MIRROR_TOTAL_NUM_BITS 96 + +/** + * This is the new medadata that is merged with the existing packet + * metadata, based on the profile selected by META_PROF. + */ +#define CFA_P70_WC_LREC_METADATA_BITPOS 5 +#define CFA_P70_WC_LREC_METADATA_NUM_BITS 32 + +/** + * Specifies one of 8 metadata profile masks to use when merging the + * input metadata with the LREC metadata for recycling. + */ +#define CFA_P70_WC_LREC_META_PROF_BITPOS 37 +#define CFA_P70_WC_LREC_META_PROF_NUM_BITS 3 + +/** + * When a packet is recycled to the Profile TCAM, this value is used as + * the PROF_FUNC field in the TCAM search. + */ +#define CFA_P70_WC_LREC_PROF_FUNC_BITPOS 40 +#define CFA_P70_WC_LREC_PROF_FUNC_NUM_BITS 8 + +/** + * Indicates whether the packet will be recycled to the L2 Context TCAM, + * the Profile TCAM. When to the Profile TCAM, PROF_FUNC is used for the + * search key. + */ +#define CFA_P70_WC_LREC_RECYCLE_DEST_BITPOS 48 +#define CFA_P70_WC_LREC_RECYCLE_DEST_NUM_BITS 1 + +/** + * Flow counter pointer. + */ +#define CFA_P70_WC_LREC_FC_PTR_BITPOS 0 +#define CFA_P70_WC_LREC_FC_PTR_NUM_BITS 28 + +/** + * Flow counter type. + */ +#define CFA_P70_WC_LREC_FC_TYPE_BITPOS 28 +#define CFA_P70_WC_LREC_FC_TYPE_NUM_BITS 2 + +/** + * Flow counter op. + */ +#define CFA_P70_WC_LREC_FC_OP_BITPOS 30 +#define CFA_P70_WC_LREC_FC_OP_NUM_BITS 1 +/** + * Enumeration definition for field 'fc_op' + */ +enum cfa_p70_wc_lrec_fc_op { + /* ingress */ + CFA_P70_WC_LREC_FC_OP_INGRESS = 0, + /* egress */ + CFA_P70_WC_LREC_FC_OP_EGRESS = 1, +}; + +/** + * When not present, a value of 0 is used which disables ECMP. The final + * action record location is: ! ACT_REC_PTR += (ECMP_HASH % PATHS_M1 + + * 1)) * ACT_REC_SIZE + */ +#define CFA_P70_WC_LREC_PATHS_M1_BITPOS 31 +#define CFA_P70_WC_LREC_PATHS_M1_NUM_BITS 4 + +/** + * Specifies the size in 32B units of the action memory allocated for + * each ECMP path. + */ +#define CFA_P70_WC_LREC_ACT_REC_SIZE_BITPOS 35 +#define CFA_P70_WC_LREC_ACT_REC_SIZE_NUM_BITS 5 + +/** + * This field is used in flow steering applications such as Linux RFS. + * This field is used in conjunction with the VNIC destination in the + * action record on RX to steer the packet to a specific ring. + */ +#define CFA_P70_WC_LREC_RING_TABLE_IDX_BITPOS 40 +#define CFA_P70_WC_LREC_RING_TABLE_IDX_NUM_BITS 9 + +/** + * This field provides a destination for the packet, which goes directly + * to the output of CFA. + */ +#define CFA_P70_WC_LREC_DESTINATION_BITPOS 49 +#define CFA_P70_WC_LREC_DESTINATION_NUM_BITS 17 + +/** + * This is the action record pointer. This value points into the current + * scope action table. Not that when ACT_REC_SIZE and PATHS_M1 are + * preset and PATHS_M1 != 0, the value may be modified using this as the + * base pointer for ECMP. + */ +#define CFA_P70_WC_LREC_ACT_REC_PTR_BITPOS 49 +#define CFA_P70_WC_LREC_ACT_REC_PTR_NUM_BITS 26 + +/** + * This value provides a hit of the action record size to the Action + * block. + */ +#define CFA_P70_WC_LREC_ACT_HINT_BITPOS 75 +#define CFA_P70_WC_LREC_ACT_HINT_NUM_BITS 2 + +/** + * When both WC and EM have a hit, the one with the higher STRENGTH is + * used. If the STRENGTHs are equal, the LKUP_TIE_BREAKER register bit + * determines the winner. (0=WC, 1=EM) + */ +#define CFA_P70_WC_LREC_STRENGTH_BITPOS 77 +#define CFA_P70_WC_LREC_STRENGTH_NUM_BITS 2 + +/** + * This field defines the format for the LREC and the basic thing that + * will be done with the packet. + */ +#define CFA_P70_WC_LREC_OPCODE_BITPOS 79 +#define CFA_P70_WC_LREC_OPCODE_NUM_BITS 4 +/** + * Enumeration definition for field 'opcode' + */ +enum cfa_p70_wc_lrec_opcode { + /* + * This value means the packet will go to the action block for edit + * processing and that no RFS will be specified for the packet. + */ + CFA_P70_WC_LREC_OPCODE_NORMAL = 0, + /* + * This value means the packet will go to the action block for edit + * processing and that RFS will be specified for the packet. + */ + CFA_P70_WC_LREC_OPCODE_NORMAL_RFS = 1, + /* + * This value means the packet will go directly to the output, bypassing + * the action block and that no RFS will be specified for the packet. + */ + CFA_P70_WC_LREC_OPCODE_FAST = 2, + /* + * This value means the packet will go directly to the output, bypassing + * the action block and that RFS will be specified for the packet. + */ + CFA_P70_WC_LREC_OPCODE_FAST_RFS = 3, + /* + * This value Recycles the packet to the Profiler and provides LREC + * fields that determine the fields returned to the Profiler for further + * processing. + */ + CFA_P70_WC_LREC_OPCODE_RECYCLE = 8, +}; + +/** + * In addition to requiring VALID=1, the bits indexed by epoch1 must be + * set to '1' in the EPOCH1_MASK table, or the LREC is invalid. This is + * used to invalidate rules as a group. + */ +#define CFA_P70_WC_LREC_EPOCH1_BITPOS 83 +#define CFA_P70_WC_LREC_EPOCH1_NUM_BITS 6 + +/** + * In addition to requiring VALID=1, the bits indexed by epoch0 must be + * set to '1' in the EPOCH0_MASK table, or the LREC is invalid. This is + * used to invalidate rules as a group. + */ +#define CFA_P70_WC_LREC_EPOCH0_BITPOS 89 +#define CFA_P70_WC_LREC_EPOCH0_NUM_BITS 12 + +/** + * Record size in 32B words minus 1 (ignored by hardware). + */ +#define CFA_P70_WC_LREC_REC_SIZE_BITPOS 101 +#define CFA_P70_WC_LREC_REC_SIZE_NUM_BITS 2 + +/** + * When set to '0', the LREC is not valid. + */ +#define CFA_P70_WC_LREC_VALID_BITPOS 103 +#define CFA_P70_WC_LREC_VALID_NUM_BITS 1 + +/** + * Total number of bits for wc_lrec + */ +#define CFA_P70_WC_LREC_TOTAL_NUM_BITS 104 + +/** + * This value provides a base pointer to the LKUP_FRC_RANGE memory. Each + * packet can have up to 16 ranges. A value of 16'hFFFF disables FRC. + */ +#define CFA_P70_EM_LREC_RANGE_IDX_BITPOS 0 +#define CFA_P70_EM_LREC_RANGE_IDX_NUM_BITS 16 + +/** + * Selects one of 16 profiles for FRC in the LKUP_RANGE_PROFILE table, + * which specifies 2 packet fields to range check and gives a mask of 16 + * ranges determined by range_index. + */ +#define CFA_P70_EM_LREC_RANGE_PROFILE_BITPOS 16 +#define CFA_P70_EM_LREC_RANGE_PROFILE_NUM_BITS 4 + +/** + * Current timer value for the connection. + */ +#define CFA_P70_EM_LREC_CREC_TIMER_VALUE_BITPOS 20 +#define CFA_P70_EM_LREC_CREC_TIMER_VALUE_NUM_BITS 4 + +/** + * Current state of the connection. + */ +#define CFA_P70_EM_LREC_CREC_STATE_BITPOS 24 +#define CFA_P70_EM_LREC_CREC_STATE_NUM_BITS 5 + +/** + * Set to one by hardware whenever a notify of a valid tcp_msb_opp has + * been written into the connection record. Software can also initialize + * this to one if it initializes tcp_msb_opp to a valid value. + */ +#define CFA_P70_EM_LREC_CREC_TCP_MSB_OPP_INIT_BITPOS 29 +#define CFA_P70_EM_LREC_CREC_TCP_MSB_OPP_INIT_NUM_BITS 1 + +/** + * Bits 31:14 of seq# or ack# as seen in packets on the opposite path. + */ +#define CFA_P70_EM_LREC_CREC_TCP_MSB_OPP_BITPOS 30 +#define CFA_P70_EM_LREC_CREC_TCP_MSB_OPP_NUM_BITS 18 + +/** + * Bits 31:14 of seq# or ack# as seen in packets on the local path. + */ +#define CFA_P70_EM_LREC_CREC_TCP_MSB_LOC_BITPOS 48 +#define CFA_P70_EM_LREC_CREC_TCP_MSB_LOC_NUM_BITS 18 + +/** + * Window size is 1<inner (single shift) */ + CFA_P70_COMPACT_ACTION_DECAP_SHIFT_SINGLE = 14, + /* Un-parse (treat header as payload) */ + CFA_P70_COMPACT_ACTION_DECAP_UNPARSE = 15, + /* Shift outer tunnel->inner (double shift) */ + CFA_P70_COMPACT_ACTION_DECAP_SHIFT_DOUBLE = 18, + /* Decap through Outer Tunnel L2 header */ + CFA_P70_COMPACT_ACTION_DECAP_TO_OL2 = 20, + /* Decap through Outer Tunnel L3 header */ + CFA_P70_COMPACT_ACTION_DECAP_TO_OL3 = 21, + /* Decap through Outer Tunnel L4 header */ + CFA_P70_COMPACT_ACTION_DECAP_TO_OL4 = 22, + /* Decap through Outer Tunnel header */ + CFA_P70_COMPACT_ACTION_DECAP_TO_OT = 23, +}; + +/** + * The mirroring value selects one of 31 mirror destinations for the + * packet. A value of zero means that there is not Action Record + * mirroring for the packet. + */ +#define CFA_P70_COMPACT_ACTION_MIRRORING_BITPOS 24 +#define CFA_P70_COMPACT_ACTION_MIRRORING_NUM_BITS 5 + +/** + * This value points to one of the 1024 meter entries. If the meter has + * scope verification enabled, then the scope in the meter table entry + * must match the scope of this action record. + */ +#define CFA_P70_COMPACT_ACTION_METER_PTR_BITPOS 29 +#define CFA_P70_COMPACT_ACTION_METER_PTR_NUM_BITS 10 + +/** + * This is the offset to the statistic structure in 8B units from the + * start of the Action Record. A value of zero will disable the + * statistics action. + */ +#define CFA_P70_COMPACT_ACTION_STAT0_OFF_BITPOS 39 +#define CFA_P70_COMPACT_ACTION_STAT0_OFF_NUM_BITS 3 + +/** + * This value controls the packet size that is used for counted stats. + */ +#define CFA_P70_COMPACT_ACTION_STAT0_OP_BITPOS 42 +#define CFA_P70_COMPACT_ACTION_STAT0_OP_NUM_BITS 1 +/** + * Enumeration definition for field 'stat0_op' + */ +enum cfa_p70_compact_action_stat0_op { + /* Statistics count reflects packet at 'ingress' to CFA. */ + CFA_P70_COMPACT_ACTION_STAT0_OP_INGRESS = 0, + /* Statistics count reflects packet at 'egress' from CFA. */ + CFA_P70_COMPACT_ACTION_STAT0_OP_EGRESS = 1, +}; + +/** + * Selects counter type. In all cases, fields are packet little endian + * in the action memory. + */ +#define CFA_P70_COMPACT_ACTION_STAT0_CTR_TYPE_BITPOS 43 +#define CFA_P70_COMPACT_ACTION_STAT0_CTR_TYPE_NUM_BITS 2 +/** + * Enumeration definition for field 'stat0_ctr_type' + */ +enum cfa_p70_compact_action_stat0_ctr_type { + /* Forward packet count(64b)/byte count(64b) */ + CFA_P70_COMPACT_ACTION_STAT0_CTR_TYPE_B16 = 0, + /* + * Forward packet count(64b)/byte count(64b) timestamp(32b) TCP + * Flags(16b) reserved(23b) + */ + CFA_P70_COMPACT_ACTION_STAT0_CTR_TYPE_B24 = 1, + /* + * Forward packet count(64b)/byte count(64b) Meter (drop or red) packet + * count(64b)/byte count(64b) + */ + CFA_P70_COMPACT_ACTION_STAT0_CTR_TYPE_B32A = 2, + /* + * Forward packet count(64b)/byte count(64b) Meter timestamp(32b) TCP + * Flags(16b) reserved(6b) (drop or red) packet count(38b)/byte + * count(42b) + */ + CFA_P70_COMPACT_ACTION_STAT0_CTR_TYPE_B32B = 3, +}; + +/** + * This is an offset to the modification record. This is the offset in + * 8B units from the start of the Action Record to get to dependent + * record data. A value of zero indicates no additional actions. + */ +#define CFA_P70_COMPACT_ACTION_MOD_OFF_BITPOS 45 +#define CFA_P70_COMPACT_ACTION_MOD_OFF_NUM_BITS 5 + +/** + * This is an offset to the encapsulation record. This is the offset in + * 8B units from the start of the Action Record to get to dependent + * record data. A value of zero indicates no additional actions. + */ +#define CFA_P70_COMPACT_ACTION_ENC_OFF_BITPOS 50 +#define CFA_P70_COMPACT_ACTION_ENC_OFF_NUM_BITS 6 + +/** + * This is an offset to the source record. This is the offset in 8B + * units from the start of the Action Record to get to dependent record + * data. A value of zero indicates no additional actions. + */ +#define CFA_P70_COMPACT_ACTION_SRC_OFF_BITPOS 56 +#define CFA_P70_COMPACT_ACTION_SRC_OFF_NUM_BITS 4 +#define CFA_P70_COMPACT_ACTION_UNUSED_0_BITPOS 60 +#define CFA_P70_COMPACT_ACTION_UNUSED_0_NUM_BITS 4 + +/** + * Total number of bits for compact_action + */ +#define CFA_P70_COMPACT_ACTION_TOTAL_NUM_BITS 64 + +/** + * The type field identifies the format of the action record to the + * hardware. + */ +#define CFA_P70_FULL_ACTION_TYPE_BITPOS 0 +#define CFA_P70_FULL_ACTION_TYPE_NUM_BITS 3 +/** + * Enumeration definition for field 'type' + */ +enum cfa_p70_full_action_type { + /* + * Full Action Record. The full action record uses full pointers to + * access needed data. It also allows access to all the action features. + * The Full Action record is 192b. + */ + CFA_P70_FULL_ACTION_TYPE_FULL_ACTION = 1, +}; + +/** + * When this value is '1', the packet will be dropped. + */ +#define CFA_P70_FULL_ACTION_DROP_BITPOS 3 +#define CFA_P70_FULL_ACTION_DROP_NUM_BITS 1 + +/** + * This value controls how the VLAN Delete/Report edit works. + */ +#define CFA_P70_FULL_ACTION_VLAN_DELETE_BITPOS 4 +#define CFA_P70_FULL_ACTION_VLAN_DELETE_NUM_BITS 2 +/** + * Enumeration definition for field 'vlan_delete' + */ +enum cfa_p70_full_action_vlan_delete { + /* The VLAN tag is left alone. */ + CFA_P70_FULL_ACTION_VLAN_DELETE_DISABLED = 0, + /* Strip/Report the outer VLAN tag. Leave the inner VLAN tag. */ + CFA_P70_FULL_ACTION_VLAN_DELETE_OUTER = 1, + /* + * Strip both the outer and inner VLAN tag. Report the inner VLAN tag. + */ + CFA_P70_FULL_ACTION_VLAN_DELETE_BOTH = 2, + /* + * If the outer VID != 0, strip and pass the outer VLAG tag and leave + * the inner VLAN tag. If outer VID == 0, then strip both VLAN tags and + * report the inner VLAN tag. + */ + CFA_P70_FULL_ACTION_VLAN_DELETE_COND = 3, +}; + +/** + * This value specifies the port destination mask for TX path and is the + * index into the VNIC Properties Table for the RX path. + */ +#define CFA_P70_FULL_ACTION_DEST_BITPOS 6 +#define CFA_P70_FULL_ACTION_DEST_NUM_BITS 7 +#define CFA_P70_FULL_ACTION_DEST_OP_BITPOS 17 +#define CFA_P70_FULL_ACTION_DEST_OP_NUM_BITS 2 +/** + * Enumeration definition for field 'dest_op' + */ +enum cfa_p70_full_action_dest_op { + /* Use the dest field from the Action Record. */ + CFA_P70_FULL_ACTION_DEST_OP_NORMAL = 0, + /* + * This value specifies that the default destination as determined by + * the Profiler/Lookup/MCG stages and passed into the Action Record + * Fetch should be used instead of the destination from the Action + * Record. For example this can be useful for applications where actions + * are desired on a packet but the destination is to be taken solely + * from the Profiler Input Lookup Table. + */ + CFA_P70_FULL_ACTION_DEST_OP_DEFAULT = 1, + /* + * This value specifies that the lower order bits of the metadata should + * be used instead of the destination from the Action Record. + */ + CFA_P70_FULL_ACTION_DEST_OP_METADATA = 2, +}; + +/** + * This field controls the decapsulation function for the action. + */ +#define CFA_P70_FULL_ACTION_DECAP_BITPOS 19 +#define CFA_P70_FULL_ACTION_DECAP_NUM_BITS 5 +/** + * Enumeration definition for field 'decap' + */ +enum cfa_p70_full_action_decap { + /* Do nothing. */ + CFA_P70_FULL_ACTION_DECAP_DISABLE = 0, + /* Decap the outer VLAN tag */ + CFA_P70_FULL_ACTION_DECAP_OVLAN = 1, + /* Decap all the VLAN tags */ + CFA_P70_FULL_ACTION_DECAP_ALL_VLAN = 2, + /* Decap through Tunnel L2 header */ + CFA_P70_FULL_ACTION_DECAP_TO_TL2 = 3, + /* Decap 1 MPLS label (does not delete outer L2) */ + CFA_P70_FULL_ACTION_DECAP_1MPLS = 4, + /* Decap 1 MPLS label and outer L2 */ + CFA_P70_FULL_ACTION_DECAP_1MPLS_OL2 = 5, + /* Decap 2 MPLS labels (does not delete outer L2) */ + CFA_P70_FULL_ACTION_DECAP_2MPLS = 6, + /* Decap 2 MPLS labels and outer L2 */ + CFA_P70_FULL_ACTION_DECAP_2MPLS_OL2 = 7, + /* Decap through Tunnel L3 header */ + CFA_P70_FULL_ACTION_DECAP_TO_TL3 = 8, + /* Decap through Tunnel L4 header */ + CFA_P70_FULL_ACTION_DECAP_TO_TL4 = 9, + /* Decap through Tunnel header */ + CFA_P70_FULL_ACTION_DECAP_TO_T = 10, + /* Decap through Inner L2 */ + CFA_P70_FULL_ACTION_DECAP_TO_L2 = 11, + /* Decap through Inner L3 */ + CFA_P70_FULL_ACTION_DECAP_TO_L3 = 12, + /* Decap through inner L4 */ + CFA_P70_FULL_ACTION_DECAP_TO_L4 = 13, + /* Shift tunnel->inner (single shift) */ + CFA_P70_FULL_ACTION_DECAP_SHIFT_SINGLE = 14, + /* Un-parse (treat header as payload) */ + CFA_P70_FULL_ACTION_DECAP_UNPARSE = 15, + /* Shift outer tunnel->inner (double shift) */ + CFA_P70_FULL_ACTION_DECAP_SHIFT_DOUBLE = 18, + /* Decap through Outer Tunnel L2 header */ + CFA_P70_FULL_ACTION_DECAP_TO_OL2 = 20, + /* Decap through Outer Tunnel L3 header */ + CFA_P70_FULL_ACTION_DECAP_TO_OL3 = 21, + /* Decap through Outer Tunnel L4 header */ + CFA_P70_FULL_ACTION_DECAP_TO_OL4 = 22, + /* Decap through Outer Tunnel header */ + CFA_P70_FULL_ACTION_DECAP_TO_OT = 23, +}; + +/** + * The mirroring value selects one of 31 mirror destinations for the + * packet. A value of zero means that there is not Action Record + * mirroring for the packet. + */ +#define CFA_P70_FULL_ACTION_MIRRORING_BITPOS 24 +#define CFA_P70_FULL_ACTION_MIRRORING_NUM_BITS 5 + +/** + * This value points to one of the 1024 meter entries. If the meter has + * scope verification enabled, then the scope in the meter table entry + * must match the scope of this action record. + */ +#define CFA_P70_FULL_ACTION_METER_PTR_BITPOS 29 +#define CFA_P70_FULL_ACTION_METER_PTR_NUM_BITS 10 + +/** + * This is the pointer to the statistic structure in 8B units A value of + * zero will disable the statistics action. + */ +#define CFA_P70_FULL_ACTION_STAT0_PTR_BITPOS 39 +#define CFA_P70_FULL_ACTION_STAT0_PTR_NUM_BITS 28 + +/** + * This value controls the packet size that is used for counted stats. + */ +#define CFA_P70_FULL_ACTION_STAT0_OP_BITPOS 67 +#define CFA_P70_FULL_ACTION_STAT0_OP_NUM_BITS 1 +/** + * Enumeration definition for field 'stat0_op' + */ +enum cfa_p70_full_action_stat0_op { + /* Statistics count reflects packet at 'ingress' to CFA. */ + CFA_P70_FULL_ACTION_STAT0_OP_INGRESS = 0, + /* Statistics count reflects packet at 'egress' from CFA. */ + CFA_P70_FULL_ACTION_STAT0_OP_EGRESS = 1, +}; + +/** + * Selects counter type. In all cases, fields are packet little endian + * in the action memory. + */ +#define CFA_P70_FULL_ACTION_STAT0_CTR_TYPE_BITPOS 68 +#define CFA_P70_FULL_ACTION_STAT0_CTR_TYPE_NUM_BITS 2 +/** + * Enumeration definition for field 'stat0_ctr_type' + */ +enum cfa_p70_full_action_stat0_ctr_type { + /* Forward packet count(64b)/byte count(64b) */ + CFA_P70_FULL_ACTION_STAT0_CTR_TYPE_B16 = 0, + /* + * Forward packet count(64b)/byte count(64b) timestamp(32b) TCP + * Flags(16b) reserved(23b) + */ + CFA_P70_FULL_ACTION_STAT0_CTR_TYPE_B24 = 1, + /* + * Forward packet count(64b)/byte count(64b) Meter (drop or red) packet + * count(64b)/byte count(64b) + */ + CFA_P70_FULL_ACTION_STAT0_CTR_TYPE_B32A = 2, + /* + * Forward packet count(64b)/byte count(64b) Meter timestamp(32b) TCP + * Flags(16b) reserved(6b) (drop or red) packet count(38b)/byte + * count(42b) + */ + CFA_P70_FULL_ACTION_STAT0_CTR_TYPE_B32B = 3, +}; + +/** + * This is the pointer to the statistic structure in 8B units A value of + * zero will disable the statistics action. + */ +#define CFA_P70_FULL_ACTION_STAT1_PTR_BITPOS 70 +#define CFA_P70_FULL_ACTION_STAT1_PTR_NUM_BITS 28 + +/** + * This value controls the packet size that is used for counted stats. + */ +#define CFA_P70_FULL_ACTION_STAT1_OP_BITPOS 98 +#define CFA_P70_FULL_ACTION_STAT1_OP_NUM_BITS 1 +/** + * Enumeration definition for field 'stat1_op' + */ +enum cfa_p70_full_action_stat1_op { + /* Statistics count reflects packet at 'ingress' to CFA. */ + CFA_P70_FULL_ACTION_STAT1_OP_INGRESS = 0, + /* Statistics count reflects packet at 'egress' from CFA. */ + CFA_P70_FULL_ACTION_STAT1_OP_EGRESS = 1, +}; + +/** + * Selects counter type. In all cases, fields are packet little endian + * in the action memory. + */ +#define CFA_P70_FULL_ACTION_STAT1_CTR_TYPE_BITPOS 99 +#define CFA_P70_FULL_ACTION_STAT1_CTR_TYPE_NUM_BITS 2 +/** + * Enumeration definition for field 'stat1_ctr_type' + */ +enum cfa_p70_full_action_stat1_ctr_type { + /* Forward packet count(64b)/byte count(64b) */ + CFA_P70_FULL_ACTION_STAT1_CTR_TYPE_B16 = 0, + /* + * Forward packet count(64b)/byte count(64b) timestamp(32b) TCP + * Flags(16b) reserved(23b) + */ + CFA_P70_FULL_ACTION_STAT1_CTR_TYPE_B24 = 1, + /* + * Forward packet count(64b)/byte count(64b) Meter (drop or red) packet + * count(64b)/byte count(64b) + */ + CFA_P70_FULL_ACTION_STAT1_CTR_TYPE_B32A = 2, + /* + * Forward packet count(64b)/byte count(64b) Meter timestamp(32b) TCP + * Flags(16b) reserved(6b) (drop or red) packet count(38b)/byte + * count(42b) + */ + CFA_P70_FULL_ACTION_STAT1_CTR_TYPE_B32B = 3, +}; + +/** + * This is a pointer to the modification record. This is a pointer in 8B + * units directly to dependent record data. A value of zero indicates no + * additional actions. + */ +#define CFA_P70_FULL_ACTION_MOD_PTR_BITPOS 101 +#define CFA_P70_FULL_ACTION_MOD_PTR_NUM_BITS 28 + +/** + * This is a pointer to the encapsulation record. This is a pointer in + * 8B units directly to dependent record data. A value of zero indicates + * no additional actions. + */ +#define CFA_P70_FULL_ACTION_ENC_PTR_BITPOS 129 +#define CFA_P70_FULL_ACTION_ENC_PTR_NUM_BITS 28 + +/** + * This is a pointer to the source record. This is a pointer in 8B units + * directly to dependent record data. A value of zero indicates no + * additional actions. + */ +#define CFA_P70_FULL_ACTION_SRC_PTR_BITPOS 157 +#define CFA_P70_FULL_ACTION_SRC_PTR_NUM_BITS 28 +#define CFA_P70_FULL_ACTION_UNUSED_0_BITPOS 185 +#define CFA_P70_FULL_ACTION_UNUSED_0_NUM_BITS 7 + +/** + * Total number of bits for full_action + */ +#define CFA_P70_FULL_ACTION_TOTAL_NUM_BITS 192 + +/** + * The type field identifies the format of the action record to the + * hardware. + */ +#define CFA_P70_MCG_ACTION_TYPE_BITPOS 0 +#define CFA_P70_MCG_ACTION_TYPE_NUM_BITS 3 +/** + * Enumeration definition for field 'type' + */ +enum cfa_p70_mcg_action_type { + /* + * Multicast Group Action Record. This action is used to send the packet + * to multiple destinations. The MGC Action record is 256b. + */ + CFA_P70_MCG_ACTION_TYPE_MCG_ACTION = 4, +}; + +/** + * When this bit is set to '1', source knockout will be supported for + * the MCG record. This value also applies to any chained subsequent MCG + * records. This is applied on the RX CFA only. + */ +#define CFA_P70_MCG_ACTION_SRC_KO_EN_BITPOS 3 +#define CFA_P70_MCG_ACTION_SRC_KO_EN_NUM_BITS 1 +#define CFA_P70_MCG_ACTION_UNUSED_0_BITPOS 4 +#define CFA_P70_MCG_ACTION_UNUSED_0_NUM_BITS 2 + +/** + * This is a pointer to the next MGC Subsequent Entries Record. The + * Subsequent Entries MGC record must be on a 32B boundary. A value of + * zero indicates that there are not additional MGC Subsequent Entries + * record. + */ +#define CFA_P70_MCG_ACTION_NEXT_PTR_BITPOS 6 +#define CFA_P70_MCG_ACTION_NEXT_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_ACTION_PTR0_ACT_HINT_BITPOS 32 +#define CFA_P70_MCG_ACTION_PTR0_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_ACTION_PTR0_ACT_REC_PTR_BITPOS 34 +#define CFA_P70_MCG_ACTION_PTR0_ACT_REC_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_ACTION_PTR1_ACT_HINT_BITPOS 60 +#define CFA_P70_MCG_ACTION_PTR1_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_ACTION_PTR1_ACT_REC_PTR_BITPOS 62 +#define CFA_P70_MCG_ACTION_PTR1_ACT_REC_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_ACTION_PTR2_ACT_HINT_BITPOS 88 +#define CFA_P70_MCG_ACTION_PTR2_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_ACTION_PTR2_ACT_REC_PTR_BITPOS 90 +#define CFA_P70_MCG_ACTION_PTR2_ACT_REC_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_ACTION_PTR3_ACT_HINT_BITPOS 116 +#define CFA_P70_MCG_ACTION_PTR3_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_ACTION_PTR3_ACT_REC_PTR_BITPOS 118 +#define CFA_P70_MCG_ACTION_PTR3_ACT_REC_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_ACTION_PTR4_ACT_HINT_BITPOS 144 +#define CFA_P70_MCG_ACTION_PTR4_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_ACTION_PTR4_ACT_REC_PTR_BITPOS 146 +#define CFA_P70_MCG_ACTION_PTR4_ACT_REC_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_ACTION_PTR5_ACT_HINT_BITPOS 172 +#define CFA_P70_MCG_ACTION_PTR5_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_ACTION_PTR5_ACT_REC_PTR_BITPOS 174 +#define CFA_P70_MCG_ACTION_PTR5_ACT_REC_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_ACTION_PTR6_ACT_HINT_BITPOS 200 +#define CFA_P70_MCG_ACTION_PTR6_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_ACTION_PTR6_ACT_REC_PTR_BITPOS 202 +#define CFA_P70_MCG_ACTION_PTR6_ACT_REC_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_ACTION_PTR7_ACT_HINT_BITPOS 228 +#define CFA_P70_MCG_ACTION_PTR7_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_ACTION_PTR7_ACT_REC_PTR_BITPOS 230 +#define CFA_P70_MCG_ACTION_PTR7_ACT_REC_PTR_NUM_BITS 26 + +/** + * Total number of bits for mcg_action + */ +#define CFA_P70_MCG_ACTION_TOTAL_NUM_BITS 256 + +/** + * The type field identifies the format of the action record to the + * hardware. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_TYPE_BITPOS 0 +#define CFA_P70_MCG_SUBSEQ_ACTION_TYPE_NUM_BITS 3 +/** + * Enumeration definition for field 'type' + */ +enum cfa_p70_mcg_subseq_action_type { + /* + * Multicast Group Action Record. This action is used to send the packet + * to multiple destinations. The MGC Action record is 256b. + */ + CFA_P70_MCG_SUBSEQ_ACTION_TYPE_MCG_ACTION = 4, +}; +#define CFA_P70_MCG_SUBSEQ_ACTION_UNUSED_0_BITPOS 3 +#define CFA_P70_MCG_SUBSEQ_ACTION_UNUSED_0_NUM_BITS 3 + +/** + * This is a pointer to the next MGC Subsequent Entries Record. The + * Subsequent Entries MGC record must be on a 32B boundary. A value of + * zero indicates that there are not additional MGC Subsequent Entries + * record. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_NEXT_PTR_BITPOS 6 +#define CFA_P70_MCG_SUBSEQ_ACTION_NEXT_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR0_ACT_HINT_BITPOS 32 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR0_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR0_ACT_REC_PTR_BITPOS 34 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR0_ACT_REC_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR1_ACT_HINT_BITPOS 60 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR1_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR1_ACT_REC_PTR_BITPOS 62 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR1_ACT_REC_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR2_ACT_HINT_BITPOS 88 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR2_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR2_ACT_REC_PTR_BITPOS 90 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR2_ACT_REC_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR3_ACT_HINT_BITPOS 116 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR3_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR3_ACT_REC_PTR_BITPOS 118 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR3_ACT_REC_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR4_ACT_HINT_BITPOS 144 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR4_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR4_ACT_REC_PTR_BITPOS 146 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR4_ACT_REC_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR5_ACT_HINT_BITPOS 172 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR5_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR5_ACT_REC_PTR_BITPOS 174 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR5_ACT_REC_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR6_ACT_HINT_BITPOS 200 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR6_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR6_ACT_REC_PTR_BITPOS 202 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR6_ACT_REC_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR7_ACT_HINT_BITPOS 228 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR7_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR7_ACT_REC_PTR_BITPOS 230 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR7_ACT_REC_PTR_NUM_BITS 26 + +/** + * Total number of bits for mcg_subseq_action + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_TOTAL_NUM_BITS 256 + +/** + * Current committed token bucket count. + */ +#define CFA_P70_METERS_BKT_C_BITPOS 0 +#define CFA_P70_METERS_BKT_C_NUM_BITS 27 + +/** + * Current excess token bucket count. + */ +#define CFA_P70_METERS_BKT_E_BITPOS 27 +#define CFA_P70_METERS_BKT_E_NUM_BITS 27 + +/** + * Meter Valid + */ +#define CFA_P70_METERS_FLAGS_MTR_VAL_BITPOS 54 +#define CFA_P70_METERS_FLAGS_MTR_VAL_NUM_BITS 1 + +/** + * ECN Remap Enable + */ +#define CFA_P70_METERS_FLAGS_ECN_RMP_EN_BITPOS 55 +#define CFA_P70_METERS_FLAGS_ECN_RMP_EN_NUM_BITS 1 + +/** + * Coupling Flag. Indicates that tokens being added to the committed + * bucket should be diverted to the excess bucket when the committed + * bucket is full. This bit is ignored when RFC2698=1 + */ +#define CFA_P70_METERS_FLAGS_CF_BITPOS 56 +#define CFA_P70_METERS_FLAGS_CF_NUM_BITS 1 + +/** + * Packet Mode. When set packet length is ignored and a global value is + * used instead. + */ +#define CFA_P70_METERS_FLAGS_PM_BITPOS 57 +#define CFA_P70_METERS_FLAGS_PM_NUM_BITS 1 + +/** + * RFC2698 Enable - Indicates if BOTH buckets must have sufficient + * tokens to color a packet green per RFC2698, as opposed to just the + * committed bucket. + */ +#define CFA_P70_METERS_FLAGS_RFC2698_BITPOS 58 +#define CFA_P70_METERS_FLAGS_RFC2698_NUM_BITS 1 + +/** + * Committed Bucket Strict Mode. If set, a packet conforms to the + * committed bucket only if the number of tokens is greater than or + * equal to the packet length. When not set meter conformance is + * independent of packet size and requires only that the token count is + * non-negative. + */ +#define CFA_P70_METERS_FLAGS_CBSM_BITPOS 59 +#define CFA_P70_METERS_FLAGS_CBSM_NUM_BITS 1 + +/** + * Excess Bucket Strict Mode. If set, a packet conforms to the excess + * bucket only if the number of tokens is greater than or equal to the + * packet length. When not set, meter conformance is independent of + * packet size and requires only that the token count is non-negative. + */ +#define CFA_P70_METERS_FLAGS_EBSM_BITPOS 60 +#define CFA_P70_METERS_FLAGS_EBSM_NUM_BITS 1 + +/** + * Committed Bucket No Decrement. If set, tokens are never decremented + * from the committed bucket, even when the packet is Green. + */ +#define CFA_P70_METERS_FLAGS_CBND_BITPOS 61 +#define CFA_P70_METERS_FLAGS_CBND_NUM_BITS 1 + +/** + * Excess Bucket No Decrement. If set, tokens are never decremented from + * the excess bucket, even when the packet is Green. + */ +#define CFA_P70_METERS_FLAGS_EBND_BITPOS 62 +#define CFA_P70_METERS_FLAGS_EBND_NUM_BITS 1 + +/** + * Committed Burst Size. Expressed in bytes in a normalized floating + * point format. + */ +#define CFA_P70_METERS_CBS_BITPOS 63 +#define CFA_P70_METERS_CBS_NUM_BITS 12 + +/** + * Excess Burst Size. Expressed in bytes in a normalized floating point + * format. + */ +#define CFA_P70_METERS_EBS_BITPOS 75 +#define CFA_P70_METERS_EBS_NUM_BITS 12 + +/** + * Committed Information Rate. A rate expressed in bytes per clock cycle + * in a normalized floating point format. + */ +#define CFA_P70_METERS_CIR_BITPOS 87 +#define CFA_P70_METERS_CIR_NUM_BITS 17 + +/** + * Excess Information Rate. A rate expressed in bytes per clock cycle in + * a normalized floating point format. + */ +#define CFA_P70_METERS_EIR_BITPOS 104 +#define CFA_P70_METERS_EIR_NUM_BITS 17 + +/** + * This is the scope whose action records will be allowed to reference + * this meter if the enable bit is '1'. + */ +#define CFA_P70_METERS_PROTECTION_SCOPE_BITPOS 121 +#define CFA_P70_METERS_PROTECTION_SCOPE_NUM_BITS 5 + +/** + * Reserved. + */ +#define CFA_P70_METERS_PROTECTION_RSVD_BITPOS 126 +#define CFA_P70_METERS_PROTECTION_RSVD_NUM_BITS 1 + +/** + * When this bit is '1', the meter will be protected from any scope + * action other than the one in the scope field. + */ +#define CFA_P70_METERS_PROTECTION_ENABLE_BITPOS 127 +#define CFA_P70_METERS_PROTECTION_ENABLE_NUM_BITS 1 + +/** + * Total number of bits for meters + */ +#define CFA_P70_METERS_TOTAL_NUM_BITS 128 + +/** + * Field length definitions for fkb + */ +#define CFA_P70_FKB_PROF_ID_NUM_BITS 8 +#define CFA_P70_FKB_L2CTXT_NUM_BITS 11 +#define CFA_P70_FKB_L2FUNC_NUM_BITS 8 +#define CFA_P70_FKB_PARIF_NUM_BITS 2 +#define CFA_P70_FKB_SPIF_NUM_BITS 2 +#define CFA_P70_FKB_SVIF_NUM_BITS 6 +#define CFA_P70_FKB_LCOS_NUM_BITS 3 +#define CFA_P70_FKB_META_HI_NUM_BITS 16 +#define CFA_P70_FKB_META_LO_NUM_BITS 16 +#define CFA_P70_FKB_RCYC_CNT_NUM_BITS 4 +#define CFA_P70_FKB_LOOPBACK_NUM_BITS 1 +#define CFA_P70_FKB_OTL2_TYPE_NUM_BITS 2 +#define CFA_P70_FKB_OTL2_DMAC_NUM_BITS 48 +#define CFA_P70_FKB_OTL2_SMAC_NUM_BITS 48 +#define CFA_P70_FKB_OTL2_DT_NUM_BITS 2 +#define CFA_P70_FKB_OTL2_SA_NUM_BITS 1 +#define CFA_P70_FKB_OTL2_NVT_NUM_BITS 2 +#define CFA_P70_FKB_OTL2_OVP_NUM_BITS 3 +#define CFA_P70_FKB_OTL2_OVD_NUM_BITS 1 +#define CFA_P70_FKB_OTL2_OVV_NUM_BITS 12 +#define CFA_P70_FKB_OTL2_OVT_NUM_BITS 3 +#define CFA_P70_FKB_OTL2_IVP_NUM_BITS 3 +#define CFA_P70_FKB_OTL2_IVD_NUM_BITS 1 +#define CFA_P70_FKB_OTL2_IVV_NUM_BITS 12 +#define CFA_P70_FKB_OTL2_IVT_NUM_BITS 3 +#define CFA_P70_FKB_OTL2_ETYPE_NUM_BITS 16 +#define CFA_P70_FKB_OTL3_TYPE_NUM_BITS 4 +#define CFA_P70_FKB_OTL3_SIP3_NUM_BITS 32 +#define CFA_P70_FKB_OTL3_SIP2_NUM_BITS 32 +#define CFA_P70_FKB_OTL3_SIP1_NUM_BITS 32 +#define CFA_P70_FKB_OTL3_SIP0_NUM_BITS 32 +#define CFA_P70_FKB_OTL3_DIP3_NUM_BITS 32 +#define CFA_P70_FKB_OTL3_DIP2_NUM_BITS 32 +#define CFA_P70_FKB_OTL3_DIP1_NUM_BITS 32 +#define CFA_P70_FKB_OTL3_DIP0_NUM_BITS 32 +#define CFA_P70_FKB_OTL3_TTL_NUM_BITS 8 +#define CFA_P70_FKB_OTL3_PROT_NUM_BITS 8 +/** + * CFA_P70_FKB_OTL3_FID bit length is not fixed + * So the CFA_P70_FKB_OTL3_FID_NUMBITS macro is defined with arguments + */ +#define CFA_P70_FKB_OTL3_FID_NUM_BITS(COND) ((COND) ? 16 : 20) +#define CFA_P70_FKB_OTL3_QOS_NUM_BITS 8 +#define CFA_P70_FKB_OTL3_IEH_NONEXT_NUM_BITS 1 +#define CFA_P70_FKB_OTL3_IEH_SEP_NUM_BITS 1 +#define CFA_P70_FKB_OTL3_IEH_AUTH_NUM_BITS 1 +#define CFA_P70_FKB_OTL3_IEH_DEST_NUM_BITS 1 +#define CFA_P70_FKB_OTL3_IEH_FRAG_NUM_BITS 1 +#define CFA_P70_FKB_OTL3_IEH_RTHDR_NUM_BITS 1 +#define CFA_P70_FKB_OTL3_IEH_HOP_NUM_BITS 1 +#define CFA_P70_FKB_OTL3_IEH_1FRAG_NUM_BITS 1 +#define CFA_P70_FKB_OTL3_DF_NUM_BITS 1 +#define CFA_P70_FKB_OTL3_L3ERR_NUM_BITS 4 +#define CFA_P70_FKB_OTL4_TYPE_NUM_BITS 4 +#define CFA_P70_FKB_OTL4_SRC_NUM_BITS 16 +#define CFA_P70_FKB_OTL4_DST_NUM_BITS 16 +#define CFA_P70_FKB_OTL4_FLAGS_NUM_BITS 9 +#define CFA_P70_FKB_OTL4_SEQ_NUM_BITS 32 +#define CFA_P70_FKB_OTL4_PA_NUM_BITS 1 +#define CFA_P70_FKB_OTL4_OPT_NUM_BITS 1 +#define CFA_P70_FKB_OTL4_TCPTS_NUM_BITS 1 +#define CFA_P70_FKB_OTL4_ERR_NUM_BITS 4 +#define CFA_P70_FKB_OT_TYPE_NUM_BITS 5 +#define CFA_P70_FKB_OT_FLAGS_NUM_BITS 8 +#define CFA_P70_FKB_OT_IDS_NUM_BITS 24 +#define CFA_P70_FKB_OT_ID_NUM_BITS 32 +#define CFA_P70_FKB_OT_CTXTS_NUM_BITS 24 +#define CFA_P70_FKB_OT_CTXT_NUM_BITS 32 +#define CFA_P70_FKB_OT_QOS_NUM_BITS 3 +#define CFA_P70_FKB_OT_ERR_NUM_BITS 4 +#define CFA_P70_FKB_TL2_TYPE_NUM_BITS 2 +#define CFA_P70_FKB_TL2_DMAC_NUM_BITS 48 +#define CFA_P70_FKB_TL2_SMAC_NUM_BITS 48 +#define CFA_P70_FKB_TL2_DT_NUM_BITS 2 +#define CFA_P70_FKB_TL2_SA_NUM_BITS 1 +#define CFA_P70_FKB_TL2_NVT_NUM_BITS 2 +#define CFA_P70_FKB_TL2_OVP_NUM_BITS 3 +#define CFA_P70_FKB_TL2_OVD_NUM_BITS 1 +#define CFA_P70_FKB_TL2_OVV_NUM_BITS 12 +#define CFA_P70_FKB_TL2_OVT_NUM_BITS 3 +#define CFA_P70_FKB_TL2_IVP_NUM_BITS 3 +#define CFA_P70_FKB_TL2_IVD_NUM_BITS 1 +#define CFA_P70_FKB_TL2_IVV_NUM_BITS 12 +#define CFA_P70_FKB_TL2_IVT_NUM_BITS 3 +#define CFA_P70_FKB_TL2_ETYPE_NUM_BITS 16 +#define CFA_P70_FKB_TL3_TYPE_NUM_BITS 4 +#define CFA_P70_FKB_TL3_SIP3_NUM_BITS 32 +#define CFA_P70_FKB_TL3_SIP2_NUM_BITS 32 +#define CFA_P70_FKB_TL3_SIP1_NUM_BITS 32 +#define CFA_P70_FKB_TL3_SIP0_NUM_BITS 32 +#define CFA_P70_FKB_TL3_DIP3_NUM_BITS 32 +#define CFA_P70_FKB_TL3_DIP2_NUM_BITS 32 +#define CFA_P70_FKB_TL3_DIP1_NUM_BITS 32 +#define CFA_P70_FKB_TL3_DIP0_NUM_BITS 32 +#define CFA_P70_FKB_TL3_TTL_NUM_BITS 8 +#define CFA_P70_FKB_TL3_PROT_NUM_BITS 8 +/** + * CFA_P70_FKB_TL3_FID bit length is not fixed + * So the CFA_P70_FKB_TL3_FID_NUMBITS macro is defined with arguments + */ +#define CFA_P70_FKB_TL3_FID_NUM_BITS(COND) ((COND) ? 16 : 20) +#define CFA_P70_FKB_TL3_QOS_NUM_BITS 8 +#define CFA_P70_FKB_TL3_IEH_NONEXT_NUM_BITS 1 +#define CFA_P70_FKB_TL3_IEH_SEP_NUM_BITS 1 +#define CFA_P70_FKB_TL3_IEH_AUTH_NUM_BITS 1 +#define CFA_P70_FKB_TL3_IEH_DEST_NUM_BITS 1 +#define CFA_P70_FKB_TL3_IEH_FRAG_NUM_BITS 1 +#define CFA_P70_FKB_TL3_IEH_RTHDR_NUM_BITS 1 +#define CFA_P70_FKB_TL3_IEH_HOP_NUM_BITS 1 +#define CFA_P70_FKB_TL3_IEH_1FRAG_NUM_BITS 1 +#define CFA_P70_FKB_TL3_DF_NUM_BITS 1 +#define CFA_P70_FKB_TL3_L3ERR_NUM_BITS 4 +#define CFA_P70_FKB_TL4_TYPE_NUM_BITS 4 +#define CFA_P70_FKB_TL4_SRC_NUM_BITS 16 +#define CFA_P70_FKB_TL4_DST_NUM_BITS 16 +#define CFA_P70_FKB_TL4_FLAGS_NUM_BITS 9 +#define CFA_P70_FKB_TL4_SEQ_NUM_BITS 32 +#define CFA_P70_FKB_TL4_PA_NUM_BITS 1 +#define CFA_P70_FKB_TL4_OPT_NUM_BITS 1 +#define CFA_P70_FKB_TL4_TCPTS_NUM_BITS 1 +#define CFA_P70_FKB_TL4_ERR_NUM_BITS 4 +#define CFA_P70_FKB_T_TYPE_NUM_BITS 5 +#define CFA_P70_FKB_T_FLAGS_NUM_BITS 8 +#define CFA_P70_FKB_T_IDS_NUM_BITS 24 +#define CFA_P70_FKB_T_ID_NUM_BITS 32 +#define CFA_P70_FKB_T_CTXTS_NUM_BITS 24 +#define CFA_P70_FKB_T_CTXT_NUM_BITS 32 +#define CFA_P70_FKB_T_QOS_NUM_BITS 3 +#define CFA_P70_FKB_T_ERR_NUM_BITS 4 +#define CFA_P70_FKB_L2_TYPE_NUM_BITS 2 +#define CFA_P70_FKB_L2_DMAC_NUM_BITS 48 +#define CFA_P70_FKB_L2_SMAC_NUM_BITS 48 +#define CFA_P70_FKB_L2_DT_NUM_BITS 2 +#define CFA_P70_FKB_L2_SA_NUM_BITS 1 +#define CFA_P70_FKB_L2_NVT_NUM_BITS 2 +#define CFA_P70_FKB_L2_OVP_NUM_BITS 3 +#define CFA_P70_FKB_L2_OVD_NUM_BITS 1 +#define CFA_P70_FKB_L2_OVV_NUM_BITS 12 +#define CFA_P70_FKB_L2_OVT_NUM_BITS 3 +#define CFA_P70_FKB_L2_IVP_NUM_BITS 3 +#define CFA_P70_FKB_L2_IVD_NUM_BITS 1 +#define CFA_P70_FKB_L2_IVV_NUM_BITS 12 +#define CFA_P70_FKB_L2_IVT_NUM_BITS 3 +#define CFA_P70_FKB_L2_ETYPE_NUM_BITS 16 +#define CFA_P70_FKB_L3_TYPE_NUM_BITS 4 +#define CFA_P70_FKB_L3_SIP3_NUM_BITS 32 +#define CFA_P70_FKB_L3_SIP2_NUM_BITS 32 +#define CFA_P70_FKB_L3_SIP1_NUM_BITS 32 +#define CFA_P70_FKB_L3_SIP0_NUM_BITS 32 +#define CFA_P70_FKB_L3_DIP3_NUM_BITS 32 +#define CFA_P70_FKB_L3_DIP2_NUM_BITS 32 +#define CFA_P70_FKB_L3_DIP1_NUM_BITS 32 +#define CFA_P70_FKB_L3_DIP0_NUM_BITS 32 +#define CFA_P70_FKB_L3_TTL_NUM_BITS 8 +#define CFA_P70_FKB_L3_PROT_NUM_BITS 8 +/** + * CFA_P70_FKB_L3_FID bit length is not fixed + * So the CFA_P70_FKB_L3_FID_NUMBITS macro is defined with arguments + */ +#define CFA_P70_FKB_L3_FID_NUM_BITS(COND) ((COND) ? 16 : 20) +#define CFA_P70_FKB_L3_QOS_NUM_BITS 8 +#define CFA_P70_FKB_L3_IEH_NONEXT_NUM_BITS 1 +#define CFA_P70_FKB_L3_IEH_SEP_NUM_BITS 1 +#define CFA_P70_FKB_L3_IEH_AUTH_NUM_BITS 1 +#define CFA_P70_FKB_L3_IEH_DEST_NUM_BITS 1 +#define CFA_P70_FKB_L3_IEH_FRAG_NUM_BITS 1 +#define CFA_P70_FKB_L3_IEH_RTHDR_NUM_BITS 1 +#define CFA_P70_FKB_L3_IEH_HOP_NUM_BITS 1 +#define CFA_P70_FKB_L3_IEH_1FRAG_NUM_BITS 1 +#define CFA_P70_FKB_L3_DF_NUM_BITS 1 +#define CFA_P70_FKB_L3_L3ERR_NUM_BITS 4 +#define CFA_P70_FKB_L4_TYPE_NUM_BITS 4 +#define CFA_P70_FKB_L4_SRC_NUM_BITS 16 +#define CFA_P70_FKB_L4_DST_NUM_BITS 16 +#define CFA_P70_FKB_L4_FLAGS_NUM_BITS 9 +#define CFA_P70_FKB_L4_SEQ_NUM_BITS 32 +#define CFA_P70_FKB_L4_ACK_NUM_BITS 32 +#define CFA_P70_FKB_L4_WIN_NUM_BITS 16 +#define CFA_P70_FKB_L4_PA_NUM_BITS 1 +#define CFA_P70_FKB_L4_OPT_NUM_BITS 1 +#define CFA_P70_FKB_L4_TCPTS_NUM_BITS 1 +#define CFA_P70_FKB_L4_TSVAL_NUM_BITS 32 +#define CFA_P70_FKB_L4_TXECR_NUM_BITS 32 +#define CFA_P70_FKB_L4_ERR_NUM_BITS 4 + +/** + * Field length definitions for wc tcam fkb + */ +#define CFA_P70_WC_TCAM_FKB_PROF_ID_NUM_BITS 8 +#define CFA_P70_WC_TCAM_FKB_L2CTXT_NUM_BITS 11 +#define CFA_P70_WC_TCAM_FKB_L2FUNC_NUM_BITS 8 +#define CFA_P70_WC_TCAM_FKB_PARIF_NUM_BITS 2 +#define CFA_P70_WC_TCAM_FKB_SPIF_NUM_BITS 2 +#define CFA_P70_WC_TCAM_FKB_SVIF_NUM_BITS 6 +#define CFA_P70_WC_TCAM_FKB_LCOS_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_META_HI_NUM_BITS 16 +#define CFA_P70_WC_TCAM_FKB_META_LO_NUM_BITS 16 +#define CFA_P70_WC_TCAM_FKB_RCYC_CNT_NUM_BITS 4 +#define CFA_P70_WC_TCAM_FKB_LOOPBACK_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL2_TYPE_NUM_BITS 2 +#define CFA_P70_WC_TCAM_FKB_OTL2_DMAC_NUM_BITS 48 +#define CFA_P70_WC_TCAM_FKB_OTL2_SMAC_NUM_BITS 48 +#define CFA_P70_WC_TCAM_FKB_OTL2_DT_NUM_BITS 2 +#define CFA_P70_WC_TCAM_FKB_OTL2_SA_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL2_NVT_NUM_BITS 2 +#define CFA_P70_WC_TCAM_FKB_OTL2_OVP_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_OTL2_OVD_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL2_OVV_NUM_BITS 12 +#define CFA_P70_WC_TCAM_FKB_OTL2_OVT_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_OTL2_IVP_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_OTL2_IVD_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL2_IVV_NUM_BITS 12 +#define CFA_P70_WC_TCAM_FKB_OTL2_IVT_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_OTL2_ETYPE_NUM_BITS 16 +#define CFA_P70_WC_TCAM_FKB_OTL3_TYPE_NUM_BITS 4 +#define CFA_P70_WC_TCAM_FKB_OTL3_SIP3_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_OTL3_SIP2_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_OTL3_SIP1_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_OTL3_SIP0_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_OTL3_DIP3_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_OTL3_DIP2_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_OTL3_DIP1_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_OTL3_DIP0_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_OTL3_TTL_NUM_BITS 8 +#define CFA_P70_WC_TCAM_FKB_OTL3_PROT_NUM_BITS 8 +/** + * CFA_P70_WC_TCAM_FKB_OTL3_FID bit length is not fixed + * So the CFA_P70_WC_TCAM_FKB_OTL3_FID_NUMBITS macro is defined with arguments + */ +#define CFA_P70_WC_TCAM_FKB_OTL3_FID_NUM_BITS(COND) ((COND) ? 16 : 20) +#define CFA_P70_WC_TCAM_FKB_OTL3_QOS_NUM_BITS 8 +#define CFA_P70_WC_TCAM_FKB_OTL3_IEH_NONEXT_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL3_IEH_SEP_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL3_IEH_AUTH_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL3_IEH_DEST_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL3_IEH_FRAG_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL3_IEH_RTHDR_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL3_IEH_HOP_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL3_IEH_1FRAG_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL3_DF_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL3_L3ERR_NUM_BITS 4 +#define CFA_P70_WC_TCAM_FKB_OTL4_TYPE_NUM_BITS 4 +#define CFA_P70_WC_TCAM_FKB_OTL4_SRC_NUM_BITS 16 +#define CFA_P70_WC_TCAM_FKB_OTL4_DST_NUM_BITS 16 +#define CFA_P70_WC_TCAM_FKB_OTL4_FLAGS_NUM_BITS 9 +#define CFA_P70_WC_TCAM_FKB_OTL4_SEQ_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_OTL4_PA_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL4_OPT_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL4_TCPTS_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL4_ERR_NUM_BITS 4 +#define CFA_P70_WC_TCAM_FKB_OT_TYPE_NUM_BITS 5 +#define CFA_P70_WC_TCAM_FKB_OT_FLAGS_NUM_BITS 8 +#define CFA_P70_WC_TCAM_FKB_OT_IDS_NUM_BITS 24 +#define CFA_P70_WC_TCAM_FKB_OT_ID_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_OT_CTXTS_NUM_BITS 24 +#define CFA_P70_WC_TCAM_FKB_OT_CTXT_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_OT_QOS_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_OT_ERR_NUM_BITS 4 +#define CFA_P70_WC_TCAM_FKB_TL2_TYPE_NUM_BITS 2 +#define CFA_P70_WC_TCAM_FKB_TL2_DMAC_NUM_BITS 48 +#define CFA_P70_WC_TCAM_FKB_TL2_SMAC_NUM_BITS 48 +#define CFA_P70_WC_TCAM_FKB_TL2_DT_NUM_BITS 2 +#define CFA_P70_WC_TCAM_FKB_TL2_SA_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL2_NVT_NUM_BITS 2 +#define CFA_P70_WC_TCAM_FKB_TL2_OVP_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_TL2_OVD_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL2_OVV_NUM_BITS 12 +#define CFA_P70_WC_TCAM_FKB_TL2_OVT_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_TL2_IVP_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_TL2_IVD_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL2_IVV_NUM_BITS 12 +#define CFA_P70_WC_TCAM_FKB_TL2_IVT_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_TL2_ETYPE_NUM_BITS 16 +#define CFA_P70_WC_TCAM_FKB_TL3_TYPE_NUM_BITS 4 +#define CFA_P70_WC_TCAM_FKB_TL3_SIP3_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_TL3_SIP2_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_TL3_SIP1_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_TL3_SIP0_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_TL3_DIP3_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_TL3_DIP2_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_TL3_DIP1_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_TL3_DIP0_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_TL3_TTL_NUM_BITS 8 +#define CFA_P70_WC_TCAM_FKB_TL3_PROT_NUM_BITS 8 +/** + * CFA_P70_WC_TCAM_FKB_TL3_FID bit length is not fixed + * So the CFA_P70_WC_TCAM_FKB_TL3_FID_NUMBITS macro is defined with arguments + */ +#define CFA_P70_WC_TCAM_FKB_TL3_FID_NUM_BITS(COND) ((COND) ? 16 : 20) +#define CFA_P70_WC_TCAM_FKB_TL3_QOS_NUM_BITS 8 +#define CFA_P70_WC_TCAM_FKB_TL3_IEH_NONEXT_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL3_IEH_SEP_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL3_IEH_AUTH_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL3_IEH_DEST_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL3_IEH_FRAG_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL3_IEH_RTHDR_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL3_IEH_HOP_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL3_IEH_1FRAG_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL3_DF_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL3_L3ERR_NUM_BITS 4 +#define CFA_P70_WC_TCAM_FKB_TL4_TYPE_NUM_BITS 4 +#define CFA_P70_WC_TCAM_FKB_TL4_SRC_NUM_BITS 16 +#define CFA_P70_WC_TCAM_FKB_TL4_DST_NUM_BITS 16 +#define CFA_P70_WC_TCAM_FKB_TL4_FLAGS_NUM_BITS 9 +#define CFA_P70_WC_TCAM_FKB_TL4_SEQ_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_TL4_PA_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL4_OPT_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL4_TCPTS_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL4_ERR_NUM_BITS 4 +#define CFA_P70_WC_TCAM_FKB_T_TYPE_NUM_BITS 5 +#define CFA_P70_WC_TCAM_FKB_T_FLAGS_NUM_BITS 8 +#define CFA_P70_WC_TCAM_FKB_T_IDS_NUM_BITS 24 +#define CFA_P70_WC_TCAM_FKB_T_ID_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_T_CTXTS_NUM_BITS 24 +#define CFA_P70_WC_TCAM_FKB_T_CTXT_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_T_QOS_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_T_ERR_NUM_BITS 4 +#define CFA_P70_WC_TCAM_FKB_L2_TYPE_NUM_BITS 2 +#define CFA_P70_WC_TCAM_FKB_L2_DMAC_NUM_BITS 48 +#define CFA_P70_WC_TCAM_FKB_L2_SMAC_NUM_BITS 48 +#define CFA_P70_WC_TCAM_FKB_L2_DT_NUM_BITS 2 +#define CFA_P70_WC_TCAM_FKB_L2_SA_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L2_NVT_NUM_BITS 2 +#define CFA_P70_WC_TCAM_FKB_L2_OVP_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_L2_OVD_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L2_OVV_NUM_BITS 12 +#define CFA_P70_WC_TCAM_FKB_L2_OVT_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_L2_IVP_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_L2_IVD_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L2_IVV_NUM_BITS 12 +#define CFA_P70_WC_TCAM_FKB_L2_IVT_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_L2_ETYPE_NUM_BITS 16 +#define CFA_P70_WC_TCAM_FKB_L3_TYPE_NUM_BITS 4 +#define CFA_P70_WC_TCAM_FKB_L3_SIP3_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_L3_SIP2_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_L3_SIP1_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_L3_SIP0_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_L3_DIP3_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_L3_DIP2_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_L3_DIP1_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_L3_DIP0_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_L3_TTL_NUM_BITS 8 +#define CFA_P70_WC_TCAM_FKB_L3_PROT_NUM_BITS 8 +/** + * CFA_P70_WC_TCAM_FKB_L3_FID bit length is not fixed + * So the CFA_P70_WC_TCAM_FKB_L3_FID_NUMBITS macro is defined with arguments + */ +#define CFA_P70_WC_TCAM_FKB_L3_FID_NUM_BITS(COND) ((COND) ? 16 : 20) +#define CFA_P70_WC_TCAM_FKB_L3_QOS_NUM_BITS 8 +#define CFA_P70_WC_TCAM_FKB_L3_IEH_NONEXT_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L3_IEH_SEP_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L3_IEH_AUTH_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L3_IEH_DEST_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L3_IEH_FRAG_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L3_IEH_RTHDR_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L3_IEH_HOP_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L3_IEH_1FRAG_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L3_DF_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L3_L3ERR_NUM_BITS 4 +#define CFA_P70_WC_TCAM_FKB_L4_TYPE_NUM_BITS 4 +#define CFA_P70_WC_TCAM_FKB_L4_SRC_NUM_BITS 16 +#define CFA_P70_WC_TCAM_FKB_L4_DST_NUM_BITS 16 +#define CFA_P70_WC_TCAM_FKB_L4_FLAGS_NUM_BITS 9 +#define CFA_P70_WC_TCAM_FKB_L4_SEQ_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_L4_ACK_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_L4_WIN_NUM_BITS 16 +#define CFA_P70_WC_TCAM_FKB_L4_PA_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L4_OPT_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L4_TCPTS_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L4_TSVAL_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_L4_TXECR_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_L4_ERR_NUM_BITS 4 + +/** + * Field length definitions for em fkb + */ +#define CFA_P70_EM_FKB_PROF_ID_NUM_BITS 8 +#define CFA_P70_EM_FKB_L2CTXT_NUM_BITS 11 +#define CFA_P70_EM_FKB_L2FUNC_NUM_BITS 8 +#define CFA_P70_EM_FKB_PARIF_NUM_BITS 2 +#define CFA_P70_EM_FKB_SPIF_NUM_BITS 2 +#define CFA_P70_EM_FKB_SVIF_NUM_BITS 6 +#define CFA_P70_EM_FKB_LCOS_NUM_BITS 3 +#define CFA_P70_EM_FKB_META_HI_NUM_BITS 16 +#define CFA_P70_EM_FKB_META_LO_NUM_BITS 16 +#define CFA_P70_EM_FKB_RCYC_CNT_NUM_BITS 4 +#define CFA_P70_EM_FKB_LOOPBACK_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL2_TYPE_NUM_BITS 2 +#define CFA_P70_EM_FKB_OTL2_DMAC_NUM_BITS 48 +#define CFA_P70_EM_FKB_OTL2_SMAC_NUM_BITS 48 +#define CFA_P70_EM_FKB_OTL2_DT_NUM_BITS 2 +#define CFA_P70_EM_FKB_OTL2_SA_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL2_NVT_NUM_BITS 2 +#define CFA_P70_EM_FKB_OTL2_OVP_NUM_BITS 3 +#define CFA_P70_EM_FKB_OTL2_OVD_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL2_OVV_NUM_BITS 12 +#define CFA_P70_EM_FKB_OTL2_OVT_NUM_BITS 3 +#define CFA_P70_EM_FKB_OTL2_IVP_NUM_BITS 3 +#define CFA_P70_EM_FKB_OTL2_IVD_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL2_IVV_NUM_BITS 12 +#define CFA_P70_EM_FKB_OTL2_IVT_NUM_BITS 3 +#define CFA_P70_EM_FKB_OTL2_ETYPE_NUM_BITS 16 +#define CFA_P70_EM_FKB_OTL3_TYPE_NUM_BITS 4 +#define CFA_P70_EM_FKB_OTL3_SIP3_NUM_BITS 32 +#define CFA_P70_EM_FKB_OTL3_SIP2_NUM_BITS 32 +#define CFA_P70_EM_FKB_OTL3_SIP1_NUM_BITS 32 +#define CFA_P70_EM_FKB_OTL3_SIP0_NUM_BITS 32 +#define CFA_P70_EM_FKB_OTL3_DIP3_NUM_BITS 32 +#define CFA_P70_EM_FKB_OTL3_DIP2_NUM_BITS 32 +#define CFA_P70_EM_FKB_OTL3_DIP1_NUM_BITS 32 +#define CFA_P70_EM_FKB_OTL3_DIP0_NUM_BITS 32 +#define CFA_P70_EM_FKB_OTL3_TTL_NUM_BITS 8 +#define CFA_P70_EM_FKB_OTL3_PROT_NUM_BITS 8 +/** + * CFA_P70_EM_FKB_OTL3_FID bit length is not fixed + * So the CFA_P70_EM_FKB_OTL3_FID_NUMBITS macro is defined with arguments + */ +#define CFA_P70_EM_FKB_OTL3_FID_NUM_BITS(COND) ((COND) ? 16 : 20) +#define CFA_P70_EM_FKB_OTL3_QOS_NUM_BITS 8 +#define CFA_P70_EM_FKB_OTL3_IEH_NONEXT_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL3_IEH_SEP_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL3_IEH_AUTH_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL3_IEH_DEST_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL3_IEH_FRAG_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL3_IEH_RTHDR_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL3_IEH_HOP_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL3_IEH_1FRAG_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL3_DF_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL3_L3ERR_NUM_BITS 4 +#define CFA_P70_EM_FKB_OTL4_TYPE_NUM_BITS 4 +#define CFA_P70_EM_FKB_OTL4_SRC_NUM_BITS 16 +#define CFA_P70_EM_FKB_OTL4_DST_NUM_BITS 16 +#define CFA_P70_EM_FKB_OTL4_FLAGS_NUM_BITS 9 +#define CFA_P70_EM_FKB_OTL4_SEQ_NUM_BITS 32 +#define CFA_P70_EM_FKB_OTL4_PA_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL4_OPT_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL4_TCPTS_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL4_ERR_NUM_BITS 4 +#define CFA_P70_EM_FKB_OT_TYPE_NUM_BITS 5 +#define CFA_P70_EM_FKB_OT_FLAGS_NUM_BITS 8 +#define CFA_P70_EM_FKB_OT_IDS_NUM_BITS 24 +#define CFA_P70_EM_FKB_OT_ID_NUM_BITS 32 +#define CFA_P70_EM_FKB_OT_CTXTS_NUM_BITS 24 +#define CFA_P70_EM_FKB_OT_CTXT_NUM_BITS 32 +#define CFA_P70_EM_FKB_OT_QOS_NUM_BITS 3 +#define CFA_P70_EM_FKB_OT_ERR_NUM_BITS 4 +#define CFA_P70_EM_FKB_TL2_TYPE_NUM_BITS 2 +#define CFA_P70_EM_FKB_TL2_DMAC_NUM_BITS 48 +#define CFA_P70_EM_FKB_TL2_SMAC_NUM_BITS 48 +#define CFA_P70_EM_FKB_TL2_DT_NUM_BITS 2 +#define CFA_P70_EM_FKB_TL2_SA_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL2_NVT_NUM_BITS 2 +#define CFA_P70_EM_FKB_TL2_OVP_NUM_BITS 3 +#define CFA_P70_EM_FKB_TL2_OVD_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL2_OVV_NUM_BITS 12 +#define CFA_P70_EM_FKB_TL2_OVT_NUM_BITS 3 +#define CFA_P70_EM_FKB_TL2_IVP_NUM_BITS 3 +#define CFA_P70_EM_FKB_TL2_IVD_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL2_IVV_NUM_BITS 12 +#define CFA_P70_EM_FKB_TL2_IVT_NUM_BITS 3 +#define CFA_P70_EM_FKB_TL2_ETYPE_NUM_BITS 16 +#define CFA_P70_EM_FKB_TL3_TYPE_NUM_BITS 4 +#define CFA_P70_EM_FKB_TL3_SIP3_NUM_BITS 32 +#define CFA_P70_EM_FKB_TL3_SIP2_NUM_BITS 32 +#define CFA_P70_EM_FKB_TL3_SIP1_NUM_BITS 32 +#define CFA_P70_EM_FKB_TL3_SIP0_NUM_BITS 32 +#define CFA_P70_EM_FKB_TL3_DIP3_NUM_BITS 32 +#define CFA_P70_EM_FKB_TL3_DIP2_NUM_BITS 32 +#define CFA_P70_EM_FKB_TL3_DIP1_NUM_BITS 32 +#define CFA_P70_EM_FKB_TL3_DIP0_NUM_BITS 32 +#define CFA_P70_EM_FKB_TL3_TTL_NUM_BITS 8 +#define CFA_P70_EM_FKB_TL3_PROT_NUM_BITS 8 +/** + * CFA_P70_EM_FKB_TL3_FID bit length is not fixed + * So the CFA_P70_EM_FKB_TL3_FID_NUMBITS macro is defined with arguments + */ +#define CFA_P70_EM_FKB_TL3_FID_NUM_BITS(COND) ((COND) ? 16 : 20) +#define CFA_P70_EM_FKB_TL3_QOS_NUM_BITS 8 +#define CFA_P70_EM_FKB_TL3_IEH_NONEXT_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL3_IEH_SEP_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL3_IEH_AUTH_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL3_IEH_DEST_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL3_IEH_FRAG_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL3_IEH_RTHDR_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL3_IEH_HOP_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL3_IEH_1FRAG_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL3_DF_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL3_L3ERR_NUM_BITS 4 +#define CFA_P70_EM_FKB_TL4_TYPE_NUM_BITS 4 +#define CFA_P70_EM_FKB_TL4_SRC_NUM_BITS 16 +#define CFA_P70_EM_FKB_TL4_DST_NUM_BITS 16 +#define CFA_P70_EM_FKB_TL4_FLAGS_NUM_BITS 9 +#define CFA_P70_EM_FKB_TL4_SEQ_NUM_BITS 32 +#define CFA_P70_EM_FKB_TL4_PA_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL4_OPT_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL4_TCPTS_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL4_ERR_NUM_BITS 4 +#define CFA_P70_EM_FKB_T_TYPE_NUM_BITS 5 +#define CFA_P70_EM_FKB_T_FLAGS_NUM_BITS 8 +#define CFA_P70_EM_FKB_T_IDS_NUM_BITS 24 +#define CFA_P70_EM_FKB_T_ID_NUM_BITS 32 +#define CFA_P70_EM_FKB_T_CTXTS_NUM_BITS 24 +#define CFA_P70_EM_FKB_T_CTXT_NUM_BITS 32 +#define CFA_P70_EM_FKB_T_QOS_NUM_BITS 3 +#define CFA_P70_EM_FKB_T_ERR_NUM_BITS 4 +#define CFA_P70_EM_FKB_L2_TYPE_NUM_BITS 2 +#define CFA_P70_EM_FKB_L2_DMAC_NUM_BITS 48 +#define CFA_P70_EM_FKB_L2_SMAC_NUM_BITS 48 +#define CFA_P70_EM_FKB_L2_DT_NUM_BITS 2 +#define CFA_P70_EM_FKB_L2_SA_NUM_BITS 1 +#define CFA_P70_EM_FKB_L2_NVT_NUM_BITS 2 +#define CFA_P70_EM_FKB_L2_OVP_NUM_BITS 3 +#define CFA_P70_EM_FKB_L2_OVD_NUM_BITS 1 +#define CFA_P70_EM_FKB_L2_OVV_NUM_BITS 12 +#define CFA_P70_EM_FKB_L2_OVT_NUM_BITS 3 +#define CFA_P70_EM_FKB_L2_IVP_NUM_BITS 3 +#define CFA_P70_EM_FKB_L2_IVD_NUM_BITS 1 +#define CFA_P70_EM_FKB_L2_IVV_NUM_BITS 12 +#define CFA_P70_EM_FKB_L2_IVT_NUM_BITS 3 +#define CFA_P70_EM_FKB_L2_ETYPE_NUM_BITS 16 +#define CFA_P70_EM_FKB_L3_TYPE_NUM_BITS 4 +#define CFA_P70_EM_FKB_L3_SIP3_NUM_BITS 32 +#define CFA_P70_EM_FKB_L3_SIP2_NUM_BITS 32 +#define CFA_P70_EM_FKB_L3_SIP1_NUM_BITS 32 +#define CFA_P70_EM_FKB_L3_SIP0_NUM_BITS 32 +#define CFA_P70_EM_FKB_L3_DIP3_NUM_BITS 32 +#define CFA_P70_EM_FKB_L3_DIP2_NUM_BITS 32 +#define CFA_P70_EM_FKB_L3_DIP1_NUM_BITS 32 +#define CFA_P70_EM_FKB_L3_DIP0_NUM_BITS 32 +#define CFA_P70_EM_FKB_L3_TTL_NUM_BITS 8 +#define CFA_P70_EM_FKB_L3_PROT_NUM_BITS 8 +/** + * CFA_P70_EM_FKB_L3_FID bit length is not fixed + * So the CFA_P70_EM_FKB_L3_FID_NUMBITS macro is defined with arguments + */ +#define CFA_P70_EM_FKB_L3_FID_NUM_BITS(COND) ((COND) ? 16 : 20) +#define CFA_P70_EM_FKB_L3_QOS_NUM_BITS 8 +#define CFA_P70_EM_FKB_L3_IEH_NONEXT_NUM_BITS 1 +#define CFA_P70_EM_FKB_L3_IEH_SEP_NUM_BITS 1 +#define CFA_P70_EM_FKB_L3_IEH_AUTH_NUM_BITS 1 +#define CFA_P70_EM_FKB_L3_IEH_DEST_NUM_BITS 1 +#define CFA_P70_EM_FKB_L3_IEH_FRAG_NUM_BITS 1 +#define CFA_P70_EM_FKB_L3_IEH_RTHDR_NUM_BITS 1 +#define CFA_P70_EM_FKB_L3_IEH_HOP_NUM_BITS 1 +#define CFA_P70_EM_FKB_L3_IEH_1FRAG_NUM_BITS 1 +#define CFA_P70_EM_FKB_L3_DF_NUM_BITS 1 +#define CFA_P70_EM_FKB_L3_L3ERR_NUM_BITS 4 +#define CFA_P70_EM_FKB_L4_TYPE_NUM_BITS 4 +#define CFA_P70_EM_FKB_L4_SRC_NUM_BITS 16 +#define CFA_P70_EM_FKB_L4_DST_NUM_BITS 16 +#define CFA_P70_EM_FKB_L4_FLAGS_NUM_BITS 9 +#define CFA_P70_EM_FKB_L4_SEQ_NUM_BITS 32 +#define CFA_P70_EM_FKB_L4_ACK_NUM_BITS 32 +#define CFA_P70_EM_FKB_L4_WIN_NUM_BITS 16 +#define CFA_P70_EM_FKB_L4_PA_NUM_BITS 1 +#define CFA_P70_EM_FKB_L4_OPT_NUM_BITS 1 +#define CFA_P70_EM_FKB_L4_TCPTS_NUM_BITS 1 +#define CFA_P70_EM_FKB_L4_TSVAL_NUM_BITS 32 +#define CFA_P70_EM_FKB_L4_TXECR_NUM_BITS 32 +#define CFA_P70_EM_FKB_L4_ERR_NUM_BITS 4 + +/** + * Field length definitions for em key layout + */ +#define CFA_P70_EM_KL_RANGE_IDX_NUM_BITS 16 +#define CFA_P70_EM_KL_RANGE_PROFILE_NUM_BITS 4 +#define CFA_P70_EM_KL_CREC_TIMER_VALUE_NUM_BITS 4 +#define CFA_P70_EM_KL_CREC_STATE_NUM_BITS 5 +#define CFA_P70_EM_KL_CREC_TCP_MSB_OPP_INIT_NUM_BITS 1 +#define CFA_P70_EM_KL_CREC_TCP_MSB_OPP_NUM_BITS 18 +#define CFA_P70_EM_KL_CREC_TCP_MSB_LOC_NUM_BITS 18 +#define CFA_P70_EM_KL_CREC_TCP_WIN_NUM_BITS 5 +#define CFA_P70_EM_KL_CREC_TCP_UPDT_EN_NUM_BITS 1 +#define CFA_P70_EM_KL_CREC_TCP_DIR_NUM_BITS 1 +#define CFA_P70_EM_KL_METADATA_NUM_BITS 32 +#define CFA_P70_EM_KL_PROF_FUNC_NUM_BITS 8 +#define CFA_P70_EM_KL_META_PROF_NUM_BITS 3 +#define CFA_P70_EM_KL_RECYCLE_DEST_NUM_BITS 1 +#define CFA_P70_EM_KL_FC_PTR_NUM_BITS 28 +#define CFA_P70_EM_KL_FC_TYPE_NUM_BITS 2 +#define CFA_P70_EM_KL_FC_OP_NUM_BITS 1 +#define CFA_P70_EM_KL_PATHS_M1_NUM_BITS 4 +#define CFA_P70_EM_KL_ACT_REC_SIZE_NUM_BITS 5 +#define CFA_P70_EM_KL_RING_TABLE_IDX_NUM_BITS 9 +#define CFA_P70_EM_KL_DESTINATION_NUM_BITS 17 +#define CFA_P70_EM_KL_ACT_REC_PTR_NUM_BITS 26 +#define CFA_P70_EM_KL_ACT_HINT_NUM_BITS 2 +#define CFA_P70_EM_KL_STRENGTH_NUM_BITS 2 +#define CFA_P70_EM_KL_OPCODE_NUM_BITS 4 +#define CFA_P70_EM_KL_EPOCH1_NUM_BITS 6 +#define CFA_P70_EM_KL_EPOCH0_NUM_BITS 12 +#define CFA_P70_EM_KL_REC_SIZE_NUM_BITS 2 +#define CFA_P70_EM_KL_VALID_NUM_BITS 1 +#define CFA_P70_EM_KL_PROF_ID_NUM_BITS 8 +#define CFA_P70_EM_KL_L2CTXT_NUM_BITS 11 +#define CFA_P70_EM_KL_L2FUNC_NUM_BITS 8 +#define CFA_P70_EM_KL_PARIF_NUM_BITS 2 +#define CFA_P70_EM_KL_SPIF_NUM_BITS 2 +#define CFA_P70_EM_KL_SVIF_NUM_BITS 6 +#define CFA_P70_EM_KL_LCOS_NUM_BITS 3 +#define CFA_P70_EM_KL_META_HI_NUM_BITS 16 +#define CFA_P70_EM_KL_META_LO_NUM_BITS 16 +#define CFA_P70_EM_KL_RCYC_CNT_NUM_BITS 4 +#define CFA_P70_EM_KL_LOOPBACK_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL2_TYPE_NUM_BITS 2 +#define CFA_P70_EM_KL_OTL2_DMAC_NUM_BITS 48 +#define CFA_P70_EM_KL_OTL2_SMAC_NUM_BITS 48 +#define CFA_P70_EM_KL_OTL2_DT_NUM_BITS 2 +#define CFA_P70_EM_KL_OTL2_SA_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL2_NVT_NUM_BITS 2 +#define CFA_P70_EM_KL_OTL2_OVP_NUM_BITS 3 +#define CFA_P70_EM_KL_OTL2_OVD_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL2_OVV_NUM_BITS 12 +#define CFA_P70_EM_KL_OTL2_OVT_NUM_BITS 3 +#define CFA_P70_EM_KL_OTL2_IVP_NUM_BITS 3 +#define CFA_P70_EM_KL_OTL2_IVD_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL2_IVV_NUM_BITS 12 +#define CFA_P70_EM_KL_OTL2_IVT_NUM_BITS 3 +#define CFA_P70_EM_KL_OTL2_ETYPE_NUM_BITS 16 +#define CFA_P70_EM_KL_OTL3_TYPE_NUM_BITS 4 +#define CFA_P70_EM_KL_OTL3_SIP3_NUM_BITS 32 +#define CFA_P70_EM_KL_OTL3_SIP2_NUM_BITS 32 +#define CFA_P70_EM_KL_OTL3_SIP1_NUM_BITS 32 +#define CFA_P70_EM_KL_OTL3_SIP0_NUM_BITS 32 +#define CFA_P70_EM_KL_OTL3_DIP3_NUM_BITS 32 +#define CFA_P70_EM_KL_OTL3_DIP2_NUM_BITS 32 +#define CFA_P70_EM_KL_OTL3_DIP1_NUM_BITS 32 +#define CFA_P70_EM_KL_OTL3_DIP0_NUM_BITS 32 +#define CFA_P70_EM_KL_OTL3_TTL_NUM_BITS 8 +#define CFA_P70_EM_KL_OTL3_PROT_NUM_BITS 8 +/** + * CFA_P70_EM_KL_OTL3_FID bit length is not fixed + * So the CFA_P70_EM_KL_OTL3_FID_NUMBITS macro is defined with arguments + */ +#define CFA_P70_EM_KL_OTL3_FID_NUM_BITS(COND) ((COND) ? 16 : 20) +#define CFA_P70_EM_KL_OTL3_QOS_NUM_BITS 8 +#define CFA_P70_EM_KL_OTL3_IEH_NONEXT_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL3_IEH_SEP_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL3_IEH_AUTH_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL3_IEH_DEST_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL3_IEH_FRAG_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL3_IEH_RTHDR_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL3_IEH_HOP_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL3_IEH_1FRAG_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL3_DF_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL3_L3ERR_NUM_BITS 4 +#define CFA_P70_EM_KL_OTL4_TYPE_NUM_BITS 4 +#define CFA_P70_EM_KL_OTL4_SRC_NUM_BITS 16 +#define CFA_P70_EM_KL_OTL4_DST_NUM_BITS 16 +#define CFA_P70_EM_KL_OTL4_FLAGS_NUM_BITS 9 +#define CFA_P70_EM_KL_OTL4_SEQ_NUM_BITS 32 +#define CFA_P70_EM_KL_OTL4_PA_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL4_OPT_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL4_TCPTS_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL4_ERR_NUM_BITS 4 +#define CFA_P70_EM_KL_OT_TYPE_NUM_BITS 5 +#define CFA_P70_EM_KL_OT_FLAGS_NUM_BITS 8 +#define CFA_P70_EM_KL_OT_IDS_NUM_BITS 24 +#define CFA_P70_EM_KL_OT_ID_NUM_BITS 32 +#define CFA_P70_EM_KL_OT_CTXTS_NUM_BITS 24 +#define CFA_P70_EM_KL_OT_CTXT_NUM_BITS 32 +#define CFA_P70_EM_KL_OT_QOS_NUM_BITS 3 +#define CFA_P70_EM_KL_OT_ERR_NUM_BITS 4 +#define CFA_P70_EM_KL_TL2_TYPE_NUM_BITS 2 +#define CFA_P70_EM_KL_TL2_DMAC_NUM_BITS 48 +#define CFA_P70_EM_KL_TL2_SMAC_NUM_BITS 48 +#define CFA_P70_EM_KL_TL2_DT_NUM_BITS 2 +#define CFA_P70_EM_KL_TL2_SA_NUM_BITS 1 +#define CFA_P70_EM_KL_TL2_NVT_NUM_BITS 2 +#define CFA_P70_EM_KL_TL2_OVP_NUM_BITS 3 +#define CFA_P70_EM_KL_TL2_OVD_NUM_BITS 1 +#define CFA_P70_EM_KL_TL2_OVV_NUM_BITS 12 +#define CFA_P70_EM_KL_TL2_OVT_NUM_BITS 3 +#define CFA_P70_EM_KL_TL2_IVP_NUM_BITS 3 +#define CFA_P70_EM_KL_TL2_IVD_NUM_BITS 1 +#define CFA_P70_EM_KL_TL2_IVV_NUM_BITS 12 +#define CFA_P70_EM_KL_TL2_IVT_NUM_BITS 3 +#define CFA_P70_EM_KL_TL2_ETYPE_NUM_BITS 16 +#define CFA_P70_EM_KL_TL3_TYPE_NUM_BITS 4 +#define CFA_P70_EM_KL_TL3_SIP3_NUM_BITS 32 +#define CFA_P70_EM_KL_TL3_SIP2_NUM_BITS 32 +#define CFA_P70_EM_KL_TL3_SIP1_NUM_BITS 32 +#define CFA_P70_EM_KL_TL3_SIP0_NUM_BITS 32 +#define CFA_P70_EM_KL_TL3_DIP3_NUM_BITS 32 +#define CFA_P70_EM_KL_TL3_DIP2_NUM_BITS 32 +#define CFA_P70_EM_KL_TL3_DIP1_NUM_BITS 32 +#define CFA_P70_EM_KL_TL3_DIP0_NUM_BITS 32 +#define CFA_P70_EM_KL_TL3_TTL_NUM_BITS 8 +#define CFA_P70_EM_KL_TL3_PROT_NUM_BITS 8 +/** + * CFA_P70_EM_KL_TL3_FID bit length is not fixed + * So the CFA_P70_EM_KL_TL3_FID_NUMBITS macro is defined with arguments + */ +#define CFA_P70_EM_KL_TL3_FID_NUM_BITS(COND) ((COND) ? 16 : 20) +#define CFA_P70_EM_KL_TL3_QOS_NUM_BITS 8 +#define CFA_P70_EM_KL_TL3_IEH_NONEXT_NUM_BITS 1 +#define CFA_P70_EM_KL_TL3_IEH_SEP_NUM_BITS 1 +#define CFA_P70_EM_KL_TL3_IEH_AUTH_NUM_BITS 1 +#define CFA_P70_EM_KL_TL3_IEH_DEST_NUM_BITS 1 +#define CFA_P70_EM_KL_TL3_IEH_FRAG_NUM_BITS 1 +#define CFA_P70_EM_KL_TL3_IEH_RTHDR_NUM_BITS 1 +#define CFA_P70_EM_KL_TL3_IEH_HOP_NUM_BITS 1 +#define CFA_P70_EM_KL_TL3_IEH_1FRAG_NUM_BITS 1 +#define CFA_P70_EM_KL_TL3_DF_NUM_BITS 1 +#define CFA_P70_EM_KL_TL3_L3ERR_NUM_BITS 4 +#define CFA_P70_EM_KL_TL4_TYPE_NUM_BITS 4 +#define CFA_P70_EM_KL_TL4_SRC_NUM_BITS 16 +#define CFA_P70_EM_KL_TL4_DST_NUM_BITS 16 +#define CFA_P70_EM_KL_TL4_FLAGS_NUM_BITS 9 +#define CFA_P70_EM_KL_TL4_SEQ_NUM_BITS 32 +#define CFA_P70_EM_KL_TL4_PA_NUM_BITS 1 +#define CFA_P70_EM_KL_TL4_OPT_NUM_BITS 1 +#define CFA_P70_EM_KL_TL4_TCPTS_NUM_BITS 1 +#define CFA_P70_EM_KL_TL4_ERR_NUM_BITS 4 +#define CFA_P70_EM_KL_T_TYPE_NUM_BITS 5 +#define CFA_P70_EM_KL_T_FLAGS_NUM_BITS 8 +#define CFA_P70_EM_KL_T_IDS_NUM_BITS 24 +#define CFA_P70_EM_KL_T_ID_NUM_BITS 32 +#define CFA_P70_EM_KL_T_CTXTS_NUM_BITS 24 +#define CFA_P70_EM_KL_T_CTXT_NUM_BITS 32 +#define CFA_P70_EM_KL_T_QOS_NUM_BITS 3 +#define CFA_P70_EM_KL_T_ERR_NUM_BITS 4 +#define CFA_P70_EM_KL_L2_TYPE_NUM_BITS 2 +#define CFA_P70_EM_KL_L2_DMAC_NUM_BITS 48 +#define CFA_P70_EM_KL_L2_SMAC_NUM_BITS 48 +#define CFA_P70_EM_KL_L2_DT_NUM_BITS 2 +#define CFA_P70_EM_KL_L2_SA_NUM_BITS 1 +#define CFA_P70_EM_KL_L2_NVT_NUM_BITS 2 +#define CFA_P70_EM_KL_L2_OVP_NUM_BITS 3 +#define CFA_P70_EM_KL_L2_OVD_NUM_BITS 1 +#define CFA_P70_EM_KL_L2_OVV_NUM_BITS 12 +#define CFA_P70_EM_KL_L2_OVT_NUM_BITS 3 +#define CFA_P70_EM_KL_L2_IVP_NUM_BITS 3 +#define CFA_P70_EM_KL_L2_IVD_NUM_BITS 1 +#define CFA_P70_EM_KL_L2_IVV_NUM_BITS 12 +#define CFA_P70_EM_KL_L2_IVT_NUM_BITS 3 +#define CFA_P70_EM_KL_L2_ETYPE_NUM_BITS 16 +#define CFA_P70_EM_KL_L3_TYPE_NUM_BITS 4 +#define CFA_P70_EM_KL_L3_SIP3_NUM_BITS 32 +#define CFA_P70_EM_KL_L3_SIP2_NUM_BITS 32 +#define CFA_P70_EM_KL_L3_SIP1_NUM_BITS 32 +#define CFA_P70_EM_KL_L3_SIP0_NUM_BITS 32 +#define CFA_P70_EM_KL_L3_DIP3_NUM_BITS 32 +#define CFA_P70_EM_KL_L3_DIP2_NUM_BITS 32 +#define CFA_P70_EM_KL_L3_DIP1_NUM_BITS 32 +#define CFA_P70_EM_KL_L3_DIP0_NUM_BITS 32 +#define CFA_P70_EM_KL_L3_TTL_NUM_BITS 8 +#define CFA_P70_EM_KL_L3_PROT_NUM_BITS 8 +/** + * CFA_P70_EM_KL_L3_FID bit length is not fixed + * So the CFA_P70_EM_KL_L3_FID_NUMBITS macro is defined with arguments + */ +#define CFA_P70_EM_KL_L3_FID_NUM_BITS(COND) ((COND) ? 16 : 20) +#define CFA_P70_EM_KL_L3_QOS_NUM_BITS 8 +#define CFA_P70_EM_KL_L3_IEH_NONEXT_NUM_BITS 1 +#define CFA_P70_EM_KL_L3_IEH_SEP_NUM_BITS 1 +#define CFA_P70_EM_KL_L3_IEH_AUTH_NUM_BITS 1 +#define CFA_P70_EM_KL_L3_IEH_DEST_NUM_BITS 1 +#define CFA_P70_EM_KL_L3_IEH_FRAG_NUM_BITS 1 +#define CFA_P70_EM_KL_L3_IEH_RTHDR_NUM_BITS 1 +#define CFA_P70_EM_KL_L3_IEH_HOP_NUM_BITS 1 +#define CFA_P70_EM_KL_L3_IEH_1FRAG_NUM_BITS 1 +#define CFA_P70_EM_KL_L3_DF_NUM_BITS 1 +#define CFA_P70_EM_KL_L3_L3ERR_NUM_BITS 4 +#define CFA_P70_EM_KL_L4_TYPE_NUM_BITS 4 +#define CFA_P70_EM_KL_L4_SRC_NUM_BITS 16 +#define CFA_P70_EM_KL_L4_DST_NUM_BITS 16 +#define CFA_P70_EM_KL_L4_FLAGS_NUM_BITS 9 +#define CFA_P70_EM_KL_L4_SEQ_NUM_BITS 32 +#define CFA_P70_EM_KL_L4_ACK_NUM_BITS 32 +#define CFA_P70_EM_KL_L4_WIN_NUM_BITS 16 +#define CFA_P70_EM_KL_L4_PA_NUM_BITS 1 +#define CFA_P70_EM_KL_L4_OPT_NUM_BITS 1 +#define CFA_P70_EM_KL_L4_TCPTS_NUM_BITS 1 +#define CFA_P70_EM_KL_L4_TSVAL_NUM_BITS 32 +#define CFA_P70_EM_KL_L4_TXECR_NUM_BITS 32 +#define CFA_P70_EM_KL_L4_ERR_NUM_BITS 4 + +/** + * Field length definitions for action + */ +#define CFA_P70_ACT_TYPE_NUM_BITS 3 +#define CFA_P70_ACT_DROP_NUM_BITS 1 +#define CFA_P70_ACT_VLAN_DELETE_NUM_BITS 2 +#define CFA_P70_ACT_DEST_NUM_BITS 7 +#define CFA_P70_ACT_DEST_OP_NUM_BITS 2 +#define CFA_P70_ACT_DECAP_NUM_BITS 5 +#define CFA_P70_ACT_MIRRORING_NUM_BITS 5 +#define CFA_P70_ACT_METER_PTR_NUM_BITS 10 +#define CFA_P70_ACT_STAT0_OFF_NUM_BITS 3 +#define CFA_P70_ACT_STAT0_OP_NUM_BITS 1 +#define CFA_P70_ACT_STAT0_CTR_TYPE_NUM_BITS 2 +#define CFA_P70_ACT_MOD_OFF_NUM_BITS 5 +#define CFA_P70_ACT_ENC_OFF_NUM_BITS 6 +#define CFA_P70_ACT_SRC_OFF_NUM_BITS 4 +#define CFA_P70_ACT_COMPACT_RSVD_0_NUM_BITS 4 +#define CFA_P70_ACT_STAT0_PTR_NUM_BITS 28 +#define CFA_P70_ACT_STAT1_PTR_NUM_BITS 28 +#define CFA_P70_ACT_STAT1_OP_NUM_BITS 1 +#define CFA_P70_ACT_STAT1_CTR_TYPE_NUM_BITS 2 +#define CFA_P70_ACT_MOD_PTR_NUM_BITS 28 +#define CFA_P70_ACT_ENC_PTR_NUM_BITS 28 +#define CFA_P70_ACT_SRC_PTR_NUM_BITS 28 +#define CFA_P70_ACT_FULL_RSVD_0_NUM_BITS 7 +#define CFA_P70_ACT_SRC_KO_EN_NUM_BITS 1 +#define CFA_P70_ACT_MCG_RSVD_0_NUM_BITS 2 +#define CFA_P70_ACT_NEXT_PTR_NUM_BITS 26 +#define CFA_P70_ACT_PTR0_ACT_HINT_NUM_BITS 2 +#define CFA_P70_ACT_PTR0_ACT_REC_PTR_NUM_BITS 26 +#define CFA_P70_ACT_PTR1_ACT_HINT_NUM_BITS 2 +#define CFA_P70_ACT_PTR1_ACT_REC_PTR_NUM_BITS 26 +#define CFA_P70_ACT_PTR2_ACT_HINT_NUM_BITS 2 +#define CFA_P70_ACT_PTR2_ACT_REC_PTR_NUM_BITS 26 +#define CFA_P70_ACT_PTR3_ACT_HINT_NUM_BITS 2 +#define CFA_P70_ACT_PTR3_ACT_REC_PTR_NUM_BITS 26 +#define CFA_P70_ACT_PTR4_ACT_HINT_NUM_BITS 2 +#define CFA_P70_ACT_PTR4_ACT_REC_PTR_NUM_BITS 26 +#define CFA_P70_ACT_PTR5_ACT_HINT_NUM_BITS 2 +#define CFA_P70_ACT_PTR5_ACT_REC_PTR_NUM_BITS 26 +#define CFA_P70_ACT_PTR6_ACT_HINT_NUM_BITS 2 +#define CFA_P70_ACT_PTR6_ACT_REC_PTR_NUM_BITS 26 +#define CFA_P70_ACT_PTR7_ACT_HINT_NUM_BITS 2 +#define CFA_P70_ACT_PTR7_ACT_REC_PTR_NUM_BITS 26 +#define CFA_P70_ACT_MCG_SUBSEQ_RSVD_0_NUM_BITS 3 +#define CFA_P70_ACT_MOD_MODIFY_ACT_HDR_NUM_BITS 16 +#define CFA_P70_ACT_MOD_MD_UPDT_DATA_NUM_BITS 32 +#define CFA_P70_ACT_MOD_MD_UPDT_PROF_NUM_BITS 4 + +/** + * Enumeration definition for field 'md_op' + */ +enum cfa_p70_md_op { + /* + * Normal Metadata update: ! md = (md & ~md_prof.mask) | (md_prof.mask & + * md_data) + */ + CFA_P70_MD_OP_NORMAL = 0, + /* + * L2 Hash Metadata update: ! md = (md & ~md_prof.mask) | (md_prof.mask + * & hash_l2(seed,packet)) + */ + CFA_P70_MD_OP_L2_HASH = 1, + /* + * L4 Hash Metadata update: ! md = (md & ~ md_prof.mask) | (md_prof.mask + * & hash_l3l4(seed,packet)) + */ + CFA_P70_MD_OP_L4_HASH = 2, + /* + * SVIF insert Metadata update: ! md = (md & ~ md_prof.mask) | + * (md_prof.mask & zero_extend(svif)) + */ + CFA_P70_MD_OP_SVIF = 3, +}; +#define CFA_P70_ACT_MOD_MD_UPDT_OP_NUM_BITS 2 +#define CFA_P70_ACT_MOD_MD_UPDT_RSVD_0_NUM_BITS 10 +#define CFA_P70_ACT_MOD_MD_UPDT_TOP_NUM_BITS 48 +#define CFA_P70_ACT_MOD_RM_OVLAN_NUM_BITS 32 +#define CFA_P70_ACT_MOD_RM_IVLAN_NUM_BITS 32 +#define CFA_P70_ACT_MOD_RPL_IVLAN_NUM_BITS 32 +#define CFA_P70_ACT_MOD_RPL_OVLAN_NUM_BITS 32 +#define CFA_P70_ACT_MOD_TTL_UPDT_OP_NUM_BITS 15 +#define CFA_P70_ACT_MOD_TTL_UPDT_ALT_VID_NUM_BITS 12 +#define CFA_P70_ACT_MOD_TTL_UPDT_ALT_PFID_NUM_BITS 5 +#define CFA_P70_ACT_MOD_TTL_UPDT_TOP_NUM_BITS 32 +#define CFA_P70_ACT_MOD_TNL_MODIFY_DEL_NUM_BITS 16 +#define CFA_P70_ACT_MOD_TNL_MODIFY_8B_NEW_PROT_NUM_BITS 8 +#define CFA_P70_ACT_MOD_TNL_MODIFY_8B_EXIST_PROT_NUM_BITS 8 +#define CFA_P70_ACT_MOD_TNL_MODIFY_8B_VEC_NUM_BITS 16 +#define CFA_P70_ACT_MOD_TNL_MODIFY_8B_TOP_NUM_BITS 32 +#define CFA_P70_ACT_MOD_TNL_MODIFY_16B_NEW_PROT_NUM_BITS 16 +#define CFA_P70_ACT_MOD_TNL_MODIFY_16B_EXIST_PROT_NUM_BITS 16 +#define CFA_P70_ACT_MOD_TNL_MODIFY_16B_VEC_NUM_BITS 16 +#define CFA_P70_ACT_MOD_TNL_MODIFY_16B_TOP_NUM_BITS 48 +#define CFA_P70_ACT_MOD_UPDT_FIELD_DATA0_NUM_BITS 32 +#define CFA_P70_ACT_MOD_UPDT_FIELD_VEC_RSVD_NUM_BITS 15 +#define CFA_P70_ACT_MOD_UPDT_FIELD_VEC_KID_NUM_BITS 1 +#define CFA_P70_ACT_MOD_UPDT_FIELD_TOP_NUM_BITS 48 +#define CFA_P70_ACT_MOD_SMAC_NUM_BITS 48 +#define CFA_P70_ACT_MOD_DMAC_NUM_BITS 48 +#define CFA_P70_ACT_MOD_SIPV6_NUM_BITS 128 +#define CFA_P70_ACT_MOD_DIPV6_NUM_BITS 128 +#define CFA_P70_ACT_MOD_SIPV4_NUM_BITS 32 +#define CFA_P70_ACT_MOD_DIPV4_NUM_BITS 32 +#define CFA_P70_ACT_MOD_SPORT_NUM_BITS 16 +#define CFA_P70_ACT_MOD_DPORT_NUM_BITS 16 + +/** + * Enumeration definition for field 'ecv_tnl' + */ +enum cfa_p70_ecv_tnl { + /* No tunnel header will be added. */ + CFA_P70_ECV_TNL_NOP = 0, + /* + * Generic full header will be added after inserted L2, L3, or L4 + * header. The first byte of the tunnel body will be the length of the + * inserted tunnel. + */ + CFA_P70_ECV_TNL_GENERIC = 1, + /* VXLAN tunnel header will be added. */ + CFA_P70_ECV_TNL_VXLAN = 2, + /* NGE (VXLAN2) Header will be added. */ + CFA_P70_ECV_TNL_NGE = 3, + /* NVGRE Header will be added. */ + CFA_P70_ECV_TNL_NVGRE = 4, + /* GRE Header will be added. */ + CFA_P70_ECV_TNL_GRE = 5, + /* + * Generic header after existing L4 header will be added. The first byte + * of the tunnel body will be the length of the inserted tunnel. + */ + CFA_P70_ECV_TNL_GENERIC_L4 = 6, + /* + * Generic header after existing tunnel will be added. The first byte of + * the tunnel body will be the length of the inserted tunnel. + */ + CFA_P70_ECV_TNL_GENERIC_TUN = 7, +}; +#define CFA_P70_ACT_ENC_ECV_TNL_NUM_BITS 3 + +/** + * Enumeration definition for field 'ecv_l4' + */ +enum cfa_p70_ecv_l4 { + /* No L4 Header */ + CFA_P70_ECV_L4_NOP = 0, + /* No L4 Header */ + CFA_P70_ECV_L4_NOP1 = 1, + /* No L4 Header */ + CFA_P70_ECV_L4_NOP2 = 2, + /* No L4 Header */ + CFA_P70_ECV_L4_NOP3 = 3, + /* Add L4 Header without entropy and with CS=0. */ + CFA_P70_ECV_L4_L4 = 4, + /* Add L4 Header without entropy and with CS=calculated. */ + CFA_P70_ECV_L4_L4_CS = 5, + /* Add L4 Header with entropy and with CS=0. */ + CFA_P70_ECV_L4_L4_ENT = 6, + /* Add L4 Header with entropy and with CS=calculated. */ + CFA_P70_ECV_L4_L4_ENT_CS = 7, +}; +#define CFA_P70_ACT_ENC_ECV_L4_NUM_BITS 3 + +/** + * Enumeration definition for field 'ecv_l3' + */ +enum cfa_p70_ecv_l3 { + /* No L3 Header */ + CFA_P70_ECV_L3_NOP = 0, + /* No L3 Header */ + CFA_P70_ECV_L3_NOP1 = 1, + /* No L3 Header */ + CFA_P70_ECV_L3_NOP2 = 2, + /* No L3 Header */ + CFA_P70_ECV_L3_NOP3 = 3, + /* Add IPV4 Header */ + CFA_P70_ECV_L3_IPV4 = 4, + /* Add IPV4 Header */ + CFA_P70_ECV_L3_IPV6 = 5, + /* Add MPLS (8847) Header */ + CFA_P70_ECV_L3_MPLS8847 = 6, + /* Add MPLS (8848) Header */ + CFA_P70_ECV_L3_MPLS8848 = 7, +}; +#define CFA_P70_ACT_ENC_ECV_L3_NUM_BITS 3 +#define CFA_P70_ACT_ENC_ECV_L2_NUM_BITS 1 + +/** + * Enumeration definition for field 'ecv_vtag' + */ +enum cfa_p70_ecv_vtag { + /* No VLAN tag will be added. */ + CFA_P70_ECV_VTAG_NOP = 0, + /* Add one VLAN tag using the PRI field from the encap record. */ + CFA_P70_ECV_VTAG_ADD1_USE_PRI = 1, + /* Add one VLAN tag remap wit inner VLAN Tag PRI field. */ + CFA_P70_ECV_VTAG_ADD1_REMAP_INNER_PRI = 2, + /* Add one VLAN tag remap with diff serve field. */ + CFA_P70_ECV_VTAG_ADD1_REMAP_DIFF = 3, + /* Add two VLAN tags using the PRI field from the encap record. */ + CFA_P70_ECV_VTAG_ADD2_USE_PRI = 4, + /* Add two VLAN tag remap with diff serve field. */ + CFA_P70_ECV_VTAG_ADD2_REMAP_DIFF = 5, + /* Add zero VLAN tags remap with inner VLAN Tag PRI Field. */ + CFA_P70_ECV_VTAG_ADD0_REMAP_INNER_PRI = 6, + /* Add zero VLAN tags remap with diff serve field. */ + CFA_P70_ECV_VTAG_ADD0_REMAP_DIFF = 7, + /* Add zero VLAG tags remap with immediate PRI=0. */ + CFA_P70_ECV_VTAG_ADD0_IMMED_PRI0 = 8, + /* Add zero VLAG tags remap with immediate PRI=1. */ + CFA_P70_ECV_VTAG_ADD0_IMMED_PRI1 = 9, + /* Add zero VLAG tags remap with immediate PRI=2. */ + CFA_P70_ECV_VTAG_ADD0_IMMED_PRI2 = 10, + /* Add zero VLAG tags remap with immediate PRI=3. */ + CFA_P70_ECV_VTAG_ADD0_IMMED_PRI3 = 11, + /* Add zero VLAG tags remap with immediate PRI=4. */ + CFA_P70_ECV_VTAG_ADD0_IMMED_PRI4 = 12, + /* Add zero VLAG tags remap with immediate PRI=5. */ + CFA_P70_ECV_VTAG_ADD0_IMMED_PRI5 = 13, + /* Add zero VLAG tags remap with immediate PRI=6. */ + CFA_P70_ECV_VTAG_ADD0_IMMED_PRI6 = 14, + /* Add zero VLAG tags remap with immediate PRI=7. */ + CFA_P70_ECV_VTAG_ADD0_IMMED_PRI7 = 15, +}; +#define CFA_P70_ACT_ENC_ECV_VTAG_NUM_BITS 4 +#define CFA_P70_ACT_ENC_ECV_EC_NUM_BITS 1 +#define CFA_P70_ACT_ENC_ECV_VALID_NUM_BITS 1 +#define CFA_P70_ACT_ENC_EC_IP_TTL_IH_NUM_BITS 1 +#define CFA_P70_ACT_ENC_EC_IP_TOS_IH_NUM_BITS 1 +#define CFA_P70_ACT_ENC_EC_TUN_QOS_NUM_BITS 3 +#define CFA_P70_ACT_ENC_EC_GRE_SET_K_NUM_BITS 1 + +/** + * Enumeration definition for field 'enccfg_dmac_ovr' + */ +enum cfa_p70_enccfg_dmac_ovr { + /* use encap record DMAC */ + CFA_P70_ENCCFG_DMAC_OVR_ENCAP = 0, + /* re-use existing inner L2 header DMAC */ + CFA_P70_ENCCFG_DMAC_OVR_INNER_DMAC = 1, + /* re-use existing tunnel L2 header DMAC */ + CFA_P70_ENCCFG_DMAC_OVR_TUNNEL_DMAC = 2, + /* re-use existing outer-most L2 header DMAC */ + CFA_P70_ENCCFG_DMAC_OVR_OUTER_DMAC = 3, +}; +#define CFA_P70_ACT_ENC_EC_DMAC_OVR_NUM_BITS 2 + +/** + * Enumeration definition for field 'enccfg_vlan_ovr' + */ +enum cfa_p70_enccfg_vlan_ovr { + /* use only encap record VLAN tags */ + CFA_P70_ENCCFG_VLAN_OVR_ENCAP = 0, + /* use only existing inner L2 header VLAN tags */ + CFA_P70_ENCCFG_VLAN_OVR_INNER_L2 = 1, + /* use only existing tunnel L2 header VLAN tags */ + CFA_P70_ENCCFG_VLAN_OVR_TUNNEL_L2 = 2, + /* use only existing outer-most L2 header VLAN tags */ + CFA_P70_ENCCFG_VLAN_OVR_OUTER_L2 = 3, + /* include inner VLAN Tag from existing inner L2 header (keeps 1 TAG) */ + CFA_P70_ENCCFG_VLAN_OVR_INNER_INNER = 4, + /* include outer VLAN Tag from existing inner L2 header (keeps 1 TAG) */ + CFA_P70_ENCCFG_VLAN_OVR_INNER_OUTER = 5, + /* + * include inner VLAN Tag from existing outer-most L2 header (keeps 1 + * TAG) + */ + CFA_P70_ENCCFG_VLAN_OVR_OUTER_INNER = 6, + /* + * include outer VLAN Tag from existing outer-most L2 header (keeps 1 + * TAG) + */ + CFA_P70_ENCCFG_VLAN_OVR_OUTER_OUTER = 7, +}; +#define CFA_P70_ACT_ENC_EC_VLAN_OVR_NUM_BITS 3 + +/** + * Enumeration definition for field 'enccfg_smac_ovr' + */ +enum cfa_p70_enccfg_smac_ovr { + /* use only source property record SMAC */ + CFA_P70_ENCCFG_SMAC_OVR_ENCAP = 0, + /* re-use existing inner L2 header SMAC */ + CFA_P70_ENCCFG_SMAC_OVR_INNER_SMAC = 1, + /* re-use existing tunnel L2 header SMAC */ + CFA_P70_ENCCFG_SMAC_OVR_TUNNEL_SMAC = 2, + /* re-use existing outer-most L2 header SMAC */ + CFA_P70_ENCCFG_SMAC_OVR_OUTER_SMAC = 3, + /* re-use existing inner L2 header DMAC */ + CFA_P70_ENCCFG_SMAC_OVR_INNER_DMAC = 5, + /* re-use existing tunnel L2 header DMAC */ + CFA_P70_ENCCFG_SMAC_OVR_TUNNEL_DMAC = 6, + /* re-use existing outer-most L2 header DMAC */ + CFA_P70_ENCCFG_SMAC_OVR_OUTER_DMAC = 7, +}; +#define CFA_P70_ACT_ENC_EC_SMAC_OVR_NUM_BITS 3 + +/** + * Enumeration definition for field 'enccfg_ipv4_id_ctrl' + */ +enum cfa_p70_enccfg_ipv4_id_ctrl { + /* use encap record IPv4 ID field */ + CFA_P70_ENCCFG_IPV4_ID_CTRL_ENCAP = 0, + /* inherit from next existing IPv4 header ID field */ + CFA_P70_ENCCFG_IPV4_ID_CTRL_INHERIT = 2, + /* use CFA incrementing IPv4 ID counter */ + CFA_P70_ENCCFG_IPV4_ID_CTRL_INCREMENT = 3, +}; +#define CFA_P70_ACT_ENC_EC_IPV4_ID_CTRL_NUM_BITS 2 +#define CFA_P70_ACT_ENC_L2_DMAC_NUM_BITS 48 +#define CFA_P70_ACT_ENC_VLAN1_TAG_VID_NUM_BITS 12 +#define CFA_P70_ACT_ENC_VLAN1_TAG_DE_NUM_BITS 1 +#define CFA_P70_ACT_ENC_VLAN1_TAG_PRI_NUM_BITS 3 +#define CFA_P70_ACT_ENC_VLAN1_TAG_TPID_NUM_BITS 16 +#define CFA_P70_ACT_ENC_VLAN2_IT_VID_NUM_BITS 12 +#define CFA_P70_ACT_ENC_VLAN2_IT_DE_NUM_BITS 1 +#define CFA_P70_ACT_ENC_VLAN2_IT_PRI_NUM_BITS 3 +#define CFA_P70_ACT_ENC_VLAN2_IT_TPID_NUM_BITS 16 +#define CFA_P70_ACT_ENC_VLAN2_OT_VID_NUM_BITS 12 +#define CFA_P70_ACT_ENC_VLAN2_OT_DE_NUM_BITS 1 +#define CFA_P70_ACT_ENC_VLAN2_OT_PRI_NUM_BITS 3 +#define CFA_P70_ACT_ENC_VLAN2_OT_TPID_NUM_BITS 16 +#define CFA_P70_ACT_ENC_IPV4_ID_NUM_BITS 16 +#define CFA_P70_ACT_ENC_IPV4_TOS_NUM_BITS 8 +#define CFA_P70_ACT_ENC_IPV4_HLEN_NUM_BITS 4 +#define CFA_P70_ACT_ENC_IPV4_VER_NUM_BITS 4 +#define CFA_P70_ACT_ENC_IPV4_PROT_NUM_BITS 8 +#define CFA_P70_ACT_ENC_IPV4_TTL_NUM_BITS 8 +#define CFA_P70_ACT_ENC_IPV4_FRAG_NUM_BITS 13 +#define CFA_P70_ACT_ENC_IPV4_FLAGS_NUM_BITS 3 +#define CFA_P70_ACT_ENC_IPV4_DEST_NUM_BITS 32 +#define CFA_P70_ACT_ENC_IPV6_FLOW_LABEL_NUM_BITS 20 +#define CFA_P70_ACT_ENC_IPV6_TRAFFIC_CLASS_NUM_BITS 8 +#define CFA_P70_ACT_ENC_IPV6_VER_NUM_BITS 4 +#define CFA_P70_ACT_ENC_IPV6_HOP_LIMIT_NUM_BITS 8 +#define CFA_P70_ACT_ENC_IPV6_NEXT_HEADER_NUM_BITS 8 +#define CFA_P70_ACT_ENC_IPV6_PAYLOAD_LENGTH_NUM_BITS 16 +#define CFA_P70_ACT_ENC_IPV6_DEST_NUM_BITS 128 +#define CFA_P70_ACT_ENC_MPLS_TAG1_NUM_BITS 32 +#define CFA_P70_ACT_ENC_MPLS_TAG2_NUM_BITS 32 +#define CFA_P70_ACT_ENC_MPLS_TAG3_NUM_BITS 32 +#define CFA_P70_ACT_ENC_MPLS_TAG4_NUM_BITS 32 +#define CFA_P70_ACT_ENC_MPLS_TAG5_NUM_BITS 32 +#define CFA_P70_ACT_ENC_MPLS_TAG6_NUM_BITS 32 +#define CFA_P70_ACT_ENC_MPLS_TAG7_NUM_BITS 32 +#define CFA_P70_ACT_ENC_MPLS_TAG8_NUM_BITS 32 +#define CFA_P70_ACT_ENC_L4_DEST_PORT_NUM_BITS 16 +#define CFA_P70_ACT_ENC_L4_SRC_PORT_NUM_BITS 16 +#define CFA_P70_ACT_ENC_TNL_VXLAN_NEXT_PROT_NUM_BITS 8 +#define CFA_P70_ACT_ENC_TNL_VXLAN_RSVD_0_NUM_BITS 16 +#define CFA_P70_ACT_ENC_TNL_VXLAN_FLAGS_NUM_BITS 8 +#define CFA_P70_ACT_ENC_TNL_VXLAN_RSVD_1_NUM_BITS 8 +#define CFA_P70_ACT_ENC_TNL_VXLAN_VNI_NUM_BITS 24 +#define CFA_P70_ACT_ENC_TNL_NGE_PROT_TYPE_NUM_BITS 16 +#define CFA_P70_ACT_ENC_TNL_NGE_RSVD_0_NUM_BITS 6 +#define CFA_P70_ACT_ENC_TNL_NGE_FLAGS_C_NUM_BITS 1 +#define CFA_P70_ACT_ENC_TNL_NGE_FLAGS_O_NUM_BITS 1 +#define CFA_P70_ACT_ENC_TNL_NGE_FLAGS_OPT_LEN_NUM_BITS 6 +#define CFA_P70_ACT_ENC_TNL_NGE_FLAGS_VER_NUM_BITS 2 +#define CFA_P70_ACT_ENC_TNL_NGE_RSVD_1_NUM_BITS 8 +#define CFA_P70_ACT_ENC_TNL_NGE_VNI_NUM_BITS 24 +#define CFA_P70_ACT_ENC_TNL_NGE_OPTIONS_NUM_BITS 64 +#define CFA_P70_ACT_ENC_TNL_NVGRE_FLOW_ID_NUM_BITS 8 +#define CFA_P70_ACT_ENC_TNL_NVGRE_VSID_NUM_BITS 24 +#define CFA_P70_ACT_ENC_TNL_GRE_KEY_NUM_BITS 32 +#define CFA_P70_ACT_ENC_TNL_GENERIC_TID_NUM_BITS 8 +#define CFA_P70_ACT_ENC_TNL_GENERIC_LENGTH_NUM_BITS 8 +#define CFA_P70_ACT_ENC_TNL_GENERIC_HEADER_NUM_BITS 32 +#define CFA_P70_ACT_SRC_MAC_NUM_BITS 48 +#define CFA_P70_ACT_SRC_IPV4_ADDR_NUM_BITS 32 +#define CFA_P70_ACT_SRC_IPV6_ADDR_NUM_BITS 128 +#define CFA_P70_ACT_STAT0_B16_FPC_NUM_BITS 64 +#define CFA_P70_ACT_STAT1_B16_FPC_NUM_BITS 64 +#define CFA_P70_ACT_STAT0_B16_FBC_NUM_BITS 64 +#define CFA_P70_ACT_STAT1_B16_FBC_NUM_BITS 64 +#define CFA_P70_ACT_STAT0_B24_FPC_NUM_BITS 64 +#define CFA_P70_ACT_STAT1_B24_FPC_NUM_BITS 64 +#define CFA_P70_ACT_STAT0_B24_FBC_NUM_BITS 64 +#define CFA_P70_ACT_STAT1_B24_FBC_NUM_BITS 64 +#define CFA_P70_ACT_STAT0_B24_TIMESTAMP_NUM_BITS 32 +#define CFA_P70_ACT_STAT1_B24_TIMESTAMP_NUM_BITS 32 +#define CFA_P70_ACT_STAT0_B24_TCP_FLAGS_NUM_BITS 9 +#define CFA_P70_ACT_STAT1_B24_TCP_FLAGS_NUM_BITS 9 +#define CFA_P70_ACT_STAT0_B24_UNUSED_0_NUM_BITS 23 +#define CFA_P70_ACT_STAT1_B24_UNUSED_0_NUM_BITS 23 +#define CFA_P70_ACT_STAT0_B32A_FPC_NUM_BITS 64 +#define CFA_P70_ACT_STAT1_B32A_FPC_NUM_BITS 64 +#define CFA_P70_ACT_STAT0_B32A_FBC_NUM_BITS 64 +#define CFA_P70_ACT_STAT1_B32A_FBC_NUM_BITS 64 +#define CFA_P70_ACT_STAT0_B32A_MPC_NUM_BITS 64 +#define CFA_P70_ACT_STAT1_B32A_MPC_NUM_BITS 64 +#define CFA_P70_ACT_STAT0_B32A_MBC_NUM_BITS 64 +#define CFA_P70_ACT_STAT1_B32A_MBC_NUM_BITS 64 +#define CFA_P70_ACT_STAT0_B32B_FPC_NUM_BITS 64 +#define CFA_P70_ACT_STAT1_B32B_FPC_NUM_BITS 64 +#define CFA_P70_ACT_STAT0_B32B_FBC_NUM_BITS 64 +#define CFA_P70_ACT_STAT1_B32B_FBC_NUM_BITS 64 +#define CFA_P70_ACT_STAT0_B32B_TIMESTAMP_NUM_BITS 32 +#define CFA_P70_ACT_STAT1_B32B_TIMESTAMP_NUM_BITS 32 +#define CFA_P70_ACT_STAT0_B32B_TCP_FLAGS_NUM_BITS 9 +#define CFA_P70_ACT_STAT1_B32B_TCP_FLAGS_NUM_BITS 9 +#define CFA_P70_ACT_STAT0_B32B_UNUSED_0_NUM_BITS 7 +#define CFA_P70_ACT_STAT1_B32B_UNUSED_0_NUM_BITS 7 +#define CFA_P70_ACT_STAT0_B32B_MPC15_0_NUM_BITS 16 +#define CFA_P70_ACT_STAT1_B32B_MPC15_0_NUM_BITS 16 +#define CFA_P70_ACT_STAT0_B32B_MPC37_16_NUM_BITS 22 +#define CFA_P70_ACT_STAT1_B32B_MPC37_16_NUM_BITS 22 +#define CFA_P70_ACT_STAT0_B32B_MBC_NUM_BITS 42 +#define CFA_P70_ACT_STAT1_B32B_MBC_NUM_BITS 42 + +#define CFA_P70_CACHE_LINE_BYTES 32 +#define CFA_P70_CACHE_LINE_BITS \ + (CFA_P70_CACHE_LINE_BYTES * BITS_PER_BYTE) + +/* clang-format on */ + +#endif /* _CFA_P70_HW_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_p70_mpc_structs.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_p70_mpc_structs.h new file mode 100644 index 0000000000..508e6f1b44 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_p70_mpc_structs.h @@ -0,0 +1,1496 @@ +/**************************************************************************** + * Copyright(c) 2001-2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * Name: cfa_p70_mpc_structs.h + * + * Description: MPC CFA command and completion structure definitions + * + * Date: 09/29/22 11:50:38 + * + * Note: This file is scripted generated by ./cfa_header_gen.py. + * DO NOT modify this file manually !!!! + * + ****************************************************************************/ +#ifndef _CFA_P70_MPC_STRUCTS_H_ +#define _CFA_P70_MPC_STRUCTS_H_ + +/* clang-format off */ + +/** + * READ_CMD: This command reads 1-4 consecutive 32B words from the + * specified address within a table scope. + */ +struct cfa_mpc_read_cmd { + /* + * This value selects the format for the mid-path command for the CFA. + */ + uint32_t opcode:8; + #define READ_CMD_OPCODE_READ 0 + /* This value selects the table type to be acted upon. */ + uint32_t table_type:4; + #define READ_CMD_TABLE_TYPE_ACTION 0 + #define READ_CMD_TABLE_TYPE_EM 1 + /* Unused field [4] */ + uint32_t unused0:4; + /* Table scope to access. */ + uint32_t table_scope:5; + /* Unused field [3] */ + uint32_t unused1:3; + /* + * Number of 32B units in access. If value is outside the range [1, 4], + * CFA aborts processing and reports FMT_ERR status. + */ + uint32_t data_size:3; + /* Unused field [1] */ + uint32_t unused2:1; + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + uint32_t cache_option:4; + /* + * A 32B index into the table identified by (TABLE_TYPE, TABLE_SCOPE): + */ + uint32_t table_index:26; + /* Unused field [6] */ + uint32_t unused3:6; + /* + * The 64-bit host address to which to write the DMA data returned in + * the completion. The data will be written to the same function as the + * one that owns the SQ this command is read from. DATA_SIZE determines + * the maximum size of the data written. If HOST_ADDRESS[1:0] is not 0, + * CFA aborts processing and reports FMT_ERR status. + */ + uint32_t host_address_1:32; + uint32_t host_address_2:32; +}; + +/** + * WRITE_CMD: This command writes 1-4 consecutive 32B words to the + * specified address within a table scope. + */ +struct cfa_mpc_write_cmd { + /* + * This value selects the format for the mid-path command for the CFA. + */ + uint32_t opcode:8; + #define WRITE_CMD_OPCODE_WRITE 1 + /* This value selects the table type to be acted upon. */ + uint32_t table_type:4; + #define WRITE_CMD_TABLE_TYPE_ACTION 0 + #define WRITE_CMD_TABLE_TYPE_EM 1 + /* + * Sets the OPTION field on the cache interface to use write-through for + * EM entry writes while processing EM_INSERT commands. For all other + * cases (inluding EM_INSERT bucket writes), the OPTION field is set by + * the CACHE_OPTION and CACHE_OPTION2 fields. + */ + uint32_t write_through:1; + /* Unused field [3] */ + uint32_t unused0:3; + /* Table scope to access. */ + uint32_t table_scope:5; + /* Unused field [3] */ + uint32_t unused1:3; + /* + * Number of 32B units in access. If value is outside the range [1, 4], + * CFA aborts processing and reports FMT_ERR status. + */ + uint32_t data_size:3; + /* Unused field [1] */ + uint32_t unused2:1; + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + uint32_t cache_option:4; + /* + * A 32B index into the table identified by (TABLE_TYPE, TABLE_SCOPE): + */ + uint32_t table_index:26; + /* Unused field [70] */ + uint32_t unused3_1:6; + uint32_t unused3_2:32; + uint32_t unused3_3:32; +}; + +/** + * READ_CLR_CMD: This command performs a read-modify-write to the + * specified 32B address using a 16b mask that specifies up to 16 16b + * words to clear before writing the data back. It returns the 32B data + * word read from cache (not the value written after the clear + * operation). + */ +struct cfa_mpc_read_clr_cmd { + /* + * This value selects the format for the mid-path command for the CFA. + */ + uint32_t opcode:8; + #define READ_CLR_CMD_OPCODE_READ_CLR 2 + /* This value selects the table type to be acted upon. */ + uint32_t table_type:4; + #define READ_CLR_CMD_TABLE_TYPE_ACTION 0 + #define READ_CLR_CMD_TABLE_TYPE_EM 1 + /* Unused field [4] */ + uint32_t unused0:4; + /* Table scope to access. */ + uint32_t table_scope:5; + /* Unused field [3] */ + uint32_t unused1:3; + /* + * This field is no longer used. The READ_CLR command always reads (and + * does a mask-clear) on a single cache line. This field was added for + * SR2 A0 to avoid an ADDR_ERR when TABLE_INDEX=0 and TABLE_TYPE=EM (see + * CUMULUS-17872). That issue was fixed in SR2 B0. + */ + uint32_t data_size:3; + /* Unused field [1] */ + uint32_t unused2:1; + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + uint32_t cache_option:4; + /* + * A 32B index into the table identified by (TABLE_TYPE, TABLE_SCOPE): + */ + uint32_t table_index:26; + /* Unused field [6] */ + uint32_t unused3:6; + /* + * The 64-bit host address to which to write the DMA data returned in + * the completion. The data will be written to the same function as the + * one that owns the SQ this command is read from. DATA_SIZE determines + * the maximum size of the data written. If HOST_ADDRESS[1:0] is not 0, + * CFA aborts processing and reports FMT_ERR status. + */ + uint32_t host_address_1:32; + uint32_t host_address_2:32; + /* + * Specifies bits in 32B data word to clear. For x=0..15, when + * clear_mask[x]=1, data[x*16+15:x*16] is set to 0. + */ + uint32_t clear_mask:16; + /* Unused field [16] */ + uint32_t unused4:16; +}; + +/** + * INVALIDATE_CMD: This command forces an explicit evict of 1-4 + * consecutive cache lines such that the next time the structure is used + * it will be re-read from its backing store location. + */ +struct cfa_mpc_invalidate_cmd { + /* + * This value selects the format for the mid-path command for the CFA. + */ + uint32_t opcode:8; + #define INVALIDATE_CMD_OPCODE_INVALIDATE 5 + /* This value selects the table type to be acted upon. */ + uint32_t table_type:4; + #define INVALIDATE_CMD_TABLE_TYPE_ACTION 0 + #define INVALIDATE_CMD_TABLE_TYPE_EM 1 + /* Unused field [4] */ + uint32_t unused0:4; + /* Table scope to access. */ + uint32_t table_scope:5; + /* Unused field [3] */ + uint32_t unused1:3; + /* + * This value identifies the number of cache lines to invalidate. A + * FMT_ERR is reported if the value is not in the range of [1, 4]. + */ + uint32_t data_size:3; + /* Unused field [1] */ + uint32_t unused2:1; + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + uint32_t cache_option:4; + /* + * A 32B index into the table identified by (TABLE_TYPE, TABLE_SCOPE): + */ + uint32_t table_index:26; + /* Unused field [6] */ + uint32_t unused3:6; +}; + +/** + * EM_SEARCH_CMD: This command supplies an exact match entry of 1-4 32B + * words to search for in the exact match table. CFA first computes the + * hash value of the key in the entry, and determines the static bucket + * address to search from the hash and the (EM_BUCKETS, EM_SIZE) for + * TABLE_SCOPE. It then searches that static bucket chain for an entry + * with a matching key (the LREC in the command entry is ignored). If a + * matching entry is found, CFA reports OK status in the completion. + * Otherwise, assuming no errors abort the search before it completes, + * it reports EM_MISS status. + */ +struct cfa_mpc_em_search_cmd { + /* + * This value selects the format for the mid-path command for the CFA. + */ + uint32_t opcode:8; + #define EM_SEARCH_CMD_OPCODE_EM_SEARCH 8 + /* Unused field [8] */ + uint32_t unused0:8; + /* Table scope to access. */ + uint32_t table_scope:5; + /* Unused field [3] */ + uint32_t unused1:3; + /* + * Number of 32B units in access. If value is outside the range [1, 4], + * CFA aborts processing and reports FMT_ERR status. + */ + uint32_t data_size:3; + /* Unused field [1] */ + uint32_t unused2:1; + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + uint32_t cache_option:4; + /* Unused field [96] */ + uint32_t unused3_1:32; + uint32_t unused3_2:32; + uint32_t unused3_3:32; +}; + +/** + * EM_INSERT_CMD: This command supplies an exact match entry of 1-4 32B + * words to insert in the exact match table. CFA first computes the hash + * value of the key in the entry, and determines the static bucket + * address to search from the hash and the (EM_BUCKETS, EM_SIZE) for + * TABLE_SCOPE. It then writes the 1-4 32B words of the exact match + * entry starting at the TABLE_INDEX location in the command. When the + * entry write completes, it searches the static bucket chain for an + * existing entry with a key matching the key in the insert entry (the + * LREC does not need to match). If a matching entry is found: * If + * REPLACE=0, the CFA aborts the insert and returns EM_DUPLICATE status. + * * If REPLACE=1, the CFA overwrites the matching entry with the new + * entry. REPLACED_ENTRY=1 in the completion in this case to signal that + * an entry was replaced. The location of the entry is provided in the + * completion. If no match is found, CFA adds the new entry to the + * lowest unused entry in the tail bucket. If the current tail bucket is + * full, this requires adding a new bucket to the tail. Then entry is + * then inserted at entry number 0. TABLE_INDEX2 provides the address of + * the new tail bucket, if needed. If set to 0, the insert is aborted + * and returns EM_ABORT status instead of adding a new bucket to the + * tail. CHAIN_UPD in the completion indicates whether a new bucket was + * added (1) or not (0). For locked scopes, if the read of the static + * bucket gives a locked scope miss error, indicating that the address + * is not in the cache, the static bucket is assumed empty. In this + * case, TAI creates a new bucket, setting entry 0 to the new entry + * fields and initializing all other fields to 0. It writes this new + * bucket to the static bucket address, which installs it in the cache. + */ +struct cfa_mpc_em_insert_cmd { + /* + * This value selects the format for the mid-path command for the CFA. + */ + uint32_t opcode:8; + #define EM_INSERT_CMD_OPCODE_EM_INSERT 9 + /* Unused field [4] */ + uint32_t unused0:4; + /* + * Sets the OPTION field on the cache interface to use write-through for + * EM entry writes while processing EM_INSERT commands. For all other + * cases (inluding EM_INSERT bucket writes), the OPTION field is set by + * the CACHE_OPTION and CACHE_OPTION2 fields. + */ + uint32_t write_through:1; + /* Unused field [3] */ + uint32_t unused1:3; + /* Table scope to access. */ + uint32_t table_scope:5; + /* Unused field [3] */ + uint32_t unused2:3; + /* + * Number of 32B units in access. If value is outside the range [1, 4], + * CFA aborts processing and reports FMT_ERR status. + */ + uint32_t data_size:3; + /* Unused field [1] */ + uint32_t unused3:1; + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + uint32_t cache_option:4; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. Starting + * address to write exact match entry being inserted. + */ + uint32_t table_index:26; + /* Unused field [2] */ + uint32_t unused4:2; + /* + * Determines setting of OPTION field for all cache write requests for + * EM_INSERT, EM_DELETE, and EM_CHAIN commands. CFA does not support + * posted write requests. Therefore, CACHE_OPTION2[1] must be set to 0. + */ + uint32_t cache_option2:4; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. Only used + * when no duplicate entry is found and the tail bucket in the chain + * searched has no unused entries. In this case, TABLE_INDEX2 provides + * the index to the 32B dynamic bucket to add to the tail of the chain + * (it is the new tail bucket). In this case, the CFA first writes + * TABLE_INDEX2 with a new bucket: * Entry 0 of the bucket sets the + * HASH_MSBS computed from the hash and ENTRY_PTR to TABLE_INDEX. * + * Entries 1-5 of the bucket set HASH_MSBS and ENTRY_PTR to 0. * CHAIN=0 + * and CHAIN_PTR is set to CHAIN_PTR from to original tail bucket to + * maintain the background chaining. CFA then sets CHAIN=1 and + * CHAIN_PTR=TABLE_INDEX2 in the original tail bucket to link the new + * bucket to the chain. CHAIN_UPD=1 in the completion to signal that the + * new bucket at TABLE_INDEX2 was added to the tail of the chain. + */ + uint32_t table_index2:26; + /* Unused field [5] */ + uint32_t unused5:5; + /* + * Only used if an entry is found whose key matches the exact match + * entry key in the command: * REPLACE=0: The insert is aborted and + * EM_DUPLICATE status is returned, signaling that the insert failed. + * The index of the matching entry that blocked the insertion is + * returned in the completion. * REPLACE=1: The matching entry is + * replaced with that from the command (ENTRY_PTR in the bucket is + * overwritten with TABLE_INDEX from the command). HASH_MSBS for the + * entry number never changes in this case since it had to match the new + * entry key HASH_MSBS to match. When an entry is replaced, + * REPLACED_ENTRY=1 in the completion and the index of the matching + * entry is returned in the completion so that software can de-allocate + * the entry. + */ + uint32_t replace:1; + /* Unused field [32] */ + uint32_t unused6:32; +}; + +/** + * EM_DELETE_CMD: This command searches for an exact match entry index + * in the static bucket chain and deletes it if found. TABLE_INDEX give + * the entry index to delete and TABLE_INDEX2 gives the static bucket + * index. If a matching entry is found: * If the matching entry is the + * last valid entry in the tail bucket, its entry fields (HASH_MSBS and + * ENTRY_PTR) are set to 0 to delete the entry. * If the matching entry + * is not the last valid entry in the tail bucket, the entry fields from + * that last entry are moved to the matching entry, and the fields of + * that last entry are set to 0. * If any of the previous processing + * results in the tail bucket not having any valid entries, the tail + * bucket is the static bucket, the scope is a locked scope, and + * CHAIN_PTR=0, hardware evicts the static bucket from the cache and the + * completion signals this case with CHAIN_UPD=1. * If any of the + * previous processing results in the tail bucket not having any valid + * entries, and the tail bucket is not the static bucket, the tail + * bucket is removed from the chain. In this case, the penultimate + * bucket in the chain becomes the tail bucket. It has CHAIN set to 0 to + * unlink the tail bucket, and CHAIN_PTR set to that from the original + * tail bucket to preserve background chaining. The completion signals + * this case with CHAIN_UPD=1 and returns the index to the bucket + * removed so that software can de-allocate it. CFA returns OK status if + * the entry was successfully deleted. Otherwise, it returns EM_MISS + * status assuming there were no errors that caused processing to be + * aborted. + */ +struct cfa_mpc_em_delete_cmd { + /* + * This value selects the format for the mid-path command for the CFA. + */ + uint32_t opcode:8; + #define EM_DELETE_CMD_OPCODE_EM_DELETE 10 + /* Unused field [4] */ + uint32_t unused0:4; + /* + * Sets the OPTION field on the cache interface to use write-through for + * EM entry writes while processing EM_INSERT commands. For all other + * cases (inluding EM_INSERT bucket writes), the OPTION field is set by + * the CACHE_OPTION and CACHE_OPTION2 fields. + */ + uint32_t write_through:1; + /* Unused field [3] */ + uint32_t unused1:3; + /* Table scope to access. */ + uint32_t table_scope:5; + /* Unused field [7] */ + uint32_t unused2:7; + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + uint32_t cache_option:4; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. Entry index + * to delete. + */ + uint32_t table_index:26; + /* Unused field [2] */ + uint32_t unused3:2; + /* + * Determines setting of OPTION field for all cache write requests for + * EM_INSERT, EM_DELETE, and EM_CHAIN commands. CFA does not support + * posted write requests. Therefore, CACHE_OPTION2[1] must be set to 0. + */ + uint32_t cache_option2:4; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. Static + * bucket address for bucket chain. + */ + uint32_t table_index2:26; + /* Unused field [6] */ + uint32_t unused4:6; +}; + +/** + * EM_CHAIN_CMD: This command updates CHAIN_PTR in the tail bucket of a + * static bucket chain, supplying both the static bucket and the new + * CHAIN_PTR value. TABLE_INDEX is the new CHAIN_PTR value and + * TABLE_INDEX2[23:0] is the static bucket. This command provides + * software a means to update background chaining coherently with other + * bucket updates. The value of CHAIN is unaffected (stays at 0). For + * locked scopes, if the static bucket is the tail bucket, it is empty + * (all of its ENTRY_PTR values are 0), and TABLE_INDEX=0 (the CHAIN_PTR + * is being set to 0), instead of updating the static bucket it is + * evicted from the cache. In this case, CHAIN_UPD=1 in the completion. + */ +struct cfa_mpc_em_chain_cmd { + /* + * This value selects the format for the mid-path command for the CFA. + */ + uint32_t opcode:8; + #define EM_CHAIN_CMD_OPCODE_EM_CHAIN 11 + /* Unused field [4] */ + uint32_t unused0:4; + /* + * Sets the OPTION field on the cache interface to use write-through for + * EM entry writes while processing EM_INSERT commands. For all other + * cases (inluding EM_INSERT bucket writes), the OPTION field is set by + * the CACHE_OPTION and CACHE_OPTION2 fields. + */ + uint32_t write_through:1; + /* Unused field [3] */ + uint32_t unused1:3; + /* Table scope to access. */ + uint32_t table_scope:5; + /* Unused field [7] */ + uint32_t unused2:7; + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + uint32_t cache_option:4; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. New + * CHAIN_PTR to write to tail bucket. + */ + uint32_t table_index:26; + /* Unused field [2] */ + uint32_t unused3:2; + /* + * Determines setting of OPTION field for all cache write requests for + * EM_INSERT, EM_DELETE, and EM_CHAIN commands. CFA does not support + * posted write requests. Therefore, CACHE_OPTION2[1] must be set to 0. + */ + uint32_t cache_option2:4; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. Static + * bucket address for bucket chain. + */ + uint32_t table_index2:26; + /* Unused field [6] */ + uint32_t unused4:6; +}; + +/** + * READ_CMP: When no errors, teturns 1-4 consecutive 32B words from the + * TABLE_INDEX within the TABLE_SCOPE specified in the command, writing + * them to HOST_ADDRESS from the command. + */ +struct cfa_mpc_read_cmp { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + uint32_t type:6; + #define READ_CMP_TYPE_MID_PATH_SHORT 30 + /* Unused field [2] */ + uint32_t unused0:2; + /* The command processing status. */ + uint32_t status:4; + #define READ_CMP_STATUS_OK 0 + #define READ_CMP_STATUS_UNSPRT_ERR 1 + #define READ_CMP_STATUS_FMT_ERR 2 + #define READ_CMP_STATUS_SCOPE_ERR 3 + #define READ_CMP_STATUS_ADDR_ERR 4 + #define READ_CMP_STATUS_CACHE_ERR 5 + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + uint32_t mp_client:4; + #define READ_CMP_MP_CLIENT_TE_CFA 2 + #define READ_CMP_MP_CLIENT_RE_CFA 3 + /* OPCODE from the command. */ + uint32_t opcode:8; + #define READ_CMP_OPCODE_READ 0 + /* + * The length of the DMA that accompanies the completion in units of + * DWORDs (32b). Valid values are [0, 128]. A value of zero indicates + * that there is no DMA that accompanies the completion. + */ + uint32_t dma_length:8; + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + uint32_t opaque:32; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + uint32_t v:1; + /* Unused field [3] */ + uint32_t unused1:3; + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + uint32_t hash_msb:12; + /* Unused field [4] */ + uint32_t unused2:4; + /* TABLE_TYPE from the command. */ + uint32_t table_type:4; + #define READ_CMP_TABLE_TYPE_ACTION 0 + #define READ_CMP_TABLE_TYPE_EM 1 + /* TABLE_SCOPE from the command. */ + uint32_t table_scope:5; + /* Unused field [3] */ + uint32_t unused3:3; + /* TABLE_INDEX from the command. */ + uint32_t table_index:26; + /* Unused field [6] */ + uint32_t unused4:6; +}; + +/** + * WRITE_CMP: Returns status of the write of 1-4 consecutive 32B words + * starting at TABLE_INDEX in the table specified by (TABLE_TYPE, + * TABLE_SCOPE). + */ +struct cfa_mpc_write_cmp { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + uint32_t type:6; + #define WRITE_CMP_TYPE_MID_PATH_SHORT 30 + /* Unused field [2] */ + uint32_t unused0:2; + /* The command processing status. */ + uint32_t status:4; + #define WRITE_CMP_STATUS_OK 0 + #define WRITE_CMP_STATUS_UNSPRT_ERR 1 + #define WRITE_CMP_STATUS_FMT_ERR 2 + #define WRITE_CMP_STATUS_SCOPE_ERR 3 + #define WRITE_CMP_STATUS_ADDR_ERR 4 + #define WRITE_CMP_STATUS_CACHE_ERR 5 + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + uint32_t mp_client:4; + #define WRITE_CMP_MP_CLIENT_TE_CFA 2 + #define WRITE_CMP_MP_CLIENT_RE_CFA 3 + /* OPCODE from the command. */ + uint32_t opcode:8; + #define WRITE_CMP_OPCODE_WRITE 1 + /* Unused field [8] */ + uint32_t unused1:8; + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + uint32_t opaque:32; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + uint32_t v:1; + /* Unused field [3] */ + uint32_t unused2:3; + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + uint32_t hash_msb:12; + /* Unused field [4] */ + uint32_t unused3:4; + /* TABLE_TYPE from the command. */ + uint32_t table_type:4; + #define WRITE_CMP_TABLE_TYPE_ACTION 0 + #define WRITE_CMP_TABLE_TYPE_EM 1 + /* TABLE_SCOPE from the command. */ + uint32_t table_scope:5; + /* Unused field [3] */ + uint32_t unused4:3; + /* TABLE_INDEX from the command. */ + uint32_t table_index:26; + /* Unused field [6] */ + uint32_t unused5:6; +}; + +/** + * READ_CLR_CMP: When no errors, returns 1 32B word from TABLE_INDEX in + * the table specified by (TABLE_TYPE, TABLE_SCOPE). The data returned + * is the value prior to the clear. + */ +struct cfa_mpc_read_clr_cmp { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + uint32_t type:6; + #define READ_CLR_CMP_TYPE_MID_PATH_SHORT 30 + /* Unused field [2] */ + uint32_t unused0:2; + /* The command processing status. */ + uint32_t status:4; + #define READ_CLR_CMP_STATUS_OK 0 + #define READ_CLR_CMP_STATUS_UNSPRT_ERR 1 + #define READ_CLR_CMP_STATUS_FMT_ERR 2 + #define READ_CLR_CMP_STATUS_SCOPE_ERR 3 + #define READ_CLR_CMP_STATUS_ADDR_ERR 4 + #define READ_CLR_CMP_STATUS_CACHE_ERR 5 + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + uint32_t mp_client:4; + #define READ_CLR_CMP_MP_CLIENT_TE_CFA 2 + #define READ_CLR_CMP_MP_CLIENT_RE_CFA 3 + /* OPCODE from the command. */ + uint32_t opcode:8; + #define READ_CLR_CMP_OPCODE_READ_CLR 2 + /* + * The length of the DMA that accompanies the completion in units of + * DWORDs (32b). Valid values are [0, 128]. A value of zero indicates + * that there is no DMA that accompanies the completion. + */ + uint32_t dma_length:8; + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + uint32_t opaque:32; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + uint32_t v:1; + /* Unused field [3] */ + uint32_t unused1:3; + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + uint32_t hash_msb:12; + /* Unused field [4] */ + uint32_t unused2:4; + /* TABLE_TYPE from the command. */ + uint32_t table_type:4; + #define READ_CLR_CMP_TABLE_TYPE_ACTION 0 + #define READ_CLR_CMP_TABLE_TYPE_EM 1 + /* TABLE_SCOPE from the command. */ + uint32_t table_scope:5; + /* Unused field [3] */ + uint32_t unused3:3; + /* TABLE_INDEX from the command. */ + uint32_t table_index:26; + /* Unused field [6] */ + uint32_t unused4:6; +}; + +/** + * INVALIDATE_CMP: Returns status for INVALIDATE commands. + */ +struct cfa_mpc_invalidate_cmp { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + uint32_t type:6; + #define INVALIDATE_CMP_TYPE_MID_PATH_SHORT 30 + /* Unused field [2] */ + uint32_t unused0:2; + /* The command processing status. */ + uint32_t status:4; + #define INVALIDATE_CMP_STATUS_OK 0 + #define INVALIDATE_CMP_STATUS_UNSPRT_ERR 1 + #define INVALIDATE_CMP_STATUS_FMT_ERR 2 + #define INVALIDATE_CMP_STATUS_SCOPE_ERR 3 + #define INVALIDATE_CMP_STATUS_ADDR_ERR 4 + #define INVALIDATE_CMP_STATUS_CACHE_ERR 5 + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + uint32_t mp_client:4; + #define INVALIDATE_CMP_MP_CLIENT_TE_CFA 2 + #define INVALIDATE_CMP_MP_CLIENT_RE_CFA 3 + /* OPCODE from the command. */ + uint32_t opcode:8; + #define INVALIDATE_CMP_OPCODE_INVALIDATE 5 + /* Unused field [8] */ + uint32_t unused1:8; + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + uint32_t opaque:32; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + uint32_t v:1; + /* Unused field [3] */ + uint32_t unused2:3; + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + uint32_t hash_msb:12; + /* Unused field [4] */ + uint32_t unused3:4; + /* TABLE_TYPE from the command. */ + uint32_t table_type:4; + #define INVALIDATE_CMP_TABLE_TYPE_ACTION 0 + #define INVALIDATE_CMP_TABLE_TYPE_EM 1 + /* TABLE_SCOPE from the command. */ + uint32_t table_scope:5; + /* Unused field [3] */ + uint32_t unused4:3; + /* TABLE_INDEX from the command. */ + uint32_t table_index:26; + /* Unused field [6] */ + uint32_t unused5:6; +}; + +/** + * EM_SEARCH_CMP: For OK status, returns the index of the matching entry + * found for the EM key supplied in the command. Returns EM_MISS status + * if no match was found. + */ +struct cfa_mpc_em_search_cmp { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + uint32_t type:6; + #define EM_SEARCH_CMP_TYPE_MID_PATH_LONG 31 + /* Unused field [2] */ + uint32_t unused0:2; + /* The command processing status. */ + uint32_t status:4; + #define EM_SEARCH_CMP_STATUS_OK 0 + #define EM_SEARCH_CMP_STATUS_UNSPRT_ERR 1 + #define EM_SEARCH_CMP_STATUS_FMT_ERR 2 + #define EM_SEARCH_CMP_STATUS_SCOPE_ERR 3 + #define EM_SEARCH_CMP_STATUS_ADDR_ERR 4 + #define EM_SEARCH_CMP_STATUS_CACHE_ERR 5 + #define EM_SEARCH_CMP_STATUS_EM_MISS 6 + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + uint32_t mp_client:4; + #define EM_SEARCH_CMP_MP_CLIENT_TE_CFA 2 + #define EM_SEARCH_CMP_MP_CLIENT_RE_CFA 3 + /* OPCODE from the command. */ + uint32_t opcode:8; + #define EM_SEARCH_CMP_OPCODE_EM_SEARCH 8 + /* Unused field [8] */ + uint32_t unused1:8; + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + uint32_t opaque:32; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + uint32_t v1:1; + /* Unused field [3] */ + uint32_t unused2:3; + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + uint32_t hash_msb:12; + /* Unused field [8] */ + uint32_t unused3:8; + /* TABLE_SCOPE from the command. */ + uint32_t table_scope:5; + /* Unused field [3] */ + uint32_t unused4:3; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. For OK + * status, gives ENTRY_PTR[25:0] of the matching entry found. Otherwise, + * set to 0. + */ + uint32_t table_index:26; + /* Unused field [6] */ + uint32_t unused5:6; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. If the hash + * is computed (no errors during initial processing of the command), + * TABLE_INDEX2[23:0] is the static bucket address determined from the + * hash of the exact match entry key in the command and the (EM_SIZE, + * EM_BUCKETS) configuration for TABLE_SCOPE of the command. Bits 25:24 + * in this case are set to 0. For any other status, it is always 0. + */ + uint32_t table_index2:26; + /* Unused field [38] */ + uint32_t unused6_1:6; + uint32_t unused6_2:32; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + uint32_t v2:1; + /* Unused field [31] */ + uint32_t unused7:31; + /* + * BKT_NUM is the bucket number in chain of the tail bucket after + * finishing processing the command, except when the command stops + * processing before the tail bucket. NUM_ENTRIES is the number of valid + * entries in the BKT_NUM bucket. The following describes the cases + * where BKT_NUM and NUM_ENTRIES are not for the tail bucket after + * finishing processing of the command: * For UNSPRT_ERR, FMT_ERR, + * SCOPE_ERR, or ADDR_ERR completion status, BKT_NUM will be set to 0. * + * For CACHE_ERR completion status, BKT_NUM will be set to the bucket + * number that was last read without error. If ERR=1 in the response to + * the static bucket read, BKT_NUM and NUM_ENTRIES are set to 0. The + * static bucket is number 0, BKT_NUM increments for each new bucket in + * the chain, and saturates at 255. Therefore, if the value is 255, + * BKT_NUM may or may not be accurate. In this case, though, NUM_ENTRIES + * will still be the correct value as described above for the bucket. + */ + uint32_t bkt_num:8; + /* See BKT_NUM description. */ + uint32_t num_entries:3; + /* Unused field [21] */ + uint32_t unused8:21; +}; + +/** + * EM_INSERT_CMP: OK status indicates that the exact match entry from + * the command was successfully inserted. EM_DUPLICATE status indicates + * that the insert was aborted because an entry with the same exact + * match key was found and REPLACE=0 in the command. EM_ABORT status + * indicates that no duplicate was found, the tail bucket in the chain + * was full, and TABLE_INDEX2=0. No changes are made to the database in + * this case. TABLE_INDEX is the starting address at which to insert the + * exact match entry (from the command). TABLE_INDEX2 is the address at + * which to insert a new bucket at the tail of the static bucket chain + * if needed (from the command). CHAIN_UPD=1 if a new bucket was added + * at this address. TABLE_INDEX3 is the static bucket address for the + * chain, determined from hashing the exact match entry. Software needs + * this address and TABLE_INDEX in order to delete the entry using an + * EM_DELETE command. TABLE_INDEX4 is the index of an entry found that + * had a matching exact match key to the command entry key. If no + * matching entry was found, it is set to 0. There are two cases when + * there is a matching entry, depending on REPLACE from the command: * + * REPLACE=0: EM_DUPLICATE status is reported and the insert is aborted. + * Software can use the static bucket address (TABLE_INDEX3[23:0]) and + * the matching entry (TABLE_INDEX4) in an EM_DELETE command if it + * wishes to explicity delete the matching entry. * REPLACE=1: + * REPLACED_ENTRY=1 to signal that the entry at TABLE_INDEX4 was + * replaced by the insert entry. REPLACED_ENTRY will only be 1 if + * reporting OK status in this case. Software can de-allocate the entry + * at TABLE_INDEX4. + */ +struct cfa_mpc_em_insert_cmp { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + uint32_t type:6; + #define EM_INSERT_CMP_TYPE_MID_PATH_LONG 31 + /* Unused field [2] */ + uint32_t unused0:2; + /* The command processing status. */ + uint32_t status:4; + #define EM_INSERT_CMP_STATUS_OK 0 + #define EM_INSERT_CMP_STATUS_UNSPRT_ERR 1 + #define EM_INSERT_CMP_STATUS_FMT_ERR 2 + #define EM_INSERT_CMP_STATUS_SCOPE_ERR 3 + #define EM_INSERT_CMP_STATUS_ADDR_ERR 4 + #define EM_INSERT_CMP_STATUS_CACHE_ERR 5 + #define EM_INSERT_CMP_STATUS_EM_DUPLICATE 7 + #define EM_INSERT_CMP_STATUS_EM_ABORT 9 + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + uint32_t mp_client:4; + #define EM_INSERT_CMP_MP_CLIENT_TE_CFA 2 + #define EM_INSERT_CMP_MP_CLIENT_RE_CFA 3 + /* OPCODE from the command. */ + uint32_t opcode:8; + #define EM_INSERT_CMP_OPCODE_EM_INSERT 9 + /* Unused field [8] */ + uint32_t unused1:8; + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + uint32_t opaque:32; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + uint32_t v1:1; + /* Unused field [3] */ + uint32_t unused2:3; + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + uint32_t hash_msb:12; + /* Unused field [8] */ + uint32_t unused3:8; + /* TABLE_SCOPE from the command. */ + uint32_t table_scope:5; + /* Unused field [3] */ + uint32_t unused4:3; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX + * from the command, which is the starting address at which to insert + * the exact match entry. + */ + uint32_t table_index:26; + /* Unused field [6] */ + uint32_t unused5:6; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX2 + * from the command, which is the index for the new tail bucket to add + * if needed (CHAIN_UPD=1 if it was used). + */ + uint32_t table_index2:26; + /* Unused field [6] */ + uint32_t unused6:6; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. If the hash + * is computed (no errors during initial processing of the command), + * TABLE_INDEX2[23:0] is the static bucket address determined from the + * hash of the exact match entry key in the command and the (EM_SIZE, + * EM_BUCKETS) configuration for TABLE_SCOPE of the command. Bits 25:24 + * in this case are set to 0. For any other status, it is always 0. + */ + uint32_t table_index3:26; + /* Unused field [6] */ + uint32_t unused7:6; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + uint32_t v2:1; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. ENTRY_PTR of + * matching entry found. Set to 0 if no matching entry found. If + * REPLACED_ENTRY=1, that indicates a matching entry was found and + * REPLACE=1 in the command. In this case, the matching entry was + * replaced by the new entry in the command and this index can therefore + * by de-allocated. + */ + uint32_t table_index4:26; + /* Unused field [5] */ + uint32_t unused8:5; + /* + * BKT_NUM is the bucket number in chain of the tail bucket after + * finishing processing the command, except when the command stops + * processing before the tail bucket. NUM_ENTRIES is the number of valid + * entries in the BKT_NUM bucket. The following describes the cases + * where BKT_NUM and NUM_ENTRIES are not for the tail bucket after + * finishing processing of the command: * For UNSPRT_ERR, FMT_ERR, + * SCOPE_ERR, or ADDR_ERR completion status, BKT_NUM will be set to 0. * + * For CACHE_ERR completion status, BKT_NUM will be set to the bucket + * number that was last read without error. If ERR=1 in the response to + * the static bucket read, BKT_NUM and NUM_ENTRIES are set to 0. The + * static bucket is number 0, BKT_NUM increments for each new bucket in + * the chain, and saturates at 255. Therefore, if the value is 255, + * BKT_NUM may or may not be accurate. In this case, though, NUM_ENTRIES + * will still be the correct value as described above for the bucket. + */ + uint32_t bkt_num:8; + /* See BKT_NUM description. */ + uint32_t num_entries:3; + /* + * Specifies if the chain was updated while processing the command: Set + * to 1 when a new bucket is added to the tail of the static bucket + * chain at TABLE_INDEX2. This occurs if and only if the insert requires + * adding a new entry and the tail bucket is full. If set to 0, + * TABLE_INDEX2 was not used and is therefore still free. + */ + uint32_t chain_upd:1; + /* + * Set to 1 if a matching entry was found and REPLACE=1 in command. In + * the case, the entry starting at TABLE_INDEX4 was replaced and can + * therefore be de-allocated. Otherwise, this flag is set to 0. + */ + uint32_t replaced_entry:1; + /* Unused field [19] */ + uint32_t unused9:19; +}; + +/** + * EM_DELETE_CMP: OK status indicates that an ENTRY_PTR matching + * TABLE_INDEX was found in the static bucket chain specified and was + * therefore deleted. EM_MISS status indicates that no match was found. + * TABLE_INDEX is from the command. It is the index of the entry to + * delete. TABLE_INDEX2 is from the command. It is the static bucket + * address. TABLE_INDEX3 is the index of the tail bucket of the static + * bucket chain prior to processing the command. TABLE_INDEX4 is the + * index of the tail bucket of the static bucket chain after processing + * the command. If CHAIN_UPD=1 and TABLE_INDEX4==TABLE_INDEX2, the + * static bucket was the tail bucket, it became empty after the delete, + * the scope is a locked scope, and CHAIN_PTR was 0. In this case, the + * static bucket has been evicted from the cache. Otherwise, if + * CHAIN_UPD=1, the original tail bucket given by TABLE_INDEX3 was + * removed from the chain because it went empty. It can therefore be de- + * allocated. + */ +struct cfa_mpc_em_delete_cmp { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + uint32_t type:6; + #define EM_DELETE_CMP_TYPE_MID_PATH_LONG 31 + /* Unused field [2] */ + uint32_t unused0:2; + /* The command processing status. */ + uint32_t status:4; + #define EM_DELETE_CMP_STATUS_OK 0 + #define EM_DELETE_CMP_STATUS_UNSPRT_ERR 1 + #define EM_DELETE_CMP_STATUS_FMT_ERR 2 + #define EM_DELETE_CMP_STATUS_SCOPE_ERR 3 + #define EM_DELETE_CMP_STATUS_ADDR_ERR 4 + #define EM_DELETE_CMP_STATUS_CACHE_ERR 5 + #define EM_DELETE_CMP_STATUS_EM_MISS 6 + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + uint32_t mp_client:4; + #define EM_DELETE_CMP_MP_CLIENT_TE_CFA 2 + #define EM_DELETE_CMP_MP_CLIENT_RE_CFA 3 + /* OPCODE from the command. */ + uint32_t opcode:8; + #define EM_DELETE_CMP_OPCODE_EM_DELETE 10 + /* Unused field [8] */ + uint32_t unused1:8; + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + uint32_t opaque:32; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + uint32_t v1:1; + /* Unused field [3] */ + uint32_t unused2:3; + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + uint32_t hash_msb:12; + /* Unused field [8] */ + uint32_t unused3:8; + /* TABLE_SCOPE from the command. */ + uint32_t table_scope:5; + /* Unused field [3] */ + uint32_t unused4:3; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX + * from the command, which is the index of the entry to delete. + */ + uint32_t table_index:26; + /* Unused field [6] */ + uint32_t unused5:6; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX2 + * from the command. + */ + uint32_t table_index2:26; + /* Unused field [6] */ + uint32_t unused6:6; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. For OK or + * EM_MISS status, the index of the tail bucket of the chain prior to + * processing the command. If CHAIN_UPD=1, the bucket was removed and + * this index can be de-allocated. For other status values, it is set to + * 0. + */ + uint32_t table_index3:26; + /* Unused field [6] */ + uint32_t unused7:6; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + uint32_t v2:1; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. For OK or + * EM_MISS status, the index of the tail bucket of the chain prior to + * after the command. If CHAIN_UPD=0 (always for EM_MISS status), it is + * always equal to TABLE_INDEX3 as the chain was not updated. For other + * status values, it is set to 0. + */ + uint32_t table_index4:26; + /* Unused field [5] */ + uint32_t unused8:5; + /* + * BKT_NUM is the bucket number in chain of the tail bucket after + * finishing processing the command, except when the command stops + * processing before the tail bucket. NUM_ENTRIES is the number of valid + * entries in the BKT_NUM bucket. The following describes the cases + * where BKT_NUM and NUM_ENTRIES are not for the tail bucket after + * finishing processing of the command: * For UNSPRT_ERR, FMT_ERR, + * SCOPE_ERR, or ADDR_ERR completion status, BKT_NUM will be set to 0. * + * For CACHE_ERR completion status, BKT_NUM will be set to the bucket + * number that was last read without error. If ERR=1 in the response to + * the static bucket read, BKT_NUM and NUM_ENTRIES are set to 0. The + * static bucket is number 0, BKT_NUM increments for each new bucket in + * the chain, and saturates at 255. Therefore, if the value is 255, + * BKT_NUM may or may not be accurate. In this case, though, NUM_ENTRIES + * will still be the correct value as described above for the bucket. + */ + uint32_t bkt_num:8; + /* See BKT_NUM description. */ + uint32_t num_entries:3; + /* + * Specifies if the chain was updated while processing the command: Set + * to 1 when a bucket is removed from the static bucket chain. This + * occurs if after the delete, the tail bucket is a dynamic bucket and + * no longer has any valid entries. In this case, software should de- + * allocate the dynamic bucket at TABLE_INDEX3. It is also set to 1 when + * the static bucket is evicted, which only occurs for locked scopes. + * See the EM_DELETE command description for details. + */ + uint32_t chain_upd:1; + /* Unused field [20] */ + uint32_t unused9:20; +}; + +/** + * EM_CHAIN_CMP: OK status indicates that the CHAIN_PTR of the tail + * bucket was successfully updated. TABLE_INDEX is from the command. It + * is the value of the new CHAIN_PTR. TABLE_INDEX2 is from the command. + * TABLE_INDEX3 is the index of the tail bucket of the static bucket + * chain. + */ +struct cfa_mpc_em_chain_cmp { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + uint32_t type:6; + #define EM_CHAIN_CMP_TYPE_MID_PATH_LONG 31 + /* Unused field [2] */ + uint32_t unused0:2; + /* The command processing status. */ + uint32_t status:4; + #define EM_CHAIN_CMP_STATUS_OK 0 + #define EM_CHAIN_CMP_STATUS_UNSPRT_ERR 1 + #define EM_CHAIN_CMP_STATUS_FMT_ERR 2 + #define EM_CHAIN_CMP_STATUS_SCOPE_ERR 3 + #define EM_CHAIN_CMP_STATUS_ADDR_ERR 4 + #define EM_CHAIN_CMP_STATUS_CACHE_ERR 5 + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + uint32_t mp_client:4; + #define EM_CHAIN_CMP_MP_CLIENT_TE_CFA 2 + #define EM_CHAIN_CMP_MP_CLIENT_RE_CFA 3 + /* OPCODE from the command. */ + uint32_t opcode:8; + #define EM_CHAIN_CMP_OPCODE_EM_CHAIN 11 + /* Unused field [8] */ + uint32_t unused1:8; + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + uint32_t opaque:32; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + uint32_t v1:1; + /* Unused field [3] */ + uint32_t unused2:3; + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + uint32_t hash_msb:12; + /* Unused field [8] */ + uint32_t unused3:8; + /* TABLE_SCOPE from the command. */ + uint32_t table_scope:5; + /* Unused field [3] */ + uint32_t unused4:3; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX + * from the command, which is the new CHAIN_PTR for the tail bucket of + * the static bucket chain. + */ + uint32_t table_index:26; + /* Unused field [6] */ + uint32_t unused5:6; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX2 + * from the command. + */ + uint32_t table_index2:26; + /* Unused field [6] */ + uint32_t unused6:6; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. For OK + * status, the index of the tail bucket of the chain. Otherwise, set to + * 0. + */ + uint32_t table_index3:26; + /* Unused field [6] */ + uint32_t unused7:6; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + uint32_t v2:1; + /* Unused field [31] */ + uint32_t unused8:31; + /* + * BKT_NUM is the bucket number in chain of the tail bucket after + * finishing processing the command, except when the command stops + * processing before the tail bucket. NUM_ENTRIES is the number of valid + * entries in the BKT_NUM bucket. The following describes the cases + * where BKT_NUM and NUM_ENTRIES are not for the tail bucket after + * finishing processing of the command: * For UNSPRT_ERR, FMT_ERR, + * SCOPE_ERR, or ADDR_ERR completion status, BKT_NUM will be set to 0. * + * For CACHE_ERR completion status, BKT_NUM will be set to the bucket + * number that was last read without error. If ERR=1 in the response to + * the static bucket read, BKT_NUM and NUM_ENTRIES are set to 0. The + * static bucket is number 0, BKT_NUM increments for each new bucket in + * the chain, and saturates at 255. Therefore, if the value is 255, + * BKT_NUM may or may not be accurate. In this case, though, NUM_ENTRIES + * will still be the correct value as described above for the bucket. + */ + uint32_t bkt_num:8; + /* See BKT_NUM description. */ + uint32_t num_entries:3; + /* + * Set to 1 when the scope is a locked scope, the tail bucket is the + * static bucket, the bucket is empty (all of its ENTRY_PTR values are + * 0), and TABLE_INDEX=0 in the command. In this case, the static bucket + * is evicted. For all other cases, it is set to 0. + */ + uint32_t chain_upd:1; + /* Unused field [20] */ + uint32_t unused9:20; +}; + +/* clang-format on */ + +#endif /* _CFA_P70_MPC_STRUCTS_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/p70/cfa_bld_p70_mpc.c b/drivers/net/bnxt/hcapi/cfa_v3/bld/p70/cfa_bld_p70_mpc.c new file mode 100644 index 0000000000..b65c37e86e --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/p70/cfa_bld_p70_mpc.c @@ -0,0 +1,927 @@ +/**************************************************************************** + * Copyright(c) 2021 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_bld_p70_mpc.c + * + * @brief CFA phase 7.0 api implementation to build CFA Mid-path commands + * and Parse CFA Mid-path Command completions + */ + +#define COMP_ID BLD + +#include +#include +#include "sys_util.h" +#include "cfa_trace.h" +#include "cfa_types.h" +#include "cfa_p70.h" +#include "cfa_bld_p70_mpc.h" +#include "cfa_bld_p70_mpc_defs.h" +#include "cfa_p70_mpc_structs.h" + +/* CFA MPC client ids */ +#define MP_CLIENT_TE_CFA READ_CMP_MP_CLIENT_TE_CFA +#define MP_CLIENT_RE_CFA READ_CMP_MP_CLIENT_RE_CFA + +/* MPC Client id check in CFA completion messages */ +#define ASSERT_CFA_MPC_CLIENT_ID(MPCID) \ + do { \ + if ((MPCID) != MP_CLIENT_TE_CFA && \ + (MPCID) != MP_CLIENT_RE_CFA) { \ + CFA_LOG_WARN( \ + "Unexpected MPC client id in response: %d\n", \ + (MPCID)); \ + } \ + } while (0) + +#ifdef NXT_ENV_DEBUG +#define ASSERT_RETURN(ERRNO) CFA_LOG_ERR("Returning error: %d\n", (ERRNO)) +#else +#define ASSERT_RETURN(ERRNO) +#endif + +/** + * MPC header definition + */ +struct mpc_header { + uint32_t type : 6; + uint32_t flags : 10; + uint32_t len : 16; + uint32_t opaque; + uint64_t unused; +}; + +/* + * For successful completions of read and read-clear MPC CFA + * commands, the responses will contain this dma info structure + * following the cfa_mpc_read(|clr)_cmp structure and preceding + * the actual data read from the cache. + */ +struct mpc_cr_short_dma_data { + uint32_t dma_length : 8; + uint32_t unused0 : 24; + uint32_t dma_addr0; + uint32_t dma_addr1; +}; + +/** Add MPC header information to MPC command message */ +static int fill_mpc_header(uint8_t *cmd, uint32_t size, uint32_t opaque_val) +{ + struct mpc_header hdr = { + .opaque = opaque_val, + }; + + if (size < sizeof(struct mpc_header)) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + memcpy(cmd, &hdr, sizeof(hdr)); + + return 0; +} + +/** Compose Table read-clear message */ +static int compose_mpc_read_clr_msg(uint8_t *cmd_buff, uint32_t *cmd_buff_len, + struct cfa_mpc_cache_axs_params *parms) +{ + struct cfa_mpc_read_clr_cmd *cmd; + struct cfa_mpc_cache_read_params *rd_parms = &parms->read; + uint32_t cmd_size = + sizeof(struct mpc_header) + sizeof(struct cfa_mpc_read_clr_cmd); + + if (parms->data_size != 1) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (parms->tbl_type >= CFA_HW_TABLE_MAX) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (*cmd_buff_len < cmd_size) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + cmd = (struct cfa_mpc_read_clr_cmd *)(cmd_buff + + sizeof(struct mpc_header)); + + /* Populate CFA MPC command header */ + memset(cmd, 0, sizeof(struct cfa_mpc_read_clr_cmd)); + cmd->opcode = READ_CLR_CMD_OPCODE_READ_CLR; + cmd->table_type = parms->tbl_type; + cmd->table_scope = parms->tbl_scope; + cmd->data_size = parms->data_size; + cmd->table_index = parms->tbl_index; + cmd->host_address_1 = (uint32_t)rd_parms->host_address; + cmd->host_address_2 = (uint32_t)(rd_parms->host_address >> 32); + switch (rd_parms->mode) { + case CFA_MPC_RD_EVICT: + cmd->cache_option = CACHE_READ_CLR_OPTION_EVICT; + break; + default: + case CFA_MPC_RD_NORMAL: + cmd->cache_option = CACHE_READ_CLR_OPTION_NORMAL; + break; + } + cmd->clear_mask = rd_parms->clear_mask; + *cmd_buff_len = cmd_size; + + return 0; +} + +/** Compose Table read message */ +static int compose_mpc_read_msg(uint8_t *cmd_buff, uint32_t *cmd_buff_len, + struct cfa_mpc_cache_axs_params *parms) +{ + struct cfa_mpc_read_cmd *cmd; + struct cfa_mpc_cache_read_params *rd_parms = &parms->read; + uint32_t cmd_size = + sizeof(struct mpc_header) + sizeof(struct cfa_mpc_read_cmd); + + if (parms->data_size < 1 || parms->data_size > 4) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (parms->tbl_type >= CFA_HW_TABLE_MAX) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (*cmd_buff_len < cmd_size) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + cmd = (struct cfa_mpc_read_cmd *)(cmd_buff + sizeof(struct mpc_header)); + + /* Populate CFA MPC command header */ + memset(cmd, 0, sizeof(struct cfa_mpc_read_cmd)); + cmd->opcode = READ_CMD_OPCODE_READ; + cmd->table_type = parms->tbl_type; + cmd->table_scope = parms->tbl_scope; + cmd->data_size = parms->data_size; + cmd->table_index = parms->tbl_index; + cmd->host_address_1 = (uint32_t)rd_parms->host_address; + cmd->host_address_2 = (uint32_t)(rd_parms->host_address >> 32); + switch (rd_parms->mode) { + case CFA_MPC_RD_EVICT: + cmd->cache_option = CACHE_READ_OPTION_EVICT; + break; + case CFA_MPC_RD_DEBUG_LINE: + cmd->cache_option = CACHE_READ_OPTION_DEBUG_LINE; + break; + case CFA_MPC_RD_DEBUG_TAG: + cmd->cache_option = CACHE_READ_OPTION_DEBUG_TAG; + break; + default: + case CFA_MPC_RD_NORMAL: + cmd->cache_option = CACHE_READ_OPTION_NORMAL; + break; + } + *cmd_buff_len = cmd_size; + + return 0; +} + +/** Compose Table write message */ +static int compose_mpc_write_msg(uint8_t *cmd_buff, uint32_t *cmd_buff_len, + struct cfa_mpc_cache_axs_params *parms) +{ + struct cfa_mpc_write_cmd *cmd; + struct cfa_mpc_cache_write_params *wr_parms = &parms->write; + uint32_t cmd_size = sizeof(struct mpc_header) + + sizeof(struct cfa_mpc_write_cmd) + + parms->data_size * MPC_CFA_CACHE_ACCESS_UNIT_SIZE; + + if (parms->data_size < 1 || parms->data_size > 4) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (parms->tbl_type >= CFA_HW_TABLE_MAX) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (!parms->write.data_ptr) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (*cmd_buff_len < cmd_size) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + cmd = (struct cfa_mpc_write_cmd *)(cmd_buff + + sizeof(struct mpc_header)); + + /* Populate CFA MPC command header */ + memset(cmd, 0, sizeof(struct cfa_mpc_write_cmd)); + cmd->opcode = WRITE_CMD_OPCODE_