From patchwork Thu Aug 22 18:53:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Soumyadeep Hore X-Patchwork-Id: 143327 X-Patchwork-Delegate: bruce.richardson@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C89784584B; Thu, 22 Aug 2024 21:48:20 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D0B8842F6B; Thu, 22 Aug 2024 21:48:16 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by mails.dpdk.org (Postfix) with ESMTP id 61B9F42F67 for ; Thu, 22 Aug 2024 21:48:15 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724356096; x=1755892096; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AfDzN/1wulD6TsJ8VBzCn/FE1MrnTQeLKaGv6usS++Y=; b=ip9NLGFe/pkd1WdqU6DEuR//TnMAV+Xkxniv0awBjPz50/y5N7O5wygS OpsdjGBL7z4K2U1pLPtl4ZVizmzg/9NCkYX+60AywCDpwL6gi6FawfyQt eE4Xs0ariOdMxbemGj5wV+CY3FiEmwS/oe7OlHfjA4ZajCm0Hyp6HcdUf App63KQ40FB2mMBxOXSApvjLlmeG2xUPJxi7O/4jg3Uszeh2M5P6B/HU8 mBerLwNhEKZluAHyNiYpmaQpIj2cB//0m2tR7wJA5k3CRvLZYeVVoBaZS eC80NA0eBEnQFeoEwvu6g5Oghxrzy011BJGakKKIJ1mxVgBv9bXsa38wB A==; X-CSE-ConnectionGUID: cpTbpbylSLC7Hyvec2oZOw== X-CSE-MsgGUID: 3htqk+FfRZWAPculeByiWg== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="22979665" X-IronPort-AV: E=Sophos;i="6.10,168,1719903600"; d="scan'208";a="22979665" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 12:48:15 -0700 X-CSE-ConnectionGUID: ApuyJ5qoS3WMb6qhansFNA== X-CSE-MsgGUID: ZbXk62SYRqaYu7Ror79qUQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,168,1719903600"; d="scan'208";a="92301375" Received: from unknown (HELO npf-hyd-clx-03..) ([10.145.170.182]) by orviesa002.jf.intel.com with ESMTP; 22 Aug 2024 12:48:13 -0700 From: Soumyadeep Hore To: bruce.richardson@intel.com, ian.stokes@intel.com, aman.deep.singh@intel.com Cc: dev@dpdk.org, shaiq.wani@intel.com Subject: [PATCH v2 01/12] net/ice: use correct format specifiers for unsigned ints Date: Thu, 22 Aug 2024 18:53:35 +0000 Message-ID: <20240822185346.221885-2-soumyadeep.hore@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240822185346.221885-1-soumyadeep.hore@intel.com> References: <20240822095612.216214-1-soumyadeep.hore@intel.com> <20240822185346.221885-1-soumyadeep.hore@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Firmware was giving a number for the MSIX vectors that was way too big and obviously not right. Because of the wrong format specifier, this big number ended up looking like a tiny negative number in the logs. This was fixed by using the right format specifier everywhere it's needed. Signed-off-by: Soumyadeep Hore --- drivers/net/ice/base/ice_common.c | 54 +++++++++++++++---------------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 536392776f..48d5fff42a 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -2365,48 +2365,48 @@ ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, switch (cap) { case ICE_AQC_CAPS_VALID_FUNCTIONS: caps->valid_functions = number; - ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, + ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = 0x%x\n", prefix, caps->valid_functions); break; case ICE_AQC_CAPS_DCB: caps->dcb = (number == 1); caps->active_tc_bitmap = logical_id; caps->maxtc = phys_id; - ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); - ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, + ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %u\n", prefix, caps->dcb); + ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = 0x%x\n", prefix, caps->active_tc_bitmap); - ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); + ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %u\n", prefix, caps->maxtc); break; case ICE_AQC_CAPS_RSS: caps->rss_table_size = number; caps->rss_table_entry_width = logical_id; - ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, + ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %u\n", prefix, caps->rss_table_size); - ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, + ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %u\n", prefix, caps->rss_table_entry_width); break; case ICE_AQC_CAPS_RXQS: caps->num_rxq = number; caps->rxq_first_id = phys_id; - ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, + ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %u\n", prefix, caps->num_rxq); - ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, + ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %u\n", prefix, caps->rxq_first_id); break; case ICE_AQC_CAPS_TXQS: caps->num_txq = number; caps->txq_first_id = phys_id; - ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, + ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %u\n", prefix, caps->num_txq); - ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, + ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %u\n", prefix, caps->txq_first_id); break; case ICE_AQC_CAPS_MSIX: caps->num_msix_vectors = number; caps->msix_vector_first_id = phys_id; - ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, + ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %u\n", prefix, caps->num_msix_vectors); - ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, + ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %u\n", prefix, caps->msix_vector_first_id); break; case ICE_AQC_CAPS_NVM_MGMT: @@ -2433,7 +2433,7 @@ ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, break; case ICE_AQC_CAPS_MAX_MTU: caps->max_mtu = number; - ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", + ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %u\n", prefix, caps->max_mtu); break; case ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE: @@ -2467,15 +2467,15 @@ ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, caps->ext_topo_dev_img_ver_schema[index] = (phys_id & ICE_EXT_TOPO_DEV_IMG_VER_SCHEMA) != 0; ice_debug(hw, ICE_DBG_INIT, - "%s: ext_topo_dev_img_ver_high[%d] = %d\n", + "%s: ext_topo_dev_img_ver_high[%d] = %u\n", prefix, index, caps->ext_topo_dev_img_ver_high[index]); ice_debug(hw, ICE_DBG_INIT, - "%s: ext_topo_dev_img_ver_low[%d] = %d\n", + "%s: ext_topo_dev_img_ver_low[%d] = %u\n", prefix, index, caps->ext_topo_dev_img_ver_low[index]); ice_debug(hw, ICE_DBG_INIT, - "%s: ext_topo_dev_img_part_num[%d] = %d\n", + "%s: ext_topo_dev_img_part_num[%d] = %u\n", prefix, index, caps->ext_topo_dev_img_part_num[index]); ice_debug(hw, ICE_DBG_INIT, @@ -2531,7 +2531,7 @@ ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) if (hw->dev_caps.num_funcs > 4) { /* Max 4 TCs per port */ caps->maxtc = 4; - ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", + ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %u (based on #ports)\n", caps->maxtc); } } @@ -2549,9 +2549,9 @@ ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, struct ice_aqc_list_caps_elem *cap) { func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); - ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", + ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %u\n", LE32_TO_CPU(cap->number)); - ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", + ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %u\n", func_p->guar_num_vsi); } @@ -2636,9 +2636,9 @@ ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) GLQF_FD_SIZE_FD_BSIZE_S; func_p->fd_fltr_best_effort = val; - ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", + ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %u\n", func_p->fd_fltr_guar); - ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", + ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %u\n", func_p->fd_fltr_best_effort); } @@ -2728,7 +2728,7 @@ ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, u32 number = LE32_TO_CPU(cap->number); dev_p->num_funcs = ice_hweight32(number); - ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", + ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %u\n", dev_p->num_funcs); hw->logical_pf_id = ice_func_id_to_logical_id(number, hw->pf_id); @@ -2749,7 +2749,7 @@ ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, u32 number = LE32_TO_CPU(cap->number); dev_p->num_vsi_allocd_to_host = number; - ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", + ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %u\n", dev_p->num_vsi_allocd_to_host); } @@ -2822,7 +2822,7 @@ ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, u32 number = LE32_TO_CPU(cap->number); dev_p->num_flow_director_fltr = number; - ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", + ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %u\n", dev_p->num_flow_director_fltr); } @@ -2841,7 +2841,7 @@ ice_parse_nac_topo_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, dev_p->nac_topo.mode = LE32_TO_CPU(cap->number); dev_p->nac_topo.id = LE32_TO_CPU(cap->phys_id) & ICE_NAC_TOPO_ID_M; - ice_info(hw, "PF is configured in %s mode with IP instance ID %d\n", + ice_info(hw, "PF is configured in %s mode with IP instance ID %u\n", (dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M) ? "primary" : "secondary", dev_p->nac_topo.id); @@ -2849,7 +2849,7 @@ ice_parse_nac_topo_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M)); ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_dual = %d\n", !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_DUAL_M)); - ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology id = %d\n", + ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology id = %u\n", dev_p->nac_topo.id); } @@ -2927,7 +2927,7 @@ ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, default: /* Don't list common capabilities as unknown */ if (!found) - ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", + ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%u]: 0x%x\n", i, cap); break; } From patchwork Thu Aug 22 18:53:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Soumyadeep Hore X-Patchwork-Id: 143328 X-Patchwork-Delegate: bruce.richardson@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D39834584B; Thu, 22 Aug 2024 21:48:27 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1575742F71; Thu, 22 Aug 2024 21:48:20 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by mails.dpdk.org (Postfix) with ESMTP id 1899942F71; Thu, 22 Aug 2024 21:48:17 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724356099; x=1755892099; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=igI137w5B1jTu4Q2k6vzezRUMi8FOCRrJhXpkUuHLng=; b=CPrLbw6ONpYFFA5Fi5Y0DhLeURE9FJC9pCpSxPsVM1GU+47lUvTLZ+09 47wFUEudVsk9iSJDLEOWXWHNi5PNegdeX6nKl5KiPC6V3/+AXm++InkAi 1OgrhgtFjO16JcTM77JyR/MpE1iFD+rlm4jb2sTtbWUxDpHqnhF2Kz7Ws hCEogm8CnXYvzzcbUd9aS3cXPuYSPyxCs13JxSz6BxVcHzhfwcnR3nkmS lRmzWAQ1XSTEN+DrkI5CW+YlbAyUFqM3WDMtw1D/lF+lCsYa6Z+stoiGK B0ekTnPdVcX+VGQRRu5Me4VHfX/TYDzrNBWJnOsEFmnUkco4/AoJpmn4v Q==; X-CSE-ConnectionGUID: EBNF1cp5Q168Ajq3fcdNJw== X-CSE-MsgGUID: mplro+u+Tyq4mrsnJUmWmQ== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="22979667" X-IronPort-AV: E=Sophos;i="6.10,168,1719903600"; d="scan'208";a="22979667" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 12:48:18 -0700 X-CSE-ConnectionGUID: 7oFmvhM6SAmQPfPp9F+iSg== X-CSE-MsgGUID: qiUvHcP7TX2extH5+f6OBQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,168,1719903600"; d="scan'208";a="92301386" Received: from unknown (HELO npf-hyd-clx-03..) ([10.145.170.182]) by orviesa002.jf.intel.com with ESMTP; 22 Aug 2024 12:48:15 -0700 From: Soumyadeep Hore To: bruce.richardson@intel.com, ian.stokes@intel.com, aman.deep.singh@intel.com Cc: dev@dpdk.org, shaiq.wani@intel.com, stable@dpdk.org Subject: [PATCH v2 02/12] net/ice: updates for ptp init in E825C Date: Thu, 22 Aug 2024 18:53:36 +0000 Message-ID: <20240822185346.221885-3-soumyadeep.hore@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240822185346.221885-1-soumyadeep.hore@intel.com> References: <20240822095612.216214-1-soumyadeep.hore@intel.com> <20240822185346.221885-1-soumyadeep.hore@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The implementation was done incorrectly assuming the TS PLL parameters would be similar to E822/E823 devices. Fix it by using proper values. Define access to SB (sideband) for second PHY and CGU devices in case of E825C devices. In E825C soft straps of CGU cannot be read from HW, and therefore it must be hard coded to default values. Fixes: 620ecf247c22 ("net/ice/base: support E825-C Tx clock changing") Cc: stable@dpdk.org Signed-off-by: Soumyadeep Hore --- drivers/net/ice/base/ice_cgu_regs.h | 19 +++++++ drivers/net/ice/base/ice_common.c | 4 ++ drivers/net/ice/base/ice_ptp_consts.h | 75 +++++++++++++++++++++++++++ drivers/net/ice/base/ice_ptp_hw.c | 75 ++++++++++++++++++--------- drivers/net/ice/base/ice_ptp_hw.h | 21 ++++++++ 5 files changed, 169 insertions(+), 25 deletions(-) diff --git a/drivers/net/ice/base/ice_cgu_regs.h b/drivers/net/ice/base/ice_cgu_regs.h index f24f4746dd..4d831959bf 100644 --- a/drivers/net/ice/base/ice_cgu_regs.h +++ b/drivers/net/ice/base/ice_cgu_regs.h @@ -64,6 +64,17 @@ union nac_cgu_dword11_e825c { u32 val; }; +#define NAC_CGU_DWORD16_E825C 0x40 +union nac_cgu_dword16_e825c { + struct { + u32 synce_remndr : 6; + u32 synce_phlmt_en : 1; + u32 misc13 : 17; + u32 tspll_ck_refclkfreq : 8; + } field; + u32 val; +}; + #define NAC_CGU_DWORD19 0x4c union nac_cgu_dword19 { struct { @@ -120,6 +131,13 @@ union nac_cgu_dword23_e825c { u32 val; }; +union nac_cgu_dword24_e825c { + struct { + u32 tspll_fbdiv_frac : 32; + } field; + u32 val; +}; + #define NAC_CGU_DWORD24 0x60 union nac_cgu_dword24 { struct { @@ -134,6 +152,7 @@ union nac_cgu_dword24 { u32 val; }; + #define TSPLL_CNTR_BIST_SETTINGS 0x344 union tspll_cntr_bist_settings { struct { diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 48d5fff42a..4750076b7d 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -2585,6 +2585,10 @@ ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); clk_freq = (number & ICE_TS_CLK_FREQ_M) >> ICE_TS_CLK_FREQ_S; + if (ice_is_e825c(hw)) { + info->clk_src = ICE_CLK_SRC_TCX0; + clk_freq = ICE_TIME_REF_FREQ_156_250; + } if (clk_freq < NUM_ICE_TIME_REF_FREQ) { info->time_ref = (enum ice_time_ref_freq)clk_freq; } else { diff --git a/drivers/net/ice/base/ice_ptp_consts.h b/drivers/net/ice/base/ice_ptp_consts.h index bd0258f437..d1f4fd2738 100644 --- a/drivers/net/ice/base/ice_ptp_consts.h +++ b/drivers/net/ice/base/ice_ptp_consts.h @@ -157,6 +157,81 @@ const struct ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = { }, }; +const +struct ice_cgu_pll_params_e825c e825c_cgu_params[NUM_ICE_TIME_REF_FREQ] = { + /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */ + { + /* tspll_ck_refclkfreq */ + 0x19, + /* tspll_ndivratio */ + 1, + /* tspll_fbdiv_intgr */ + 320, + /* tspll_fbdiv_frac */ + 0, + }, + + /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */ + { + /* tspll_ck_refclkfreq */ + 0x29, + /* tspll_ndivratio */ + 3, + /* tspll_fbdiv_intgr */ + 195, + /* tspll_fbdiv_frac */ + 1342177280, + }, + + /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */ + { + /* tspll_ck_refclkfreq */ + 0x3E, + /* tspll_ndivratio */ + 2, + /* tspll_fbdiv_intgr */ + 128, + /* tspll_fbdiv_frac */ + 0, + }, + + /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */ + { + /* tspll_ck_refclkfreq */ + 0x33, + /* tspll_ndivratio */ + 3, + /* tspll_fbdiv_intgr */ + 156, + /* tspll_fbdiv_frac */ + 1073741824, + }, + + /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */ + { + /* tspll_ck_refclkfreq */ + 0x1F, + /* tspll_ndivratio */ + 5, + /* tspll_fbdiv_intgr */ + 256, + /* tspll_fbdiv_frac */ + 0, + }, + + /* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */ + { + /* tspll_ck_refclkfreq */ + 0x52, + /* tspll_ndivratio */ + 3, + /* tspll_fbdiv_intgr */ + 97, + /* tspll_fbdiv_frac */ + 2818572288, + }, +}; + /* * struct ice_vernier_info_e822 * diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 004f659eae..e574ae6d4f 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -362,10 +362,11 @@ ice_cfg_cgu_pll_e825c(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq, enum ice_clk_src *clk_src) { union tspll_ro_lock_e825c ro_lock; + union nac_cgu_dword16_e825c dw16; union nac_cgu_dword23_e825c dw23; + union nac_cgu_dword24_e825c dw24; union nac_cgu_dword19 dw19; union nac_cgu_dword22 dw22; - union nac_cgu_dword24 dw24; union nac_cgu_dword9 dw9; int err; @@ -380,8 +381,8 @@ ice_cfg_cgu_pll_e825c(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq, } if (*clk_src == ICE_CLK_SRC_TCX0 && - *clk_freq != ICE_TIME_REF_FREQ_25_000) { - ice_warn(hw, "TCX0 only supports 25 MHz frequency\n"); + *clk_freq != ICE_TIME_REF_FREQ_156_250) { + ice_warn(hw, "TCX0 only supports 156.25 MHz frequency\n"); return ICE_ERR_PARAM; } @@ -393,6 +394,10 @@ ice_cfg_cgu_pll_e825c(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq, if (err) return err; + err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD16_E825C, &dw16.val); + if (err) + return err; + err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val); if (err) return err; @@ -403,7 +408,7 @@ ice_cfg_cgu_pll_e825c(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq, /* Log the current clock configuration */ ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", - dw24.field.ts_pll_enable ? "enabled" : "disabled", + dw23.field.ts_pll_enable ? "enabled" : "disabled", ice_clk_src_str(dw23.field.time_ref_sel), ice_clk_freq_str(dw9.field.time_ref_freq_sel), ro_lock.field.plllock_true_lock_cri ? "locked" : "unlocked"); @@ -418,19 +423,43 @@ ice_cfg_cgu_pll_e825c(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq, return err; } - /* Set the frequency */ + if (dw9.field.time_sync_en) { + dw9.field.time_sync_en = 0; + + err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, + dw9.val); + if (err) + return err; + } + + /* Set the frequency and enable the correct receiver */ dw9.field.time_ref_freq_sel = *clk_freq; + if (*clk_src == ICE_CLK_SRC_TCX0) { + dw9.field.time_ref_en = 0; + dw9.field.clk_eref0_en = 1; + } else { + dw9.field.time_ref_en = 1; + dw9.field.clk_eref0_en = 0; + } + dw9.field.time_sync_en = 1; err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val); if (err) return err; + /* Choose the referenced frequency */ + dw16.field.tspll_ck_refclkfreq = + e825c_cgu_params[*clk_freq].tspll_ck_refclkfreq; + err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD16_E825C, dw16.val); + if (err) + return err; + /* Configure the TS PLL feedback divisor */ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val); if (err) return err; - dw19.field.tspll_fbdiv_intgr = e822_cgu_params[*clk_freq].feedback_div; - dw19.field.tspll_ndivratio = 1; + dw19.field.tspll_fbdiv_intgr = e825c_cgu_params[*clk_freq].tspll_fbdiv_intgr; + dw19.field.tspll_ndivratio = e825c_cgu_params[*clk_freq].tspll_ndivratio; err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val); if (err) @@ -441,7 +470,8 @@ ice_cfg_cgu_pll_e825c(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq, if (err) return err; - dw22.field.time1588clk_div = e822_cgu_params[*clk_freq].post_pll_div; + /* those two are constant for E825C */ + dw22.field.time1588clk_div = 5; dw22.field.time1588clk_sel_div2 = 0; err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val); @@ -453,14 +483,14 @@ ice_cfg_cgu_pll_e825c(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq, if (err) return err; - dw23.field.ref1588_ck_div = e822_cgu_params[*clk_freq].refclk_pre_div; + dw23.field.ref1588_ck_div = REF1588_CK_DIV; dw23.field.time_ref_sel = *clk_src; err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val); if (err) return err; - dw24.field.tspll_fbdiv_frac = e822_cgu_params[*clk_freq].frac_n_div; + dw24.field.tspll_fbdiv_frac = e825c_cgu_params[*clk_freq].tspll_fbdiv_frac; err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val); if (err) @@ -486,11 +516,9 @@ ice_cfg_cgu_pll_e825c(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq, } /* Log the current clock configuration */ - ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", - dw24.field.ts_pll_enable ? "enabled" : "disabled", + ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- clk_src %s, clk_freq %s\n", ice_clk_src_str(dw23.field.time_ref_sel), - ice_clk_freq_str(dw9.field.time_ref_freq_sel), - ro_lock.field.plllock_true_lock_cri ? "locked" : "unlocked"); + ice_clk_freq_str(dw9.field.time_ref_freq_sel)); *clk_freq = (enum ice_time_ref_freq)dw9.field.time_ref_freq_sel; *clk_src = (enum ice_clk_src)dw23.field.time_ref_sel; @@ -770,7 +798,10 @@ static int ice_init_cgu_e82x(struct ice_hw *hw) ice_warn(hw, "Failed to lock TS PLL to predefined frequency. Retrying with fallback frequency.\n"); /* Try to lock to internal 25 MHz TCXO as a fallback */ - time_ref_freq = ICE_TIME_REF_FREQ_25_000; + if (hw->phy_model == ICE_PHY_ETH56G) + time_ref_freq = ICE_TIME_REF_FREQ_156_250; + else + time_ref_freq = ICE_TIME_REF_FREQ_25_000; clk_src = ICE_CLK_SRC_TCX0; if (ice_is_e825c(hw)) err = ice_cfg_cgu_pll_e825c(hw, &time_ref_freq, @@ -2328,21 +2359,15 @@ ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port) */ static void ice_sb_access_ena_eth56g(struct ice_hw *hw, bool enable) { - u32 regval; - /* Enable reading and writing switch and PHY registers over the * sideband queue. */ -#define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1) -#define PF_SB_REM_DEV_CTL_PHY0 BIT(2) - regval = rd32(hw, PF_SB_REM_DEV_CTL); + u32 regval = rd32(hw, PF_SB_REM_DEV_CTL); + if (enable) - regval |= (PF_SB_REM_DEV_CTL_SWITCH_READ | - PF_SB_REM_DEV_CTL_PHY0); + regval |= (cgu | eth56g_dev_0 | eth56g_dev_1); else - regval &= ~(PF_SB_REM_DEV_CTL_SWITCH_READ | - PF_SB_REM_DEV_CTL_PHY0); - + regval &= ~(cgu | eth56g_dev_0 | eth56g_dev_1); wr32(hw, PF_SB_REM_DEV_CTL, regval); } diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index 9357dfd327..5d6636c0d1 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -122,6 +122,27 @@ struct ice_cgu_pll_params_e822 { extern const struct ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ]; +/** + * struct ice_cgu_pll_params_e825c + * @tspll_ck_refclkfreq: tspll_ck_refclkfreq selection + * @tspll_ndivratio: ndiv ratio that goes directly to the pll + * @tspll_fbdiv_intgr: TS PLL integer feedback divide + * @tspll_fbdiv_frac: TS PLL fractional feedback divide + * + * Clock Generation Unit parameters used to program the PLL based on the + * selected TIME_REF/TCXO frequency. + */ +struct ice_cgu_pll_params_e825c { + u32 tspll_ck_refclkfreq; + u32 tspll_ndivratio; + u32 tspll_fbdiv_intgr; + u32 tspll_fbdiv_frac; +}; + +extern const struct +ice_cgu_pll_params_e825c e825c_cgu_params[NUM_ICE_TIME_REF_FREQ]; +#define REF1588_CK_DIV 0 + /* Table of constants related to possible TIME_REF sources */ extern const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ]; From patchwork Thu Aug 22 18:53:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Soumyadeep Hore X-Patchwork-Id: 143329 X-Patchwork-Delegate: bruce.richardson@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BE0BD4584B; Thu, 22 Aug 2024 21:48:38 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2BB3E42F89; Thu, 22 Aug 2024 21:48:23 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by mails.dpdk.org (Postfix) with ESMTP id 3E0AA42F76 for ; Thu, 22 Aug 2024 21:48:20 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724356101; x=1755892101; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yzUtvDhndvRKb8Bu5q9U9fOjTDoS4xcKbK+iLj8Vxgo=; b=NRMy85Uxfjsi+UFF+Ro7MhvnFzvT13YhUvO4XRV4pZZU6djWLvhVBWQE sFLsCO8FF1DvAqtXErGL0E4ntKpqwvgpaU9hw7wvxc62sKdXAiSvu6un0 quTztF2g7N6nNxGnkRVb4u5RIbCdVmedJjv1PhE3115WkDvXtnqIrMi1g KmGvukjtwdPpofaujKqDpvvXm5L+lFCyh3qwXyhYzRB5MpXaft6rW7iMo asm5i++uy+ADB4oL5cyWiKFyTFNgDnyuopUWKaiyPbZAj+9M8gYiUKQNR 2V5shiyrOfRQ8lWUkaWNCX6u6TA1O1NPdmEVBLNBnWuFeA+BZDiqDMtm/ g==; X-CSE-ConnectionGUID: lkeKqoktR0yfrvDHatjWOw== X-CSE-MsgGUID: mx15rxRwTaaocTtDECvfvQ== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="22979670" X-IronPort-AV: E=Sophos;i="6.10,168,1719903600"; d="scan'208";a="22979670" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 12:48:20 -0700 X-CSE-ConnectionGUID: r6BrAf/fStmauZZjZURpnQ== X-CSE-MsgGUID: /HlPqqUJS4KltK9rOKY9Xw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,168,1719903600"; d="scan'208";a="92301392" Received: from unknown (HELO npf-hyd-clx-03..) ([10.145.170.182]) by orviesa002.jf.intel.com with ESMTP; 22 Aug 2024 12:48:18 -0700 From: Soumyadeep Hore To: bruce.richardson@intel.com, ian.stokes@intel.com, aman.deep.singh@intel.com Cc: dev@dpdk.org, shaiq.wani@intel.com Subject: [PATCH v2 03/12] net/ice: add new tag definitions Date: Thu, 22 Aug 2024 18:53:37 +0000 Message-ID: <20240822185346.221885-4-soumyadeep.hore@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240822185346.221885-1-soumyadeep.hore@intel.com> References: <20240822095612.216214-1-soumyadeep.hore@intel.com> <20240822185346.221885-1-soumyadeep.hore@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE* defines to unified_manual.inc to make them available externally. Signed-off-by: Soumyadeep Hore --- drivers/net/ice/base/ice_hw_autogen.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/net/ice/base/ice_hw_autogen.h b/drivers/net/ice/base/ice_hw_autogen.h index 3753cc77c2..5877ddb5e8 100644 --- a/drivers/net/ice/base/ice_hw_autogen.h +++ b/drivers/net/ice/base/ice_hw_autogen.h @@ -13,6 +13,20 @@ #define PRTMAC_CTL_RX_PAUSE_ENABLE_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_RX_PAUSE_ENABLE : E800_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE) #define PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_S_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_S : E800_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_S) #define PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_M : E800_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_M) +#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE(_i) (0x000FD000 + ((_i) * 64)) /*_i=0-7 Rst Src:CORER*/ +#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_MAX_INDEX 7 +#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_START_S 0 +#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_START_M MAKEMASK(0x3F, 0) +#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_END_S 6 +#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_END_M MAKEMASK(0x3F, 6) +#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_VM_VF_TYPE_S 12 +#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_VM_VF_TYPE_M MAKEMASK(0x3, 12) +#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_VM_VF_NUM_S 14 +#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_VM_VF_NUM_M MAKEMASK(0x3FF, 14) +#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_PF_NUM_S 24 +#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_PF_NUM_M MAKEMASK(0x7, 24) +#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_ENABLE_S 31 +#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_ENABLE_M BIT(31) #define GL_HIDA(_i) (0x00082000 + ((_i) * 4)) #define GL_HIBA(_i) (0x00081000 + ((_i) * 4)) #define GL_HICR 0x00082040 From patchwork Thu Aug 22 18:53:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Soumyadeep Hore X-Patchwork-Id: 143330 X-Patchwork-Delegate: bruce.richardson@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 037A54584B; Thu, 22 Aug 2024 21:48:46 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 54B4D42F97; Thu, 22 Aug 2024 21:48:24 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by mails.dpdk.org (Postfix) with ESMTP id 1D3B442F7E for ; Thu, 22 Aug 2024 21:48:21 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724356102; x=1755892102; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vMA047NQAw8nCTmvhb2VtOcpilkawQnq2VTMGzChbSQ=; b=awM2C1SQh4kS/S0c9j545nMAvApT6ZHXkEOVRiiypYNZGP9ZuzXN+xHv 088P/WwurSP24nXi6o9zhn3V/39sw6Xcvt5enFN39D1C4/rQLpV3c3NP/ JbvhZ7UoZOAPgHqX9QOgyVf9ZCFQJdz0EsClXXouRnMw4WaA+S0omujLZ qh56n48m7b5UR8qOzmBAMZufnKrCmSzdgdF04Ty9B8Be5U2Q9Jx9iUHLg NcfxOWrrESYe40eGdIIpSSA6GTiGPxHnwis5EYUv3zLrANex1DXZek2DO YASrIEW0cvIPfV5PcIfgXMEjPpY6XuZGCH/DoK3aWmbcQU5dppN7N6wv0 Q==; X-CSE-ConnectionGUID: DEky+wX7Tp639mO4md1Q2A== X-CSE-MsgGUID: 6q0GjPrgSBCa3vUZRhyFxA== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="22979672" X-IronPort-AV: E=Sophos;i="6.10,168,1719903600"; d="scan'208";a="22979672" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 12:48:22 -0700 X-CSE-ConnectionGUID: 7VZdUS4dSZ6HQVW7NY9VgA== X-CSE-MsgGUID: laO8OIbIQaeTHoUcs3t2bg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,168,1719903600"; d="scan'208";a="92301402" Received: from unknown (HELO npf-hyd-clx-03..) ([10.145.170.182]) by orviesa002.jf.intel.com with ESMTP; 22 Aug 2024 12:48:20 -0700 From: Soumyadeep Hore To: bruce.richardson@intel.com, ian.stokes@intel.com, aman.deep.singh@intel.com Cc: dev@dpdk.org, shaiq.wani@intel.com Subject: [PATCH v2 04/12] net/ice: avoid reading past end of PFA Date: Thu, 22 Aug 2024 18:53:38 +0000 Message-ID: <20240822185346.221885-5-soumyadeep.hore@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240822185346.221885-1-soumyadeep.hore@intel.com> References: <20240822095612.216214-1-soumyadeep.hore@intel.com> <20240822185346.221885-1-soumyadeep.hore@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The ice_get_pfa_module_tlv() function iterates over the Preserved Fields Area to read data from the Shadow RAM, including the Part Board Assembly data, among others. If the specific TLV being requested is not found in the current NVM, the code will read past the end of the PFA, misinterpreting the last word of the PFA and the word just after the PFA as another TLV. This typically results in one extra iteration before the length check of the while loop is triggered. Signed-off-by: Soumyadeep Hore --- drivers/net/ice/base/ice_nvm.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c index 5e982de4b5..0124cef04c 100644 --- a/drivers/net/ice/base/ice_nvm.c +++ b/drivers/net/ice/base/ice_nvm.c @@ -498,11 +498,16 @@ ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len, ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n"); return status; } - /* Starting with first TLV after PFA length, iterate through the list + /* The Preserved Fields Area contains a sequence of TLVs which define + * its contents. The PFA length includes all of the TLVs, plus its + * initial length word itself, *and* one final word at the end of all + * of the TLVs. + * + * Starting with first TLV after PFA length, iterate through the list * of TLVs to find the requested one. */ next_tlv = pfa_ptr + 1; - while (next_tlv < ((u32)pfa_ptr + pfa_len)) { + while (next_tlv < ((u32)pfa_ptr + pfa_len - 1)) { u16 tlv_sub_module_type; u16 tlv_len; From patchwork Thu Aug 22 18:53:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Soumyadeep Hore X-Patchwork-Id: 143331 X-Patchwork-Delegate: bruce.richardson@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D69E94584B; Thu, 22 Aug 2024 21:48:52 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8536542F91; Thu, 22 Aug 2024 21:48:25 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by mails.dpdk.org (Postfix) with ESMTP id 22CC542F91 for ; Thu, 22 Aug 2024 21:48:23 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724356104; x=1755892104; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EH8HRfoh8LdCED85KprHW+74xGY0OkR3/84EZYhFj4E=; b=RSNz0PsHYS1zDXxrMN1tRl51632O2z/KjrVZVmFBTMuaI/1ksE3uQIsa W47MpDegDcs6DuYPICTwIiNCbY2PE9lWxrjbg0gCFwkvMRGIgwSrAEV3P cEqASZH8FTOC+LUU/paeHl+XYbmIxBp24YidzklAi/Atfng+ReRQZmWG+ xAY2kpVuDTu8eri22aWrxvv5OJVgyruixZJamGLDgSlIMwXf0gcuA1lWU XI9Nfj2IvPIfFQ42FkDL8J9CD3+6GODEn8U2jqp/8O3hOyyXcoh08B52+ lmHAplc5wBX2IAqb1ISm5BnT5W1iAZpMhaWiIgOWv0Y/sCSVkCQDzz9hq Q==; X-CSE-ConnectionGUID: DALI/LlQSFmKkmObFWkJPg== X-CSE-MsgGUID: kx1EuB8GSgenFthDdIUDDA== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="22979673" X-IronPort-AV: E=Sophos;i="6.10,168,1719903600"; d="scan'208";a="22979673" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 12:48:24 -0700 X-CSE-ConnectionGUID: FwIU78gXQ8SyLA7I+eYO8g== X-CSE-MsgGUID: v5zGpfJZRQ6XjN5HasYRdw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,168,1719903600"; d="scan'208";a="92301414" Received: from unknown (HELO npf-hyd-clx-03..) ([10.145.170.182]) by orviesa002.jf.intel.com with ESMTP; 22 Aug 2024 12:48:22 -0700 From: Soumyadeep Hore To: bruce.richardson@intel.com, ian.stokes@intel.com, aman.deep.singh@intel.com Cc: dev@dpdk.org, shaiq.wani@intel.com Subject: [PATCH v2 05/12] net/ice: update PTP init Date: Thu, 22 Aug 2024 18:53:39 +0000 Message-ID: <20240822185346.221885-6-soumyadeep.hore@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240822185346.221885-1-soumyadeep.hore@intel.com> References: <20240822095612.216214-1-soumyadeep.hore@intel.com> <20240822185346.221885-1-soumyadeep.hore@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add Bit macro to init PHY 1 for E825C devices. Signed-off-by: Soumyadeep Hore --- drivers/net/ice/base/ice_ptp_hw.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index e574ae6d4f..e61810cbdc 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -2365,9 +2365,10 @@ static void ice_sb_access_ena_eth56g(struct ice_hw *hw, bool enable) u32 regval = rd32(hw, PF_SB_REM_DEV_CTL); if (enable) - regval |= (cgu | eth56g_dev_0 | eth56g_dev_1); + regval |= (BIT(eth56g_dev_1)); else - regval &= ~(cgu | eth56g_dev_0 | eth56g_dev_1); + regval &= ~(BIT(eth56g_dev_1)); + wr32(hw, PF_SB_REM_DEV_CTL, regval); } @@ -5691,6 +5692,7 @@ void ice_ptp_init_phy_model(struct ice_hw *hw) } ice_sb_access_ena_eth56g(hw, true); + for (phy = 0; phy < hw->num_phys; phy++) if (hw->phy_addr[phy]) { int err; From patchwork Thu Aug 22 18:53:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Soumyadeep Hore X-Patchwork-Id: 143332 X-Patchwork-Delegate: bruce.richardson@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 885404584B; Thu, 22 Aug 2024 21:49:00 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D04BD42FA9; Thu, 22 Aug 2024 21:48:27 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by mails.dpdk.org (Postfix) with ESMTP id 2A2D042F9D for ; Thu, 22 Aug 2024 21:48:26 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724356106; x=1755892106; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FNkux+KL+WZ+4J/gmh58qvjXAF4Sb6bJmi83SMMQqh0=; b=QryWGIojKQxxelcW8SxgJFbvOn/W/fWOaNmSwYIVKOa3xCFFr2LNeX4H +n3BBwwQUUeug3CR4Eu4xF4V8X41TusmYNwDmukSuIi9oSSsUSatK+jfv oEuoWtPm3jQ94sHqJL9qlrne1lIyJUmT+R1xA686yfM2ona+3MaYS1xDe OW+Ty4UXNF6tdAoDa3+XNPOHRqD4auPWf1u45QbYGC2LgZAXJPsu55VLM /mMoyXA4PNsqQ6HIMqGmZjVV/U5/b0r4NT91R1VyeFivVzZS2OxATuvqm 6CJruA9Nw7H80Kbt0pXDOTEQgMNcslzpPBHZb0tpG8lSzbLi3EG9yu3gK g==; X-CSE-ConnectionGUID: 5VOExEnfR9Ss8M36nJQo0g== X-CSE-MsgGUID: uEg+NS7/RUyZsa9eUxURMQ== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="22979676" X-IronPort-AV: E=Sophos;i="6.10,168,1719903600"; d="scan'208";a="22979676" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 12:48:26 -0700 X-CSE-ConnectionGUID: KnlByoH9RCSBkeoTEoPaqQ== X-CSE-MsgGUID: BrmkAN23SVGAb4+Gr+21RA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,168,1719903600"; d="scan'208";a="92301423" Received: from unknown (HELO npf-hyd-clx-03..) ([10.145.170.182]) by orviesa002.jf.intel.com with ESMTP; 22 Aug 2024 12:48:24 -0700 From: Soumyadeep Hore To: bruce.richardson@intel.com, ian.stokes@intel.com, aman.deep.singh@intel.com Cc: dev@dpdk.org, shaiq.wani@intel.com Subject: [PATCH v2 06/12] net/ice: address compilation errors Date: Thu, 22 Aug 2024 18:53:40 +0000 Message-ID: <20240822185346.221885-7-soumyadeep.hore@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240822185346.221885-1-soumyadeep.hore@intel.com> References: <20240822095612.216214-1-soumyadeep.hore@intel.com> <20240822185346.221885-1-soumyadeep.hore@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Visual Studio C++ compiler does not pass 32->16 or 16->8 bits conversions because of possible loss of data. Signed-off-by: Soumyadeep Hore --- drivers/net/ice/base/ice_ptp_hw.c | 31 ++++--------------------------- 1 file changed, 4 insertions(+), 27 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index e61810cbdc..2a112fea12 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -1092,7 +1092,7 @@ ice_read_phy_eth56g_raw_lp(struct ice_hw *hw, u8 phy_index, u32 reg_addr, */ static int ice_phy_port_res_address_eth56g(u8 port, enum eth56g_res_type res_type, - u16 offset, u32 *address) + u32 offset, u32 *address) { u8 phy, lane; @@ -1615,7 +1615,7 @@ ice_clear_phy_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx) */ static void ice_ptp_reset_ts_memory_eth56g(struct ice_hw *hw) { - unsigned int port; + u8 port; for (port = 0; port < hw->max_phy_port; port++) { ice_write_phy_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L, @@ -2018,21 +2018,6 @@ int ice_phy_cfg_tx_offset_eth56g(struct ice_hw *hw, u8 port) return ice_write_phy_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 1); } -/** - * ice_calc_fixed_rx_offset_eth56g - Calculated the fixed Rx offset for a port - * @hw: pointer to HW struct - * @link_spd: The Link speed to calculate for - * - * Determine the fixed Rx latency for a given link speed. - */ -static u64 -ice_calc_fixed_rx_offset_eth56g(struct ice_hw *hw, - enum ice_ptp_link_spd link_spd) -{ - u64 fixed_offset = 0; - return fixed_offset; -} - /** * ice_phy_cfg_rx_offset_eth56g - Configure total Rx timestamp offset * @hw: pointer to the HW struct @@ -2055,16 +2040,8 @@ ice_calc_fixed_rx_offset_eth56g(struct ice_hw *hw, int ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port) { int err; - u64 total_offset; - - total_offset = ice_calc_fixed_rx_offset_eth56g(hw, 0); - /* Now that the total offset has been calculated, program it to the - * PHY and indicate that the Rx offset is ready. After this, - * timestamps will be enabled. - */ - err = ice_write_64b_phy_reg_eth56g(hw, port, PHY_REG_TOTAL_RX_OFFSET_L, - total_offset); + err = ice_write_64b_phy_reg_eth56g(hw, port, PHY_REG_TOTAL_RX_OFFSET_L, 0); if (err) return err; @@ -5672,7 +5649,7 @@ void ice_ptp_unlock(struct ice_hw *hw) */ void ice_ptp_init_phy_model(struct ice_hw *hw) { - unsigned int phy; + u8 phy; for (phy = 0; phy < MAX_PHYS_PER_ICE; phy++) hw->phy_addr[phy] = 0; From patchwork Thu Aug 22 18:53:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Soumyadeep Hore X-Patchwork-Id: 143333 X-Patchwork-Delegate: bruce.richardson@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 81AE34584B; Thu, 22 Aug 2024 21:49:08 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3CC1A42FB3; Thu, 22 Aug 2024 21:48:30 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by mails.dpdk.org (Postfix) with ESMTP id 71F7142FB1; Thu, 22 Aug 2024 21:48:28 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724356109; x=1755892109; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nencafhC2QsLnsdal1cSj2ubAZKY3+Vy4ATV/LRbHHk=; b=BUSMXOyO95rFgt6XclalwyMn4lodQyaU0kwZhACt9yHPmWvnxA+9qO1l Nffm6JyoUHE5Rg/+8o803shJPJrAQiV6IktYwbNVoZQ3od4soAy1YkFEj UjS6+vHLgDrR3TJ5NzMuHDJOHAaVULyZsiEl2IORZcooZDdSDBnJszadA /FPea59/fNsLsB6R5U2WNkw8WumQWTryr9PZ9besDxZ7/9fPHgiJ9I7kX Gn2WkPTl0yAO9ryjD5soOYxDzIfAkUZfOKZccXxJ5U0xkyPBX8IhiklN1 Gs+BKd5BDeKiQkvQPYNZ+6KGqAR5gMlyVxiLxCO1vlmHXb6RX6kvjcWmm g==; X-CSE-ConnectionGUID: p5+DgcK7RA+QnYE65lcgmQ== X-CSE-MsgGUID: B7Va5vT0TKmCdCLnyPZ/VA== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="22979678" X-IronPort-AV: E=Sophos;i="6.10,168,1719903600"; d="scan'208";a="22979678" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 12:48:28 -0700 X-CSE-ConnectionGUID: FNiXNS1kSlSUriNRrwLuRg== X-CSE-MsgGUID: TFr4IgiHR8aic8xTpS7mOg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,168,1719903600"; d="scan'208";a="92301440" Received: from unknown (HELO npf-hyd-clx-03..) ([10.145.170.182]) by orviesa002.jf.intel.com with ESMTP; 22 Aug 2024 12:48:26 -0700 From: Soumyadeep Hore To: bruce.richardson@intel.com, ian.stokes@intel.com, aman.deep.singh@intel.com Cc: dev@dpdk.org, shaiq.wani@intel.com, stable@dpdk.org Subject: [PATCH v2 07/12] net/ice: fix link speed for 200G Date: Thu, 22 Aug 2024 18:53:41 +0000 Message-ID: <20240822185346.221885-8-soumyadeep.hore@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240822185346.221885-1-soumyadeep.hore@intel.com> References: <20240822095612.216214-1-soumyadeep.hore@intel.com> <20240822185346.221885-1-soumyadeep.hore@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When setting PHY configuration during driver initialization, 200G link speed is not being advertised even when the PHY is capable. This is because the get PHY capabilities link speed response is being masked by ICE_AQ_LINK_SPEED_M, which does not include 200G link speed bit. Fixes: d13ad9cf1721 ("net/ice/base: add helper functions for PHY caching") Cc: stable@dpdk.org Signed-off-by: Soumyadeep Hore --- drivers/net/ice/base/ice_adminq_cmd.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index 6a89e1614a..3ec207927b 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -1624,7 +1624,7 @@ struct ice_aqc_get_link_status_data { #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 __le16 link_speed; -#define ICE_AQ_LINK_SPEED_M 0x7FF +#define ICE_AQ_LINK_SPEED_M 0xFFF #define ICE_AQ_LINK_SPEED_10MB BIT(0) #define ICE_AQ_LINK_SPEED_100MB BIT(1) #define ICE_AQ_LINK_SPEED_1000MB BIT(2) From patchwork Thu Aug 22 18:53:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Soumyadeep Hore X-Patchwork-Id: 143334 X-Patchwork-Delegate: bruce.richardson@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2D2594584B; Thu, 22 Aug 2024 21:49:15 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7822D42F95; Thu, 22 Aug 2024 21:48:32 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by mails.dpdk.org (Postfix) with ESMTP id A3B2C42F8D for ; Thu, 22 Aug 2024 21:48:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724356111; x=1755892111; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=26rfZKre3kC1RtcIlE5+0dR6bY7qKOx5mcPLtf72cjM=; b=ew76FKATdS1odycYBqoCwoorD7h2Ctx9fnFgcbnTbuts4zglcwno9R6X Qw8em+jXhJbS4cdlHY7WEARm98hrofLDkB/Pm/egCMPbH/zjFtZc0/eYD HwdxNIbnXA/qYCy1S2ZgGNxcekDUu15wLsylAiNvEibYuJBRi7YXufX2E dCAWb0AxrVfQuf4PYC0rVg9A+iWmif9Hi8V4vwkmPCxN4Ge2XXxIi+apq clscERs+iX+5g+RTVruxe+TuqCu9LJzy28v6umBUnEUPlL5z/6jZPhSlT qRloVsogJEJR+T2+lhBGArz3Vz7klVi8OwUrTjiDv0PVnBAl96lk/mVua g==; X-CSE-ConnectionGUID: QRJ3upVaTcmpJiabfaupjQ== X-CSE-MsgGUID: E64TtpLrR1Sz/fQktU21YA== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="22979680" X-IronPort-AV: E=Sophos;i="6.10,168,1719903600"; d="scan'208";a="22979680" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 12:48:30 -0700 X-CSE-ConnectionGUID: PUziMV6ZR/6ZrV6SMOf2Qg== X-CSE-MsgGUID: GD9H+RWySDKOgYCfqJoilQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,168,1719903600"; d="scan'208";a="92301453" Received: from unknown (HELO npf-hyd-clx-03..) ([10.145.170.182]) by orviesa002.jf.intel.com with ESMTP; 22 Aug 2024 12:48:28 -0700 From: Soumyadeep Hore To: bruce.richardson@intel.com, ian.stokes@intel.com, aman.deep.singh@intel.com Cc: dev@dpdk.org, shaiq.wani@intel.com Subject: [PATCH v2 08/12] net/ice: update iteration of TLVs in Preserved Fields Area Date: Thu, 22 Aug 2024 18:53:42 +0000 Message-ID: <20240822185346.221885-9-soumyadeep.hore@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240822185346.221885-1-soumyadeep.hore@intel.com> References: <20240822095612.216214-1-soumyadeep.hore@intel.com> <20240822185346.221885-1-soumyadeep.hore@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Correct the logic for determining the maximum PFA offset to include the extra last word. Additionally, make the driver robust against overflows by using check_add_overflow. This ensures that even if the NVM provides bogus data, the driver will not overflow, and will instead log a useful warning message. The check for whether the TLV length exceeds the PFA length is also removed, in favor of relying on the overflow warning instead. Signed-off-by: Soumyadeep Hore --- drivers/net/ice/base/ice_nvm.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c index 0124cef04c..56c6c96a95 100644 --- a/drivers/net/ice/base/ice_nvm.c +++ b/drivers/net/ice/base/ice_nvm.c @@ -469,6 +469,8 @@ int ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data) return status; } +#define check_add_overflow __builtin_add_overflow + /** * ice_get_pfa_module_tlv - Reads sub module TLV from NVM PFA * @hw: pointer to hardware structure @@ -484,8 +486,7 @@ int ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len, u16 module_type) { - u16 pfa_len, pfa_ptr; - u32 next_tlv; + u16 pfa_len, pfa_ptr, next_tlv, max_tlv; int status; status = ice_read_sr_word(hw, ICE_SR_PFA_PTR, &pfa_ptr); @@ -498,6 +499,13 @@ ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len, ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n"); return status; } + + if (check_add_overflow(pfa_ptr, (u16)(pfa_len - 1), &max_tlv)) { + ice_debug(hw, ICE_DBG_INIT, "PFA starts at offset %u. PFA length of %u caused 16-bit arithmetic overflow.\n", + pfa_ptr, pfa_len); + return ICE_ERR_INVAL_SIZE; + } + /* The Preserved Fields Area contains a sequence of TLVs which define * its contents. The PFA length includes all of the TLVs, plus its * initial length word itself, *and* one final word at the end of all @@ -507,7 +515,7 @@ ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len, * of TLVs to find the requested one. */ next_tlv = pfa_ptr + 1; - while (next_tlv < ((u32)pfa_ptr + pfa_len - 1)) { + while (next_tlv < max_tlv) { u16 tlv_sub_module_type; u16 tlv_len; @@ -524,10 +532,6 @@ ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len, ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV length.\n"); break; } - if (tlv_len > pfa_len) { - ice_debug(hw, ICE_DBG_INIT, "Invalid TLV length.\n"); - return ICE_ERR_INVAL_SIZE; - } if (tlv_sub_module_type == module_type) { if (tlv_len) { *module_tlv = (u16)next_tlv; @@ -536,10 +540,13 @@ ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len, } return ICE_ERR_INVAL_SIZE; } - /* Check next TLV, i.e. current TLV pointer + length + 2 words - * (for current TLV's type and length) - */ - next_tlv = next_tlv + tlv_len + 2; + + if (check_add_overflow(next_tlv, (u16)2, &next_tlv) || + check_add_overflow(next_tlv, tlv_len, &next_tlv)) { + ice_debug(hw, ICE_DBG_INIT, "TLV of type %u and length 0x%04x caused 16-bit arithmetic overflow. The PFA starts at 0x%04x and has length of 0x%04x\n", + tlv_sub_module_type, tlv_len, pfa_ptr, pfa_len); + return ICE_ERR_INVAL_SIZE; + } } /* Module does not exist */ return ICE_ERR_DOES_NOT_EXIST; From patchwork Thu Aug 22 18:53:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Soumyadeep Hore X-Patchwork-Id: 143335 X-Patchwork-Delegate: bruce.richardson@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AD3154584B; Thu, 22 Aug 2024 21:49:21 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AC02942FC1; Thu, 22 Aug 2024 21:48:34 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by mails.dpdk.org (Postfix) with ESMTP id AA3A942FB9 for ; Thu, 22 Aug 2024 21:48:32 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724356113; x=1755892113; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=g7m4D9MpoZfTZ1C58rcKHWnj3SH6/vP32lFbobOB6cw=; b=EMztBuP+E2b14dTtO3g1cG3WUVO9x1i7gMEvz7MnT2tYqGC8pRdQ+Mkm PPRKjtY/jjtR7RNLzVUVlIWQBFW3AVs7hEyM8k7pHplt+5wRZ4907n2NZ lbpWKch2wff1r+3BOKQvQbBKUF2pAOCfkBaCz1OIRMiV/kOp3S3RsbF1D 321zfy9h4A5TIErDZWtALIhCz6mZiFRB2Kgimk8VzsEzsafKtLSuZiuyS UMQDT+P4nyAnGASnHxlnY2VlaFYZlIOSIeq7NyokEyMxxzFFH6fkXPoAW Tmo4UCjDmabsFzzR+d0Q3GzyOmzekR0rM7ki+qCviwfmVEsIzityk4TX2 w==; X-CSE-ConnectionGUID: EksSJpldQdydGyuhC8ggXQ== X-CSE-MsgGUID: j+PeffnOQEaHT0FuFOnKeg== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="22979682" X-IronPort-AV: E=Sophos;i="6.10,168,1719903600"; d="scan'208";a="22979682" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 12:48:32 -0700 X-CSE-ConnectionGUID: ZFPepIEnQoC7dBlcRrhTGA== X-CSE-MsgGUID: Dt+EprKiQ9yOamHRodsOKw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,168,1719903600"; d="scan'208";a="92301460" Received: from unknown (HELO npf-hyd-clx-03..) ([10.145.170.182]) by orviesa002.jf.intel.com with ESMTP; 22 Aug 2024 12:48:31 -0700 From: Soumyadeep Hore To: bruce.richardson@intel.com, ian.stokes@intel.com, aman.deep.singh@intel.com Cc: dev@dpdk.org, shaiq.wani@intel.com Subject: [PATCH v2 09/12] net/ice: correct Tx Scheduler AQ command RD bit for E825C Date: Thu, 22 Aug 2024 18:53:43 +0000 Message-ID: <20240822185346.221885-10-soumyadeep.hore@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240822185346.221885-1-soumyadeep.hore@intel.com> References: <20240822095612.216214-1-soumyadeep.hore@intel.com> <20240822185346.221885-1-soumyadeep.hore@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org In E825C, regarding the Get Tx Topology AQ command, there is a change in the way that the RD bit must be set. For E825C, the RD bit must be cleared for the Get Tx Topology operation, whereas for E810 devices, the RD bit must be set. Signed-off-by: Soumyadeep Hore --- drivers/net/ice/base/ice_ddp.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/net/ice/base/ice_ddp.c b/drivers/net/ice/base/ice_ddp.c index 24506dfaea..d0c1cb9660 100644 --- a/drivers/net/ice/base/ice_ddp.c +++ b/drivers/net/ice/base/ice_ddp.c @@ -2270,6 +2270,22 @@ void ice_release_change_lock(struct ice_hw *hw) ice_release_res(hw, ICE_CHANGE_LOCK_RES_ID); } +/** + * ice_is_get_tx_sched_new_format + * @hw: pointer to the HW struct + * + * Determines if the new format for the Tx scheduler get api is supported + */ +static bool +ice_is_get_tx_sched_new_format(struct ice_hw *hw) +{ + if (ice_is_e830(hw)) + return true; + if (ice_is_e825c(hw)) + return true; + return false; +} + /** * ice_get_set_tx_topo - get or set tx topology * @hw: pointer to the HW struct @@ -2303,7 +2319,7 @@ ice_get_set_tx_topo(struct ice_hw *hw, u8 *buf, u16 buf_size, ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_tx_topo); cmd->get_flags = ICE_AQC_TX_TOPO_GET_RAM; - if (!ice_is_e830(hw)) + if (!ice_is_get_tx_sched_new_format(hw)) desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); } From patchwork Thu Aug 22 18:53:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Soumyadeep Hore X-Patchwork-Id: 143336 X-Patchwork-Delegate: bruce.richardson@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4BFA94584B; Thu, 22 Aug 2024 21:49:30 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 56E6342FE1; Thu, 22 Aug 2024 21:48:37 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by mails.dpdk.org (Postfix) with ESMTP id EFA1C42FD7 for ; Thu, 22 Aug 2024 21:48:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724356116; x=1755892116; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XaLM4bxvHc6aV3/5zDDeMTIoZ5nqIsy8JoLzI8dwADo=; b=L6Q5AZAQC808d2CRkqch3U3FxSbSTqqmwE8OT4bH35nCswtZ9tvcKUBa JgZiZx/cE2AAKebBZkh29KOqXEfv2XVe1SWezqYTQBN/6vdU0fIy1+f9k W+vRr+Zi6sIP+yJ/n3x36O8WjP3kQeog+Pjdpyk0zGz5wQGpVWi53SS3G oG0XZWzy2CsdkEFDcDgiiR899UhMvU+O5GG4mXMEurbLSMgL0Gkii748f yLZUQGjKy1xZfXT0LXd9dhyCXynrZqKZJDDviFSztGikLPrDkB8zGTXJM Pl00WQEH6LzH6GUsjpeR555PNX9mpovR/SWALqm8TE8dKh6Xcwwj8tMDL g==; X-CSE-ConnectionGUID: T71xxillQZucO2vX7bWkgA== X-CSE-MsgGUID: K/bG45YfTxyScqgIQ9anRw== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="22979701" X-IronPort-AV: E=Sophos;i="6.10,168,1719903600"; d="scan'208";a="22979701" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 12:48:35 -0700 X-CSE-ConnectionGUID: mukXzoYgS3arBCCkmPIvpw== X-CSE-MsgGUID: pe/kRxyyRtCP3mzTf6KMJA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,168,1719903600"; d="scan'208";a="92301481" Received: from unknown (HELO npf-hyd-clx-03..) ([10.145.170.182]) by orviesa002.jf.intel.com with ESMTP; 22 Aug 2024 12:48:33 -0700 From: Soumyadeep Hore To: bruce.richardson@intel.com, ian.stokes@intel.com, aman.deep.singh@intel.com Cc: dev@dpdk.org, shaiq.wani@intel.com Subject: [PATCH v2 10/12] net/ice: support optional flags in signature segment header Date: Thu, 22 Aug 2024 18:53:44 +0000 Message-ID: <20240822185346.221885-11-soumyadeep.hore@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240822185346.221885-1-soumyadeep.hore@intel.com> References: <20240822095612.216214-1-soumyadeep.hore@intel.com> <20240822185346.221885-1-soumyadeep.hore@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org An optional flag field has been added to the signature segment header. The flags field contains two flags, a valid flag, and a last segment flag that indicates whether the segment is the last segment that will be downloaded to firmware. If the flag field's valid bit is NOT set, then as was done before, assume that this is the last segment being downloaded. However, if the flag field's valid bit IS set, then use the last segment flag to determine if this segment is the last segment to download. Signed-off-by: Soumyadeep Hore --- drivers/net/ice/base/ice_ddp.c | 13 ++++++++++--- drivers/net/ice/base/ice_ddp.h | 5 ++++- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/net/ice/base/ice_ddp.c b/drivers/net/ice/base/ice_ddp.c index d0c1cb9660..90aaa6b331 100644 --- a/drivers/net/ice/base/ice_ddp.c +++ b/drivers/net/ice/base/ice_ddp.c @@ -499,12 +499,13 @@ ice_download_pkg_sig_seg(struct ice_hw *hw, struct ice_sign_seg *seg) * @idx: segment index * @start: starting buffer * @count: buffer count + * @last_seg: last segment being downloaded * * Note: idx must reference a ICE segment */ static enum ice_ddp_state ice_download_pkg_config_seg(struct ice_hw *hw, struct ice_pkg_hdr *pkg_hdr, - u32 idx, u32 start, u32 count) + u32 idx, u32 start, u32 count, bool last_seg) { struct ice_buf_table *bufs; enum ice_ddp_state state; @@ -522,7 +523,7 @@ ice_download_pkg_config_seg(struct ice_hw *hw, struct ice_pkg_hdr *pkg_hdr, return ICE_DDP_PKG_ERR; state = ice_dwnld_cfg_bufs_no_lock(hw, bufs->buf_array, start, count, - true); + last_seg); return state; } @@ -541,9 +542,11 @@ ice_dwnld_sign_and_cfg_segs(struct ice_hw *hw, struct ice_pkg_hdr *pkg_hdr, { enum ice_ddp_state state; struct ice_sign_seg *seg; + bool last_seg = true; u32 conf_idx; u32 start; u32 count; + u32 flags; seg = (struct ice_sign_seg *)ice_get_pkg_seg_by_idx(pkg_hdr, idx); if (!seg) { @@ -554,6 +557,10 @@ ice_dwnld_sign_and_cfg_segs(struct ice_hw *hw, struct ice_pkg_hdr *pkg_hdr, conf_idx = LE32_TO_CPU(seg->signed_seg_idx); start = LE32_TO_CPU(seg->signed_buf_start); count = LE32_TO_CPU(seg->signed_buf_count); + flags = LE32_TO_CPU(seg->flags); + + if (flags & ICE_SIGN_SEG_FLAGS_VALID) + last_seg = !!(flags & ICE_SIGN_SEG_FLAGS_LAST); state = ice_download_pkg_sig_seg(hw, seg); if (state) @@ -568,7 +575,7 @@ ice_dwnld_sign_and_cfg_segs(struct ice_hw *hw, struct ice_pkg_hdr *pkg_hdr, } state = ice_download_pkg_config_seg(hw, pkg_hdr, conf_idx, start, - count); + count, last_seg); exit: return state; diff --git a/drivers/net/ice/base/ice_ddp.h b/drivers/net/ice/base/ice_ddp.h index 5761920207..5512669f44 100644 --- a/drivers/net/ice/base/ice_ddp.h +++ b/drivers/net/ice/base/ice_ddp.h @@ -177,7 +177,10 @@ struct ice_sign_seg { __le32 signed_seg_idx; __le32 signed_buf_start; __le32 signed_buf_count; -#define ICE_SIGN_SEG_RESERVED_COUNT 44 +#define ICE_SIGN_SEG_FLAGS_VALID 0x80000000 +#define ICE_SIGN_SEG_FLAGS_LAST 0x00000001 + __le32 flags; +#define ICE_SIGN_SEG_RESERVED_COUNT 40 u8 reserved[ICE_SIGN_SEG_RESERVED_COUNT]; struct ice_buf_table buf_tbl; }; From patchwork Thu Aug 22 18:53:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Soumyadeep Hore X-Patchwork-Id: 143337 X-Patchwork-Delegate: bruce.richardson@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3D9EB4584B; Thu, 22 Aug 2024 21:49:37 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7C8ED42FE7; Thu, 22 Aug 2024 21:48:38 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by mails.dpdk.org (Postfix) with ESMTP id 3CB9842FDD for ; Thu, 22 Aug 2024 21:48:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724356118; x=1755892118; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=auKcdIynEAiarowcxGyKNl5523QIIFS0C880YktYJCY=; b=AE4G6viD0mgoP6SCl1ESThutqJMTWQCRAKEH04Az5k7mgImBSBy+kcie hChA7qVUWc3HVgRDqQDmPeOesZDssGI65mweHzrQAf8atGZc7RfBCvteh JgQ4dyp8gl7OQ7K+4TpUZtRwL9iDetUMBvezAgXPpUDN3ZQYf46YfD9pN r99Xq0/NJLUD5mcb6x9UuUidbYW6QAanwZ1cBYNS9yhp4djlQCMQ3wl7j KrGQecaQm8hzb0NCkIIm4/9vKpaWUsCkbGJWbczgyPSwSqciusGpLCr61 vupoA5B8SfTEoHKYqEZWzW4JEGltGJStXZAqfY/RdRJ9Rbyx6L4iBe0n8 A==; X-CSE-ConnectionGUID: mvCAlR8tSt6obuKlQR8kZA== X-CSE-MsgGUID: nHxbvNxFRiumynvCx65luw== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="22979708" X-IronPort-AV: E=Sophos;i="6.10,168,1719903600"; d="scan'208";a="22979708" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 12:48:37 -0700 X-CSE-ConnectionGUID: +q9SzdLSTiqNlZ85cpVHXg== X-CSE-MsgGUID: aDtDBuqTRFO7yxiCIGdJ8w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,168,1719903600"; d="scan'208";a="92301490" Received: from unknown (HELO npf-hyd-clx-03..) ([10.145.170.182]) by orviesa002.jf.intel.com with ESMTP; 22 Aug 2024 12:48:35 -0700 From: Soumyadeep Hore To: bruce.richardson@intel.com, ian.stokes@intel.com, aman.deep.singh@intel.com Cc: dev@dpdk.org, shaiq.wani@intel.com Subject: [PATCH v2 11/12] net/ice: update E830 50G branding strings Date: Thu, 22 Aug 2024 18:53:45 +0000 Message-ID: <20240822185346.221885-12-soumyadeep.hore@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240822185346.221885-1-soumyadeep.hore@intel.com> References: <20240822095612.216214-1-soumyadeep.hore@intel.com> <20240822185346.221885-1-soumyadeep.hore@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Update E830 50G branding strings from "E830-XXV" to "E830-L". Signed-off-by: Soumyadeep Hore --- drivers/net/ice/base/ice_common.c | 6 +++--- drivers/net/ice/base/ice_devids.h | 12 ++++++------ drivers/net/ice/ice_ethdev.c | 6 +++--- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 4750076b7d..08ba0b45a5 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -184,11 +184,11 @@ static int ice_set_mac_type(struct ice_hw *hw) case ICE_DEV_ID_E830_QSFP56: case ICE_DEV_ID_E830_SFP: case ICE_DEV_ID_E830C_BACKPLANE: - case ICE_DEV_ID_E830_XXV_BACKPLANE: + case ICE_DEV_ID_E830_L_BACKPLANE: case ICE_DEV_ID_E830C_QSFP: - case ICE_DEV_ID_E830_XXV_QSFP: + case ICE_DEV_ID_E830_L_QSFP: case ICE_DEV_ID_E830C_SFP: - case ICE_DEV_ID_E830_XXV_SFP: + case ICE_DEV_ID_E830_L_SFP: hw->mac_type = ICE_MAC_E830; break; default: diff --git a/drivers/net/ice/base/ice_devids.h b/drivers/net/ice/base/ice_devids.h index 07fb9aca0b..807b5d0c29 100644 --- a/drivers/net/ice/base/ice_devids.h +++ b/drivers/net/ice/base/ice_devids.h @@ -25,16 +25,16 @@ #define ICE_DEV_ID_E830_SFP 0x12D3 /* Intel(R) Ethernet Controller E830-C for backplane */ #define ICE_DEV_ID_E830C_BACKPLANE 0x12D5 -/* Intel(R) Ethernet Controller E830-XXV for backplane */ -#define ICE_DEV_ID_E830_XXV_BACKPLANE 0x12DC +/* Intel(R) Ethernet Controller E830-L for backplane */ +#define ICE_DEV_ID_E830_L_BACKPLANE 0x12DC /* Intel(R) Ethernet Controller E830-C for QSFP */ #define ICE_DEV_ID_E830C_QSFP 0x12D8 -/* Intel(R) Ethernet Controller E830-XXV for QSFP */ -#define ICE_DEV_ID_E830_XXV_QSFP 0x12DD +/* Intel(R) Ethernet Controller E830-L for QSFP */ +#define ICE_DEV_ID_E830_L_QSFP 0x12DD /* Intel(R) Ethernet Controller E830-C for SFP */ #define ICE_DEV_ID_E830C_SFP 0x12DA -/* Intel(R) Ethernet Controller E830-XXV for SFP */ -#define ICE_DEV_ID_E830_XXV_SFP 0x12DE +/* Intel(R) Ethernet Controller E830-L for SFP */ +#define ICE_DEV_ID_E830_L_SFP 0x12DE /* Intel(R) Ethernet Controller E810-C for backplane */ #define ICE_DEV_ID_E810C_BACKPLANE 0x1591 /* Intel(R) Ethernet Controller E810-C for QSFP */ diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 304f959b7e..034018073a 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -225,11 +225,11 @@ static const struct rte_pci_id pci_id_ice_map[] = { { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830_QSFP56) }, { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830_SFP) }, { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830C_BACKPLANE) }, - { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830_XXV_BACKPLANE) }, + { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830_L_BACKPLANE) }, { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830C_QSFP) }, - { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830_XXV_QSFP) }, + { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830_L_QSFP) }, { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830C_SFP) }, - { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830_XXV_SFP) }, + { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830_L_SFP) }, { .vendor_id = 0, /* sentinel */ }, }; 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([10.145.170.182]) by orviesa002.jf.intel.com with ESMTP; 22 Aug 2024 12:48:37 -0700 From: Soumyadeep Hore To: bruce.richardson@intel.com, ian.stokes@intel.com, aman.deep.singh@intel.com Cc: dev@dpdk.org, shaiq.wani@intel.com Subject: [PATCH v2 12/12] net/ice: add support for FEC auto-detect for E830 Date: Thu, 22 Aug 2024 18:53:46 +0000 Message-ID: <20240822185346.221885-13-soumyadeep.hore@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240822185346.221885-1-soumyadeep.hore@intel.com> References: <20240822095612.216214-1-soumyadeep.hore@intel.com> <20240822185346.221885-1-soumyadeep.hore@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Extends the functionality of the function responsible for checking if the firmware supports FEC (Forward Error Correction) disable in Auto FEC mode. It now includes an additional check to determine if the adapter is a E830 model. With this change, the function will enable FEC auto-detect support for E830 adapters. Signed-off-by: Soumyadeep Hore --- drivers/net/ice/base/ice_common.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 08ba0b45a5..c8047ca59f 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -6456,6 +6456,8 @@ u32 ice_get_link_speed(u16 index) */ bool ice_fw_supports_fec_dis_auto(struct ice_hw *hw) { + if (ice_is_e830(hw)) + return true; return ice_is_fw_min_ver(hw, ICE_FW_VER_BRANCH_E810, ICE_FW_FEC_DIS_AUTO_MAJ, ICE_FW_FEC_DIS_AUTO_MIN,