From patchwork Mon Jul 22 06:58:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Hai X-Patchwork-Id: 142570 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 486CD4567C; Mon, 22 Jul 2024 09:05:59 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D106842F00; Mon, 22 Jul 2024 09:05:27 +0200 (CEST) Received: from szxga07-in.huawei.com (szxga07-in.huawei.com [45.249.212.35]) by mails.dpdk.org (Postfix) with ESMTP id F31CD42DC9 for ; Mon, 22 Jul 2024 08:58:56 +0200 (CEST) Received: from mail.maildlp.com (unknown [172.19.163.17]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4WS9xf5GKyz1X4k0; Mon, 22 Jul 2024 14:54:30 +0800 (CST) Received: from kwepemf500004.china.huawei.com (unknown [7.202.181.242]) by mail.maildlp.com (Postfix) with ESMTPS id 075DE1A0188; Mon, 22 Jul 2024 14:58:54 +0800 (CST) Received: from localhost.huawei.com (10.90.30.45) by kwepemf500004.china.huawei.com (7.202.181.242) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Mon, 22 Jul 2024 14:58:53 +0800 From: Jie Hai To: , Thomas Monjalon , Ferruh Yigit , Andrew Rybchenko CC: , Subject: [PATCH v6 1/8] ethdev: support report register names and filter Date: Mon, 22 Jul 2024 14:58:19 +0800 Message-ID: <20240722065826.3039119-2-haijie1@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20240722065826.3039119-1-haijie1@huawei.com> References: <20231214015650.3738578-1-haijie1@huawei.com> <20240722065826.3039119-1-haijie1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.90.30.45] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To kwepemf500004.china.huawei.com (7.202.181.242) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds "filter" and "names" fields to "rte_dev_reg_info" structure. Names of registers in data fields can be reported and the registers can be filtered by their module names. The new API rte_eth_dev_get_reg_info_ext() is added to support reporting names and filtering by modules. And the original API rte_eth_dev_get_reg_info() does not use the names and filter fields. A local variable is used in rte_eth_dev_get_reg_info for compatibility. If the drivers does not report the names, set them to "index_XXX", which means the location in the register table. Signed-off-by: Jie Hai Acked-by: Huisong Li Acked-by: Chengwen Feng --- doc/guides/rel_notes/release_24_07.rst | 8 ++++++ lib/ethdev/ethdev_trace.h | 2 ++ lib/ethdev/rte_dev_info.h | 11 ++++++++ lib/ethdev/rte_ethdev.c | 38 ++++++++++++++++++++++++++ lib/ethdev/rte_ethdev.h | 29 ++++++++++++++++++++ lib/ethdev/version.map | 3 ++ 6 files changed, 91 insertions(+) diff --git a/doc/guides/rel_notes/release_24_07.rst b/doc/guides/rel_notes/release_24_07.rst index 058609b0f36b..b0bb49c8f29e 100644 --- a/doc/guides/rel_notes/release_24_07.rst +++ b/doc/guides/rel_notes/release_24_07.rst @@ -186,6 +186,12 @@ New Features * Added defer queue reclamation via RCU. * Added SVE support for bulk lookup. +* **Added support for dumping registers with names and filtering by modules.** + + * Added new API functions ``rte_eth_dev_get_reg_info_ext()`` to filter the + registers by module names and get the information (names, values and other + attributes) of the filtered registers. + Removed Items ------------- @@ -241,6 +247,8 @@ ABI Changes This section is a comment. Do not overwrite or remove it. Also, make sure to start the actual text at the margin. ======================================================= + * ethdev: Added ``filter`` and ``names`` fields to ``rte_dev_reg_info`` + structure for filtering by modules and reporting names of registers. * No ABI change that would break compatibility with 23.11. diff --git a/lib/ethdev/ethdev_trace.h b/lib/ethdev/ethdev_trace.h index 3bec87bfdb70..0c4780a09ef5 100644 --- a/lib/ethdev/ethdev_trace.h +++ b/lib/ethdev/ethdev_trace.h @@ -1152,6 +1152,8 @@ RTE_TRACE_POINT( rte_trace_point_emit_u32(info->length); rte_trace_point_emit_u32(info->width); rte_trace_point_emit_u32(info->version); + rte_trace_point_emit_ptr(info->names); + rte_trace_point_emit_ptr(info->filter); rte_trace_point_emit_int(ret); ) diff --git a/lib/ethdev/rte_dev_info.h b/lib/ethdev/rte_dev_info.h index 67cf0ae52668..26b777f9836e 100644 --- a/lib/ethdev/rte_dev_info.h +++ b/lib/ethdev/rte_dev_info.h @@ -11,6 +11,11 @@ extern "C" { #include +#define RTE_ETH_REG_NAME_SIZE 64 +struct rte_eth_reg_name { + char name[RTE_ETH_REG_NAME_SIZE]; +}; + /* * Placeholder for accessing device registers */ @@ -20,6 +25,12 @@ struct rte_dev_reg_info { uint32_t length; /**< Number of registers to fetch */ uint32_t width; /**< Size of device register */ uint32_t version; /**< Device version */ + /** + * Name of target module, filter for target subset of registers. + * This field could affects register selection for data/length/names. + */ + const char *filter; + struct rte_eth_reg_name *names; /**< Registers name saver */ }; /* diff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c index f1c658f49e80..30ca4a0043c5 100644 --- a/lib/ethdev/rte_ethdev.c +++ b/lib/ethdev/rte_ethdev.c @@ -6388,8 +6388,37 @@ rte_eth_read_clock(uint16_t port_id, uint64_t *clock) int rte_eth_dev_get_reg_info(uint16_t port_id, struct rte_dev_reg_info *info) +{ + struct rte_dev_reg_info reg_info = { 0 }; + int ret; + + if (info == NULL) { + RTE_ETHDEV_LOG_LINE(ERR, + "Cannot get ethdev port %u register info to NULL", + port_id); + return -EINVAL; + } + + reg_info.length = info->length; + reg_info.data = info->data; + + ret = rte_eth_dev_get_reg_info_ext(port_id, ®_info); + if (ret != 0) + return ret; + + info->length = reg_info.length; + info->width = reg_info.width; + info->version = reg_info.version; + info->offset = reg_info.offset; + + return 0; +} + +int +rte_eth_dev_get_reg_info_ext(uint16_t port_id, struct rte_dev_reg_info *info) { struct rte_eth_dev *dev; + uint32_t i; int ret; RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); @@ -6402,12 +6431,21 @@ rte_eth_dev_get_reg_info(uint16_t port_id, struct rte_dev_reg_info *info) return -EINVAL; } + if (info->names != NULL && info->length != 0) + memset(info->names, 0, sizeof(struct rte_eth_reg_name) * info->length); + if (*dev->dev_ops->get_reg == NULL) return -ENOTSUP; ret = eth_err(port_id, (*dev->dev_ops->get_reg)(dev, info)); rte_ethdev_trace_get_reg_info(port_id, info, ret); + /* Report the default names if drivers not report. */ + if (ret == 0 && info->names != NULL && strlen(info->names[0].name) == 0) { + for (i = 0; i < info->length; i++) + snprintf(info->names[i].name, RTE_ETH_REG_NAME_SIZE, + "index_%u", info->offset + i); + } return ret; } diff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h index 548fada1c7ad..02cb3c07f742 100644 --- a/lib/ethdev/rte_ethdev.h +++ b/lib/ethdev/rte_ethdev.h @@ -5071,6 +5071,35 @@ __rte_experimental int rte_eth_get_monitor_addr(uint16_t port_id, uint16_t queue_id, struct rte_power_monitor_cond *pmc); +/** + * Retrieve the filtered device registers (values and names) and + * register attributes (number of registers and register size) + * + * @param port_id + * The port identifier of the Ethernet device. + * @param info + * Pointer to rte_dev_reg_info structure to fill in. + * - If info->filter is NULL, return info for all registers (seen as filter + * none). + * - If info->filter is not NULL, return error if the driver does not support + * filter. Fill the length field with filtered register number. + * - If info->data is NULL, the function fills in the width and length fields. + * - If info->data is not NULL, ethdev considers there are enough spaces to + * store the registers, and the values of registers with the filter string + * as the module name are put into the buffer pointed at by info->data. + * - If info->names is not NULL, drivers should fill it or the ethdev fills it + * with default names. + * @return + * - (0) if successful. + * - (-ENOTSUP) if hardware doesn't support. + * - (-EINVAL) if bad parameter. + * - (-ENODEV) if *port_id* invalid. + * - (-EIO) if device is removed. + * - others depends on the specific operations implementation. + */ +__rte_experimental +int rte_eth_dev_get_reg_info_ext(uint16_t port_id, struct rte_dev_reg_info *info); + /** * Retrieve device registers and register attributes (number of registers and * register size) diff --git a/lib/ethdev/version.map b/lib/ethdev/version.map index 79f6f5293b5c..e3289e999382 100644 --- a/lib/ethdev/version.map +++ b/lib/ethdev/version.map @@ -325,6 +325,9 @@ EXPERIMENTAL { rte_flow_template_table_resizable; rte_flow_template_table_resize; rte_flow_template_table_resize_complete; + + # added in 24.07 + rte_eth_dev_get_reg_info_ext; }; INTERNAL { From patchwork Mon Jul 22 06:58:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Hai X-Patchwork-Id: 142566 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 883754567C; Mon, 22 Jul 2024 09:05:27 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9377F42E4F; Mon, 22 Jul 2024 09:05:22 +0200 (CEST) Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) by mails.dpdk.org (Postfix) with ESMTP id 805F342DA3 for ; Mon, 22 Jul 2024 08:58:56 +0200 (CEST) Received: from mail.maildlp.com (unknown [172.19.88.234]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4WS9xg5pb7z28ff3; Mon, 22 Jul 2024 14:54:31 +0800 (CST) Received: from kwepemf500004.china.huawei.com (unknown [7.202.181.242]) by mail.maildlp.com (Postfix) with ESMTPS id 8E67714022F; Mon, 22 Jul 2024 14:58:54 +0800 (CST) Received: from localhost.huawei.com (10.90.30.45) by kwepemf500004.china.huawei.com (7.202.181.242) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Mon, 22 Jul 2024 14:58:54 +0800 From: Jie Hai To: , Thomas Monjalon , Ferruh Yigit , Andrew Rybchenko CC: , Subject: [PATCH v6 2/8] ethdev: add telemetry cmd for registers Date: Mon, 22 Jul 2024 14:58:20 +0800 Message-ID: <20240722065826.3039119-3-haijie1@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20240722065826.3039119-1-haijie1@huawei.com> References: <20231214015650.3738578-1-haijie1@huawei.com> <20240722065826.3039119-1-haijie1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.90.30.45] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To kwepemf500004.china.huawei.com (7.202.181.242) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds a telemetry command for registers dump, and supports obtaining the registers of a specified module. In one way, the number of registers that can be exported is limited by the number of elements carried by dict and container. In another way, the length of the string exported by telemetry is limited by MAX_OUTPUT_LEN. Therefore, when the number of registers to be exported exceeds, some information will be lost. Warn on the former case. An example usage is shown below: --> /ethdev/regs,0,ring { "/ethdev/regs": { "registers_length": 318, "registers_width": 4, "register_offset": "0x0", "version": "0x1140011", "group_0": { "Q0_ring_rx_bd_num": "0x0", "Q0_ring_rx_bd_len": "0x0", ... }, "group_1": { ... }, ... } Signed-off-by: Jie Hai --- lib/ethdev/rte_ethdev_telemetry.c | 128 ++++++++++++++++++++++++++++++ 1 file changed, 128 insertions(+) diff --git a/lib/ethdev/rte_ethdev_telemetry.c b/lib/ethdev/rte_ethdev_telemetry.c index 6b873e7abe68..1d59c693883e 100644 --- a/lib/ethdev/rte_ethdev_telemetry.c +++ b/lib/ethdev/rte_ethdev_telemetry.c @@ -1395,6 +1395,132 @@ eth_dev_handle_port_tm_node_caps(const char *cmd __rte_unused, return ret; } +static void +eth_dev_add_reg_data(struct rte_tel_data *d, struct rte_dev_reg_info *reg_info, + uint32_t idx) +{ + if (reg_info->width == sizeof(uint32_t)) + rte_tel_data_add_dict_uint_hex(d, reg_info->names[idx].name, + *((uint32_t *)reg_info->data + idx), 0); + else + rte_tel_data_add_dict_uint_hex(d, reg_info->names[idx].name, + *((uint64_t *)reg_info->data + idx), 0); +} + +static int +eth_dev_store_regs(struct rte_tel_data *d, struct rte_dev_reg_info *reg_info) +{ + struct rte_tel_data *groups[RTE_TEL_MAX_DICT_ENTRIES]; + char group_name[RTE_TEL_MAX_STRING_LEN] = {0}; + struct rte_tel_data *group = NULL; + uint32_t grp_num = 0; + uint32_t i; + int ret; + + rte_tel_data_start_dict(d); + rte_tel_data_add_dict_uint(d, "register_length", reg_info->length); + rte_tel_data_add_dict_uint(d, "register_width", reg_info->width); + rte_tel_data_add_dict_uint_hex(d, "register_offset", reg_info->offset, 0); + rte_tel_data_add_dict_uint_hex(d, "version", reg_info->version, 0); + + for (i = 0; i < reg_info->length; i++) { + if (i % RTE_TEL_MAX_DICT_ENTRIES != 0) { + eth_dev_add_reg_data(group, reg_info, i); + continue; + } + + group = rte_tel_data_alloc(); + if (group == NULL) { + ret = -ENOMEM; + RTE_ETHDEV_LOG_LINE(WARNING, "No enough memory for group data"); + goto out; + } + groups[grp_num++] = group; + rte_tel_data_start_dict(group); + eth_dev_add_reg_data(group, reg_info, i); + } + + for (i = 0; i < grp_num; i++) { + snprintf(group_name, RTE_TEL_MAX_STRING_LEN, "group_%u", i); + ret = rte_tel_data_add_dict_container(d, group_name, groups[i], 0); + if (ret == -ENOSPC) { + RTE_ETHDEV_LOG_LINE(WARNING, + "Reduce register number to be displayed from %u to %u due to limited capacity of telemetry", + reg_info->length, i * RTE_TEL_MAX_DICT_ENTRIES); + break; + } + } + return 0; +out: + for (i = 0; i < grp_num; i++) + rte_tel_data_free(groups[i]); + + return ret; +} + +static int +eth_dev_get_port_regs(int port_id, struct rte_tel_data *d, char *filter) +{ + struct rte_dev_reg_info reg_info; + int ret; + + memset(®_info, 0, sizeof(reg_info)); + reg_info.filter = filter; + + ret = rte_eth_dev_get_reg_info_ext(port_id, ®_info); + if (ret != 0) { + RTE_ETHDEV_LOG_LINE(ERR, "Error getting device reg info: %d", ret); + return ret; + } + + reg_info.data = calloc(reg_info.length, reg_info.width); + if (reg_info.data == NULL) { + RTE_ETHDEV_LOG_LINE(ERR, "Fail to allocate memory for reg_info.data"); + return -ENOMEM; + } + + reg_info.names = calloc(reg_info.length, sizeof(struct rte_eth_reg_name)); + if (reg_info.names == NULL) { + RTE_ETHDEV_LOG_LINE(ERR, "Fail to allocate memory for reg_info.names"); + free(reg_info.data); + return -ENOMEM; + } + + ret = rte_eth_dev_get_reg_info_ext(port_id, ®_info); + if (ret != 0) { + RTE_ETHDEV_LOG_LINE(ERR, "Error getting regs from device: %d", ret); + ret = -EINVAL; + goto out; + } + + ret = eth_dev_store_regs(d, ®_info); +out: + free(reg_info.data); + free(reg_info.names); + + return ret; +} + +static int +eth_dev_handle_port_regs(const char *cmd __rte_unused, + const char *params, + struct rte_tel_data *d) +{ + char *filter, *end_param; + uint16_t port_id; + int ret; + + ret = eth_dev_parse_port_params(params, &port_id, &end_param, true); + if (ret != 0) + return ret; + + filter = strtok(end_param, ","); + if (filter != NULL && strlen(filter) == 0) + filter = NULL; + + return eth_dev_get_port_regs(port_id, d, filter); +} + RTE_INIT(ethdev_init_telemetry) { rte_telemetry_register_cmd("/ethdev/list", eth_dev_handle_port_list, @@ -1436,4 +1562,6 @@ RTE_INIT(ethdev_init_telemetry) "Returns TM Level Capabilities info for a port. Parameters: int port_id, int level_id (see tm_capability for the max)"); rte_telemetry_register_cmd("/ethdev/tm_node_capability", eth_dev_handle_port_tm_node_caps, "Returns TM Node Capabilities info for a port. Parameters: int port_id, int node_id (see tm_capability for the max)"); + rte_telemetry_register_cmd("/ethdev/regs", eth_dev_handle_port_regs, + "Returns all or filtered registers info for a port. Parameters: int port_id, string module_name (Optional if show all)"); } From patchwork Mon Jul 22 06:58:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Hai X-Patchwork-Id: 142567 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 05E7D4567C; Mon, 22 Jul 2024 09:05:35 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C3C3C42E89; Mon, 22 Jul 2024 09:05:23 +0200 (CEST) Received: from szxga07-in.huawei.com (szxga07-in.huawei.com [45.249.212.35]) by mails.dpdk.org (Postfix) with ESMTP id E3031427D6 for ; Mon, 22 Jul 2024 08:58:56 +0200 (CEST) Received: from mail.maildlp.com (unknown [172.19.163.17]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4WS9xg5zsZz1X4jv; Mon, 22 Jul 2024 14:54:31 +0800 (CST) Received: from kwepemf500004.china.huawei.com (unknown [7.202.181.242]) by mail.maildlp.com (Postfix) with ESMTPS id 2099F1A0188; Mon, 22 Jul 2024 14:58:55 +0800 (CST) Received: from localhost.huawei.com (10.90.30.45) by kwepemf500004.china.huawei.com (7.202.181.242) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Mon, 22 Jul 2024 14:58:54 +0800 From: Jie Hai To: , Yisen Zhuang CC: , , , Subject: [PATCH v6 3/8] net/hns3: remove some basic address dump Date: Mon, 22 Jul 2024 14:58:21 +0800 Message-ID: <20240722065826.3039119-4-haijie1@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20240722065826.3039119-1-haijie1@huawei.com> References: <20231214015650.3738578-1-haijie1@huawei.com> <20240722065826.3039119-1-haijie1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.90.30.45] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To kwepemf500004.china.huawei.com (7.202.181.242) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org For security reasons, some address registers are not suitable to be exposed, remove them. Cc: stable@dpdk.org Signed-off-by: Jie Hai Acked-by: Huisong Li --- drivers/net/hns3/hns3_regs.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c index be1be6a89c94..53d829a4fc68 100644 --- a/drivers/net/hns3/hns3_regs.c +++ b/drivers/net/hns3/hns3_regs.c @@ -17,13 +17,9 @@ static int hns3_get_dfx_reg_line(struct hns3_hw *hw, uint32_t *lines); -static const uint32_t cmdq_reg_addrs[] = {HNS3_CMDQ_TX_ADDR_L_REG, - HNS3_CMDQ_TX_ADDR_H_REG, - HNS3_CMDQ_TX_DEPTH_REG, +static const uint32_t cmdq_reg_addrs[] = {HNS3_CMDQ_TX_DEPTH_REG, HNS3_CMDQ_TX_TAIL_REG, HNS3_CMDQ_TX_HEAD_REG, - HNS3_CMDQ_RX_ADDR_L_REG, - HNS3_CMDQ_RX_ADDR_H_REG, HNS3_CMDQ_RX_DEPTH_REG, HNS3_CMDQ_RX_TAIL_REG, HNS3_CMDQ_RX_HEAD_REG, @@ -44,9 +40,7 @@ static const uint32_t common_vf_reg_addrs[] = {HNS3_MISC_VECTOR_REG_BASE, HNS3_FUN_RST_ING, HNS3_GRO_EN_REG}; -static const uint32_t ring_reg_addrs[] = {HNS3_RING_RX_BASEADDR_L_REG, - HNS3_RING_RX_BASEADDR_H_REG, - HNS3_RING_RX_BD_NUM_REG, +static const uint32_t ring_reg_addrs[] = {HNS3_RING_RX_BD_NUM_REG, HNS3_RING_RX_BD_LEN_REG, HNS3_RING_RX_EN_REG, HNS3_RING_RX_MERGE_EN_REG, @@ -57,8 +51,6 @@ static const uint32_t ring_reg_addrs[] = {HNS3_RING_RX_BASEADDR_L_REG, HNS3_RING_RX_FBD_OFFSET_REG, HNS3_RING_RX_STASH_REG, HNS3_RING_RX_BD_ERR_REG, - HNS3_RING_TX_BASEADDR_L_REG, - HNS3_RING_TX_BASEADDR_H_REG, HNS3_RING_TX_BD_NUM_REG, HNS3_RING_TX_EN_REG, HNS3_RING_TX_PRIORITY_REG, From patchwork Mon Jul 22 06:58:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Hai X-Patchwork-Id: 142568 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BB6194567C; Mon, 22 Jul 2024 09:05:43 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2141E42ED7; Mon, 22 Jul 2024 09:05:25 +0200 (CEST) Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by mails.dpdk.org (Postfix) with ESMTP id 8349C427D6 for ; Mon, 22 Jul 2024 08:58:57 +0200 (CEST) Received: from mail.maildlp.com (unknown [172.19.163.48]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4WS9xC4qhnzyN64; Mon, 22 Jul 2024 14:54:07 +0800 (CST) Received: from kwepemf500004.china.huawei.com (unknown [7.202.181.242]) by mail.maildlp.com (Postfix) with ESMTPS id D671118009B; Mon, 22 Jul 2024 14:58:55 +0800 (CST) Received: from localhost.huawei.com (10.90.30.45) by kwepemf500004.china.huawei.com (7.202.181.242) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Mon, 22 Jul 2024 14:58:55 +0800 From: Jie Hai To: , Yisen Zhuang , Chengchang Tang , Lijun Ou , Huisong Li , Hao Chen , Ferruh Yigit , "Min Hu (Connor)" , Chunsong Feng CC: , , Subject: [PATCH v6 4/8] net/hns3: fix dump counter of registers Date: Mon, 22 Jul 2024 14:58:22 +0800 Message-ID: <20240722065826.3039119-5-haijie1@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20240722065826.3039119-1-haijie1@huawei.com> References: <20231214015650.3738578-1-haijie1@huawei.com> <20240722065826.3039119-1-haijie1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.90.30.45] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To kwepemf500004.china.huawei.com (7.202.181.242) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Since the driver dumps the queue interrupt registers according to the intr_tqps_num, the counter should be the same. Fixes: acb3260fac5c ("net/hns3: fix dump register out of range") Fixes: 936eda25e8da ("net/hns3: support dump register") Cc: stable@dpdk.org Signed-off-by: Jie Hai Acked-by: Huisong Li Acked-by: Chengwen Feng --- drivers/net/hns3/hns3_regs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c index 53d829a4fc68..d9c546470dbe 100644 --- a/drivers/net/hns3/hns3_regs.c +++ b/drivers/net/hns3/hns3_regs.c @@ -127,7 +127,7 @@ hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length) tqp_intr_lines = sizeof(tqp_intr_reg_addrs) / REG_LEN_PER_LINE + 1; len = (cmdq_lines + common_lines + ring_lines * hw->tqps_num + - tqp_intr_lines * hw->num_msi) * REG_NUM_PER_LINE; + tqp_intr_lines * hw->intr_tqps_num) * REG_NUM_PER_LINE; if (!hns->is_vf) { ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit); From patchwork Mon Jul 22 06:58:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Hai X-Patchwork-Id: 142569 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D9F134567C; Mon, 22 Jul 2024 09:05:51 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 83D2042EF4; Mon, 22 Jul 2024 09:05:26 +0200 (CEST) Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) by mails.dpdk.org (Postfix) with ESMTP id F2A3142DA3 for ; Mon, 22 Jul 2024 08:58:57 +0200 (CEST) Received: from mail.maildlp.com (unknown [172.19.88.214]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4WS9xj4gS5z28ffV; Mon, 22 Jul 2024 14:54:33 +0800 (CST) Received: from kwepemf500004.china.huawei.com (unknown [7.202.181.242]) by mail.maildlp.com (Postfix) with ESMTPS id 684AD1A016C; Mon, 22 Jul 2024 14:58:56 +0800 (CST) Received: from localhost.huawei.com (10.90.30.45) by kwepemf500004.china.huawei.com (7.202.181.242) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Mon, 22 Jul 2024 14:58:55 +0800 From: Jie Hai To: , Yisen Zhuang CC: , , , Subject: [PATCH v6 5/8] net/hns3: remove separators between register module Date: Mon, 22 Jul 2024 14:58:23 +0800 Message-ID: <20240722065826.3039119-6-haijie1@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20240722065826.3039119-1-haijie1@huawei.com> References: <20231214015650.3738578-1-haijie1@huawei.com> <20240722065826.3039119-1-haijie1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.90.30.45] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To kwepemf500004.china.huawei.com (7.202.181.242) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Since the driver is going to support reporting names of all registers, remove the counter and insert of separators between different register modules. Signed-off-by: Jie Hai Reviewed-by: Huisong Li Acked-by: Chengwen Feng --- drivers/net/hns3/hns3_regs.c | 68 ++++++++++-------------------------- 1 file changed, 18 insertions(+), 50 deletions(-) diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c index d9c546470dbe..c8e3fb118e4b 100644 --- a/drivers/net/hns3/hns3_regs.c +++ b/drivers/net/hns3/hns3_regs.c @@ -10,12 +10,9 @@ #include "hns3_rxtx.h" #include "hns3_regs.h" -#define MAX_SEPARATE_NUM 4 -#define SEPARATOR_VALUE 0xFFFFFFFF -#define REG_NUM_PER_LINE 4 -#define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(uint32_t)) +#define HNS3_64_BIT_REG_OUTPUT_SIZE (sizeof(uint64_t) / sizeof(uint32_t)) -static int hns3_get_dfx_reg_line(struct hns3_hw *hw, uint32_t *lines); +static int hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count); static const uint32_t cmdq_reg_addrs[] = {HNS3_CMDQ_TX_DEPTH_REG, HNS3_CMDQ_TX_TAIL_REG, @@ -111,23 +108,21 @@ static int hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length) { struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); - uint32_t cmdq_lines, common_lines, ring_lines, tqp_intr_lines; uint32_t regs_num_32_bit, regs_num_64_bit; - uint32_t dfx_reg_lines; + uint32_t dfx_reg_cnt; + uint32_t common_cnt; uint32_t len; int ret; - cmdq_lines = sizeof(cmdq_reg_addrs) / REG_LEN_PER_LINE + 1; if (hns->is_vf) - common_lines = - sizeof(common_vf_reg_addrs) / REG_LEN_PER_LINE + 1; + common_cnt = sizeof(common_vf_reg_addrs); else - common_lines = sizeof(common_reg_addrs) / REG_LEN_PER_LINE + 1; - ring_lines = sizeof(ring_reg_addrs) / REG_LEN_PER_LINE + 1; - tqp_intr_lines = sizeof(tqp_intr_reg_addrs) / REG_LEN_PER_LINE + 1; + common_cnt = sizeof(common_reg_addrs); - len = (cmdq_lines + common_lines + ring_lines * hw->tqps_num + - tqp_intr_lines * hw->intr_tqps_num) * REG_NUM_PER_LINE; + len = sizeof(cmdq_reg_addrs) + common_cnt + + sizeof(ring_reg_addrs) * hw->tqps_num + + sizeof(tqp_intr_reg_addrs) * hw->intr_tqps_num; + len /= sizeof(uint32_t); if (!hns->is_vf) { ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit); @@ -136,18 +131,16 @@ hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length) "ret = %d.", ret); return ret; } - dfx_reg_lines = regs_num_32_bit * sizeof(uint32_t) / - REG_LEN_PER_LINE + 1; - dfx_reg_lines += regs_num_64_bit * sizeof(uint64_t) / - REG_LEN_PER_LINE + 1; + dfx_reg_cnt = regs_num_32_bit + + regs_num_64_bit * HNS3_64_BIT_REG_OUTPUT_SIZE; - ret = hns3_get_dfx_reg_line(hw, &dfx_reg_lines); + ret = hns3_get_dfx_reg_cnt(hw, &dfx_reg_cnt); if (ret) { hns3_err(hw, "fail to get the number of dfx registers, " "ret = %d.", ret); return ret; } - len += dfx_reg_lines * REG_NUM_PER_LINE; + len += dfx_reg_cnt; } *length = len; @@ -268,18 +261,6 @@ hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data) return 0; } -static int -hns3_insert_reg_separator(int reg_num, uint32_t *data) -{ - int separator_num; - int i; - - separator_num = MAX_SEPARATE_NUM - reg_num % REG_NUM_PER_LINE; - for (i = 0; i < separator_num; i++) - *data++ = SEPARATOR_VALUE; - return separator_num; -} - static int hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data) { @@ -294,7 +275,6 @@ hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data) reg_num = sizeof(cmdq_reg_addrs) / sizeof(uint32_t); for (i = 0; i < reg_num; i++) *data++ = hns3_read_dev(hw, cmdq_reg_addrs[i]); - data += hns3_insert_reg_separator(reg_num, data); if (hns->is_vf) reg_num = sizeof(common_vf_reg_addrs) / sizeof(uint32_t); @@ -305,7 +285,6 @@ hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data) *data++ = hns3_read_dev(hw, common_vf_reg_addrs[i]); else *data++ = hns3_read_dev(hw, common_reg_addrs[i]); - data += hns3_insert_reg_separator(reg_num, data); reg_num = sizeof(ring_reg_addrs) / sizeof(uint32_t); for (j = 0; j < hw->tqps_num; j++) { @@ -313,7 +292,6 @@ hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data) for (i = 0; i < reg_num; i++) *data++ = hns3_read_dev(hw, ring_reg_addrs[i] + reg_offset); - data += hns3_insert_reg_separator(reg_num, data); } reg_num = sizeof(tqp_intr_reg_addrs) / sizeof(uint32_t); @@ -322,7 +300,6 @@ hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data) for (i = 0; i < reg_num; i++) *data++ = hns3_read_dev(hw, tqp_intr_reg_addrs[i] + reg_offset); - data += hns3_insert_reg_separator(reg_num, data); } return data - origin_data_ptr; } @@ -398,17 +375,15 @@ hns3_dfx_reg_fetch_data(struct hns3_cmd_desc *desc, int bd_num, uint32_t *reg) index = i % HNS3_CMD_DESC_DATA_NUM; *reg++ = desc[desc_index].data[index]; } - reg_num += hns3_insert_reg_separator(reg_num, reg); return reg_num; } static int -hns3_get_dfx_reg_line(struct hns3_hw *hw, uint32_t *lines) +hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count) { int opcode_num = RTE_DIM(hns3_dfx_reg_opcode_list); uint32_t bd_num_list[opcode_num]; - uint32_t bd_num, data_len; int ret; int i; @@ -416,11 +391,8 @@ hns3_get_dfx_reg_line(struct hns3_hw *hw, uint32_t *lines) if (ret) return ret; - for (i = 0; i < opcode_num; i++) { - bd_num = bd_num_list[i]; - data_len = bd_num * HNS3_CMD_DESC_DATA_NUM * sizeof(uint32_t); - *lines += data_len / REG_LEN_PER_LINE + 1; - } + for (i = 0; i < opcode_num; i++) + *count += bd_num_list[i] * HNS3_CMD_DESC_DATA_NUM; return 0; } @@ -467,7 +439,6 @@ hns3_get_dfx_regs(struct hns3_hw *hw, void **data) int hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs) { -#define HNS3_64_BIT_REG_SIZE (sizeof(uint64_t) / sizeof(uint32_t)) struct hns3_adapter *hns = eth_dev->data->dev_private; struct hns3_hw *hw = &hns->hw; uint32_t regs_num_32_bit; @@ -512,16 +483,13 @@ hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs) return ret; } data += regs_num_32_bit; - data += hns3_insert_reg_separator(regs_num_32_bit, data); ret = hns3_get_64_bit_regs(hw, regs_num_64_bit, data); if (ret) { hns3_err(hw, "Get 64 bit register failed, ret = %d", ret); return ret; } - data += regs_num_64_bit * HNS3_64_BIT_REG_SIZE; - data += hns3_insert_reg_separator(regs_num_64_bit * - HNS3_64_BIT_REG_SIZE, data); + data += regs_num_64_bit * HNS3_64_BIT_REG_OUTPUT_SIZE; return hns3_get_dfx_regs(hw, (void **)&data); } From patchwork Mon Jul 22 06:58:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Hai X-Patchwork-Id: 142571 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0E2984567C; Mon, 22 Jul 2024 09:06:06 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E86B642F43; Mon, 22 Jul 2024 09:05:28 +0200 (CEST) Received: from szxga03-in.huawei.com (szxga03-in.huawei.com [45.249.212.189]) by mails.dpdk.org (Postfix) with ESMTP id A1033427D6 for ; Mon, 22 Jul 2024 08:58:58 +0200 (CEST) Received: from mail.maildlp.com (unknown [172.19.163.174]) by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4WS9y01HskzQmSk; Mon, 22 Jul 2024 14:54:48 +0800 (CST) Received: from kwepemf500004.china.huawei.com (unknown [7.202.181.242]) by mail.maildlp.com (Postfix) with ESMTPS id 0444C140414; Mon, 22 Jul 2024 14:58:57 +0800 (CST) Received: from localhost.huawei.com (10.90.30.45) by kwepemf500004.china.huawei.com (7.202.181.242) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Mon, 22 Jul 2024 14:58:56 +0800 From: Jie Hai To: , Yisen Zhuang CC: , , , Subject: [PATCH v6 6/8] net/hns3: refactor register dump Date: Mon, 22 Jul 2024 14:58:24 +0800 Message-ID: <20240722065826.3039119-7-haijie1@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20240722065826.3039119-1-haijie1@huawei.com> References: <20231214015650.3738578-1-haijie1@huawei.com> <20240722065826.3039119-1-haijie1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.90.30.45] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To kwepemf500004.china.huawei.com (7.202.181.242) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch refactors codes dumping registers from firmware. Signed-off-by: Jie Hai --- drivers/net/hns3/hns3_regs.c | 203 ++++++++++++++++++++--------------- 1 file changed, 115 insertions(+), 88 deletions(-) diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c index c8e3fb118e4b..89858c2b1c09 100644 --- a/drivers/net/hns3/hns3_regs.c +++ b/drivers/net/hns3/hns3_regs.c @@ -104,12 +104,93 @@ hns3_get_regs_num(struct hns3_hw *hw, uint32_t *regs_num_32_bit, return 0; } +static int +hns3_get_32_64_regs_cnt(struct hns3_hw *hw, uint32_t *count) +{ + uint32_t regs_num_32_bit, regs_num_64_bit; + int ret; + + ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit); + if (ret) { + hns3_err(hw, "fail to get the number of registers, " + "ret = %d.", ret); + return ret; + } + + *count += regs_num_32_bit + regs_num_64_bit * HNS3_64_BIT_REG_OUTPUT_SIZE; + return 0; +} + +static int +hns3_get_dfx_reg_bd_num(struct hns3_hw *hw, uint32_t *bd_num_list, + uint32_t list_size) +{ +#define HNS3_GET_DFX_REG_BD_NUM_SIZE 4 + struct hns3_cmd_desc desc[HNS3_GET_DFX_REG_BD_NUM_SIZE]; + uint32_t index, desc_index; + uint32_t bd_num; + uint32_t i; + int ret; + + for (i = 0; i < HNS3_GET_DFX_REG_BD_NUM_SIZE - 1; i++) { + hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_DFX_BD_NUM, true); + desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); + } + /* The last BD does not need a next flag */ + hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_DFX_BD_NUM, true); + + ret = hns3_cmd_send(hw, desc, HNS3_GET_DFX_REG_BD_NUM_SIZE); + if (ret) { + hns3_err(hw, "fail to get dfx bd num, ret = %d.\n", ret); + return ret; + } + + /* The first data in the first BD is a reserved field */ + for (i = 1; i <= list_size; i++) { + desc_index = i / HNS3_CMD_DESC_DATA_NUM; + index = i % HNS3_CMD_DESC_DATA_NUM; + bd_num = rte_le_to_cpu_32(desc[desc_index].data[index]); + bd_num_list[i - 1] = bd_num; + } + + return 0; +} + +static int +hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count) +{ + int opcode_num = RTE_DIM(hns3_dfx_reg_opcode_list); + uint32_t bd_num_list[opcode_num]; + int ret; + int i; + + ret = hns3_get_dfx_reg_bd_num(hw, bd_num_list, opcode_num); + if (ret) + return ret; + + for (i = 0; i < opcode_num; i++) + *count += bd_num_list[i] * HNS3_CMD_DESC_DATA_NUM; + + return 0; +} + +static int +hns3_get_firmware_reg_cnt(struct hns3_hw *hw, uint32_t *count) +{ + int ret; + + ret = hns3_get_32_64_regs_cnt(hw, count); + if (ret < 0) + return ret; + + return hns3_get_dfx_reg_cnt(hw, count); +} + static int hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length) { struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); - uint32_t regs_num_32_bit, regs_num_64_bit; - uint32_t dfx_reg_cnt; + uint32_t dfx_reg_cnt = 0; uint32_t common_cnt; uint32_t len; int ret; @@ -125,16 +206,7 @@ hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length) len /= sizeof(uint32_t); if (!hns->is_vf) { - ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit); - if (ret) { - hns3_err(hw, "fail to get the number of registers, " - "ret = %d.", ret); - return ret; - } - dfx_reg_cnt = regs_num_32_bit + - regs_num_64_bit * HNS3_64_BIT_REG_OUTPUT_SIZE; - - ret = hns3_get_dfx_reg_cnt(hw, &dfx_reg_cnt); + ret = hns3_get_firmware_reg_cnt(hw, &dfx_reg_cnt); if (ret) { hns3_err(hw, "fail to get the number of dfx registers, " "ret = %d.", ret); @@ -304,41 +376,6 @@ hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data) return data - origin_data_ptr; } -static int -hns3_get_dfx_reg_bd_num(struct hns3_hw *hw, uint32_t *bd_num_list, - uint32_t list_size) -{ -#define HNS3_GET_DFX_REG_BD_NUM_SIZE 4 - struct hns3_cmd_desc desc[HNS3_GET_DFX_REG_BD_NUM_SIZE]; - uint32_t index, desc_index; - uint32_t bd_num; - uint32_t i; - int ret; - - for (i = 0; i < HNS3_GET_DFX_REG_BD_NUM_SIZE - 1; i++) { - hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_DFX_BD_NUM, true); - desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); - } - /* The last BD does not need a next flag */ - hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_DFX_BD_NUM, true); - - ret = hns3_cmd_send(hw, desc, HNS3_GET_DFX_REG_BD_NUM_SIZE); - if (ret) { - hns3_err(hw, "fail to get dfx bd num, ret = %d.\n", ret); - return ret; - } - - /* The first data in the first BD is a reserved field */ - for (i = 1; i <= list_size; i++) { - desc_index = i / HNS3_CMD_DESC_DATA_NUM; - index = i % HNS3_CMD_DESC_DATA_NUM; - bd_num = rte_le_to_cpu_32(desc[desc_index].data[index]); - bd_num_list[i - 1] = bd_num; - } - - return 0; -} - static int hns3_dfx_reg_cmd_send(struct hns3_hw *hw, struct hns3_cmd_desc *desc, int bd_num, uint32_t opcode) @@ -379,24 +416,6 @@ hns3_dfx_reg_fetch_data(struct hns3_cmd_desc *desc, int bd_num, uint32_t *reg) return reg_num; } -static int -hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count) -{ - int opcode_num = RTE_DIM(hns3_dfx_reg_opcode_list); - uint32_t bd_num_list[opcode_num]; - int ret; - int i; - - ret = hns3_get_dfx_reg_bd_num(hw, bd_num_list, opcode_num); - if (ret) - return ret; - - for (i = 0; i < opcode_num; i++) - *count += bd_num_list[i] * HNS3_CMD_DESC_DATA_NUM; - - return 0; -} - static int hns3_get_dfx_regs(struct hns3_hw *hw, void **data) { @@ -436,13 +455,41 @@ hns3_get_dfx_regs(struct hns3_hw *hw, void **data) return ret; } +static int +hns3_get_regs_from_firmware(struct hns3_hw *hw, uint32_t *data) +{ + uint32_t regs_num_32_bit; + uint32_t regs_num_64_bit; + int ret; + + ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit); + if (ret) { + hns3_err(hw, "Get register number failed, ret = %d", ret); + return ret; + } + + ret = hns3_get_32_bit_regs(hw, regs_num_32_bit, data); + if (ret) { + hns3_err(hw, "Get 32 bit register failed, ret = %d", ret); + return ret; + } + data += regs_num_32_bit; + + ret = hns3_get_64_bit_regs(hw, regs_num_64_bit, data); + if (ret) { + hns3_err(hw, "Get 64 bit register failed, ret = %d", ret); + return ret; + } + data += regs_num_64_bit * HNS3_64_BIT_REG_OUTPUT_SIZE; + + return hns3_get_dfx_regs(hw, (void **)&data); +} + int hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs) { struct hns3_adapter *hns = eth_dev->data->dev_private; struct hns3_hw *hw = &hns->hw; - uint32_t regs_num_32_bit; - uint32_t regs_num_64_bit; uint32_t length; uint32_t *data; int ret; @@ -470,26 +517,6 @@ hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs) if (hns->is_vf) return 0; - ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit); - if (ret) { - hns3_err(hw, "Get register number failed, ret = %d", ret); - return ret; - } - /* fetching PF common registers values from firmware */ - ret = hns3_get_32_bit_regs(hw, regs_num_32_bit, data); - if (ret) { - hns3_err(hw, "Get 32 bit register failed, ret = %d", ret); - return ret; - } - data += regs_num_32_bit; - - ret = hns3_get_64_bit_regs(hw, regs_num_64_bit, data); - if (ret) { - hns3_err(hw, "Get 64 bit register failed, ret = %d", ret); - return ret; - } - data += regs_num_64_bit * HNS3_64_BIT_REG_OUTPUT_SIZE; - - return hns3_get_dfx_regs(hw, (void **)&data); + return hns3_get_regs_from_firmware(hw, data); } From patchwork Mon Jul 22 06:58:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Hai X-Patchwork-Id: 142573 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B53154567C; Mon, 22 Jul 2024 09:06:21 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C24F842F77; Mon, 22 Jul 2024 09:05:31 +0200 (CEST) Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by mails.dpdk.org (Postfix) with ESMTP id 12B64427D6 for ; Mon, 22 Jul 2024 08:59:01 +0200 (CEST) Received: from mail.maildlp.com (unknown [172.19.88.105]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4WSB1w0sZQznbbB; Mon, 22 Jul 2024 14:58:12 +0800 (CST) Received: from kwepemf500004.china.huawei.com (unknown [7.202.181.242]) by mail.maildlp.com (Postfix) with ESMTPS id 96D08140382; Mon, 22 Jul 2024 14:58:57 +0800 (CST) Received: from localhost.huawei.com (10.90.30.45) by kwepemf500004.china.huawei.com (7.202.181.242) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Mon, 22 Jul 2024 14:58:57 +0800 From: Jie Hai To: , Yisen Zhuang CC: , , , Subject: [PATCH v6 7/8] net/hns3: support report names of registers Date: Mon, 22 Jul 2024 14:58:25 +0800 Message-ID: <20240722065826.3039119-8-haijie1@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20240722065826.3039119-1-haijie1@huawei.com> References: <20231214015650.3738578-1-haijie1@huawei.com> <20240722065826.3039119-1-haijie1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.90.30.45] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To kwepemf500004.china.huawei.com (7.202.181.242) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds names for register lists, and support report names of registers. Some registers has different names on different platform, use names of HIP08 as default names. Signed-off-by: Jie Hai --- drivers/net/hns3/hns3_regs.c | 1090 +++++++++++++++++++++++++++++----- 1 file changed, 957 insertions(+), 133 deletions(-) diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c index 89858c2b1c09..622d2e1c3d02 100644 --- a/drivers/net/hns3/hns3_regs.c +++ b/drivers/net/hns3/hns3_regs.c @@ -14,73 +14,829 @@ static int hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count); -static const uint32_t cmdq_reg_addrs[] = {HNS3_CMDQ_TX_DEPTH_REG, - HNS3_CMDQ_TX_TAIL_REG, - HNS3_CMDQ_TX_HEAD_REG, - HNS3_CMDQ_RX_DEPTH_REG, - HNS3_CMDQ_RX_TAIL_REG, - HNS3_CMDQ_RX_HEAD_REG, - HNS3_VECTOR0_CMDQ_SRC_REG, - HNS3_CMDQ_INTR_STS_REG, - HNS3_CMDQ_INTR_EN_REG, - HNS3_CMDQ_INTR_GEN_REG}; - -static const uint32_t common_reg_addrs[] = {HNS3_MISC_VECTOR_REG_BASE, - HNS3_VECTOR0_OTER_EN_REG, - HNS3_MISC_RESET_STS_REG, - HNS3_VECTOR0_OTHER_INT_STS_REG, - HNS3_GLOBAL_RESET_REG, - HNS3_FUN_RST_ING, - HNS3_GRO_EN_REG}; - -static const uint32_t common_vf_reg_addrs[] = {HNS3_MISC_VECTOR_REG_BASE, - HNS3_FUN_RST_ING, - HNS3_GRO_EN_REG}; - -static const uint32_t ring_reg_addrs[] = {HNS3_RING_RX_BD_NUM_REG, - HNS3_RING_RX_BD_LEN_REG, - HNS3_RING_RX_EN_REG, - HNS3_RING_RX_MERGE_EN_REG, - HNS3_RING_RX_TAIL_REG, - HNS3_RING_RX_HEAD_REG, - HNS3_RING_RX_FBDNUM_REG, - HNS3_RING_RX_OFFSET_REG, - HNS3_RING_RX_FBD_OFFSET_REG, - HNS3_RING_RX_STASH_REG, - HNS3_RING_RX_BD_ERR_REG, - HNS3_RING_TX_BD_NUM_REG, - HNS3_RING_TX_EN_REG, - HNS3_RING_TX_PRIORITY_REG, - HNS3_RING_TX_TC_REG, - HNS3_RING_TX_MERGE_EN_REG, - HNS3_RING_TX_TAIL_REG, - HNS3_RING_TX_HEAD_REG, - HNS3_RING_TX_FBDNUM_REG, - HNS3_RING_TX_OFFSET_REG, - HNS3_RING_TX_EBD_NUM_REG, - HNS3_RING_TX_EBD_OFFSET_REG, - HNS3_RING_TX_BD_ERR_REG, - HNS3_RING_EN_REG}; - -static const uint32_t tqp_intr_reg_addrs[] = {HNS3_TQP_INTR_CTRL_REG, - HNS3_TQP_INTR_GL0_REG, - HNS3_TQP_INTR_GL1_REG, - HNS3_TQP_INTR_GL2_REG, - HNS3_TQP_INTR_RL_REG}; +struct hns3_dirt_reg_entry { + const char *name; + uint32_t addr; +}; + +static const struct hns3_dirt_reg_entry cmdq_reg_list[] = { + {"cmdq_tx_depth", HNS3_CMDQ_TX_DEPTH_REG}, + {"cmdq_tx_tail", HNS3_CMDQ_TX_TAIL_REG}, + {"cmdq_tx_head", HNS3_CMDQ_TX_HEAD_REG}, + {"cmdq_rx_depth", HNS3_CMDQ_RX_DEPTH_REG}, + {"cmdq_rx_tail", HNS3_CMDQ_RX_TAIL_REG}, + {"cmdq_rx_head", HNS3_CMDQ_RX_HEAD_REG}, + {"vector0_cmdq_src", HNS3_VECTOR0_CMDQ_SRC_REG}, + {"cmdq_intr_sts", HNS3_CMDQ_INTR_STS_REG}, + {"cmdq_intr_en", HNS3_CMDQ_INTR_EN_REG}, + {"cmdq_intr_gen", HNS3_CMDQ_INTR_GEN_REG}, +}; + +static const struct hns3_dirt_reg_entry common_reg_list[] = { + {"misc_vector_reg_base", HNS3_MISC_VECTOR_REG_BASE}, + {"vector0_oter_en", HNS3_VECTOR0_OTER_EN_REG}, + {"misc_reset_sts", HNS3_MISC_RESET_STS_REG}, + {"vector0_other_int_sts", HNS3_VECTOR0_OTHER_INT_STS_REG}, + {"global_reset", HNS3_GLOBAL_RESET_REG}, + {"fun_rst_ing", HNS3_FUN_RST_ING}, + {"gro_en", HNS3_GRO_EN_REG}, +}; + +static const struct hns3_dirt_reg_entry common_vf_reg_list[] = { + {"misc_vector_reg_base", HNS3_MISC_VECTOR_REG_BASE}, + {"fun_rst_ing", HNS3_FUN_RST_ING}, + {"gro_en", HNS3_GRO_EN_REG}, +}; + +static const struct hns3_dirt_reg_entry ring_reg_list[] = { + {"ring_rx_bd_num", HNS3_RING_RX_BD_NUM_REG}, + {"ring_rx_bd_len", HNS3_RING_RX_BD_LEN_REG}, + {"ring_rx_en", HNS3_RING_RX_EN_REG}, + {"ring_rx_merge_en", HNS3_RING_RX_MERGE_EN_REG}, + {"ring_rx_tail", HNS3_RING_RX_TAIL_REG}, + {"ring_rx_head", HNS3_RING_RX_HEAD_REG}, + {"ring_rx_fbdnum", HNS3_RING_RX_FBDNUM_REG}, + {"ring_rx_offset", HNS3_RING_RX_OFFSET_REG}, + {"ring_rx_fbd_offset", HNS3_RING_RX_FBD_OFFSET_REG}, + {"ring_rx_stash", HNS3_RING_RX_STASH_REG}, + {"ring_rx_bd_err", HNS3_RING_RX_BD_ERR_REG}, + {"ring_tx_bd_num", HNS3_RING_TX_BD_NUM_REG}, + {"ring_tx_en", HNS3_RING_TX_EN_REG}, + {"ring_tx_priority", HNS3_RING_TX_PRIORITY_REG}, + {"ring_tx_tc", HNS3_RING_TX_TC_REG}, + {"ring_tx_merge_en", HNS3_RING_TX_MERGE_EN_REG}, + {"ring_tx_tail", HNS3_RING_TX_TAIL_REG}, + {"ring_tx_head", HNS3_RING_TX_HEAD_REG}, + {"ring_tx_fbdnum", HNS3_RING_TX_FBDNUM_REG}, + {"ring_tx_offset", HNS3_RING_TX_OFFSET_REG}, + {"ring_tx_ebd_num", HNS3_RING_TX_EBD_NUM_REG}, + {"ring_tx_ebd_offset", HNS3_RING_TX_EBD_OFFSET_REG}, + {"ring_tx_bd_err", HNS3_RING_TX_BD_ERR_REG}, + {"ring_en", HNS3_RING_EN_REG}, +}; + +static const struct hns3_dirt_reg_entry tqp_intr_reg_list[] = { + {"tqp_intr_ctrl", HNS3_TQP_INTR_CTRL_REG}, + {"tqp_intr_gl0", HNS3_TQP_INTR_GL0_REG}, + {"tqp_intr_gl1", HNS3_TQP_INTR_GL1_REG}, + {"tqp_intr_gl2", HNS3_TQP_INTR_GL2_REG}, + {"tqp_intr_rl", HNS3_TQP_INTR_RL_REG}, +}; + +struct hns3_dfx_reg_entry { + /** + * name_v1 -- default register name for all platforms (HIP08/HIP09/newer). + * name_v2 -- register name different from the default for HIP09. + * If there are more platform with different register name, name_vXX is extended. + * If the platform is newer than HIP09, use default name. + */ + const char *name_v1; + const char *name_v2; +}; + +static struct hns3_dfx_reg_entry regs_32_bit_list[] = { + {"ssu_common_err_int"}, + {"ssu_port_based_err_int"}, + {"ssu_fifo_overflow_int"}, + {"ssu_ets_tcg_int"}, + {"ssu_bp_status_0"}, + {"ssu_bp_status_1"}, + + {"ssu_bp_status_2"}, + {"ssu_bp_status_3"}, + {"ssu_bp_status_4"}, + {"ssu_bp_status_5"}, + {"ssu_mac_tx_pfc_ind"}, + {"ssu_mac_rx_pfc_ind"}, + + {"ssu_rx_oq_drop_pkt_cnt"}, + {"ssu_tx_oq_drop_pkt_cnt"}, +}; + +static struct hns3_dfx_reg_entry regs_64_bit_list[] = { + {"ppp_get_rx_pkt_cnt_l"}, + {"ppp_get_rx_pkt_cnt_h"}, + {"ppp_get_tx_pkt_cnt_l"}, + {"ppp_get_tx_pkt_cnt_h"}, + {"ppp_send_uc_prt2host_pkt_cnt_l"}, + {"ppp_send_uc_prt2host_pkt_cnt_h"}, + + {"ppp_send_uc_prt2prt_pkt_cnt_l"}, + {"ppp_send_uc_prt2prt_pkt_cnt_h"}, + {"ppp_send_uc_host2host_pkt_cnt_l"}, + {"ppp_send_uc_host2host_pkt_cnt_h"}, + {"ppp_send_uc_host2prt_pkt_cnt_l"}, + {"ppp_send_uc_host2prt_pkt_cnt_h"}, + {"ppp_send_mc_from_prt_cnt_l"}, + {"ppp_send_mc_from_prt_cnt_h"}, +}; + +static struct hns3_dfx_reg_entry dfx_bios_common_reg_list[] = { + {"bios_rsv0"}, + {"bp_cpu_state"}, + {"dfx_msix_info_nic_0"}, + {"dfx_msix_info_nic_1"}, + {"dfx_msix_info_nic_2"}, + {"dfx_msix_info_nic_3"}, + + {"dfx_msix_info_roce_0"}, + {"dfx_msix_info_roce_1"}, + {"dfx_msix_info_roce_2"}, + {"dfx_msix_info_roce_3"}, + {"bios_rsv1"}, + {"bios_rsv2"}, +}; + +static struct hns3_dfx_reg_entry dfx_ssu_reg_0_list[] = { + {"dfx_ssu0_rsv0"}, + {"ssu_ets_port_status"}, + {"ssu_ets_tcg_status"}, + {"dfx_ssu0_rsv1"}, + {"dfx_ssu0_rsv2"}, + {"ssu_bp_status_0"}, + + {"ssu_bp_status_1"}, + {"ssu_bp_status_2"}, + {"ssu_bp_status_3"}, + {"ssu_bp_status_4"}, + {"ssu_bp_status_5"}, + {"ssu_mac_tx_pfc_ind"}, + + {"mac_ssu_rx_pfc_ind"}, + {"btmp_ageing_st_b0"}, + {"btmp_ageing_st_b1"}, + {"btmp_ageing_st_b2"}, + {"dfx_ssu0_rsv3"}, + {"dfx_ssu0_rsv4"}, + + {"ssu_full_drop_num"}, + {"ssu_part_drop_num"}, + {"ppp_key_drop_num"}, + {"ppp_rlt_drop_num"}, + {"lo_pri_unicast_rlt_drop_num"}, + {"hi_pri_multicast_rlt_drop_num"}, + + {"lo_pri_multicast_rlt_drop_num"}, + {"ncsi_packet_curr_buffer_cnt"}, + {"btmp_ageing_rls_cnt_bank0", "dfx_ssu0_rsv5"}, + {"btmp_ageing_rls_cnt_bank1", "dfx_ssu0_rsv6"}, + {"btmp_ageing_rls_cnt_bank2", "dfx_ssu0_rsv7"}, + {"ssu_mb_rd_rlt_drop_cnt"}, + + {"ssu_ppp_mac_key_num_l"}, + {"ssu_ppp_mac_key_num_h"}, + {"ssu_ppp_host_key_num_l"}, + {"ssu_ppp_host_key_num_h"}, + {"ppp_ssu_mac_rlt_num_l"}, + {"ppp_ssu_mac_rlt_num_h"}, + + {"ppp_ssu_host_rlt_num_l"}, + {"ppp_ssu_host_rlt_num_h"}, + {"ncsi_rx_packet_in_cnt_l"}, + {"ncsi_rx_packet_in_cnt_h"}, + {"ncsi_tx_packet_out_cnt_l"}, + {"ncsi_tx_packet_out_cnt_h"}, + + {"ssu_key_drop_num"}, + {"mb_uncopy_num"}, + {"rx_oq_drop_pkt_cnt"}, + {"tx_oq_drop_pkt_cnt"}, + {"bank_unbalance_drop_cnt"}, + {"bank_unbalance_rx_drop_cnt"}, + + {"nic_l2_eer_drop_pkt_cnt"}, + {"roc_l2_eer_drop_pkt_cnt"}, + {"nic_l2_eer_drop_pkt_cnt_rx"}, + {"roc_l2_eer_drop_pkt_cnt_rx"}, + {"rx_oq_glb_drop_pkt_cnt"}, + {"dfx_ssu0_rsv8"}, + + {"lo_pri_unicast_cur_cnt"}, + {"hi_pri_multicast_cur_cnt"}, + {"lo_pri_multicast_cur_cnt"}, + {"dfx_ssu0_rsv9"}, + {"dfx_ssu0_rsv10"}, + {"dfx_ssu0_rsv11"}, +}; + +static struct hns3_dfx_reg_entry dfx_ssu_reg_1_list[] = { + {"dfx_ssu1_prt_id"}, + {"packet_tc_curr_buffer_cnt_0"}, + {"packet_tc_curr_buffer_cnt_1"}, + {"packet_tc_curr_buffer_cnt_2"}, + {"packet_tc_curr_buffer_cnt_3"}, + {"packet_tc_curr_buffer_cnt_4"}, + + {"packet_tc_curr_buffer_cnt_5"}, + {"packet_tc_curr_buffer_cnt_6"}, + {"packet_tc_curr_buffer_cnt_7"}, + {"packet_curr_buffer_cnt"}, + {"dfx_ssu1_rsv0"}, + {"dfx_ssu1_rsv1"}, + + {"rx_packet_in_cnt_l"}, + {"rx_packet_in_cnt_h"}, + {"rx_packet_out_cnt_l"}, + {"rx_packet_out_cnt_h"}, + {"tx_packet_in_cnt_l"}, + {"tx_packet_in_cnt_h"}, + + {"tx_packet_out_cnt_l"}, + {"tx_packet_out_cnt_h"}, + {"roc_rx_packet_in_cnt_l"}, + {"roc_rx_packet_in_cnt_h"}, + {"roc_tx_packet_in_cnt_l"}, + {"roc_tx_packet_in_cnt_h"}, + + {"rx_packet_tc_in_cnt_0_l"}, + {"rx_packet_tc_in_cnt_0_h"}, + {"rx_packet_tc_in_cnt_1_l"}, + {"rx_packet_tc_in_cnt_1_h"}, + {"rx_packet_tc_in_cnt_2_l"}, + {"rx_packet_tc_in_cnt_2_h"}, + + {"rx_packet_tc_in_cnt_3_l"}, + {"rx_packet_tc_in_cnt_3_h"}, + {"rx_packet_tc_in_cnt_4_l"}, + {"rx_packet_tc_in_cnt_4_h"}, + {"rx_packet_tc_in_cnt_5_l"}, + {"rx_packet_tc_in_cnt_5_h"}, + + {"rx_packet_tc_in_cnt_6_l"}, + {"rx_packet_tc_in_cnt_6_h"}, + {"rx_packet_tc_in_cnt_7_l"}, + {"rx_packet_tc_in_cnt_7_h"}, + {"rx_packet_tc_out_cnt_0_l"}, + {"rx_packet_tc_out_cnt_0_h"}, + + {"rx_packet_tc_out_cnt_1_l"}, + {"rx_packet_tc_out_cnt_1_h"}, + {"rx_packet_tc_out_cnt_2_l"}, + {"rx_packet_tc_out_cnt_2_h"}, + {"rx_packet_tc_out_cnt_3_l"}, + {"rx_packet_tc_out_cnt_3_h"}, + + {"rx_packet_tc_out_cnt_4_l"}, + {"rx_packet_tc_out_cnt_4_h"}, + {"rx_packet_tc_out_cnt_5_l"}, + {"rx_packet_tc_out_cnt_5_h"}, + {"rx_packet_tc_out_cnt_6_l"}, + {"rx_packet_tc_out_cnt_6_h"}, + + {"rx_packet_tc_out_cnt_7_l"}, + {"rx_packet_tc_out_cnt_7_h"}, + {"tx_packet_tc_in_cnt_0_l"}, + {"tx_packet_tc_in_cnt_0_h"}, + {"tx_packet_tc_in_cnt_1_l"}, + {"tx_packet_tc_in_cnt_1_h"}, + + {"tx_packet_tc_in_cnt_2_l"}, + {"tx_packet_tc_in_cnt_2_h"}, + {"tx_packet_tc_in_cnt_3_l"}, + {"tx_packet_tc_in_cnt_3_h"}, + {"tx_packet_tc_in_cnt_4_l"}, + {"tx_packet_tc_in_cnt_4_h"}, + + {"tx_packet_tc_in_cnt_5_l"}, + {"tx_packet_tc_in_cnt_5_h"}, + {"tx_packet_tc_in_cnt_6_l"}, + {"tx_packet_tc_in_cnt_6_h"}, + {"tx_packet_tc_in_cnt_7_l"}, + {"tx_packet_tc_in_cnt_7_h"}, + + {"tx_packet_tc_out_cnt_0_l"}, + {"tx_packet_tc_out_cnt_0_h"}, + {"tx_packet_tc_out_cnt_1_l"}, + {"tx_packet_tc_out_cnt_1_h"}, + {"tx_packet_tc_out_cnt_2_l"}, + {"tx_packet_tc_out_cnt_2_h"}, + + {"tx_packet_tc_out_cnt_3_l"}, + {"tx_packet_tc_out_cnt_3_h"}, + {"tx_packet_tc_out_cnt_4_l"}, + {"tx_packet_tc_out_cnt_4_h"}, + {"tx_packet_tc_out_cnt_5_l"}, + {"tx_packet_tc_out_cnt_5_h"}, + + {"tx_packet_tc_out_cnt_6_l"}, + {"tx_packet_tc_out_cnt_6_h"}, + {"tx_packet_tc_out_cnt_7_l"}, + {"tx_packet_tc_out_cnt_7_h"}, + {"dfx_ssu1_rsv2"}, + {"dfx_ssu1_rsv3"}, +}; + +static struct hns3_dfx_reg_entry dfx_igu_egu_reg_list[] = { + {"igu_egu_prt_id"}, + {"igu_rx_err_pkt"}, + {"igu_rx_no_sof_pkt"}, + {"egu_tx_1588_short_pkt"}, + {"egu_tx_1588_pkt"}, + {"egu_tx_1588_err_pkt"}, + + {"igu_rx_out_l2_pkt"}, + {"igu_rx_out_l3_pkt"}, + {"igu_rx_out_l4_pkt"}, + {"igu_rx_in_l2_pkt"}, + {"igu_rx_in_l3_pkt"}, + {"igu_rx_in_l4_pkt"}, + + {"igu_rx_el3e_pkt"}, + {"igu_rx_el4e_pkt"}, + {"igu_rx_l3e_pkt"}, + {"igu_rx_l4e_pkt"}, + {"igu_rx_rocee_pkt"}, + {"igu_rx_out_udp0_pkt"}, + + {"igu_rx_in_udp0_pkt"}, + {"igu_egu_rsv0", "igu_egu_mul_car_drop_pkt_cnt_l"}, + {"igu_egu_rsv1", "igu_egu_mul_car_drop_pkt_cnt_h"}, + {"igu_egu_rsv2", "igu_egu_bro_car_drop_pkt_cnt_l"}, + {"igu_egu_rsv3", "igu_egu_bro_car_drop_pkt_cnt_h"}, + {"igu_egu_rsv4", "igu_egu_rsv0"}, + + {"igu_rx_oversize_pkt_l"}, + {"igu_rx_oversize_pkt_h"}, + {"igu_rx_undersize_pkt_l"}, + {"igu_rx_undersize_pkt_h"}, + {"igu_rx_out_all_pkt_l"}, + {"igu_rx_out_all_pkt_h"}, + + {"igu_tx_out_all_pkt_l"}, + {"igu_tx_out_all_pkt_h"}, + {"igu_rx_uni_pkt_l"}, + {"igu_rx_uni_pkt_h"}, + {"igu_rx_multi_pkt_l"}, + {"igu_rx_multi_pkt_h"}, + + {"igu_rx_broad_pkt_l"}, + {"igu_rx_broad_pkt_h"}, + {"egu_tx_out_all_pkt_l"}, + {"egu_tx_out_all_pkt_h"}, + {"egu_tx_uni_pkt_l"}, + {"egu_tx_uni_pkt_h"}, + + {"egu_tx_multi_pkt_l"}, + {"egu_tx_multi_pkt_h"}, + {"egu_tx_broad_pkt_l"}, + {"egu_tx_broad_pkt_h"}, + {"igu_tx_key_num_l"}, + {"igu_tx_key_num_h"}, + + {"igu_rx_non_tun_pkt_l"}, + {"igu_rx_non_tun_pkt_h"}, + {"igu_rx_tun_pkt_l"}, + {"igu_rx_tun_pkt_h"}, + {"igu_egu_rsv5"}, + {"igu_egu_rsv6"}, +}; + +static struct hns3_dfx_reg_entry dfx_rpu_reg_0_list[] = { + {"rpu_tc_queue_num", "rpu_currport_tnl_index"}, + {"rpu_fsm_dfx_st0"}, + {"rpu_fsm_dfx_st1"}, + {"rpu_rpu_rx_pkt_drop_cnt"}, + {"rpu_buf_wait_timeout"}, + {"rpu_buf_wait_timeout_qid"}, +}; + +static struct hns3_dfx_reg_entry dfx_rpu_reg_1_list[] = { + {"rpu_rsv0"}, + {"rpu_fifo_dfx_st0"}, + {"rpu_fifo_dfx_st1"}, + {"rpu_fifo_dfx_st2"}, + {"rpu_fifo_dfx_st3"}, + {"rpu_fifo_dfx_st4"}, + + {"rpu_fifo_dfx_st5"}, + {"rpu_rsv1"}, + {"rpu_rsv2"}, + {"rpu_rsv3"}, + {"rpu_rsv4"}, + {"rpu_rsv5"}, +}; + +static struct hns3_dfx_reg_entry dfx_ncsi_reg_list[] = { + {"ncsi_rsv0"}, + {"ncsi_egu_tx_fifo_sts"}, + {"ncsi_pause_status"}, + {"ncsi_rx_ctrl_dmac_err_cnt"}, + {"ncsi_rx_ctrl_smac_err_cnt"}, + {"ncsi_rx_ctrl_cks_err_cnt"}, + + {"ncsi_rx_ctrl_pkt_err_cnt"}, + {"ncsi_rx_pt_dmac_err_cnt"}, + {"ncsi_rx_pt_smac_err_cnt"}, + {"ncsi_rx_pt_pkt_cnt"}, + {"ncsi_rx_fcs_err_cnt"}, + {"ncsi_tx_ctrl_dmac_err_cnt"}, + + {"ncsi_tx_ctrl_smac_err_cnt"}, + {"ncsi_tx_ctrl_pkt_cnt"}, + {"ncsi_tx_pt_dmac_err_cnt"}, + {"ncsi_tx_pt_smac_err_cnt"}, + {"ncsi_tx_pt_pkt_cnt"}, + {"ncsi_tx_pt_pkt_trun_cnt"}, + + {"ncsi_tx_pt_pkt_err_cnt"}, + {"ncsi_tx_ctrl_pkt_err_cnt"}, + {"ncsi_rx_ctrl_pkt_trun_cnt"}, + {"ncsi_rx_ctrl_pkt_cflit_cnt"}, + {"ncsi_rsv1"}, + {"ncsi_rsv2"}, + + {"ncsi_mac_rx_octets_ok"}, + {"ncsi_mac_rx_octets_bad"}, + {"ncsi_mac_rx_uc_pkts"}, + {"ncsi_mac_rx_mc_pkts"}, + {"ncsi_mac_rx_bc_pkts"}, + {"ncsi_mac_rx_pkts_64octets"}, + + {"ncsi_mac_rx_pkts_64to127_octets"}, + {"ncsi_mac_rx_pkts_128to255_octets"}, + {"ncsi_mac_rx_pkts_256to511_octets"}, + {"ncsi_mac_rx_pkts_512to1023_octets"}, + {"ncsi_mac_rx_pkts_1024to1518_octets"}, + {"ncsi_mac_rx_pkts_1519tomax_octets"}, + + {"ncsi_mac_rx_fcs_errors"}, + {"ncsi_mac_rx_long_errors"}, + {"ncsi_mac_rx_jabber_errors"}, + {"ncsi_mac_rx_runt_err_cnt"}, + {"ncsi_mac_rx_short_err_cnt"}, + {"ncsi_mac_rx_filt_pkt_cnt"}, + + {"ncsi_mac_rx_octets_total_filt"}, + {"ncsi_mac_tx_octets_ok"}, + {"ncsi_mac_tx_octets_bad"}, + {"ncsi_mac_tx_uc_pkts"}, + {"ncsi_mac_tx_mc_pkts"}, + {"ncsi_mac_tx_bc_pkts"}, + + {"ncsi_mac_tx_pkts_64octets"}, + {"ncsi_mac_tx_pkts_64to127_octets"}, + {"ncsi_mac_tx_pkts_128to255_octets"}, + {"ncsi_mac_tx_pkts_256to511_octets"}, + {"ncsi_mac_tx_pkts_512to1023_octets"}, + {"ncsi_mac_tx_pkts_1024to1518_octets"}, + + {"ncsi_mac_tx_pkts_1519tomax_octets"}, + {"ncsi_mac_tx_underrun"}, + {"ncsi_mac_tx_crc_error"}, + {"ncsi_mac_tx_pause_frames"}, + {"ncsi_mac_rx_pad_pkts"}, + {"ncsi_mac_rx_pause_frames"}, +}; + +static struct hns3_dfx_reg_entry dfx_rtc_reg_list[] = { + {"rtc_rsv0"}, + {"lge_igu_afifo_dfx_0"}, + {"lge_igu_afifo_dfx_1"}, + {"lge_igu_afifo_dfx_2"}, + {"lge_igu_afifo_dfx_3"}, + {"lge_igu_afifo_dfx_4"}, + + {"lge_igu_afifo_dfx_5"}, + {"lge_igu_afifo_dfx_6"}, + {"lge_igu_afifo_dfx_7"}, + {"lge_egu_afifo_dfx_0"}, + {"lge_egu_afifo_dfx_1"}, + {"lge_egu_afifo_dfx_2"}, + + {"lge_egu_afifo_dfx_3"}, + {"lge_egu_afifo_dfx_4"}, + {"lge_egu_afifo_dfx_5"}, + {"lge_egu_afifo_dfx_6"}, + {"lge_egu_afifo_dfx_7"}, + {"cge_igu_afifo_dfx_0"}, + + {"cge_igu_afifo_dfx_1"}, + {"cge_egu_afifo_dfx_0"}, + {"cge_egu_afifo_dfx_i"}, + {"rtc_rsv1"}, + {"rtc_rsv2"}, + {"rtc_rsv3"}, +}; + +static struct hns3_dfx_reg_entry dfx_ppp_reg_list[] = { + {"ppp_rsv0"}, + {"ppp_drop_from_prt_pkt_cnt"}, + {"ppp_drop_from_host_pkt_cnt"}, + {"ppp_drop_tx_vlan_proc_cnt"}, + {"ppp_drop_mng_cnt"}, + {"ppp_drop_fd_cnt"}, + + {"ppp_drop_no_dst_cnt"}, + {"ppp_drop_mc_mbid_full_cnt"}, + {"ppp_drop_sc_filtered"}, + {"ppp_ppp_mc_drop_pkt_cnt"}, + {"ppp_drop_pt_cnt"}, + {"ppp_drop_mac_anti_spoof_cnt"}, + + {"ppp_drop_ig_vfv_cnt"}, + {"ppp_drop_ig_prtv_cnt"}, + {"ppp_drop_cnm_pfc_pause_cnt"}, + {"ppp_drop_torus_tc_cnt"}, + {"ppp_drop_torus_lpbk_cnt"}, + {"ppp_ppp_hfs_sts"}, + + {"ppp_mc_rslt_sts"}, + {"ppp_p3u_sts"}, + {"ppp_rslt_descr_sts", "ppp_rsv1"}, + {"ppp_umv_sts_0"}, + {"ppp_umv_sts_1"}, + {"ppp_vfv_sts"}, + + {"ppp_gro_key_cnt"}, + {"ppp_gro_info_cnt"}, + {"ppp_gro_drop_cnt"}, + {"ppp_gro_out_cnt"}, + {"ppp_gro_key_match_data_cnt"}, + {"ppp_gro_key_match_tcam_cnt"}, + + {"ppp_gro_info_match_cnt"}, + {"ppp_gro_free_entry_cnt"}, + {"ppp_gro_inner_dfx_signal"}, + {"ppp_rsv2"}, + {"ppp_rsv3"}, + {"ppp_rsv4"}, + + {"ppp_get_rx_pkt_cnt_l"}, + {"ppp_get_rx_pkt_cnt_h"}, + {"ppp_get_tx_pkt_cnt_l"}, + {"ppp_get_tx_pkt_cnt_h"}, + {"ppp_send_uc_prt2host_pkt_cnt_l"}, + {"ppp_send_uc_prt2host_pkt_cnt_h"}, + + {"ppp_send_uc_prt2prt_pkt_cnt_l"}, + {"ppp_send_uc_prt2prt_pkt_cnt_h"}, + {"ppp_send_uc_host2host_pkt_cnt_l"}, + {"ppp_send_uc_host2host_pkt_cnt_h"}, + {"ppp_send_uc_host2prt_pkt_cnt_l"}, + {"ppp_send_uc_host2prt_pkt_cnt_h"}, + + {"ppp_send_mc_from_prt_cnt_l"}, + {"ppp_send_mc_from_prt_cnt_h"}, + {"ppp_send_mc_from_host_cnt_l"}, + {"ppp_send_mc_from_host_cnt_h"}, + {"ppp_ssu_mc_rd_cnt_l"}, + {"ppp_ssu_mc_rd_cnt_h"}, + + {"ppp_ssu_mc_drop_cnt_l"}, + {"ppp_ssu_mc_drop_cnt_h"}, + {"ppp_ssu_mc_rd_pkt_cnt_l"}, + {"ppp_ssu_mc_rd_pkt_cnt_h"}, + {"ppp_mc_2host_pkt_cnt_l"}, + {"ppp_mc_2host_pkt_cnt_h"}, + + {"ppp_mc_2prt_pkt_cnt_l"}, + {"ppp_mc_2prt_pkt_cnt_h"}, + {"ppp_ntsnos_pkt_cnt_l"}, + {"ppp_ntsnos_pkt_cnt_h"}, + {"ppp_ntup_pkt_cnt_l"}, + {"ppp_ntup_pkt_cnt_h"}, + + {"ppp_ntlcl_pkt_cnt_l"}, + {"ppp_ntlcl_pkt_cnt_h"}, + {"ppp_nttgt_pkt_cnt_l"}, + {"ppp_nttgt_pkt_cnt_h"}, + {"ppp_rtns_pkt_cnt_l"}, + {"ppp_rtns_pkt_cnt_h"}, + + {"ppp_rtlpbk_pkt_cnt_l"}, + {"ppp_rtlpbk_pkt_cnt_h"}, + {"ppp_nr_pkt_cnt_l"}, + {"ppp_nr_pkt_cnt_h"}, + {"ppp_rr_pkt_cnt_l"}, + {"ppp_rr_pkt_cnt_h"}, + + {"ppp_mng_tbl_hit_cnt_l"}, + {"ppp_mng_tbl_hit_cnt_h"}, + {"ppp_fd_tbl_hit_cnt_l"}, + {"ppp_fd_tbl_hit_cnt_h"}, + {"ppp_fd_lkup_cnt_l"}, + {"ppp_fd_lkup_cnt_h"}, + + {"ppp_bc_hit_cnt"}, + {"ppp_bc_hit_cnt_h"}, + {"ppp_um_tbl_uc_hit_cnt"}, + {"ppp_um_tbl_uc_hit_cnt_h"}, + {"ppp_um_tbl_mc_hit_cnt"}, + {"ppp_um_tbl_mc_hit_cnt_h"}, + + {"ppp_um_tbl_vmdq1_hit_cnt_l", "ppp_um_tbl_snq_hit_cnt_l"}, + {"ppp_um_tbl_vmdq1_hit_cnt_h", "ppp_um_tbl_snq_hit_cnt_h"}, + {"ppp_mta_tbl_hit_cnt_l", "ppp_rsv5"}, + {"ppp_mta_tbl_hit_cnt_h", "ppp_rsv6"}, + {"ppp_fwd_bonding_hit_cnt_l"}, + {"ppp_fwd_bonding_hit_cnt_h"}, + + {"ppp_promisc_tbl_hit_cnt_l"}, + {"ppp_promisc_tbl_hit_cnt_h"}, + {"ppp_get_tunl_pkt_cnt_l"}, + {"ppp_get_tunl_pkt_cnt_h"}, + {"ppp_get_bmc_pkt_cnt_l"}, + {"ppp_get_bmc_pkt_cnt_h"}, + + {"ppp_send_uc_prt2bmc_pkt_cnt_l"}, + {"ppp_send_uc_prt2bmc_pkt_cnt_h"}, + {"ppp_send_uc_host2bmc_pkt_cnt_l"}, + {"ppp_send_uc_host2bmc_pkt_cnt_h"}, + {"ppp_send_uc_bmc2host_pkt_cnt_l"}, + {"ppp_send_uc_bmc2host_pkt_cnt_h"}, + + {"ppp_send_uc_bmc2prt_pkt_cnt_l"}, + {"ppp_send_uc_bmc2prt_pkt_cnt_h"}, + {"ppp_mc_2bmc_pkt_cnt_l"}, + {"ppp_mc_2bmc_pkt_cnt_h"}, + {"ppp_vlan_mirr_cnt_l", "ppp_rsv7"}, + {"ppp_vlan_mirr_cnt_h", "ppp_rsv8"}, + + {"ppp_ig_mirr_cnt_l", "ppp_rsv9"}, + {"ppp_ig_mirr_cnt_h", "ppp_rsv10"}, + {"ppp_eg_mirr_cnt_l", "ppp_rsv11"}, + {"ppp_eg_mirr_cnt_h", "ppp_rsv12"}, + {"ppp_rx_default_host_hit_cnt_l"}, + {"ppp_rx_default_host_hit_cnt_h"}, + + {"ppp_lan_pair_cnt_l"}, + {"ppp_lan_pair_cnt_h"}, + {"ppp_um_tbl_mc_hit_pkt_cnt_l"}, + {"ppp_um_tbl_mc_hit_pkt_cnt_h"}, + {"ppp_mta_tbl_hit_pkt_cnt_l"}, + {"ppp_mta_tbl_hit_pkt_cnt_h"}, + + {"ppp_promisc_tbl_hit_pkt_cnt_l"}, + {"ppp_promisc_tbl_hit_pkt_cnt_h"}, + {"ppp_rsv13"}, + {"ppp_rsv14"}, + {"ppp_rsv15"}, + {"ppp_rsv16"}, +}; + +static struct hns3_dfx_reg_entry dfx_rcb_reg_list[] = { + {"rcb_rsv0"}, + {"rcb_fsm_dfx_st0"}, + {"rcb_fsm_dfx_st1"}, + {"rcb_fsm_dfx_st2"}, + {"rcb_fifo_dfx_st0"}, + {"rcb_fifo_dfx_st1"}, + + {"rcb_fifo_dfx_st2"}, + {"rcb_fifo_dfx_st3"}, + {"rcb_fifo_dfx_st4"}, + {"rcb_fifo_dfx_st5"}, + {"rcb_fifo_dfx_st6"}, + {"rcb_fifo_dfx_st7"}, + + {"rcb_fifo_dfx_st8"}, + {"rcb_fifo_dfx_st9"}, + {"rcb_fifo_dfx_st10"}, + {"rcb_fifo_dfx_st11"}, + {"rcb_q_credit_vld_0"}, + {"rcb_q_credit_vld_1"}, + + {"rcb_q_credit_vld_2"}, + {"rcb_q_credit_vld_3"}, + {"rcb_q_credit_vld_4"}, + {"rcb_q_credit_vld_5"}, + {"rcb_q_credit_vld_6"}, + {"rcb_q_credit_vld_7"}, + + {"rcb_q_credit_vld_8"}, + {"rcb_q_credit_vld_9"}, + {"rcb_q_credit_vld_10"}, + {"rcb_q_credit_vld_11"}, + {"rcb_q_credit_vld_12"}, + {"rcb_q_credit_vld_13"}, + + {"rcb_q_credit_vld_14"}, + {"rcb_q_credit_vld_15"}, + {"rcb_q_credit_vld_16"}, + {"rcb_q_credit_vld_17"}, + {"rcb_q_credit_vld_18"}, + {"rcb_q_credit_vld_19"}, + + {"rcb_q_credit_vld_20"}, + {"rcb_q_credit_vld_21"}, + {"rcb_q_credit_vld_22"}, + {"rcb_q_credit_vld_23"}, + {"rcb_q_credit_vld_24"}, + {"rcb_q_credit_vld_25"}, + + {"rcb_q_credit_vld_26"}, + {"rcb_q_credit_vld_27"}, + {"rcb_q_credit_vld_28"}, + {"rcb_q_credit_vld_29"}, + {"rcb_q_credit_vld_30"}, + {"rcb_q_credit_vld_31"}, + + {"rcb_gro_bd_serr_cnt"}, + {"rcb_gro_context_serr_cnt"}, + {"rcb_rx_stash_cfg_serr_cnt"}, + {"rcb_axi_rd_fbd_serr_cnt", "rcb_rcb_tx_mem_serr_cnt"}, + {"rcb_gro_bd_merr_cnt"}, + {"rcb_gro_context_merr_cnt"}, + + {"rcb_rx_stash_cfg_merr_cnt"}, + {"rcb_axi_rd_fbd_merr_cnt"}, + {"rcb_rsv1"}, + {"rcb_rsv2"}, + {"rcb_rsv3"}, + {"rcb_rsv4"}, +}; + +static struct hns3_dfx_reg_entry dfx_tqp_reg_list[] = { + {"dfx_tqp_q_num"}, + {"rcb_cfg_rx_ring_tail"}, + {"rcb_cfg_rx_ring_head"}, + {"rcb_cfg_rx_ring_fbdnum"}, + {"rcb_cfg_rx_ring_offset"}, + {"rcb_cfg_rx_ring_fbdoffset"}, + + {"rcb_cfg_rx_ring_pktnum_record"}, + {"rcb_cfg_tx_ring_tail"}, + {"rcb_cfg_tx_ring_head"}, + {"rcb_cfg_tx_ring_fbdnum"}, + {"rcb_cfg_tx_ring_offset"}, + {"rcb_cfg_tx_ring_ebdnum"}, +}; + +static struct hns3_dfx_reg_entry dfx_ssu_reg_2_list[] = { + {"dfx_ssu2_oq_index"}, + {"dfx_ssu2_queue_cnt"}, + {"dfx_ssu2_rsv0"}, + {"dfx_ssu2_rsv1"}, + {"dfx_ssu2_rsv2"}, + {"dfx_ssu2_rsv3"}, +}; + +enum hns3_reg_modules { + HNS3_BIOS_COMMON = 0, + HNS3_SSU_0, + HNS3_SSU_1, + HNS3_IGU_EGU, + HNS3_RPU_0, + HNS3_RPU_1, + HNS3_NCSI, + HNS3_RTC, + HNS3_PPP, + HNS3_RCB, + HNS3_TQP, + HNS3_SSU_2, + + HNS3_CMDQ = 12, + HNS3_COMMON_PF, + HNS3_COMMON_VF, + HNS3_RING, + HNS3_TQP_INTR, + + HNS3_32_BIT_DFX, + HNS3_64_BIT_DFX, +}; + +struct hns3_reg_list { + const void *reg_list; + uint32_t entry_num; +}; + +static struct hns3_reg_list hns3_reg_lists[] = { + [HNS3_BIOS_COMMON] = { dfx_bios_common_reg_list, RTE_DIM(dfx_bios_common_reg_list)}, + [HNS3_SSU_0] = { dfx_ssu_reg_0_list, RTE_DIM(dfx_ssu_reg_0_list)}, + [HNS3_SSU_1] = { dfx_ssu_reg_1_list, RTE_DIM(dfx_ssu_reg_1_list)}, + [HNS3_IGU_EGU] = { dfx_igu_egu_reg_list, RTE_DIM(dfx_igu_egu_reg_list)}, + [HNS3_RPU_0] = { dfx_rpu_reg_0_list, RTE_DIM(dfx_rpu_reg_0_list)}, + [HNS3_RPU_1] = { dfx_rpu_reg_1_list, RTE_DIM(dfx_rpu_reg_1_list)}, + [HNS3_NCSI] = { dfx_ncsi_reg_list, RTE_DIM(dfx_ncsi_reg_list)}, + [HNS3_RTC] = { dfx_rtc_reg_list, RTE_DIM(dfx_rtc_reg_list)}, + [HNS3_PPP] = { dfx_ppp_reg_list, RTE_DIM(dfx_ppp_reg_list)}, + [HNS3_RCB] = { dfx_rcb_reg_list, RTE_DIM(dfx_rcb_reg_list)}, + [HNS3_TQP] = { dfx_tqp_reg_list, RTE_DIM(dfx_tqp_reg_list)}, + [HNS3_SSU_2] = { dfx_ssu_reg_2_list, RTE_DIM(dfx_ssu_reg_2_list)}, + + [HNS3_CMDQ] = { cmdq_reg_list, RTE_DIM(cmdq_reg_list)}, + [HNS3_COMMON_PF] = { common_reg_list, RTE_DIM(common_reg_list)}, + [HNS3_COMMON_VF] = { common_vf_reg_list, RTE_DIM(common_vf_reg_list)}, + [HNS3_RING] = { ring_reg_list, RTE_DIM(ring_reg_list)}, + [HNS3_TQP_INTR] = { tqp_intr_reg_list, RTE_DIM(tqp_intr_reg_list)}, + + [HNS3_32_BIT_DFX] = { regs_32_bit_list, RTE_DIM(regs_32_bit_list)}, + [HNS3_64_BIT_DFX] = { regs_64_bit_list, RTE_DIM(regs_64_bit_list)}, +}; static const uint32_t hns3_dfx_reg_opcode_list[] = { - HNS3_OPC_DFX_BIOS_COMMON_REG, - HNS3_OPC_DFX_SSU_REG_0, - HNS3_OPC_DFX_SSU_REG_1, - HNS3_OPC_DFX_IGU_EGU_REG, - HNS3_OPC_DFX_RPU_REG_0, - HNS3_OPC_DFX_RPU_REG_1, - HNS3_OPC_DFX_NCSI_REG, - HNS3_OPC_DFX_RTC_REG, - HNS3_OPC_DFX_PPP_REG, - HNS3_OPC_DFX_RCB_REG, - HNS3_OPC_DFX_TQP_REG, - HNS3_OPC_DFX_SSU_REG_2 + [HNS3_BIOS_COMMON] = HNS3_OPC_DFX_BIOS_COMMON_REG, + [HNS3_SSU_0] = HNS3_OPC_DFX_SSU_REG_0, + [HNS3_SSU_1] = HNS3_OPC_DFX_SSU_REG_1, + [HNS3_IGU_EGU] = HNS3_OPC_DFX_IGU_EGU_REG, + [HNS3_RPU_0] = HNS3_OPC_DFX_RPU_REG_0, + [HNS3_RPU_1] = HNS3_OPC_DFX_RPU_REG_1, + [HNS3_NCSI] = HNS3_OPC_DFX_NCSI_REG, + [HNS3_RTC] = HNS3_OPC_DFX_RTC_REG, + [HNS3_PPP] = HNS3_OPC_DFX_PPP_REG, + [HNS3_RCB] = HNS3_OPC_DFX_RCB_REG, + [HNS3_TQP] = HNS3_OPC_DFX_TQP_REG, + [HNS3_SSU_2] = HNS3_OPC_DFX_SSU_REG_2 }; static int @@ -100,6 +856,11 @@ hns3_get_regs_num(struct hns3_hw *hw, uint32_t *regs_num_32_bit, *regs_num_32_bit = rte_le_to_cpu_32(desc.data[0]); *regs_num_64_bit = rte_le_to_cpu_32(desc.data[1]); + if (*regs_num_32_bit != RTE_DIM(regs_32_bit_list) || + *regs_num_64_bit * HNS3_64_BIT_REG_OUTPUT_SIZE != RTE_DIM(regs_64_bit_list)) { + hns3_err(hw, "Query register number differ from the list!"); + return -EINVAL; + } return 0; } @@ -161,6 +922,7 @@ hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count) { int opcode_num = RTE_DIM(hns3_dfx_reg_opcode_list); uint32_t bd_num_list[opcode_num]; + uint32_t reg_num; int ret; int i; @@ -168,8 +930,14 @@ hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count) if (ret) return ret; - for (i = 0; i < opcode_num; i++) - *count += bd_num_list[i] * HNS3_CMD_DESC_DATA_NUM; + for (i = 0; i < opcode_num; i++) { + reg_num = bd_num_list[i] * HNS3_CMD_DESC_DATA_NUM; + if (reg_num != hns3_reg_lists[i].entry_num) { + hns3_err(hw, "Query register number differ from the list for module!"); + return -EINVAL; + } + *count += reg_num; + } return 0; } @@ -196,14 +964,13 @@ hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length) int ret; if (hns->is_vf) - common_cnt = sizeof(common_vf_reg_addrs); + common_cnt = RTE_DIM(common_vf_reg_list); else - common_cnt = sizeof(common_reg_addrs); + common_cnt = RTE_DIM(common_reg_list); - len = sizeof(cmdq_reg_addrs) + common_cnt + - sizeof(ring_reg_addrs) * hw->tqps_num + - sizeof(tqp_intr_reg_addrs) * hw->intr_tqps_num; - len /= sizeof(uint32_t); + len = RTE_DIM(cmdq_reg_list) + common_cnt + + RTE_DIM(ring_reg_list) * hw->tqps_num + + RTE_DIM(tqp_intr_reg_list) * hw->intr_tqps_num; if (!hns->is_vf) { ret = hns3_get_firmware_reg_cnt(hw, &dfx_reg_cnt); @@ -219,13 +986,31 @@ hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length) return 0; } +static void +hns3_fill_dfx_regs_name(struct hns3_hw *hw, struct rte_dev_reg_info *regs, + const struct hns3_dfx_reg_entry *reg_list, uint32_t reg_num) +{ + uint32_t i, cnt = regs->length; + const char *name; + + if (regs->names == NULL) + return; + + for (i = 0; i < reg_num; i++) { + name = reg_list[i].name_v1; + if (hw->revision == PCI_REVISION_ID_HIP09_A && reg_list[i].name_v2 != NULL) + name = reg_list[i].name_v2; + snprintf(regs->names[cnt++].name, RTE_ETH_REG_NAME_SIZE, "%s", name); + } +} + static int -hns3_get_32_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data) +hns3_get_32_bit_regs(struct hns3_hw *hw, uint32_t regs_num, struct rte_dev_reg_info *regs) { #define HNS3_32_BIT_REG_RTN_DATANUM 8 #define HNS3_32_BIT_DESC_NODATA_LEN 2 + uint32_t *reg_val = regs->data; struct hns3_cmd_desc *desc; - uint32_t *reg_val = data; uint32_t *desc_data; int cmd_num; int i, k, n; @@ -254,6 +1039,9 @@ hns3_get_32_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data) return ret; } + hns3_fill_dfx_regs_name(hw, regs, regs_32_bit_list, regs_num); + reg_val += regs->length; + regs->length += regs_num; for (i = 0; i < cmd_num; i++) { if (i == 0) { desc_data = &desc[i].data[0]; @@ -265,7 +1053,6 @@ hns3_get_32_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data) } for (k = 0; k < n; k++) { *reg_val++ = rte_le_to_cpu_32(*desc_data++); - regs_num--; if (regs_num == 0) break; @@ -277,12 +1064,12 @@ hns3_get_32_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data) } static int -hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data) +hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, struct rte_dev_reg_info *regs) { #define HNS3_64_BIT_REG_RTN_DATANUM 4 #define HNS3_64_BIT_DESC_NODATA_LEN 1 + uint32_t *reg_val = regs->data; struct hns3_cmd_desc *desc; - uint64_t *reg_val = data; uint64_t *desc_data; int cmd_num; int i, k, n; @@ -311,6 +1098,9 @@ hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data) return ret; } + hns3_fill_dfx_regs_name(hw, regs, regs_64_bit_list, regs_num * HNS3_64_BIT_REG_OUTPUT_SIZE); + reg_val += regs->length; + regs->length += regs_num * HNS3_64_BIT_REG_OUTPUT_SIZE; for (i = 0; i < cmd_num; i++) { if (i == 0) { desc_data = (uint64_t *)(&desc[i].data[0]); @@ -322,7 +1112,6 @@ hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data) } for (k = 0; k < n; k++) { *reg_val++ = rte_le_to_cpu_64(*desc_data++); - regs_num--; if (!regs_num) break; @@ -333,47 +1122,80 @@ hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data) return 0; } -static int -hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data) +static void +hns3_direct_access_regs_help(struct hns3_hw *hw, struct rte_dev_reg_info *regs, + enum hns3_reg_modules idx) { - struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); - uint32_t *origin_data_ptr = data; - uint32_t reg_offset; - size_t reg_num; - uint16_t j; - size_t i; + const struct hns3_dirt_reg_entry *reg_list; + uint32_t *data = regs->data; + size_t reg_num, i, cnt; + + data += regs->length; + reg_num = hns3_reg_lists[idx].entry_num; + reg_list = hns3_reg_lists[idx].reg_list; + cnt = regs->length; + for (i = 0; i < reg_num; i++) { + *data++ = hns3_read_dev(hw, reg_list[i].addr); + if (regs->names != NULL) + snprintf(regs->names[cnt++].name, RTE_ETH_REG_NAME_SIZE, + "%s", reg_list[i].name); + } - /* fetching per-PF registers values from PF PCIe register space */ - reg_num = sizeof(cmdq_reg_addrs) / sizeof(uint32_t); - for (i = 0; i < reg_num; i++) - *data++ = hns3_read_dev(hw, cmdq_reg_addrs[i]); + regs->length += reg_num; +} + +static uint32_t +hns3_get_module_tqp_reg_offset(enum hns3_reg_modules idx, uint16_t queue_id) +{ + if (idx == HNS3_RING) + return hns3_get_tqp_reg_offset(queue_id); + else if (idx == HNS3_TQP_INTR) + return hns3_get_tqp_intr_reg_offset(queue_id); + + return 0; +} + +static void +hns3_direct_access_tqp_regs_help(struct hns3_hw *hw, struct rte_dev_reg_info *regs, + enum hns3_reg_modules idx) +{ + const struct hns3_dirt_reg_entry *reg_list; + uint16_t tqp_num, reg_offset; + uint32_t *data = regs->data; + uint32_t reg_num, i, j; + + if (idx != HNS3_RING && idx != HNS3_TQP_INTR) + return; + + tqp_num = (idx == HNS3_RING) ? hw->tqps_num : hw->intr_tqps_num; + reg_list = hns3_reg_lists[idx].reg_list; + reg_num = hns3_reg_lists[idx].entry_num; + data += regs->length; + for (i = 0; i < tqp_num; i++) { + reg_offset = hns3_get_module_tqp_reg_offset(idx, i); + for (j = 0; j < reg_num; j++) { + *data++ = hns3_read_dev(hw, reg_list[j].addr + reg_offset); + if (regs->names != NULL) + snprintf(regs->names[regs->length].name, + RTE_ETH_REG_NAME_SIZE, "Q%u_%s", i, reg_list[j].name); + regs->length++; + } + } +} + +static void +hns3_direct_access_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs) +{ + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); if (hns->is_vf) - reg_num = sizeof(common_vf_reg_addrs) / sizeof(uint32_t); + hns3_direct_access_regs_help(hw, regs, HNS3_COMMON_VF); else - reg_num = sizeof(common_reg_addrs) / sizeof(uint32_t); - for (i = 0; i < reg_num; i++) - if (hns->is_vf) - *data++ = hns3_read_dev(hw, common_vf_reg_addrs[i]); - else - *data++ = hns3_read_dev(hw, common_reg_addrs[i]); - - reg_num = sizeof(ring_reg_addrs) / sizeof(uint32_t); - for (j = 0; j < hw->tqps_num; j++) { - reg_offset = hns3_get_tqp_reg_offset(j); - for (i = 0; i < reg_num; i++) - *data++ = hns3_read_dev(hw, - ring_reg_addrs[i] + reg_offset); - } + hns3_direct_access_regs_help(hw, regs, HNS3_COMMON_PF); - reg_num = sizeof(tqp_intr_reg_addrs) / sizeof(uint32_t); - for (j = 0; j < hw->intr_tqps_num; j++) { - reg_offset = hns3_get_tqp_intr_reg_offset(j); - for (i = 0; i < reg_num; i++) - *data++ = hns3_read_dev(hw, tqp_intr_reg_addrs[i] + - reg_offset); - } - return data - origin_data_ptr; + hns3_direct_access_regs_help(hw, regs, HNS3_CMDQ); + hns3_direct_access_tqp_regs_help(hw, regs, HNS3_RING); + hns3_direct_access_tqp_regs_help(hw, regs, HNS3_TQP_INTR); } static int @@ -417,13 +1239,13 @@ hns3_dfx_reg_fetch_data(struct hns3_cmd_desc *desc, int bd_num, uint32_t *reg) } static int -hns3_get_dfx_regs(struct hns3_hw *hw, void **data) +hns3_get_dfx_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs) { int opcode_num = RTE_DIM(hns3_dfx_reg_opcode_list); - uint32_t max_bd_num, bd_num, opcode; + uint32_t max_bd_num, bd_num, opcode, regs_num; uint32_t bd_num_list[opcode_num]; struct hns3_cmd_desc *cmd_descs; - uint32_t *reg_val = (uint32_t *)*data; + uint32_t *data = regs->data; int ret; int i; @@ -447,42 +1269,47 @@ hns3_get_dfx_regs(struct hns3_hw *hw, void **data) ret = hns3_dfx_reg_cmd_send(hw, cmd_descs, bd_num, opcode); if (ret) break; - reg_val += hns3_dfx_reg_fetch_data(cmd_descs, bd_num, reg_val); + + data += regs->length; + regs_num = hns3_dfx_reg_fetch_data(cmd_descs, bd_num, data); + hns3_fill_dfx_regs_name(hw, regs, hns3_reg_lists[i].reg_list, regs_num); + regs->length += regs_num; } rte_free(cmd_descs); - *data = (void *)reg_val; return ret; } static int -hns3_get_regs_from_firmware(struct hns3_hw *hw, uint32_t *data) +hns3_get_regs_from_firmware(struct hns3_hw *hw, struct rte_dev_reg_info *regs) { + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); uint32_t regs_num_32_bit; uint32_t regs_num_64_bit; int ret; + if (hns->is_vf) + return 0; + ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit); if (ret) { hns3_err(hw, "Get register number failed, ret = %d", ret); return ret; } - ret = hns3_get_32_bit_regs(hw, regs_num_32_bit, data); + ret = hns3_get_32_bit_regs(hw, regs_num_32_bit, regs); if (ret) { hns3_err(hw, "Get 32 bit register failed, ret = %d", ret); return ret; } - data += regs_num_32_bit; - ret = hns3_get_64_bit_regs(hw, regs_num_64_bit, data); + ret = hns3_get_64_bit_regs(hw, regs_num_64_bit, regs); if (ret) { hns3_err(hw, "Get 64 bit register failed, ret = %d", ret); return ret; } - data += regs_num_64_bit * HNS3_64_BIT_REG_OUTPUT_SIZE; - return hns3_get_dfx_regs(hw, (void **)&data); + return hns3_get_dfx_regs(hw, regs); } int @@ -491,15 +1318,13 @@ hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs) struct hns3_adapter *hns = eth_dev->data->dev_private; struct hns3_hw *hw = &hns->hw; uint32_t length; - uint32_t *data; int ret; ret = hns3_get_regs_length(hw, &length); if (ret) return ret; - data = regs->data; - if (data == NULL) { + if (regs->data == NULL) { regs->length = length; regs->width = sizeof(uint32_t); return 0; @@ -510,13 +1335,12 @@ hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs) return -ENOTSUP; regs->version = hw->fw_version; + /* to count the number of filled registers */ + regs->length = 0; /* fetching per-PF registers values from PF PCIe register space */ - data += hns3_direct_access_regs(hw, data); - - if (hns->is_vf) - return 0; + hns3_direct_access_regs(hw, regs); /* fetching PF common registers values from firmware */ - return hns3_get_regs_from_firmware(hw, data); + return hns3_get_regs_from_firmware(hw, regs); } From patchwork Mon Jul 22 06:58:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Hai X-Patchwork-Id: 142572 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7282E4567C; Mon, 22 Jul 2024 09:06:13 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4822342F65; Mon, 22 Jul 2024 09:05:30 +0200 (CEST) Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) by mails.dpdk.org (Postfix) with ESMTP id DE1DC427D6 for ; Mon, 22 Jul 2024 08:58:59 +0200 (CEST) Received: from mail.maildlp.com (unknown [172.19.163.44]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4WS9y15cDNz20krj; Mon, 22 Jul 2024 14:54:49 +0800 (CST) Received: from kwepemf500004.china.huawei.com (unknown [7.202.181.242]) by mail.maildlp.com (Postfix) with ESMTPS id 2E5A2140136; Mon, 22 Jul 2024 14:58:58 +0800 (CST) Received: from localhost.huawei.com (10.90.30.45) by kwepemf500004.china.huawei.com (7.202.181.242) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Mon, 22 Jul 2024 14:58:57 +0800 From: Jie Hai To: , Yisen Zhuang CC: , , , Subject: [PATCH v6 8/8] net/hns3: support filter registers by module names Date: Mon, 22 Jul 2024 14:58:26 +0800 Message-ID: <20240722065826.3039119-9-haijie1@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20240722065826.3039119-1-haijie1@huawei.com> References: <20231214015650.3738578-1-haijie1@huawei.com> <20240722065826.3039119-1-haijie1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.90.30.45] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To kwepemf500004.china.huawei.com (7.202.181.242) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch support dumping registers which name contains the `filter` string. The module names are in lower case and so is the `filter`. Available module names are cmdq, common_pf, common_vf, ring, tqp_intr, 32_bit_dfx, 64_bit_dfx, bios, igu_egu, ssu, ppp, rpu, ncsi, rtc, rcb, etc. Signed-off-by: Jie Hai --- drivers/net/hns3/hns3_regs.c | 309 ++++++++++++++++++++--------------- 1 file changed, 180 insertions(+), 129 deletions(-) diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c index 622d2e1c3d02..265d9b433653 100644 --- a/drivers/net/hns3/hns3_regs.c +++ b/drivers/net/hns3/hns3_regs.c @@ -12,8 +12,6 @@ #define HNS3_64_BIT_REG_OUTPUT_SIZE (sizeof(uint64_t) / sizeof(uint32_t)) -static int hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count); - struct hns3_dirt_reg_entry { const char *name; uint32_t addr; @@ -795,33 +793,77 @@ enum hns3_reg_modules { HNS3_64_BIT_DFX, }; +#define HNS3_MODULE_MASK(x) RTE_BIT32(x) +#define HNS3_VF_MODULES (HNS3_MODULE_MASK(HNS3_CMDQ) | HNS3_MODULE_MASK(HNS3_COMMON_VF) | \ + HNS3_MODULE_MASK(HNS3_RING) | HNS3_MODULE_MASK(HNS3_TQP_INTR)) +#define HNS3_VF_ONLY_MODULES HNS3_MODULE_MASK(HNS3_COMMON_VF) + struct hns3_reg_list { const void *reg_list; uint32_t entry_num; + const char *module; }; static struct hns3_reg_list hns3_reg_lists[] = { - [HNS3_BIOS_COMMON] = { dfx_bios_common_reg_list, RTE_DIM(dfx_bios_common_reg_list)}, - [HNS3_SSU_0] = { dfx_ssu_reg_0_list, RTE_DIM(dfx_ssu_reg_0_list)}, - [HNS3_SSU_1] = { dfx_ssu_reg_1_list, RTE_DIM(dfx_ssu_reg_1_list)}, - [HNS3_IGU_EGU] = { dfx_igu_egu_reg_list, RTE_DIM(dfx_igu_egu_reg_list)}, - [HNS3_RPU_0] = { dfx_rpu_reg_0_list, RTE_DIM(dfx_rpu_reg_0_list)}, - [HNS3_RPU_1] = { dfx_rpu_reg_1_list, RTE_DIM(dfx_rpu_reg_1_list)}, - [HNS3_NCSI] = { dfx_ncsi_reg_list, RTE_DIM(dfx_ncsi_reg_list)}, - [HNS3_RTC] = { dfx_rtc_reg_list, RTE_DIM(dfx_rtc_reg_list)}, - [HNS3_PPP] = { dfx_ppp_reg_list, RTE_DIM(dfx_ppp_reg_list)}, - [HNS3_RCB] = { dfx_rcb_reg_list, RTE_DIM(dfx_rcb_reg_list)}, - [HNS3_TQP] = { dfx_tqp_reg_list, RTE_DIM(dfx_tqp_reg_list)}, - [HNS3_SSU_2] = { dfx_ssu_reg_2_list, RTE_DIM(dfx_ssu_reg_2_list)}, - - [HNS3_CMDQ] = { cmdq_reg_list, RTE_DIM(cmdq_reg_list)}, - [HNS3_COMMON_PF] = { common_reg_list, RTE_DIM(common_reg_list)}, - [HNS3_COMMON_VF] = { common_vf_reg_list, RTE_DIM(common_vf_reg_list)}, - [HNS3_RING] = { ring_reg_list, RTE_DIM(ring_reg_list)}, - [HNS3_TQP_INTR] = { tqp_intr_reg_list, RTE_DIM(tqp_intr_reg_list)}, - - [HNS3_32_BIT_DFX] = { regs_32_bit_list, RTE_DIM(regs_32_bit_list)}, - [HNS3_64_BIT_DFX] = { regs_64_bit_list, RTE_DIM(regs_64_bit_list)}, + [HNS3_BIOS_COMMON] = { + dfx_bios_common_reg_list, RTE_DIM(dfx_bios_common_reg_list), "bios" + }, + [HNS3_SSU_0] = { + dfx_ssu_reg_0_list, RTE_DIM(dfx_ssu_reg_0_list), "ssu" + }, + [HNS3_SSU_1] = { + dfx_ssu_reg_1_list, RTE_DIM(dfx_ssu_reg_1_list), "ssu" + }, + [HNS3_IGU_EGU] = { + dfx_igu_egu_reg_list, RTE_DIM(dfx_igu_egu_reg_list), "igu_egu" + }, + [HNS3_RPU_0] = { + dfx_rpu_reg_0_list, RTE_DIM(dfx_rpu_reg_0_list), "rpu" + }, + [HNS3_RPU_1] = { + dfx_rpu_reg_1_list, RTE_DIM(dfx_rpu_reg_1_list), "rpu" + }, + [HNS3_NCSI] = { + dfx_ncsi_reg_list, RTE_DIM(dfx_ncsi_reg_list), "ncsi" + }, + [HNS3_RTC] = { + dfx_rtc_reg_list, RTE_DIM(dfx_rtc_reg_list), "rtc" + }, + [HNS3_PPP] = { + dfx_ppp_reg_list, RTE_DIM(dfx_ppp_reg_list), "ppp" + }, + [HNS3_RCB] = { + dfx_rcb_reg_list, RTE_DIM(dfx_rcb_reg_list), "rcb" + }, + [HNS3_TQP] = { + dfx_tqp_reg_list, RTE_DIM(dfx_tqp_reg_list), "tqp" + }, + [HNS3_SSU_2] = { + dfx_ssu_reg_2_list, RTE_DIM(dfx_ssu_reg_2_list), "ssu" + }, + + [HNS3_CMDQ] = { + cmdq_reg_list, RTE_DIM(cmdq_reg_list), "cmdq" + }, + [HNS3_COMMON_PF] = { + common_reg_list, RTE_DIM(common_reg_list), "common_pf" + }, + [HNS3_COMMON_VF] = { + common_vf_reg_list, RTE_DIM(common_vf_reg_list), "common_vf" + }, + [HNS3_RING] = { + ring_reg_list, RTE_DIM(ring_reg_list), "ring" + }, + [HNS3_TQP_INTR] = { + tqp_intr_reg_list, RTE_DIM(tqp_intr_reg_list), "tqp_intr" + }, + + [HNS3_32_BIT_DFX] = { + regs_32_bit_list, RTE_DIM(regs_32_bit_list), "32_bit_dfx" + }, + [HNS3_64_BIT_DFX] = { + regs_64_bit_list, RTE_DIM(regs_64_bit_list), "64_bit_dfx" + }, }; static const uint32_t hns3_dfx_reg_opcode_list[] = { @@ -865,21 +907,52 @@ hns3_get_regs_num(struct hns3_hw *hw, uint32_t *regs_num_32_bit, return 0; } -static int -hns3_get_32_64_regs_cnt(struct hns3_hw *hw, uint32_t *count) +static bool +hns3_check_module_match(const char *module, const char *filter) { - uint32_t regs_num_32_bit, regs_num_64_bit; - int ret; + if (filter != NULL && strcmp(filter, module) != 0) + return false; - ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit); - if (ret) { - hns3_err(hw, "fail to get the number of registers, " - "ret = %d.", ret); - return ret; + return true; +} + +#define HNS3_MAX_MODULES_LEN 512 +static uint32_t +hns3_check_module_names(const char *filter, char *names) +{ + uint32_t ret = 0, pos = 0; + size_t i; + + for (i = 0; i < RTE_DIM(hns3_reg_lists); i++) { + if (hns3_check_module_match(hns3_reg_lists[i].module, filter)) + ret |= HNS3_MODULE_MASK(i); + if (HNS3_MAX_MODULES_LEN - pos <= strlen(hns3_reg_lists[i].module)) + return -ENOMEM; + snprintf(&names[pos], HNS3_MAX_MODULES_LEN - pos, " %s", hns3_reg_lists[i].module); + pos += strlen(hns3_reg_lists[i].module) + 1; } + return ret; +} - *count += regs_num_32_bit + regs_num_64_bit * HNS3_64_BIT_REG_OUTPUT_SIZE; - return 0; +static uint32_t +hns3_check_filter(struct hns3_hw *hw, const char *filter) +{ + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); + char names[HNS3_MAX_MODULES_LEN + 1] = {0}; + uint32_t modules = 0; + + if (filter == NULL) + return (1 << RTE_DIM(hns3_reg_lists)) - 1; + + modules = hns3_check_module_names(filter, names); + if (hns->is_vf) + modules &= HNS3_VF_MODULES; + else + modules &= ~HNS3_VF_ONLY_MODULES; + if (modules == 0) + hns3_err(hw, "mismatched module name! Available names are:\n%s.", names); + + return modules; } static int @@ -917,73 +990,25 @@ hns3_get_dfx_reg_bd_num(struct hns3_hw *hw, uint32_t *bd_num_list, return 0; } -static int -hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count) -{ - int opcode_num = RTE_DIM(hns3_dfx_reg_opcode_list); - uint32_t bd_num_list[opcode_num]; - uint32_t reg_num; - int ret; - int i; - - ret = hns3_get_dfx_reg_bd_num(hw, bd_num_list, opcode_num); - if (ret) - return ret; - - for (i = 0; i < opcode_num; i++) { - reg_num = bd_num_list[i] * HNS3_CMD_DESC_DATA_NUM; - if (reg_num != hns3_reg_lists[i].entry_num) { - hns3_err(hw, "Query register number differ from the list for module!"); - return -EINVAL; - } - *count += reg_num; - } - - return 0; -} - -static int -hns3_get_firmware_reg_cnt(struct hns3_hw *hw, uint32_t *count) -{ - int ret; - - ret = hns3_get_32_64_regs_cnt(hw, count); - if (ret < 0) - return ret; - - return hns3_get_dfx_reg_cnt(hw, count); -} - -static int -hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length) +static uint32_t +hns3_get_regs_length(struct hns3_hw *hw, uint32_t modules) { - struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); - uint32_t dfx_reg_cnt = 0; - uint32_t common_cnt; - uint32_t len; - int ret; - - if (hns->is_vf) - common_cnt = RTE_DIM(common_vf_reg_list); - else - common_cnt = RTE_DIM(common_reg_list); + uint32_t reg_num = 0, length = 0; + uint32_t i; - len = RTE_DIM(cmdq_reg_list) + common_cnt + - RTE_DIM(ring_reg_list) * hw->tqps_num + - RTE_DIM(tqp_intr_reg_list) * hw->intr_tqps_num; + for (i = 0; i < RTE_DIM(hns3_reg_lists); i++) { + if ((BIT(i) & modules) == 0) + continue; + reg_num = hns3_reg_lists[i].entry_num; + if (i == HNS3_RING) + reg_num *= hw->tqps_num; + else if (i == HNS3_TQP_INTR) + reg_num *= hw->intr_tqps_num; - if (!hns->is_vf) { - ret = hns3_get_firmware_reg_cnt(hw, &dfx_reg_cnt); - if (ret) { - hns3_err(hw, "fail to get the number of dfx registers, " - "ret = %d.", ret); - return ret; - } - len += dfx_reg_cnt; + length += reg_num; } - *length = len; - return 0; + return length; } static void @@ -1124,12 +1149,15 @@ hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, struct rte_dev_reg_i static void hns3_direct_access_regs_help(struct hns3_hw *hw, struct rte_dev_reg_info *regs, - enum hns3_reg_modules idx) + uint32_t modules, enum hns3_reg_modules idx) { const struct hns3_dirt_reg_entry *reg_list; uint32_t *data = regs->data; size_t reg_num, i, cnt; + if ((modules & HNS3_MODULE_MASK(idx)) == 0) + return; + data += regs->length; reg_num = hns3_reg_lists[idx].entry_num; reg_list = hns3_reg_lists[idx].reg_list; @@ -1157,14 +1185,14 @@ hns3_get_module_tqp_reg_offset(enum hns3_reg_modules idx, uint16_t queue_id) static void hns3_direct_access_tqp_regs_help(struct hns3_hw *hw, struct rte_dev_reg_info *regs, - enum hns3_reg_modules idx) + uint32_t modules, enum hns3_reg_modules idx) { const struct hns3_dirt_reg_entry *reg_list; uint16_t tqp_num, reg_offset; uint32_t *data = regs->data; uint32_t reg_num, i, j; - if (idx != HNS3_RING && idx != HNS3_TQP_INTR) + if ((modules & HNS3_MODULE_MASK(idx)) == 0) return; tqp_num = (idx == HNS3_RING) ? hw->tqps_num : hw->intr_tqps_num; @@ -1184,18 +1212,13 @@ hns3_direct_access_tqp_regs_help(struct hns3_hw *hw, struct rte_dev_reg_info *re } static void -hns3_direct_access_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs) +hns3_direct_access_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs, uint32_t modules) { - struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); - - if (hns->is_vf) - hns3_direct_access_regs_help(hw, regs, HNS3_COMMON_VF); - else - hns3_direct_access_regs_help(hw, regs, HNS3_COMMON_PF); - - hns3_direct_access_regs_help(hw, regs, HNS3_CMDQ); - hns3_direct_access_tqp_regs_help(hw, regs, HNS3_RING); - hns3_direct_access_tqp_regs_help(hw, regs, HNS3_TQP_INTR); + hns3_direct_access_regs_help(hw, regs, modules, HNS3_COMMON_VF); + hns3_direct_access_regs_help(hw, regs, modules, HNS3_COMMON_PF); + hns3_direct_access_regs_help(hw, regs, modules, HNS3_CMDQ); + hns3_direct_access_tqp_regs_help(hw, regs, modules, HNS3_RING); + hns3_direct_access_tqp_regs_help(hw, regs, modules, HNS3_TQP_INTR); } static int @@ -1239,7 +1262,7 @@ hns3_dfx_reg_fetch_data(struct hns3_cmd_desc *desc, int bd_num, uint32_t *reg) } static int -hns3_get_dfx_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs) +hns3_get_dfx_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs, uint32_t modules) { int opcode_num = RTE_DIM(hns3_dfx_reg_opcode_list); uint32_t max_bd_num, bd_num, opcode, regs_num; @@ -1264,6 +1287,8 @@ hns3_get_dfx_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs) for (i = 0; i < opcode_num; i++) { opcode = hns3_dfx_reg_opcode_list[i]; bd_num = bd_num_list[i]; + if ((modules & HNS3_MODULE_MASK(i)) == 0) + continue; if (bd_num == 0) continue; ret = hns3_dfx_reg_cmd_send(hw, cmd_descs, bd_num, opcode); @@ -1272,6 +1297,11 @@ hns3_get_dfx_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs) data += regs->length; regs_num = hns3_dfx_reg_fetch_data(cmd_descs, bd_num, data); + if (regs_num != hns3_reg_lists[i].entry_num) { + hns3_err(hw, "Query register number differ from the list for module %s!", + hns3_reg_lists[i].module); + return -EINVAL; + } hns3_fill_dfx_regs_name(hw, regs, hns3_reg_lists[i].reg_list, regs_num); regs->length += regs_num; } @@ -1281,14 +1311,14 @@ hns3_get_dfx_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs) } static int -hns3_get_regs_from_firmware(struct hns3_hw *hw, struct rte_dev_reg_info *regs) +hns3_get_32_b4_bit_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs, uint32_t modules) { - struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); uint32_t regs_num_32_bit; uint32_t regs_num_64_bit; int ret; - if (hns->is_vf) + if ((modules & HNS3_MODULE_MASK(HNS3_32_BIT_DFX)) == 0 && + (modules & HNS3_MODULE_MASK(HNS3_32_BIT_DFX)) == 0) return 0; ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit); @@ -1297,19 +1327,39 @@ hns3_get_regs_from_firmware(struct hns3_hw *hw, struct rte_dev_reg_info *regs) return ret; } - ret = hns3_get_32_bit_regs(hw, regs_num_32_bit, regs); - if (ret) { - hns3_err(hw, "Get 32 bit register failed, ret = %d", ret); - return ret; + if ((modules & HNS3_MODULE_MASK(HNS3_32_BIT_DFX)) != 0) { + ret = hns3_get_32_bit_regs(hw, regs_num_32_bit, regs); + if (ret) { + hns3_err(hw, "Get 32 bit register failed, ret = %d", ret); + return ret; + } } - ret = hns3_get_64_bit_regs(hw, regs_num_64_bit, regs); - if (ret) { - hns3_err(hw, "Get 64 bit register failed, ret = %d", ret); - return ret; + if ((modules & HNS3_MODULE_MASK(HNS3_32_BIT_DFX)) != 0) { + ret = hns3_get_64_bit_regs(hw, regs_num_64_bit, regs); + if (ret) { + hns3_err(hw, "Get 64 bit register failed, ret = %d", ret); + return ret; + } } - return hns3_get_dfx_regs(hw, regs); + return 0; +} + +static int +hns3_get_regs_from_firmware(struct hns3_hw *hw, struct rte_dev_reg_info *regs, uint32_t modules) +{ + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); + int ret; + + if (hns->is_vf) + return 0; + + ret = hns3_get_32_b4_bit_regs(hw, regs, modules); + if (ret != 0) + return ret; + + return hns3_get_dfx_regs(hw, regs, modules); } int @@ -1317,13 +1367,14 @@ hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs) { struct hns3_adapter *hns = eth_dev->data->dev_private; struct hns3_hw *hw = &hns->hw; + uint32_t modules = 0; uint32_t length; - int ret; - ret = hns3_get_regs_length(hw, &length); - if (ret) - return ret; + modules = hns3_check_filter(hw, regs->filter); + if (modules == 0) + return -EINVAL; + length = hns3_get_regs_length(hw, modules); if (regs->data == NULL) { regs->length = length; regs->width = sizeof(uint32_t); @@ -1339,8 +1390,8 @@ hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs) regs->length = 0; /* fetching per-PF registers values from PF PCIe register space */ - hns3_direct_access_regs(hw, regs); + hns3_direct_access_regs(hw, regs, modules); /* fetching PF common registers values from firmware */ - return hns3_get_regs_from_firmware(hw, regs); + return hns3_get_regs_from_firmware(hw, regs, modules); }