From patchwork Sun May 5 18:31:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arkadiusz Kusztal X-Patchwork-Id: 139873 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 90CA843FB9; Sun, 5 May 2024 20:32:07 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 66501400EF; Sun, 5 May 2024 20:32:05 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mails.dpdk.org (Postfix) with ESMTP id 7148B40041 for ; Sun, 5 May 2024 20:32:03 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714933924; x=1746469924; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=GB6GG23MTwbe2w9QmkWgaLODHtzST2ZWMopboNzznpI=; b=iyPBZCTbscfSelc4r94jpMW8URb/D/xOG44STJuZsLuUFiV6mmgsHp/1 bq2vqC1TlleWZIlJ+xntXhUt5JD1diHbvwr8XGzYJGZJP+wbaIox7l1MK PA225TZbHEgbHcU15b6gf1+UziD1LvEzXybcL9Yt6HNiWlOfgcrpLBnWz G8EChRnxrvwyXWhjQFcImLMDAwsVHF6zYnKDydZ+iD+fJOxc+G5uVj1sH DCrgA5Y1KnD4s/jQcYC7CpSmZLwZN4aO3YuKKYyy16rXH87bTlhT1CeUf 1PnZgTFpFLHKPh39173hOZ12nNk42QdkxZoMzL2Q3zEvFrUv0p1B7K9eF w==; X-CSE-ConnectionGUID: p8rF0/H6TmGz+93SH445mA== X-CSE-MsgGUID: mGYBQ9IvRMeBLn7L0ErSVw== X-IronPort-AV: E=McAfee;i="6600,9927,11064"; a="28150514" X-IronPort-AV: E=Sophos;i="6.07,256,1708416000"; d="scan'208";a="28150514" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2024 11:32:03 -0700 X-CSE-ConnectionGUID: zjwD3ImhSK65dGHq+lJbyQ== X-CSE-MsgGUID: rkebN1UuT6ChUbpLyjpvAQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,256,1708416000"; d="scan'208";a="32428957" Received: from silpixa00400308.ir.intel.com ([10.237.214.154]) by fmviesa005.fm.intel.com with ESMTP; 05 May 2024 11:32:00 -0700 From: Arkadiusz Kusztal To: dev@dpdk.org Cc: gakhil@marvell.com, ciara.power@intel.com, Arkadiusz Kusztal Subject: [PATCH v2] common/qat: add legacy algorithm option Date: Sun, 5 May 2024 19:31:42 +0100 Message-Id: <20240505183142.20148-1-arkadiuszx.kusztal@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240418165128.17261-1-arkadiuszx.kusztal@intel.com> References: <20240418165128.17261-1-arkadiuszx.kusztal@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This commit adds legacy algorithms flag to the qat_device struct. This will allow handling this flag within the device itself, and not using the global variable. Signed-off-by: Arkadiusz Kusztal Acked-by: Ciara Power --- v2: - added session parameters handling drivers/common/qat/qat_common.h | 9 +++++++++ drivers/common/qat/qat_device.c | 7 +++---- drivers/common/qat/qat_device.h | 7 ++----- drivers/common/qat/qat_qp.c | 2 +- drivers/common/qat/qat_qp.h | 3 ++- drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c | 4 ++-- drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 17 +++++++++-------- drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 4 ++-- drivers/crypto/qat/dev/qat_crypto_pmd_gen5.c | 4 ++-- drivers/crypto/qat/dev/qat_sym_pmd_gen1.c | 6 +++--- drivers/crypto/qat/qat_asym.c | 23 ++++++++++++++--------- drivers/crypto/qat/qat_crypto.h | 1 - drivers/crypto/qat/qat_sym.c | 24 ++++++++++++------------ drivers/crypto/qat/qat_sym_session.c | 10 +++++----- 14 files changed, 66 insertions(+), 55 deletions(-) diff --git a/drivers/common/qat/qat_common.h b/drivers/common/qat/qat_common.h index 6d0f4aefd5..97828e2c67 100644 --- a/drivers/common/qat/qat_common.h +++ b/drivers/common/qat/qat_common.h @@ -19,6 +19,15 @@ extern const char *const *qat_cmdline_defines[]; +struct qat_options { + uint32_t slice_map; + /**< Map of the crypto and compression slices */ + uint16_t has_wireless_slice; + /**< Wireless Slices supported */ + uint8_t legacy_alg; + /**< are legacy algorithm supported */ +}; + enum qat_device_gen { QAT_GEN1, QAT_GEN2, diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c index 666e2bb995..c6ac7a0015 100644 --- a/drivers/common/qat/qat_device.c +++ b/drivers/common/qat/qat_device.c @@ -31,7 +31,6 @@ struct qat_service qat_service[QAT_MAX_SERVICES]; /* per-process array of device data */ struct qat_device_info qat_pci_devs[RTE_PMD_QAT_MAX_PCI_DEVICES]; static int qat_nb_pci_devices; -int qat_legacy_capa; /* * The set of PCI devices this driver supports @@ -331,7 +330,7 @@ qat_pci_device_allocate(struct rte_pci_device *pci_dev) qat_pci_devs[qat_dev_id].pci_dev = pci_dev; if (wireless_slice_support(pci_dev->id.device_id)) - qat_dev->has_wireless_slice = 1; + qat_dev->options.has_wireless_slice = 1; ops_hw = qat_dev_hw_spec[qat_dev->qat_dev_gen]; NOT_NULL(ops_hw->qat_dev_get_misc_bar, goto error, @@ -352,7 +351,7 @@ qat_pci_device_allocate(struct rte_pci_device *pci_dev) /* Parse the arguments */ cmdline = qat_dev_cmdline_get_val(qat_dev, QAT_LEGACY_CAPA); if (cmdline) - qat_legacy_capa = atoi(cmdline); + qat_dev->options.legacy_alg = atoi(cmdline); if (qat_read_qp_config(qat_dev)) { QAT_LOG(ERR, @@ -372,7 +371,7 @@ qat_pci_device_allocate(struct rte_pci_device *pci_dev) NOT_NULL(ops_hw->qat_dev_get_slice_map, goto error, "QAT internal error! Read slice function not set, gen : %d", qat_dev_gen); - if (ops_hw->qat_dev_get_slice_map(&qat_dev->slice_map, pci_dev) < 0) { + if (ops_hw->qat_dev_get_slice_map(&qat_dev->options.slice_map, pci_dev) < 0) { RTE_LOG(ERR, EAL, "Cannot read slice configuration\n"); goto error; diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h index 9275156ef8..f5ba1592c3 100644 --- a/drivers/common/qat/qat_device.h +++ b/drivers/common/qat/qat_device.h @@ -42,7 +42,6 @@ typedef int (*qat_dev_get_extra_size_t)(void); typedef int (*qat_dev_get_slice_map_t)(uint32_t *map, const struct rte_pci_device *pci_dev); -extern int qat_legacy_capa; char *qat_dev_cmdline_get_val(struct qat_pci_device *qat_dev, const char *key); struct qat_dev_hw_spec_funcs { @@ -122,14 +121,12 @@ struct qat_pci_device { /**< Address of misc bar */ void *dev_private; /**< Per generation specific information */ - uint32_t slice_map; - /**< Map of the crypto and compression slices */ - uint16_t has_wireless_slice; - /**< Wireless Slices supported */ char *command_line; /**< Map of the crypto and compression slices */ void *pmd[QAT_MAX_SERVICES]; /**< link back to pmd private data */ + struct qat_options options; + /**< qat device options */ }; struct qat_gen_hw_data { diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c index f95dd33375..ad44b0e01f 100644 --- a/drivers/common/qat/qat_qp.c +++ b/drivers/common/qat/qat_qp.c @@ -634,7 +634,7 @@ qat_enqueue_op_burst(void *qp, qat_op_build_request_t op_build_request, while (nb_ops_sent != nb_ops_possible) { ret = op_build_request(*ops, base_addr + tail, tmp_qp->op_cookies[tail >> queue->trailz], - tmp_qp->opaque, tmp_qp->qat_dev_gen); + tmp_qp); if (ret != 0) { tmp_qp->stats.enqueue_err_count++; diff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h index ae18fb942e..9fb1bf62ae 100644 --- a/drivers/common/qat/qat_qp.h +++ b/drivers/common/qat/qat_qp.h @@ -12,6 +12,7 @@ #define QAT_QP_MIN_INFL_THRESHOLD 256 +struct qat_qp; struct qat_pci_device; /** @@ -57,7 +58,7 @@ struct qat_queue { * - EINVAL if error **/ typedef int (*qat_op_build_request_t)(void *in_op, uint8_t *out_msg, - void *op_cookie, uint64_t *opaque, enum qat_device_gen dev_gen); + void *op_cookie, struct qat_qp *qp); /** * Type define qat_op_dequeue_t function pointer, passed in as argument diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c index 62874039a9..f20d367404 100644 --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c @@ -290,7 +290,7 @@ qat_sym_crypto_cap_get_gen2(struct qat_cryptodev_private *internals, uint32_t legacy_size = sizeof(qat_sym_crypto_legacy_caps_gen2); legacy_capa_num = legacy_size/sizeof(struct rte_cryptodev_capabilities); - if (unlikely(qat_legacy_capa)) + if (unlikely(internals->qat_dev->options.legacy_alg)) size = size + legacy_size; internals->capa_mz = rte_memzone_lookup(capa_memz_name); @@ -309,7 +309,7 @@ qat_sym_crypto_cap_get_gen2(struct qat_cryptodev_private *internals, internals->capa_mz->addr; struct rte_cryptodev_capabilities *capabilities; - if (unlikely(qat_legacy_capa)) { + if (unlikely(internals->qat_dev->options.legacy_alg)) { capabilities = qat_sym_crypto_legacy_caps_gen2; memcpy(addr, capabilities, legacy_size); addr += legacy_capa_num; diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c index 907c3ce3e2..af664fb9b9 100644 --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c @@ -206,7 +206,7 @@ qat_sym_crypto_cap_get_gen3(struct qat_cryptodev_private *internals, legacy_capa_num = legacy_size/sizeof(struct rte_cryptodev_capabilities); struct rte_cryptodev_capabilities *cap; - if (unlikely(qat_legacy_capa)) + if (unlikely(internals->qat_dev->options.legacy_alg)) size = size + legacy_size; internals->capa_mz = rte_memzone_lookup(capa_memz_name); @@ -225,7 +225,7 @@ qat_sym_crypto_cap_get_gen3(struct qat_cryptodev_private *internals, internals->capa_mz->addr; struct rte_cryptodev_capabilities *capabilities; - if (unlikely(qat_legacy_capa)) { + if (unlikely(internals->qat_dev->options.legacy_alg)) { capabilities = qat_sym_crypto_legacy_caps_gen3; capa_num += legacy_capa_num; } else { @@ -233,7 +233,8 @@ qat_sym_crypto_cap_get_gen3(struct qat_cryptodev_private *internals, } for (i = 0; i < capa_num; i++, iter++) { - if (unlikely(qat_legacy_capa) && (i == legacy_capa_num)) { + if (unlikely(internals->qat_dev->options.legacy_alg) && + (i == legacy_capa_num)) { capabilities = qat_sym_crypto_caps_gen3; addr += curr_capa; curr_capa = 0; @@ -265,7 +266,7 @@ qat_sym_crypto_cap_get_gen3(struct qat_cryptodev_private *internals, continue; } - if (internals->qat_dev->has_wireless_slice && ( + if (internals->qat_dev->options.has_wireless_slice && ( check_auth_capa(&capabilities[iter], RTE_CRYPTO_AUTH_KASUMI_F9) || check_cipher_capa(&capabilities[iter], @@ -279,7 +280,7 @@ qat_sym_crypto_cap_get_gen3(struct qat_cryptodev_private *internals, memcpy(addr + curr_capa, capabilities + iter, sizeof(struct rte_cryptodev_capabilities)); - if (internals->qat_dev->has_wireless_slice && ( + if (internals->qat_dev->options.has_wireless_slice && ( check_auth_capa(&capabilities[iter], RTE_CRYPTO_AUTH_ZUC_EIA3))) { cap = addr + curr_capa; @@ -290,7 +291,7 @@ qat_sym_crypto_cap_get_gen3(struct qat_cryptodev_private *internals, cap->sym.auth.digest_size.max = 16; cap->sym.auth.digest_size.increment = 4; } - if (internals->qat_dev->has_wireless_slice && ( + if (internals->qat_dev->options.has_wireless_slice && ( check_cipher_capa(&capabilities[iter], RTE_CRYPTO_CIPHER_ZUC_EEA3))) { cap = addr + curr_capa; @@ -551,7 +552,7 @@ qat_sym_crypto_set_session_gen3(void *cdev, void *session) ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3)) { qat_sym_session_set_ext_hash_flags_gen2(ctx, 0); - } else if ((internals->qat_dev->has_wireless_slice) && + } else if ((internals->qat_dev->options.has_wireless_slice) && ((ctx->aes_cmac || ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) && (ctx->qat_cipher_alg == @@ -560,7 +561,7 @@ qat_sym_crypto_set_session_gen3(void *cdev, void *session) ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3 || ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_ZUC_256))) { qat_sym_session_set_ext_hash_flags_gen2(ctx, 0); - } else if ((internals->qat_dev->has_wireless_slice) && + } else if ((internals->qat_dev->options.has_wireless_slice) && (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_32 || ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_64 || ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_128) && diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c index 11f6078759..5e808a60bf 100644 --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c @@ -124,7 +124,7 @@ qat_sym_crypto_cap_get_gen4(struct qat_cryptodev_private *internals, uint32_t legacy_size = sizeof(qat_sym_crypto_legacy_caps_gen4); legacy_capa_num = legacy_size/sizeof(struct rte_cryptodev_capabilities); - if (unlikely(qat_legacy_capa)) + if (unlikely(internals->qat_dev->options.legacy_alg)) size = size + legacy_size; internals->capa_mz = rte_memzone_lookup(capa_memz_name); @@ -144,7 +144,7 @@ qat_sym_crypto_cap_get_gen4(struct qat_cryptodev_private *internals, struct rte_cryptodev_capabilities *capabilities; - if (unlikely(qat_legacy_capa)) { + if (unlikely(internals->qat_dev->options.legacy_alg)) { capabilities = qat_sym_crypto_legacy_caps_gen4; memcpy(addr, capabilities, legacy_size); addr += legacy_capa_num; diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen5.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen5.c index 1902430480..e1302e9b36 100644 --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen5.c +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen5.c @@ -167,7 +167,7 @@ qat_sym_crypto_cap_get_gen5(struct qat_cryptodev_private *internals, legacy_capa_num = legacy_size/sizeof(struct rte_cryptodev_capabilities); capa_num = RTE_DIM(qat_sym_crypto_caps_gen5); - if (unlikely(qat_legacy_capa)) + if (unlikely(internals->qat_dev->options.legacy_alg)) size = size + legacy_size; internals->capa_mz = rte_memzone_lookup(capa_memz_name); @@ -187,7 +187,7 @@ qat_sym_crypto_cap_get_gen5(struct qat_cryptodev_private *internals, struct rte_cryptodev_capabilities *capabilities; - if (unlikely(qat_legacy_capa)) { + if (unlikely(internals->qat_dev->options.legacy_alg)) { capabilities = qat_sym_crypto_legacy_caps_gen5; memcpy(addr, capabilities, legacy_size); addr += legacy_capa_num; diff --git a/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c b/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c index bdd1647ea2..24e51a9318 100644 --- a/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c +++ b/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c @@ -164,7 +164,7 @@ qat_sym_crypto_cap_get_gen1(struct qat_cryptodev_private *internals, uint32_t legacy_size = sizeof(qat_sym_crypto_legacy_caps_gen1); legacy_capa_num = legacy_size/sizeof(struct rte_cryptodev_capabilities); - if (unlikely(qat_legacy_capa)) + if (unlikely(internals->qat_dev->options.legacy_alg)) size = size + legacy_size; internals->capa_mz = rte_memzone_lookup(capa_memz_name); @@ -184,7 +184,7 @@ qat_sym_crypto_cap_get_gen1(struct qat_cryptodev_private *internals, struct rte_cryptodev_capabilities *capabilities; - if (unlikely(qat_legacy_capa)) { + if (unlikely(internals->qat_dev->options.legacy_alg)) { capabilities = qat_sym_crypto_legacy_caps_gen1; memcpy(addr, capabilities, legacy_size); addr += legacy_capa_num; @@ -292,7 +292,7 @@ qat_sym_build_op_auth_gen1(void *in_op, struct qat_sym_session *ctx, cdev = rte_cryptodev_pmd_get_dev(ctx->dev_id); internals = cdev->data->dev_private; - if (internals->qat_dev->has_wireless_slice && !ctx->is_gmac) + if (internals->qat_dev->options.has_wireless_slice && !ctx->is_gmac) ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET( req->comn_hdr.serv_specif_flags, 0); diff --git a/drivers/crypto/qat/qat_asym.c b/drivers/crypto/qat/qat_asym.c index 14d6ec358c..491f5ecd5b 100644 --- a/drivers/crypto/qat/qat_asym.c +++ b/drivers/crypto/qat/qat_asym.c @@ -986,7 +986,8 @@ static int asym_set_input(struct icp_qat_fw_pke_request *qat_req, struct qat_asym_op_cookie *cookie, const struct rte_crypto_asym_op *asym_op, - const struct rte_crypto_asym_xform *xform) + const struct rte_crypto_asym_xform *xform, + uint8_t legacy_alg) { switch (xform->xform_type) { case RTE_CRYPTO_ASYM_XFORM_MODEX: @@ -995,7 +996,7 @@ asym_set_input(struct icp_qat_fw_pke_request *qat_req, return modinv_set_input(qat_req, cookie, asym_op, xform); case RTE_CRYPTO_ASYM_XFORM_RSA:{ if (unlikely((xform->rsa.n.length < RSA_MODULUS_2048_BITS) - && (qat_legacy_capa == 0))) + && (legacy_alg == 0))) return RTE_CRYPTO_OP_STATUS_INVALID_ARGS; return rsa_set_input(qat_req, cookie, asym_op, xform); } @@ -1029,9 +1030,10 @@ asym_set_input(struct icp_qat_fw_pke_request *qat_req, } static int -qat_asym_build_request(void *in_op, uint8_t *out_msg, void *op_cookie, - __rte_unused uint64_t *opaque, - __rte_unused enum qat_device_gen qat_dev_gen) +qat_asym_build_request(void *in_op, + uint8_t *out_msg, + void *op_cookie, + struct qat_qp *qp) { struct rte_crypto_op *op = (struct rte_crypto_op *)in_op; struct rte_crypto_asym_op *asym_op = op->asym; @@ -1065,7 +1067,8 @@ qat_asym_build_request(void *in_op, uint8_t *out_msg, void *op_cookie, op->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION; goto error; } - err = asym_set_input(qat_req, cookie, asym_op, xform); + err = asym_set_input(qat_req, cookie, asym_op, xform, + qp->qat_dev->options.legacy_alg); if (err) { op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS; goto error; @@ -1354,9 +1357,11 @@ qat_asym_session_configure(struct rte_cryptodev *dev __rte_unused, struct rte_crypto_asym_xform *xform, struct rte_cryptodev_asym_session *session) { + struct qat_cryptodev_private *crypto_qat; struct qat_asym_session *qat_session; int ret = 0; + crypto_qat = dev->data->dev_private; qat_session = (struct qat_asym_session *) session->sess_private_data; memset(qat_session, 0, sizeof(*qat_session)); @@ -1370,7 +1375,7 @@ qat_asym_session_configure(struct rte_cryptodev *dev __rte_unused, break; case RTE_CRYPTO_ASYM_XFORM_RSA: { if (unlikely((xform->rsa.n.length < RSA_MODULUS_2048_BITS) - && (qat_legacy_capa == 0))) { + && (crypto_qat->qat_dev->options.legacy_alg == 0))) { ret = -ENOTSUP; return ret; } @@ -1594,7 +1599,7 @@ qat_asym_dev_create(struct qat_pci_device *qat_pci_dev) atoi(cmdline); } - if (qat_pci_dev->slice_map & ICP_ACCEL_MASK_PKE_SLICE) { + if (qat_pci_dev->options.slice_map & ICP_ACCEL_MASK_PKE_SLICE) { QAT_LOG(ERR, "Device %s does not support PKE slice", name); rte_cryptodev_pmd_destroy(cryptodev); @@ -1604,7 +1609,7 @@ qat_asym_dev_create(struct qat_pci_device *qat_pci_dev) } if (gen_dev_ops->get_capabilities(internals, - capa_memz_name, qat_pci_dev->slice_map) < 0) { + capa_memz_name, qat_pci_dev->options.slice_map) < 0) { QAT_LOG(ERR, "Device cannot obtain capabilities, destroying PMD for %s", name); diff --git a/drivers/crypto/qat/qat_crypto.h b/drivers/crypto/qat/qat_crypto.h index 2e702927b0..fcd62eda27 100644 --- a/drivers/crypto/qat/qat_crypto.h +++ b/drivers/crypto/qat/qat_crypto.h @@ -11,7 +11,6 @@ extern uint8_t qat_sym_driver_id; extern uint8_t qat_asym_driver_id; -extern int qat_legacy_capa; /** * helper macro to set cryptodev capability range diff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c index c530496786..b41d1b1def 100644 --- a/drivers/crypto/qat/qat_sym.c +++ b/drivers/crypto/qat/qat_sym.c @@ -71,11 +71,11 @@ qat_sym_init_op_cookie(void *op_cookie) static __rte_always_inline int qat_sym_build_request(void *in_op, uint8_t *out_msg, - void *op_cookie, uint64_t *opaque, enum qat_device_gen dev_gen) + void *op_cookie, struct qat_qp *qp) { struct rte_crypto_op *op = (struct rte_crypto_op *)in_op; - uintptr_t sess = (uintptr_t)opaque[0]; - uintptr_t build_request_p = (uintptr_t)opaque[1]; + uintptr_t sess = (uintptr_t)qp->opaque[0]; + uintptr_t build_request_p = (uintptr_t)qp->opaque[1]; qat_sym_build_request_t build_request = (void *)build_request_p; struct qat_sym_session *ctx = NULL; enum rte_proc_type_t proc_type = rte_eal_process_type(); @@ -92,7 +92,7 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg, cdev = rte_cryptodev_pmd_get_dev(ctx->dev_id); internals = cdev->data->dev_private; - if (internals->qat_dev->qat_dev_gen != dev_gen) { + if (internals->qat_dev->qat_dev_gen != qp->qat_dev_gen) { op->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION; return -EINVAL; @@ -100,7 +100,7 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg, if (unlikely(ctx->build_request[proc_type] == NULL)) { int ret = - qat_sym_gen_dev_ops[dev_gen].set_session( + qat_sym_gen_dev_ops[qp->qat_dev_gen].set_session( (void *)cdev, (void *)ctx); if (ret < 0) { op->status = @@ -110,8 +110,8 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg, } build_request = ctx->build_request[proc_type]; - opaque[0] = (uintptr_t)ctx; - opaque[1] = (uintptr_t)build_request; + qp->opaque[0] = (uintptr_t)ctx; + qp->opaque[1] = (uintptr_t)build_request; } } else if (op->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION) { ctx = SECURITY_GET_SESS_PRIV(op->sym->session); @@ -145,7 +145,7 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg, cdev = rte_cryptodev_pmd_get_dev(ctx->dev_id); internals = cdev->data->dev_private; - if (internals->qat_dev->qat_dev_gen != dev_gen) { + if (internals->qat_dev->qat_dev_gen != qp->qat_dev_gen) { op->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION; return -EINVAL; @@ -153,7 +153,7 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg, if (unlikely(ctx->build_request[proc_type] == NULL)) { int ret = - qat_sym_gen_dev_ops[dev_gen].set_session( + qat_sym_gen_dev_ops[qp->qat_dev_gen].set_session( (void *)cdev, (void *)sess); if (ret < 0) { op->status = @@ -164,8 +164,8 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg, sess = (uintptr_t)op->sym->session; build_request = ctx->build_request[proc_type]; - opaque[0] = sess; - opaque[1] = (uintptr_t)build_request; + qp->opaque[0] = sess; + qp->opaque[1] = (uintptr_t)build_request; } } else { /* RTE_CRYPTO_OP_SESSIONLESS */ op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS; @@ -317,7 +317,7 @@ qat_sym_dev_create(struct qat_pci_device *qat_pci_dev) internals->cipher_crc_offload_enable = atoi(cmdline); if (gen_dev_ops->get_capabilities(internals, - capa_memz_name, qat_pci_dev->slice_map) < 0) { + capa_memz_name, qat_pci_dev->options.slice_map) < 0) { QAT_LOG(ERR, "Device cannot obtain capabilities, destroying PMD for %s", name); diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c index 9e2dba5423..eb267db424 100644 --- a/drivers/crypto/qat/qat_sym_session.c +++ b/drivers/crypto/qat/qat_sym_session.c @@ -422,7 +422,7 @@ qat_sym_session_configure_cipher(struct rte_cryptodev *dev, goto error_out; } session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE; - if (internals->qat_dev->has_wireless_slice) + if (internals->qat_dev->options.has_wireless_slice) is_wireless = 1; break; case RTE_CRYPTO_CIPHER_NULL: @@ -543,7 +543,7 @@ qat_sym_session_configure_cipher(struct rte_cryptodev *dev, session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE; if (cipher_xform->key.length == ICP_QAT_HW_ZUC_256_KEY_SZ) session->is_zuc256 = 1; - if (internals->qat_dev->has_wireless_slice) + if (internals->qat_dev->options.has_wireless_slice) is_wireless = 1; break; case RTE_CRYPTO_CIPHER_AES_XTS: @@ -933,7 +933,7 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev, break; case RTE_CRYPTO_AUTH_AES_CMAC: session->aes_cmac = 1; - if (!internals->qat_dev->has_wireless_slice) { + if (!internals->qat_dev->options.has_wireless_slice) { session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC; break; } @@ -968,7 +968,7 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev, break; case RTE_CRYPTO_AUTH_SNOW3G_UIA2: session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2; - if (internals->qat_dev->has_wireless_slice) { + if (internals->qat_dev->options.has_wireless_slice) { is_wireless = 1; session->is_wireless = 1; hash_flag = 1 << ICP_QAT_FW_AUTH_HDR_FLAG_SNOW3G_UIA2_BITPOS; @@ -1012,7 +1012,7 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev, QAT_LOG(ERR, "Invalid key length: %d", key_length); return -ENOTSUP; } - if (internals->qat_dev->has_wireless_slice) { + if (internals->qat_dev->options.has_wireless_slice) { is_wireless = 1; session->is_wireless = 1; hash_flag = 1 << ICP_QAT_FW_AUTH_HDR_FLAG_ZUC_EIA3_BITPOS;