From patchwork Thu May 2 05:57:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Mattias_R=C3=B6nnblom?= X-Patchwork-Id: 139795 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4E6F843F65; Thu, 2 May 2024 08:07:38 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 51095402D4; Thu, 2 May 2024 08:07:33 +0200 (CEST) Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2068.outbound.protection.outlook.com [40.107.20.68]) by mails.dpdk.org (Postfix) with ESMTP id 462994026F for ; Thu, 2 May 2024 08:07:31 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=hkKBbR8X4Oet4ZKs7W+FGC54m4pcHpIHd4IbhFKxz7toR7jqnlzypi97xE/lsrD+z0l35JLhJCaTs+GPyQrmUtJsIqDqb9BG1PxH9ZRBSnz4sh91wlOfkEohJ1gZMQmMmZxJJxag6Tqr6VZGB7MNpWO1glYdaO5revXIzUn45ovXSO+UdN3AWQ9nw+ZwMjQFBdwO66G0hmQZSbgHp/mp97BaXzXZr11fO745p1/wH6XXLaS1seu6aBW7cjXZXbsQkD54u4knwRK18aRepvKc+gdqhLCPHnKqoJZiLv14KPKhukU71Q2GBMptYPPKINMbVH19oNwIPj8yErEWLf+Rqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=uGaYNBWczZiaiy2F567USLR166LHBzCdDI8GvTpYwsg=; b=ePN6cjHDdiiMXKstlrkAwDjaamosm4ZR+IKft67F9Snod0Z7VVH0UemRd7Mq+SC1aJfnXe4+lU7bzVYrkiQoKKtgfnzmiL3p+9ueAed7PPC5Hg4mkkLlVLWfqSiSPjVZGrm/b2jUWe1fuZ+dcxN70GUEFJupbD3Dn23S5mW/IPcShvZ3/ndVb/VzeggXeGIirNnFMw0e/RYEWYOBF6myiT/gMAcqG7Ie0h+ZZEFOA6xSqmB/qIjRw2RnmkJGS2pZ9Dwl2NF7el354iwe61nrczocmRE3YooOX97RoNjULpVmCBRDcszQND//QAG+X1kwXMaYim9loNWO/StuxzuPBw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 192.176.1.74) smtp.rcpttodomain=dpdk.org smtp.mailfrom=ericsson.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=ericsson.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ericsson.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=uGaYNBWczZiaiy2F567USLR166LHBzCdDI8GvTpYwsg=; b=R5dxa1mwFH60c5yccaHqdUBHsfAy45qFbew7gUIoU9KvA374YXvPDXHlHVdCFxf5RAJJQPiw/qAstdB+3ZgvvSlTgGOUY7iopiW1sOsXJGi/PWVZRM/NbTlN6aqSx/l7oJnAgMuy1P0lUQ2+mJmYiBcV6KpyNwvnB2rk1KyaOywOz1Ho7W145RKDKJ8l6QDd0vUXIKpoc1ZsfRMowbGbIvXDu8qBIF5uFHjWPcKhAWROpLZixYyC81e85xSDLGzoQrHMjrv5ViAQZuFHeqgLMGHIX5j18IE5By9zL7oCgrByW/mIOlKPvD5TJeR7FouUr/FtmV41xfgilA658OXbGA== Received: from DUZPR01CA0190.eurprd01.prod.exchangelabs.com (2603:10a6:10:4b6::8) by GVXPR07MB9751.eurprd07.prod.outlook.com (2603:10a6:150:11c::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.29; Thu, 2 May 2024 06:07:29 +0000 Received: from DB1PEPF00039230.eurprd03.prod.outlook.com (2603:10a6:10:4b6:cafe::28) by DUZPR01CA0190.outlook.office365.com (2603:10a6:10:4b6::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.29 via Frontend Transport; Thu, 2 May 2024 06:07:29 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 192.176.1.74) smtp.mailfrom=ericsson.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ericsson.com; Received-SPF: Pass (protection.outlook.com: domain of ericsson.com designates 192.176.1.74 as permitted sender) receiver=protection.outlook.com; client-ip=192.176.1.74; helo=oa.msg.ericsson.com; pr=C Received: from oa.msg.ericsson.com (192.176.1.74) by DB1PEPF00039230.mail.protection.outlook.com (10.167.8.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.18 via Frontend Transport; Thu, 2 May 2024 06:07:29 +0000 Received: from seliicinfr00049.seli.gic.ericsson.se (153.88.142.248) by smtp-central.internal.ericsson.com (100.87.178.61) with Microsoft SMTP Server id 15.2.1544.9; Thu, 2 May 2024 08:07:28 +0200 Received: from breslau.. (seliicwb00002.seli.gic.ericsson.se [10.156.25.100]) by seliicinfr00049.seli.gic.ericsson.se (Postfix) with ESMTP id C9C29380061; Thu, 2 May 2024 08:07:28 +0200 (CEST) From: =?utf-8?q?Mattias_R=C3=B6nnblom?= To: CC: , Heng Wang , "Stephen Hemminger" , Tyler Retzlaff , =?utf-8?q?Morten_Br=C3=B8rup?= , =?utf-8?q?Mattia?= =?utf-8?q?s_R=C3=B6nnblom?= Subject: [RFC v6 1/6] eal: extend bit manipulation functionality Date: Thu, 2 May 2024 07:57:01 +0200 Message-ID: <20240502055706.112443-2-mattias.ronnblom@ericsson.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240502055706.112443-1-mattias.ronnblom@ericsson.com> References: <20240430120810.108928-2-mattias.ronnblom@ericsson.com> <20240502055706.112443-1-mattias.ronnblom@ericsson.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB1PEPF00039230:EE_|GVXPR07MB9751:EE_ X-MS-Office365-Filtering-Correlation-Id: 468adaf1-448e-4f5d-1c78-08dc6a6e25ea X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|36860700004|376005; X-Microsoft-Antispam-Message-Info: =?utf-8?q?PLH1j7kOJjcIhvi+R1WpaJf9G9JCkVQ?= =?utf-8?q?7FImJvToAmrg0zG3qjYNhKjaEIXljT4HWxwNxi7iIAUeuQqoJk4Bs5lTQOexQrHZS?= =?utf-8?q?/PxhT98DGk0ugm6DI9boK0Z8tfYnJN/bk02F/VAWNXiR1ijNtswDHs46Bd8J+P6v6?= =?utf-8?q?Fb57BY/+KE9k7VNiZagttPizmzxcvlvTO03PaBsLmc3268oaWXaDPxp3yNNeNhHYz?= =?utf-8?q?gBiKF/CSIMXgvSPKSI/9C0rZ25QeGfZlzECBc2p3W1BCaUMot0sSY9qmDgn1ukkcS?= =?utf-8?q?y7xjfdnyDhFcBevjxkcI5tzpnwAOtz9WvxI2bH5cSnYnBIGguYTLZ2OK1EAE3xZ86?= =?utf-8?q?RykXq0urkBxXzmkufXzZ2i/izX7obuyYPj3MBA9VdSXMQp83MKJI/INAMz6n8hrzv?= =?utf-8?q?oRhIJNn5fhIvB6OFkx7EpGxp4bfq9IWAqQqWm4kGsXlBk2HQdK/vZwxmpZeyCPqQP?= =?utf-8?q?9gbS9eLOl8FUWiitE96pnEkOswMUzmTZHDaqOCRZQNinFPBT2yAhj1N/KYNyfYwNa?= =?utf-8?q?B3kTiVzan/GTc1Y4mSpnTWr/MLHr7cKaX51MjdjGWQflZ8vgcULVjgsjTM2ewhuaQ?= =?utf-8?q?WBgV+em1m+ZLgIMv420szkM/sZMGJup1x70BZ8dPLHm/2jDfDkpnmIGK67AnHUckT?= =?utf-8?q?sRRlazjw+s/t2KL1DXNGKGo9bnCQcRUeJ/fURwK0twAlC7pt0WLHA9ZP/iQIwmw/r?= =?utf-8?q?7AnOoULgW6zUnvhg56vywulC0dsb0nnw4+XAyFpBIgbgydABYdi1itN8kpBUMyglx?= =?utf-8?q?GvJnDPfBdxNFQSdHgeZC4+D3GpvOeRxtKi0EqcRmlSeESOBxrcr3Le5hmqHWdiFa2?= =?utf-8?q?AROTtXWQRph979czMo0M66YiMYfXGVVxR3o/HpInMP+JVehvu5qs5GZWqKcEnVk2C?= =?utf-8?q?nFO5GYcqfa3hGnwPXbKMWJs+I486io7cszB38D7N+4Jbfz35Acmc+dwLPSSkL+Uow?= =?utf-8?q?PjZ7eJeeNhmmAZr22QfDG1iyxPzlsiujoAZ6ECPtgVcdyj/drNJXP+W1Epp06Qhb5?= =?utf-8?q?uV7OMFNmrlBmvsKvMWrRTQMWd2l8/THtEwKjZ5D0IIKcTnLlfewKOrwzADIBJn+qD?= =?utf-8?q?HMB+6l2EIOYDQ4lURJqaHDWKCt1vMpOwil2T1A034nyLAFDUqz2yQ0Isl3q1E7cQl?= =?utf-8?q?4ZxNzpk9duPGQljKr7Ei/Z0DAv8qrPzA2O4cGAWhIKJ7mQmOl5pGUr1QCsU2//gTC?= =?utf-8?q?WLAUvgjr1YHmhKzGr5GiASHtAkX+izjKw99xMqbXJpXoApLDQSprxJvGC3oFS6xjo?= =?utf-8?q?yHYbHXKJQTtAbjqYp3mFHDJsuWLZLArUBmzPqXdOnP3ryUa8o3+lYB2nq5jWGf7jH?= =?utf-8?q?FSRde1+eq6go?= X-Forefront-Antispam-Report: CIP:192.176.1.74; CTRY:SE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:oa.msg.ericsson.com; PTR:office365.se.ericsson.net; CAT:NONE; SFS:(13230031)(1800799015)(36860700004)(376005); DIR:OUT; SFP:1101; X-OriginatorOrg: ericsson.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2024 06:07:29.4033 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 468adaf1-448e-4f5d-1c78-08dc6a6e25ea X-MS-Exchange-CrossTenant-Id: 92e84ceb-fbfd-47ab-be52-080c6b87953f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=92e84ceb-fbfd-47ab-be52-080c6b87953f; Ip=[192.176.1.74]; Helo=[oa.msg.ericsson.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF00039230.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GVXPR07MB9751 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add functionality to test and modify the value of individual bits in 32-bit or 64-bit words. These functions have no implications on memory ordering, atomicity and does not use volatile and thus does not prevent any compiler optimizations. RFC v6: * Have rte_bit_test() accept const-marked bitsets. RFC v4: * Add rte_bit_flip() which, believe it or not, flips the value of a bit. * Mark macro-generated private functions as experimental. * Use macros to generate *assign*() functions. RFC v3: * Work around lack of C++ support for _Generic (Tyler Retzlaff). * Fix ','-related checkpatch warnings. Signed-off-by: Mattias Rönnblom Acked-by: Morten Brørup Acked-by: Tyler Retzlaff --- lib/eal/include/rte_bitops.h | 259 ++++++++++++++++++++++++++++++++++- 1 file changed, 257 insertions(+), 2 deletions(-) diff --git a/lib/eal/include/rte_bitops.h b/lib/eal/include/rte_bitops.h index 449565eeae..3297133e22 100644 --- a/lib/eal/include/rte_bitops.h +++ b/lib/eal/include/rte_bitops.h @@ -2,6 +2,7 @@ * Copyright(c) 2020 Arm Limited * Copyright(c) 2010-2019 Intel Corporation * Copyright(c) 2023 Microsoft Corporation + * Copyright(c) 2024 Ericsson AB */ #ifndef _RTE_BITOPS_H_ @@ -11,12 +12,14 @@ * @file * Bit Operations * - * This file defines a family of APIs for bit operations - * without enforcing memory ordering. + * This file provides functionality for low-level, single-word + * arithmetic and bit-level operations, such as counting or + * setting individual bits. */ #include +#include #include #ifdef __cplusplus @@ -105,6 +108,196 @@ extern "C" { #define RTE_FIELD_GET64(mask, reg) \ ((typeof(mask))(((reg) & (mask)) >> rte_ctz64(mask))) +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Test bit in word. + * + * Generic selection macro to test the value of a bit in a 32-bit or + * 64-bit word. The type of operation depends on the type of the @c + * addr parameter. + * + * This macro does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + */ +#define rte_bit_test(addr, nr) \ + _Generic((addr), \ + uint32_t *: __rte_bit_test32, \ + const uint32_t *: __rte_bit_test32, \ + uint64_t *: __rte_bit_test64, \ + const uint64_t *: __rte_bit_test64)(addr, nr) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Set bit in word. + * + * Generic selection macro to set a bit in a 32-bit or 64-bit + * word. The type of operation depends on the type of the @c addr + * parameter. + * + * This macro does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + */ +#define rte_bit_set(addr, nr) \ + _Generic((addr), \ + uint32_t *: __rte_bit_set32, \ + uint64_t *: __rte_bit_set64)(addr, nr) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Clear bit in word. + * + * Generic selection macro to clear a bit in a 32-bit or 64-bit + * word. The type of operation depends on the type of the @c addr + * parameter. + * + * This macro does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + */ +#define rte_bit_clear(addr, nr) \ + _Generic((addr), \ + uint32_t *: __rte_bit_clear32, \ + uint64_t *: __rte_bit_clear64)(addr, nr) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Assign a value to a bit in word. + * + * Generic selection macro to assign a value to a bit in a 32-bit or 64-bit + * word. The type of operation depends on the type of the @c addr parameter. + * + * This macro does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param value + * The new value of the bit - true for '1', or false for '0'. + */ +#define rte_bit_assign(addr, nr, value) \ + _Generic((addr), \ + uint32_t *: __rte_bit_assign32, \ + uint64_t *: __rte_bit_assign64)(addr, nr, value) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Flip a bit in word. + * + * Generic selection macro to change the value of a bit to '0' if '1' + * or '1' if '0' in a 32-bit or 64-bit word. The type of operation + * depends on the type of the @c addr parameter. + * + * This macro does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + */ +#define rte_bit_flip(addr, nr) \ + _Generic((addr), \ + uint32_t *: __rte_bit_flip32, \ + uint64_t *: __rte_bit_flip64)(addr, nr) + +#define __RTE_GEN_BIT_TEST(family, fun, qualifier, size) \ + __rte_experimental \ + static inline bool \ + __rte_bit_ ## family ## fun ## size(const qualifier uint ## size ## _t *addr, \ + unsigned int nr) \ + { \ + RTE_ASSERT(nr < size); \ + \ + uint ## size ## _t mask = (uint ## size ## _t)1 << nr; \ + return *addr & mask; \ + } + +#define __RTE_GEN_BIT_SET(family, fun, qualifier, size) \ + __rte_experimental \ + static inline void \ + __rte_bit_ ## family ## fun ## size(qualifier uint ## size ## _t *addr, \ + unsigned int nr) \ + { \ + RTE_ASSERT(nr < size); \ + \ + uint ## size ## _t mask = (uint ## size ## _t)1 << nr; \ + *addr |= mask; \ + } \ + +#define __RTE_GEN_BIT_CLEAR(family, fun, qualifier, size) \ + __rte_experimental \ + static inline void \ + __rte_bit_ ## family ## fun ## size(qualifier uint ## size ## _t *addr, \ + unsigned int nr) \ + { \ + RTE_ASSERT(nr < size); \ + \ + uint ## size ## _t mask = ~((uint ## size ## _t)1 << nr); \ + (*addr) &= mask; \ + } \ + +#define __RTE_GEN_BIT_ASSIGN(family, fun, qualifier, size) \ + __rte_experimental \ + static inline void \ + __rte_bit_ ## family ## fun ## size(qualifier uint ## size ## _t *addr, \ + unsigned int nr, bool value) \ + { \ + if (value) \ + __rte_bit_ ## family ## set ## size(addr, nr); \ + else \ + __rte_bit_ ## family ## clear ## size(addr, nr); \ + } + +#define __RTE_GEN_BIT_FLIP(family, fun, qualifier, size) \ + __rte_experimental \ + static inline void \ + __rte_bit_ ## family ## fun ## size(qualifier uint ## size ## _t *addr, \ + unsigned int nr) \ + { \ + bool value; \ + \ + value = __rte_bit_ ## family ## test ## size(addr, nr); \ + __rte_bit_ ## family ## assign ## size(addr, nr, !value); \ + } + +__RTE_GEN_BIT_TEST(, test,, 32) +__RTE_GEN_BIT_SET(, set,, 32) +__RTE_GEN_BIT_CLEAR(, clear,, 32) +__RTE_GEN_BIT_ASSIGN(, assign,, 32) +__RTE_GEN_BIT_FLIP(, flip,, 32) + +__RTE_GEN_BIT_TEST(, test,, 64) +__RTE_GEN_BIT_SET(, set,, 64) +__RTE_GEN_BIT_CLEAR(, clear,, 64) +__RTE_GEN_BIT_ASSIGN(, assign,, 64) +__RTE_GEN_BIT_FLIP(, flip,, 64) + /*------------------------ 32-bit relaxed operations ------------------------*/ /** @@ -787,6 +980,68 @@ rte_log2_u64(uint64_t v) #ifdef __cplusplus } + +/* + * Since C++ doesn't support generic selection (i.e., _Generic), + * function overloading is used instead. Such functions must be + * defined outside 'extern "C"' to be accepted by the compiler. + */ + +#undef rte_bit_test +#undef rte_bit_set +#undef rte_bit_clear +#undef rte_bit_assign +#undef rte_bit_flip + +#define __RTE_BIT_OVERLOAD_SZ_2(fun, qualifier, size, arg1_type, arg1_name) \ + static inline void \ + rte_bit_ ## fun(qualifier uint ## size ## _t *addr, \ + arg1_type arg1_name) \ + { \ + __rte_bit_ ## fun ## size(addr, arg1_name); \ + } + +#define __RTE_BIT_OVERLOAD_2(fun, qualifier, arg1_type, arg1_name) \ + __RTE_BIT_OVERLOAD_SZ_2(fun, qualifier, 32, arg1_type, arg1_name) \ + __RTE_BIT_OVERLOAD_SZ_2(fun, qualifier, 64, arg1_type, arg1_name) + +#define __RTE_BIT_OVERLOAD_SZ_2R(fun, qualifier, size, ret_type, arg1_type, \ + arg1_name) \ + static inline ret_type \ + rte_bit_ ## fun(qualifier uint ## size ## _t *addr, \ + arg1_type arg1_name) \ + { \ + return __rte_bit_ ## fun ## size(addr, arg1_name); \ + } + +#define __RTE_BIT_OVERLOAD_2R(fun, qualifier, ret_type, arg1_type, arg1_name) \ + __RTE_BIT_OVERLOAD_SZ_2R(fun, qualifier, 32, ret_type, arg1_type, \ + arg1_name) \ + __RTE_BIT_OVERLOAD_SZ_2R(fun, qualifier, 64, ret_type, arg1_type, \ + arg1_name) + +#define __RTE_BIT_OVERLOAD_SZ_3(fun, qualifier, size, arg1_type, arg1_name, \ + arg2_type, arg2_name) \ + static inline void \ + rte_bit_ ## fun(uint ## size ## _t *addr, arg1_type arg1_name, \ + arg2_type arg2_name) \ + { \ + __rte_bit_ ## fun ## size(addr, arg1_name, arg2_name); \ + } + +#define __RTE_BIT_OVERLOAD_3(fun, qualifier, arg1_type, arg1_name, arg2_type, \ + arg2_name) \ + __RTE_BIT_OVERLOAD_SZ_3(fun, qualifier, 32, arg1_type, arg1_name, \ + arg2_type, arg2_name) \ + __RTE_BIT_OVERLOAD_SZ_3(fun, qualifier, 64, arg1_type, arg1_name, \ + arg2_type, arg2_name) + +__RTE_BIT_OVERLOAD_2R(test, const, bool, unsigned int, nr) +__RTE_BIT_OVERLOAD_2(set,, unsigned int, nr) +__RTE_BIT_OVERLOAD_2(clear,, unsigned int, nr) +__RTE_BIT_OVERLOAD_3(assign,, unsigned int, nr, bool, value) +__RTE_BIT_OVERLOAD_2(flip,, unsigned int, nr) + #endif #endif /* _RTE_BITOPS_H_ */ From patchwork Thu May 2 05:57:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Mattias_R=C3=B6nnblom?= X-Patchwork-Id: 139796 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EC49743F65; Thu, 2 May 2024 08:07:46 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8BF61402D9; Thu, 2 May 2024 08:07:34 +0200 (CEST) Received: from EUR03-DBA-obe.outbound.protection.outlook.com (mail-dbaeur03on2064.outbound.protection.outlook.com [40.107.104.64]) by mails.dpdk.org (Postfix) with ESMTP id A69F04026F for ; Thu, 2 May 2024 08:07:31 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Zu2u4qXEZheB+tS0yN+wGYwnYBGP4W2w6YPAxqRTl47clLUkAxzOWAnBPxOmmfbS8mje0QvoOadL7Ar5JsSHQWDGvWpAfcIe2Z/1f+nLaiB0k3WCcULwpEZjz8FR8IPjWE4ZgwqoCdfDN1/cP9aMcklkG1uL7SF7Rv0/o2P2EPEgXXUUwELhgyKwR9AdzirPSAqNnSxFN9b7ycHn6lE0uDvBFLEWlViLVyod+0wnbZH4yDvYkjXmulbohB0vr7VgZ/NWU+IVxe1epPPaKynpF8uuIfuzQR1sO8CDnasEQnFxffLERClg1CFi5DRLKKDm7votyBzjZ0Jb0aCdrxAKIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=d8z68B8fzU8h0PRajH8DnhYus8GmVFVNaHI8wvhWqbw=; b=YvAZ+hEgbuF1d3NHXDL6NGynUV1I599AP7xBu93M3WqaAT9NvRYvsCp6f+dRB/xFDURFctHtA8oGeblMeWp5chjZJVBjUayEpUtiC2V4i6QqzzqRN119/kMN3Y8ytRVc3kUmW/DwUZPy+mQSmLsax69wWHq6Uk1TIlKGBKBmnrCUHeTZ0rNLrFV/Mvq14r4S8iuqVuh64cgBlQJ9/GX0hWJa0ujt5SZ1+se/2xfjiOQ0ZrIY/q3QK5BSR5vZgHzRsZflowqW9sO8EUij/E8xK5/ckGb+1xXCCFmMcJTcq41rEtMRdPqFB30SvBUYyXK9xqkoqJk5rNUNhyKJH0TI7A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 192.176.1.74) smtp.rcpttodomain=dpdk.org smtp.mailfrom=ericsson.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=ericsson.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ericsson.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=d8z68B8fzU8h0PRajH8DnhYus8GmVFVNaHI8wvhWqbw=; b=RHyaA7Otl18h2ScW4s7iwOxlH7Q/oN1hgqzkeD5hbE3VY9UFTT6fMWyD3hqnaeO5A2XTnmbLseNePJJx7tAC/UGR+Ti8VJiw5pxQN5ShgQWwCSrFmQuM7V2d1Q4VWhGOfRu/pwzIMRyvf3FjdLgTpa3/GGwwHbr669ftoEUk3FIc+yCAT+FYw3QXuMNOH9wmKwhDL1i56Sos/LEKm9ya4UDP528JhEUB6AykTyxRQDnmPXfEZzgg1X8wx9yAq6i7BlCEIU82UGILJ1lQLzw4SN/KacIHtpT5LL7J1Gtd3Vv3dgc9hwyA+AEdJiCZmnXwWIvnkBcwSFLyuIPdXCO8Lw== Received: from DUZPR01CA0202.eurprd01.prod.exchangelabs.com (2603:10a6:10:4b6::13) by PR3PR07MB6954.eurprd07.prod.outlook.com (2603:10a6:102:76::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.28; Thu, 2 May 2024 06:07:30 +0000 Received: from DB1PEPF00039230.eurprd03.prod.outlook.com (2603:10a6:10:4b6:cafe::b6) by DUZPR01CA0202.outlook.office365.com (2603:10a6:10:4b6::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.27 via Frontend Transport; Thu, 2 May 2024 06:07:30 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 192.176.1.74) smtp.mailfrom=ericsson.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ericsson.com; Received-SPF: Pass (protection.outlook.com: domain of ericsson.com designates 192.176.1.74 as permitted sender) receiver=protection.outlook.com; client-ip=192.176.1.74; helo=oa.msg.ericsson.com; pr=C Received: from oa.msg.ericsson.com (192.176.1.74) by DB1PEPF00039230.mail.protection.outlook.com (10.167.8.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.18 via Frontend Transport; Thu, 2 May 2024 06:07:30 +0000 Received: from seliicinfr00049.seli.gic.ericsson.se (153.88.142.248) by smtp-central.internal.ericsson.com (100.87.178.61) with Microsoft SMTP Server id 15.2.1544.9; Thu, 2 May 2024 08:07:29 +0200 Received: from breslau.. (seliicwb00002.seli.gic.ericsson.se [10.156.25.100]) by seliicinfr00049.seli.gic.ericsson.se (Postfix) with ESMTP id 5DFD3380061; Thu, 2 May 2024 08:07:29 +0200 (CEST) From: =?utf-8?q?Mattias_R=C3=B6nnblom?= To: CC: , Heng Wang , "Stephen Hemminger" , Tyler Retzlaff , =?utf-8?q?Morten_Br=C3=B8rup?= , =?utf-8?q?Mattia?= =?utf-8?q?s_R=C3=B6nnblom?= Subject: [RFC v6 2/6] eal: add unit tests for bit operations Date: Thu, 2 May 2024 07:57:02 +0200 Message-ID: <20240502055706.112443-3-mattias.ronnblom@ericsson.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240502055706.112443-1-mattias.ronnblom@ericsson.com> References: <20240430120810.108928-2-mattias.ronnblom@ericsson.com> <20240502055706.112443-1-mattias.ronnblom@ericsson.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB1PEPF00039230:EE_|PR3PR07MB6954:EE_ X-MS-Office365-Filtering-Correlation-Id: 8509c36f-ce17-4ea2-b481-08dc6a6e2663 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|36860700004|376005|1800799015; X-Microsoft-Antispam-Message-Info: =?utf-8?q?dD2wO5ZckcxWAMWiSgyPynNr+zTYQOs?= =?utf-8?q?ypA8uBZ2K0oVSCHaT4kqYaeMdMyBVJYn29KrTJluOYEm+RiLcitcAP+oxD5qju2dB?= =?utf-8?q?Ggjpx+Oanz3Thdcepda1TM7jhP3s1NuGNiRNppIDIYe9C+sark+cz9/A9Tgc8ZMBi?= =?utf-8?q?94dLaBDrCF2acpFldZo+p+KxKqxgn3KGKf/EwfEKU6uqysPjv8RoEbOWwecl/8TP7?= =?utf-8?q?Uo289yf2SMN2b2vRclTdJJ+p0wWUkL766Fo2YI0ZsKoklW8FCSTsWxopvzonZIYOU?= =?utf-8?q?yHhrlLf50u1LMbyvhM29HmlkZ38paHc7f9hy/O5p48WjGHypDiJGriaqE0EmhUovR?= =?utf-8?q?4FbZGpIt+hVbvmvVQeY87PR1ygQuN72/Uep2Qo1wkDaLsapl2AbU4DR8C3BYrG1dY?= =?utf-8?q?gj2tdMEwGc94lTf6jBarj6s8vT2kBajK05PtUAN3420E+1hlhJ2uhqTBrdvdLt9zL?= =?utf-8?q?3lBIL+cbfMA7xOv0E5enlT6HbuujGwF32ysUxoS9zyPyqztTXtMOOawoVphIQo2GA?= =?utf-8?q?qxG2hwvcB7BHrR/XdZ7TOrDAZfMN0pnf4OXvbTrTIFK4HYsgk5FvaIBVPqrNaIM/8?= =?utf-8?q?mKWHFIbF5jQNQzG6GmkZsJrPS46JLlN5PMbe7e5sqz6i5EtpsIbfMhBIX7qh+6SZN?= =?utf-8?q?fgl9yMMsQ9nXWqxhZ3iCGqD2bclR63+swcxpskMcKUGNSU8Mm+5uj8mqsU2UxwbXi?= =?utf-8?q?KjjMAoHkuLRxVuu0LXAsG5iBgmQ8yOc/qg4xFkyDJyBXtBExYMGGEXwTVjHxVZMDu?= =?utf-8?q?D42UYrJZANpmCLWmwi+DDN8FihXkJKn99xsd5SgqYP+usSyll2UtT8UdLdWU6u9Th?= =?utf-8?q?edMEp7re2JfeQmQ4I5sHvtHmYKAu8H9UD3yRM9/p+F3iR/FUCWYwZcfVtdm3ykTpo?= =?utf-8?q?/CdaIaNfyQWsTnjq61jjhPG8CuCZXL1kYrR6YY6hmOB71iC5KvPJ5rYnyshj87UBt?= =?utf-8?q?VB9aCfzwD5bSZzSWPpbwh4S3xF84aWR291wQJjsicNC3m8r8nBWbXE9U/TR7nA195?= =?utf-8?q?0CAhYh8++NupldcMjWgrlytps5T/8tq6P/1X/+YEdYDptXsLE8EnKu3FvoAZoR5B7?= =?utf-8?q?TLL1CVEifB72Skvi+mjmrSI21yvCeGrb/EjYkSwWhgi+LpPDFhkFRd28A0M0EKXd3?= =?utf-8?q?eL2PKDsztm/+wKNJrtV422WeLmGgGdIRyz8UUDt8FybEfNp8A5NXIBRBKLvYvzeAB?= =?utf-8?q?Jwv6Jzljxl6XcKSHbX8i7xN+Ccw4upDGRm9SvA6NzZDucBtM68xzY8dMvHNBBRFCr?= =?utf-8?q?pzgl90MjHxVbRWNIIW+GQ13o/FvzMG4jXN7XHJVoQLpInMRaTWcCB2Cs=3D?= X-Forefront-Antispam-Report: CIP:192.176.1.74; CTRY:SE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:oa.msg.ericsson.com; PTR:office365.se.ericsson.net; CAT:NONE; SFS:(13230031)(36860700004)(376005)(1800799015); DIR:OUT; SFP:1101; X-OriginatorOrg: ericsson.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2024 06:07:30.2001 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8509c36f-ce17-4ea2-b481-08dc6a6e2663 X-MS-Exchange-CrossTenant-Id: 92e84ceb-fbfd-47ab-be52-080c6b87953f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=92e84ceb-fbfd-47ab-be52-080c6b87953f; Ip=[192.176.1.74]; Helo=[oa.msg.ericsson.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF00039230.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PR3PR07MB6954 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Extend bitops tests to cover the rte_bit_[test|set|clear|assign|flip]() functions. The tests are converted to use the test suite runner framework. RFC v6: * Test rte_bit_*test() usage through const pointers. RFC v4: * Remove redundant line continuations. Signed-off-by: Mattias Rönnblom Acked-by: Morten Brørup Acked-by: Tyler Retzlaff --- app/test/test_bitops.c | 85 ++++++++++++++++++++++++++++++++++-------- 1 file changed, 70 insertions(+), 15 deletions(-) diff --git a/app/test/test_bitops.c b/app/test/test_bitops.c index 0d4ccfb468..322f58c066 100644 --- a/app/test/test_bitops.c +++ b/app/test/test_bitops.c @@ -1,13 +1,68 @@ /* SPDX-License-Identifier: BSD-3-Clause * Copyright(c) 2019 Arm Limited + * Copyright(c) 2024 Ericsson AB */ +#include + #include #include +#include #include "test.h" -uint32_t val32; -uint64_t val64; +#define GEN_TEST_BIT_ACCESS(test_name, set_fun, clear_fun, assign_fun, \ + flip_fun, test_fun, size) \ + static int \ + test_name(void) \ + { \ + uint ## size ## _t reference = (uint ## size ## _t)rte_rand(); \ + unsigned int bit_nr; \ + uint ## size ## _t word = (uint ## size ## _t)rte_rand(); \ + \ + for (bit_nr = 0; bit_nr < size; bit_nr++) { \ + bool reference_bit = (reference >> bit_nr) & 1; \ + bool assign = rte_rand() & 1; \ + if (assign) \ + assign_fun(&word, bit_nr, reference_bit); \ + else { \ + if (reference_bit) \ + set_fun(&word, bit_nr); \ + else \ + clear_fun(&word, bit_nr); \ + \ + } \ + TEST_ASSERT(test_fun(&word, bit_nr) == reference_bit, \ + "Bit %d had unexpected value", bit_nr); \ + flip_fun(&word, bit_nr); \ + TEST_ASSERT(test_fun(&word, bit_nr) != reference_bit, \ + "Bit %d had unflipped value", bit_nr); \ + flip_fun(&word, bit_nr); \ + \ + const uint ## size ## _t *const_ptr = &word; \ + TEST_ASSERT(test_fun(const_ptr, bit_nr) == \ + reference_bit, \ + "Bit %d had unexpected value", bit_nr); \ + } \ + \ + for (bit_nr = 0; bit_nr < size; bit_nr++) { \ + bool reference_bit = (reference >> bit_nr) & 1; \ + TEST_ASSERT(test_fun(&word, bit_nr) == reference_bit, \ + "Bit %d had unexpected value", bit_nr); \ + } \ + \ + TEST_ASSERT(reference == word, "Word had unexpected value"); \ + \ + return TEST_SUCCESS; \ + } + +GEN_TEST_BIT_ACCESS(test_bit_access32, rte_bit_set, rte_bit_clear, + rte_bit_assign, rte_bit_flip, rte_bit_test, 32) + +GEN_TEST_BIT_ACCESS(test_bit_access64, rte_bit_set, rte_bit_clear, + rte_bit_assign, rte_bit_flip, rte_bit_test, 64) + +static uint32_t val32; +static uint64_t val64; #define MAX_BITS_32 32 #define MAX_BITS_64 64 @@ -117,22 +172,22 @@ test_bit_relaxed_test_set_clear(void) return TEST_SUCCESS; } +static struct unit_test_suite test_suite = { + .suite_name = "Bitops test suite", + .unit_test_cases = { + TEST_CASE(test_bit_access32), + TEST_CASE(test_bit_access64), + TEST_CASE(test_bit_relaxed_set), + TEST_CASE(test_bit_relaxed_clear), + TEST_CASE(test_bit_relaxed_test_set_clear), + TEST_CASES_END() + } +}; + static int test_bitops(void) { - val32 = 0; - val64 = 0; - - if (test_bit_relaxed_set() < 0) - return TEST_FAILED; - - if (test_bit_relaxed_clear() < 0) - return TEST_FAILED; - - if (test_bit_relaxed_test_set_clear() < 0) - return TEST_FAILED; - - return TEST_SUCCESS; + return unit_test_suite_runner(&test_suite); } REGISTER_FAST_TEST(bitops_autotest, true, true, test_bitops); From patchwork Thu May 2 05:57:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Mattias_R=C3=B6nnblom?= X-Patchwork-Id: 139797 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BFF3243F65; Thu, 2 May 2024 08:07:53 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CEC93402E1; Thu, 2 May 2024 08:07:35 +0200 (CEST) Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2046.outbound.protection.outlook.com [40.107.20.46]) by mails.dpdk.org (Postfix) with ESMTP id 41E61402C5 for ; Thu, 2 May 2024 08:07:32 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=WmwSslY2LfGBsbjmSEGE60YpyXYIqnjkXb54s7Qcztqx0K7vOGA/n4S1rsjP56tZXAh2nYPZsnCSt0dedkX74PRlE5B38sBUWTkc7TBtHLp1pbAkJPA9TMIztxrOHfG+W6QH5oby/BW2wc7rRvrgrKw2EYSUHew+T4AIn6C1emQlC25p14HwmAeOggdvmoc0SnKwrUbkZIN0brF2FZNae2oE5gbWNKAYVcrG9ZQee1AgMRfx0287rzMw4Zfhpsg3HrUzccP0AMehXQ19UlK3ntjBpnjbonVAV1dDgN1Si9BICyrjJ16XuTZmnkObZuxA8iK9MMCtOZI5xMJoLu1exQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=zmUfRKzoqHSFuLBu20WiDhlgo8uRunsquRSfzUxzP2M=; b=KWKKMrHP6XtwQ56Jr61NzqtfGtzDOuFKwyKgLcGEeg3jvszl1s2CJCOwT03j16ghy0o25DImu6FTn/OQGd+tg4xDRgxYg96BenoIhKNQzI9hOfOZZSNEFsCPYGFmfRQ8APjEm3cCWBMGEJC3Nqi3k4fEqwy2SjVZAzrsyWZZQTtA8I/crisl4VYrl/LrQjeelk7qg1tv7o6dWyCWYnEOSKKlRGKKxRyp3DaeN2mfzY0GXkQCFCSykExXOBOdxvkt/qj6l2/GGgCdJwwk9jPF2PYdwUaocN0PN88ElHqcXNP91afEg8CzkpmOcb2+8WhRFYn3poxr77OGRbU5AfhOog== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 192.176.1.74) smtp.rcpttodomain=dpdk.org smtp.mailfrom=ericsson.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=ericsson.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ericsson.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zmUfRKzoqHSFuLBu20WiDhlgo8uRunsquRSfzUxzP2M=; b=SQdbOeOZZKxYYBV4yJRbpK4/c5dTMbSt1ocERu+PQgR2kfc0RqoHcy3XT6w79OC3rJHoNUT312LGf3YnvnkiF+il/T3DbxocVWtiS9Ndeolj99km2w1utzJpbZer84zyqLvcMjdLddnjIcFgxJnqT+5XFcUFzTdykRMF8z8ZgoRddiDODiUAnO9zRCju8PpZWb23JvyjWuuUO5gz1IDQ8f4KOztsFuLLZCW+rjw9eUJ30ETZx5zL8IrZDI8d1Efa3/Tryx+BDiMd8D5d6Xxz0BmZps+185oA1/bBIMut/Qn1JytFYb/ziXeV6kiaCR8HDzXEOSVkpbQRjdFO7BULgQ== Received: from DUZPR01CA0073.eurprd01.prod.exchangelabs.com (2603:10a6:10:3c2::11) by AS5PR07MB9820.eurprd07.prod.outlook.com (2603:10a6:20b:651::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.26; Thu, 2 May 2024 06:07:31 +0000 Received: from DB5PEPF00014B9E.eurprd02.prod.outlook.com (2603:10a6:10:3c2:cafe::82) by DUZPR01CA0073.outlook.office365.com (2603:10a6:10:3c2::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.29 via Frontend Transport; Thu, 2 May 2024 06:07:30 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 192.176.1.74) smtp.mailfrom=ericsson.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ericsson.com; Received-SPF: Pass (protection.outlook.com: domain of ericsson.com designates 192.176.1.74 as permitted sender) receiver=protection.outlook.com; client-ip=192.176.1.74; helo=oa.msg.ericsson.com; pr=C Received: from oa.msg.ericsson.com (192.176.1.74) by DB5PEPF00014B9E.mail.protection.outlook.com (10.167.8.171) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.18 via Frontend Transport; Thu, 2 May 2024 06:07:30 +0000 Received: from seliicinfr00049.seli.gic.ericsson.se (153.88.142.248) by smtp-central.internal.ericsson.com (100.87.178.64) with Microsoft SMTP Server id 15.2.1544.9; Thu, 2 May 2024 08:07:30 +0200 Received: from breslau.. (seliicwb00002.seli.gic.ericsson.se [10.156.25.100]) by seliicinfr00049.seli.gic.ericsson.se (Postfix) with ESMTP id E20C5380061; Thu, 2 May 2024 08:07:29 +0200 (CEST) From: =?utf-8?q?Mattias_R=C3=B6nnblom?= To: CC: , Heng Wang , "Stephen Hemminger" , Tyler Retzlaff , =?utf-8?q?Morten_Br=C3=B8rup?= , =?utf-8?q?Mattia?= =?utf-8?q?s_R=C3=B6nnblom?= Subject: [RFC v6 3/6] eal: add exactly-once bit access functions Date: Thu, 2 May 2024 07:57:03 +0200 Message-ID: <20240502055706.112443-4-mattias.ronnblom@ericsson.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240502055706.112443-1-mattias.ronnblom@ericsson.com> References: <20240430120810.108928-2-mattias.ronnblom@ericsson.com> <20240502055706.112443-1-mattias.ronnblom@ericsson.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB5PEPF00014B9E:EE_|AS5PR07MB9820:EE_ X-MS-Office365-Filtering-Correlation-Id: 6a0b8216-8e2b-4f67-0ea7-08dc6a6e2698 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|376005|36860700004|1800799015; X-Microsoft-Antispam-Message-Info: =?utf-8?q?i5aRxRCKuh0wYBXB5Y4UQRDNPy+CP/U?= =?utf-8?q?lmJWdHNj8atKoKqobtZAI26rUEPt/JltWWCe9OKTGW+ECiDKnPYB9PsjD7pSTkWYh?= =?utf-8?q?tU3WT0fU2aaHv9Dsn72tcLO1jws2Ho7BmLjEQlRxaQ6BH+wbbApSk8JNdjDQKqyos?= =?utf-8?q?oiEEhhVadFnTnsuyetWPyQXcOs3PrluGajXss9wBFZ4I5t7jpx7SElq/zEXprlTkZ?= =?utf-8?q?w4+SBJ5rZgJwWQEfQX7RMAGK8EWogrYHT5ygAaGbsi+jFV14SRuZ6R7Kqum3oXaqb?= =?utf-8?q?69WIMlemcln7IzPFO3xiZs9c8NcNuXhn+ejFoVr0xOs9bAKyCe9j6g03vKno60l0Z?= =?utf-8?q?SKgeovcGMAMtx/rkLMqa4SvkwBFfW4IlnRMEzU0Lp2G3KJaUismt+7H3nOFe4UT+x?= =?utf-8?q?mMfTHx72BZoHCWT3JbTqwkCycfcuK+CSxqgd0LQ54IDtrtRi5MlBl5zM0QLCuvcBY?= =?utf-8?q?hO7xCIrdViDlJNqV6HJp7skAoyZ1/ZFwvXSxR/9hMCLC8Hfrc7OWU4TM+SR0aPrnz?= =?utf-8?q?KlFlCoTaP4PM5mmc8rw8u9eCo/zQ4aoVyor2220kQa8Z03RRQSFM5ahK4uaM+C/Kp?= =?utf-8?q?I6o65zLfX8228I0/4WxLOj7s+VTlD0yIziLmDNYynCECjmf8d57mdKarp3WTBmmbf?= =?utf-8?q?Rk/Cs/Bh4/EaRrDTjDRDizJqjaarVOkdJPQsKunTn9U725/r0fNVjDxj3zc6q2frG?= =?utf-8?q?xzW2zwK4+4c9v5KKu77sY9eVR7HMWXj/j+F0Uzx+XI2rDZKDd2OZKp4Uknm8GHTJQ?= =?utf-8?q?io2zUG/lXFSa/li4cIU0dkKw/xm45mdYSNJQ8q7LrpcsE9NRVr5sWPo3uSC+jsJ1P?= =?utf-8?q?hmG2VrDDCyAR+JIaIVqDyU8aKhAhvpuRP6E+ZlwCEIoLBpcsoRuv46TerzHfhe5AV?= =?utf-8?q?X98UbDw/GvGoDKwSPrzMNdJ/q1SXZ7/bxGVQV9YS9eXYTp86f8gZ+vlaTFRci5Cu5?= =?utf-8?q?O9i1Y3BiFGgi687WgH1gV44W7m5P98S3Z/H4XGYnCVnFCRXNQL5Ss9pahq9eHaRue?= =?utf-8?q?2xj1972McS0ltwVob+u2fapLS7mUoVq7UQrA2nlLBN3I/cmOWqdkKpSUAnk77+in3?= =?utf-8?q?+D4rmNMID9lTPCnNsx77c2MKcjYzZ5l9lq7QjaB+H+wA7Fh4mGaF8PjNwE2bH7ARX?= =?utf-8?q?6aqMqjpSu+nrXGjOnWo0/OXTlWR040S6Ed5CCU01aJruFMkozCCyGRBngqwlr6Amo?= =?utf-8?q?sSCXofFHU4ttGMXJfo75QkHJ5Ja5mmSG0oDhgRAjGACOG9FbluJvdB75tA35iqvSf?= =?utf-8?q?2LSrMhhSGUcVUHAVYfyERzMwqALJuJ9DNEPOzKKqUyfh3DoOvs1C03EI5caTHZwdT?= =?utf-8?q?JqS54mNcA6Cr?= X-Forefront-Antispam-Report: CIP:192.176.1.74; CTRY:SE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:oa.msg.ericsson.com; PTR:office365.se.ericsson.net; CAT:NONE; SFS:(13230031)(376005)(36860700004)(1800799015); DIR:OUT; SFP:1101; X-OriginatorOrg: ericsson.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2024 06:07:30.5432 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6a0b8216-8e2b-4f67-0ea7-08dc6a6e2698 X-MS-Exchange-CrossTenant-Id: 92e84ceb-fbfd-47ab-be52-080c6b87953f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=92e84ceb-fbfd-47ab-be52-080c6b87953f; Ip=[192.176.1.74]; Helo=[oa.msg.ericsson.com] X-MS-Exchange-CrossTenant-AuthSource: DB5PEPF00014B9E.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS5PR07MB9820 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add test/set/clear/assign/flip functions which prevents certain compiler optimizations and guarantees that program-level memory loads and/or stores will actually occur. These functions are useful when interacting with memory-mapped hardware devices. The "once" family of functions does not promise atomicity and provides no memory ordering guarantees beyond the C11 relaxed memory model. RFC v6: * Have rte_bit_once_test() accept const-marked bitsets. RFC v3: * Work around lack of C++ support for _Generic (Tyler Retzlaff). Signed-off-by: Mattias Rönnblom Acked-by: Morten Brørup Acked-by: Tyler Retzlaff --- lib/eal/include/rte_bitops.h | 197 +++++++++++++++++++++++++++++++++++ 1 file changed, 197 insertions(+) diff --git a/lib/eal/include/rte_bitops.h b/lib/eal/include/rte_bitops.h index 3297133e22..caec4f36bb 100644 --- a/lib/eal/include/rte_bitops.h +++ b/lib/eal/include/rte_bitops.h @@ -226,6 +226,179 @@ extern "C" { uint32_t *: __rte_bit_flip32, \ uint64_t *: __rte_bit_flip64)(addr, nr) +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Generic selection macro to test exactly once the value of a bit in + * a 32-bit or 64-bit word. The type of operation depends on the type + * of the @c addr parameter. + * + * This function is guaranteed to result in exactly one memory load + * (e.g., it may not be eliminate or merged by the compiler). + * + * \code{.c} + * rte_bit_once_set(addr, 17); + * if (rte_bit_once_test(addr, 17)) { + * ... + * } + * \endcode + * + * In the above example, rte_bit_once_set() may not be removed by + * the compiler, which would be allowed in case rte_bit_set() and + * rte_bit_test() was used. + * + * \code{.c} + * while (rte_bit_once_test(addr, 17); + * ; + * \endcode + * + * In case rte_bit_test(addr, 17) was used instead, the resulting + * object code could (and in many cases would be) replaced with + * the equivalent to + * \code{.c} + * if (rte_bit_test(addr, 17)) { + * for (;;) // spin forever + * ; + * } + * \endcode + * + * rte_bit_once_test() does not give any guarantees in regards to + * memory ordering or atomicity. + * + * The regular bit set operations (e.g., rte_bit_test()) should be + * preferred over the "once" family of operations (e.g., + * rte_bit_once_test()) if possible, since the latter may prevent + * optimizations crucial for run-time performance. + * + * @param addr + * A pointer to the word to query. + * @param nr + * The index of the bit. + * @return + * Returns true if the bit is set, and false otherwise. + */ + +#define rte_bit_once_test(addr, nr) \ + _Generic((addr), \ + uint32_t *: __rte_bit_once_test32, \ + const uint32_t *: __rte_bit_once_test32, \ + uint64_t *: __rte_bit_once_test64, \ + const uint64_t *: __rte_bit_once_test64)(addr, nr) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Set bit in word exactly once. + * + * Set bit specified by @c nr in the word pointed to by @c addr to '1' + * exactly once. + * + * This function is guaranteed to result in exactly one memory load + * and exactly one memory store, *or* an atomic bit set operation. + * + * See rte_bit_test_once32() for more information and uses cases for + * the "once" class of functions. + * + * This macro does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + */ + +#define rte_bit_once_set(addr, nr) \ + _Generic((addr), \ + uint32_t *: __rte_bit_once_set32, \ + uint64_t *: __rte_bit_once_set64)(addr, nr) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Clear bit in word exactly once. + * + * Set bit specified by @c nr in the word pointed to by @c addr to '0' + * exactly once. + * + * This function is guaranteed to result in exactly one memory load + * and exactly one memory store, *or* an atomic bit clear operation. + * + * See rte_bit_test_once32() for more information and uses cases for + * the "once" class of functions. + * + * This macro does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + */ +#define rte_bit_once_clear(addr, nr) \ + _Generic((addr), \ + uint32_t *: __rte_bit_once_clear32, \ + uint64_t *: __rte_bit_once_clear64)(addr, nr) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Assign a value to bit in a word exactly once. + * + * Set bit specified by @c nr in the word pointed to by @c addr to the + * value indicated by @c value exactly once. + * + * This function is guaranteed to result in exactly one memory load + * and exactly one memory store, *or* an atomic bit clear operation. + * + * This function does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param value + * The new value of the bit - true for '1', or false for '0'. + */ +#define rte_bit_once_assign(addr, nr, value) \ + _Generic((addr), \ + uint32_t *: __rte_bit_once_assign32, \ + uint64_t *: __rte_bit_once_assign64)(addr, nr, value) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Flip bit in word, reading and writing exactly once. + * + * Change the value of a bit to '0' if '1' or '1' if '0' in a 32-bit + * or 64-bit word. The type of operation depends on the type of the @c + * addr parameter. + * + * This function is guaranteed to result in exactly one memory load + * and exactly one memory store, *or* an atomic bit flip operation. + * + * See rte_bit_test_once32() for more information and uses cases for + * the "once" class of functions. + * + * This macro does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + */ +#define rte_bit_once_flip(addr, nr) \ + _Generic((addr), \ + uint32_t *: __rte_bit_once_flip32, \ + uint64_t *: __rte_bit_once_flip64)(addr, nr) + #define __RTE_GEN_BIT_TEST(family, fun, qualifier, size) \ __rte_experimental \ static inline bool \ @@ -298,6 +471,18 @@ __RTE_GEN_BIT_CLEAR(, clear,, 64) __RTE_GEN_BIT_ASSIGN(, assign,, 64) __RTE_GEN_BIT_FLIP(, flip,, 64) +__RTE_GEN_BIT_TEST(once_, test, volatile, 32) +__RTE_GEN_BIT_SET(once_, set, volatile, 32) +__RTE_GEN_BIT_CLEAR(once_, clear, volatile, 32) +__RTE_GEN_BIT_ASSIGN(once_, assign, volatile, 32) +__RTE_GEN_BIT_FLIP(once_, flip, volatile, 32) + +__RTE_GEN_BIT_TEST(once_, test, volatile, 64) +__RTE_GEN_BIT_SET(once_, set, volatile, 64) +__RTE_GEN_BIT_CLEAR(once_, clear, volatile, 64) +__RTE_GEN_BIT_ASSIGN(once_, assign, volatile, 64) +__RTE_GEN_BIT_FLIP(once_, flip, volatile, 64) + /*------------------------ 32-bit relaxed operations ------------------------*/ /** @@ -993,6 +1178,12 @@ rte_log2_u64(uint64_t v) #undef rte_bit_assign #undef rte_bit_flip +#undef rte_bit_once_test +#undef rte_bit_once_set +#undef rte_bit_once_clear +#undef rte_bit_once_assign +#undef rte_bit_once_flip + #define __RTE_BIT_OVERLOAD_SZ_2(fun, qualifier, size, arg1_type, arg1_name) \ static inline void \ rte_bit_ ## fun(qualifier uint ## size ## _t *addr, \ @@ -1042,6 +1233,12 @@ __RTE_BIT_OVERLOAD_2(clear,, unsigned int, nr) __RTE_BIT_OVERLOAD_3(assign,, unsigned int, nr, bool, value) __RTE_BIT_OVERLOAD_2(flip,, unsigned int, nr) +__RTE_BIT_OVERLOAD_2R(once_test, const volatile, bool, unsigned int, nr) +__RTE_BIT_OVERLOAD_2(once_set, volatile, unsigned int, nr) +__RTE_BIT_OVERLOAD_2(once_clear, volatile, unsigned int, nr) +__RTE_BIT_OVERLOAD_3(once_assign, volatile, unsigned int, nr, bool, value) +__RTE_BIT_OVERLOAD_2(once_flip, volatile, unsigned int, nr) + #endif #endif /* _RTE_BITOPS_H_ */ From patchwork Thu May 2 05:57:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Mattias_R=C3=B6nnblom?= X-Patchwork-Id: 139799 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B358143F65; Thu, 2 May 2024 08:08:11 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E5E46402E8; Thu, 2 May 2024 08:07:38 +0200 (CEST) Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-db3eur04on2081.outbound.protection.outlook.com [40.107.6.81]) by mails.dpdk.org (Postfix) with ESMTP id CE67E402D7 for ; Thu, 2 May 2024 08:07:33 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=AbB5QPaladELbQMbkafq9Q2FjEU9q0nQJKwwJY9AcvEBTsBrV3CNiqNac8Y0SDIon3J+3xevOj5IVnJz2C7Y2WM1hKKboAIOTCF7Ham7dw+VSk0epZM9U4hDLZ3HECei2qog6AGMexFHZR5d6/y7inaQEf2YgPtW7tYEl9vPXepag7VFLaPgwQ66KY/Sv44a1d+s11Fi43IGlEGk/by73jLsLwca7sstDc3hWEKVBkkRoMhV2kGI34zAyB+qonAssg1Yw+O/p3BtEZXkt7IMl/zpZGn44nxe/XAfFuIPhcbQSXF10Xpcm3ptZOMVjKFuGGnPvoFMo67amiPqkdULmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=3sGw/xeCUCWn//mCtmdfD0/OHX4OH+QhKpNnji9Ybjc=; b=FLI+ewYxHwBn8/PanoBFOOJEiyo/yu0r2l0/CstuydlJz4G/XK1kXIIe00yNoAA755bBzFawXMKhGlgyW5VmCeQDzfJs/DKuM1sSAXpxQJnj/zwC6a5z/0z9iTUk5fE0CSeKEWi9+xL4Rsueo50JAGmEWyZttLHkHtVoni5WkmP5QrclVzQAg99WL8RWeRnrlimt/hVfrRhe+Mznp6jpHWt0XpWQra8gDwfzW1J4fUVoGgORR2Bf9+qLtm0YMCu7KDUSmdDfUzyp5AG87KtEEmwmCl4k57W9/81sLnR2WaWaAvbIitU/7QmNMorz1I1N0MITmq9vZVt0rIDun/foKw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 192.176.1.74) smtp.rcpttodomain=dpdk.org smtp.mailfrom=ericsson.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=ericsson.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ericsson.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=3sGw/xeCUCWn//mCtmdfD0/OHX4OH+QhKpNnji9Ybjc=; b=hGphjBaU+4ZfAop7/dAAlyobXY2l1+69xIm/wHt0s5DWVmIR3miDOYvRdXBtmCzutN2tFbtJm9p9Wy3qQD7E80lB6mgoyWj3Fo4ktujCEeURlgcGirIYInyRA+855QKydBcrA+khNxWNLTawP72hix2UaHeiMRM7B0h9CthsQwZtyTBwy27Hkogn3BLv0KvVUjPTriEDW5+aR9ndpjewi8pBeXWJME76wGofZYux/+mgqeuJ6Pce5ADQ6mSV2pJ+8QhBTjj3+F59bLiIzr/vqDA1I0h8tlYxk9ImP0U0gBr/A1MLLJ5PqX41wWtVQWMyKuW3TOu3GCjrbPRTzENENQ== Received: from DU2PR04CA0057.eurprd04.prod.outlook.com (2603:10a6:10:234::32) by GVXPR07MB9961.eurprd07.prod.outlook.com (2603:10a6:150:11f::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.39; Thu, 2 May 2024 06:07:32 +0000 Received: from DB5PEPF00014B91.eurprd02.prod.outlook.com (2603:10a6:10:234:cafe::14) by DU2PR04CA0057.outlook.office365.com (2603:10a6:10:234::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.36 via Frontend Transport; Thu, 2 May 2024 06:07:31 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 192.176.1.74) smtp.mailfrom=ericsson.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ericsson.com; Received-SPF: Pass (protection.outlook.com: domain of ericsson.com designates 192.176.1.74 as permitted sender) receiver=protection.outlook.com; client-ip=192.176.1.74; helo=oa.msg.ericsson.com; pr=C Received: from oa.msg.ericsson.com (192.176.1.74) by DB5PEPF00014B91.mail.protection.outlook.com (10.167.8.229) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.18 via Frontend Transport; Thu, 2 May 2024 06:07:31 +0000 Received: from seliicinfr00049.seli.gic.ericsson.se (153.88.142.248) by smtp-central.internal.ericsson.com (100.87.178.62) with Microsoft SMTP Server id 15.2.1544.9; Thu, 2 May 2024 08:07:30 +0200 Received: from breslau.. (seliicwb00002.seli.gic.ericsson.se [10.156.25.100]) by seliicinfr00049.seli.gic.ericsson.se (Postfix) with ESMTP id 6FAEB380061; Thu, 2 May 2024 08:07:30 +0200 (CEST) From: =?utf-8?q?Mattias_R=C3=B6nnblom?= To: CC: , Heng Wang , "Stephen Hemminger" , Tyler Retzlaff , =?utf-8?q?Morten_Br=C3=B8rup?= , =?utf-8?q?Mattia?= =?utf-8?q?s_R=C3=B6nnblom?= Subject: [RFC v6 4/6] eal: add unit tests for exactly-once bit access functions Date: Thu, 2 May 2024 07:57:04 +0200 Message-ID: <20240502055706.112443-5-mattias.ronnblom@ericsson.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240502055706.112443-1-mattias.ronnblom@ericsson.com> References: <20240430120810.108928-2-mattias.ronnblom@ericsson.com> <20240502055706.112443-1-mattias.ronnblom@ericsson.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB5PEPF00014B91:EE_|GVXPR07MB9961:EE_ X-MS-Office365-Filtering-Correlation-Id: 09e73556-e21d-4954-cd60-08dc6a6e2759 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|36860700004|376005; X-Microsoft-Antispam-Message-Info: =?utf-8?q?g2pJZD2rE/mOddDn0BR65M55Yy2B1JF?= =?utf-8?q?vON5PDgXSCqw4oGHvls0nbs/jj4gI3E6N4Dq3t7fL7/15eNMcmgwuHGAsHOS5zwtD?= =?utf-8?q?i3aXKsqmdlZAfstQB9VYzgod6QoGuxXYfZY2ECKGctdtggychZiaQyAlOnw3Cz7A4?= =?utf-8?q?qndDoORGlwbxsX+Xo6X5uW8dev0Gs/VHZ1XQQREjs73p0QiP97bpFpBYuyxXjx0Pj?= =?utf-8?q?IfJU2Y+GAfiWriPhCwZIp2lOs++0zQFCUizUbk1rzV8WF018VVFf480S8Gofh0/kb?= =?utf-8?q?/srd1dErikGrJV0TDLhgoDoXdyGT6/0KF9BOGq4nN4iurYWLNWZ3hNAUXIEkyEV4F?= =?utf-8?q?A5ayTjhImYzBjt2SH3EcpW6zR61c4iCCYCqDj/f6Q5epdYO1eZPSroZslSVNYPqYt?= =?utf-8?q?hN/43oGZAijj+VvGgFt5QxNt51hBaTdj0wBM+4Uy4QD5M8RPrAxoELOQrwzAwQeyH?= =?utf-8?q?bZwO20TjaiBNCJfoYZNiAeXiMpVOkNnTNAszuwon+vs67cAYHfcHEmmogV0sB9DJt?= =?utf-8?q?m2t7menE382H7Knmssil8nUbvmniTUUwpeWy3IcfVSrM+3IPae347DWus06XiHKSU?= =?utf-8?q?bobJKlgvw+emFNWaBOVhNPkTE2Jl+K/ab4/rqRiCVpeexKJYL1UJDeFg+Acu1vSWh?= =?utf-8?q?QgA9N5M4mLwdq3vW1ZqE2iZDipfZ1Ne6k0k92E7FvQQ6CCU4570EMAkjiAru9yvoQ?= =?utf-8?q?Yqyl3eh44WLGfBMvK99SuSmtc7ju2PjVkdLIDswy2s/eSpXcF4+zheppINJ7/+L5l?= =?utf-8?q?lzVOWWkkU79nmIl9u9n6fV1hSodonMjrg+4+ZUfd8J23uKS9CbolrhdMoqwY5tHo/?= =?utf-8?q?kO81C4RRPMc6AMDBWkJqzwtlbW19mO4InNvuI8GmLxMkPSL9zezed66PO/uSx7u/x?= =?utf-8?q?OwrWKKZ+APklylxVHS8NjIICkHnMqaQriJdL4rxkc/5rlh7jv5OaaPRutY2HYOm14?= =?utf-8?q?8tMR2znhsSLrmAtwrDn5SAZgeqLKULL9EpPmB1NQEOizH45vS3C30kQtkcfPCN+Br?= =?utf-8?q?IPLTu3G5w1HUPc+0IHeQKL+J0uaRrxYgRsvQ60HKxGOpr6bXaQekNAqoGnqW924qq?= =?utf-8?q?Ct6F6hexxxoaF3yCKrlrW2FvZkJYysBfIrGcKY/QIytoA/9RacVA+NhuqtL8l8Ub9?= =?utf-8?q?8CusdmXvw4iYXDNRmeVKHmDQBh/dZtSoCV5/sLCPF7Kp4tZcXxQ5+UYkkrRPU2IRy?= =?utf-8?q?0LpXiGzI6pgUwohl5g2LR4BT0rRj0zzdssqzP1bawzxr+EoTZiQPVP/Zm6Xt/7p/H?= =?utf-8?q?6XEprVTu4FZbimAHoV1R5Rspm1X+7TunnlrxQQ3ZGZKnGMCRzQvkGMJ8=3D?= X-Forefront-Antispam-Report: CIP:192.176.1.74; CTRY:SE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:oa.msg.ericsson.com; PTR:office365.se.ericsson.net; CAT:NONE; SFS:(13230031)(1800799015)(36860700004)(376005); DIR:OUT; SFP:1101; X-OriginatorOrg: ericsson.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2024 06:07:31.8130 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 09e73556-e21d-4954-cd60-08dc6a6e2759 X-MS-Exchange-CrossTenant-Id: 92e84ceb-fbfd-47ab-be52-080c6b87953f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=92e84ceb-fbfd-47ab-be52-080c6b87953f; Ip=[192.176.1.74]; Helo=[oa.msg.ericsson.com] X-MS-Exchange-CrossTenant-AuthSource: DB5PEPF00014B91.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GVXPR07MB9961 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Extend bitops tests to cover the rte_bit_once_*() family of functions. RFC v5: * Atomic bit op implementation moved from this patch to the proper patch in the series. (Morten Brørup) RFC v4: * Remove redundant continuations. Signed-off-by: Mattias Rönnblom Acked-by: Morten Brørup Acked-by: Tyler Retzlaff --- app/test/test_bitops.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/app/test/test_bitops.c b/app/test/test_bitops.c index 322f58c066..9bffc4da14 100644 --- a/app/test/test_bitops.c +++ b/app/test/test_bitops.c @@ -61,6 +61,14 @@ GEN_TEST_BIT_ACCESS(test_bit_access32, rte_bit_set, rte_bit_clear, GEN_TEST_BIT_ACCESS(test_bit_access64, rte_bit_set, rte_bit_clear, rte_bit_assign, rte_bit_flip, rte_bit_test, 64) +GEN_TEST_BIT_ACCESS(test_bit_once_access32, rte_bit_once_set, + rte_bit_once_clear, rte_bit_once_assign, + rte_bit_once_flip, rte_bit_once_test, 32) + +GEN_TEST_BIT_ACCESS(test_bit_once_access64, rte_bit_once_set, + rte_bit_once_clear, rte_bit_once_assign, + rte_bit_once_flip, rte_bit_once_test, 64) + static uint32_t val32; static uint64_t val64; @@ -177,6 +185,8 @@ static struct unit_test_suite test_suite = { .unit_test_cases = { TEST_CASE(test_bit_access32), TEST_CASE(test_bit_access64), + TEST_CASE(test_bit_once_access32), + TEST_CASE(test_bit_once_access64), TEST_CASE(test_bit_relaxed_set), TEST_CASE(test_bit_relaxed_clear), TEST_CASE(test_bit_relaxed_test_set_clear), From patchwork Thu May 2 05:57:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Mattias_R=C3=B6nnblom?= X-Patchwork-Id: 139800 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 22BF343F65; Thu, 2 May 2024 08:08:20 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A75FB402EF; Thu, 2 May 2024 08:07:54 +0200 (CEST) Received: from EUR02-AM0-obe.outbound.protection.outlook.com (mail-am0eur02on2068.outbound.protection.outlook.com [40.107.247.68]) by mails.dpdk.org (Postfix) with ESMTP id 2FA3E40648 for ; Thu, 2 May 2024 08:07:52 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=D20Z8dfbO+qKA8ZJhYrieLPgxerwDE57A+MqznKUvyopHx4rd4z1dtfyCjIP/hiazWjIwFNDoke7WEvFb569ighmEiQwzCHOd97a6ZH17Z/dODVdVBov1my7z81YCq8mOdGF9+KrNlg/+EUEI/EpJGcPRQX1JWwmBc9uNddeXNyySQAB94mb7NesClKMf53oS6yrwp7xJFQa4BlyOEyF0pY79O+1w5cylPkoM9Z1oI12OQvb246+P4ZxehJ4EL80BYdKCCGn9T0lq9hK3EeFOFsVLDWJUeV4Es9NNniOGEeU7/EJG+L7cRPyDLT5D1CNWa7lDOL70IvbfYqB0uPTwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=iix87jH2d/awBLwQeacjw9HkFf5+mqxMKitHxlP8fMg=; b=ogwInMXiUMFxpfkcbrWULay+p8b6upJlPzViH+81jKkSJhPt9XQSHqChgjqZwbflQzv+ElG+zMmhsWrzXvITiwlalzgZJNPQLsnDop4o2YAA5VcWuD8Ido1qAHo0LcoLgMZR2eG51nlAfhNRMSmTEFWXCub/qNSofp5HGaasT76A80C88Y6kcf7Br6f65k4nLk7TwQMlx71+yFjAldwb8emuF0PuUWvHtHWSNCeQHNy848XvUQpY6elJ6aZQjnuF1kIcyXyew8bE6lFqrZDLFPcxyffrGckGma3ydBhrYWRqE1QN8TyT2H3xe6y5NV5fle8Q5KvYKAv8JOjWVweNFw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 192.176.1.74) smtp.rcpttodomain=dpdk.org smtp.mailfrom=ericsson.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=ericsson.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ericsson.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=iix87jH2d/awBLwQeacjw9HkFf5+mqxMKitHxlP8fMg=; b=RS/72sEWSWwVSXtoZq5JOz5vciStZ9In3Im7p8zpu7ct7SrUD14JEXiCq2Cpp1wPZzrX5JR430cL0m/ddagXAIsSytV6GVdm5Avdolw/0g9InKP4ajQZDVHZ0yeXRRWDqBPY6MbLVz6hXsQmfHdWgv5Ns+IfeS7f1bd264VeO3uBXF5IOUysEuxvnH3U2UcIFPt4vvWJalOlfT9bnnEbVmxyCfNZi7eAB1eGjnS3OTNJiBQ8D3ebF3DTnd+e4gAruTmcdsUQUsFvfXJv0o5/FCPJKJ1MSHLWXi9OfKjL1gKd0wtBWy7ALuMUI4bPU8ZWT/OP9JchfUI/lovNo77wzA== Received: from DU2PR04CA0018.eurprd04.prod.outlook.com (2603:10a6:10:3b::23) by DB9PR07MB8893.eurprd07.prod.outlook.com (2603:10a6:10:301::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.29; Thu, 2 May 2024 06:07:50 +0000 Received: from DB1PEPF000509FA.eurprd03.prod.outlook.com (2603:10a6:10:3b:cafe::b2) by DU2PR04CA0018.outlook.office365.com (2603:10a6:10:3b::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.29 via Frontend Transport; Thu, 2 May 2024 06:07:50 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 192.176.1.74) smtp.mailfrom=ericsson.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ericsson.com; Received-SPF: Pass (protection.outlook.com: domain of ericsson.com designates 192.176.1.74 as permitted sender) receiver=protection.outlook.com; client-ip=192.176.1.74; helo=oa.msg.ericsson.com; pr=C Received: from oa.msg.ericsson.com (192.176.1.74) by DB1PEPF000509FA.mail.protection.outlook.com (10.167.242.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.19 via Frontend Transport; Thu, 2 May 2024 06:07:50 +0000 Received: from seliicinfr00049.seli.gic.ericsson.se (153.88.142.248) by smtp-central.internal.ericsson.com (100.87.178.67) with Microsoft SMTP Server id 15.2.1544.9; Thu, 2 May 2024 08:07:31 +0200 Received: from breslau.. (seliicwb00002.seli.gic.ericsson.se [10.156.25.100]) by seliicinfr00049.seli.gic.ericsson.se (Postfix) with ESMTP id 03B57380061; Thu, 2 May 2024 08:07:31 +0200 (CEST) From: =?utf-8?q?Mattias_R=C3=B6nnblom?= To: CC: , Heng Wang , "Stephen Hemminger" , Tyler Retzlaff , =?utf-8?q?Morten_Br=C3=B8rup?= , =?utf-8?q?Mattia?= =?utf-8?q?s_R=C3=B6nnblom?= Subject: [RFC v6 5/6] eal: add atomic bit operations Date: Thu, 2 May 2024 07:57:05 +0200 Message-ID: <20240502055706.112443-6-mattias.ronnblom@ericsson.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240502055706.112443-1-mattias.ronnblom@ericsson.com> References: <20240430120810.108928-2-mattias.ronnblom@ericsson.com> <20240502055706.112443-1-mattias.ronnblom@ericsson.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB1PEPF000509FA:EE_|DB9PR07MB8893:EE_ X-MS-Office365-Filtering-Correlation-Id: a26a1e4a-35c1-4f96-4dd4-08dc6a6e3266 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|36860700004|376005; X-Microsoft-Antispam-Message-Info: =?utf-8?q?eVGRZz0ztApJ4mW3SX0N4liJDL1Wntz?= =?utf-8?q?fg8oolRDMOJi45UuX+ET7w8R1MMtqI20ETck2X8Eiy+YuPJ2ekHRPpnCe2zQVVn8P?= =?utf-8?q?4cGjccKGmk+i3++0HQAb1JPrLfhnIoy2HgDs6do/cLVvrU7QgLAyQK8NQ9nwxZt5X?= =?utf-8?q?Gl3ZTiBejLnI+Vu4SWPBVnja6TfS5BYqGArIvJy+pokeakKf2jGYpiC5mSDoi1r/F?= =?utf-8?q?965+swc+KsduQaLv/HIeomOi2hjyqEaQBXo7Bk8WQZNVz9viLttrV1x9qipSkdXU7?= =?utf-8?q?rNfYERdVP8fRBTl/eL8hw94IFLbX+j75q7GogI0l7C5AZfaHtVxHMMuJsAzP8p/+x?= =?utf-8?q?jUC4w0yWg1+qjjNUeBHWW1gWfuys3QwqqRysK2cBab0VhsuakOka3y9AFfY5pj9ui?= =?utf-8?q?z4k4Fgl37ySiLAV9a+RNX7UDG8Dg8s3DN0v8Lq4OvBxJVswvllwf9B5PS9O9rl4nb?= =?utf-8?q?zpRQ12ZmSA0Bsj+j4vQREBJ1deK/7BazkwoBOjLyYzj+kYeB7HkYdxQ90+wIpUCRF?= =?utf-8?q?kXNCGKBT4RUEyXbYKMb/0Uewf2iPFhBzu9ZTMwxEP+sjTVrCB0RFw06MgNZdWH369?= =?utf-8?q?Sgt2+uqD/k8l6yP/MaWrnqvt7tFcgoDiPc3QIuNh2RUNnQ1C1VS1MCKAGjKy1P/Qs?= =?utf-8?q?5YhDoPG5ATa4CxIPAFKAUhqvN4jtQ7ICim9cJuJ8W0Rr3Soan76btZGChc+3DtjYr?= =?utf-8?q?+CPk32bIdIEult2XJ7yNPLD7iadSFWALuF84FG4JaG1Y00LiRBx/nAcgwZfXSNX7a?= =?utf-8?q?VD/PFkPjOh/xKlE8ksTi1ee1RavDmUjjQ5kTfmwLaI612DRAzpO4d9I11tSFs2nVX?= =?utf-8?q?NT8+tR/uSIOFq453t9dYRvSek1li43a7PFZbHf9Vr7hGdDoV0MTfTItJ52aL/DD3H?= =?utf-8?q?+r4ncD8lXS5doeRX01ZdyiXjXn3RkLcrXO8fkalT2NVuXSYyiXs/EKzvAEUPMSQRG?= =?utf-8?q?cE7C4OHPWtn/wYjeG2OiM1o3nDF8VpELdBOlccrIOUVkkcFBYAo4ZTjYsbDM3+l8D?= =?utf-8?q?PzoLd9+UtxrC81Fzk5ec/hS8LYYabeaL4mTFH7cGoXMXUGQtzCctZ44uhaOqR0j3c?= =?utf-8?q?WSOJOjQ6Vz7OYErIyGm3NLwb0dx14krmXnrzJzfkQGQ3gnLqWiU/wx9Vu8iUtGkS5?= =?utf-8?q?1Jd+SjJJ009Nno4mXrehsSZD+EaRYTLKna160szvs5lI0M9ntRd8Upw5ANAsJtt2I?= =?utf-8?q?tM9kKz2FbyVYjFtEZ2dyw9C5HuFjvRlzhzUN6PlCDbw1Ckq8tE6BmYFvOTpg08AvC?= =?utf-8?q?5O/jZwL5OHGdEGwe20274HHKE8mC180uO94vjQrCFdY7ZNvygKiOj4xZ2WzkxD7p+?= =?utf-8?q?UbjGb4p2iG5J?= X-Forefront-Antispam-Report: CIP:192.176.1.74; CTRY:SE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:oa.msg.ericsson.com; PTR:office365.se.ericsson.net; CAT:NONE; SFS:(13230031)(1800799015)(36860700004)(376005); DIR:OUT; SFP:1101; X-OriginatorOrg: ericsson.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2024 06:07:50.3498 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a26a1e4a-35c1-4f96-4dd4-08dc6a6e3266 X-MS-Exchange-CrossTenant-Id: 92e84ceb-fbfd-47ab-be52-080c6b87953f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=92e84ceb-fbfd-47ab-be52-080c6b87953f; Ip=[192.176.1.74]; Helo=[oa.msg.ericsson.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509FA.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR07MB8893 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add atomic bit test/set/clear/assign/flip and test-and-set/clear/assign/flip functions. All atomic bit functions allow (and indeed, require) the caller to specify a memory order. RFC v6: * Have rte_bit_atomic_test() accept const-marked bitsets. RFC v4: * Add atomic bit flip. * Mark macro-generated private functions experimental. RFC v3: * Work around lack of C++ support for _Generic (Tyler Retzlaff). RFC v2: o Add rte_bit_atomic_test_and_assign() (for consistency). o Fix bugs in rte_bit_atomic_test_and_[set|clear](). o Use to support MSVC. Signed-off-by: Mattias Rönnblom Acked-by: Morten Brørup Acked-by: Tyler Retzlaff --- lib/eal/include/rte_bitops.h | 428 +++++++++++++++++++++++++++++++++++ 1 file changed, 428 insertions(+) diff --git a/lib/eal/include/rte_bitops.h b/lib/eal/include/rte_bitops.h index caec4f36bb..9cde982113 100644 --- a/lib/eal/include/rte_bitops.h +++ b/lib/eal/include/rte_bitops.h @@ -21,6 +21,7 @@ #include #include +#include #ifdef __cplusplus extern "C" { @@ -399,6 +400,202 @@ extern "C" { uint32_t *: __rte_bit_once_flip32, \ uint64_t *: __rte_bit_once_flip64)(addr, nr) +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Test if a particular bit in a word is set with a particular memory + * order. + * + * Test a bit with the resulting memory load ordered as per the + * specified memory order. + * + * @param addr + * A pointer to the word to query. + * @param nr + * The index of the bit. + * @param memory_order + * The memory order to use. See for details. + * @return + * Returns true if the bit is set, and false otherwise. + */ +#define rte_bit_atomic_test(addr, nr, memory_order) \ + _Generic((addr), \ + uint32_t *: __rte_bit_atomic_test32, \ + const uint32_t *: __rte_bit_atomic_test32, \ + uint64_t *: __rte_bit_atomic_test64, \ + const uint64_t *: __rte_bit_atomic_test64)(addr, nr, \ + memory_order) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Atomically set bit in word. + * + * Atomically set bit specified by @c nr in the word pointed to by @c + * addr to '1', with the memory ordering as specified by @c + * memory_order. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param memory_order + * The memory order to use. See for details. + */ +#define rte_bit_atomic_set(addr, nr, memory_order) \ + _Generic((addr), \ + uint32_t *: __rte_bit_atomic_set32, \ + uint64_t *: __rte_bit_atomic_set64)(addr, nr, memory_order) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Atomically clear bit in word. + * + * Atomically set bit specified by @c nr in the word pointed to by @c + * addr to '0', with the memory ordering as specified by @c + * memory_order. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param memory_order + * The memory order to use. See for details. + */ +#define rte_bit_atomic_clear(addr, nr, memory_order) \ + _Generic((addr), \ + uint32_t *: __rte_bit_atomic_clear32, \ + uint64_t *: __rte_bit_atomic_clear64)(addr, nr, memory_order) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Atomically assign a value to bit in word. + * + * Atomically set bit specified by @c nr in the word pointed to by @c + * addr to the value indicated by @c value, with the memory ordering + * as specified with @c memory_order. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param value + * The new value of the bit - true for '1', or false for '0'. + * @param memory_order + * The memory order to use. See for details. + */ +#define rte_bit_atomic_assign(addr, nr, value, memory_order) \ + _Generic((addr), \ + uint32_t *: __rte_bit_atomic_assign32, \ + uint64_t *: __rte_bit_atomic_assign64)(addr, nr, value, \ + memory_order) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Atomically flip bit in word. + * + * Atomically negate the value of the bit specified by @c nr in the + * word pointed to by @c addr to the value indicated by @c value, with + * the memory ordering as specified with @c memory_order. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param memory_order + * The memory order to use. See for details. + */ +#define rte_bit_atomic_flip(addr, nr, memory_order) \ + _Generic((addr), \ + uint32_t *: __rte_bit_atomic_flip32, \ + uint64_t *: __rte_bit_atomic_flip64)(addr, nr, memory_order) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Atomically test and set a bit in word. + * + * Atomically test and set bit specified by @c nr in the word pointed + * to by @c addr to '1', with the memory ordering as specified with @c + * memory_order. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param memory_order + * The memory order to use. See for details. + * @return + * Returns true if the bit was set, and false otherwise. + */ +#define rte_bit_atomic_test_and_set(addr, nr, memory_order) \ + _Generic((addr), \ + uint32_t *: __rte_bit_atomic_test_and_set32, \ + uint64_t *: __rte_bit_atomic_test_and_set64)(addr, nr, \ + memory_order) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Atomically test and clear a bit in word. + * + * Atomically test and clear bit specified by @c nr in the word + * pointed to by @c addr to '0', with the memory ordering as specified + * with @c memory_order. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param memory_order + * The memory order to use. See for details. + * @return + * Returns true if the bit was set, and false otherwise. + */ +#define rte_bit_atomic_test_and_clear(addr, nr, memory_order) \ + _Generic((addr), \ + uint32_t *: __rte_bit_atomic_test_and_clear32, \ + uint64_t *: __rte_bit_atomic_test_and_clear64)(addr, nr, \ + memory_order) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Atomically test and assign a bit in word. + * + * Atomically test and assign bit specified by @c nr in the word + * pointed to by @c addr the value specified by @c value, with the + * memory ordering as specified with @c memory_order. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param value + * The new value of the bit - true for '1', or false for '0'. + * @param memory_order + * The memory order to use. See for details. + * @return + * Returns true if the bit was set, and false otherwise. + */ +#define rte_bit_atomic_test_and_assign(addr, nr, value, memory_order) \ + _Generic((addr), \ + uint32_t *: __rte_bit_atomic_test_and_assign32, \ + uint64_t *: __rte_bit_atomic_test_and_assign64)(addr, nr, \ + value, \ + memory_order) + #define __RTE_GEN_BIT_TEST(family, fun, qualifier, size) \ __rte_experimental \ static inline bool \ @@ -483,6 +680,162 @@ __RTE_GEN_BIT_CLEAR(once_, clear, volatile, 64) __RTE_GEN_BIT_ASSIGN(once_, assign, volatile, 64) __RTE_GEN_BIT_FLIP(once_, flip, volatile, 64) +#define __RTE_GEN_BIT_ATOMIC_TEST(size) \ + __rte_experimental \ + static inline bool \ + __rte_bit_atomic_test ## size(const uint ## size ## _t *addr, \ + unsigned int nr, int memory_order) \ + { \ + RTE_ASSERT(nr < size); \ + \ + const RTE_ATOMIC(uint ## size ## _t) *a_addr = \ + (const RTE_ATOMIC(uint ## size ## _t) *)addr; \ + uint ## size ## _t mask = (uint ## size ## _t)1 << nr; \ + return rte_atomic_load_explicit(a_addr, memory_order) & mask; \ + } + +#define __RTE_GEN_BIT_ATOMIC_SET(size) \ + __rte_experimental \ + static inline void \ + __rte_bit_atomic_set ## size(uint ## size ## _t *addr, \ + unsigned int nr, int memory_order) \ + { \ + RTE_ASSERT(nr < size); \ + \ + RTE_ATOMIC(uint ## size ## _t) *a_addr = \ + (RTE_ATOMIC(uint ## size ## _t) *)addr; \ + uint ## size ## _t mask = (uint ## size ## _t)1 << nr; \ + rte_atomic_fetch_or_explicit(a_addr, mask, memory_order); \ + } + +#define __RTE_GEN_BIT_ATOMIC_CLEAR(size) \ + __rte_experimental \ + static inline void \ + __rte_bit_atomic_clear ## size(uint ## size ## _t *addr, \ + unsigned int nr, int memory_order) \ + { \ + RTE_ASSERT(nr < size); \ + \ + RTE_ATOMIC(uint ## size ## _t) *a_addr = \ + (RTE_ATOMIC(uint ## size ## _t) *)addr; \ + uint ## size ## _t mask = (uint ## size ## _t)1 << nr; \ + rte_atomic_fetch_and_explicit(a_addr, ~mask, memory_order); \ + } + +#define __RTE_GEN_BIT_ATOMIC_ASSIGN(size) \ + __rte_experimental \ + static inline void \ + __rte_bit_atomic_assign ## size(uint ## size ## _t *addr, \ + unsigned int nr, bool value, \ + int memory_order) \ + { \ + if (value) \ + __rte_bit_atomic_set ## size(addr, nr, memory_order); \ + else \ + __rte_bit_atomic_clear ## size(addr, nr, \ + memory_order); \ + } + +#define __RTE_GEN_BIT_ATOMIC_TEST_AND_ASSIGN(size) \ + __rte_experimental \ + static inline bool \ + __rte_bit_atomic_test_and_assign ## size(uint ## size ## _t *addr, \ + unsigned int nr, \ + bool value, \ + int memory_order) \ + { \ + RTE_ASSERT(nr < size); \ + \ + RTE_ATOMIC(uint ## size ## _t) *a_addr = \ + (RTE_ATOMIC(uint ## size ## _t) *)addr; \ + uint ## size ## _t before; \ + uint ## size ## _t target; \ + \ + before = rte_atomic_load_explicit(a_addr, \ + rte_memory_order_relaxed); \ + \ + do { \ + target = before; \ + __rte_bit_assign ## size(&target, nr, value); \ + } while (!rte_atomic_compare_exchange_weak_explicit( \ + a_addr, &before, target, \ + rte_memory_order_relaxed, \ + memory_order)); \ + return __rte_bit_test ## size(&before, nr); \ + } + +#define __RTE_GEN_BIT_ATOMIC_FLIP(size) \ + __rte_experimental \ + static inline void \ + __rte_bit_atomic_flip ## size(uint ## size ## _t *addr, \ + unsigned int nr, int memory_order) \ + { \ + RTE_ASSERT(nr < size); \ + \ + RTE_ATOMIC(uint ## size ## _t) *a_addr = \ + (RTE_ATOMIC(uint ## size ## _t) *)addr; \ + uint ## size ## _t before; \ + uint ## size ## _t target; \ + \ + before = rte_atomic_load_explicit(a_addr, \ + rte_memory_order_relaxed); \ + \ + do { \ + target = before; \ + __rte_bit_flip ## size(&target, nr); \ + } while (!rte_atomic_compare_exchange_weak_explicit( \ + a_addr, &before, target, \ + rte_memory_order_relaxed, \ + memory_order)); \ + } + +#define __RTE_GEN_BIT_ATOMIC_OPS(size) \ + __RTE_GEN_BIT_ATOMIC_TEST(size) \ + __RTE_GEN_BIT_ATOMIC_SET(size) \ + __RTE_GEN_BIT_ATOMIC_CLEAR(size) \ + __RTE_GEN_BIT_ATOMIC_ASSIGN(size) \ + __RTE_GEN_BIT_ATOMIC_TEST_AND_ASSIGN(size) \ + __RTE_GEN_BIT_ATOMIC_FLIP(size) + +__RTE_GEN_BIT_ATOMIC_OPS(32) +__RTE_GEN_BIT_ATOMIC_OPS(64) + +__rte_experimental +static inline bool +__rte_bit_atomic_test_and_set32(uint32_t *addr, unsigned int nr, + int memory_order) +{ + return __rte_bit_atomic_test_and_assign32(addr, nr, true, + memory_order); +} + +__rte_experimental +static inline bool +__rte_bit_atomic_test_and_clear32(uint32_t *addr, unsigned int nr, + int memory_order) +{ + return __rte_bit_atomic_test_and_assign32(addr, nr, false, + memory_order); +} + +__rte_experimental +static inline bool +__rte_bit_atomic_test_and_set64(uint64_t *addr, unsigned int nr, + int memory_order) +{ + return __rte_bit_atomic_test_and_assign64(addr, nr, true, + memory_order); +} + +__rte_experimental +static inline bool +__rte_bit_atomic_test_and_clear64(uint64_t *addr, unsigned int nr, + int memory_order) +{ + return __rte_bit_atomic_test_and_assign64(addr, nr, false, + memory_order); +} + /*------------------------ 32-bit relaxed operations ------------------------*/ /** @@ -1184,6 +1537,14 @@ rte_log2_u64(uint64_t v) #undef rte_bit_once_assign #undef rte_bit_once_flip +#undef rte_bit_atomic_test +#undef rte_bit_atomic_set +#undef rte_bit_atomic_clear +#undef rte_bit_atomic_assign +#undef rte_bit_atomic_test_and_set +#undef rte_bit_atomic_test_and_clear +#undef rte_bit_atomic_test_and_assign + #define __RTE_BIT_OVERLOAD_SZ_2(fun, qualifier, size, arg1_type, arg1_name) \ static inline void \ rte_bit_ ## fun(qualifier uint ## size ## _t *addr, \ @@ -1227,6 +1588,59 @@ rte_log2_u64(uint64_t v) __RTE_BIT_OVERLOAD_SZ_3(fun, qualifier, 64, arg1_type, arg1_name, \ arg2_type, arg2_name) +#define __RTE_BIT_OVERLOAD_SZ_3R(fun, qualifier, size, ret_type, arg1_type, \ + arg1_name, arg2_type, arg2_name) \ + static inline ret_type \ + rte_bit_ ## fun(uint ## size ## _t *addr, arg1_type arg1_name, \ + arg2_type arg2_name) \ + { \ + return __rte_bit_ ## fun ## size(addr, arg1_name, arg2_name); \ + } + +#define __RTE_BIT_OVERLOAD_3R(fun, qualifier, ret_type, arg1_type, arg1_name, \ + arg2_type, arg2_name) \ + __RTE_BIT_OVERLOAD_SZ_3R(fun, qualifier, 32, ret_type, arg1_type, \ + arg1_name, arg2_type, arg2_name) \ + __RTE_BIT_OVERLOAD_SZ_3R(fun, qualifier, 64, ret_type, arg1_type, \ + arg1_name, arg2_type, arg2_name) + +#define __RTE_BIT_OVERLOAD_SZ_4(fun, qualifier, size, arg1_type, arg1_name, \ + arg2_type, arg2_name, arg3_type, arg3_name) \ + static inline void \ + rte_bit_ ## fun(uint ## size ## _t *addr, arg1_type arg1_name, \ + arg2_type arg2_name, arg3_type arg3_name) \ + { \ + __rte_bit_ ## fun ## size(addr, arg1_name, arg2_name, \ + arg3_name); \ + } + +#define __RTE_BIT_OVERLOAD_4(fun, qualifier, arg1_type, arg1_name, arg2_type, \ + arg2_name, arg3_type, arg3_name) \ + __RTE_BIT_OVERLOAD_SZ_4(fun, qualifier, 32, arg1_type, arg1_name, \ + arg2_type, arg2_name, arg3_type, arg3_name) \ + __RTE_BIT_OVERLOAD_SZ_4(fun, qualifier, 64, arg1_type, arg1_name, \ + arg2_type, arg2_name, arg3_type, arg3_name) + +#define __RTE_BIT_OVERLOAD_SZ_4R(fun, qualifier, size, ret_type, arg1_type, \ + arg1_name, arg2_type, arg2_name, arg3_type, \ + arg3_name) \ + static inline ret_type \ + rte_bit_ ## fun(uint ## size ## _t *addr, arg1_type arg1_name, \ + arg2_type arg2_name, arg3_type arg3_name) \ + { \ + return __rte_bit_ ## fun ## size(addr, arg1_name, arg2_name, \ + arg3_name); \ + } + +#define __RTE_BIT_OVERLOAD_4R(fun, qualifier, ret_type, arg1_type, arg1_name, \ + arg2_type, arg2_name, arg3_type, arg3_name) \ + __RTE_BIT_OVERLOAD_SZ_4R(fun, qualifier, 32, ret_type, arg1_type, \ + arg1_name, arg2_type, arg2_name, arg3_type, \ + arg3_name) \ + __RTE_BIT_OVERLOAD_SZ_4R(fun, qualifier, 64, ret_type, arg1_type, \ + arg1_name, arg2_type, arg2_name, arg3_type, \ + arg3_name) + __RTE_BIT_OVERLOAD_2R(test, const, bool, unsigned int, nr) __RTE_BIT_OVERLOAD_2(set,, unsigned int, nr) __RTE_BIT_OVERLOAD_2(clear,, unsigned int, nr) @@ -1239,6 +1653,20 @@ __RTE_BIT_OVERLOAD_2(once_clear, volatile, unsigned int, nr) __RTE_BIT_OVERLOAD_3(once_assign, volatile, unsigned int, nr, bool, value) __RTE_BIT_OVERLOAD_2(once_flip, volatile, unsigned int, nr) +__RTE_BIT_OVERLOAD_3R(atomic_test, const, bool, unsigned int, nr, + int, memory_order) +__RTE_BIT_OVERLOAD_3(atomic_set,, unsigned int, nr, int, memory_order) +__RTE_BIT_OVERLOAD_3(atomic_clear,, unsigned int, nr, int, memory_order) +__RTE_BIT_OVERLOAD_4(atomic_assign,, unsigned int, nr, bool, value, + int, memory_order) +__RTE_BIT_OVERLOAD_3(atomic_flip,, unsigned int, nr, int, memory_order) +__RTE_BIT_OVERLOAD_3R(atomic_test_and_set,, bool, unsigned int, nr, + int, memory_order) +__RTE_BIT_OVERLOAD_3R(atomic_test_and_clear,, bool, unsigned int, nr, + int, memory_order) +__RTE_BIT_OVERLOAD_4R(atomic_test_and_assign,, bool, unsigned int, nr, + bool, value, int, memory_order) + #endif #endif /* _RTE_BITOPS_H_ */ From patchwork Thu May 2 05:57:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Mattias_R=C3=B6nnblom?= X-Patchwork-Id: 139798 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8F04A43F65; Thu, 2 May 2024 08:08:04 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9610D402F0; Thu, 2 May 2024 08:07:37 +0200 (CEST) Received: from EUR02-AM0-obe.outbound.protection.outlook.com (mail-am0eur02on2080.outbound.protection.outlook.com [40.107.247.80]) by mails.dpdk.org (Postfix) with ESMTP id 86BD3402D6 for ; Thu, 2 May 2024 08:07:33 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=jwbZgHVwTMP4EHdlIlzKWMhWeSbcp9S/pYHVMFZpf3j/wU9YC0b7E8vxpBo7gZfzyOebPtIXMBBWn+weScurUw2a5j4z6o3vEI7j/klAn0SezElBTqTrlHvjJ3QirwMMb5EixwOTjsgEtIQtLjFuOzA4rZi6ppA1PcYV+31Et63UjxTGC4OU/35ecKwh5ZgoNZnECAx/OnGThoZOgrrgSMIrZByare7UekRAmT235UX1ol0+QS67P0sWksr4QvMx6xuZzVJUSWcz7hq3Epm6O2D6EKz2G36NACTwk+iJsXgxRQFNEJP8n49GNIu9AoMozW8wDQSUjQKYzj626VcrKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=9OUelsYpMkkuM3XvGHV53aJb4v8YWs53DjmkXfumHoc=; b=ZdRvL9iag0MVyLoL+ivfHHSbVgeh4dhjZv1g05wBfB2LiO4b0Dm+wYvLj22/I93F4tw2gx+b0SmIZnPCUiodi8yZ1h6GS66JQIp7G0fCSTLw8YF9o/f2/ors1tgy7ONEvZkM4LDKZ/UvzGI7jI+YN5qR1JGsqV23y1/mlMaKv1gCb4QVCQJK4MbEvjWX5vy2ESDyMT1xqRLLBQFgjw48sqwHBYfOv7dayl4Hjm/A1Kpi4JFzscaJ4IpOQdjc1Cx6vRxSgc5QQMsYIaSNIApGWVXX4VxR9R5VktX4uN9QhxOIdO3M0jDljK0wKHMQUf7NfvpM0z3Sq+o7IB7nt8UGGA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 192.176.1.74) smtp.rcpttodomain=dpdk.org smtp.mailfrom=ericsson.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=ericsson.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ericsson.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=9OUelsYpMkkuM3XvGHV53aJb4v8YWs53DjmkXfumHoc=; b=jo0r5exqj3lg8w5FpZbpLK47fQ53rGSlwsGGD4bqX+v7LPpuJM7AvPho5XZ3bGkpBiq4+XkYxaVDHSUExDrX0TzNT5PQbmNPOh9fV5hWlsksaZhk6/UxGzcsC/+MaCNtN6yUEHxXi7SIM+npF7F/sgXlU7b7qPke186GM5xQMa1sIlH1FuVyvxu71ZqRLcBSKs3e6Spk6BLcNiiud2UwM5CcH/zZK674qmG9SIMmgXAQgZsDVBppP4Xok/kBVMhvR1UYWL4USKI0gUamARzh/TJWoBL4hp9Iv6Iv9oOSUnvZL1s8ANfLcPV2YBblFrXJS7rxn45CftbxpH/4mIwPlQ== Received: from AS4P251CA0024.EURP251.PROD.OUTLOOK.COM (2603:10a6:20b:5d3::16) by DB9PR07MB10004.eurprd07.prod.outlook.com (2603:10a6:10:4cd::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.29; Thu, 2 May 2024 06:07:32 +0000 Received: from AM4PEPF00025F98.EURPRD83.prod.outlook.com (2603:10a6:20b:5d3:cafe::2e) by AS4P251CA0024.outlook.office365.com (2603:10a6:20b:5d3::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7452.27 via Frontend Transport; Thu, 2 May 2024 06:07:32 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 192.176.1.74) smtp.mailfrom=ericsson.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ericsson.com; Received-SPF: Pass (protection.outlook.com: domain of ericsson.com designates 192.176.1.74 as permitted sender) receiver=protection.outlook.com; client-ip=192.176.1.74; helo=oa.msg.ericsson.com; pr=C Received: from oa.msg.ericsson.com (192.176.1.74) by AM4PEPF00025F98.mail.protection.outlook.com (10.167.16.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.0 via Frontend Transport; Thu, 2 May 2024 06:07:31 +0000 Received: from seliicinfr00049.seli.gic.ericsson.se (153.88.142.248) by smtp-central.internal.ericsson.com (100.87.178.60) with Microsoft SMTP Server id 15.2.1544.9; Thu, 2 May 2024 08:07:31 +0200 Received: from breslau.. (seliicwb00002.seli.gic.ericsson.se [10.156.25.100]) by seliicinfr00049.seli.gic.ericsson.se (Postfix) with ESMTP id 8056E380061; Thu, 2 May 2024 08:07:31 +0200 (CEST) From: =?utf-8?q?Mattias_R=C3=B6nnblom?= To: CC: , Heng Wang , "Stephen Hemminger" , Tyler Retzlaff , =?utf-8?q?Morten_Br=C3=B8rup?= , =?utf-8?q?Mattia?= =?utf-8?q?s_R=C3=B6nnblom?= Subject: [RFC v6 6/6] eal: add unit tests for atomic bit access functions Date: Thu, 2 May 2024 07:57:06 +0200 Message-ID: <20240502055706.112443-7-mattias.ronnblom@ericsson.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240502055706.112443-1-mattias.ronnblom@ericsson.com> References: <20240430120810.108928-2-mattias.ronnblom@ericsson.com> <20240502055706.112443-1-mattias.ronnblom@ericsson.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM4PEPF00025F98:EE_|DB9PR07MB10004:EE_ X-MS-Office365-Filtering-Correlation-Id: 1463655b-71f5-4d0a-c5c4-08dc6a6e2770 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|36860700004|376005; X-Microsoft-Antispam-Message-Info: =?utf-8?q?tTzI7EhL8L6byEHhpEd9EK9bEs4Qns/?= =?utf-8?q?SXhPLlWNTRq4r+iWBMhv298yr1ZpEsrqLHSmrusH56NQW31LjUtS+5YtudGYLNWd8?= =?utf-8?q?f66+o8gHfe6tEUaPUbX2X4I3TWRknUqHLeE1LhRTvkrSLoqyM4zGEnggm+k7qx+kj?= =?utf-8?q?+oGrzMnCMoHndscj1SwQxYLh/dzan8Bz6ezEdUS9VjqxBpyQduj7JJxwqSF/R2R71?= =?utf-8?q?NE2do7ad8qi3x/pdSoDsZzTZ9QVrWs7L1VorHtSjD62tZcNGkZ9kPDvi8IqDU0fdg?= =?utf-8?q?nM14CPbqdeBU7TU3glYOFfmEkSYH/2hITz8k6oCb4TUbw8PLinlZBDQtxjkna0Pjz?= =?utf-8?q?RNLjp46LCU+A14RZAIqqthF4kMwGMTLq7mEC5Ewks3wXNaXFKZh0SMHF/xnwh0n+J?= =?utf-8?q?qZFZocPoBDO+yLpW9W4PG1f29O44FkEHIaLVX/n29Z3buO/rWeGOvELLBro1B0OhN?= =?utf-8?q?arvWvvz+RjHuT++onTRTdUCz8Zvh60ta4w1sXLyt5UjLzNW46MEnhYOmeZ9MerplP?= =?utf-8?q?xz8vqS6C2ABEwpJDK1CY96sfaTTkYG6QxHmHEsdAIPMjhh4+TLeVLIkukY+z8XuLN?= =?utf-8?q?8y6yfqFJwcwoaE1JE3ZNjqhuC9rGfI9gH1E9jVwXguDMqcW1e3/1RuJFRDQBgVEBd?= =?utf-8?q?Go1cUQct22VEezJYsD5i/dIwPo7xE3oUnCCdf5BGOg/rjmdEHszK90pfGYhLvewyn?= =?utf-8?q?iaecO6UZTcdpwIr9Nyi9P/pr+0DvZ5OM2s7atwJWozjpTxm2fYOO15h0msRaN4Ls5?= =?utf-8?q?K2NoBDX/6QB1M0de0PEvhABVtlhUNjQZStPRcHlb9B5qz4dBYuksvxFdwNpYOsAWd?= =?utf-8?q?muHdOyMceHcokjkefqsRpr+sIOyqjpBVAiH8VTzDa4GTbtRu22usT/dKrgcprI7HK?= =?utf-8?q?0Yw1mlL6q4XrdcYqAPeyHsqIwep8uLjtWIAF3vaXeNFnnjBxECLJ4pOL89wb3tKOL?= =?utf-8?q?2kC9JI97wWUKW/kwV81JwXPvUeCu5hool8rTRLibml4IqgBckB0g9smiWI9mdUlit?= =?utf-8?q?KXVdlPszWa758Q0x0bmQn8z8+DqL0HkJGx1jW3FhtjCPrJCqPjblMIlmCkqy3oKp1?= =?utf-8?q?Te4Kec2qntpsw6G2AnSEHl7rNAKNxhWnUm+upfNNypZUKycfnlRXd2Zas2fE0Bhev?= =?utf-8?q?1WNMkvc/nUHMNtqedAyHhjK47T+S0jEknHra24/4xTBzW+P7S9HCFMqAUNojr8KUP?= =?utf-8?q?VYFMDzGfIx/UNqOc3s9nMIConPBfgM7FH9EoPLFCTkHMeOybNKTgog55g8F/ZL+Ld?= =?utf-8?q?M4p+1Q1NsKvoaJwxubuZl3KCLf2LOata2WUMIIT6Bkg3erjLMD+Zx/fgUP/TP49bn?= =?utf-8?q?nClLrFLrDih4?= X-Forefront-Antispam-Report: CIP:192.176.1.74; CTRY:SE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:oa.msg.ericsson.com; PTR:office365.se.ericsson.net; CAT:NONE; SFS:(13230031)(1800799015)(36860700004)(376005); DIR:OUT; SFP:1101; X-OriginatorOrg: ericsson.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2024 06:07:31.9947 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1463655b-71f5-4d0a-c5c4-08dc6a6e2770 X-MS-Exchange-CrossTenant-Id: 92e84ceb-fbfd-47ab-be52-080c6b87953f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=92e84ceb-fbfd-47ab-be52-080c6b87953f; Ip=[192.176.1.74]; Helo=[oa.msg.ericsson.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00025F98.EURPRD83.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR07MB10004 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Extend bitops tests to cover the rte_bit_atomic_*() family of functions. RFC v4: * Add atomicity test for atomic bit flip. RFC v3: * Rename variable 'main' to make ICC happy. Signed-off-by: Mattias Rönnblom Acked-by: Morten Brørup Acked-by: Tyler Retzlaff --- app/test/test_bitops.c | 315 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 314 insertions(+), 1 deletion(-) diff --git a/app/test/test_bitops.c b/app/test/test_bitops.c index 9bffc4da14..c86d7e1f77 100644 --- a/app/test/test_bitops.c +++ b/app/test/test_bitops.c @@ -3,10 +3,13 @@ * Copyright(c) 2024 Ericsson AB */ +#include #include -#include #include +#include +#include +#include #include #include "test.h" @@ -69,6 +72,304 @@ GEN_TEST_BIT_ACCESS(test_bit_once_access64, rte_bit_once_set, rte_bit_once_clear, rte_bit_once_assign, rte_bit_once_flip, rte_bit_once_test, 64) +#define bit_atomic_set(addr, nr) \ + rte_bit_atomic_set(addr, nr, rte_memory_order_relaxed) + +#define bit_atomic_clear(addr, nr) \ + rte_bit_atomic_clear(addr, nr, rte_memory_order_relaxed) + +#define bit_atomic_assign(addr, nr, value) \ + rte_bit_atomic_assign(addr, nr, value, rte_memory_order_relaxed) + +#define bit_atomic_flip(addr, nr) \ + rte_bit_atomic_flip(addr, nr, rte_memory_order_relaxed) + +#define bit_atomic_test(addr, nr) \ + rte_bit_atomic_test(addr, nr, rte_memory_order_relaxed) + +GEN_TEST_BIT_ACCESS(test_bit_atomic_access32, bit_atomic_set, + bit_atomic_clear, bit_atomic_assign, + bit_atomic_flip, bit_atomic_test, 32) + +GEN_TEST_BIT_ACCESS(test_bit_atomic_access64, bit_atomic_set, + bit_atomic_clear, bit_atomic_assign, + bit_atomic_flip, bit_atomic_test, 64) + +#define PARALLEL_TEST_RUNTIME 0.25 + +#define GEN_TEST_BIT_PARALLEL_ASSIGN(size) \ + \ + struct parallel_access_lcore ## size \ + { \ + unsigned int bit; \ + uint ## size ##_t *word; \ + bool failed; \ + }; \ + \ + static int \ + run_parallel_assign ## size(void *arg) \ + { \ + struct parallel_access_lcore ## size *lcore = arg; \ + uint64_t deadline = rte_get_timer_cycles() + \ + PARALLEL_TEST_RUNTIME * rte_get_timer_hz(); \ + bool value = false; \ + \ + do { \ + bool new_value = rte_rand() & 1; \ + bool use_test_and_modify = rte_rand() & 1; \ + bool use_assign = rte_rand() & 1; \ + \ + if (rte_bit_atomic_test(lcore->word, lcore->bit, \ + rte_memory_order_relaxed) != value) { \ + lcore->failed = true; \ + break; \ + } \ + \ + if (use_test_and_modify) { \ + bool old_value; \ + if (use_assign) \ + old_value = rte_bit_atomic_test_and_assign( \ + lcore->word, lcore->bit, new_value, \ + rte_memory_order_relaxed); \ + else { \ + old_value = new_value ? \ + rte_bit_atomic_test_and_set( \ + lcore->word, lcore->bit, \ + rte_memory_order_relaxed) : \ + rte_bit_atomic_test_and_clear( \ + lcore->word, lcore->bit, \ + rte_memory_order_relaxed); \ + } \ + if (old_value != value) { \ + lcore->failed = true; \ + break; \ + } \ + } else { \ + if (use_assign) \ + rte_bit_atomic_assign(lcore->word, lcore->bit, \ + new_value, \ + rte_memory_order_relaxed); \ + else { \ + if (new_value) \ + rte_bit_atomic_set( \ + lcore->word, lcore->bit, \ + rte_memory_order_relaxed); \ + else \ + rte_bit_atomic_clear( \ + lcore->word, lcore->bit, \ + rte_memory_order_relaxed); \ + } \ + } \ + \ + value = new_value; \ + } while (rte_get_timer_cycles() < deadline); \ + \ + return 0; \ + } \ + \ + static int \ + test_bit_atomic_parallel_assign ## size(void) \ + { \ + unsigned int worker_lcore_id; \ + uint ## size ## _t word = 0; \ + struct parallel_access_lcore ## size lmain = { \ + .word = &word \ + }; \ + struct parallel_access_lcore ## size lworker = { \ + .word = &word \ + }; \ + \ + if (rte_lcore_count() < 2) { \ + printf("Need multiple cores to run parallel test.\n"); \ + return TEST_SKIPPED; \ + } \ + \ + worker_lcore_id = rte_get_next_lcore(-1, 1, 0); \ + \ + lmain.bit = rte_rand_max(size); \ + do { \ + lworker.bit = rte_rand_max(size); \ + } while (lworker.bit == lmain.bit); \ + \ + int rc = rte_eal_remote_launch(run_parallel_assign ## size, \ + &lworker, worker_lcore_id); \ + TEST_ASSERT(rc == 0, "Worker thread launch failed"); \ + \ + run_parallel_assign ## size(&lmain); \ + \ + rte_eal_mp_wait_lcore(); \ + \ + TEST_ASSERT(!lmain.failed, "Main lcore atomic access failed"); \ + TEST_ASSERT(!lworker.failed, "Worker lcore atomic access " \ + "failed"); \ + \ + return TEST_SUCCESS; \ + } + +GEN_TEST_BIT_PARALLEL_ASSIGN(32) +GEN_TEST_BIT_PARALLEL_ASSIGN(64) + +#define GEN_TEST_BIT_PARALLEL_TEST_AND_MODIFY(size) \ + \ + struct parallel_test_and_set_lcore ## size \ + { \ + uint ## size ##_t *word; \ + unsigned int bit; \ + uint64_t flips; \ + }; \ + \ + static int \ + run_parallel_test_and_modify ## size(void *arg) \ + { \ + struct parallel_test_and_set_lcore ## size *lcore = arg; \ + uint64_t deadline = rte_get_timer_cycles() + \ + PARALLEL_TEST_RUNTIME * rte_get_timer_hz(); \ + do { \ + bool old_value; \ + bool new_value = rte_rand() & 1; \ + bool use_assign = rte_rand() & 1; \ + \ + if (use_assign) \ + old_value = rte_bit_atomic_test_and_assign( \ + lcore->word, lcore->bit, new_value, \ + rte_memory_order_relaxed); \ + else \ + old_value = new_value ? \ + rte_bit_atomic_test_and_set( \ + lcore->word, lcore->bit, \ + rte_memory_order_relaxed) : \ + rte_bit_atomic_test_and_clear( \ + lcore->word, lcore->bit, \ + rte_memory_order_relaxed); \ + if (old_value != new_value) \ + lcore->flips++; \ + } while (rte_get_timer_cycles() < deadline); \ + \ + return 0; \ + } \ + \ + static int \ + test_bit_atomic_parallel_test_and_modify ## size(void) \ + { \ + unsigned int worker_lcore_id; \ + uint ## size ## _t word = 0; \ + unsigned int bit = rte_rand_max(size); \ + struct parallel_test_and_set_lcore ## size lmain = { \ + .word = &word, \ + .bit = bit \ + }; \ + struct parallel_test_and_set_lcore ## size lworker = { \ + .word = &word, \ + .bit = bit \ + }; \ + \ + if (rte_lcore_count() < 2) { \ + printf("Need multiple cores to run parallel test.\n"); \ + return TEST_SKIPPED; \ + } \ + \ + worker_lcore_id = rte_get_next_lcore(-1, 1, 0); \ + \ + int rc = rte_eal_remote_launch(run_parallel_test_and_modify ## size, \ + &lworker, worker_lcore_id); \ + TEST_ASSERT(rc == 0, "Worker thread launch failed"); \ + \ + run_parallel_test_and_modify ## size(&lmain); \ + \ + rte_eal_mp_wait_lcore(); \ + \ + uint64_t total_flips = lmain.flips + lworker.flips; \ + bool expected_value = total_flips % 2; \ + \ + TEST_ASSERT(expected_value == rte_bit_test(&word, bit), \ + "After %"PRId64" flips, the bit value " \ + "should be %d", total_flips, expected_value); \ + \ + uint64_t expected_word = 0; \ + rte_bit_assign(&expected_word, bit, expected_value); \ + \ + TEST_ASSERT(expected_word == word, "Untouched bits have " \ + "changed value"); \ + \ + return TEST_SUCCESS; \ + } + +GEN_TEST_BIT_PARALLEL_TEST_AND_MODIFY(32) +GEN_TEST_BIT_PARALLEL_TEST_AND_MODIFY(64) + +#define GEN_TEST_BIT_PARALLEL_FLIP(size) \ + \ + struct parallel_flip_lcore ## size \ + { \ + uint ## size ##_t *word; \ + unsigned int bit; \ + uint64_t flips; \ + }; \ + \ + static int \ + run_parallel_flip ## size(void *arg) \ + { \ + struct parallel_flip_lcore ## size *lcore = arg; \ + uint64_t deadline = rte_get_timer_cycles() + \ + PARALLEL_TEST_RUNTIME * rte_get_timer_hz(); \ + do { \ + rte_bit_atomic_flip(lcore->word, lcore->bit, \ + rte_memory_order_relaxed); \ + lcore->flips++; \ + } while (rte_get_timer_cycles() < deadline); \ + \ + return 0; \ + } \ + \ + static int \ + test_bit_atomic_parallel_flip ## size(void) \ + { \ + unsigned int worker_lcore_id; \ + uint ## size ## _t word = 0; \ + unsigned int bit = rte_rand_max(size); \ + struct parallel_flip_lcore ## size lmain = { \ + .word = &word, \ + .bit = bit \ + }; \ + struct parallel_flip_lcore ## size lworker = { \ + .word = &word, \ + .bit = bit \ + }; \ + \ + if (rte_lcore_count() < 2) { \ + printf("Need multiple cores to run parallel test.\n"); \ + return TEST_SKIPPED; \ + } \ + \ + worker_lcore_id = rte_get_next_lcore(-1, 1, 0); \ + \ + int rc = rte_eal_remote_launch(run_parallel_flip ## size, \ + &lworker, worker_lcore_id); \ + TEST_ASSERT(rc == 0, "Worker thread launch failed"); \ + \ + run_parallel_flip ## size(&lmain); \ + \ + rte_eal_mp_wait_lcore(); \ + \ + uint64_t total_flips = lmain.flips + lworker.flips; \ + bool expected_value = total_flips % 2; \ + \ + TEST_ASSERT(expected_value == rte_bit_test(&word, bit), \ + "After %"PRId64" flips, the bit value " \ + "should be %d", total_flips, expected_value); \ + \ + uint64_t expected_word = 0; \ + rte_bit_assign(&expected_word, bit, expected_value); \ + \ + TEST_ASSERT(expected_word == word, "Untouched bits have " \ + "changed value"); \ + \ + return TEST_SUCCESS; \ + } + +GEN_TEST_BIT_PARALLEL_FLIP(32) +GEN_TEST_BIT_PARALLEL_FLIP(64) + static uint32_t val32; static uint64_t val64; @@ -187,6 +488,18 @@ static struct unit_test_suite test_suite = { TEST_CASE(test_bit_access64), TEST_CASE(test_bit_once_access32), TEST_CASE(test_bit_once_access64), + TEST_CASE(test_bit_access32), + TEST_CASE(test_bit_access64), + TEST_CASE(test_bit_once_access32), + TEST_CASE(test_bit_once_access64), + TEST_CASE(test_bit_atomic_access32), + TEST_CASE(test_bit_atomic_access64), + TEST_CASE(test_bit_atomic_parallel_assign32), + TEST_CASE(test_bit_atomic_parallel_assign64), + TEST_CASE(test_bit_atomic_parallel_test_and_modify32), + TEST_CASE(test_bit_atomic_parallel_test_and_modify64), + TEST_CASE(test_bit_atomic_parallel_flip32), + TEST_CASE(test_bit_atomic_parallel_flip64), TEST_CASE(test_bit_relaxed_set), TEST_CASE(test_bit_relaxed_clear), TEST_CASE(test_bit_relaxed_test_set_clear),