From patchwork Wed Mar 20 07:23:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ma, WenwuX" X-Patchwork-Id: 138487 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 89A3443CFE; Wed, 20 Mar 2024 08:36:27 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6A09B40F1A; Wed, 20 Mar 2024 08:36:27 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by mails.dpdk.org (Postfix) with ESMTP id 26B11402A2; Wed, 20 Mar 2024 08:36:25 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1710920185; x=1742456185; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ayjyL3xPGgKlnU8q02oLgKhHgdvoXnOjclOhRTafxcU=; b=lfPWSNAnu9zfi0vkolmMzyqzhBplPTh2WaKXMwSPG0kmjQhhZ9WXvRbf qNvybkVei1jfhCUFXKckQaX1K3E75lVYGCjQeFKt4oKbf2HxSsy2KZ8VL GEechIizpvZidkTKoZwu+54FVpAzPZELoaQ7GdOmSUAvtXqfWrp8fBpct QRRAs6mD9c5243XwrlMS0bMg2ThvdwqTssYiqHA9V8tzvr/if1Q5LGBbx d9yRvykKWCjSAe1pmkp7u7cqzdSJZIh7na2UQmbFn0Py7/YwgwGCejsZz TI2f+rqIcWgEdUjyuRYzwI0v8+lhNEMWQD4zHyMcCoVY6GU76ao4xpJew Q==; X-IronPort-AV: E=McAfee;i="6600,9927,11018"; a="5664010" X-IronPort-AV: E=Sophos;i="6.07,139,1708416000"; d="scan'208";a="5664010" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Mar 2024 00:36:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,139,1708416000"; d="scan'208";a="18532723" Received: from unknown (HELO localhost.localdomain) ([10.239.252.55]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Mar 2024 00:36:22 -0700 From: Wenwu Ma To: dev@dpdk.org, fengchengwen@huawei.com Cc: songx.jiale@intel.com, Wenwu Ma , stable@dpdk.org Subject: [PATCH v3] dmadev: fix structure alignment Date: Wed, 20 Mar 2024 15:23:32 +0800 Message-Id: <20240320072332.1433526-1-wenwux.ma@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240308053711.1260154-1-wenwux.ma@intel.com> References: <20240308053711.1260154-1-wenwux.ma@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The structure rte_dma_dev needs to be aligned to the cache line, but the return value of malloc may not be aligned to the cache line. When we use memset to clear the rte_dma_dev object, it may cause a segmentation fault in clang-x86-platform. This is because clang uses the "vmovaps" assembly instruction for memset, which requires that the operands (rte_dma_dev objects) must aligned on a 16-byte boundary or a general-protection exception (#GP) is generated. Therefore, either additional memory is applied for re-alignment, or the rte_dma_dev object does not require cache line alignment. The patch chooses the former option to fix the issue. Fixes: b36970f2e13e ("dmadev: introduce DMA device library") Cc: stable@dpdk.org Signed-off-by: Wenwu Ma Reviewed-by: Chengwen Feng --- v2: - Because of performance drop, adjust the code to no longer demand cache line alignment v3: - back to v1 patch --- lib/dmadev/rte_dmadev.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/lib/dmadev/rte_dmadev.c b/lib/dmadev/rte_dmadev.c index 5953a77bd6..61e106d574 100644 --- a/lib/dmadev/rte_dmadev.c +++ b/lib/dmadev/rte_dmadev.c @@ -160,15 +160,25 @@ static int dma_dev_data_prepare(void) { size_t size; + void *ptr; if (rte_dma_devices != NULL) return 0; - size = dma_devices_max * sizeof(struct rte_dma_dev); - rte_dma_devices = malloc(size); - if (rte_dma_devices == NULL) + /* The dma device object is expected to align cacheline, but + * the return value of malloc may not be aligned to the cache line. + * Therefore, extra memory is applied for realignment. + * note: We do not call posix_memalign/aligned_alloc because it is + * version dependent on libc. + */ + size = dma_devices_max * sizeof(struct rte_dma_dev) + + RTE_CACHE_LINE_SIZE; + ptr = malloc(size); + if (ptr == NULL) return -ENOMEM; - memset(rte_dma_devices, 0, size); + memset(ptr, 0, size); + + rte_dma_devices = RTE_PTR_ALIGN(ptr, RTE_CACHE_LINE_SIZE); return 0; }