From patchwork Thu Mar 14 11:38:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 138379 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 98F0343CA5; Thu, 14 Mar 2024 12:38:47 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 24DD040297; Thu, 14 Mar 2024 12:38:47 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id C67EE4028C for ; Thu, 14 Mar 2024 12:38:45 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42DNMqR9016210; Thu, 14 Mar 2024 04:38:43 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; s= pfpt0220; bh=GlKTeQHY5IQ/jJIsxdPAXDBw0CAcwimMZmdFfP+cElw=; b=PGB hWcDacXjGLNnzICEWyiFqeYwbaBIjvFz21PaNZ18omzfgh7b/vxcd41BRIbnBd4j jPDv4BNwFaJPb09KUApbBvN7p2pQmX3xFrMWZ6gyoep9hHrksjQ1UUsvxSV2ZXO1 KmO1q4gYFl73zLwJy9dhx53/KpolHtyslZx4vTvbIrgNaA/k7qtItNprm/bamKnX zV/8YpOBLXxr0cj3FbjbLdFMIISyzSHPNeD57853oJNmO6Twn7B5Vh1sIO5BSf3n UOmNCu8C6PQHgyYZaiUyOPRLytRt40z+cX+4X0HxAbvZp0wRxEV366x5CV2NjvfL pRWP1WGErEYgDnii48g== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3wucg2vn7x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Mar 2024 04:38:42 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 14 Mar 2024 04:38:42 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 14 Mar 2024 04:38:41 -0700 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id A3AC73F7068; Thu, 14 Mar 2024 04:38:38 -0700 (PDT) From: To: , , , , Ruifeng Wang , "Bruce Richardson" CC: , Pavan Nikhilesh Subject: [PATCH v8 1/5] config/arm: avoid mcpu and march conflicts Date: Thu, 14 Mar 2024 17:08:25 +0530 Message-ID: <20240314113829.2511-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240306154957.750-1-pbhagavatula@marvell.com> References: <20240306154957.750-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 7EmulXlil6HzoxQm58ih0sRh4KvltMus X-Proofpoint-GUID: 7EmulXlil6HzoxQm58ih0sRh4KvltMus X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-14_10,2024-03-13_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh The compiler options march and mtune are a subset of mcpu and will lead to conflicts if improper march is chosen for a given mcpu. To avoid conflicts, discard part number march when mcpu is available and is supported by the compiler. Example: march = armv9-a mcpu = neoverse-n2 mcpu supported, march supported machine_args = ['-mcpu=neoverse-n2'] mcpu supported, march not supported machine_args = ['-mcpu=neoverse-n2'] mcpu not supported, march supported machine_args = ['-march=armv9-a'] mcpu not supported, march not supported machine_args = ['-march=armv8.6-a'] Signed-off-by: Pavan Nikhilesh Reviewed-by: Juraj Linkeš --- v2 Changes: - Cleanup march inconsistencies. (Juraj Linkes) - Unify fallback march selection. (Juraj Linkes) - Tag along ARM WFE patch. v3 Changes: - Fix missing 'fallback_march' key check. v4 Changes: - Discard march when mcpu is supported. v5 Changes: - Consolidate mcpu and march checks. (Juraj Linkes) - Fix unintentionally skipping fallback march (Juraj Linkes) v6 Changes: - Remove compiler support check when march is forced. (Juraj Linkes) - Simplify fallback march configuration. v7 Changes: - Rebase on master. v8 Changes: - Split patches to be more explicit about changes. config/arm/meson.build | 115 ++++++++++++++++++++++++----------------- 1 file changed, 69 insertions(+), 46 deletions(-) -- 2.25.1 diff --git a/config/arm/meson.build b/config/arm/meson.build index 9d6fb87d7f..4e7e072053 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -58,18 +58,18 @@ implementer_generic = { } part_number_config_arm = { - '0xd03': {'compiler_options': ['-mcpu=cortex-a53']}, - '0xd04': {'compiler_options': ['-mcpu=cortex-a35']}, - '0xd05': {'compiler_options': ['-mcpu=cortex-a55']}, - '0xd07': {'compiler_options': ['-mcpu=cortex-a57']}, - '0xd08': {'compiler_options': ['-mcpu=cortex-a72']}, - '0xd09': {'compiler_options': ['-mcpu=cortex-a73']}, - '0xd0a': {'compiler_options': ['-mcpu=cortex-a75']}, - '0xd0b': {'compiler_options': ['-mcpu=cortex-a76']}, + '0xd03': {'mcpu': 'cortex-a53'}, + '0xd04': {'mcpu': 'cortex-a35'}, + '0xd05': {'mcpu': 'cortex-a55'}, + '0xd07': {'mcpu': 'cortex-a57'}, + '0xd08': {'mcpu': 'cortex-a72'}, + '0xd09': {'mcpu': 'cortex-a73'}, + '0xd0a': {'mcpu': 'cortex-a75'}, + '0xd0b': {'mcpu': 'cortex-a76'}, '0xd0c': { 'march': 'armv8.2-a', 'march_features': ['crypto', 'rcpc'], - 'compiler_options': ['-mcpu=neoverse-n1'], + 'mcpu': 'neoverse-n1', 'flags': [ ['RTE_MACHINE', '"neoverse-n1"'], ['RTE_ARM_FEATURE_ATOMICS', true], @@ -81,7 +81,7 @@ part_number_config_arm = { '0xd40': { 'march': 'armv8.4-a', 'march_features': ['sve'], - 'compiler_options': ['-mcpu=neoverse-v1'], + 'mcpu': 'neoverse-v1', 'flags': [ ['RTE_MACHINE', '"neoverse-v1"'], ['RTE_ARM_FEATURE_ATOMICS', true], @@ -93,7 +93,7 @@ part_number_config_arm = { }, '0xd49': { 'march_features': ['sve2'], - 'compiler_options': ['-mcpu=neoverse-n2'], + 'mcpu': 'neoverse-n2', 'flags': [ ['RTE_MACHINE', '"neoverse-n2"'], ['RTE_ARM_FEATURE_ATOMICS', true], @@ -103,7 +103,7 @@ part_number_config_arm = { }, '0xd4f': { 'march_features': ['sve2'], - 'compiler_options': ['-mcpu=neoverse-v2'], + 'mcpu' : 'neoverse-v2', 'flags': [ ['RTE_MACHINE', '"neoverse-v2"'], ['RTE_ARM_FEATURE_ATOMICS', true], @@ -137,21 +137,23 @@ implementer_cavium = { ], 'part_number_config': { '0xa1': { - 'compiler_options': ['-mcpu=thunderxt88'], + 'mcpu': 'thunderxt88', 'flags': flags_part_number_thunderx }, '0xa2': { - 'compiler_options': ['-mcpu=thunderxt81'], + 'mcpu': 'thunderxt81', 'flags': flags_part_number_thunderx }, '0xa3': { - 'compiler_options': ['-march=armv8-a+crc', '-mcpu=thunderxt83'], + 'march': 'armv8-a', + 'march_features': ['crc'], + 'mcpu': 'thunderxt83', 'flags': flags_part_number_thunderx }, '0xaf': { 'march': 'armv8.1-a', 'march_features': ['crc', 'crypto'], - 'compiler_options': ['-mcpu=thunderx2t99'], + 'mcpu': 'thunderx2t99', 'flags': [ ['RTE_MACHINE', '"thunderx2"'], ['RTE_ARM_FEATURE_ATOMICS', true], @@ -163,7 +165,7 @@ implementer_cavium = { '0xb2': { 'march': 'armv8.2-a', 'march_features': ['crc', 'crypto', 'lse'], - 'compiler_options': ['-mcpu=octeontx2'], + 'mcpu': 'octeontx2', 'flags': [ ['RTE_MACHINE', '"cn9k"'], ['RTE_ARM_FEATURE_ATOMICS', true], @@ -186,7 +188,7 @@ implementer_ampere = { '0x0': { 'march': 'armv8-a', 'march_features': ['crc', 'crypto'], - 'compiler_options': ['-mtune=emag'], + 'mcpu': 'emag', 'flags': [ ['RTE_MACHINE', '"eMAG"'], ['RTE_MAX_LCORE', 32], @@ -196,7 +198,7 @@ implementer_ampere = { '0xac3': { 'march': 'armv8.6-a', 'march_features': ['crc', 'crypto'], - 'compiler_options': ['-mcpu=ampere1'], + 'mcpu': 'ampere1', 'flags': [ ['RTE_MACHINE', '"AmpereOne"'], ['RTE_MAX_LCORE', 320], @@ -216,7 +218,7 @@ implementer_hisilicon = { '0xd01': { 'march': 'armv8.2-a', 'march_features': ['crypto'], - 'compiler_options': ['-mtune=tsv110'], + 'mcpu': 'tsv110', 'flags': [ ['RTE_MACHINE', '"Kunpeng 920"'], ['RTE_ARM_FEATURE_ATOMICS', true], @@ -258,14 +260,14 @@ implementer_ionic = { ], 'part_number_config': { '0xc1': { - 'compiler_options': ['-mcpu=cortex-a72'], + 'mcpu' : 'cortex-a72', 'flags': [ ['RTE_MAX_LCORE', 4], ['RTE_LIBRTE_IONIC_PMD_BARRIER_ERRATA', true], ] }, '0xc2': { - 'compiler_options': ['-mcpu=cortex-a72'], + 'mcpu' : 'cortex-a72', 'flags': [ ['RTE_MAX_LCORE', 16], ['RTE_LIBRTE_IONIC_PMD_BARRIER_ERRATA', true], @@ -797,9 +799,31 @@ if update_flags machine_args = [] # Clear previous machine args - # probe supported archs and their features + march_features = [] + if part_number_config.has_key('march_features') + march_features += part_number_config['march_features'] + endif + if soc_config.has_key('extra_march_features') + march_features += soc_config['extra_march_features'] + endif + + candidate_mcpu = '' candidate_march = '' - if part_number_config.has_key('march') + + if (part_number_config.has_key('mcpu') and + cc.has_argument('-mcpu=' + part_number_config['mcpu'])) + candidate_mcpu = '-mcpu=' + part_number_config['mcpu'] + foreach feature: march_features + if cc.has_argument('+'.join([candidate_mcpu, feature])) + candidate_mcpu = '+'.join([candidate_mcpu, feature]) + else + warning('The compiler does not support feature @0@' + .format(feature)) + endif + endforeach + machine_args += candidate_mcpu + elif part_number_config.has_key('march') + # probe supported archs and their features if part_number_config.get('force_march', false) candidate_march = part_number_config['march'] else @@ -819,32 +843,31 @@ if update_flags endif endforeach endif - if candidate_march == '' - error('No suitable armv8 march version found.') - endif + if candidate_march != part_number_config['march'] - warning('Configuration march version is ' + - '@0@, but the compiler supports only @1@.' - .format(part_number_config['march'], candidate_march)) + warning('Configuration march version is @0@, not supported.' + .format(part_number_config['march'])) + if candidate_march != '' + warning('Using march version @0@.'.format(candidate_march)) + endif endif - candidate_march = '-march=' + candidate_march - march_features = [] - if part_number_config.has_key('march_features') - march_features += part_number_config['march_features'] - endif - if soc_config.has_key('extra_march_features') - march_features += soc_config['extra_march_features'] + if candidate_march != '' + candidate_march = '-march=' + candidate_march + foreach feature: march_features + if cc.has_argument('+'.join([candidate_march, feature])) + candidate_march = '+'.join([candidate_march, feature]) + else + warning('The compiler does not support feature @0@' + .format(feature)) + endif + endforeach + machine_args += candidate_march endif - foreach feature: march_features - if cc.has_argument('+'.join([candidate_march, feature])) - candidate_march = '+'.join([candidate_march, feature]) - else - warning('The compiler does not support feature @0@' - .format(feature)) - endif - endforeach - machine_args += candidate_march + endif + + if candidate_mcpu == '' and candidate_march == '' + error('No suitable ARM march/mcpu version found.') endif # apply supported compiler options From patchwork Thu Mar 14 11:38:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 138381 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1087943CA5; Thu, 14 Mar 2024 12:39:16 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0D62342E93; Thu, 14 Mar 2024 12:39:13 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id A53B042E7E for ; Thu, 14 Mar 2024 12:39:09 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42E5JIS5011171; Thu, 14 Mar 2024 04:39:06 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=UGqwfqKwzKaWTcxJ6Lh7zlpt8xJ886X+G8vuMgHEG1A=; b=g+U 7906M9RzOzBawrYYd3vTOlKjDcc+BmEsL1MR77JXmser55UL8UiVWLtQRJOP0HKD zq91f4NzsbRNt7CydP+zrq3hAhWX3uNH+GajJhNPgTduXKbMn4azXHIAA7bhE5Tq 7CuAz54yoiVDXilc1/q8DWkEohxhdB6eOXyH4oYTADDQ1V0uUbSGeCsiuTQmfU5q hb8qxri78EsXZIR8EZB5uRqXEPXbn+hPIo2oZ7f3Yu/+rkYsJIwy+Sf4Lg6HN5vl TplqqKxfNurhRUmQ3R1iY1SYT+6oioyLkMrH26525gnOfdP8Mik4fav5IkXwpJeq zzWCmMifz2RY/MPtSJg== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3wutyq9agp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Mar 2024 04:39:05 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 14 Mar 2024 04:38:45 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 14 Mar 2024 04:38:45 -0700 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id D14363F7067; Thu, 14 Mar 2024 04:38:41 -0700 (PDT) From: To: , , , , Ruifeng Wang , "Bruce Richardson" CC: , Pavan Nikhilesh Subject: [PATCH v8 2/5] config/arm: add armv9-a march support Date: Thu, 14 Mar 2024 17:08:26 +0530 Message-ID: <20240314113829.2511-2-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240314113829.2511-1-pbhagavatula@marvell.com> References: <20240306154957.750-1-pbhagavatula@marvell.com> <20240314113829.2511-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: h-76wZiUctrL4u71zNHVVvh7s-0xqOen X-Proofpoint-ORIG-GUID: h-76wZiUctrL4u71zNHVVvh7s-0xqOen X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-14_10,2024-03-13_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Add armv9-a as supported march flag for ARM neoverse class of processors. Update supported march list to include armv9-a. Signed-off-by: Pavan Nikhilesh --- config/arm/meson.build | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index 4e7e072053..0e7f54862a 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -92,6 +92,7 @@ part_number_config_arm = { 'march': 'armv8.4-a', }, '0xd49': { + 'march': 'armv9-a', 'march_features': ['sve2'], 'mcpu': 'neoverse-n2', 'flags': [ @@ -102,6 +103,7 @@ part_number_config_arm = { ] }, '0xd4f': { + 'march': 'armv9-a', 'march_features': ['sve2'], 'mcpu' : 'neoverse-v2', 'flags': [ @@ -827,7 +829,7 @@ if update_flags if part_number_config.get('force_march', false) candidate_march = part_number_config['march'] else - supported_marchs = ['armv8.6-a', 'armv8.5-a', 'armv8.4-a', 'armv8.3-a', + supported_marchs = ['armv9-a', 'armv8.6-a', 'armv8.5-a', 'armv8.4-a', 'armv8.3-a', 'armv8.2-a', 'armv8.1-a', 'armv8-a'] check_compiler_support = false foreach supported_march: supported_marchs From patchwork Thu Mar 14 11:38:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 138380 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0FE7443CA5; Thu, 14 Mar 2024 12:39:12 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F12B942E7E; Thu, 14 Mar 2024 12:39:11 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 89E1B42E7C for ; Thu, 14 Mar 2024 12:39:09 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42E5IRNJ010148; Thu, 14 Mar 2024 04:39:05 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=/FjdMWs9YMF6tHW27RpGrtwBCIFGfC67/D9xDWBchr8=; b=VpN xNcGRXB3zcsFYHdeY8JCwq0QeSG4j908AlLR27kBmrmIwkuUv+mJjhX5VtH1P03p Lh6GmPxWfMheCntJ0xXbyax1w1hpDGoLc/3i/NbnQnaSOBDSq9wuT9fdzTjorpLB UG6d6f12tHBxT2xV8bWKHgz0p1YMAe62AOpc92ibI3TAVsb3jmKiXq7xEkoQ7R4Z I9N6Xka2mt8/veLvzsrawHgdhFBSXmArklPz5d9ogrOApK6F5hTEe6kIUmb/kV2D 6AkX07Hb58SOSdPzKKrfnsHdI5zfeRgwLUXf7Vf6E2eqnoZKm/FurKKtqHDlkTGX o+s+LqoHp7vIwOXd4SQ== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3wutyq9agu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Mar 2024 04:39:05 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 14 Mar 2024 04:38:48 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 14 Mar 2024 04:38:48 -0700 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id 0C3963F7051; Thu, 14 Mar 2024 04:38:44 -0700 (PDT) From: To: , , , , Ruifeng Wang , "Bruce Richardson" CC: , Pavan Nikhilesh Subject: [PATCH v8 3/5] config/arm: add crypto march feature to thunderxt83 Date: Thu, 14 Mar 2024 17:08:27 +0530 Message-ID: <20240314113829.2511-3-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240314113829.2511-1-pbhagavatula@marvell.com> References: <20240306154957.750-1-pbhagavatula@marvell.com> <20240314113829.2511-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: U9sVbBoOCTpe_rCKfWL_j68qnxiU-Nmm X-Proofpoint-ORIG-GUID: U9sVbBoOCTpe_rCKfWL_j68qnxiU-Nmm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-14_10,2024-03-13_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Some older compilers don't recognize crypto march feature for thunderxt83 mcpu. Explicitly add it to march feature list. Signed-off-by: Pavan Nikhilesh Acked-by: Jerin Jacob --- config/arm/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index 0e7f54862a..45f5db2c58 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -148,7 +148,7 @@ implementer_cavium = { }, '0xa3': { 'march': 'armv8-a', - 'march_features': ['crc'], + 'march_features': ['crc', 'crypto'], 'mcpu': 'thunderxt83', 'flags': flags_part_number_thunderx }, From patchwork Thu Mar 14 11:38:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 138382 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0744143CA5; Thu, 14 Mar 2024 12:39:22 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6592F42E9C; Thu, 14 Mar 2024 12:39:14 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 7E21542E7C for ; Thu, 14 Mar 2024 12:39:10 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42E5JIS6011171; Thu, 14 Mar 2024 04:39:06 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; s= pfpt0220; bh=7XdPwMDDPTXdMnZ/La+4qmEajqp3cVVIThUlf37gMy0=; b=a8j +oNVFjmUvpVNoVfUHEIljq9D2gbaMpPTXiGsauB8yUI9RALUgu7Zb52ZVX9mOIc6 ARKlNH/GrkbTiWanG0kr/UhmW9wPGA9H5vhwJA0hOedYp3OdNvz2V9QJM902Lhsv FQG+GiuIb3FeFxaE2kckX4yXxysyMNAqLEDatEiNFUYdM8nfwqeTz14tB1fKOe9w aEMf6qnu/5XcABUVIyq0I88NBJbY6YOxHTgTBCc0JFRgbEoY6yWERIFk0+1OhDY8 BGHKckIhp0aKHS/OGA3eJyDDleqscpFxRfQt4AW2Xt2ghxOdshrDQmVMwpbnx+Rs +YajlxsQWrBnQ1bl04g== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3wutyq9agp-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Mar 2024 04:39:06 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 14 Mar 2024 04:38:51 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 14 Mar 2024 04:38:51 -0700 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id 507D43F7051; Thu, 14 Mar 2024 04:38:48 -0700 (PDT) From: To: , , , , Ruifeng Wang , "Bruce Richardson" CC: , Pavan Nikhilesh Subject: [PATCH v8 4/5] config/arm: add support for fallback march Date: Thu, 14 Mar 2024 17:08:28 +0530 Message-ID: <20240314113829.2511-4-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240314113829.2511-1-pbhagavatula@marvell.com> References: <20240306154957.750-1-pbhagavatula@marvell.com> <20240314113829.2511-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: rEsRHKFVMkFTV3KDjS6T_ChOGNrgha1k X-Proofpoint-ORIG-GUID: rEsRHKFVMkFTV3KDjS6T_ChOGNrgha1k X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-14_10,2024-03-13_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Some ARM CPUs have specific march requirements and are not compatible with the supported march list. Add fallback march in case the mcpu and the march advertised in the part_number_config are not supported by the compiler. Example mcpu = neoverse-n2 march = armv9-a fallback_march = armv8.5-a mcpu, march not supported machine_args = ['-march=armv8.5-a'] mcpu, march, fallback_march not supported least march supported = armv8-a machine_args = ['-march=armv8-a'] Signed-off-by: Pavan Nikhilesh Reviewed-by: Juraj Linkeš --- config/arm/meson.build | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/config/arm/meson.build b/config/arm/meson.build index 45f5db2c58..fd38031308 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -94,6 +94,7 @@ part_number_config_arm = { '0xd49': { 'march': 'armv9-a', 'march_features': ['sve2'], + 'fallback_march': 'armv8.5-a', 'mcpu': 'neoverse-n2', 'flags': [ ['RTE_MACHINE', '"neoverse-n2"'], @@ -844,6 +845,11 @@ if update_flags break endif endforeach + if (part_number_config.has_key('fallback_march') and + candidate_march != part_number_config['march'] and + cc.has_argument('-march=' + part_number_config['fallback_march'])) + candidate_march = part_number_config['fallback_march'] + endif endif if candidate_march != part_number_config['march'] From patchwork Thu Mar 14 11:38:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 138383 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7386943CA5; Thu, 14 Mar 2024 12:39:27 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F06ED42EA1; Thu, 14 Mar 2024 12:39:15 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 5160B42E7C for ; Thu, 14 Mar 2024 12:39:11 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42E5JIS7011171; Thu, 14 Mar 2024 04:39:07 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=lC24GiWW7NchBe/Xb5qMsLX7WKN6YlQHJiAFVv072QE=; b=k+A leAOelQo5tuLp2mwhgo8B4GSJgl6LdyPZ/o2ys3JDbBGqTQ8ydMj/G/k7RzA8HwP hylIkE0P36WJ+e8Xc3KStiib7l+q/ZqrYM5PBGGPKonndlMNE8EK09kVjqoHnP9D FeAphOqotsGsS9rD0kLeIpyhIq7524kwNPDcmtiwXqoqnuhAJEuHL5ilsxcDkGaw SamqEtP6Bu81WUxnYUoxqbcW2KbGG4kRIp3HMNs7M/oRa6vynlHdUnbABCeRF6Zw XKFRha8bnQebeeXh0Iv0reFpLcPuATa8Pj5tl2Y7jn3L+DqIFk5CxplxFI7V9lzg b5Yi69l3ahJhRhyZ+rg== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3wutyq9agp-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Mar 2024 04:39:07 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 14 Mar 2024 04:38:55 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 14 Mar 2024 04:38:55 -0700 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id 8FDFA3F7051; Thu, 14 Mar 2024 04:38:51 -0700 (PDT) From: To: , , , , Ruifeng Wang , "Bruce Richardson" CC: , Pavan Nikhilesh , Chengwen Feng , Honnappa Nagarahalli Subject: [PATCH v8 5/5] config/arm: allow WFE to be enabled config time Date: Thu, 14 Mar 2024 17:08:29 +0530 Message-ID: <20240314113829.2511-5-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240314113829.2511-1-pbhagavatula@marvell.com> References: <20240306154957.750-1-pbhagavatula@marvell.com> <20240314113829.2511-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: YF7ZNBgi1br-XKMeGgz_9pwIWEfKd2wB X-Proofpoint-ORIG-GUID: YF7ZNBgi1br-XKMeGgz_9pwIWEfKd2wB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-14_10,2024-03-13_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Allow RTE_ARM_USE_WFE to be enabled at meson configuration time by passing it via c_args instead of modifying `config/arm/meson.build`. Example usage: meson build -Dc_args='-DRTE_ARM_USE_WFE' \ --cross-file config/arm/arm64_cn10k_linux_gcc Signed-off-by: Pavan Nikhilesh Acked-by: Chengwen Feng Acked-by: Ruifeng Wang Reviewed-by: Honnappa Nagarahalli Reviewed-by: Wathsala Vithanage --- config/arm/meson.build | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index fd38031308..883e668c1a 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -17,7 +17,9 @@ flags_common = [ # ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF], # ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false], - ['RTE_ARM_USE_WFE', false], + # Enable use of ARM wait for event instruction. + # ['RTE_ARM_USE_WFE', false], + ['RTE_ARCH_ARM64', true], ['RTE_CACHE_LINE_SIZE', 128] ]