From patchwork Mon Mar 4 09:52:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satha Koteswara Rao Kottidi X-Patchwork-Id: 137878 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4AE7843B7C; Mon, 4 Mar 2024 10:52:59 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 37A4240271; Mon, 4 Mar 2024 10:52:59 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id DB37F400D7 for ; Mon, 4 Mar 2024 10:52:57 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 4245ROI3026997 for ; Mon, 4 Mar 2024 01:52:57 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=pfpt0220; bh=rGOgYI92LUkypmXuIN2Xn Y9SGUFblWMT4NA17EiIZN4=; b=BH2DoolujXZ8pJjmQg6SrP+0wksR9FzpN1SGf y0N/kFCyp2mSYs8SkRiU/vlNueXvZ4ryfanmidkkFjhrnzANQOwYcnfZLw2Pkecv 9DBLpKbGlvGWbXBQw5MfIoeSD3SRasy2Om17u4iJ+TdTFxmQZC59SwvBze1u1KJr EYyM5DNJ2Ri2ReyDM5ZP8LshCDEsvg7Hpk9C7SsR/lOUMlvuc6WuMC5/GhqzIL4x WXwpU+Utu6NiZ0oKIz9qDH2E0mm9rB0sn+jyyDXhLjbowvRt5NsCPEbXV5I6ccXc PtfhBDduO7KN2oO0acpQa5iIN3rF9d3pn+I4OV3EXuXZoLA6Q== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3wn85xgpu8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 04 Mar 2024 01:52:56 -0800 (PST) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 4 Mar 2024 01:52:55 -0800 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 4 Mar 2024 01:52:55 -0800 Received: from Cavium-PET630-BM22.localdomain (unknown [10.28.34.26]) by maili.marvell.com (Postfix) with ESMTP id 4B3253F704C; Mon, 4 Mar 2024 01:52:53 -0800 (PST) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: Subject: [PATCH v6] net/cnxk: support Tx queue descriptor count Date: Mon, 4 Mar 2024 04:52:51 -0500 Message-ID: <1709545971-17364-1-git-send-email-skoteshwar@marvell.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1709286509-18322-1-git-send-email-skoteshwar@marvell.com> References: <1709286509-18322-1-git-send-email-skoteshwar@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: LhQIhRhEIpDyXdx58DRVTz_9fQ553bn9 X-Proofpoint-GUID: LhQIhRhEIpDyXdx58DRVTz_9fQ553bn9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-04_06,2024-03-01_03,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Satha Rao Added CNXK APIs to get used txq descriptor count. Signed-off-by: Satha Rao --- Depends-on: series-30833 ("ethdev: support Tx queue used count") v2: Updated release notes and fixed API for CPT queues. v3: Addressed review comments v5: Fixed compilation errors v6: Fixed checkpatch doc/guides/nics/features/cnxk.ini | 1 + doc/guides/rel_notes/release_24_03.rst | 1 + drivers/net/cnxk/cn10k_tx_select.c | 22 ++++++++++++++++++++++ drivers/net/cnxk/cn9k_tx_select.c | 23 +++++++++++++++++++++++ drivers/net/cnxk/cnxk_ethdev.h | 25 +++++++++++++++++++++++++ 5 files changed, 72 insertions(+) diff --git a/doc/guides/nics/features/cnxk.ini b/doc/guides/nics/features/cnxk.ini index b5d9f7e..1c8db1a 100644 --- a/doc/guides/nics/features/cnxk.ini +++ b/doc/guides/nics/features/cnxk.ini @@ -40,6 +40,7 @@ Timesync = Y Timestamp offload = Y Rx descriptor status = Y Tx descriptor status = Y +Tx queue count = Y Basic stats = Y Stats per queue = Y Extended stats = Y diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst index 2b160cf..b1942b5 100644 --- a/doc/guides/rel_notes/release_24_03.rst +++ b/doc/guides/rel_notes/release_24_03.rst @@ -113,6 +113,7 @@ New Features * Added support for Rx inject. * Optimized SW external mbuf free for better performance and avoid SQ corruption. * Added support for port representors. + * Added support for ``rte_eth_tx_queue_count``. * **Updated Marvell OCTEON EP driver.** diff --git a/drivers/net/cnxk/cn10k_tx_select.c b/drivers/net/cnxk/cn10k_tx_select.c index 404f5ba..aa0620e 100644 --- a/drivers/net/cnxk/cn10k_tx_select.c +++ b/drivers/net/cnxk/cn10k_tx_select.c @@ -20,6 +20,24 @@ eth_dev->tx_pkt_burst; } +#if defined(RTE_ARCH_ARM64) +static int +cn10k_nix_tx_queue_count(void *tx_queue) +{ + struct cn10k_eth_txq *txq = (struct cn10k_eth_txq *)tx_queue; + + return cnxk_nix_tx_queue_count(txq->fc_mem, txq->sqes_per_sqb_log2); +} + +static int +cn10k_nix_tx_queue_sec_count(void *tx_queue) +{ + struct cn10k_eth_txq *txq = (struct cn10k_eth_txq *)tx_queue; + + return cnxk_nix_tx_queue_sec_count(txq->fc_mem, txq->sqes_per_sqb_log2, txq->cpt_fc); +} +#endif + void cn10k_eth_set_tx_function(struct rte_eth_dev *eth_dev) { @@ -63,6 +81,10 @@ if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_MULTI_SEGS) pick_tx_func(eth_dev, nix_eth_tx_vec_burst_mseg); } + if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY) + eth_dev->tx_queue_count = cn10k_nix_tx_queue_sec_count; + else + eth_dev->tx_queue_count = cn10k_nix_tx_queue_count; rte_mb(); #else diff --git a/drivers/net/cnxk/cn9k_tx_select.c b/drivers/net/cnxk/cn9k_tx_select.c index e08883f..5ecf919 100644 --- a/drivers/net/cnxk/cn9k_tx_select.c +++ b/drivers/net/cnxk/cn9k_tx_select.c @@ -20,6 +20,24 @@ eth_dev->tx_pkt_burst; } +#if defined(RTE_ARCH_ARM64) +static int +cn9k_nix_tx_queue_count(void *tx_queue) +{ + struct cn9k_eth_txq *txq = (struct cn9k_eth_txq *)tx_queue; + + return cnxk_nix_tx_queue_count(txq->fc_mem, txq->sqes_per_sqb_log2); +} + +static int +cn9k_nix_tx_queue_sec_count(void *tx_queue) +{ + struct cn9k_eth_txq *txq = (struct cn9k_eth_txq *)tx_queue; + + return cnxk_nix_tx_queue_sec_count(txq->fc_mem, txq->sqes_per_sqb_log2, txq->cpt_fc); +} +#endif + void cn9k_eth_set_tx_function(struct rte_eth_dev *eth_dev) { @@ -59,6 +77,11 @@ if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_MULTI_SEGS) pick_tx_func(eth_dev, nix_eth_tx_vec_burst_mseg); } + if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY) + eth_dev->tx_queue_count = cn9k_nix_tx_queue_sec_count; + else + eth_dev->tx_queue_count = cn9k_nix_tx_queue_count; + rte_mb(); #else diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index 5d42e13..5e04064 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -464,6 +464,31 @@ struct cnxk_eth_txq_sp { return ((struct cnxk_eth_txq_sp *)__txq) - 1; } +static inline int +cnxk_nix_tx_queue_count(uint64_t *mem, uint16_t sqes_per_sqb_log2) +{ + uint64_t val; + + val = rte_atomic_load_explicit((RTE_ATOMIC(uint64_t)*)mem, rte_memory_order_relaxed); + val = (val << sqes_per_sqb_log2) - val; + + return (val & 0xFFFF); +} + +static inline int +cnxk_nix_tx_queue_sec_count(uint64_t *mem, uint16_t sqes_per_sqb_log2, uint64_t *sec_fc) +{ + uint64_t sq_cnt, sec_cnt, val; + + sq_cnt = rte_atomic_load_explicit((RTE_ATOMIC(uint64_t)*)mem, rte_memory_order_relaxed); + sq_cnt = (sq_cnt << sqes_per_sqb_log2) - sq_cnt; + sec_cnt = rte_atomic_load_explicit((RTE_ATOMIC(uint64_t)*)sec_fc, + rte_memory_order_relaxed); + val = RTE_MAX(sq_cnt, sec_cnt); + + return (val & 0xFFFF); +} + /* Common ethdev ops */ extern struct eth_dev_ops cnxk_eth_dev_ops;