From patchwork Mon Feb 26 07:38:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 137189 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0A0DA43BE5; Mon, 26 Feb 2024 08:38:27 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 835C1402BA; Mon, 26 Feb 2024 08:38:26 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 5E3AA40144 for ; Mon, 26 Feb 2024 08:38:24 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41Q6jjgr008783; Sun, 25 Feb 2024 23:38:20 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; s= pfpt0220; bh=ModVPXt1Wua8TtbGFtTR9Hd0c2ZAFoU3T98wcyRAQSQ=; b=NcW w1pVeqHEmlqoHDABeeTcrtMJTjSv3TZ+ZvnOvunSl4ruXIsKPiKTroAPOAQ/GVZl MmHggrokR9Ip7CJsydOT9e7gGdYQii/rBQ4F7NoumvBCg4X/SX5yxfWDVUcImpHN 3iEoAJ4CU1+SfGYKzuO08a5zXqcpCPKJlUi5eXnlGz2sPg1xi3K54RFpO082gXjW w3htmPKoVEJljiVmk7DWfCY1PQ0tof7+shTJthn6XwK8bTyV9dSoa8VH52O65BXI A94Wll9W6m5rR2YcaDPvm595Bk7zUepEATbB+yD1Wn30Ms/8UqL66nU+HKZSpWCa d+ZbDZt5HzsEBq+oKJA== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3wfepr4dtd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 25 Feb 2024 23:38:20 -0800 (PST) Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.1258.12; Sun, 25 Feb 2024 23:38:19 -0800 Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Sun, 25 Feb 2024 23:38:18 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Sun, 25 Feb 2024 23:38:18 -0800 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id 199BF3F7080; Sun, 25 Feb 2024 23:38:14 -0800 (PST) From: To: , , , , Ruifeng Wang , "Bruce Richardson" CC: , Pavan Nikhilesh Subject: [PATCH v6 1/3] config/arm: avoid mcpu and march conflicts Date: Mon, 26 Feb 2024 13:08:08 +0530 Message-ID: <20240226073810.19015-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240222124503.17043-1-pbhagavatula@marvell.com> References: <20240222124503.17043-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: lSyX5CoFgolE1F8lNMlBDaLEluOaP0uH X-Proofpoint-GUID: lSyX5CoFgolE1F8lNMlBDaLEluOaP0uH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-26_04,2024-02-23_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh The compiler options march and mtune are a subset of mcpu and will lead to conflicts if improper march is chosen for a given mcpu. To avoid conflicts, discard part number march when mcpu is available and is supported by the compiler. Example: march = armv9-a mcpu = neoverse-n2 mcpu supported, march supported machine_args = ['-mcpu=neoverse-n2'] mcpu supported, march not supported machine_args = ['-mcpu=neoverse-n2'] mcpu not supported, march supported machine_args = ['-march=armv9-a'] mcpu not supported, march not supported machine_args = ['-march=armv8.6-a'] Signed-off-by: Pavan Nikhilesh Reviewed-by: Juraj Linkeš --- v2 Changes: - Cleanup march inconsistencies. (Juraj Linkes) - Unify fallback march selection. (Juraj Linkes) - Tag along ARM WFE patch. v3 Changes: - Fix missing 'fallback_march' key check. v4 Changes: - Discard march when mcpu is supported. v5 Changes: - Consolidate mcpu and march checks. (Juraj Linkes) - Fix unintentionally skipping fallback march (Juraj Linkes) v6 Changes: - Remove compiler support check when march is forced. (Juraj Linkes) - Simplify fallback march configuration. config/arm/meson.build | 112 +++++++++++++++++++++++++---------------- 1 file changed, 68 insertions(+), 44 deletions(-) -- 2.25.1 diff --git a/config/arm/meson.build b/config/arm/meson.build index 36f21d2259..236ad3702d 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -58,18 +58,18 @@ implementer_generic = { } part_number_config_arm = { - '0xd03': {'compiler_options': ['-mcpu=cortex-a53']}, - '0xd04': {'compiler_options': ['-mcpu=cortex-a35']}, - '0xd05': {'compiler_options': ['-mcpu=cortex-a55']}, - '0xd07': {'compiler_options': ['-mcpu=cortex-a57']}, - '0xd08': {'compiler_options': ['-mcpu=cortex-a72']}, - '0xd09': {'compiler_options': ['-mcpu=cortex-a73']}, - '0xd0a': {'compiler_options': ['-mcpu=cortex-a75']}, - '0xd0b': {'compiler_options': ['-mcpu=cortex-a76']}, + '0xd03': {'mcpu': 'cortex-a53'}, + '0xd04': {'mcpu': 'cortex-a35'}, + '0xd05': {'mcpu': 'cortex-a55'}, + '0xd07': {'mcpu': 'cortex-a57'}, + '0xd08': {'mcpu': 'cortex-a72'}, + '0xd09': {'mcpu': 'cortex-a73'}, + '0xd0a': {'mcpu': 'cortex-a75'}, + '0xd0b': {'mcpu': 'cortex-a76'}, '0xd0c': { 'march': 'armv8.2-a', 'march_features': ['crypto', 'rcpc'], - 'compiler_options': ['-mcpu=neoverse-n1'], + 'mcpu': 'neoverse-n1', 'flags': [ ['RTE_MACHINE', '"neoverse-n1"'], ['RTE_ARM_FEATURE_ATOMICS', true], @@ -81,7 +81,7 @@ part_number_config_arm = { '0xd40': { 'march': 'armv8.4-a', 'march_features': ['sve'], - 'compiler_options': ['-mcpu=neoverse-v1'], + 'mcpu': 'neoverse-v1', 'flags': [ ['RTE_MACHINE', '"neoverse-v1"'], ['RTE_ARM_FEATURE_ATOMICS', true], @@ -92,8 +92,9 @@ part_number_config_arm = { 'march': 'armv8.4-a', }, '0xd49': { + 'march': 'armv9-a', 'march_features': ['sve2'], - 'compiler_options': ['-mcpu=neoverse-n2'], + 'mcpu': 'neoverse-n2', 'flags': [ ['RTE_MACHINE', '"neoverse-n2"'], ['RTE_ARM_FEATURE_ATOMICS', true], @@ -127,21 +128,23 @@ implementer_cavium = { ], 'part_number_config': { '0xa1': { - 'compiler_options': ['-mcpu=thunderxt88'], + 'mcpu': 'thunderxt88', 'flags': flags_part_number_thunderx }, '0xa2': { - 'compiler_options': ['-mcpu=thunderxt81'], + 'mcpu': 'thunderxt81', 'flags': flags_part_number_thunderx }, '0xa3': { - 'compiler_options': ['-march=armv8-a+crc', '-mcpu=thunderxt83'], + 'march': 'armv8-a', + 'march_features': ['crc'], + 'mcpu': 'thunderxt83', 'flags': flags_part_number_thunderx }, '0xaf': { 'march': 'armv8.1-a', 'march_features': ['crc', 'crypto'], - 'compiler_options': ['-mcpu=thunderx2t99'], + 'mcpu': 'thunderx2t99', 'flags': [ ['RTE_MACHINE', '"thunderx2"'], ['RTE_ARM_FEATURE_ATOMICS', true], @@ -153,7 +156,7 @@ implementer_cavium = { '0xb2': { 'march': 'armv8.2-a', 'march_features': ['crc', 'crypto', 'lse'], - 'compiler_options': ['-mcpu=octeontx2'], + 'mcpu': 'octeontx2', 'flags': [ ['RTE_MACHINE', '"cn9k"'], ['RTE_ARM_FEATURE_ATOMICS', true], @@ -176,7 +179,7 @@ implementer_ampere = { '0x0': { 'march': 'armv8-a', 'march_features': ['crc', 'crypto'], - 'compiler_options': ['-mtune=emag'], + 'mcpu': 'emag', 'flags': [ ['RTE_MACHINE', '"eMAG"'], ['RTE_MAX_LCORE', 32], @@ -186,7 +189,7 @@ implementer_ampere = { '0xac3': { 'march': 'armv8.6-a', 'march_features': ['crc', 'crypto'], - 'compiler_options': ['-mcpu=ampere1'], + 'mcpu': 'ampere1', 'flags': [ ['RTE_MACHINE', '"AmpereOne"'], ['RTE_MAX_LCORE', 320], @@ -206,7 +209,7 @@ implementer_hisilicon = { '0xd01': { 'march': 'armv8.2-a', 'march_features': ['crypto'], - 'compiler_options': ['-mtune=tsv110'], + 'mcpu': 'tsv110', 'flags': [ ['RTE_MACHINE', '"Kunpeng 920"'], ['RTE_ARM_FEATURE_ATOMICS', true], @@ -695,13 +698,35 @@ if update_flags machine_args = [] # Clear previous machine args - # probe supported archs and their features + march_features = [] + if part_number_config.has_key('march_features') + march_features += part_number_config['march_features'] + endif + if soc_config.has_key('extra_march_features') + march_features += soc_config['extra_march_features'] + endif + + candidate_mcpu = '' candidate_march = '' - if part_number_config.has_key('march') + + if (part_number_config.has_key('mcpu') and + cc.has_argument('-mcpu=' + part_number_config['mcpu'])) + candidate_mcpu = '-mcpu=' + part_number_config['mcpu'] + foreach feature: march_features + if cc.has_argument('+'.join([candidate_mcpu, feature])) + candidate_mcpu = '+'.join([candidate_mcpu, feature]) + else + warning('The compiler does not support feature @0@' + .format(feature)) + endif + endforeach + machine_args += candidate_mcpu + elif part_number_config.has_key('march') + # probe supported archs and their features if part_number_config.get('force_march', false) candidate_march = part_number_config['march'] else - supported_marchs = ['armv8.6-a', 'armv8.5-a', 'armv8.4-a', 'armv8.3-a', + supported_marchs = ['armv9-a', 'armv8.6-a', 'armv8.5-a', 'armv8.4-a', 'armv8.3-a', 'armv8.2-a', 'armv8.1-a', 'armv8-a'] check_compiler_support = false foreach supported_march: supported_marchs @@ -717,32 +742,31 @@ if update_flags endif endforeach endif - if candidate_march == '' - error('No suitable armv8 march version found.') - endif + if candidate_march != part_number_config['march'] - warning('Configuration march version is ' + - '@0@, but the compiler supports only @1@.' - .format(part_number_config['march'], candidate_march)) + warning('Configuration march version is @0@, not supported.' + .format(part_number_config['march'])) + if candidate_march != '' + warning('Using march version @0@.'.format(candidate_march)) + endif endif - candidate_march = '-march=' + candidate_march - march_features = [] - if part_number_config.has_key('march_features') - march_features += part_number_config['march_features'] - endif - if soc_config.has_key('extra_march_features') - march_features += soc_config['extra_march_features'] + if candidate_march != '' + candidate_march = '-march=' + candidate_march + foreach feature: march_features + if cc.has_argument('+'.join([candidate_march, feature])) + candidate_march = '+'.join([candidate_march, feature]) + else + warning('The compiler does not support feature @0@' + .format(feature)) + endif + endforeach + machine_args += candidate_march endif - foreach feature: march_features - if cc.has_argument('+'.join([candidate_march, feature])) - candidate_march = '+'.join([candidate_march, feature]) - else - warning('The compiler does not support feature @0@' - .format(feature)) - endif - endforeach - machine_args += candidate_march + endif + + if candidate_mcpu == '' and candidate_march == '' + error('No suitable ARM march/mcpu version found.') endif # apply supported compiler options From patchwork Mon Feb 26 07:38:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 137190 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C2BBB43BE5; Mon, 26 Feb 2024 08:38:31 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E7BA742DED; Mon, 26 Feb 2024 08:38:30 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 9FAA042DEC for ; Mon, 26 Feb 2024 08:38:28 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41Q6jCJt007246; Sun, 25 Feb 2024 23:38:25 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; s= pfpt0220; bh=fyQF7tPQuV4p46XQqMBeaqrodKqcFvtXYQE7471jkA4=; b=Frl hMW+iglBa7ORu8tLUeNE9l35+B0Z6hCLs+jXO+ZatwgjskVHa0UpsrEz5dEY50tg GIgnvTrvQJ5FYfChM9TeS7xWv1tObflwEh4K7GP8zrzTOvXH8NwFKnTGApIe6LmT dU89hAtfremUUr9wWSW0J8d3ikqc3No8pd9QWTw9YNqRkSNJI92yd353G2qglm0J GB/uUHJKS698gpF934PkqRelG1wHpyoWyEw1WkSOyKNZSjdKOh9eVefO8bVypIOm DQPoSBjlLXo/ctfTH3kmo90aKDKXRy399urBu3ZNb7kj5vworzvntYlDkZ7WxHPd /Eq51oEbZLhw0lyjRvg== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3wfepr4dth-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 25 Feb 2024 23:38:24 -0800 (PST) Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.1258.12; Sun, 25 Feb 2024 23:38:24 -0800 Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Sun, 25 Feb 2024 23:38:23 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Sun, 25 Feb 2024 23:38:23 -0800 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id 164863F706F; Sun, 25 Feb 2024 23:38:19 -0800 (PST) From: To: , , , , Ruifeng Wang , "Bruce Richardson" CC: , Pavan Nikhilesh Subject: [PATCH v6 2/3] config/arm: add support for fallback march Date: Mon, 26 Feb 2024 13:08:09 +0530 Message-ID: <20240226073810.19015-2-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240226073810.19015-1-pbhagavatula@marvell.com> References: <20240222124503.17043-1-pbhagavatula@marvell.com> <20240226073810.19015-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: dGR6ls5uSfbsXdJtAKqAmc63Ynf2tu6p X-Proofpoint-GUID: dGR6ls5uSfbsXdJtAKqAmc63Ynf2tu6p X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-26_04,2024-02-23_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Some ARM CPUs have specific march requirements and are not compatible with the supported march list. Add fallback march in case the mcpu and the march advertised in the part_number_config are not supported by the compiler. Example mcpu = neoverse-n2 march = armv9-a fallback_march = armv8.5-a mcpu, march not supported machine_args = ['-march=armv8.5-a'] mcpu, march, fallback_march not supported least march supported = armv8-a machine_args = ['-march=armv8-a'] Signed-off-by: Pavan Nikhilesh Reviewed-by: Juraj Linkeš --- config/arm/meson.build | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.25.1 diff --git a/config/arm/meson.build b/config/arm/meson.build index 236ad3702d..7f856709ef 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -94,6 +94,7 @@ part_number_config_arm = { '0xd49': { 'march': 'armv9-a', 'march_features': ['sve2'], + 'fallback_march': 'armv8.5-a', 'mcpu': 'neoverse-n2', 'flags': [ ['RTE_MACHINE', '"neoverse-n2"'], @@ -741,6 +742,11 @@ if update_flags break endif endforeach + if (part_number_config.has_key('fallback_march') and + candidate_march != part_number_config['march'] and + cc.has_argument('-march=' + part_number_config['fallback_march'])) + candidate_march = part_number_config['fallback_march'] + endif endif if candidate_march != part_number_config['march'] From patchwork Mon Feb 26 07:38:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 137191 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D2F9E43BE5; Mon, 26 Feb 2024 08:38:36 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3925842DF8; Mon, 26 Feb 2024 08:38:34 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id A56F742DF5 for ; Mon, 26 Feb 2024 08:38:31 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41Q6jOfA005822; Sun, 25 Feb 2024 23:38:29 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=PDUZ4Pj4R/ERrVQ5f784EZuatZdQAo4PmKpefycVv2s=; b=Nfg 2DQi2yWxP3oKBTrDZJz+hCyime32n61mRpLV0rVAMojF+jsZyhHUOGFiV7NOzfRV C8I6MGVLBOcrKj8lNr3GXEq5ZjpLxx1nO8xjuTQ3iSmk+XVk8ZpeVRd6JfCkK6sy m9/f6+SVxvqCN0YQrbtarDe0TujTxpsTi8SfyP9v/J0UGIm/90qQm+LK8AI/bl6O TraRrch8BOXdGP3WcCDpPjA64TuioLUCvfQB7/4yngyeqCKb51I8VnsCRpVsxK7m QVQRkM6A2aO7E46dbTFNwttrSvlQU20GkMZxD0ue1FYB+4lp1JqpDjVICOZ5EQYK aTryW4xRfoe4vpREb2g== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3wfgun435x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 25 Feb 2024 23:38:28 -0800 (PST) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Sun, 25 Feb 2024 23:38:28 -0800 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Sun, 25 Feb 2024 23:38:28 -0800 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id 0D0FC3F706A; Sun, 25 Feb 2024 23:38:23 -0800 (PST) From: To: , , , , Ruifeng Wang , "Bruce Richardson" CC: , Pavan Nikhilesh , Chengwen Feng , Honnappa Nagarahalli Subject: [PATCH v6 3/3] config/arm: allow WFE to be enabled config time Date: Mon, 26 Feb 2024 13:08:10 +0530 Message-ID: <20240226073810.19015-3-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240226073810.19015-1-pbhagavatula@marvell.com> References: <20240222124503.17043-1-pbhagavatula@marvell.com> <20240226073810.19015-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: lBp2CcMaHW_vV0DBAu0c05s8Vs75vh7A X-Proofpoint-GUID: lBp2CcMaHW_vV0DBAu0c05s8Vs75vh7A X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-26_04,2024-02-23_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Allow RTE_ARM_USE_WFE to be enabled at meson configuration time by passing it via c_args instead of modifying `config/arm/meson.build`. Example usage: meson build -Dc_args='-DRTE_ARM_USE_WFE' \ --cross-file config/arm/arm64_cn10k_linux_gcc Signed-off-by: Pavan Nikhilesh Acked-by: Chengwen Feng Acked-by: Ruifeng Wang Reviewed-by: Honnappa Nagarahalli Reviewed-by: Wathsala Vithanage --- config/arm/meson.build | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index 7f856709ef..c1300a8ce8 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -17,7 +17,9 @@ flags_common = [ # ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF], # ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false], - ['RTE_ARM_USE_WFE', false], + # Enable use of ARM wait for event instruction. + # ['RTE_ARM_USE_WFE', false], + ['RTE_ARCH_ARM64', true], ['RTE_CACHE_LINE_SIZE', 128] ]