From patchwork Thu Feb 1 21:57:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 136290 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5A67443A44; Thu, 1 Feb 2024 22:57:48 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 279EC402B9; Thu, 1 Feb 2024 22:57:48 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 49F8E4021D for ; Thu, 1 Feb 2024 22:57:46 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 411HXAJQ027051; Thu, 1 Feb 2024 13:57:42 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=vbN549l+6oWDuRf3bdp8ur6I8rp8F5KW7tgGLqFXH6A=; b=fiq 8bNOCKZwf3PMzPM6mWprAMi15AM6wgWPcoZPhHO8Lz/lXoi00z3q34fX5ZojUUpt fsUNrastsODBWY90mgJ56vKctLN3Y87NdBFMlUr+cQW0CnSVoGyCIqMSvrhbYDa7 CUHXbN1BnwInpfBxUJfDPFN3jKHD2nRsfUcStQ4tVYAHagkwtQSQriQEJyZJD3k2 nTukjo0BCJAD1YSUCF1ha4aHZ9bjzGz8t0ri84kO5fa5Pqc1LEjnNRIMCnxDYv8h PAVyeWqMtB1BWL5/SlvRIWVCw0DnuRthgOxh9a+hK709oZ7EHNXeqk7Di51i3Niy ezGzn3q9V+wz9kci8RQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3w06u8k4t5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 01 Feb 2024 13:57:42 -0800 (PST) Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 1 Feb 2024 13:57:41 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 1 Feb 2024 13:57:41 -0800 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id DDEF83F7044; Thu, 1 Feb 2024 13:57:38 -0800 (PST) From: To: , , , "Ruifeng Wang" , Bruce Richardson CC: , Pavan Nikhilesh Subject: [PATCH v2 1/3] config/arm: avoid mcpu and march conflicts Date: Fri, 2 Feb 2024 03:27:29 +0530 Message-ID: <20240201215731.4543-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240121093653.2890-1-pbhagavatula@marvell.com> References: <20240121093653.2890-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: uHCp9T_lFYQQVQssBVSe9QG0wzJAaC3C X-Proofpoint-ORIG-GUID: uHCp9T_lFYQQVQssBVSe9QG0wzJAaC3C X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-01_08,2024-01-31_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh The compiler options march and mtune are a subset of mcpu and will lead to conflicts if improper march is chosen for a given mcpu. To avoid conflicts, force part number march when mcpu is available and is supported by the compiler. Example: march = armv9-a mcpu = neoverse-n2 mcpu supported, march supported machine_args = ['-mcpu=neoverse-n2', '-march=armv9-a'] mcpu supported, march not supported machine_args = ['-mcpu=neoverse-n2'] mcpu not supported, march supported machine_args = ['-march=armv9-a'] mcpu not supported, march not supported machine_args = ['-march=armv8.6-a'] Signed-off-by: Pavan Nikhilesh --- v2 Changes: - Cleanup march inconsistencies. (Juraj Linkes) - Unify fallback march selection. (Juraj Linkes) - Tag along ARM WFE patch. config/arm/meson.build | 108 +++++++++++++++++++++++++---------------- 1 file changed, 66 insertions(+), 42 deletions(-) -- 2.25.1 diff --git a/config/arm/meson.build b/config/arm/meson.build index 36f21d2259..ba859bd060 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -58,18 +58,18 @@ implementer_generic = { } part_number_config_arm = { - '0xd03': {'compiler_options': ['-mcpu=cortex-a53']}, - '0xd04': {'compiler_options': ['-mcpu=cortex-a35']}, - '0xd05': {'compiler_options': ['-mcpu=cortex-a55']}, - '0xd07': {'compiler_options': ['-mcpu=cortex-a57']}, - '0xd08': {'compiler_options': ['-mcpu=cortex-a72']}, - '0xd09': {'compiler_options': ['-mcpu=cortex-a73']}, - '0xd0a': {'compiler_options': ['-mcpu=cortex-a75']}, - '0xd0b': {'compiler_options': ['-mcpu=cortex-a76']}, + '0xd03': {'mcpu': 'cortex-a53'}, + '0xd04': {'mcpu': 'cortex-a35'}, + '0xd05': {'mcpu': 'cortex-a55'}, + '0xd07': {'mcpu': 'cortex-a57'}, + '0xd08': {'mcpu': 'cortex-a72'}, + '0xd09': {'mcpu': 'cortex-a73'}, + '0xd0a': {'mcpu': 'cortex-a75'}, + '0xd0b': {'mcpu': 'cortex-a76'}, '0xd0c': { 'march': 'armv8.2-a', 'march_features': ['crypto', 'rcpc'], - 'compiler_options': ['-mcpu=neoverse-n1'], + 'mcpu': 'neoverse-n1', 'flags': [ ['RTE_MACHINE', '"neoverse-n1"'], ['RTE_ARM_FEATURE_ATOMICS', true], @@ -81,7 +81,7 @@ part_number_config_arm = { '0xd40': { 'march': 'armv8.4-a', 'march_features': ['sve'], - 'compiler_options': ['-mcpu=neoverse-v1'], + 'mcpu': 'neoverse-v1', 'flags': [ ['RTE_MACHINE', '"neoverse-v1"'], ['RTE_ARM_FEATURE_ATOMICS', true], @@ -92,8 +92,9 @@ part_number_config_arm = { 'march': 'armv8.4-a', }, '0xd49': { + 'march': 'armv9-a', 'march_features': ['sve2'], - 'compiler_options': ['-mcpu=neoverse-n2'], + 'mcpu': 'neoverse-n2', 'flags': [ ['RTE_MACHINE', '"neoverse-n2"'], ['RTE_ARM_FEATURE_ATOMICS', true], @@ -127,21 +128,23 @@ implementer_cavium = { ], 'part_number_config': { '0xa1': { - 'compiler_options': ['-mcpu=thunderxt88'], + 'mcpu': 'thunderxt88', 'flags': flags_part_number_thunderx }, '0xa2': { - 'compiler_options': ['-mcpu=thunderxt81'], + 'mcpu': 'thunderxt81', 'flags': flags_part_number_thunderx }, '0xa3': { - 'compiler_options': ['-march=armv8-a+crc', '-mcpu=thunderxt83'], + 'march': 'armv8-a', + 'march_features': ['crc'], + 'mcpu': 'thunderxt83', 'flags': flags_part_number_thunderx }, '0xaf': { 'march': 'armv8.1-a', 'march_features': ['crc', 'crypto'], - 'compiler_options': ['-mcpu=thunderx2t99'], + 'mcpu': 'thunderx2t99', 'flags': [ ['RTE_MACHINE', '"thunderx2"'], ['RTE_ARM_FEATURE_ATOMICS', true], @@ -153,7 +156,7 @@ implementer_cavium = { '0xb2': { 'march': 'armv8.2-a', 'march_features': ['crc', 'crypto', 'lse'], - 'compiler_options': ['-mcpu=octeontx2'], + 'mcpu': 'octeontx2', 'flags': [ ['RTE_MACHINE', '"cn9k"'], ['RTE_ARM_FEATURE_ATOMICS', true], @@ -176,7 +179,7 @@ implementer_ampere = { '0x0': { 'march': 'armv8-a', 'march_features': ['crc', 'crypto'], - 'compiler_options': ['-mtune=emag'], + 'mcpu': 'emag', 'flags': [ ['RTE_MACHINE', '"eMAG"'], ['RTE_MAX_LCORE', 32], @@ -186,7 +189,7 @@ implementer_ampere = { '0xac3': { 'march': 'armv8.6-a', 'march_features': ['crc', 'crypto'], - 'compiler_options': ['-mcpu=ampere1'], + 'mcpu': 'ampere1', 'flags': [ ['RTE_MACHINE', '"AmpereOne"'], ['RTE_MAX_LCORE', 320], @@ -206,7 +209,7 @@ implementer_hisilicon = { '0xd01': { 'march': 'armv8.2-a', 'march_features': ['crypto'], - 'compiler_options': ['-mtune=tsv110'], + 'mcpu': 'tsv110', 'flags': [ ['RTE_MACHINE', '"Kunpeng 920"'], ['RTE_ARM_FEATURE_ATOMICS', true], @@ -695,11 +698,21 @@ if update_flags machine_args = [] # Clear previous machine args + candidate_mcpu = '' + if part_number_config.has_key('mcpu') + mcpu = part_number_config['mcpu'] + if (cc.has_argument('-mcpu=' + mcpu)) + candidate_mcpu = mcpu + endif + endif + # probe supported archs and their features candidate_march = '' if part_number_config.has_key('march') - if part_number_config.get('force_march', false) - candidate_march = part_number_config['march'] + if part_number_config.get('force_march', false) or candidate_mcpu != '' + if cc.has_argument('-march=' + part_number_config['march']) + candidate_march = part_number_config['march'] + endif else supported_marchs = ['armv8.6-a', 'armv8.5-a', 'armv8.4-a', 'armv8.3-a', 'armv8.2-a', 'armv8.1-a', 'armv8-a'] @@ -717,32 +730,43 @@ if update_flags endif endforeach endif - if candidate_march == '' - error('No suitable armv8 march version found.') - endif + if candidate_march != part_number_config['march'] - warning('Configuration march version is ' + - '@0@, but the compiler supports only @1@.' - .format(part_number_config['march'], candidate_march)) + warning('Configuration march version is @0@, not supported.' + .format(part_number_config['march'])) + if candidate_march != '' + warning('Using march version @0@.'.format(candidate_march)) + endif endif - candidate_march = '-march=' + candidate_march - march_features = [] - if part_number_config.has_key('march_features') - march_features += part_number_config['march_features'] - endif - if soc_config.has_key('extra_march_features') - march_features += soc_config['extra_march_features'] + if candidate_march == '' and candidate_mcpu == '' + error('No suitable ARM march/mcpu version found.') endif - foreach feature: march_features - if cc.has_argument('+'.join([candidate_march, feature])) - candidate_march = '+'.join([candidate_march, feature]) - else - warning('The compiler does not support feature @0@' - .format(feature)) + + if candidate_march != '' + candidate_march = '-march=' + candidate_march + march_features = [] + if part_number_config.has_key('march_features') + march_features += part_number_config['march_features'] endif - endforeach - machine_args += candidate_march + if soc_config.has_key('extra_march_features') + march_features += soc_config['extra_march_features'] + endif + foreach feature: march_features + if cc.has_argument('+'.join([candidate_march, feature])) + candidate_march = '+'.join([candidate_march, feature]) + else + warning('The compiler does not support feature @0@' + .format(feature)) + endif + endforeach + machine_args += candidate_march + endif + endif + + if candidate_mcpu != '' + candidate_mcpu = '-mcpu=' + candidate_mcpu + machine_args += candidate_mcpu endif # apply supported compiler options From patchwork Thu Feb 1 21:57:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 136291 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6F9F343A44; Thu, 1 Feb 2024 22:57:55 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8596E42DAC; Thu, 1 Feb 2024 22:57:51 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 26DB842D90 for ; Thu, 1 Feb 2024 22:57:48 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 411HGxOl027154; Thu, 1 Feb 2024 13:57:45 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=Sa6ou51u7ExSeJUfOozc+tZ5WoFK2qW2fwmDDnjKJzg=; b=L4n X9QB29dKijCEBClpHhKvfZA2nddZex3/ZLlQLjr7SDIMmVE9Q9hl0WtaAxQggGLM ldMJebQP6f056+efx5ZtMhDdvJVuLFXybj79+po+zvS7tu6q4tmxW7daN92TInKk OBJSUjEpx6Ou0CQRJn7TylwGUX2koUNfN/FaGafMH5EOScPr6yK5G0iH4MQo2Z0f dNkWZXZXuM0q+Kj1vWPB0Vij+A7qVeIIHpHj5nQoJ446yNPcUZ7Vf7NZLIxHssBe 3AFEQ6xKOuDo4CjhMbunDkWLsXSoI8YYth9xnJzx0DWJjBf7CVjFUJvi5HnOn7xK Y/ZQp+K24+nPGCrVzrg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3w06u8k4t9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 01 Feb 2024 13:57:45 -0800 (PST) Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 1 Feb 2024 13:57:44 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 1 Feb 2024 13:57:44 -0800 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id C4EC13F704D; Thu, 1 Feb 2024 13:57:41 -0800 (PST) From: To: , , , "Ruifeng Wang" , Bruce Richardson CC: , Pavan Nikhilesh Subject: [PATCH v2 2/3] config/arm: add support for fallback march Date: Fri, 2 Feb 2024 03:27:30 +0530 Message-ID: <20240201215731.4543-2-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240201215731.4543-1-pbhagavatula@marvell.com> References: <20240121093653.2890-1-pbhagavatula@marvell.com> <20240201215731.4543-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: jY543FmAp4410NPhLBIJbucFsbjqwaHM X-Proofpoint-ORIG-GUID: jY543FmAp4410NPhLBIJbucFsbjqwaHM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-01_08,2024-01-31_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Some ARM CPUs have specific march requirements and are not compatible with the supported march list. Add fallback march in case the mcpu and the march advertised in the part_number_config are not supported by the compiler. Example mcpu = neoverse-n2 march = armv9-a fallback_march = armv8.5-a mcpu, march not supported machine_args = ['-march=armv8.5-a'] mcpu, march, fallback_march not supported least march supported = armv8-a machine_args = ['-march=armv8-a'] Signed-off-by: Pavan Nikhilesh --- config/arm/meson.build | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/config/arm/meson.build b/config/arm/meson.build index ba859bd060..6f2308f2fa 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -94,6 +94,7 @@ part_number_config_arm = { '0xd49': { 'march': 'armv9-a', 'march_features': ['sve2'], + 'fallback_march': 'armv8.5-a', 'mcpu': 'neoverse-n2', 'flags': [ ['RTE_MACHINE', '"neoverse-n2"'], @@ -708,6 +709,7 @@ if update_flags # probe supported archs and their features candidate_march = '' + fallback_march = '' if part_number_config.has_key('march') if part_number_config.get('force_march', false) or candidate_mcpu != '' if cc.has_argument('-march=' + part_number_config['march']) @@ -728,10 +730,17 @@ if update_flags # highest supported march version found break endif + if (supported_march == part_number_config['fallback_march'] + and cc.has_argument('-march=' + supported_march)) + fallback_march = supported_march + endif endforeach endif if candidate_march != part_number_config['march'] + if fallback_march != '' + candidate_march = fallback_march + endif warning('Configuration march version is @0@, not supported.' .format(part_number_config['march'])) if candidate_march != '' From patchwork Thu Feb 1 21:57:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 136292 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 52C5643A44; Thu, 1 Feb 2024 22:58:01 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B815142E00; Thu, 1 Feb 2024 22:57:54 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id E00CF42DFF for ; Thu, 1 Feb 2024 22:57:52 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 411HUYMd027032; Thu, 1 Feb 2024 13:57:49 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; 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Thu, 1 Feb 2024 13:57:47 -0800 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id A53C13F7044; Thu, 1 Feb 2024 13:57:44 -0800 (PST) From: To: , , , "Ruifeng Wang" , Bruce Richardson CC: , Pavan Nikhilesh , Chengwen Feng Subject: [PATCH v2 3/3] config/arm: allow WFE to be enabled config time Date: Fri, 2 Feb 2024 03:27:31 +0530 Message-ID: <20240201215731.4543-3-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240201215731.4543-1-pbhagavatula@marvell.com> References: <20240121093653.2890-1-pbhagavatula@marvell.com> <20240201215731.4543-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: amz1VHX-h9gSv1ka9TmZ_EBbnSqGwGpr X-Proofpoint-ORIG-GUID: amz1VHX-h9gSv1ka9TmZ_EBbnSqGwGpr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-01_08,2024-01-31_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Allow RTE_ARM_USE_WFE to be enabled at meson configuration time by passing it via c_args instead of modifying `config/arm/meson.build`. Example usage: meson build -Dc_args='-DRTE_ARM_USE_WFE' \ --cross-file config/arm/arm64_cn10k_linux_gcc Signed-off-by: Pavan Nikhilesh Acked-by: Chengwen Feng Acked-by: Ruifeng Wang --- config/arm/meson.build | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index 6f2308f2fa..3467bef466 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -17,7 +17,9 @@ flags_common = [ # ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF], # ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false], - ['RTE_ARM_USE_WFE', false], + # Enable use of ARM wait for event instruction. + # ['RTE_ARM_USE_WFE', false], + ['RTE_ARCH_ARM64', true], ['RTE_CACHE_LINE_SIZE', 128] ]