From patchwork Mon Dec 11 13:23:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 135020 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 646A8436C8; Mon, 11 Dec 2023 14:23:30 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 51AEA40608; Mon, 11 Dec 2023 14:23:30 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 3EC5940289 for ; Mon, 11 Dec 2023 14:23:29 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BAMrKxp012215 for ; Mon, 11 Dec 2023 05:23:28 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=9I4YeoJhir77Mpx1mo5XF4rSktmMsocP8m3tZsmnySE=; b=dW7 bsaFAHugoqjt52MWztChiKzFrUO1FwkoEFYPY6DNI9m+qaRTMGfCAymkbg23dK4u wYLhYATiuYy8rhQTBGn3SJhH7fw3aYZ89pdMCayXInZJdJ9YqyIqkrvu1M4C7MDU f+i/2S5o5UiyVsIXtc3eUFxjjJiKwAQmf/BE9UoOkm+sax1M/4kP8/NzH1XHoa43 wv0isIaNR83mx3/ycoJVXZjS0BWfh0lBWXaq5hdaxqZipWmuMIjJR36hCGYkvVqv h3tK8eGXO1BDAAj2JKKn7tBUar4dD4e0io5aWJcbdgA6CcPZUwCnjv4QFZ+lk9+7 5Vk1S5CHHqG7jhRZ5vw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3uvrmjmm81-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 11 Dec 2023 05:23:28 -0800 (PST) Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Mon, 11 Dec 2023 05:23:26 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Mon, 11 Dec 2023 05:23:26 -0800 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id D2A683F7068; Mon, 11 Dec 2023 05:23:22 -0800 (PST) From: To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , Pavan Nikhilesh Subject: [PATCH v2 1/3] common/cnxk: update timer base code Date: Mon, 11 Dec 2023 18:53:18 +0530 Message-ID: <20231211132320.1254-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231207065630.4009-1-pbhagavatula@marvell.com> References: <20231207065630.4009-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: iq3-cV9yWmXjMt_q_0jKjXokJgvtwk9Y X-Proofpoint-ORIG-GUID: iq3-cV9yWmXjMt_q_0jKjXokJgvtwk9Y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Update event timer base code. Signed-off-by: Pavan Nikhilesh --- v2 Changes: - Split patches. drivers/common/cnxk/hw/tim.h | 5 +++-- drivers/common/cnxk/roc_mbox.h | 11 +++++++++++ drivers/common/cnxk/roc_sso.c | 2 +- drivers/common/cnxk/roc_tim.c | 27 ++++++++++++++++++++++++++- drivers/common/cnxk/roc_tim.h | 3 +++ 5 files changed, 44 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/drivers/common/cnxk/hw/tim.h b/drivers/common/cnxk/hw/tim.h index 61c38ae175..82b094e3dc 100644 --- a/drivers/common/cnxk/hw/tim.h +++ b/drivers/common/cnxk/hw/tim.h @@ -49,7 +49,8 @@ #define TIM_LF_RING_REL (0x400) #define TIM_MAX_INTERVAL_TICKS ((1ULL << 32) - 1) -#define TIM_MAX_BUCKET_SIZE ((1ULL << 20) - 1) -#define TIM_MIN_BUCKET_SIZE 3 +#define TIM_MAX_BUCKET_SIZE ((1ULL << 20) - 2) +#define TIM_MIN_BUCKET_SIZE 1 +#define TIM_BUCKET_WRAP_SIZE 3 #endif /* __TIM_HW_H__ */ diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 05434aec5a..4590e5f2dd 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -154,6 +154,8 @@ struct mbox_msghdr { M(TIM_DISABLE_RING, 0x804, tim_disable_ring, tim_ring_req, msg_rsp) \ M(TIM_GET_MIN_INTVL, 0x805, tim_get_min_intvl, tim_intvl_req, \ tim_intvl_rsp) \ + M(TIM_CAPTURE_COUNTERS, 0x806, tim_capture_counters, msg_req, \ + tim_capture_rsp) \ /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, msg_rsp) \ M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \ @@ -2541,6 +2543,10 @@ enum tim_clk_srcs { TIM_CLK_SRCS_GPIO = 1, TIM_CLK_SRCS_GTI = 2, TIM_CLK_SRCS_PTP = 3, + TIM_CLK_SRCS_SYNCE = 4, + TIM_CLK_SRCS_BTS = 5, + TIM_CLK_SRCS_EXT_MIO = 6, + TIM_CLK_SRCS_EXT_GTI = 7, TIM_CLK_SRSC_INVALID, }; @@ -2652,6 +2658,11 @@ struct tim_intvl_rsp { uint64_t __io intvl_ns; }; +struct tim_capture_rsp { + struct mbox_msghdr hdr; + uint64_t __io counters[TIM_CLK_SRSC_INVALID]; +}; + struct sdp_node_info { /* Node to which this PF belons to */ uint8_t __io node_id; diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c index 748d287bad..f09b535c80 100644 --- a/drivers/common/cnxk/roc_sso.c +++ b/drivers/common/cnxk/roc_sso.c @@ -891,7 +891,7 @@ roc_sso_rsrc_init(struct roc_sso *roc_sso, uint8_t nb_hws, uint16_t nb_hwgrp, ui goto sso_msix_fail; } - nb_tim_lfs = nb_tim_lfs ? PLT_MIN(nb_tim_lfs, free_tim_lfs) : free_tim_lfs; + nb_tim_lfs = PLT_MIN(nb_tim_lfs, free_tim_lfs); } /* 2 error interrupt per TIM LF */ diff --git a/drivers/common/cnxk/roc_tim.c b/drivers/common/cnxk/roc_tim.c index f8607b2852..095afbb9e6 100644 --- a/drivers/common/cnxk/roc_tim.c +++ b/drivers/common/cnxk/roc_tim.c @@ -91,6 +91,31 @@ tim_err_desc(int rc) } } +int +roc_tim_capture_counters(struct roc_tim *roc_tim, uint64_t *counters, uint8_t nb_cntrs) +{ + struct sso *sso = roc_sso_to_sso_priv(roc_tim->roc_sso); + struct dev *dev = &sso->dev; + struct mbox *mbox = mbox_get(dev->mbox); + struct tim_capture_rsp *rsp; + int rc, i; + + mbox_alloc_msg_tim_capture_counters(mbox); + rc = mbox_process_msg(dev->mbox, (void **)&rsp); + if (rc) { + tim_err_desc(rc); + rc = -EIO; + goto fail; + } + + for (i = 0; i < nb_cntrs; i++) + counters[i] = rsp->counters[i]; + +fail: + mbox_put(mbox); + return rc; +} + int roc_tim_lf_enable(struct roc_tim *roc_tim, uint8_t ring_id, uint64_t *start_tsc, uint32_t *cur_bkt) @@ -138,7 +163,7 @@ roc_tim_lf_disable(struct roc_tim *roc_tim, uint8_t ring_id) goto fail; req->ring = ring_id; - rc = mbox_process(dev->mbox); + rc = mbox_process(mbox); if (rc) { tim_err_desc(rc); rc = -EIO; diff --git a/drivers/common/cnxk/roc_tim.h b/drivers/common/cnxk/roc_tim.h index 7dc9ae0a61..f9a9ad1887 100644 --- a/drivers/common/cnxk/roc_tim.h +++ b/drivers/common/cnxk/roc_tim.h @@ -14,6 +14,8 @@ enum roc_tim_clk_src { ROC_TIM_CLK_SRC_PTP, ROC_TIM_CLK_SRC_SYNCE, ROC_TIM_CLK_SRC_BTS, + ROC_TIM_CLK_SRC_EXT_MIO, + ROC_TIM_CLK_SRC_EXT_GTI, ROC_TIM_CLK_SRC_INVALID, }; @@ -48,5 +50,6 @@ int __roc_api roc_tim_lf_alloc(struct roc_tim *roc_tim, uint8_t ring_id, int __roc_api roc_tim_lf_free(struct roc_tim *roc_tim, uint8_t ring_id); uintptr_t __roc_api roc_tim_lf_base_get(struct roc_tim *roc_tim, uint8_t ring_id); +int roc_tim_capture_counters(struct roc_tim *roc_tim, uint64_t *counters, uint8_t nb_cntrs); #endif From patchwork Mon Dec 11 13:23:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 135021 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 60DA6436C8; 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Mon, 11 Dec 2023 05:23:31 -0800 (PST) Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Mon, 11 Dec 2023 05:23:29 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Mon, 11 Dec 2023 05:23:29 -0800 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id D40983F7096; Mon, 11 Dec 2023 05:23:26 -0800 (PST) From: To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , Pavan Nikhilesh Subject: [PATCH v2 2/3] common/cnxk: update scheduler base code Date: Mon, 11 Dec 2023 18:53:19 +0530 Message-ID: <20231211132320.1254-2-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231211132320.1254-1-pbhagavatula@marvell.com> References: <20231207065630.4009-1-pbhagavatula@marvell.com> <20231211132320.1254-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: r6TwC1fvcHolyQ4UcbEHfGi8Pzt2CwDf X-Proofpoint-GUID: r6TwC1fvcHolyQ4UcbEHfGi8Pzt2CwDf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Update event scheduler base code. Signed-off-by: Pavan Nikhilesh --- drivers/common/cnxk/hw/ssow.h | 4 ++++ drivers/common/cnxk/roc_sso.c | 34 +++++++++++++++++++++++----------- drivers/common/cnxk/roc_sso.h | 2 +- 3 files changed, 28 insertions(+), 12 deletions(-) diff --git a/drivers/common/cnxk/hw/ssow.h b/drivers/common/cnxk/hw/ssow.h index 618ab7973b..c146a8c3ef 100644 --- a/drivers/common/cnxk/hw/ssow.h +++ b/drivers/common/cnxk/hw/ssow.h @@ -54,6 +54,8 @@ #define SSOW_LF_GWS_OP_SWTAG_FULL1 (0xc28ull) #define SSOW_LF_GWS_OP_GWC_INVAL (0xe00ull) +#define SSOW_LF_GWS_MAX_NW_TIM_US (0x400) /* [CN9K, CN10K) */ + /* Enum offsets */ #define SSOW_LF_INT_VEC_IOP (0x0ull) @@ -65,6 +67,8 @@ #define SSOW_LF_GWS_TAG_PEND_GET_WORK_BIT 63 #define SSOW_LF_GWS_TAG_PEND_SWITCH_BIT 62 #define SSOW_LF_GWS_TAG_PEND_DESCHED_BIT 58 +#define SSOW_LF_GWS_TAG_PEND_FLUSH 56 +#define SSOW_LF_GWS_TAG_PEND_SWUNT 54 #define SSOW_LF_GWS_TAG_HEAD_BIT 35 #endif /* __SSOW_HW_H__ */ diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c index f09b535c80..e5c16b2a05 100644 --- a/drivers/common/cnxk/roc_sso.c +++ b/drivers/common/cnxk/roc_sso.c @@ -17,6 +17,11 @@ sso_lf_alloc(struct dev *dev, enum sso_lf_type lf_type, uint16_t nb_lf, struct mbox *mbox = mbox_get(dev->mbox); int rc = -ENOSPC; + if (!nb_lf) { + mbox_put(mbox); + return 0; + } + switch (lf_type) { case SSO_LF_TYPE_HWS: { struct ssow_lf_alloc_req *req; @@ -56,6 +61,11 @@ sso_lf_free(struct dev *dev, enum sso_lf_type lf_type, uint16_t nb_lf) struct mbox *mbox = mbox_get(dev->mbox); int rc = -ENOSPC; + if (!nb_lf) { + mbox_put(mbox); + return 0; + } + switch (lf_type) { case SSO_LF_TYPE_HWS: { struct ssow_lf_free_req *req; @@ -98,6 +108,11 @@ sso_rsrc_attach(struct roc_sso *roc_sso, enum sso_lf_type lf_type, struct rsrc_attach_req *req; int rc = -ENOSPC; + if (!nb_lf) { + mbox_put(mbox); + return 0; + } + req = mbox_alloc_msg_attach_resources(mbox); if (req == NULL) goto exit; @@ -264,13 +279,10 @@ roc_sso_hwgrp_base_get(struct roc_sso *roc_sso, uint16_t hwgrp) } uint64_t -roc_sso_ns_to_gw(struct roc_sso *roc_sso, uint64_t ns) +roc_sso_ns_to_gw(uint64_t base, uint64_t ns) { - struct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev; - uint64_t current_us, current_ns, new_ns; - uintptr_t base; + uint64_t current_us; - base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20); current_us = plt_read64(base + SSOW_LF_GWS_NW_TIM); /* From HRM, table 14-19: * The SSOW_LF_GWS_NW_TIM[NW_TIM] period is specified in n-1 notation. @@ -279,14 +291,11 @@ roc_sso_ns_to_gw(struct roc_sso *roc_sso, uint64_t ns) /* From HRM, table 14-1: * SSOW_LF_GWS_NW_TIM[NW_TIM] specifies the minimum timeout. The SSO - * hardware times out a GET_WORK request within 2 usec of the minimum + * hardware times out a GET_WORK request within 1 usec of the minimum * timeout specified by SSOW_LF_GWS_NW_TIM[NW_TIM]. */ - current_us += 2; - current_ns = current_us * 1E3; - new_ns = (ns - PLT_MIN(ns, current_ns)); - new_ns = !new_ns ? 1 : new_ns; - return (new_ns * plt_tsc_hz()) / 1E9; + current_us += 1; + return PLT_MAX(1UL, (uint64_t)PLT_DIV_CEIL(ns, (current_us * 1E3))); } int @@ -705,6 +714,9 @@ roc_sso_hwgrp_release_xaq(struct roc_sso *roc_sso, uint16_t hwgrps) struct dev *dev = &sso->dev; int rc; + if (!hwgrps) + return 0; + rc = sso_hwgrp_release_xaq(dev, hwgrps); return rc; } diff --git a/drivers/common/cnxk/roc_sso.h b/drivers/common/cnxk/roc_sso.h index 64f14b8119..26061f25f8 100644 --- a/drivers/common/cnxk/roc_sso.h +++ b/drivers/common/cnxk/roc_sso.h @@ -83,7 +83,7 @@ int __roc_api roc_sso_hwgrp_release_xaq(struct roc_sso *roc_sso, int __roc_api roc_sso_hwgrp_set_priority(struct roc_sso *roc_sso, uint16_t hwgrp, uint8_t weight, uint8_t affinity, uint8_t priority); -uint64_t __roc_api roc_sso_ns_to_gw(struct roc_sso *roc_sso, uint64_t ns); +uint64_t __roc_api roc_sso_ns_to_gw(uint64_t base, uint64_t ns); int __roc_api roc_sso_hws_link(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[], uint16_t nb_hwgrp, uint8_t set); int __roc_api roc_sso_hws_unlink(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[], From patchwork Mon Dec 11 13:23:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 135022 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 37E95436C8; Mon, 11 Dec 2023 14:23:43 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1BF9442831; Mon, 11 Dec 2023 14:23:37 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id D9DC3427E4 for ; Mon, 11 Dec 2023 14:23:35 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BB9IHhF009912 for ; Mon, 11 Dec 2023 05:23:35 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=urtNF9RunH7jpPLYZPrbd+Im8pGgqKsd8AUQDXX+8qA=; b=fmi fDqdRfBRVxGsm9HHKwKjfABQ+L+6nx5+x79UWKZAx0WBYtuLyILHtGUDesPK78xC zZ3DuMmEHuRWG2R/lLWwHwpF7/l4vhsXWbF9V34oXsk5+AwzkXmZvZPVwoT2NUhs 2IILGIeSrGzzsnO43mM6ukvIc5ldEkqg3EgKd5bvyK8JqofXdtE8kkJLgKFWtt9w LX04aquuowElSsvf2dgg9cne7Hrl8Uis1KAjW85hypgoP0XwnG7rYGsiKZiG8dnv vSn1qxcIWlighH+L2yEqBa3wXGo/C95gP86WyfWsaRJQh/OM+7tHLNhqrKvuhqDQ SxSYH9Ki1gmsYeqWiIQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3uwyp4gqpw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 11 Dec 2023 05:23:34 -0800 (PST) Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Mon, 11 Dec 2023 05:23:33 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Mon, 11 Dec 2023 05:23:33 -0800 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id 34F213F7068; Mon, 11 Dec 2023 05:23:29 -0800 (PST) From: To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Pavan Nikhilesh , Shijith Thotton CC: Subject: [PATCH v2 3/3] event/cnxk: add option to update links via mbox Date: Mon, 11 Dec 2023 18:53:20 +0530 Message-ID: <20231211132320.1254-3-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231211132320.1254-1-pbhagavatula@marvell.com> References: <20231207065630.4009-1-pbhagavatula@marvell.com> <20231211132320.1254-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 9PnXHZhRYwLhxRpfoktkQrY0yAES68uc X-Proofpoint-GUID: 9PnXHZhRYwLhxRpfoktkQrY0yAES68uc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Add option to update event queue to event port links via mailbox. Signed-off-by: Pavan Nikhilesh --- drivers/common/cnxk/roc_sso.c | 87 +++++++++++++++++++++++++---- drivers/common/cnxk/roc_sso.h | 4 +- drivers/event/cnxk/cn10k_eventdev.c | 6 +- drivers/event/cnxk/cn9k_eventdev.c | 18 +++--- 4 files changed, 90 insertions(+), 25 deletions(-) diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c index e5c16b2a05..293b0c81a1 100644 --- a/drivers/common/cnxk/roc_sso.c +++ b/drivers/common/cnxk/roc_sso.c @@ -235,6 +235,47 @@ sso_hws_link_modify(uint8_t hws, uintptr_t base, struct plt_bitmap *bmp, uint16_ } } +static int +sso_hws_link_modify_af(struct dev *dev, uint8_t hws, struct plt_bitmap *bmp, uint16_t hwgrp[], + uint16_t n, uint8_t set, uint16_t enable) +{ + struct mbox *mbox = mbox_get(dev->mbox); + struct ssow_chng_mship *req; + int rc, i; + + req = mbox_alloc_msg_ssow_chng_mship(mbox); + if (req == NULL) { + rc = mbox_process(mbox); + if (rc) { + mbox_put(mbox); + return -EIO; + } + req = mbox_alloc_msg_ssow_chng_mship(mbox); + if (req == NULL) { + mbox_put(mbox); + return -ENOSPC; + } + } + req->enable = enable; + req->set = set; + req->hws = hws; + req->nb_hwgrps = n; + for (i = 0; i < n; i++) + req->hwgrps[i] = hwgrp[i]; + rc = mbox_process(mbox); + mbox_put(mbox); + if (rc == MBOX_MSG_INVALID) + return rc; + if (rc) + return -EIO; + + for (i = 0; i < n; i++) + enable ? plt_bitmap_set(bmp, hwgrp[i]) : + plt_bitmap_clear(bmp, hwgrp[i]); + + return 0; +} + static int sso_msix_fill(struct roc_sso *roc_sso, uint16_t nb_hws, uint16_t nb_hwgrp) { @@ -300,31 +341,55 @@ roc_sso_ns_to_gw(uint64_t base, uint64_t ns) int roc_sso_hws_link(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[], uint16_t nb_hwgrp, - uint8_t set) + uint8_t set, bool use_mbox) { - struct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev; - struct sso *sso; + struct sso *sso = roc_sso_to_sso_priv(roc_sso); + struct dev *dev = &sso->dev; uintptr_t base; + int rc; - sso = roc_sso_to_sso_priv(roc_sso); + if (!nb_hwgrp) + return 0; + + if (use_mbox && roc_model_is_cn10k()) { + rc = sso_hws_link_modify_af(dev, hws, sso->link_map[hws], hwgrp, nb_hwgrp, set, 1); + if (rc == MBOX_MSG_INVALID) + goto lf_access; + if (rc < 0) + return 0; + goto done; + } +lf_access: base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | hws << 12); sso_hws_link_modify(hws, base, sso->link_map[hws], hwgrp, nb_hwgrp, set, 1); - +done: return nb_hwgrp; } int -roc_sso_hws_unlink(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[], uint16_t nb_hwgrp, - uint8_t set) +roc_sso_hws_unlink(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[], + uint16_t nb_hwgrp, uint8_t set, bool use_mbox) { - struct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev; - struct sso *sso; + struct sso *sso = roc_sso_to_sso_priv(roc_sso); + struct dev *dev = &sso->dev; uintptr_t base; + int rc; - sso = roc_sso_to_sso_priv(roc_sso); + if (!nb_hwgrp) + return 0; + + if (use_mbox && roc_model_is_cn10k()) { + rc = sso_hws_link_modify_af(dev, hws, sso->link_map[hws], hwgrp, nb_hwgrp, set, 0); + if (rc == MBOX_MSG_INVALID) + goto lf_access; + if (rc < 0) + return 0; + goto done; + } +lf_access: base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | hws << 12); sso_hws_link_modify(hws, base, sso->link_map[hws], hwgrp, nb_hwgrp, set, 0); - +done: return nb_hwgrp; } diff --git a/drivers/common/cnxk/roc_sso.h b/drivers/common/cnxk/roc_sso.h index 26061f25f8..4ac901762e 100644 --- a/drivers/common/cnxk/roc_sso.h +++ b/drivers/common/cnxk/roc_sso.h @@ -85,9 +85,9 @@ int __roc_api roc_sso_hwgrp_set_priority(struct roc_sso *roc_sso, uint8_t affinity, uint8_t priority); uint64_t __roc_api roc_sso_ns_to_gw(uint64_t base, uint64_t ns); int __roc_api roc_sso_hws_link(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[], - uint16_t nb_hwgrp, uint8_t set); + uint16_t nb_hwgrp, uint8_t set, bool use_mbox); int __roc_api roc_sso_hws_unlink(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[], - uint16_t nb_hwgrp, uint8_t set); + uint16_t nb_hwgrp, uint8_t set, bool use_mbox); int __roc_api roc_sso_hwgrp_hws_link_status(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp); uintptr_t __roc_api roc_sso_hws_base_get(struct roc_sso *roc_sso, uint8_t hws); diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index bb0c910553..221f419055 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -71,7 +71,7 @@ cn10k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link, uint8 struct cnxk_sso_evdev *dev = arg; struct cn10k_sso_hws *ws = port; - return roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link, profile); + return roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link, profile, 0); } static int @@ -80,7 +80,7 @@ cn10k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link, uin struct cnxk_sso_evdev *dev = arg; struct cn10k_sso_hws *ws = port; - return roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link, profile); + return roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link, profile, 0); } static void @@ -111,7 +111,7 @@ cn10k_sso_hws_release(void *arg, void *hws) for (i = 0; i < CNXK_SSO_MAX_PROFILES; i++) for (j = 0; j < dev->nb_event_queues; j++) - roc_sso_hws_unlink(&dev->sso, ws->hws_id, &j, 1, i); + roc_sso_hws_unlink(&dev->sso, ws->hws_id, &j, 1, i, 0); memset(ws, 0, sizeof(*ws)); } diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index 9fb9ca0d63..5e6305947b 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -25,12 +25,12 @@ cn9k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link, uint8_ if (dev->dual_ws) { dws = port; rc = roc_sso_hws_link(&dev->sso, CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0), map, nb_link, - profile); + profile, 0); rc |= roc_sso_hws_link(&dev->sso, CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1), map, - nb_link, profile); + nb_link, profile, 0); } else { ws = port; - rc = roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link, profile); + rc = roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link, profile, 0); } return rc; @@ -47,12 +47,12 @@ cn9k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link, uint if (dev->dual_ws) { dws = port; rc = roc_sso_hws_unlink(&dev->sso, CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0), map, - nb_link, profile); + nb_link, profile, 0); rc |= roc_sso_hws_unlink(&dev->sso, CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1), map, - nb_link, profile); + nb_link, profile, 0); } else { ws = port; - rc = roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link, profile); + rc = roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link, profile, 0); } return rc; @@ -100,9 +100,9 @@ cn9k_sso_hws_release(void *arg, void *hws) for (i = 0; i < dev->nb_event_queues; i++) { for (k = 0; k < CNXK_SSO_MAX_PROFILES; k++) { roc_sso_hws_unlink(&dev->sso, CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0), - &i, 1, k); + &i, 1, k, 0); roc_sso_hws_unlink(&dev->sso, CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1), - &i, 1, k); + &i, 1, k, 0); } } memset(dws, 0, sizeof(*dws)); @@ -110,7 +110,7 @@ cn9k_sso_hws_release(void *arg, void *hws) ws = hws; for (i = 0; i < dev->nb_event_queues; i++) for (k = 0; k < CNXK_SSO_MAX_PROFILES; k++) - roc_sso_hws_unlink(&dev->sso, ws->hws_id, &i, 1, k); + roc_sso_hws_unlink(&dev->sso, ws->hws_id, &i, 1, k, 0); memset(ws, 0, sizeof(*ws)); } }