From patchwork Thu Jul 6 03:20:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhichao Zeng X-Patchwork-Id: 129325 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F119F42DE1; Thu, 6 Jul 2023 05:13:47 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C29FC42D7E; Thu, 6 Jul 2023 05:13:47 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mails.dpdk.org (Postfix) with ESMTP id 686B5400D5 for ; Thu, 6 Jul 2023 05:13:46 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1688613226; x=1720149226; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=MqY+vLmppYmtd5kzofiNLi3fMxupVxDic43g4a1tCgk=; b=VSUU/g94tFDtNlHqogZ4W9tfcpayaY3MUPWtBd4ZjLcmLNad9JP0Ew9z ZjUfPRGpdTsGvyX4/zVsGdl6qEdtTy/yR6RIxLbh06zjWbX0gR29sLGwr FSF1eQ/m6Edv56gxpwqsAKCNaoGe3/VxWsHET2AsJZlqKpyuy64IDuoyA BSp7iAQ8CEAemmujKYjnNYnOOUrB4GUT0mmwfjJfnmOahTf3PYc/F9hJN aVCwNwg8FXKhwRW876uBzPAmrWVKvzmMwuDOzyQwOatHnR6M6nAjZuMa+ MPYHFi5Q2imikYNuFLD1E6TgfJcRX1QvemD7bhteabTGosWWxnL4uDzMj g==; X-IronPort-AV: E=McAfee;i="6600,9927,10762"; a="343087876" X-IronPort-AV: E=Sophos;i="6.01,184,1684825200"; d="scan'208";a="343087876" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jul 2023 20:13:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10762"; a="832783380" X-IronPort-AV: E=Sophos;i="6.01,184,1684825200"; d="scan'208";a="832783380" Received: from unknown (HELO zhichao-dpdk..) ([10.239.252.103]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jul 2023 20:13:43 -0700 From: Zhichao Zeng To: dev@dpdk.org Cc: qi.z.zhang@intel.com, ke1.xu@intel.com, Zhichao Zeng , Jingjing Wu , Beilei Xing , Wenzhuo Lu Subject: [PATCH] net/iavf: fix AVX2 path selection Date: Thu, 6 Jul 2023 11:20:23 +0800 Message-Id: <20230706032023.1053203-1-zhichaox.zeng@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The AVX2 path does not support outer checksum offload, when AVX2 is forcibly selected and outer checksum offload is configured, the basic Tx path will be selected to ensure proper functionality. Fixes: 5712bf9d6e14 ("net/iavf: add Tx AVX2 offload path") Signed-off-by: Zhichao Zeng Tested-by: Ke Xu --- drivers/net/iavf/iavf_rxtx.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/iavf/iavf_rxtx.c b/drivers/net/iavf/iavf_rxtx.c index bf7e4546a8..f7df4665d1 100644 --- a/drivers/net/iavf/iavf_rxtx.c +++ b/drivers/net/iavf/iavf_rxtx.c @@ -3950,6 +3950,12 @@ iavf_set_tx_function(struct rte_eth_dev *dev) dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx2; PMD_DRV_LOG(DEBUG, "Using AVX2 Vector Tx (port %d).", dev->data->port_id); + } else if (check_ret == IAVF_VECTOR_CTX_OFFLOAD_PATH) { + dev->tx_pkt_burst = iavf_xmit_pkts; + dev->tx_pkt_prepare = iavf_prep_pkts; + PMD_DRV_LOG(DEBUG, + "AVX2 does not support outer checksum offload, using Basic Tx (port %d).", + dev->data->port_id); } else { dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx2_offload; dev->tx_pkt_prepare = iavf_prep_pkts;