From patchwork Tue Jul 4 10:46:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Itamar Gozlan X-Patchwork-Id: 129244 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E8D1A42DD1; Tue, 4 Jul 2023 12:48:05 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 86D3840E03; Tue, 4 Jul 2023 12:48:05 +0200 (CEST) Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2043.outbound.protection.outlook.com [40.107.100.43]) by mails.dpdk.org (Postfix) with ESMTP id C4AD640042 for ; Tue, 4 Jul 2023 12:48:03 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Y0BaYITmjQmxethjaoMGODmOhXXtVhJBWfmmg35gAPc5TqMzbnKx42KX90MPoZxcRFtnUuI4YcdV2JsXJYYwdNqloj7PMrzFkmEr/cZCSaXyA4QEtYkJkXY6ETjHCq64Bk0clw0L8skxhCT0yF8ATz1wtha4bXJ6Xcz7dF1K7MdqkUH6Q6GsuWL0XMySoZ7fCfYNP0KatgSa/14bFklf9vOXi9AdElz781XQPD7OxAVzrE/+2vbLb0VLzkXvfO1VL3me5YBW6Yh45bjrF/88V9Sv1EXPkUpBCGnJjxjMW4QqCsfwgZGCjWYcSz+O79UnIyjw7EhJx9z5a6bwyw2+5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Cx7G65NElZqvqbnFj16+Afv+XDVDlwCNj7vVJhgFJI8=; b=DFdLnkUN27m6zhC8HjGedj4+f/B9CUUwYw4cNcFsWe+yEIzhuiDipGbDbpyu/IzlHtSrsOh0cHq1p67zfA6xMg8V7tKF3ZHWtozJuCZz91HZoTemagjLLEUqnvmEgU952HsgVwAcTuphW2MGWCp7sl671KyjirXzH/DlfGRMtllp3Afv2z7zEm3WDuSbje9gcYCLdSQSJPcLedimMSGP5MWqSVOxBa25Kzd3gyzJAJIq5xc2h/VvVtKQoKFifs5rxWJMUshrHke50p0+PNZezWajNImIDqm1i9zBVzTtGlCkP+pVmLyvOIKI5M8h0spvTAGCNGCTVUP46SOyOK23Mg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Cx7G65NElZqvqbnFj16+Afv+XDVDlwCNj7vVJhgFJI8=; b=k3mRgaa0/P42fgNoS1xQw+tU2AMpkaom2T0yKH6IZedNuTB7Xe63khVJSZJ1UVfGTVQGHKwF25aIJcEG/PziJPiUDySnS4DblDD84eqrUh9LRxutPlb11Dtm5ajcna/lw9vfr9Ohj1ZvPluGW/0tYYRs60JR2+QEXQJBb10O5/2VeqCyAh1lJ5O2M6PBIY+VuwwfHgNNhtUxVOz8cM0Pk+HnRebC0+xT7XVp5mLL4LrBBCbVTHYATlc14HRmn+M6UN147z+KR65JlzermIFesJz3BNGo0zPX1FvuKIb7TD+kDZ1yDE5m9Hm7tGJAm6ZRnX2uAjkf5tHcM1gBdZKxEA== Received: from DS7PR06CA0031.namprd06.prod.outlook.com (2603:10b6:8:54::11) by SJ2PR12MB8181.namprd12.prod.outlook.com (2603:10b6:a03:4f6::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6544.24; Tue, 4 Jul 2023 10:47:59 +0000 Received: from DM6NAM11FT049.eop-nam11.prod.protection.outlook.com (2603:10b6:8:54:cafe::a4) by DS7PR06CA0031.outlook.office365.com (2603:10b6:8:54::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6544.31 via Frontend Transport; Tue, 4 Jul 2023 10:47:59 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DM6NAM11FT049.mail.protection.outlook.com (10.13.172.188) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6521.43 via Frontend Transport; Tue, 4 Jul 2023 10:47:58 +0000 Received: from rnnvmail205.nvidia.com (10.129.68.10) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Tue, 4 Jul 2023 03:47:48 -0700 Received: from rnnvmail203.nvidia.com (10.129.68.9) by rnnvmail205.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Tue, 4 Jul 2023 03:47:47 -0700 Received: from nvidia.com (10.127.8.12) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37 via Frontend Transport; Tue, 4 Jul 2023 03:47:45 -0700 From: Itamar Gozlan To: , , , , , Ori Kam CC: Subject: [v1 1/5] net/mlx5/hws: remove uneeded new line for DR_LOG Date: Tue, 4 Jul 2023 13:46:41 +0300 Message-ID: <20230704104645.19800-1-igozlan@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20230702045758.23244-4-igozlan@nvidia.com> References: <20230702045758.23244-4-igozlan@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT049:EE_|SJ2PR12MB8181:EE_ X-MS-Office365-Filtering-Correlation-Id: d80ddd4a-56c6-4d16-c1a2-08db7c7c21e3 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 11Ru2hj5QKveNjQ1kFPoBDzpcVc1pIhx2L4JFnV54tnqu4DJ+c4NqL1UsTa+SgA7RQIdlECqRuo8pNrPQ5hlKwSsQB3SeNqVT/xGOvPZ8X6URgqYxEnH8T9jfj0bw6leAu1P3FPgymE2RJrAFNwGk5pMYDYTfJb5stlnJ0psdLyWQauG+njRKWvYQi0JhMC9THKKf1xM29VnGqPxDaUxQY433sqnxQqAtaoCsUmO/IYyG9EXWfaTAFbTGaLkcDqK1WHls/xfAQ/W+KkCdtNYG9knV6fMlCh3m6xUa5T5Dn5kx0WMrqPLxVXzkDKY7VfazC3PeSTcPRvkk0cTs68+sYZtShrOqZFOeJoBVVPFhiBTKUK4G9BFhtOBCzKNvBDrp/nSL0jqxuLRbsiEl2ZMV/Qb667AebUwa9reqYDCqHTgJhIfI6dRlm8Ueym3DLYKC9LsCevXOb/hjS5sjF+2lLCLWwEIrFzkyAZK3/gfz4jKnx1tiECLsXG/Lgudx67bVInXLck0rRo98HNfE8CNVg4bf3MjV6kkqeeEw71Ql1f4chxUiiZETm9cLyQ4JzhEAekKzzdiHE+h2iLvLmePUqAuTeyK288pQuvEZLT3oFux7NGwmKK6lJOJhvWEOrk+NzOsiLxwI1VGRMykLYiMa9mszYtwwaIOOefwt99nYleu668u2msZ1YSXXW8x8vsJx2UZRHbvWpAkhz9HfnNpEVw/fWZfgQD1hR4p6byEUbn85OdmaF1ui7sq8/RxjrLO X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230028)(4636009)(346002)(39860400002)(376002)(396003)(136003)(451199021)(40470700004)(46966006)(36840700001)(336012)(40460700003)(41300700001)(7696005)(6666004)(82310400005)(26005)(7636003)(356005)(82740400003)(83380400001)(2616005)(426003)(186003)(1076003)(6286002)(47076005)(40480700001)(36860700001)(55016003)(86362001)(110136005)(478600001)(36756003)(2906002)(316002)(4326008)(70206006)(70586007)(8936002)(8676002)(6636002)(5660300002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jul 2023 10:47:58.8014 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d80ddd4a-56c6-4d16-c1a2-08db7c7c21e3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT049.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8181 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Alex Vesker In some places an extra new line was added, remove to have clean prints. Signed-off-by: Alex Vesker Acked-by: Matan Azrad --- v2->v3 1. Right patches instead of wrong patches in the previous series v1->v2 1. Last patch in the series (net/mlx5/hws: support default miss action on FDB) needed some fixes to be properly rebased. drivers/net/mlx5/hws/mlx5dr_action.c | 30 +++++++++++++-------------- drivers/net/mlx5/hws/mlx5dr_cmd.c | 2 +- drivers/net/mlx5/hws/mlx5dr_definer.c | 4 ++-- drivers/net/mlx5/hws/mlx5dr_pat_arg.c | 4 ++-- 4 files changed, 20 insertions(+), 20 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_action.c b/drivers/net/mlx5/hws/mlx5dr_action.c index 01d30b8442..e2db85940c 100644 --- a/drivers/net/mlx5/hws/mlx5dr_action.c +++ b/drivers/net/mlx5/hws/mlx5dr_action.c @@ -112,7 +112,7 @@ static int mlx5dr_action_get_shared_stc_nic(struct mlx5dr_context *ctx, stc_attr.remove_words.num_of_words = MLX5DR_ACTION_HDR_LEN_L2_VLAN; break; default: - DR_LOG(ERR, "No such type : stc_type\n"); + DR_LOG(ERR, "No such type : stc_type"); assert(false); rte_errno = EINVAL; goto unlock_and_out; @@ -469,7 +469,7 @@ static uint32_t mlx5dr_action_get_mh_stc_type(__be64 pattern) return MLX5_IFC_STC_ACTION_TYPE_COPY; default: assert(false); - DR_LOG(ERR, "Unsupported action type: 0x%x\n", action_type); + DR_LOG(ERR, "Unsupported action type: 0x%x", action_type); rte_errno = ENOTSUP; return MLX5_IFC_STC_ACTION_TYPE_NOP; } @@ -1017,7 +1017,7 @@ static int mlx5dr_action_create_dest_vport_hws(struct mlx5dr_context *ctx, ret = mlx5dr_cmd_query_ib_port(ctx->ibv_ctx, &vport_caps, ib_port_num); if (ret) { - DR_LOG(ERR, "Failed querying port %d\n", ib_port_num); + DR_LOG(ERR, "Failed querying port %d", ib_port_num); return ret; } action->vport.vport_num = vport_caps.vport_num; @@ -1025,7 +1025,7 @@ static int mlx5dr_action_create_dest_vport_hws(struct mlx5dr_context *ctx, ret = mlx5dr_action_create_stcs(action, NULL); if (ret) { - DR_LOG(ERR, "Failed creating stc for port %d\n", ib_port_num); + DR_LOG(ERR, "Failed creating stc for port %d", ib_port_num); return ret; } @@ -1041,7 +1041,7 @@ mlx5dr_action_create_dest_vport(struct mlx5dr_context *ctx, int ret; if (!(flags & MLX5DR_ACTION_FLAG_HWS_FDB)) { - DR_LOG(ERR, "Vport action is supported for FDB only\n"); + DR_LOG(ERR, "Vport action is supported for FDB only"); rte_errno = EINVAL; return NULL; } @@ -1052,7 +1052,7 @@ mlx5dr_action_create_dest_vport(struct mlx5dr_context *ctx, ret = mlx5dr_action_create_dest_vport_hws(ctx, action, ib_port_num); if (ret) { - DR_LOG(ERR, "Failed to create vport action HWS\n"); + DR_LOG(ERR, "Failed to create vport action HWS"); goto free_action; } @@ -1081,7 +1081,7 @@ mlx5dr_action_create_push_vlan(struct mlx5dr_context *ctx, uint32_t flags) ret = mlx5dr_action_create_stcs(action, NULL); if (ret) { - DR_LOG(ERR, "Failed creating stc for push vlan\n"); + DR_LOG(ERR, "Failed creating stc for push vlan"); goto free_action; } @@ -1115,7 +1115,7 @@ mlx5dr_action_create_pop_vlan(struct mlx5dr_context *ctx, uint32_t flags) ret = mlx5dr_action_create_stcs(action, NULL); if (ret) { - DR_LOG(ERR, "Failed creating stc for pop vlan\n"); + DR_LOG(ERR, "Failed creating stc for pop vlan"); goto free_shared; } @@ -1418,7 +1418,7 @@ mlx5dr_action_handle_tunnel_l3_to_l2(struct mlx5dr_context *ctx, if (data_sz != MLX5DR_ACTION_HDR_LEN_L2 && data_sz != MLX5DR_ACTION_HDR_LEN_L2_W_VLAN) { - DR_LOG(ERR, "Data size is not supported for decap-l3\n"); + DR_LOG(ERR, "Data size is not supported for decap-l3"); rte_errno = EINVAL; return rte_errno; } @@ -1430,7 +1430,7 @@ mlx5dr_action_handle_tunnel_l3_to_l2(struct mlx5dr_context *ctx, ret = mlx5dr_pat_arg_create_modify_header(ctx, action, mh_data_size, (__be64 *)mh_data, bulk_size); if (ret) { - DR_LOG(ERR, "Failed allocating modify-header for decap-l3\n"); + DR_LOG(ERR, "Failed allocating modify-header for decap-l3"); return ret; } @@ -1528,7 +1528,7 @@ mlx5dr_action_create_reformat(struct mlx5dr_context *ctx, if (!mlx5dr_action_is_hws_flags(flags) || ((flags & MLX5DR_ACTION_FLAG_SHARED) && log_bulk_size)) { - DR_LOG(ERR, "Reformat flags don't fit HWS (flags: %x0x)\n", + DR_LOG(ERR, "Reformat flags don't fit HWS (flags: %x0x)", flags); rte_errno = EINVAL; goto free_action; @@ -1536,7 +1536,7 @@ mlx5dr_action_create_reformat(struct mlx5dr_context *ctx, ret = mlx5dr_action_create_reformat_hws(ctx, data_sz, inline_data, log_bulk_size, action); if (ret) { - DR_LOG(ERR, "Failed to create reformat.\n"); + DR_LOG(ERR, "Failed to create reformat."); rte_errno = EINVAL; goto free_action; } @@ -1605,14 +1605,14 @@ mlx5dr_action_create_modify_header(struct mlx5dr_context *ctx, if (!mlx5dr_action_is_hws_flags(flags) || ((flags & MLX5DR_ACTION_FLAG_SHARED) && log_bulk_size)) { - DR_LOG(ERR, "Flags don't fit hws (flags: %x0x, log_bulk_size: %d)\n", + DR_LOG(ERR, "Flags don't fit hws (flags: %x0x, log_bulk_size: %d)", flags, log_bulk_size); rte_errno = EINVAL; goto free_action; } if (!mlx5dr_pat_arg_verify_actions(pattern, pattern_sz / MLX5DR_MODIFY_ACTION_SIZE)) { - DR_LOG(ERR, "One of the actions is not supported\n"); + DR_LOG(ERR, "One of the actions is not supported"); rte_errno = EINVAL; goto free_action; } @@ -1628,7 +1628,7 @@ mlx5dr_action_create_modify_header(struct mlx5dr_context *ctx, ret = mlx5dr_pat_arg_create_modify_header(ctx, action, pattern_sz, pattern, log_bulk_size); if (ret) { - DR_LOG(ERR, "Failed allocating modify-header\n"); + DR_LOG(ERR, "Failed allocating modify-header"); goto free_action; } } diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c b/drivers/net/mlx5/hws/mlx5dr_cmd.c index f1ae256a7e..f9f220cc6a 100644 --- a/drivers/net/mlx5/hws/mlx5dr_cmd.c +++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c @@ -1134,7 +1134,7 @@ int mlx5dr_cmd_query_caps(struct ibv_context *ctx, ret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); if (ret) { - DR_LOG(ERR, "Query eswitch capabilities failed %d\n", ret); + DR_LOG(ERR, "Query eswitch capabilities failed %d", ret); rte_errno = errno; return rte_errno; } diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index 7b01f4c9ec..33d0f2d18e 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -535,7 +535,7 @@ mlx5dr_definer_get_mpls_fc(struct mlx5dr_definer_conv_data *cd, bool inner) break; default: rte_errno = ENOTSUP; - DR_LOG(ERR, "MPLS index %d is not supported\n", mpls_idx); + DR_LOG(ERR, "MPLS index %d is not supported", mpls_idx); return NULL; } @@ -571,7 +571,7 @@ mlx5dr_definer_get_mpls_oks_fc(struct mlx5dr_definer_conv_data *cd, bool inner) break; default: rte_errno = ENOTSUP; - DR_LOG(ERR, "MPLS index %d is not supported\n", mpls_idx); + DR_LOG(ERR, "MPLS index %d is not supported", mpls_idx); return NULL; } diff --git a/drivers/net/mlx5/hws/mlx5dr_pat_arg.c b/drivers/net/mlx5/hws/mlx5dr_pat_arg.c index 830bc08678..bedaedb677 100644 --- a/drivers/net/mlx5/hws/mlx5dr_pat_arg.c +++ b/drivers/net/mlx5/hws/mlx5dr_pat_arg.c @@ -449,7 +449,7 @@ bool mlx5dr_pat_arg_verify_actions(__be64 pattern[], uint16_t num_of_actions) u8 action_id = MLX5_GET(set_action_in, &pattern[i], action_type); if (action_id >= MLX5_MODIFICATION_TYPE_MAX) { - DR_LOG(ERR, "Invalid action %u\n", action_id); + DR_LOG(ERR, "Invalid action %u", action_id); return false; } } @@ -468,7 +468,7 @@ int mlx5dr_pat_arg_create_modify_header(struct mlx5dr_context *ctx, num_of_actions = pattern_sz / MLX5DR_MODIFY_ACTION_SIZE; if (num_of_actions == 0) { - DR_LOG(ERR, "Invalid number of actions %u\n", num_of_actions); + DR_LOG(ERR, "Invalid number of actions %u", num_of_actions); rte_errno = EINVAL; return rte_errno; } From patchwork Tue Jul 4 10:46:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Itamar Gozlan X-Patchwork-Id: 129245 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BFFC342DD1; Tue, 4 Jul 2023 12:48:16 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id ABD1942BFE; Tue, 4 Jul 2023 12:48:16 +0200 (CEST) Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2058.outbound.protection.outlook.com [40.107.102.58]) by mails.dpdk.org (Postfix) with ESMTP id DEBA840042 for ; Tue, 4 Jul 2023 12:48:14 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=GR6RI9RRLZTOSaK3pnaFvE9nEqzLEj0kqPiNAAd58MVm+lOwO9QE24So7KygqQS9vXe7B1UgtmArVoasaXFiP9FfmtMsYpWVYfIFf/u+uNos07iQWnyjpfsk49CE4gw2+5EFAhiGqh+3Zeq8Rw5g2XPJGZGrrT1V91ADO+TCfPPwKpdK/Rk5UEwcNIec2Xg1IpboxJdsxGMpnmnAsSbfkGfMsoLwdP54wnfBcQwJWX4lrYnBoFhxBj6xqHwoWPQVWju4jf6S5gfu519CeaD/uhiCEG/yWjc343Pxqk3GMgAi2c59/AxavTMSgvJ4yb4c6PwirWG4Q0PpzZbnqEq1Ew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=MZqltVc9C7tFlZcBGBqtk9ARhPSKmqbrdkkyMwpcY9A=; b=gm3OfJB2c6Xm49//4qkdG229nUMf+J2PwTEP1tXv+0gQNLLbqATWlEMmUYqzrPmyvTtmVGknYRs9ueqyYNi0v6bHNTA7IM31UDwu9HctrkbyT6l0yJrvRzfyl+SMYjWflHslAGR/lZ+Gcw2efZ0tkQ8XlfoCa/o0KAFs0/wqq9TQOcQ7LMHYFN6tKOIVbeeDyPWhCbZ83UWmV0NFVDutCqtiy/YzAFGjDrbfB+HZreVQqsSJU/GIaj/byuiGRGgr07IHZGqr89nzi82hOUVrXzglxmHBU4yvesRuLlLNKutN1IIuVqLw4GMCEvgIds5h2rHWR8vNu61ybCmPGKPgOw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MZqltVc9C7tFlZcBGBqtk9ARhPSKmqbrdkkyMwpcY9A=; b=Y+OWWyZmIx2v94WJ+b+fw5+Hn66LP/JKQhu2/7nqEQkFs5yY8gz16bF6wvyPvZvFFGTrMXHG+ZnX01IhEtbrB1Irf/Ck23ZY02KJDlkkyPS+dmex5e2AD4xSlQhe1oBfBcRBgLwvumPRS1pvIhiH8PbxQMR4QFwNI7G2H1MTPTh0kG4u2TJDXQ3uY5OCGeY7nz7e8epMuH1CP4exu2DCA6FdeufOph6qAWrFKKsMLkqIActyI+qCso3rgmmViQPofpHor3TS4NN5SFuRmwN9CrAJu6Go8l95gYTOMm9T87SpZzp5tQ5Iag8zDxLKZbU/pb0k6FBNj/DB0LEOSQmN6Q== Received: from MW4P221CA0015.NAMP221.PROD.OUTLOOK.COM (2603:10b6:303:8b::20) by CH3PR12MB9249.namprd12.prod.outlook.com (2603:10b6:610:1bc::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6565.17; Tue, 4 Jul 2023 10:48:13 +0000 Received: from CO1NAM11FT049.eop-nam11.prod.protection.outlook.com (2603:10b6:303:8b:cafe::8) by MW4P221CA0015.outlook.office365.com (2603:10b6:303:8b::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6544.31 via Frontend Transport; Tue, 4 Jul 2023 10:48:13 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CO1NAM11FT049.mail.protection.outlook.com (10.13.175.50) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6521.44 via Frontend Transport; Tue, 4 Jul 2023 10:48:12 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Tue, 4 Jul 2023 03:48:01 -0700 Received: from rnnvmail203.nvidia.com (10.129.68.9) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Tue, 4 Jul 2023 03:48:01 -0700 Received: from nvidia.com (10.127.8.12) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37 via Frontend Transport; Tue, 4 Jul 2023 03:47:59 -0700 From: Itamar Gozlan To: , , , , , Ori Kam CC: Subject: [v1 2/5] net/mlx5/hws: allow destroying rule resources on error Date: Tue, 4 Jul 2023 13:46:42 +0300 Message-ID: <20230704104645.19800-2-igozlan@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20230704104645.19800-1-igozlan@nvidia.com> References: <20230702045758.23244-4-igozlan@nvidia.com> <20230704104645.19800-1-igozlan@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT049:EE_|CH3PR12MB9249:EE_ X-MS-Office365-Filtering-Correlation-Id: 0468fde2-caae-421d-4f80-08db7c7c2a3e X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: U5b7HeqmsCMHH7srzemfWP1d3f30w6HDGOh2d2y19x0yaOQLQviwo1zJwWlsNlFoZR21U4U9A1Nhh5SCgJdUGeWXXXwqls1icd2/lz5MQDs/5jpbUNDL/ZdSV+u88Wdcavp5NAHJDxgBn7ZhKJYUVsanP3n7TaieiL3B8YMLVI0Rk+yXDGzKzrk5uut1p67HT57p4KaMpwI1OSAl0v185qUJt4NFJ62KBUs/gsKlOYj0p51J3mtz94knhZppinNdbADolAqaNvaUIsl4EMAnEh4OE3qW0SCPpk804MtfUxsCNXuLtCPK5QyEnVf7/WxIfvtYZSaUfAqQPNQ4j6iitZ2p1FJXQed07TWK7CSl0UYVdSDPpfE1l7jlIBso/+1fF/3l1ZPLXt5Gpc+//Z8ZyUXG4ApCfbptC2VlWJhwYcyivH5t+Vc7wnoOtQ95zNh5a3BpcyuVNyy2fTkZh6eg2QJq4tK4NjLFCjGXvwZGPGxQW61/mXGT8qTRgfx+ZUl0QakFboMEOwrzklxxnF0IxPx50pTOOjHvIHzAWcbxtdxADdgg0oETclI6Mj0Q4QKTz+pqHMWsTVy/vMb5NLfZPcXbIh/PTzmKnmhAcIdTcg8LSmXv6wpJxuardjukXSxvAZiA5Z+RTiTIq0rvm0g+OiPDNlynjKvlIX/94eWJlH+Uhs+raIL5PWF3DTMqgr6RnvXooM7jEQaLu+lXtSLgh2xkHZrC9GS54g+oQguodUEy7yHnIcbvIFPp7wGaWMR+ X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230028)(4636009)(39860400002)(396003)(136003)(376002)(346002)(451199021)(36840700001)(40470700004)(46966006)(41300700001)(8936002)(8676002)(110136005)(36756003)(40480700001)(7696005)(55016003)(316002)(5660300002)(2906002)(6666004)(6636002)(4326008)(70586007)(70206006)(40460700003)(426003)(336012)(478600001)(82740400003)(82310400005)(186003)(86362001)(6286002)(2616005)(356005)(7636003)(47076005)(83380400001)(1076003)(26005)(36860700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jul 2023 10:48:12.8010 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0468fde2-caae-421d-4f80-08db7c7c2a3e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT049.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9249 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Alex Vesker In case the send engine is in error state API should provide a way to free rule resources and provide a fake completion. Otherwise there is no way to release these resources. Signed-off-by: Alex Vesker Acked-by: Matan Azrad --- drivers/net/mlx5/hws/mlx5dr_rule.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_rule.c b/drivers/net/mlx5/hws/mlx5dr_rule.c index 071e1ad769..931c68b160 100644 --- a/drivers/net/mlx5/hws/mlx5dr_rule.c +++ b/drivers/net/mlx5/hws/mlx5dr_rule.c @@ -521,6 +521,11 @@ static int mlx5dr_rule_destroy_hws(struct mlx5dr_rule *rule, queue = &ctx->send_queue[attr->queue_id]; + if (unlikely(mlx5dr_send_engine_err(queue))) { + mlx5dr_rule_destroy_failed_hws(rule, attr); + return 0; + } + /* Rule is not completed yet */ if (rule->status == MLX5DR_RULE_STATUS_CREATING) { rte_errno = EBUSY; @@ -533,11 +538,6 @@ static int mlx5dr_rule_destroy_hws(struct mlx5dr_rule *rule, return 0; } - if (unlikely(mlx5dr_send_engine_err(queue))) { - mlx5dr_rule_destroy_failed_hws(rule, attr); - return 0; - } - mlx5dr_send_engine_inc_rule(queue); /* Send dependent WQE */ From patchwork Tue Jul 4 10:46:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Itamar Gozlan X-Patchwork-Id: 129246 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 39D3B42DD1; Tue, 4 Jul 2023 12:48:27 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2924242D12; Tue, 4 Jul 2023 12:48:27 +0200 (CEST) Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2040.outbound.protection.outlook.com [40.107.236.40]) by mails.dpdk.org (Postfix) with ESMTP id C576242D10 for ; Tue, 4 Jul 2023 12:48:25 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=BrhN80NhVUzTpivoGS1fmvwgD5iNnjSULpRssJHxm2zhIhnNixTK1HpImvlYxaxK5nH/et2nD2XSVbHYYjwH+P083SiIftAyLmKh4EmJabvn049Ou4fx1a3xKG4QFBorETqCOUtcv1p44no7LtKjTjvqE0Drv5b7U44CDxvLM2ieEJRbYpv26iRig3k6psJf7VQVYgaGTx/BXTRP8qd7U0fF6SfTNk9w3zNA23N2klYogYSkFtKvWOMyMcdXBHxAHZW5fy6x8LNXW7IzPP+QtgFw9mZftSu5TJ1IrLt1ATG0YPzcRlzTe2z6DUNB5ycbgIGd4VCxwut6cG5nXEeqSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=s6Z870rGHHMAyojkZY2etlAQXfIvYJcSpEVQo0/BLZM=; b=NoG8hTyXBUzTHTP78KXORh+c+FW/fGpI5+XKa0zfCBCdzBEAsbWEIP5TZ/g/jpAk1dy+/l3InWWW0bn6aBk2+WLUxz16VpAeM5zoYX51WelyQ4O/qk+rcC1AfD4JL499GoizJ+1PRm1GxNOh2I1fZoY4G3RtYcD0kET0K0VWGVYhg6gjXi26jAgLH9OVJcgtv9fJY6OAiczhbm0xzHZ3EZZjb4vbWFZ6xxaJcoLSKcC7/1UD5MarymmwkqWWuKmlydRjMLbZWvowGeNka261e5lwr1cccUjiWsLdD5Z0uoGSxqZZMUWb4MY6xVKt6+ZXGY0J//9RLbhZo+qN3XZYZA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=s6Z870rGHHMAyojkZY2etlAQXfIvYJcSpEVQo0/BLZM=; b=LMapwCjWteXIAlC4akkWV4b7G6PKTOpMCtsh4DoR0jMS5Azrmpgt6qyr+VUvjUAEsNMy90Gil4YqJHO+diMkBFdzNKg4Y9KMTdvD3fatOKFYR8/Te3Gsrx0de03viN3rSIOaopyQDXWFLbDPsX6O5Nk5K+iI977nhddpTvwuP+WfAb3P4vaNdvE/eIsHy4iMp5HSa+OD+FkPg+GWwfGtbCTRpIasglOLalTr6FQN0GO1IDYlBdo0BCksm6Lg9F/ntx2YBevMP2Fjdo3RA7EGcIfssvIRW4vFvUEEpyhkh8w4H4VUkP/vEs1dYOig4afFAr5c5ngP82WXpQJ4GhxtQg== Received: from MW4PR04CA0207.namprd04.prod.outlook.com (2603:10b6:303:86::32) by MN2PR12MB4189.namprd12.prod.outlook.com (2603:10b6:208:1d8::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6544.24; Tue, 4 Jul 2023 10:48:23 +0000 Received: from CO1NAM11FT076.eop-nam11.prod.protection.outlook.com (2603:10b6:303:86:cafe::ef) by MW4PR04CA0207.outlook.office365.com (2603:10b6:303:86::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6544.31 via Frontend Transport; Tue, 4 Jul 2023 10:48:23 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CO1NAM11FT076.mail.protection.outlook.com (10.13.174.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6521.43 via Frontend Transport; Tue, 4 Jul 2023 10:48:23 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Tue, 4 Jul 2023 03:48:12 -0700 Received: from rnnvmail203.nvidia.com (10.129.68.9) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Tue, 4 Jul 2023 03:48:11 -0700 Received: from nvidia.com (10.127.8.12) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37 via Frontend Transport; Tue, 4 Jul 2023 03:48:09 -0700 From: Itamar Gozlan To: , , , , , Ori Kam CC: , Shun Hao Subject: [v1 3/5] net/mlx5/hws: remove duplicated reformat type Date: Tue, 4 Jul 2023 13:46:43 +0300 Message-ID: <20230704104645.19800-3-igozlan@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20230704104645.19800-1-igozlan@nvidia.com> References: <20230702045758.23244-4-igozlan@nvidia.com> <20230704104645.19800-1-igozlan@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT076:EE_|MN2PR12MB4189:EE_ X-MS-Office365-Filtering-Correlation-Id: 86441812-9f92-4b7a-6aa4-08db7c7c3057 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: GF0u86s4NH8E4XgD5xObdB4SUTjcIBpsUXsybLrahvlZrxjduMdQzd7r3s8CvnzRzuKdLt0Ri8CoSPfhXpTTwpHxYdB9qqRDivSoJ62QBST6vQS/q1CjyRpCWoma1qoHgncgPcemN9/wDm+4QBXOQRPjfCYcwmugX/D4EHoMAfRbNRlKVIzVXg/8VULshCHfzqGaxINN+sNHDk3PyUIR5+VIy/NKDCCws/5y9Qw7T5urEFQf1FTorl2ij2wzzZcJ7hFgjZYo11SA+CqhwF0AVvj4miBRvU14sSHfWr3UNpBc77HNZlw87qQFex9HfB5LUoYxnodUjZb6QP3B1JB3rxhR/UbkwPCa/KtlYfXRMeRsWdjpbVnFAVCPDht437uhGCF8CazcW95ukyltXfJbNSKgDkGCB6lySVdRdg5D9KSpAgyyrSq7HxBJ2pXsuhnxyHqqF4gOPg+5sHJDXdIq9x7V7RpP2QIDHaMZz3+6Nd4Sb+HcMfkzn01zcxRiQkfwe9C4megH6PiafFeqtxPwY+qWSB5Lq96Uh7oVLmg/0Le//HGvbRVA9z5UDnAV1a0Y5c3bhANvMpzE0wVodM6D9FJk1+JXoc3vun7LNV6XWhRoQqc+3Taz7LKxbVBU908I00HCpGUrqGW/GahsHhFtdtC8viisGx3sFCFaxvIaqcksr2rdJY5WRIimEsDaGSVezhKPVlXZnQgWKDkDZRRi9/Rv71zhCQAFQWardN8LeK1SzjX02MJfSQ4nZdSHWb29 X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230028)(4636009)(39860400002)(376002)(346002)(396003)(136003)(451199021)(36840700001)(40470700004)(46966006)(336012)(40460700003)(41300700001)(86362001)(7696005)(30864003)(6666004)(82310400005)(2616005)(7636003)(107886003)(6286002)(83380400001)(356005)(82740400003)(186003)(1076003)(426003)(26005)(47076005)(36860700001)(40480700001)(55016003)(54906003)(110136005)(2906002)(478600001)(36756003)(316002)(70586007)(4326008)(70206006)(6636002)(8936002)(8676002)(5660300002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jul 2023 10:48:23.0318 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 86441812-9f92-4b7a-6aa4-08db7c7c3057 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT076.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4189 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shun Hao Currently there are two enum definitions for reformat type: mlx5dr_action_reformat_type and mlx5dr_action_type. They are actually the same. This patch remove the unnecessary mlx5dr_action_reformat_type so use only one definition for reformat type. Signed-off-by: Shun Hao Acked-by: Matan Azrad --- drivers/net/mlx5/hws/mlx5dr.h | 19 ++--- drivers/net/mlx5/hws/mlx5dr_action.c | 110 ++++++++++---------------- drivers/net/mlx5/hws/mlx5dr_debug.c | 8 +- drivers/net/mlx5/hws/mlx5dr_pat_arg.c | 2 +- drivers/net/mlx5/mlx5_flow_hw.c | 34 ++++---- 5 files changed, 68 insertions(+), 105 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr.h b/drivers/net/mlx5/hws/mlx5dr.h index 7942fb0a8f..7d5af4c9bb 100644 --- a/drivers/net/mlx5/hws/mlx5dr.h +++ b/drivers/net/mlx5/hws/mlx5dr.h @@ -29,10 +29,10 @@ enum mlx5dr_matcher_resource_mode { enum mlx5dr_action_type { MLX5DR_ACTION_TYP_LAST, - MLX5DR_ACTION_TYP_TNL_L2_TO_L2, - MLX5DR_ACTION_TYP_L2_TO_TNL_L2, - MLX5DR_ACTION_TYP_TNL_L3_TO_L2, - MLX5DR_ACTION_TYP_L2_TO_TNL_L3, + MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2, + MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2, + MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2, + MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3, MLX5DR_ACTION_TYP_DROP, MLX5DR_ACTION_TYP_TIR, MLX5DR_ACTION_TYP_FT, @@ -62,13 +62,6 @@ enum mlx5dr_action_flags { MLX5DR_ACTION_FLAG_SHARED = 1 << 6, }; -enum mlx5dr_action_reformat_type { - MLX5DR_ACTION_REFORMAT_TYPE_TNL_L2_TO_L2, - MLX5DR_ACTION_REFORMAT_TYPE_L2_TO_TNL_L2, - MLX5DR_ACTION_REFORMAT_TYPE_TNL_L3_TO_L2, - MLX5DR_ACTION_REFORMAT_TYPE_L2_TO_TNL_L3, -}; - enum mlx5dr_action_aso_meter_color { MLX5DR_ACTION_ASO_METER_COLOR_RED = 0x0, MLX5DR_ACTION_ASO_METER_COLOR_YELLOW = 0x1, @@ -487,7 +480,7 @@ mlx5dr_action_create_counter(struct mlx5dr_context *ctx, * @param[in] ctx * The context in which the new action will be created. * @param[in] reformat_type - * Type of reformat. + * Type of reformat prefixed with MLX5DR_ACTION_TYP_REFORMAT. * @param[in] data_sz * Size in bytes of data. * @param[in] inline_data @@ -500,7 +493,7 @@ mlx5dr_action_create_counter(struct mlx5dr_context *ctx, */ struct mlx5dr_action * mlx5dr_action_create_reformat(struct mlx5dr_context *ctx, - enum mlx5dr_action_reformat_type reformat_type, + enum mlx5dr_action_type reformat_type, size_t data_sz, void *inline_data, uint32_t log_bulk_size, diff --git a/drivers/net/mlx5/hws/mlx5dr_action.c b/drivers/net/mlx5/hws/mlx5dr_action.c index e2db85940c..851cee8802 100644 --- a/drivers/net/mlx5/hws/mlx5dr_action.c +++ b/drivers/net/mlx5/hws/mlx5dr_action.c @@ -18,8 +18,8 @@ static const uint32_t action_order_arr[MLX5DR_TABLE_TYPE_MAX][MLX5DR_ACTION_TYP_MAX] = { [MLX5DR_TABLE_TYPE_NIC_RX] = { BIT(MLX5DR_ACTION_TYP_TAG), - BIT(MLX5DR_ACTION_TYP_TNL_L2_TO_L2) | - BIT(MLX5DR_ACTION_TYP_TNL_L3_TO_L2), + BIT(MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2) | + BIT(MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2), BIT(MLX5DR_ACTION_TYP_POP_VLAN), BIT(MLX5DR_ACTION_TYP_POP_VLAN), BIT(MLX5DR_ACTION_TYP_CTR), @@ -28,8 +28,8 @@ static const uint32_t action_order_arr[MLX5DR_TABLE_TYPE_MAX][MLX5DR_ACTION_TYP_ BIT(MLX5DR_ACTION_TYP_PUSH_VLAN), BIT(MLX5DR_ACTION_TYP_PUSH_VLAN), BIT(MLX5DR_ACTION_TYP_MODIFY_HDR), - BIT(MLX5DR_ACTION_TYP_L2_TO_TNL_L2) | - BIT(MLX5DR_ACTION_TYP_L2_TO_TNL_L3), + BIT(MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2) | + BIT(MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3), BIT(MLX5DR_ACTION_TYP_FT) | BIT(MLX5DR_ACTION_TYP_MISS) | BIT(MLX5DR_ACTION_TYP_TIR) | @@ -46,8 +46,8 @@ static const uint32_t action_order_arr[MLX5DR_TABLE_TYPE_MAX][MLX5DR_ACTION_TYP_ BIT(MLX5DR_ACTION_TYP_PUSH_VLAN), BIT(MLX5DR_ACTION_TYP_PUSH_VLAN), BIT(MLX5DR_ACTION_TYP_MODIFY_HDR), - BIT(MLX5DR_ACTION_TYP_L2_TO_TNL_L2) | - BIT(MLX5DR_ACTION_TYP_L2_TO_TNL_L3), + BIT(MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2) | + BIT(MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3), BIT(MLX5DR_ACTION_TYP_FT) | BIT(MLX5DR_ACTION_TYP_MISS) | BIT(MLX5DR_ACTION_TYP_DROP) | @@ -55,8 +55,8 @@ static const uint32_t action_order_arr[MLX5DR_TABLE_TYPE_MAX][MLX5DR_ACTION_TYP_ BIT(MLX5DR_ACTION_TYP_LAST), }, [MLX5DR_TABLE_TYPE_FDB] = { - BIT(MLX5DR_ACTION_TYP_TNL_L2_TO_L2) | - BIT(MLX5DR_ACTION_TYP_TNL_L3_TO_L2), + BIT(MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2) | + BIT(MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2), BIT(MLX5DR_ACTION_TYP_POP_VLAN), BIT(MLX5DR_ACTION_TYP_POP_VLAN), BIT(MLX5DR_ACTION_TYP_CTR), @@ -65,8 +65,8 @@ static const uint32_t action_order_arr[MLX5DR_TABLE_TYPE_MAX][MLX5DR_ACTION_TYP_ BIT(MLX5DR_ACTION_TYP_PUSH_VLAN), BIT(MLX5DR_ACTION_TYP_PUSH_VLAN), BIT(MLX5DR_ACTION_TYP_MODIFY_HDR), - BIT(MLX5DR_ACTION_TYP_L2_TO_TNL_L2) | - BIT(MLX5DR_ACTION_TYP_L2_TO_TNL_L3), + BIT(MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2) | + BIT(MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3), BIT(MLX5DR_ACTION_TYP_FT) | BIT(MLX5DR_ACTION_TYP_MISS) | BIT(MLX5DR_ACTION_TYP_VPORT) | @@ -292,10 +292,10 @@ int mlx5dr_action_root_build_attr(struct mlx5dr_rule_action rule_actions[], case MLX5DR_ACTION_TYP_DROP: attr[i].type = MLX5DV_FLOW_ACTION_DROP; break; - case MLX5DR_ACTION_TYP_TNL_L2_TO_L2: - case MLX5DR_ACTION_TYP_L2_TO_TNL_L2: - case MLX5DR_ACTION_TYP_TNL_L3_TO_L2: - case MLX5DR_ACTION_TYP_L2_TO_TNL_L3: + case MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2: + case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2: + case MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2: + case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3: case MLX5DR_ACTION_TYP_MODIFY_HDR: attr[i].type = MLX5DV_FLOW_ACTION_IBV_FLOW_ACTION; attr[i].action = action->flow_action; @@ -503,7 +503,7 @@ static void mlx5dr_action_fill_stc_attr(struct mlx5dr_action *action, attr->action_offset = MLX5DR_ACTION_OFFSET_HIT; attr->dest_tir_num = obj->id; break; - case MLX5DR_ACTION_TYP_TNL_L3_TO_L2: + case MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2: case MLX5DR_ACTION_TYP_MODIFY_HDR: attr->action_offset = MLX5DR_ACTION_OFFSET_DW6; if (action->modify_header.num_of_actions == 1) { @@ -529,14 +529,14 @@ static void mlx5dr_action_fill_stc_attr(struct mlx5dr_action *action, attr->action_offset = MLX5DR_ACTION_OFFSET_HIT; attr->dest_table_id = action->root_tbl.sa->id; break; - case MLX5DR_ACTION_TYP_TNL_L2_TO_L2: + case MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2: attr->action_type = MLX5_IFC_STC_ACTION_TYPE_HEADER_REMOVE; attr->action_offset = MLX5DR_ACTION_OFFSET_DW5; attr->remove_header.decap = 1; attr->remove_header.start_anchor = MLX5_HEADER_ANCHOR_PACKET_START; attr->remove_header.end_anchor = MLX5_HEADER_ANCHOR_INNER_MAC; break; - case MLX5DR_ACTION_TYP_L2_TO_TNL_L2: + case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2: attr->action_type = MLX5_IFC_STC_ACTION_TYPE_HEADER_INSERT; attr->action_offset = MLX5DR_ACTION_OFFSET_DW6; attr->insert_header.encap = 1; @@ -544,7 +544,7 @@ static void mlx5dr_action_fill_stc_attr(struct mlx5dr_action *action, attr->insert_header.arg_id = action->reformat.arg_obj->id; attr->insert_header.header_size = action->reformat.header_size; break; - case MLX5DR_ACTION_TYP_L2_TO_TNL_L3: + case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3: attr->action_type = MLX5_IFC_STC_ACTION_TYPE_HEADER_INSERT; attr->action_offset = MLX5DR_ACTION_OFFSET_DW6; attr->insert_header.encap = 1; @@ -1128,49 +1128,24 @@ mlx5dr_action_create_pop_vlan(struct mlx5dr_context *ctx, uint32_t flags) return NULL; } -static int -mlx5dr_action_conv_reformat_type_to_action(uint32_t reformat_type, - enum mlx5dr_action_type *action_type) -{ - switch (reformat_type) { - case MLX5DR_ACTION_REFORMAT_TYPE_TNL_L2_TO_L2: - *action_type = MLX5DR_ACTION_TYP_TNL_L2_TO_L2; - break; - case MLX5DR_ACTION_REFORMAT_TYPE_L2_TO_TNL_L2: - *action_type = MLX5DR_ACTION_TYP_L2_TO_TNL_L2; - break; - case MLX5DR_ACTION_REFORMAT_TYPE_TNL_L3_TO_L2: - *action_type = MLX5DR_ACTION_TYP_TNL_L3_TO_L2; - break; - case MLX5DR_ACTION_REFORMAT_TYPE_L2_TO_TNL_L3: - *action_type = MLX5DR_ACTION_TYP_L2_TO_TNL_L3; - break; - default: - DR_LOG(ERR, "Invalid reformat type requested"); - rte_errno = ENOTSUP; - return rte_errno; - } - return 0; -} - static void mlx5dr_action_conv_reformat_to_verbs(uint32_t action_type, uint32_t *verb_reformat_type) { switch (action_type) { - case MLX5DR_ACTION_TYP_TNL_L2_TO_L2: + case MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2: *verb_reformat_type = MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2; break; - case MLX5DR_ACTION_TYP_L2_TO_TNL_L2: + case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2: *verb_reformat_type = MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL; break; - case MLX5DR_ACTION_TYP_TNL_L3_TO_L2: + case MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2: *verb_reformat_type = MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2; break; - case MLX5DR_ACTION_TYP_L2_TO_TNL_L3: + case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3: *verb_reformat_type = MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL; break; @@ -1470,16 +1445,16 @@ mlx5dr_action_create_reformat_hws(struct mlx5dr_context *ctx, int ret; switch (action->type) { - case MLX5DR_ACTION_TYP_TNL_L2_TO_L2: + case MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2: ret = mlx5dr_action_create_stcs(action, NULL); break; - case MLX5DR_ACTION_TYP_L2_TO_TNL_L2: + case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2: ret = mlx5dr_action_handle_l2_to_tunnel_l2(ctx, data_sz, data, bulk_size, action); break; - case MLX5DR_ACTION_TYP_L2_TO_TNL_L3: + case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3: ret = mlx5dr_action_handle_l2_to_tunnel_l3(ctx, data_sz, data, bulk_size, action); break; - case MLX5DR_ACTION_TYP_TNL_L3_TO_L2: + case MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2: ret = mlx5dr_action_handle_tunnel_l3_to_l2(ctx, data_sz, data, bulk_size, action); break; @@ -1494,21 +1469,16 @@ mlx5dr_action_create_reformat_hws(struct mlx5dr_context *ctx, struct mlx5dr_action * mlx5dr_action_create_reformat(struct mlx5dr_context *ctx, - enum mlx5dr_action_reformat_type reformat_type, + enum mlx5dr_action_type reformat_type, size_t data_sz, void *inline_data, uint32_t log_bulk_size, uint32_t flags) { - enum mlx5dr_action_type action_type; struct mlx5dr_action *action; int ret; - ret = mlx5dr_action_conv_reformat_type_to_action(reformat_type, &action_type); - if (ret) - return NULL; - - action = mlx5dr_action_create_generic(ctx, flags, action_type); + action = mlx5dr_action_create_generic(ctx, flags, reformat_type); if (!action) return NULL; @@ -1712,7 +1682,7 @@ static void mlx5dr_action_destroy_hws(struct mlx5dr_action *action) case MLX5DR_ACTION_TYP_DROP: case MLX5DR_ACTION_TYP_CTR: case MLX5DR_ACTION_TYP_FT: - case MLX5DR_ACTION_TYP_TNL_L2_TO_L2: + case MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2: case MLX5DR_ACTION_TYP_ASO_METER: case MLX5DR_ACTION_TYP_ASO_CT: case MLX5DR_ACTION_TYP_PUSH_VLAN: @@ -1726,18 +1696,18 @@ static void mlx5dr_action_destroy_hws(struct mlx5dr_action *action) mlx5dr_action_destroy_stcs(action); mlx5dr_action_put_shared_stc(action, MLX5DR_CONTEXT_SHARED_STC_POP); break; - case MLX5DR_ACTION_TYP_TNL_L3_TO_L2: + case MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2: case MLX5DR_ACTION_TYP_MODIFY_HDR: mlx5dr_action_destroy_stcs(action); if (action->modify_header.num_of_actions > 1) mlx5dr_pat_arg_destroy_modify_header(action->ctx, action); break; - case MLX5DR_ACTION_TYP_L2_TO_TNL_L3: + case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3: mlx5dr_action_destroy_stcs(action); mlx5dr_action_put_shared_stc(action, MLX5DR_CONTEXT_SHARED_STC_DECAP); mlx5dr_cmd_destroy_obj(action->reformat.arg_obj); break; - case MLX5DR_ACTION_TYP_L2_TO_TNL_L2: + case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2: mlx5dr_action_destroy_stcs(action); mlx5dr_cmd_destroy_obj(action->reformat.arg_obj); break; @@ -1747,10 +1717,10 @@ static void mlx5dr_action_destroy_hws(struct mlx5dr_action *action) static void mlx5dr_action_destroy_root(struct mlx5dr_action *action) { switch (action->type) { - case MLX5DR_ACTION_TYP_TNL_L2_TO_L2: - case MLX5DR_ACTION_TYP_L2_TO_TNL_L2: - case MLX5DR_ACTION_TYP_TNL_L3_TO_L2: - case MLX5DR_ACTION_TYP_L2_TO_TNL_L3: + case MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2: + case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2: + case MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2: + case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3: case MLX5DR_ACTION_TYP_MODIFY_HDR: ibv_destroy_flow_action(action->flow_action); break; @@ -2256,7 +2226,7 @@ int mlx5dr_action_template_process(struct mlx5dr_action_template *at) setter->idx_double = i; break; - case MLX5DR_ACTION_TYP_TNL_L2_TO_L2: + case MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2: /* Single remove header to header */ setter = mlx5dr_action_setter_find_first(last_setter, ASF_SINGLE1 | ASF_MODIFY); setter->flags |= ASF_SINGLE1 | ASF_REMOVE | ASF_REPARSE; @@ -2264,7 +2234,7 @@ int mlx5dr_action_template_process(struct mlx5dr_action_template *at) setter->idx_single = i; break; - case MLX5DR_ACTION_TYP_L2_TO_TNL_L2: + case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2: /* Double insert header with pointer */ setter = mlx5dr_action_setter_find_first(last_setter, ASF_DOUBLE); setter->flags |= ASF_DOUBLE | ASF_REPARSE; @@ -2272,7 +2242,7 @@ int mlx5dr_action_template_process(struct mlx5dr_action_template *at) setter->idx_double = i; break; - case MLX5DR_ACTION_TYP_L2_TO_TNL_L3: + case MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3: /* Single remove + Double insert header with pointer */ setter = mlx5dr_action_setter_find_first(last_setter, ASF_SINGLE1 | ASF_DOUBLE); setter->flags |= ASF_SINGLE1 | ASF_DOUBLE | ASF_REPARSE | ASF_REMOVE; @@ -2282,7 +2252,7 @@ int mlx5dr_action_template_process(struct mlx5dr_action_template *at) setter->idx_single = i; break; - case MLX5DR_ACTION_TYP_TNL_L3_TO_L2: + case MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2: /* Double modify header list with remove and push inline */ setter = mlx5dr_action_setter_find_first(last_setter, ASF_DOUBLE | ASF_REMOVE); diff --git a/drivers/net/mlx5/hws/mlx5dr_debug.c b/drivers/net/mlx5/hws/mlx5dr_debug.c index d249f8d869..5064b23b7d 100644 --- a/drivers/net/mlx5/hws/mlx5dr_debug.c +++ b/drivers/net/mlx5/hws/mlx5dr_debug.c @@ -6,10 +6,10 @@ const char *mlx5dr_debug_action_type_str[] = { [MLX5DR_ACTION_TYP_LAST] = "LAST", - [MLX5DR_ACTION_TYP_TNL_L2_TO_L2] = "TNL_L2_TO_L2", - [MLX5DR_ACTION_TYP_L2_TO_TNL_L2] = "L2_TO_TNL_L2", - [MLX5DR_ACTION_TYP_TNL_L3_TO_L2] = "TNL_L3_TO_L2", - [MLX5DR_ACTION_TYP_L2_TO_TNL_L3] = "L2_TO_TNL_L3", + [MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2] = "TNL_L2_TO_L2", + [MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2] = "L2_TO_TNL_L2", + [MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2] = "TNL_L3_TO_L2", + [MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3] = "L2_TO_TNL_L3", [MLX5DR_ACTION_TYP_DROP] = "DROP", [MLX5DR_ACTION_TYP_TIR] = "TIR", [MLX5DR_ACTION_TYP_FT] = "FT", diff --git a/drivers/net/mlx5/hws/mlx5dr_pat_arg.c b/drivers/net/mlx5/hws/mlx5dr_pat_arg.c index bedaedb677..309a61d477 100644 --- a/drivers/net/mlx5/hws/mlx5dr_pat_arg.c +++ b/drivers/net/mlx5/hws/mlx5dr_pat_arg.c @@ -73,7 +73,7 @@ static bool mlx5dr_pat_compare_pattern(enum mlx5dr_action_type cur_type, return false; /* All decap-l3 look the same, only change is the num of actions */ - if (type == MLX5DR_ACTION_TYP_TNL_L3_TO_L2) + if (type == MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2) return true; for (i = 0; i < num_of_actions; i++) { diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 330386df77..e1adc081c1 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -1420,7 +1420,7 @@ __flow_hw_actions_translate(struct rte_eth_dev *dev, struct rte_flow_action *actions = at->actions; struct rte_flow_action *action_start = actions; struct rte_flow_action *masks = at->masks; - enum mlx5dr_action_reformat_type refmt_type = 0; + enum mlx5dr_action_type refmt_type = 0; const struct rte_flow_action_raw_encap *raw_encap_data; const struct rte_flow_item *enc_item = NULL, *enc_item_m = NULL; uint16_t reformat_src = 0; @@ -1575,7 +1575,7 @@ __flow_hw_actions_translate(struct rte_eth_dev *dev, masks->conf)->definition; reformat_used = true; reformat_src = actions - action_start; - refmt_type = MLX5DR_ACTION_REFORMAT_TYPE_L2_TO_TNL_L2; + refmt_type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2; break; case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: MLX5_ASSERT(!reformat_used); @@ -1586,13 +1586,13 @@ __flow_hw_actions_translate(struct rte_eth_dev *dev, masks->conf)->definition; reformat_used = true; reformat_src = actions - action_start; - refmt_type = MLX5DR_ACTION_REFORMAT_TYPE_L2_TO_TNL_L2; + refmt_type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2; break; case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP: case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP: MLX5_ASSERT(!reformat_used); reformat_used = true; - refmt_type = MLX5DR_ACTION_REFORMAT_TYPE_TNL_L2_TO_L2; + refmt_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2; break; case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: raw_encap_data = @@ -1608,18 +1608,18 @@ __flow_hw_actions_translate(struct rte_eth_dev *dev, if (reformat_used) { refmt_type = data_size < MLX5_ENCAPSULATION_DECISION_SIZE ? - MLX5DR_ACTION_REFORMAT_TYPE_TNL_L3_TO_L2 : - MLX5DR_ACTION_REFORMAT_TYPE_L2_TO_TNL_L3; + MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2 : + MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3; } else { reformat_used = true; refmt_type = - MLX5DR_ACTION_REFORMAT_TYPE_L2_TO_TNL_L2; + MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2; } reformat_src = actions - action_start; break; case RTE_FLOW_ACTION_TYPE_RAW_DECAP: reformat_used = true; - refmt_type = MLX5DR_ACTION_REFORMAT_TYPE_TNL_L2_TO_L2; + refmt_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2; break; case RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL: flow_hw_translate_group(dev, cfg, attr->group, @@ -4523,10 +4523,10 @@ static enum mlx5dr_action_type mlx5_hw_dr_action_types[] = { [RTE_FLOW_ACTION_TYPE_JUMP] = MLX5DR_ACTION_TYP_FT, [RTE_FLOW_ACTION_TYPE_QUEUE] = MLX5DR_ACTION_TYP_TIR, [RTE_FLOW_ACTION_TYPE_RSS] = MLX5DR_ACTION_TYP_TIR, - [RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP] = MLX5DR_ACTION_TYP_L2_TO_TNL_L2, - [RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP] = MLX5DR_ACTION_TYP_L2_TO_TNL_L2, - [RTE_FLOW_ACTION_TYPE_VXLAN_DECAP] = MLX5DR_ACTION_TYP_TNL_L2_TO_L2, - [RTE_FLOW_ACTION_TYPE_NVGRE_DECAP] = MLX5DR_ACTION_TYP_TNL_L2_TO_L2, + [RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP] = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2, + [RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP] = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2, + [RTE_FLOW_ACTION_TYPE_VXLAN_DECAP] = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2, + [RTE_FLOW_ACTION_TYPE_NVGRE_DECAP] = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2, [RTE_FLOW_ACTION_TYPE_MODIFY_FIELD] = MLX5DR_ACTION_TYP_MODIFY_HDR, [RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT] = MLX5DR_ACTION_TYP_VPORT, [RTE_FLOW_ACTION_TYPE_CONNTRACK] = MLX5DR_ACTION_TYP_ASO_CT, @@ -4604,7 +4604,7 @@ flow_hw_dr_actions_template_create(struct rte_flow_actions_template *at) enum mlx5dr_action_type action_types[MLX5_HW_MAX_ACTS] = { MLX5DR_ACTION_TYP_LAST }; unsigned int i; uint16_t curr_off; - enum mlx5dr_action_type reformat_act_type = MLX5DR_ACTION_TYP_TNL_L2_TO_L2; + enum mlx5dr_action_type reformat_act_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2; uint16_t reformat_off = UINT16_MAX; uint16_t mhdr_off = UINT16_MAX; uint16_t cnt_off = UINT16_MAX; @@ -4642,16 +4642,16 @@ flow_hw_dr_actions_template_create(struct rte_flow_actions_template *at) data_size = raw_encap_data->size; if (reformat_off != UINT16_MAX) { reformat_act_type = data_size < MLX5_ENCAPSULATION_DECISION_SIZE ? - MLX5DR_ACTION_TYP_TNL_L3_TO_L2 : - MLX5DR_ACTION_TYP_L2_TO_TNL_L3; + MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2 : + MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3; } else { reformat_off = curr_off++; - reformat_act_type = MLX5DR_ACTION_TYP_L2_TO_TNL_L2; + reformat_act_type = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2; } break; case RTE_FLOW_ACTION_TYPE_RAW_DECAP: reformat_off = curr_off++; - reformat_act_type = MLX5DR_ACTION_TYP_TNL_L2_TO_L2; + reformat_act_type = MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2; break; case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD: if (mhdr_off == UINT16_MAX) { From patchwork Tue Jul 4 10:46:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Itamar Gozlan X-Patchwork-Id: 129247 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7CBD842DD1; Tue, 4 Jul 2023 12:48:35 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 67FE042D10; Tue, 4 Jul 2023 12:48:35 +0200 (CEST) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2089.outbound.protection.outlook.com [40.107.244.89]) by mails.dpdk.org (Postfix) with ESMTP id D4BC242D20 for ; Tue, 4 Jul 2023 12:48:32 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=A7OAKW4GmQStcuLvjKiNQ2kGfT/vO7uc1Ljv5GrCx9UwOaJZKrv2CNhMRHV6Bx0uqig04Zz/lNCD1+UvpAd44IYNplJkWNTE8Cbx5IZeSDbwiERIdVWwYhNSv9AJbcIgtXc3yJgAlR1dZWNUJep+NEypEc1jFl9NXyW+K7FtW2CIBrmOxUNjSK3w/P4ZJ4ZjosLyxUhlJlP0T4mOanyWhAMS1tjkj8u7m8TJgz3aVwKc8iw+aX7i7CIX8Kd4mzdLMA1YoK/vyDiFjwC3p3acIKVQ2zXRku7NLQm9y6OATRjeA5Org8nSQlyskVdPg9gR/XUhNpee/bVVs0SBy+cFWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=GMxZjpBQPQZmU9nbtVcE/zi/wJ9+03qTuSLVyC82A+w=; b=RFV3AUPjOyQy+spSU3JE7HSPsIGp3VOcdVBPoj9LIXydO8SX8tMxSVt+saAV+KhPim31kGaDq4EMln/0wNaO0vJY6AzkqtNnwcdBGnjqOldesD5+PyIQdmhZPT3BpjVLhB6pg4viS8/CEd2nZElINC9heVhwchBVHgqje+YBZXFcGfdwYfc5jLjoqG9YCWAhGoIxHEvIdtM3LQd5eA5jNGAYoeZ1HopuqVekU75ggCIjCXXdcJUQH/XHARnse4e+eaVsY0azMdeYSev5TEoOeQX7JETiA4HACECK5mTIkSVqoDSJIibYPXXCFnuXpWhwrLgh9dn7b+dt9CuhOqLvHQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=GMxZjpBQPQZmU9nbtVcE/zi/wJ9+03qTuSLVyC82A+w=; b=Zq4aKb1g4scA2fm5Nyxpwb//xn/I/IwS08SS3Y2aufa3gs6GQThhsqh7PVhV8+8eiZPEGRr6PVrjrCEP7eIDGSjqhXS+Pj3109gvB7DwbeCPVpEnqh3tfTebtyVI4OCnFp1m7/GCrlEtJzH2yFh9cXP97ErrUQ23cIs9fiXCralIg3kHedNmnm/iDz+bCVAA0xR1aiticxMwGcZphc2wkA5N6xV0xR9/vStQ15OV1+S7JWttbdJ5TUBvFkUURarhIOxcXcWNS21vbPWiCnWsmCKr8TZ7YvpjOpSt8seyJXRVLaeIliFRlx82SYgxGw+hkYD/qZCf5sSTSUbDgLSGBg== Received: from MW4PR04CA0303.namprd04.prod.outlook.com (2603:10b6:303:82::8) by DM4PR12MB5842.namprd12.prod.outlook.com (2603:10b6:8:65::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6544.19; Tue, 4 Jul 2023 10:48:31 +0000 Received: from CO1NAM11FT019.eop-nam11.prod.protection.outlook.com (2603:10b6:303:82:cafe::7) by MW4PR04CA0303.outlook.office365.com (2603:10b6:303:82::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6544.31 via Frontend Transport; Tue, 4 Jul 2023 10:48:30 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CO1NAM11FT019.mail.protection.outlook.com (10.13.175.57) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6521.44 via Frontend Transport; Tue, 4 Jul 2023 10:48:30 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Tue, 4 Jul 2023 03:48:19 -0700 Received: from rnnvmail203.nvidia.com (10.129.68.9) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Tue, 4 Jul 2023 03:48:18 -0700 Received: from nvidia.com (10.127.8.12) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37 via Frontend Transport; Tue, 4 Jul 2023 03:48:16 -0700 From: Itamar Gozlan To: , , , , , Ori Kam CC: Subject: [v1 4/5] net/mlx5/hws: renaming FT to TBL Date: Tue, 4 Jul 2023 13:46:44 +0300 Message-ID: <20230704104645.19800-4-igozlan@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20230704104645.19800-1-igozlan@nvidia.com> References: <20230702045758.23244-4-igozlan@nvidia.com> <20230704104645.19800-1-igozlan@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT019:EE_|DM4PR12MB5842:EE_ X-MS-Office365-Filtering-Correlation-Id: b7418193-9730-46d6-0ac6-08db7c7c34ae X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Yo9p884FCbnVYNU+NhqD9B8KNLALtPCrhc0YLvMjDtuy5EDr4RDXbo+X/5Su5LO8YqCOMM6F1KAUlw7bIJbOuwuvhq99cdBGTNb40gvDVsaD47dQU8KTEHDEp+aFGcMslkhDi67Jd7jfx0+0HNDJBAE2mEN241cGAKH+Y4lwJGX6Krs2wUxVdWVwoCRJPUb15eC5au8DN47z9zQmWhOHPPrAExoXaEiBhZzwyOsv/KiFOtNfoKSFXeyxPm9FzMQe6xKxtJeiwsVQllkf6YVBLnINi9srI0q/nfKbCqzC6N9pBpSJXABxibxeO7wTs8v25FWBxfIuvu9khmbi4x9E/DxuyoO85Rcn+7PD1p2UuNRgGdznE3nRW+ohdGJh68KfEoF9G1w5g19i/5vjTVV/d8tOtCzUOk541oRUai5dxy4N9yrXQiFDhfBHHn8QP8jXtt8WZ9det66Ot83OCOp/HUYCGpR1JhloJ8Cew3vYvy6M2bOyYx4oV1sRmsfv+jCsHxWssMkeCxe0q544w7a8N/d7nh0w1w9J7Z3BSy2mnDx2Rnyr54VsVcjwxNZA9UsvB8EOUFt8Zo8iKeNLm3Nxx9IpOdQ1uZXIm8dzmgesCNjuGSEkGHjuFJPTKmvi4MYapn3vlGK1BiSEMPdj6vn84IsYO18IVowrNZm4U3CE/oHJno5bAhG6KMkI9egTsx7rMzqeBnGMqLkfZWDU9HE5PmD9Ude0Mb/YEJxFNKFnbGWIXv8k2w01n+EkzsrV++j6 X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230028)(4636009)(346002)(396003)(39860400002)(136003)(376002)(451199021)(46966006)(36840700001)(40470700004)(55016003)(426003)(83380400001)(40460700003)(336012)(47076005)(2616005)(2906002)(82740400003)(7636003)(356005)(36860700001)(36756003)(40480700001)(8936002)(8676002)(82310400005)(110136005)(5660300002)(86362001)(4326008)(41300700001)(70586007)(6666004)(316002)(70206006)(7696005)(478600001)(186003)(6286002)(6636002)(1076003)(26005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jul 2023 10:48:30.3104 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b7418193-9730-46d6-0ac6-08db7c7c34ae X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT019.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5842 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org An action naming change is made to describe the action better and avoid implicit meaning. Signed-off-by: Itamar Gozlan Acked-by: Matan Azrad --- drivers/net/mlx5/hws/mlx5dr.h | 2 +- drivers/net/mlx5/hws/mlx5dr_action.c | 16 ++++++++-------- drivers/net/mlx5/hws/mlx5dr_debug.c | 2 +- drivers/net/mlx5/mlx5_flow_hw.c | 4 ++-- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr.h b/drivers/net/mlx5/hws/mlx5dr.h index 7d5af4c9bb..ec2230d136 100644 --- a/drivers/net/mlx5/hws/mlx5dr.h +++ b/drivers/net/mlx5/hws/mlx5dr.h @@ -35,7 +35,7 @@ enum mlx5dr_action_type { MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3, MLX5DR_ACTION_TYP_DROP, MLX5DR_ACTION_TYP_TIR, - MLX5DR_ACTION_TYP_FT, + MLX5DR_ACTION_TYP_TBL, MLX5DR_ACTION_TYP_CTR, MLX5DR_ACTION_TYP_TAG, MLX5DR_ACTION_TYP_MODIFY_HDR, diff --git a/drivers/net/mlx5/hws/mlx5dr_action.c b/drivers/net/mlx5/hws/mlx5dr_action.c index 851cee8802..74f4e60863 100644 --- a/drivers/net/mlx5/hws/mlx5dr_action.c +++ b/drivers/net/mlx5/hws/mlx5dr_action.c @@ -30,7 +30,7 @@ static const uint32_t action_order_arr[MLX5DR_TABLE_TYPE_MAX][MLX5DR_ACTION_TYP_ BIT(MLX5DR_ACTION_TYP_MODIFY_HDR), BIT(MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2) | BIT(MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3), - BIT(MLX5DR_ACTION_TYP_FT) | + BIT(MLX5DR_ACTION_TYP_TBL) | BIT(MLX5DR_ACTION_TYP_MISS) | BIT(MLX5DR_ACTION_TYP_TIR) | BIT(MLX5DR_ACTION_TYP_DROP) | @@ -48,7 +48,7 @@ static const uint32_t action_order_arr[MLX5DR_TABLE_TYPE_MAX][MLX5DR_ACTION_TYP_ BIT(MLX5DR_ACTION_TYP_MODIFY_HDR), BIT(MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2) | BIT(MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3), - BIT(MLX5DR_ACTION_TYP_FT) | + BIT(MLX5DR_ACTION_TYP_TBL) | BIT(MLX5DR_ACTION_TYP_MISS) | BIT(MLX5DR_ACTION_TYP_DROP) | BIT(MLX5DR_ACTION_TYP_DEST_ROOT), @@ -67,7 +67,7 @@ static const uint32_t action_order_arr[MLX5DR_TABLE_TYPE_MAX][MLX5DR_ACTION_TYP_ BIT(MLX5DR_ACTION_TYP_MODIFY_HDR), BIT(MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2) | BIT(MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3), - BIT(MLX5DR_ACTION_TYP_FT) | + BIT(MLX5DR_ACTION_TYP_TBL) | BIT(MLX5DR_ACTION_TYP_MISS) | BIT(MLX5DR_ACTION_TYP_VPORT) | BIT(MLX5DR_ACTION_TYP_DROP) | @@ -275,7 +275,7 @@ int mlx5dr_action_root_build_attr(struct mlx5dr_rule_action rule_actions[], action = rule_actions[i].action; switch (action->type) { - case MLX5DR_ACTION_TYP_FT: + case MLX5DR_ACTION_TYP_TBL: case MLX5DR_ACTION_TYP_TIR: attr[i].type = MLX5DV_FLOW_ACTION_DEST_DEVX; attr[i].obj = action->devx_obj; @@ -519,7 +519,7 @@ static void mlx5dr_action_fill_stc_attr(struct mlx5dr_action *action, attr->modify_header.pattern_id = action->modify_header.pattern_obj->id; } break; - case MLX5DR_ACTION_TYP_FT: + case MLX5DR_ACTION_TYP_TBL: attr->action_type = MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_FT; attr->action_offset = MLX5DR_ACTION_OFFSET_HIT; attr->dest_table_id = obj->id; @@ -747,7 +747,7 @@ mlx5dr_action_create_dest_table(struct mlx5dr_context *ctx, return NULL; } - action = mlx5dr_action_create_generic(ctx, flags, MLX5DR_ACTION_TYP_FT); + action = mlx5dr_action_create_generic(ctx, flags, MLX5DR_ACTION_TYP_TBL); if (!action) return NULL; @@ -1681,7 +1681,7 @@ static void mlx5dr_action_destroy_hws(struct mlx5dr_action *action) case MLX5DR_ACTION_TYP_TAG: case MLX5DR_ACTION_TYP_DROP: case MLX5DR_ACTION_TYP_CTR: - case MLX5DR_ACTION_TYP_FT: + case MLX5DR_ACTION_TYP_TBL: case MLX5DR_ACTION_TYP_REFORMAT_TNL_L2_TO_L2: case MLX5DR_ACTION_TYP_ASO_METER: case MLX5DR_ACTION_TYP_ASO_CT: @@ -2178,7 +2178,7 @@ int mlx5dr_action_template_process(struct mlx5dr_action_template *at) switch (action_type[i]) { case MLX5DR_ACTION_TYP_DROP: case MLX5DR_ACTION_TYP_TIR: - case MLX5DR_ACTION_TYP_FT: + case MLX5DR_ACTION_TYP_TBL: case MLX5DR_ACTION_TYP_DEST_ROOT: case MLX5DR_ACTION_TYP_VPORT: case MLX5DR_ACTION_TYP_MISS: diff --git a/drivers/net/mlx5/hws/mlx5dr_debug.c b/drivers/net/mlx5/hws/mlx5dr_debug.c index 5064b23b7d..48810142a0 100644 --- a/drivers/net/mlx5/hws/mlx5dr_debug.c +++ b/drivers/net/mlx5/hws/mlx5dr_debug.c @@ -12,7 +12,7 @@ const char *mlx5dr_debug_action_type_str[] = { [MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L3] = "L2_TO_TNL_L3", [MLX5DR_ACTION_TYP_DROP] = "DROP", [MLX5DR_ACTION_TYP_TIR] = "TIR", - [MLX5DR_ACTION_TYP_FT] = "FT", + [MLX5DR_ACTION_TYP_TBL] = "TBL", [MLX5DR_ACTION_TYP_CTR] = "CTR", [MLX5DR_ACTION_TYP_TAG] = "TAG", [MLX5DR_ACTION_TYP_MODIFY_HDR] = "MODIFY_HDR", diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index e1adc081c1..521df9ff40 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -4520,7 +4520,7 @@ flow_hw_actions_validate(struct rte_eth_dev *dev, static enum mlx5dr_action_type mlx5_hw_dr_action_types[] = { [RTE_FLOW_ACTION_TYPE_MARK] = MLX5DR_ACTION_TYP_TAG, [RTE_FLOW_ACTION_TYPE_DROP] = MLX5DR_ACTION_TYP_DROP, - [RTE_FLOW_ACTION_TYPE_JUMP] = MLX5DR_ACTION_TYP_FT, + [RTE_FLOW_ACTION_TYPE_JUMP] = MLX5DR_ACTION_TYP_TBL, [RTE_FLOW_ACTION_TYPE_QUEUE] = MLX5DR_ACTION_TYP_TIR, [RTE_FLOW_ACTION_TYPE_RSS] = MLX5DR_ACTION_TYP_TIR, [RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP] = MLX5DR_ACTION_TYP_REFORMAT_L2_TO_TNL_L2, @@ -4665,7 +4665,7 @@ flow_hw_dr_actions_template_create(struct rte_flow_actions_template *at) action_types[curr_off++] = MLX5DR_ACTION_TYP_ASO_METER; if (curr_off >= MLX5_HW_MAX_ACTS) goto err_actions_num; - action_types[curr_off++] = MLX5DR_ACTION_TYP_FT; + action_types[curr_off++] = MLX5DR_ACTION_TYP_TBL; break; case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: type = mlx5_hw_dr_action_types[at->actions[i].type]; From patchwork Tue Jul 4 10:46:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Itamar Gozlan X-Patchwork-Id: 129248 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EE41742DD1; Tue, 4 Jul 2023 12:48:42 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EE0F142D2C; Tue, 4 Jul 2023 12:48:40 +0200 (CEST) Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2041.outbound.protection.outlook.com [40.107.236.41]) by mails.dpdk.org (Postfix) with ESMTP id 6DD5242BC9 for ; Tue, 4 Jul 2023 12:48:39 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Z2F4RcwDhbVqpNK2jZWy/99dtsdgPrfkcdyaVt3PB7MYoBWO7pYDjIZyLPVV3FZ+0cNvZWthPBWyv2lbOt8N2HWOL7gXhayTkuz6fbtPggBJ4p4BVFBAle5pak0Lzvx/YRLiaITPO4yJlQuTpnNErh58W69qbmZIcpUqq7Ha8lALJ0I1CqtQF4nh20zuUp6uDd/Cq0Wn31sajOSN0LqoLklNr130io1nCfBUluAeeX+Ur6DyDHg/kfumLFf8AzzAh6crkrZq7+5lBYwXpxoTFnKWk9at58rFWarKWBZ23kyP/U4d21xyCYEry6C1isH0ZCKkgWluKqxCMSGmhmVgMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=+VoFDzi8ASKM6OvldCv5dyKY3OEw7zHyhhYx6lchfJ0=; b=Rvgw8duX42indk7EQFlGGKt2i5hMrQkiwAoO6E/mXXTX97u3Ydm18ZiWP5NDDnNH++ivJ/AsMRfHQ4DPTNAgk6u9OwO0QG4GlfT+i0KblJOCTTL9jwCKyJfAYMC0G9iS6DjkBspptA21DRX7igzCHph9PY4F1SgySzCCz6VqQRpWn0OBFvXMMF5rcpz+L2Qk+jnBBwiQ+UUDOPyCdKGrZzvdYytdicySqtiwQBmanixfXWIy6faCWzcobuAvFemhyzHErJe9jqO+9iYu824t4ZvqCRjYAlyJVKRotxZUyii/HSw267Y8qAaaqFdE/ou/4W+Z7/xqYyTKpL1sXkl40g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+VoFDzi8ASKM6OvldCv5dyKY3OEw7zHyhhYx6lchfJ0=; b=m47gJGQke/EvhARrNVGC09Y8V+FMAOZMoaXgE0rzI2GZxTtiM0VjwMhgG5MJburxw2+YuVqZqhxm1Hg54D1svSEdwCMPhj2vwmF9ksjz7MDOiJzXKG2biIktMTVQU+UfU1qIGton4o2VApmbw+p9SJnjYZjBvFabIR54SfePaIQ+bPBE/gLxT8QUbKhr2d9L0caZC+rBFWs+o9ZI4pV3ORVQzgOr+kHFhiKcvFLTxNCC+8QhyGSzgCf2gV2L10V2cZ3gXZrGNU079F95MGCDCdZ2BfF9vAQiEI5mI1ynPDxXGvFXniq4qG5Xdddaiqx7m2ZOIsUk9EpE3KzikjJj1w== Received: from DM6PR03CA0062.namprd03.prod.outlook.com (2603:10b6:5:100::39) by PH8PR12MB6987.namprd12.prod.outlook.com (2603:10b6:510:1be::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6544.24; Tue, 4 Jul 2023 10:48:37 +0000 Received: from DM6NAM11FT049.eop-nam11.prod.protection.outlook.com (2603:10b6:5:100:cafe::9c) by DM6PR03CA0062.outlook.office365.com (2603:10b6:5:100::39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6565.18 via Frontend Transport; Tue, 4 Jul 2023 10:48:37 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DM6NAM11FT049.mail.protection.outlook.com (10.13.172.188) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6521.43 via Frontend Transport; Tue, 4 Jul 2023 10:48:37 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Tue, 4 Jul 2023 03:48:29 -0700 Received: from rnnvmail203.nvidia.com (10.129.68.9) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Tue, 4 Jul 2023 03:48:28 -0700 Received: from nvidia.com (10.127.8.12) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37 via Frontend Transport; Tue, 4 Jul 2023 03:48:26 -0700 From: Itamar Gozlan To: , , , , , Ori Kam CC: Subject: [v1 5/5] net/mlx5/hws: support default miss action on FDB Date: Tue, 4 Jul 2023 13:46:45 +0300 Message-ID: <20230704104645.19800-5-igozlan@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20230704104645.19800-1-igozlan@nvidia.com> References: <20230702045758.23244-4-igozlan@nvidia.com> <20230704104645.19800-1-igozlan@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT049:EE_|PH8PR12MB6987:EE_ X-MS-Office365-Filtering-Correlation-Id: c21e3ea9-f0ec-4bfb-4068-08db7c7c38e9 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HUSnYknsyCUqcwXudGJODqdUd6MTlxN7sMBP889W2lLEFNZMxCpJUUKLZxL7GqMYjYIRjD34pN0sCn7a3lXMOazJMPZzHUSA/QeRaKrbkJ9alBx249JevBKy5h6bNTfwvwRCl12f5zSM3hXiE5Onf6Wg50uhj3GA5zfDGdAWFcJf2GnHrnZYlgxlujHN1D7HRnKsFjX+wfKu/RJum+qAW5lTDl6ahxc5UCQI2nyQcNWimk0bq6gKvPRTxXOYFjGCPVMP0CBf8NdfoYS80kJDyv18vH9tZb7N9qGxUk1BOi/TFmzCxYoR/XhWycXoTtY3+dVGs1NSlRdgNHpe6k4XIPCG16yX0M4yPO06x8dX8Pmf0ZDHYmNXTsaNr6fxr9Qk0ISpjV5LyDYlXQ5RJqQ/DeljndbkGyjom3gCgUFsUDLI2eq0VGPtSJh/r4ezMtl4Q3kGlhLmJzGm88Vn48+DUAQE0agq14o1WYJP1P1H09e/1d/IgD6o8JrYyxlG/3hhvWR9IGj5malSSvdNXZBt2pz5PlMEXH3jh/zCM5gRKbHDSuZXqSE6hzqY/gHY1wQ4ZzGfB8hX4n1MiZk5Ar+w1Dgjw99VSUjZfmj0uyJZ4hXj7GcNcdeAQGCKzGJcw17mo9OyFmfSXHK0conW95hUpoGCYyTFbiMEMCOl7NYmrc2uJyqmmmkxu2yz1piv92rBpwJsN2MERuVb4geTwBgOaM5cNNl3T94lSFq1UD6LjHJ4OApC5qym/JY+xIfV9YFC X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230028)(4636009)(376002)(346002)(136003)(39860400002)(396003)(451199021)(40470700004)(46966006)(36840700001)(26005)(478600001)(1076003)(82740400003)(6666004)(86362001)(6286002)(2616005)(186003)(36860700001)(6636002)(4326008)(70586007)(356005)(336012)(7636003)(110136005)(83380400001)(426003)(7696005)(70206006)(316002)(47076005)(8676002)(8936002)(40460700003)(41300700001)(2906002)(40480700001)(55016003)(5660300002)(82310400005)(36756003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jul 2023 10:48:37.4250 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c21e3ea9-f0ec-4bfb-4068-08db7c7c38e9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT049.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6987 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Alex Vesker Add the support for default miss on HWS FDB, this implementation was missing until now. Default miss can be used for more efficient miss flow instead of going to an empty matcher or some defecated empty table. Signed-off-by: Alex Vesker Acked-by: Matan Azrad --- drivers/net/mlx5/hws/mlx5dr_action.c | 27 ++++++++++++++++++++------- drivers/net/mlx5/hws/mlx5dr_table.c | 6 +----- 2 files changed, 21 insertions(+), 12 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_action.c b/drivers/net/mlx5/hws/mlx5dr_action.c index 74f4e60863..920099ba5b 100644 --- a/drivers/net/mlx5/hws/mlx5dr_action.c +++ b/drivers/net/mlx5/hws/mlx5dr_action.c @@ -322,10 +322,12 @@ int mlx5dr_action_root_build_attr(struct mlx5dr_rule_action rule_actions[], return 0; } -static bool mlx5dr_action_fixup_stc_attr(struct mlx5dr_cmd_stc_modify_attr *stc_attr, - struct mlx5dr_cmd_stc_modify_attr *fixup_stc_attr, - enum mlx5dr_table_type table_type, - bool is_mirror) +static bool +mlx5dr_action_fixup_stc_attr(struct mlx5dr_context *ctx, + struct mlx5dr_cmd_stc_modify_attr *stc_attr, + struct mlx5dr_cmd_stc_modify_attr *fixup_stc_attr, + enum mlx5dr_table_type table_type, + bool is_mirror) { struct mlx5dr_devx_obj *devx_obj; bool use_fixup = false; @@ -348,6 +350,17 @@ static bool mlx5dr_action_fixup_stc_attr(struct mlx5dr_cmd_stc_modify_attr *stc_ use_fixup = true; break; + case MLX5_IFC_STC_ACTION_TYPE_ALLOW: + if (fw_tbl_type == FS_FT_FDB_TX || fw_tbl_type == FS_FT_FDB_RX) { + fixup_stc_attr->action_type = MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_VPORT; + fixup_stc_attr->action_offset = stc_attr->action_offset; + fixup_stc_attr->stc_offset = stc_attr->stc_offset; + fixup_stc_attr->vport.esw_owner_vhca_id = ctx->caps->vhca_id; + fixup_stc_attr->vport.vport_num = ctx->caps->eswitch_manager_vport_number; + use_fixup = true; + } + break; + case MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_VPORT: if (stc_attr->vport.vport_num != WIRE_PORT) break; @@ -397,7 +410,7 @@ int mlx5dr_action_alloc_single_stc(struct mlx5dr_context *ctx, devx_obj_0 = mlx5dr_pool_chunk_get_base_devx_obj(stc_pool, stc); /* According to table/action limitation change the stc_attr */ - use_fixup = mlx5dr_action_fixup_stc_attr(stc_attr, &fixup_stc_attr, table_type, false); + use_fixup = mlx5dr_action_fixup_stc_attr(ctx, stc_attr, &fixup_stc_attr, table_type, false); ret = mlx5dr_cmd_stc_modify(devx_obj_0, use_fixup ? &fixup_stc_attr : stc_attr); if (ret) { DR_LOG(ERR, "Failed to modify STC action_type %d tbl_type %d", @@ -411,7 +424,8 @@ int mlx5dr_action_alloc_single_stc(struct mlx5dr_context *ctx, devx_obj_1 = mlx5dr_pool_chunk_get_base_devx_obj_mirror(stc_pool, stc); - use_fixup = mlx5dr_action_fixup_stc_attr(stc_attr, &fixup_stc_attr, + use_fixup = mlx5dr_action_fixup_stc_attr(ctx, stc_attr, + &fixup_stc_attr, table_type, true); ret = mlx5dr_cmd_stc_modify(devx_obj_1, use_fixup ? &fixup_stc_attr : stc_attr); if (ret) { @@ -491,7 +505,6 @@ static void mlx5dr_action_fill_stc_attr(struct mlx5dr_action *action, case MLX5DR_ACTION_TYP_MISS: attr->action_type = MLX5_IFC_STC_ACTION_TYPE_ALLOW; attr->action_offset = MLX5DR_ACTION_OFFSET_HIT; - /* TODO Need to support default miss for FDB */ break; case MLX5DR_ACTION_TYP_CTR: attr->id = obj->id; diff --git a/drivers/net/mlx5/hws/mlx5dr_table.c b/drivers/net/mlx5/hws/mlx5dr_table.c index c18ee7c552..f91f04d924 100644 --- a/drivers/net/mlx5/hws/mlx5dr_table.c +++ b/drivers/net/mlx5/hws/mlx5dr_table.c @@ -24,7 +24,6 @@ mlx5dr_table_up_default_fdb_miss_tbl(struct mlx5dr_table *tbl) struct mlx5dr_cmd_forward_tbl *default_miss; struct mlx5dr_context *ctx = tbl->ctx; uint8_t tbl_type = tbl->type; - uint32_t vport; if (tbl->type != MLX5DR_TABLE_TYPE_FDB) return 0; @@ -38,12 +37,9 @@ mlx5dr_table_up_default_fdb_miss_tbl(struct mlx5dr_table *tbl) ft_attr.level = tbl->ctx->caps->fdb_ft.max_level; /* The last level */ ft_attr.rtc_valid = false; - assert(ctx->caps->eswitch_manager); - vport = ctx->caps->eswitch_manager_vport_number; - fte_attr.action_flags = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; fte_attr.destination_type = MLX5_FLOW_DESTINATION_TYPE_VPORT; - fte_attr.destination_id = vport; + fte_attr.destination_id = ctx->caps->eswitch_manager_vport_number; default_miss = mlx5dr_cmd_forward_tbl_create(mlx5dr_context_get_local_ibv(ctx), &ft_attr, &fte_attr);