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Tue, 23 May 2023 05:48:12 -0700 From: Michael Baum To: CC: Ori Kam , Aman Singh , "Yuying Zhang" , Ferruh Yigit , "Thomas Monjalon" , , Subject: [PATCH v4 1/5] doc: fix blank lines in modify field action description Date: Tue, 23 May 2023 15:48:01 +0300 Message-ID: <20230523124805.3846360-2-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230523124805.3846360-1-michaelba@nvidia.com> References: <20230522192804.3759072-1-michaelba@nvidia.com> <20230523124805.3846360-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000C96B:EE_|SA1PR12MB6704:EE_ X-MS-Office365-Filtering-Correlation-Id: 2ec70a22-09aa-4410-00bc-08db5b8c02a9 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 6cELoMzt4+E1V5JorVPufyQahmCDXzrqedRX1UFotBNec4PGT9MrlyjN/C70nHTKQlHy/xHFBMgqhwuNpFc2Uylw/8CSpnfEqEtWZjViwo9Pt1wQ/7T8dEV0EP98+h06TFn/EwFDY9XeECxvpBSuJ/XwiiSfexv3Qg/DNMPFzJNbx7W1FSW1HtDQmw0VVgueUH1KjZYl5E1ZmMv2nfzmHmyuQN92zuikMTJE1oQMfIyM1uSUsU5YBIQGKh2zvsgLriAUF9pQm9/z/2kC7Cz5kV7IgdsMfVtENjGxLPfo2zPetp1oh5nqROQbWdX0czUjNeFhk3CNOhX6W5kbU0nX6Ev3f3BWXJVncL7+jNTUdI3b0LQGMn4fuAMD6bWbz5NUKFbQQ7TrutiiYOLnobBa9RYDIkrPGiE4BZKNAnIUS52cE/QEpQuf1T7EUuuIMh65tuBBmh9kcbDmOgT760rsTpmQt/wfRkCORqdcKq48iicZoiKwyUbJgQZdgW4wP6v8djIsTDjTtbPxhessGs0nsZHVsdzcTBUslX8QyopKL5cmNxF/ka6fXeRwShbKUKA8TgRquLO8pqL/2qVolHiLwtkvV2wzQHGF9U7CDb3MfDkJ92ds2By4+cqu6w2bqajZuy+xDKudH7hLn3DfOhtR9wH9MKn59xtXo6FBjvHov9sVlFdptz1HEr5i8juOgcg+NcLTNUvukxMIUv8Rhr4WncpwBOunC5kk32Mw6D7f1GE= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230028)(4636009)(346002)(136003)(39860400002)(376002)(396003)(451199021)(40470700004)(36840700001)(46966006)(316002)(4326008)(6916009)(70206006)(70586007)(426003)(336012)(478600001)(82310400005)(54906003)(8676002)(8936002)(7696005)(86362001)(6666004)(41300700001)(5660300002)(26005)(36756003)(36860700001)(82740400003)(83380400001)(7636003)(1076003)(356005)(47076005)(55016003)(6286002)(186003)(40460700003)(2906002)(2616005)(40480700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 May 2023 12:48:30.0142 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2ec70a22-09aa-4410-00bc-08db5b8c02a9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000C96B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6704 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The modify field action description inside "Generic flow API (rte_flow)" documentation, lists all operations supported for a destination field. In addition, it lists the values supported for a encapsulation level field. Before the lists, in both cases, miss a blank line causing them to look regular text lines. This patch adds the blank lines. Fixes: 73b68f4c54a0 ("ethdev: introduce generic modify flow action") Cc: akozyrev@nvidia.com Cc: stable@dpdk.org Signed-off-by: Michael Baum Acked-by: Ori Kam --- doc/guides/prog_guide/rte_flow.rst | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst index 32fc45516a..e7faa368a1 100644 --- a/doc/guides/prog_guide/rte_flow.rst +++ b/doc/guides/prog_guide/rte_flow.rst @@ -2917,20 +2917,23 @@ The immediate value ``RTE_FLOW_FIELD_VALUE`` (or a pointer to it ``RTE_FLOW_FIELD_START`` is used to point to the beginning of a packet. See ``enum rte_flow_field_id`` for the list of supported fields. -``op`` selects the operation to perform on a destination field. +``op`` selects the operation to perform on a destination field: + - ``set`` copies the data from ``src`` field to ``dst`` field. - ``add`` adds together ``dst`` and ``src`` and stores the result into ``dst``. -- ``sub`` subtracts ``src`` from ``dst`` and stores the result into ``dst`` +- ``sub`` subtracts ``src`` from ``dst`` and stores the result into ``dst``. ``width`` defines a number of bits to use from ``src`` field. ``level`` is used to access any packet field on any encapsulation level -as well as any tag element in the tag array. -- ``0`` means the default behaviour. Depending on the packet type, it can -mean outermost, innermost or anything in between. +as well as any tag element in the tag array: + +- ``0`` means the default behaviour. Depending on the packet type, + it can mean outermost, innermost or anything in between. - ``1`` requests access to the outermost packet encapsulation level. - ``2`` and subsequent values requests access to the specified packet -encapsulation level, from outermost to innermost (lower to higher values). + encapsulation level, from outermost to innermost (lower to higher values). + For the tag array (in case of multiple tags are supported and present) ``level`` translates directly into the array index. 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Tue, 23 May 2023 05:48:15 -0700 From: Michael Baum To: CC: Ori Kam , Aman Singh , "Yuying Zhang" , Ferruh Yigit , "Thomas Monjalon" , , Subject: [PATCH v4 2/5] doc: fix blank line in asynchronous operations description Date: Tue, 23 May 2023 15:48:02 +0300 Message-ID: <20230523124805.3846360-3-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230523124805.3846360-1-michaelba@nvidia.com> References: <20230522192804.3759072-1-michaelba@nvidia.com> <20230523124805.3846360-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000C969:EE_|DM4PR12MB5183:EE_ X-MS-Office365-Filtering-Correlation-Id: e6a7e02a-bc28-44d5-96d0-08db5b8c05dd X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: WPRm5HpxadBn7bS7uz41K3oQUTJJbZpsZrd2TtgLOeS1kJVsrFbG8UBs+n1rP74JBzFGqNcflQgtHlTB+frW0JIvOFZvgyl8Q/RyV7obOJcK1xutL4OavX/r/BsnVEhLL/RmfaepK3HPjoeF2eI8KyPHsqAnlCCGWm55mJzXpGcKD2E7zATe01Z94d0z88Tt+yRe4UBkc0/gb+GfQIXMEe+K5U5eu6ebw0EvPXbzN8mvj8NIulD2PidVF42K5zRx6qV2sggsTf4eD4sIZjwAQe98iJUbqndAsZ2DBI76wodyZJfWgUQo54zEinbHg6/jOZqRdnYIPAp1zCDYI8xHfyzwUd9g+Q1EaT1kV6F5kEqIkDxZQR4gEsQzlHFxSchHXKEldAo/MeCglzVZCSwC+t/W9JYpu2KKYyg+Muj+QFF5kmWu7BxIH96RYw2cGA3bCYDkB+PDS/zxWIXHnjK0RJKbaMim3tscOXYrct0ZJ4L6fdWBnNlxc3kbpOIaOiFs8uHgb6eHI1vb2uDKuMJcsyTtp/TsYTIdWAIGpx51l1KJ9ZIqZB9LxdPJ04/ZUJV/nkX4DiipiTnnwr0ITuAoIUYozxg5ezaKRLGBP3/iLQDXVm0i5XuqExIRwqZWtN/G+Wlh/m6nShwxjHbtGn/Zu2L4ENUoz/YeYna3jNTVpyUiDHwe8/Tc/Oz2Iw2FEZ1AmSv3JaiHQtF9hZGUFjeJiKhvYvn7JCMFFh0NKqitJ9c0fwmBS4r/9oCs4hIfRFaA X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230028)(4636009)(39860400002)(136003)(346002)(396003)(376002)(451199021)(46966006)(36840700001)(40470700004)(2906002)(5660300002)(82310400005)(83380400001)(8676002)(8936002)(70206006)(70586007)(4326008)(6916009)(36756003)(55016003)(54906003)(316002)(41300700001)(7696005)(478600001)(40480700001)(6666004)(86362001)(7636003)(2616005)(356005)(26005)(82740400003)(36860700001)(47076005)(6286002)(186003)(1076003)(40460700003)(426003)(336012); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 May 2023 12:48:35.3764 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e6a7e02a-bc28-44d5-96d0-08db5b8c05dd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000C969.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5183 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The asynchronous operations description inside "Generic flow API (rte_flow)" documentation, adds some bullets to describe asynchronous operations behavior. Before the first bullet, miss a blank line causing it to look a regular text line. This patch adds the blank line. Fixes: 197e820c6685 ("ethdev: bring in async queue-based flow rules operations") Cc: akozyrev@nvidia.com Cc: stable@dpdk.org Signed-off-by: Michael Baum Acked-by: Ori Kam --- doc/guides/prog_guide/rte_flow.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst index e7faa368a1..76e69190fc 100644 --- a/doc/guides/prog_guide/rte_flow.rst +++ b/doc/guides/prog_guide/rte_flow.rst @@ -3702,6 +3702,7 @@ Asynchronous operations ----------------------- Flow rules management can be done via special lockless flow management queues. + - Queue operations are asynchronous and not thread-safe. - Operations can thus be invoked by the app's datapath, From patchwork Tue May 23 12:48:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 127206 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B5AA142B81; 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Tue, 23 May 2023 05:48:20 -0700 Received: from rnnvmail203.nvidia.com (10.129.68.9) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Tue, 23 May 2023 05:48:20 -0700 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37 via Frontend Transport; Tue, 23 May 2023 05:48:17 -0700 From: Michael Baum To: CC: Ori Kam , Aman Singh , "Yuying Zhang" , Ferruh Yigit , "Thomas Monjalon" , , Subject: [PATCH v4 3/5] doc: fix wrong indentation in RSS action description Date: Tue, 23 May 2023 15:48:03 +0300 Message-ID: <20230523124805.3846360-4-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230523124805.3846360-1-michaelba@nvidia.com> References: <20230522192804.3759072-1-michaelba@nvidia.com> <20230523124805.3846360-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT038:EE_|SA1PR12MB7197:EE_ X-MS-Office365-Filtering-Correlation-Id: 0b14b6af-4bb8-45a4-470c-08db5b8c05ff X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 May 2023 12:48:35.5659 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0b14b6af-4bb8-45a4-470c-08db5b8c05ff X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7197 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The RSS action description inside "Generic flow API (rte_flow)" documentation, lists the values supported for a encapsulation level field. For "2" value, it uses 3 spaces as an indentation instead of 2 after line breaking, causing the first line to be bold. This patch updates the number of spaces in the indentation. Fixes: 18aee2861a1f ("ethdev: add encap level to RSS flow API action") Cc: adrien.mazarguil@6wind.com Cc: stable@dpdk.org Signed-off-by: Michael Baum Acked-by: Ori Kam --- doc/guides/prog_guide/rte_flow.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst index 76e69190fc..25b57bf86d 100644 --- a/doc/guides/prog_guide/rte_flow.rst +++ b/doc/guides/prog_guide/rte_flow.rst @@ -1954,8 +1954,8 @@ Also, regarding packet encapsulation ``level``: level. - ``2`` and subsequent values request RSS to be performed on the specified - inner packet encapsulation level, from outermost to innermost (lower to - higher values). + inner packet encapsulation level, from outermost to innermost (lower to + higher values). Values other than ``0`` are not necessarily supported. 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Tue, 23 May 2023 05:48:20 -0700 From: Michael Baum To: CC: Ori Kam , Aman Singh , "Yuying Zhang" , Ferruh Yigit , "Thomas Monjalon" Subject: [PATCH v4 4/5] ethdev: add GENEVE TLV option modification support Date: Tue, 23 May 2023 15:48:04 +0300 Message-ID: <20230523124805.3846360-5-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230523124805.3846360-1-michaelba@nvidia.com> References: <20230522192804.3759072-1-michaelba@nvidia.com> <20230523124805.3846360-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000C966:EE_|PH7PR12MB7356:EE_ X-MS-Office365-Filtering-Correlation-Id: 61d26eae-7ea3-4d90-a761-08db5b8c0860 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5yRLDVE72Z1G/6XTHm/N/wujNlLBW5XCW/dQwvrl/PuQqwy5PEYyJlLFAzl6MRbIp4qlAGYVcS5kDmIqbzpCEwlHQy432wDW+S9DLHxW+mMAKOH8ANmUDCdiX1xYiPFhM0Hpf/f/irXZUWmV5DXtg9i75F2TI03ovaWS3BWM17+pbRhw81jaYfqtcQ4WTpmboT4snUIuoKcj0pTa2414fO5BaiWRFE9NtnISZ+9T6rp815QJGkMQOdYY7rKvOzouRlIFMqEn/g8a42vs0bJTW5zPvV1ENl/xYpsSsvuElMNUGCBSMxQDoXVEjdc009Xmt2vh3qiwKcVYMSBQGGH0hTU1+T1sL18Mg1BHD6qNyTGdmBWTmlrlAE71SUHhaSrxN+2ND9ng27hWsK9MFQkVi62sBOcoJml/xUaHmVLy1N9ezQtWIDlw4qlpXdoZ5Zlwi2UQiydJWpGmLvT9o8vX6vcyJ7cnnx/bcocoScFDd6W6gfcuU4GlCf0v1r2H8gbtt8podkS9waQ7usiKbKSq8TiHUJkicBetoRDdDe4ut83zg/vwy3WHJMySBqrpdfOx4n28wTdbw2yjYGpu06Hx6K9SP+/HPPqN8APITIcCy7qnwvd8sGUx9S6fUytlT9GX/Syv+Mp7im969xwvMfMs4KNeMCaKW2t+QurxiFnwtHrx9jArkyg7PSzJSwsqF7OdpeIj5dx36nDYrpUjPbQ2ju/zK2ACHsLzu/Fy5M250M1JE9iNgTi9iJaYoTElKAKHc42MeKuPrv0JhDxf3t7KRuGNEQfmmMgwp09v2lcnq5ETccBHHKzq8fcE7lRIWnGz X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230028)(4636009)(136003)(396003)(346002)(376002)(39860400002)(451199021)(40470700004)(36840700001)(46966006)(41300700001)(356005)(5660300002)(8676002)(70586007)(7636003)(6916009)(4326008)(8936002)(70206006)(36860700001)(82740400003)(316002)(40480700001)(47076005)(426003)(54906003)(82310400005)(83380400001)(336012)(30864003)(2906002)(478600001)(2616005)(40460700003)(55016003)(26005)(1076003)(86362001)(7696005)(6666004)(36756003)(186003)(6286002)(21314003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 May 2023 12:48:39.6063 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 61d26eae-7ea3-4d90-a761-08db5b8c0860 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000C966.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7356 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add modify field support for GENEVE option fields: - "RTE_FLOW_FIELD_GENEVE_OPT_TYPE" - "RTE_FLOW_FIELD_GENEVE_OPT_CLASS" - "RTE_FLOW_FIELD_GENEVE_OPT_DATA" Each GENEVE TLV option is identified by both its "class" and "type", so 2 new fields were added to "rte_flow_action_modify_data" structure to help specify which option to modify. To get room for those 2 new fields, the "level" field move to use "uint8_t" which is more than enough for encapsulation level. This patch also reduces all modify field encapsulation level "fully masked" initializations to use UINT8_MAX instead of UINT32_MAX. This change avoids compilation warning caused by this API changing. Signed-off-by: Michael Baum Acked-by: Ori Kam --- app/test-pmd/cmdline_flow.c | 48 +++++++++++++++++++++++++- doc/guides/prog_guide/rte_flow.rst | 23 ++++++++++++ doc/guides/rel_notes/release_23_07.rst | 3 ++ drivers/net/mlx5/mlx5_flow_hw.c | 22 ++++++------ lib/ethdev/rte_flow.h | 48 +++++++++++++++++++++++++- 5 files changed, 131 insertions(+), 13 deletions(-) diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c index 58939ec321..8c1dea53c0 100644 --- a/app/test-pmd/cmdline_flow.c +++ b/app/test-pmd/cmdline_flow.c @@ -636,11 +636,15 @@ enum index { ACTION_MODIFY_FIELD_DST_TYPE_VALUE, ACTION_MODIFY_FIELD_DST_LEVEL, ACTION_MODIFY_FIELD_DST_LEVEL_VALUE, + ACTION_MODIFY_FIELD_DST_TYPE_ID, + ACTION_MODIFY_FIELD_DST_CLASS_ID, ACTION_MODIFY_FIELD_DST_OFFSET, ACTION_MODIFY_FIELD_SRC_TYPE, ACTION_MODIFY_FIELD_SRC_TYPE_VALUE, ACTION_MODIFY_FIELD_SRC_LEVEL, ACTION_MODIFY_FIELD_SRC_LEVEL_VALUE, + ACTION_MODIFY_FIELD_SRC_TYPE_ID, + ACTION_MODIFY_FIELD_SRC_CLASS_ID, ACTION_MODIFY_FIELD_SRC_OFFSET, ACTION_MODIFY_FIELD_SRC_VALUE, ACTION_MODIFY_FIELD_SRC_POINTER, @@ -854,7 +858,9 @@ static const char *const modify_field_ids[] = { "ipv4_ecn", "ipv6_ecn", "gtp_psc_qfi", "meter_color", "ipv6_proto", "flex_item", - "hash_result", NULL + "hash_result", + "geneve_opt_type", "geneve_opt_class", "geneve_opt_data", + NULL }; static const char *const meter_colors[] = { @@ -2295,6 +2301,8 @@ static const enum index next_action_sample[] = { static const enum index action_modify_field_dst[] = { ACTION_MODIFY_FIELD_DST_LEVEL, + ACTION_MODIFY_FIELD_DST_TYPE_ID, + ACTION_MODIFY_FIELD_DST_CLASS_ID, ACTION_MODIFY_FIELD_DST_OFFSET, ACTION_MODIFY_FIELD_SRC_TYPE, ZERO, @@ -2302,6 +2310,8 @@ static const enum index action_modify_field_dst[] = { static const enum index action_modify_field_src[] = { ACTION_MODIFY_FIELD_SRC_LEVEL, + ACTION_MODIFY_FIELD_SRC_TYPE_ID, + ACTION_MODIFY_FIELD_SRC_CLASS_ID, ACTION_MODIFY_FIELD_SRC_OFFSET, ACTION_MODIFY_FIELD_SRC_VALUE, ACTION_MODIFY_FIELD_SRC_POINTER, @@ -6388,6 +6398,24 @@ static const struct token token_list[] = { .call = parse_vc_modify_field_level, .comp = comp_none, }, + [ACTION_MODIFY_FIELD_DST_TYPE_ID] = { + .name = "dst_type_id", + .help = "destination field type ID", + .next = NEXT(action_modify_field_dst, + NEXT_ENTRY(COMMON_UNSIGNED)), + .args = ARGS(ARGS_ENTRY(struct rte_flow_action_modify_field, + dst.type)), + .call = parse_vc_conf, + }, + [ACTION_MODIFY_FIELD_DST_CLASS_ID] = { + .name = "dst_class", + .help = "destination field class ID", + .next = NEXT(action_modify_field_dst, + NEXT_ENTRY(COMMON_UNSIGNED)), + .args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_action_modify_field, + dst.class_id)), + .call = parse_vc_conf, + }, [ACTION_MODIFY_FIELD_DST_OFFSET] = { .name = "dst_offset", .help = "destination field bit offset", @@ -6423,6 +6451,24 @@ static const struct token token_list[] = { .call = parse_vc_modify_field_level, .comp = comp_none, }, + [ACTION_MODIFY_FIELD_SRC_TYPE_ID] = { + .name = "src_type_id", + .help = "source field type ID", + .next = NEXT(action_modify_field_src, + NEXT_ENTRY(COMMON_UNSIGNED)), + .args = ARGS(ARGS_ENTRY(struct rte_flow_action_modify_field, + src.type)), + .call = parse_vc_conf, + }, + [ACTION_MODIFY_FIELD_SRC_CLASS_ID] = { + .name = "src_class", + .help = "source field class ID", + .next = NEXT(action_modify_field_src, + NEXT_ENTRY(COMMON_UNSIGNED)), + .args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_action_modify_field, + src.class_id)), + .call = parse_vc_conf, + }, [ACTION_MODIFY_FIELD_SRC_OFFSET] = { .name = "src_offset", .help = "source field bit offset", diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst index 25b57bf86d..ec812de335 100644 --- a/doc/guides/prog_guide/rte_flow.rst +++ b/doc/guides/prog_guide/rte_flow.rst @@ -2937,6 +2937,14 @@ as well as any tag element in the tag array: For the tag array (in case of multiple tags are supported and present) ``level`` translates directly into the array index. +``type`` is used to specify (along with ``class_id``) the Geneve option which +is being modified. +This field is relevant only for ``RTE_FLOW_FIELD_GENEVE_OPT_XXXX`` type. + +``class_id`` is used to specify (along with ``type``) the Geneve option which +is being modified. +This field is relevant only for ``RTE_FLOW_FIELD_GENEVE_OPT_XXXX`` type. + ``flex_handle`` is used to specify the flex item pointer which is being modified. ``flex_handle`` and ``level`` are mutually exclusive. @@ -2967,6 +2975,17 @@ to replace the third byte of MAC address with value 0x85, application should specify destination width as 8, destination offset as 16, and provide immediate value as sequence of bytes {xxx, xxx, 0x85, xxx, xxx, xxx}. +The ``RTE_FLOW_FIELD_GENEVE_OPT_DATA`` type supports modifying only one DW in +single action and align to 32 bits. For example, for modifying 16 bits start +from offset 24, 2 different actions should be prepared. The first one includs +``offset=24`` and ``width=8``, and the seconde one includs ``offset=32`` and +``width=8``. +Application should provide the data in immediate value memory only for the +single DW even though the offset is related to start of first DW. For example, +to replace the third byte of second DW in Geneve option data with value 0x85, +application should specify destination width as 8, destination offset as 48, +and provide immediate value 0xXXXX85XX. + .. _table_rte_flow_action_modify_field: .. table:: MODIFY_FIELD @@ -2994,6 +3013,10 @@ value as sequence of bytes {xxx, xxx, 0x85, xxx, xxx, xxx}. +-----------------+----------------------------------------------------------+ | ``level`` | encapsulation level of a packet field or tag array index | +-----------------+----------------------------------------------------------+ + | ``type`` | geneve option type | + +-----------------+----------------------------------------------------------+ + | ``class_id`` | geneve option class ID | + +-----------------+----------------------------------------------------------+ | ``flex_handle`` | flex item handle of a packet field | +-----------------+----------------------------------------------------------+ | ``offset`` | number of bits to skip at the beginning | diff --git a/doc/guides/rel_notes/release_23_07.rst b/doc/guides/rel_notes/release_23_07.rst index a9b1293689..ce1755096f 100644 --- a/doc/guides/rel_notes/release_23_07.rst +++ b/doc/guides/rel_notes/release_23_07.rst @@ -84,6 +84,9 @@ API Changes Also, make sure to start the actual text at the margin. ======================================================= +* The ``level`` field in experimental structure + ``struct rte_flow_action_modify_data`` was reduced to 8 bits. + ABI Changes ----------- diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 7e0ee8d883..1b68a19900 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -3565,7 +3565,7 @@ flow_hw_validate_action_modify_field(const struct rte_flow_action *action, return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, action, "immediate value, pointer and hash result cannot be used as destination"); - if (mask_conf->dst.level != UINT32_MAX) + if (mask_conf->dst.level != UINT8_MAX) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, action, "destination encapsulation level must be fully masked"); @@ -3579,7 +3579,7 @@ flow_hw_validate_action_modify_field(const struct rte_flow_action *action, "destination field mask and template are not equal"); if (action_conf->src.field != RTE_FLOW_FIELD_POINTER && action_conf->src.field != RTE_FLOW_FIELD_VALUE) { - if (mask_conf->src.level != UINT32_MAX) + if (mask_conf->src.level != UINT8_MAX) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, action, "source encapsulation level must be fully masked"); @@ -4450,7 +4450,7 @@ flow_hw_set_vlan_vid(struct rte_eth_dev *dev, .operation = RTE_FLOW_MODIFY_SET, .dst = { .field = RTE_FLOW_FIELD_VLAN_ID, - .level = 0xffffffff, .offset = 0xffffffff, + .level = 0xff, .offset = 0xffffffff, }, .src = { .field = RTE_FLOW_FIELD_VALUE, @@ -4583,12 +4583,12 @@ flow_hw_actions_template_create(struct rte_eth_dev *dev, .operation = RTE_FLOW_MODIFY_SET, .dst = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = UINT32_MAX, + .level = UINT8_MAX, .offset = UINT32_MAX, }, .src = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = UINT32_MAX, + .level = UINT8_MAX, .offset = UINT32_MAX, }, .width = UINT32_MAX, @@ -5653,7 +5653,7 @@ flow_hw_create_tx_repr_tag_jump_acts_tmpl(struct rte_eth_dev *dev) .operation = RTE_FLOW_MODIFY_SET, .dst = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = UINT32_MAX, + .level = UINT8_MAX, .offset = UINT32_MAX, }, .src = { @@ -5677,12 +5677,12 @@ flow_hw_create_tx_repr_tag_jump_acts_tmpl(struct rte_eth_dev *dev) .operation = RTE_FLOW_MODIFY_SET, .dst = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = UINT32_MAX, + .level = UINT8_MAX, .offset = UINT32_MAX, }, .src = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = UINT32_MAX, + .level = UINT8_MAX, .offset = UINT32_MAX, }, .width = UINT32_MAX, @@ -6009,7 +6009,7 @@ flow_hw_create_ctrl_regc_jump_actions_template(struct rte_eth_dev *dev) .operation = RTE_FLOW_MODIFY_SET, .dst = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = UINT32_MAX, + .level = UINT8_MAX, .offset = UINT32_MAX, }, .src = { @@ -6182,12 +6182,12 @@ flow_hw_create_tx_default_mreg_copy_actions_template(struct rte_eth_dev *dev) .operation = RTE_FLOW_MODIFY_SET, .dst = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = UINT32_MAX, + .level = UINT8_MAX, .offset = UINT32_MAX, }, .src = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = UINT32_MAX, + .level = UINT8_MAX, .offset = UINT32_MAX, }, .width = UINT32_MAX, diff --git a/lib/ethdev/rte_flow.h b/lib/ethdev/rte_flow.h index 713ba8b65c..f30d4b033f 100644 --- a/lib/ethdev/rte_flow.h +++ b/lib/ethdev/rte_flow.h @@ -3773,6 +3773,9 @@ enum rte_flow_field_id { RTE_FLOW_FIELD_IPV6_PROTO, /**< IPv6 next header. */ RTE_FLOW_FIELD_FLEX_ITEM, /**< Flex item. */ RTE_FLOW_FIELD_HASH_RESULT, /**< Hash result. */ + RTE_FLOW_FIELD_GENEVE_OPT_TYPE, /**< GENEVE option type */ + RTE_FLOW_FIELD_GENEVE_OPT_CLASS,/**< GENEVE option class */ + RTE_FLOW_FIELD_GENEVE_OPT_DATA /**< GENEVE option data */ }; /** @@ -3788,7 +3791,50 @@ struct rte_flow_action_modify_data { struct { /** Encapsulation level or tag index or flex item handle. */ union { - uint32_t level; + struct { + /** + * Packet encapsulation level containing + * the field modify to. + * + * - @p 0 requests the default behavior. + * Depending on the packet type, it + * can mean outermost, innermost or + * anything in between. + * + * It basically stands for the + * innermost encapsulation level + * modification can be performed on + * according to PMD and device + * capabilities. + * + * - @p 1 requests modification to be + * performed on the outermost packet + * encapsulation level. + * + * - @p 2 and subsequent values request + * modification to be performed on + * the specified inner packet + * encapsulation level, from + * outermost to innermost (lower to + * higher values). + * + * Values other than @p 0 are not + * necessarily supported. + */ + uint8_t level; + /** + * Geneve option type. relevant only + * for RTE_FLOW_FIELD_GENEVE_OPT_XXXX + * modification type. + */ + uint8_t type; + /** + * Geneve option class. relevant only + * for RTE_FLOW_FIELD_GENEVE_OPT_XXXX + * modification type. + */ + rte_be16_t class_id; + }; struct rte_flow_item_flex_handle *flex_handle; }; /** Number of bits to skip from a field. */ From patchwork Tue May 23 12:48:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 127208 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D6CD942B81; Tue, 23 May 2023 14:49:12 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 639C842D65; Tue, 23 May 2023 14:48:46 +0200 (CEST) Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2055.outbound.protection.outlook.com [40.107.237.55]) by mails.dpdk.org (Postfix) with ESMTP id A629B42D65 for ; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 May 2023 12:48:41.8748 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9fb42d52-e982-4497-2cc5-08db5b8c09bd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000C967.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9145 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for MPLS modify header using "RTE_FLOW_FIELD_MPLS" id. Since MPLS heaser might appear more the one time in inner/outer/tunnel, a new field was added to "rte_flow_action_modify_data" structure in addition to "level" field. The "tag_index" field is the index of the header inside encapsulation level. It is used for modify multiple MPLS headers in same encapsulation level. This addition enables to modify multiple VLAN headers too, so the description of "RTE_FLOW_FIELD_VLAN_XXXX" was updated. Since the "tag_index" field is added, the "RTE_FLOW_FIELD_TAG" type moves to use it for tag array instead of using "level" field. Using "level" is still supported for backwards compatibility when "tag_index" field is zero. Signed-off-by: Michael Baum Acked-by: Ori Kam --- app/test-pmd/cmdline_flow.c | 24 +++++++++++- doc/guides/prog_guide/rte_flow.rst | 18 ++++++--- doc/guides/rel_notes/release_23_07.rst | 8 +++- drivers/net/mlx5/mlx5_flow.c | 34 +++++++++++++++++ drivers/net/mlx5/mlx5_flow.h | 23 ++++++++++++ drivers/net/mlx5/mlx5_flow_dv.c | 29 +++++++-------- drivers/net/mlx5/mlx5_flow_hw.c | 21 ++++++++--- lib/ethdev/rte_flow.h | 51 ++++++++++++++++++-------- 8 files changed, 162 insertions(+), 46 deletions(-) diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c index 8c1dea53c0..a51e37276b 100644 --- a/app/test-pmd/cmdline_flow.c +++ b/app/test-pmd/cmdline_flow.c @@ -636,6 +636,7 @@ enum index { ACTION_MODIFY_FIELD_DST_TYPE_VALUE, ACTION_MODIFY_FIELD_DST_LEVEL, ACTION_MODIFY_FIELD_DST_LEVEL_VALUE, + ACTION_MODIFY_FIELD_DST_TAG_INDEX, ACTION_MODIFY_FIELD_DST_TYPE_ID, ACTION_MODIFY_FIELD_DST_CLASS_ID, ACTION_MODIFY_FIELD_DST_OFFSET, @@ -643,6 +644,7 @@ enum index { ACTION_MODIFY_FIELD_SRC_TYPE_VALUE, ACTION_MODIFY_FIELD_SRC_LEVEL, ACTION_MODIFY_FIELD_SRC_LEVEL_VALUE, + ACTION_MODIFY_FIELD_SRC_TAG_INDEX, ACTION_MODIFY_FIELD_SRC_TYPE_ID, ACTION_MODIFY_FIELD_SRC_CLASS_ID, ACTION_MODIFY_FIELD_SRC_OFFSET, @@ -859,7 +861,7 @@ static const char *const modify_field_ids[] = { "ipv6_proto", "flex_item", "hash_result", - "geneve_opt_type", "geneve_opt_class", "geneve_opt_data", + "geneve_opt_type", "geneve_opt_class", "geneve_opt_data", "mpls", NULL }; @@ -2301,6 +2303,7 @@ static const enum index next_action_sample[] = { static const enum index action_modify_field_dst[] = { ACTION_MODIFY_FIELD_DST_LEVEL, + ACTION_MODIFY_FIELD_DST_TAG_INDEX, ACTION_MODIFY_FIELD_DST_TYPE_ID, ACTION_MODIFY_FIELD_DST_CLASS_ID, ACTION_MODIFY_FIELD_DST_OFFSET, @@ -2310,6 +2313,7 @@ static const enum index action_modify_field_dst[] = { static const enum index action_modify_field_src[] = { ACTION_MODIFY_FIELD_SRC_LEVEL, + ACTION_MODIFY_FIELD_SRC_TAG_INDEX, ACTION_MODIFY_FIELD_SRC_TYPE_ID, ACTION_MODIFY_FIELD_SRC_CLASS_ID, ACTION_MODIFY_FIELD_SRC_OFFSET, @@ -6398,6 +6402,15 @@ static const struct token token_list[] = { .call = parse_vc_modify_field_level, .comp = comp_none, }, + [ACTION_MODIFY_FIELD_DST_TAG_INDEX] = { + .name = "dst_tag_index", + .help = "destination field tag array", + .next = NEXT(action_modify_field_dst, + NEXT_ENTRY(COMMON_UNSIGNED)), + .args = ARGS(ARGS_ENTRY(struct rte_flow_action_modify_field, + dst.tag_index)), + .call = parse_vc_conf, + }, [ACTION_MODIFY_FIELD_DST_TYPE_ID] = { .name = "dst_type_id", .help = "destination field type ID", @@ -6451,6 +6464,15 @@ static const struct token token_list[] = { .call = parse_vc_modify_field_level, .comp = comp_none, }, + [ACTION_MODIFY_FIELD_SRC_TAG_INDEX] = { + .name = "stc_tag_index", + .help = "source field tag array", + .next = NEXT(action_modify_field_src, + NEXT_ENTRY(COMMON_UNSIGNED)), + .args = ARGS(ARGS_ENTRY(struct rte_flow_action_modify_field, + src.tag_index)), + .call = parse_vc_conf, + }, [ACTION_MODIFY_FIELD_SRC_TYPE_ID] = { .name = "src_type_id", .help = "source field type ID", diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst index ec812de335..e4328e7ed6 100644 --- a/doc/guides/prog_guide/rte_flow.rst +++ b/doc/guides/prog_guide/rte_flow.rst @@ -2925,8 +2925,7 @@ See ``enum rte_flow_field_id`` for the list of supported fields. ``width`` defines a number of bits to use from ``src`` field. -``level`` is used to access any packet field on any encapsulation level -as well as any tag element in the tag array: +``level`` is used to access any packet field on any encapsulation level: - ``0`` means the default behaviour. Depending on the packet type, it can mean outermost, innermost or anything in between. @@ -2934,8 +2933,15 @@ as well as any tag element in the tag array: - ``2`` and subsequent values requests access to the specified packet encapsulation level, from outermost to innermost (lower to higher values). -For the tag array (in case of multiple tags are supported and present) -``level`` translates directly into the array index. +``tag_index`` is the index of the header inside encapsulation level. +It is used for modify either ``VLAN`` or ``MPLS`` or ``TAG`` headers which +multiple of them might be supported in same encapsulation level. + +.. note:: + + For ``RTE_FLOW_FIELD_TAG`` type, the tag array was provided in ``level`` + field and it is still supported for backwards compatibility. + When ``tag_index`` is zero, the tag array is taken from ``level`` field. ``type`` is used to specify (along with ``class_id``) the Geneve option which is being modified. @@ -3011,7 +3017,9 @@ and provide immediate value 0xXXXX85XX. +=================+==========================================================+ | ``field`` | ID: packet field, mark, meta, tag, immediate, pointer | +-----------------+----------------------------------------------------------+ - | ``level`` | encapsulation level of a packet field or tag array index | + | ``level`` | encapsulation level of a packet field | + +-----------------+----------------------------------------------------------+ + | ``tag_index`` | tag index inside encapsulation level | +-----------------+----------------------------------------------------------+ | ``type`` | geneve option type | +-----------------+----------------------------------------------------------+ diff --git a/doc/guides/rel_notes/release_23_07.rst b/doc/guides/rel_notes/release_23_07.rst index ce1755096f..fd3e35eea3 100644 --- a/doc/guides/rel_notes/release_23_07.rst +++ b/doc/guides/rel_notes/release_23_07.rst @@ -84,8 +84,12 @@ API Changes Also, make sure to start the actual text at the margin. ======================================================= -* The ``level`` field in experimental structure - ``struct rte_flow_action_modify_data`` was reduced to 8 bits. +* ethdev: in experimental structure ``struct rte_flow_action_modify_data``: + + * ``level`` field was reduced to 8 bits. + + * ``tag_index`` field replaced ``level`` field in representing tag array for + ``RTE_FLOW_FIELD_TAG`` type. ABI Changes diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 19f7f92717..867b7b8ea2 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -2318,6 +2318,40 @@ mlx5_validate_action_ct(struct rte_eth_dev *dev, return 0; } +/** + * Validate the level value for modify field action. + * + * @param[in] data + * Pointer to the rte_flow_action_modify_data structure either src or dst. + * @param[out] error + * Pointer to error structure. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +flow_validate_modify_field_level(const struct rte_flow_action_modify_data *data, + struct rte_flow_error *error) +{ + if (data->level == 0) + return 0; + if (data->field != RTE_FLOW_FIELD_TAG) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ACTION, NULL, + "inner header fields modification is not supported"); + if (data->tag_index != 0) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, NULL, + "tag array can be provided using 'level' or 'tag_index' fields, not both"); + /* + * The tag array for RTE_FLOW_FIELD_TAG type is provided using + * 'tag_index' field. In old API, it was provided using 'level' field + * and it is still supported for backwards compatibility. + */ + DRV_LOG(WARNING, "tag array provided in 'level' field instead of 'tag_index' field."); + return 0; +} + /** * Validate ICMP6 item. * diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 1d116ea0f6..cba04b4f45 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1045,6 +1045,26 @@ flow_items_to_tunnel(const struct rte_flow_item items[]) return items[0].spec; } +/** + * Gets the tag array given for RTE_FLOW_FIELD_TAG type. + * + * In old API the value was provided in "level" field, but in new API + * it is provided in "tag_array" field. Since encapsulation level is not + * relevant for metadata, the tag array can be still provided in "level" + * for backwards compatibility. + * + * @param[in] data + * Pointer to tag modify data structure. + * + * @return + * Tag array index. + */ +static inline uint8_t +flow_tag_index_get(const struct rte_flow_action_modify_data *data) +{ + return data->tag_index ? data->tag_index : data->level; +} + /** * Fetch 1, 2, 3 or 4 byte field from the byte array * and return as unsigned integer in host-endian format. @@ -2276,6 +2296,9 @@ int mlx5_flow_validate_action_rss(const struct rte_flow_action *action, int mlx5_flow_validate_action_default_miss(uint64_t action_flags, const struct rte_flow_attr *attr, struct rte_flow_error *error); +int flow_validate_modify_field_level + (const struct rte_flow_action_modify_data *data, + struct rte_flow_error *error); int mlx5_flow_item_acceptable(const struct rte_flow_item *item, const uint8_t *mask, const uint8_t *nic_mask, diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index f136f43b0a..729962a488 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -1896,16 +1896,17 @@ mlx5_flow_field_id_to_modify_info case RTE_FLOW_FIELD_TAG: { MLX5_ASSERT(data->offset + width <= 32); + uint8_t tag_index = flow_tag_index_get(data); int reg; - off_be = (data->level == MLX5_LINEAR_HASH_TAG_INDEX) ? + off_be = (tag_index == MLX5_LINEAR_HASH_TAG_INDEX) ? 16 - (data->offset + width) + 16 : data->offset; if (priv->sh->config.dv_flow_en == 2) reg = flow_hw_get_reg_id(RTE_FLOW_ITEM_TYPE_TAG, - data->level); + tag_index); else reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, - data->level, error); + tag_index, error); if (reg < 0) return; MLX5_ASSERT(reg != REG_NON); @@ -1985,7 +1986,7 @@ mlx5_flow_field_id_to_modify_info { uint32_t meta_mask = priv->sh->dv_meta_mask; uint32_t meta_count = __builtin_popcount(meta_mask); - uint32_t reg = data->level; + uint8_t reg = flow_tag_index_get(data); RTE_SET_USED(meta_count); MLX5_ASSERT(data->offset + width <= meta_count); @@ -5250,6 +5251,14 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev, uint32_t dst_width, src_width; ret = flow_dv_validate_action_modify_hdr(action_flags, action, error); + if (ret) + return ret; + ret = flow_validate_modify_field_level(&action_modify_field->dst, + error); + if (ret) + return ret; + ret = flow_validate_modify_field_level(&action_modify_field->src, + error); if (ret) return ret; if (action_modify_field->src.field == RTE_FLOW_FIELD_FLEX_ITEM || @@ -5279,12 +5288,6 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev, return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, action, "destination offset is too big"); - if (action_modify_field->dst.level && - action_modify_field->dst.field != RTE_FLOW_FIELD_TAG) - return rte_flow_error_set(error, ENOTSUP, - RTE_FLOW_ERROR_TYPE_ACTION, action, - "inner header fields modification" - " is not supported"); } if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE && action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) { @@ -5298,12 +5301,6 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev, return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, action, "source offset is too big"); - if (action_modify_field->src.level && - action_modify_field->src.field != RTE_FLOW_FIELD_TAG) - return rte_flow_error_set(error, ENOTSUP, - RTE_FLOW_ERROR_TYPE_ACTION, action, - "inner header fields modification" - " is not supported"); } if ((action_modify_field->dst.field == action_modify_field->src.field) && diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 1b68a19900..e55e3d6c1a 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -1022,9 +1022,11 @@ flow_hw_modify_field_compile(struct rte_eth_dev *dev, conf->dst.field == RTE_FLOW_FIELD_TAG || conf->dst.field == RTE_FLOW_FIELD_METER_COLOR || conf->dst.field == (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG) { + uint8_t tag_index = flow_tag_index_get(&conf->dst); + value = *(const unaligned_uint32_t *)item.spec; if (conf->dst.field == RTE_FLOW_FIELD_TAG && - conf->dst.level == MLX5_LINEAR_HASH_TAG_INDEX) + tag_index == MLX5_LINEAR_HASH_TAG_INDEX) value = rte_cpu_to_be_32(value << 16); else value = rte_cpu_to_be_32(value); @@ -2055,9 +2057,11 @@ flow_hw_modify_field_construct(struct mlx5_hw_q_job *job, mhdr_action->dst.field == RTE_FLOW_FIELD_TAG || mhdr_action->dst.field == RTE_FLOW_FIELD_METER_COLOR || mhdr_action->dst.field == (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG) { + uint8_t tag_index = flow_tag_index_get(&mhdr_action->dst); + value_p = (unaligned_uint32_t *)values; if (mhdr_action->dst.field == RTE_FLOW_FIELD_TAG && - mhdr_action->dst.level == MLX5_LINEAR_HASH_TAG_INDEX) + tag_index == MLX5_LINEAR_HASH_TAG_INDEX) *value_p = rte_cpu_to_be_32(*value_p << 16); else *value_p = rte_cpu_to_be_32(*value_p); @@ -3546,11 +3550,16 @@ flow_hw_validate_action_modify_field(const struct rte_flow_action *action, const struct rte_flow_action *mask, struct rte_flow_error *error) { - const struct rte_flow_action_modify_field *action_conf = - action->conf; - const struct rte_flow_action_modify_field *mask_conf = - mask->conf; + const struct rte_flow_action_modify_field *action_conf = action->conf; + const struct rte_flow_action_modify_field *mask_conf = mask->conf; + int ret; + ret = flow_validate_modify_field_level(&action_conf->dst, error); + if (ret) + return ret; + ret = flow_validate_modify_field_level(&action_conf->src, error); + if (ret) + return ret; if (action_conf->operation != mask_conf->operation) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, action, diff --git a/lib/ethdev/rte_flow.h b/lib/ethdev/rte_flow.h index f30d4b033f..1df4b49219 100644 --- a/lib/ethdev/rte_flow.h +++ b/lib/ethdev/rte_flow.h @@ -3740,8 +3740,8 @@ enum rte_flow_field_id { RTE_FLOW_FIELD_START = 0, /**< Start of a packet. */ RTE_FLOW_FIELD_MAC_DST, /**< Destination MAC Address. */ RTE_FLOW_FIELD_MAC_SRC, /**< Source MAC Address. */ - RTE_FLOW_FIELD_VLAN_TYPE, /**< 802.1Q Tag Identifier. */ - RTE_FLOW_FIELD_VLAN_ID, /**< 802.1Q VLAN Identifier. */ + RTE_FLOW_FIELD_VLAN_TYPE, /**< VLAN Tag Identifier. */ + RTE_FLOW_FIELD_VLAN_ID, /**< VLAN Identifier. */ RTE_FLOW_FIELD_MAC_TYPE, /**< EtherType. */ RTE_FLOW_FIELD_IPV4_DSCP, /**< IPv4 DSCP. */ RTE_FLOW_FIELD_IPV4_TTL, /**< IPv4 Time To Live. */ @@ -3775,7 +3775,8 @@ enum rte_flow_field_id { RTE_FLOW_FIELD_HASH_RESULT, /**< Hash result. */ RTE_FLOW_FIELD_GENEVE_OPT_TYPE, /**< GENEVE option type */ RTE_FLOW_FIELD_GENEVE_OPT_CLASS,/**< GENEVE option class */ - RTE_FLOW_FIELD_GENEVE_OPT_DATA /**< GENEVE option data */ + RTE_FLOW_FIELD_GENEVE_OPT_DATA, /**< GENEVE option data */ + RTE_FLOW_FIELD_MPLS /**< MPLS header. */ }; /** @@ -3789,7 +3790,7 @@ struct rte_flow_action_modify_data { RTE_STD_C11 union { struct { - /** Encapsulation level or tag index or flex item handle. */ + /** Encapsulation level and tag index or flex item handle. */ union { struct { /** @@ -3820,20 +3821,38 @@ struct rte_flow_action_modify_data { * * Values other than @p 0 are not * necessarily supported. + * + * @note that for MPLS field, + * encapsulation level also include + * tunnel since MPLS may appear in + * outer, inner or tunnel. */ uint8_t level; - /** - * Geneve option type. relevant only - * for RTE_FLOW_FIELD_GENEVE_OPT_XXXX - * modification type. - */ - uint8_t type; - /** - * Geneve option class. relevant only - * for RTE_FLOW_FIELD_GENEVE_OPT_XXXX - * modification type. - */ - rte_be16_t class_id; + union { + /** + * Tag index array inside + * encapsulation level. + * Used for VLAN, MPLS or TAG + * types. + */ + uint8_t tag_index; + /** + * Geneve option identifier. + * relevant only for + * RTE_FLOW_FIELD_GENEVE_OPT_XXXX + * modification type. + */ + struct { + /** + * Geneve option type. + */ + uint8_t type; + /** + * Geneve option class. + */ + rte_be16_t class_id; + }; + }; }; struct rte_flow_item_flex_handle *flex_handle; };