From patchwork Fri Apr 21 18:11:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Randy Schacher X-Patchwork-Id: 126405 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E4708429A8; Fri, 21 Apr 2023 20:12:25 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A4A4F427F5; Fri, 21 Apr 2023 20:12:21 +0200 (CEST) Received: from mail-oa1-f97.google.com (mail-oa1-f97.google.com [209.85.160.97]) by mails.dpdk.org (Postfix) with ESMTP id 65B78410FB for ; Fri, 21 Apr 2023 20:12:19 +0200 (CEST) Received: by mail-oa1-f97.google.com with SMTP id 586e51a60fabf-187b70ab997so12503802fac.0 for ; Fri, 21 Apr 2023 11:12:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1682100738; x=1684692738; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qpvsiJdpfyTuqMaY1TXtFaHTLjYU3VzTIf6dV4GyrZo=; b=VfBebhLdDbb4YicPmeiqR3HvPEjXQk/SqNj9HjgHfDM1jr04+eNTQn5hU8CnQVd0aW yiVwZrqAP+WgF4mAoq/UCqf3Bg8nghtnX6tfD2ER/ckhlPEy4+acxe2rA5vKl3rmwQ+1 Sj51/OIV8qemKpBY6EAlXmEZ3ZRcBD76iu4ak= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682100738; x=1684692738; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qpvsiJdpfyTuqMaY1TXtFaHTLjYU3VzTIf6dV4GyrZo=; b=RSp0PbUpsqEJQSo/u0BRU85PGDGZBZxtl29nPfxzrX0JHHqaPtp1jUqo/whSoTYLp9 GzseSO3BxiS56N3sDGbwVU38ft2Y9U0i+U7dofBywOtBQ8wwtDTQS6AkeJQvXdjevPAu qRx7S9XNH2fs4zuIiAW11G9Nf8evrk2RUrBJso+9MoxNUTMGtim9ZrzYNs20HrlPTlxn ppYQbMS596eWsttypthzxnYo6rdh0Hq33kvJ1Ub9NOt/W3lTzXhh9/efhiG1PqeM7nEg 7DaIIvLl8TWS38mycHzeUReK3ChV3bBg1D+FfrwVWwztgX10X/8Y2bi1RuSgZh4FxJ0u Ar4w== X-Gm-Message-State: AAQBX9fDdg4ujIFRw+ZfqedzjPUDhJYQSWjEtvw8VMm7HAl3b8L5mqve WM1jMrk5dRS9iqafJ6OLx7ZdkCcjEi6UqjdpSCC/4ibDhMDYjAHf53enk0z217JgLUtda7R5sSb vK45lFc7CTmwxK4f6OPYCo1czIrI7BfJscx06XHMAW8xjhYphC1j41NLOwr2qNwvjI2hQUA5Ziv YjqXsffV1ISHwS X-Google-Smtp-Source: AKy350YvD5OwlnOu5AQlBJw2QW/55n988dkX2GGk8AggBoUBPz6vy5R2ryhJFG2imBAyAwrkUFevZWUG95hJ X-Received: by 2002:a05:6870:a792:b0:177:be5e:4532 with SMTP id x18-20020a056870a79200b00177be5e4532mr4352457oao.10.1682100738162; Fri, 21 Apr 2023 11:12:18 -0700 (PDT) Received: from r650-k2.dhcp.broadcom.net ([192.19.144.250]) by smtp-relay.gmail.com with ESMTPS id o21-20020a056870e81500b0017eb57c3417sm397528oan.19.2023.04.21.11.12.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Apr 2023 11:12:18 -0700 (PDT) X-Relaying-Domain: broadcom.com From: Randy Schacher To: dev@dpdk.org Cc: Kishore Padmanabha , Peter Spreadborough Subject: [PATCH v2 01/11] net/bnxt: remove deprecated features Date: Fri, 21 Apr 2023 18:11:45 +0000 Message-Id: <20230421181155.2160482-2-stuart.schacher@broadcom.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230421181155.2160482-1-stuart.schacher@broadcom.com> References: <20230421181155.2160482-1-stuart.schacher@broadcom.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org - Deprecate shadow identifier - Deprecate shadow tcam Signed-off-by: Randy Schacher Signed-off-by: Kishore Padmanabha Reviewed-by: Peter Spreadborough --- drivers/net/bnxt/bnxt_hwrm.c | 53 -- drivers/net/bnxt/bnxt_hwrm.h | 10 - drivers/net/bnxt/tf_core/meson.build | 2 - drivers/net/bnxt/tf_core/tf_core.c | 2 - drivers/net/bnxt/tf_core/tf_core.h | 91 +- drivers/net/bnxt/tf_core/tf_device.c | 35 - drivers/net/bnxt/tf_core/tf_device.h | 6 - drivers/net/bnxt/tf_core/tf_device_p4.c | 10 - drivers/net/bnxt/tf_core/tf_device_p58.c | 10 - drivers/net/bnxt/tf_core/tf_identifier.c | 108 --- drivers/net/bnxt/tf_core/tf_identifier.h | 4 - drivers/net/bnxt/tf_core/tf_if_tbl.h | 8 - drivers/net/bnxt/tf_core/tf_session.c | 9 +- drivers/net/bnxt/tf_core/tf_session.h | 18 +- .../net/bnxt/tf_core/tf_shadow_identifier.c | 190 ---- .../net/bnxt/tf_core/tf_shadow_identifier.h | 229 ----- drivers/net/bnxt/tf_core/tf_shadow_tcam.c | 837 ------------------ drivers/net/bnxt/tf_core/tf_shadow_tcam.h | 195 ---- drivers/net/bnxt/tf_core/tf_tcam.c | 243 ----- drivers/net/bnxt/tf_core/tf_tcam.h | 38 +- drivers/net/bnxt/tf_core/tf_util.c | 2 - drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 3 - 22 files changed, 8 insertions(+), 2095 deletions(-) delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_identifier.c delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_identifier.h delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_tcam.c delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_tcam.h diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index d86ac73293..3f273df6f3 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -407,59 +407,6 @@ int bnxt_hwrm_tf_message_direct(struct bnxt *bp, return rc; } -int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp, - bool use_kong_mb, - uint16_t tf_type, - uint16_t tf_subtype, - uint32_t *tf_response_code, - void *msg, - uint32_t msg_len, - void *response, - uint32_t response_len) -{ - int rc = 0; - struct hwrm_cfa_tflib_input req = { .req_type = 0 }; - struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr; - bool mailbox = BNXT_USE_CHIMP_MB; - - if (msg_len > sizeof(req.tf_req)) - return -ENOMEM; - - if (use_kong_mb) - mailbox = BNXT_USE_KONG(bp); - - HWRM_PREP(&req, HWRM_TF, mailbox); - /* Build request using the user supplied request payload. - * TLV request size is checked at build time against HWRM - * request max size, thus no checking required. - */ - req.tf_type = tf_type; - req.tf_subtype = tf_subtype; - memcpy(req.tf_req, msg, msg_len); - - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox); - HWRM_CHECK_RESULT(); - - /* Copy the resp to user provided response buffer */ - if (response != NULL) - /* Post process response data. We need to copy only - * the 'payload' as the HWRM data structure really is - * HWRM header + msg header + payload and the TFLIB - * only provided a payload place holder. - */ - if (response_len != 0) { - memcpy(response, - resp->tf_resp, - response_len); - } - - /* Extract the internal tflib response code */ - *tf_response_code = resp->tf_resp_code; - HWRM_UNLOCK(); - - return rc; -} - int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic) { int rc = 0; diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h index a82d9fb3ef..f9d9fe0ef2 100644 --- a/drivers/net/bnxt/bnxt_hwrm.h +++ b/drivers/net/bnxt/bnxt_hwrm.h @@ -79,16 +79,6 @@ struct hwrm_func_qstats_output; bp->rx_cos_queue[x].profile = \ resp->queue_id##x##_service_profile -int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp, - bool use_kong_mb, - uint16_t tf_type, - uint16_t tf_subtype, - uint32_t *tf_response_code, - void *msg, - uint32_t msg_len, - void *response, - uint32_t response_len); - int bnxt_hwrm_tf_message_direct(struct bnxt *bp, bool use_kong_mb, uint16_t msg_type, diff --git a/drivers/net/bnxt/tf_core/meson.build b/drivers/net/bnxt/tf_core/meson.build index 206935d18a..f812e471d1 100644 --- a/drivers/net/bnxt/tf_core/meson.build +++ b/drivers/net/bnxt/tf_core/meson.build @@ -30,9 +30,7 @@ sources += files( 'tf_identifier.c', 'tf_if_tbl.c', 'tf_session.c', - 'tf_shadow_tcam.c', 'tf_tcam.c', 'tf_tcam_shared.c', - 'tf_shadow_identifier.c', 'tf_hash.c', 'tf_device_p58.c') diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index 90ff93946b..038e439101 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -917,7 +917,6 @@ tf_free_tcam_entry(struct tf *tfp, return 0; } -#ifdef TF_TCAM_SHARED int tf_move_tcam_shared_entries(struct tf *tfp, struct tf_move_tcam_shared_entries_parms *parms) @@ -1019,7 +1018,6 @@ tf_clear_tcam_shared_entries(struct tf *tfp, return 0; } -#endif /* TF_TCAM_SHARED */ int tf_alloc_tbl_entry(struct tf *tfp, diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index f891d7a48f..814eff68da 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -337,41 +337,6 @@ enum tf_tbl_type { TF_TBL_TYPE_MAX }; -/** Enable Shared TCAM Management - * - * This feature allows for management of high and low pools within - * the WC TCAM. These pools are only valid when this feature is enabled. - * - * For normal OVS-DPDK operation, this feature is not required and can - * be disabled by commenting out TF_TCAM_SHARED in this header file. - * - * Operation: - * - * When a shared session is created with WC TCAM entries allocated during - * tf_open_session(), the TF_TCAM_TBL_TYPE_WC_TCAM pool entries will be divided - * into 2 equal pools - TF_TCAM_TBL_TYPE_WC_TCAM_HIGH and - * TF_TCAM_TBL_TYPE_WC_TCAM_LOW. - * - * The user will allocate and free entries from either of these pools to obtain - * WC_TCAM entry offsets. For the WC_TCAM_HI/LO management, alloc/free is done - * using the tf_alloc_tcam_entry()/tf_free_tcam_entry() APIs for the shared - * session. - * - * The use case for this feature is so that applications can have a shared - * session and use the TF core to allocate/set/free entries within a given - * region of the WC_TCAM within the shared session. Application A only writes - * to the LOW region for example and Application B only writes to the HIGH - * region during normal operation. After Application A goes down, Application - * B may decide to overwrite the LOW region with the HIGH region's entries - * and switch to the low region. - * - * For other TCAM types in the shared session, no alloc/free operations are - * permitted. Only set should be used for other TCAM table types after getting - * the range as provided by the tf_get_resource_info() API. - * - */ -#define TF_TCAM_SHARED 1 - /** * TCAM table type */ @@ -390,12 +355,10 @@ enum tf_tcam_tbl_type { TF_TCAM_TBL_TYPE_CT_RULE_TCAM, /** Virtual Edge Bridge TCAM */ TF_TCAM_TBL_TYPE_VEB_TCAM, -#ifdef TF_TCAM_SHARED /** Wildcard TCAM HI Priority */ TF_TCAM_TBL_TYPE_WC_TCAM_HIGH, /** Wildcard TCAM Low Priority */ TF_TCAM_TBL_TYPE_WC_TCAM_LOW, -#endif /* TF_TCAM_SHARED */ TF_TCAM_TBL_TYPE_MAX }; @@ -626,20 +589,6 @@ struct tf_open_session_parms { * 0000:02:00.0. The name for shared session is 0000:02:00.0-tf_shared. */ char ctrl_chan_name[TF_SESSION_NAME_MAX]; - /** - * [in] shadow_copy - * - * Boolean controlling the use and availability of shadow - * copy. Shadow copy will allow the TruFlow to keep track of - * resource content on the firmware side without having to - * query firmware. Additional private session core_data will - * be allocated if this boolean is set to 'true', default - * 'false'. - * - * Size of memory depends on the NVM Resource settings for the - * control channel. - */ - bool shadow_copy; /** * [in/out] session_id * @@ -1045,9 +994,6 @@ struct tf_search_identifier_parms { * TruFlow core will allocate a free id from the per identifier resource type * pool reserved for the session during tf_open(). No firmware is involved. * - * If shadow copy is enabled, the internal ref_cnt is set to 1 in the - * shadow table for a newly allocated resource. - * * Returns success or failure code. */ int tf_alloc_identifier(struct tf *tfp, @@ -1061,8 +1007,7 @@ int tf_alloc_identifier(struct tf *tfp, * complete pool is returned to the firmware. * * additional operation (experimental) - * Decrement reference count. Only release resource once refcnt goes to 0 if - * shadow copy is enabled. + * Decrement reference count. * * Returns success or failure code. */ @@ -1072,19 +1017,6 @@ int tf_free_identifier(struct tf *tfp, /** * Search identifier resource (experimental) * - * If the shadow copy is enabled search_id is used to search for a matching - * entry in the shadow table. The shadow table consists of an array of - * reference counts indexed by identifier. If a matching entry is found hit is - * set to TRUE, refcnt is increased by 1 and returned. Otherwise, hit is - * set to false and refcnt is set to 0. - * - * TODO: we may need a per table internal shadow copy enable flag to stage - * the shadow table implementation. We do not need the shadow table for other - * tables at this time so we may only want to enable the identifier shadow. - * - * TODO: remove this pseudocode below added to show that if search fails - * we shouldn't allocate a new entry but return. - * * identifier alloc (search_en=1) * if (ident is allocated and ref_cnt >=1) * return ident - hit is set, incr refcnt @@ -1262,11 +1194,9 @@ int tf_free_tbl_scope(struct tf *tfp, * * @ref tf_free_tcam_entry * -#ifdef TF_TCAM_SHARED * @ref tf_move_tcam_shared_entries * * @ref tf_clear_tcam_shared_entries -#endif */ /** @@ -1332,14 +1262,9 @@ struct tf_search_tcam_entry_parms { * * Search for a TCAM entry * - * This function searches the shadow copy of the TCAM table for a matching - * entry. Key and mask must match for hit to be set. Only TruFlow core data - * is accessed. If shadow_copy is not enabled, an error is returned. - * * Implementation: * - * A hash is performed on the key/mask data and mapped to a shadow copy entry - * where the full key/mask is populated. If the full key/mask matches the + * If the full key/mask matches the * entry, hit is set, ref_cnt is incremented, and search_status indicates what * action the caller can take regarding setting the entry. * @@ -1416,8 +1341,7 @@ struct tf_alloc_tcam_entry_parms { * * This function allocates a TCAM table record. This function * will attempt to allocate a TCAM table entry from the session - * owned TCAM entries or search a shadow copy of the TCAM table for a - * matching entry if search is enabled. Key, mask and result must match for + * owned TCAM entries. Key, mask and result must match for * hit to be set. Only TruFlow core data is accessed. * A hash table to entry mapping is maintained for search purposes. If * search is not enabled, the first available free entry is returned based @@ -1568,7 +1492,6 @@ struct tf_free_tcam_entry_parms { int tf_free_tcam_entry(struct tf *tfp, struct tf_free_tcam_entry_parms *parms); -#ifdef TF_TCAM_SHARED /** * tf_move_tcam_shared_entries parameter definition */ @@ -1633,7 +1556,6 @@ struct tf_clear_tcam_shared_entries_parms { int tf_clear_tcam_shared_entries(struct tf *tfp, struct tf_clear_tcam_shared_entries_parms *parms); -#endif /* TF_TCAM_SHARED */ /** * @page table Table Access * @@ -1854,9 +1776,6 @@ struct tf_get_tbl_entry_parms { * * Used to retrieve a previous set index table entry. * - * Reads and compares with the shadow table copy (if enabled) (only - * for internal objects). - * * Returns success or failure code. Failure will be returned if the * provided data buffer is too small for the data type requested. */ @@ -2165,9 +2084,7 @@ int tf_delete_em_entry(struct tf *tfp, * succeeds, a pointer to the matching entry and the result record associated * with the matching entry will be provided. * - * If flow_handle is set, search shadow copy. - * - * Otherwise, query the fw with key to get result. + * Query the fw with key to get result. * * External: * diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c index a35d22841c..1c97218b5b 100644 --- a/drivers/net/bnxt/tf_core/tf_device.c +++ b/drivers/net/bnxt/tf_core/tf_device.c @@ -9,10 +9,8 @@ #include "tfp.h" #include "tf_em.h" #include "tf_rm.h" -#ifdef TF_TCAM_SHARED #include "tf_tcam_shared.h" #include "tf_tbl_sram.h" -#endif /* TF_TCAM_SHARED */ struct tf; @@ -67,9 +65,6 @@ tf_dev_reservation_check(uint16_t count, * [in] tfp * Pointer to TF handle * - * [in] shadow_copy - * Flag controlling shadow copy DB creation - * * [in] resources * Pointer to resource allocation information * @@ -82,7 +77,6 @@ tf_dev_reservation_check(uint16_t count, */ static int tf_dev_bind_p4(struct tf *tfp, - bool shadow_copy, struct tf_session_resources *resources, struct tf_dev_info *dev_handle, enum tf_wc_num_slice wc_num_slices) @@ -115,7 +109,6 @@ tf_dev_bind_p4(struct tf *tfp, if (rsv_cnt) { ident_cfg.num_elements = TF_IDENT_TYPE_MAX; ident_cfg.cfg = tf_ident_p4; - ident_cfg.shadow_copy = shadow_copy; ident_cfg.resources = resources; rc = tf_ident_bind(tfp, &ident_cfg); if (rc) { @@ -150,14 +143,9 @@ tf_dev_bind_p4(struct tf *tfp, if (rsv_cnt) { tcam_cfg.num_elements = TF_TCAM_TBL_TYPE_MAX; tcam_cfg.cfg = tf_tcam_p4; - tcam_cfg.shadow_copy = shadow_copy; tcam_cfg.resources = resources; tcam_cfg.wc_num_slices = wc_num_slices; -#ifdef TF_TCAM_SHARED rc = tf_tcam_shared_bind(tfp, &tcam_cfg); -#else /* !TF_TCAM_SHARED */ - rc = tf_tcam_bind(tfp, &tcam_cfg); -#endif if (rc) { TFP_DRV_LOG(ERR, "TCAM initialization failure\n"); @@ -223,7 +211,6 @@ tf_dev_bind_p4(struct tf *tfp, */ if_tbl_cfg.num_elements = TF_IF_TBL_TYPE_MAX; if_tbl_cfg.cfg = tf_if_tbl_p4; - if_tbl_cfg.shadow_copy = shadow_copy; rc = tf_if_tbl_bind(tfp, &if_tbl_cfg); if (rc) { TFP_DRV_LOG(ERR, @@ -287,11 +274,7 @@ tf_dev_unbind_p4(struct tf *tfp) * In case of residuals TCAMs are cleaned up first as to * invalidate the pipeline in a clean manner. */ -#ifdef TF_TCAM_SHARED rc = tf_tcam_shared_unbind(tfp); -#else /* !TF_TCAM_SHARED */ - rc = tf_tcam_unbind(tfp); -#endif /* TF_TCAM_SHARED */ if (rc) { TFP_DRV_LOG(INFO, "Device unbind failed, TCAM\n"); @@ -354,9 +337,6 @@ tf_dev_unbind_p4(struct tf *tfp) * [in] tfp * Pointer to TF handle * - * [in] shadow_copy - * Flag controlling shadow copy DB creation - * * [in] resources * Pointer to resource allocation information * @@ -369,7 +349,6 @@ tf_dev_unbind_p4(struct tf *tfp) */ static int tf_dev_bind_p58(struct tf *tfp, - bool shadow_copy, struct tf_session_resources *resources, struct tf_dev_info *dev_handle, enum tf_wc_num_slice wc_num_slices) @@ -400,7 +379,6 @@ tf_dev_bind_p58(struct tf *tfp, if (rsv_cnt) { ident_cfg.num_elements = TF_IDENT_TYPE_MAX; ident_cfg.cfg = tf_ident_p58; - ident_cfg.shadow_copy = shadow_copy; ident_cfg.resources = resources; rc = tf_ident_bind(tfp, &ident_cfg); if (rc) { @@ -443,14 +421,9 @@ tf_dev_bind_p58(struct tf *tfp, if (rsv_cnt) { tcam_cfg.num_elements = TF_TCAM_TBL_TYPE_MAX; tcam_cfg.cfg = tf_tcam_p58; - tcam_cfg.shadow_copy = shadow_copy; tcam_cfg.resources = resources; tcam_cfg.wc_num_slices = wc_num_slices; -#ifdef TF_TCAM_SHARED rc = tf_tcam_shared_bind(tfp, &tcam_cfg); -#else /* !TF_TCAM_SHARED */ - rc = tf_tcam_bind(tfp, &tcam_cfg); -#endif if (rc) { TFP_DRV_LOG(ERR, "TCAM initialization failure\n"); @@ -495,7 +468,6 @@ tf_dev_bind_p58(struct tf *tfp, */ if_tbl_cfg.num_elements = TF_IF_TBL_TYPE_MAX; if_tbl_cfg.cfg = tf_if_tbl_p58; - if_tbl_cfg.shadow_copy = shadow_copy; rc = tf_if_tbl_bind(tfp, &if_tbl_cfg); if (rc) { TFP_DRV_LOG(ERR, @@ -560,11 +532,7 @@ tf_dev_unbind_p58(struct tf *tfp) * In case of residuals TCAMs are cleaned up first as to * invalidate the pipeline in a clean manner. */ -#ifdef TF_TCAM_SHARED rc = tf_tcam_shared_unbind(tfp); -#else /* !TF_TCAM_SHARED */ - rc = tf_tcam_unbind(tfp); -#endif /* TF_TCAM_SHARED */ if (rc) { TFP_DRV_LOG(INFO, "Device unbind failed, TCAM\n"); @@ -629,7 +597,6 @@ tf_dev_unbind_p58(struct tf *tfp) int tf_dev_bind(struct tf *tfp __rte_unused, enum tf_device_type type, - bool shadow_copy, struct tf_session_resources *resources, uint16_t wc_num_slices, struct tf_dev_info *dev_handle) @@ -639,14 +606,12 @@ tf_dev_bind(struct tf *tfp __rte_unused, case TF_DEVICE_TYPE_SR: dev_handle->type = type; return tf_dev_bind_p4(tfp, - shadow_copy, resources, dev_handle, wc_num_slices); case TF_DEVICE_TYPE_THOR: dev_handle->type = type; return tf_dev_bind_p58(tfp, - shadow_copy, resources, dev_handle, wc_num_slices); diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index bfb5de4370..bc6de60423 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -11,9 +11,7 @@ #include "tf_identifier.h" #include "tf_tbl.h" #include "tf_tcam.h" -#ifdef TF_TCAM_SHARED #include "tf_tcam_shared.h" -#endif #include "tf_if_tbl.h" #include "tf_global_cfg.h" @@ -86,7 +84,6 @@ struct tf_hcapi_resource_map { */ int tf_dev_bind(struct tf *tfp, enum tf_device_type type, - bool shadow_copy, struct tf_session_resources *resources, uint16_t wc_num_slices, struct tf_dev_info *dev_handle); @@ -705,7 +702,6 @@ struct tf_dev_ops { int (*tf_dev_get_tcam)(struct tf *tfp, struct tf_tcam_get_parms *parms); -#ifdef TF_TCAM_SHARED /** * Move TCAM shared entries * @@ -738,8 +734,6 @@ struct tf_dev_ops { int (*tf_dev_clear_tcam)(struct tf *tfp, struct tf_clear_tcam_shared_entries_parms *parms); -#endif /* TF_TCAM_SHARED */ - /** * Retrieves the tcam resource info. * diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index b8b3dcbb3f..72c6b1cde8 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -10,9 +10,7 @@ #include "tf_identifier.h" #include "tf_tbl.h" #include "tf_tcam.h" -#ifdef TF_TCAM_SHARED #include "tf_tcam_shared.h" -#endif /* TF_TCAM_SHARED */ #include "tf_em.h" #include "tf_if_tbl.h" #include "tfp.h" @@ -540,20 +538,12 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_get_bulk_sram_tbl = NULL, .tf_dev_get_shared_tbl_increment = tf_dev_p4_get_shared_tbl_increment, .tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info, -#ifdef TF_TCAM_SHARED .tf_dev_alloc_tcam = tf_tcam_shared_alloc, .tf_dev_free_tcam = tf_tcam_shared_free, .tf_dev_set_tcam = tf_tcam_shared_set, .tf_dev_get_tcam = tf_tcam_shared_get, .tf_dev_move_tcam = tf_tcam_shared_move_p4, .tf_dev_clear_tcam = tf_tcam_shared_clear, -#else /* !TF_TCAM_SHARED */ - .tf_dev_alloc_tcam = tf_tcam_alloc, - .tf_dev_free_tcam = tf_tcam_free, - .tf_dev_set_tcam = tf_tcam_set, - .tf_dev_get_tcam = tf_tcam_get, -#endif - .tf_dev_alloc_search_tcam = tf_tcam_alloc_search, .tf_dev_get_tcam_resc_info = tf_tcam_get_resc_info, .tf_dev_insert_int_em_entry = tf_em_insert_int_entry, .tf_dev_delete_int_em_entry = tf_em_delete_int_entry, diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 8179287e46..f8b424ebc9 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -10,9 +10,7 @@ #include "tf_identifier.h" #include "tf_tbl.h" #include "tf_tcam.h" -#ifdef TF_TCAM_SHARED #include "tf_tcam_shared.h" -#endif /* TF_TCAM_SHARED */ #include "tf_em.h" #include "tf_if_tbl.h" #include "tfp.h" @@ -848,20 +846,12 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_get_bulk_sram_tbl = tf_tbl_sram_bulk_get, .tf_dev_get_shared_tbl_increment = tf_dev_p58_get_shared_tbl_increment, .tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info, -#ifdef TF_TCAM_SHARED .tf_dev_alloc_tcam = tf_tcam_shared_alloc, .tf_dev_free_tcam = tf_tcam_shared_free, .tf_dev_set_tcam = tf_tcam_shared_set, .tf_dev_get_tcam = tf_tcam_shared_get, .tf_dev_move_tcam = tf_tcam_shared_move_p58, .tf_dev_clear_tcam = tf_tcam_shared_clear, -#else /* !TF_TCAM_SHARED */ - .tf_dev_alloc_tcam = tf_tcam_alloc, - .tf_dev_free_tcam = tf_tcam_free, - .tf_dev_set_tcam = tf_tcam_set, - .tf_dev_get_tcam = tf_tcam_get, -#endif - .tf_dev_alloc_search_tcam = tf_tcam_alloc_search, .tf_dev_get_tcam_resc_info = tf_tcam_get_resc_info, .tf_dev_insert_int_em_entry = tf_em_hash_insert_int_entry, .tf_dev_delete_int_em_entry = tf_em_hash_delete_int_entry, diff --git a/drivers/net/bnxt/tf_core/tf_identifier.c b/drivers/net/bnxt/tf_core/tf_identifier.c index c491f77a2b..8131d8754d 100644 --- a/drivers/net/bnxt/tf_core/tf_identifier.c +++ b/drivers/net/bnxt/tf_core/tf_identifier.c @@ -6,7 +6,6 @@ #include #include "tf_identifier.h" -#include "tf_shadow_identifier.h" #include "tf_common.h" #include "tf_rm.h" #include "tf_util.h" @@ -15,16 +14,6 @@ struct tf; -/** - * Identifier shadow DBs. - */ -static void *ident_shadow_db[TF_DIR_MAX]; - -/** - * Shadow DB Init flag, set on bind and cleared on unbind - */ -static uint8_t shadow_init; - int tf_ident_bind(struct tf *tfp, struct tf_ident_cfg_parms *parms) @@ -33,8 +22,6 @@ tf_ident_bind(struct tf *tfp, int db_rc[TF_DIR_MAX] = { 0 }; int i; struct tf_rm_create_db_parms db_cfg = { 0 }; - struct tf_shadow_ident_cfg_parms shadow_cfg = { 0 }; - struct tf_shadow_ident_create_db_parms shadow_cdb = { 0 }; struct ident_rm_db *ident_db; struct tfp_calloc_parms cparms; struct tf_session *tfs; @@ -74,23 +61,6 @@ tf_ident_bind(struct tf *tfp, db_rc[i] = tf_rm_create_db_no_reservation(tfp, &db_cfg); else db_rc[i] = tf_rm_create_db(tfp, &db_cfg); - - if (parms->shadow_copy) { - shadow_cfg.alloc_cnt = - parms->resources->ident_cnt[i].cnt; - shadow_cdb.num_elements = parms->num_elements; - shadow_cdb.tf_shadow_ident_db = &ident_shadow_db[i]; - shadow_cdb.cfg = &shadow_cfg; - rc = tf_shadow_ident_create_db(&shadow_cdb); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Ident shadow DB creation failed\n", - tf_dir_2_str(i)); - - return rc; - } - shadow_init = 1; - } } /* No db created */ @@ -111,7 +81,6 @@ tf_ident_unbind(struct tf *tfp) int rc = 0; int i; struct tf_rm_free_db_parms fparms = { 0 }; - struct tf_shadow_ident_free_db_parms sparms = { 0 }; struct ident_rm_db *ident_db; void *ident_db_ptr = NULL; @@ -132,22 +101,8 @@ tf_ident_unbind(struct tf *tfp) TFP_DRV_LOG(ERR, "rm free failed on unbind\n"); } - if (shadow_init) { - sparms.tf_shadow_ident_db = ident_shadow_db[i]; - rc = tf_shadow_ident_free_db(&sparms); - if (rc) { - /* TODO: If there are failures on unbind we - * really just have to try until all DBs are - * attempted to be cleared. - */ - } - ident_shadow_db[i] = NULL; - } ident_db->ident_db[i] = NULL; } - - shadow_init = 0; - return 0; } @@ -159,7 +114,6 @@ tf_ident_alloc(struct tf *tfp __rte_unused, uint32_t id; uint32_t base_id; struct tf_rm_allocate_parms aparms = { 0 }; - struct tf_shadow_ident_insert_parms iparms = { 0 }; struct ident_rm_db *ident_db; void *ident_db_ptr = NULL; @@ -187,23 +141,7 @@ tf_ident_alloc(struct tf *tfp __rte_unused, return rc; } - if (shadow_init) { - iparms.tf_shadow_ident_db = ident_shadow_db[parms->dir]; - iparms.type = parms->type; - iparms.id = base_id; - - rc = tf_shadow_ident_insert(&iparms); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Failed insert shadow DB, type:%d\n", - tf_dir_2_str(parms->dir), - parms->type); - return rc; - } - } - *parms->id = id; - return 0; } @@ -214,7 +152,6 @@ tf_ident_free(struct tf *tfp __rte_unused, int rc; struct tf_rm_is_allocated_parms aparms = { 0 }; struct tf_rm_free_parms fparms = { 0 }; - struct tf_shadow_ident_remove_parms rparms = { 0 }; int allocated = 0; uint32_t base_id; struct ident_rm_db *ident_db; @@ -250,27 +187,6 @@ tf_ident_free(struct tf *tfp __rte_unused, return -EINVAL; } - if (shadow_init) { - rparms.tf_shadow_ident_db = ident_shadow_db[parms->dir]; - rparms.type = parms->type; - rparms.id = base_id; - rparms.ref_cnt = parms->ref_cnt; - - rc = tf_shadow_ident_remove(&rparms); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: ref_cnt was 0 in shadow DB," - " type:%d, index:%d\n", - tf_dir_2_str(parms->dir), - parms->type, - parms->id); - return rc; - } - - if (*rparms.ref_cnt > 0) - return 0; - } - /* Free requested element */ fparms.rm_db = ident_db->ident_db[parms->dir]; fparms.subtype = parms->type; @@ -294,7 +210,6 @@ tf_ident_search(struct tf *tfp __rte_unused, { int rc; struct tf_rm_is_allocated_parms aparms = { 0 }; - struct tf_shadow_ident_search_parms sparms = { 0 }; int allocated = 0; uint32_t base_id; struct ident_rm_db *ident_db; @@ -302,13 +217,6 @@ tf_ident_search(struct tf *tfp __rte_unused, TF_CHECK_PARMS2(tfp, parms); - if (!shadow_init) { - TFP_DRV_LOG(ERR, - "%s: Identifier Shadow copy is not enabled\n", - tf_dir_2_str(parms->dir)); - return -EINVAL; - } - rc = tf_session_get_db(tfp, TF_MODULE_TYPE_IDENTIFIER, &ident_db_ptr); if (rc) { TFP_DRV_LOG(ERR, @@ -336,22 +244,6 @@ tf_ident_search(struct tf *tfp __rte_unused, parms->search_id); return -EINVAL; } - - sparms.tf_shadow_ident_db = ident_shadow_db[parms->dir]; - sparms.type = parms->type; - sparms.search_id = base_id; - sparms.hit = parms->hit; - sparms.ref_cnt = parms->ref_cnt; - - rc = tf_shadow_ident_search(&sparms); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Failed search shadow DB, type:%d\n", - tf_dir_2_str(parms->dir), - parms->type); - return rc; - } - return 0; } diff --git a/drivers/net/bnxt/tf_core/tf_identifier.h b/drivers/net/bnxt/tf_core/tf_identifier.h index 55c093802e..285ff11ce2 100644 --- a/drivers/net/bnxt/tf_core/tf_identifier.h +++ b/drivers/net/bnxt/tf_core/tf_identifier.h @@ -22,10 +22,6 @@ struct tf_ident_cfg_parms { * [in] Identifier configuration array */ struct tf_rm_element_cfg *cfg; - /** - * [in] Boolean controlling the request shadow copy. - */ - bool shadow_copy; /** * [in] Session resource allocations */ diff --git a/drivers/net/bnxt/tf_core/tf_if_tbl.h b/drivers/net/bnxt/tf_core/tf_if_tbl.h index 9f081c8196..bea2f07324 100644 --- a/drivers/net/bnxt/tf_core/tf_if_tbl.h +++ b/drivers/net/bnxt/tf_core/tf_if_tbl.h @@ -84,14 +84,6 @@ struct tf_if_tbl_cfg_parms { * Table Type element configuration array */ struct tf_if_tbl_cfg *cfg; - /** - * Shadow table type configuration array - */ - struct tf_shadow_if_tbl_cfg *shadow_cfg; - /** - * Boolean controlling the request shadow copy. - */ - bool shadow_copy; }; /** diff --git a/drivers/net/bnxt/tf_core/tf_session.c b/drivers/net/bnxt/tf_core/tf_session.c index c30c0e7029..d0a0916c6a 100644 --- a/drivers/net/bnxt/tf_core/tf_session.c +++ b/drivers/net/bnxt/tf_core/tf_session.c @@ -141,8 +141,6 @@ tf_session_create(struct tf *tfp, /* Return the allocated session id */ session_id->id = session->session_id.id; - session->shadow_copy = parms->open_cfg->shadow_copy; - /* Init session client list */ ll_init(&session->client_ll); @@ -200,7 +198,6 @@ tf_session_create(struct tf *tfp, rc = tf_dev_bind(tfp, parms->open_cfg->device_type, - session->shadow_copy, &parms->open_cfg->resources, parms->open_cfg->wc_num_slices, &session->dev); @@ -360,7 +357,7 @@ tf_session_client_create(struct tf *tfp, * - (-EINVAL) on failure. * - (-ENOTFOUND) error, client not owned by the session. * - (-ENOTSUPP) error, unable to destroy client as its the last - * client. Please use the tf_session_close(). + * client. Please use the tf_session_close(). */ static int tf_session_client_destroy(struct tf *tfp, @@ -992,8 +989,6 @@ tf_session_set_db(struct tf *tfp, return rc; } -#ifdef TF_TCAM_SHARED - int tf_session_get_tcam_shared_db(struct tf *tfp, void **tcam_shared_db_handle) @@ -1070,8 +1065,6 @@ tf_session_set_sram_db(struct tf *tfp, return rc; } -#endif /* TF_TCAM_SHARED */ - int tf_session_get_global_db(struct tf *tfp, void **global_handle) diff --git a/drivers/net/bnxt/tf_core/tf_session.h b/drivers/net/bnxt/tf_core/tf_session.h index 19a96c28b1..a6716dfff4 100644 --- a/drivers/net/bnxt/tf_core/tf_session.h +++ b/drivers/net/bnxt/tf_core/tf_session.h @@ -48,8 +48,7 @@ * * Shared memory containing private TruFlow session information. * Through this structure the session can keep track of resource - * allocations and (if so configured) any shadow copy of flow - * information. It also holds info about Session Clients. + * allocations. It also holds info about Session Clients. * * Memory is assigned to the Truflow instance by way of * tf_open_session. Memory is allocated and owned by i.e. ULP. @@ -86,19 +85,6 @@ struct tf_session { */ bool shared_session_creator; - /** - * Boolean controlling the use and availability of shadow - * copy. Shadow copy will allow the TruFlow Core to keep track - * of resource content on the firmware side without having to - * query firmware. Additional private session core_data will - * be allocated if this boolean is set to 'true', default - * 'false'. - * - * Size of memory depends on the NVM Resource settings for the - * control channel. - */ - bool shadow_copy; - /** * Session Reference Count. To keep track of functions per * session the ref_count is updated. There is also a @@ -159,12 +145,10 @@ struct tf_session { */ void *em_pool[TF_DIR_MAX]; -#ifdef TF_TCAM_SHARED /** * tcam db reference for the session */ void *tcam_shared_db_handle; -#endif /* TF_TCAM_SHARED */ /** * SRAM db reference for the session diff --git a/drivers/net/bnxt/tf_core/tf_shadow_identifier.c b/drivers/net/bnxt/tf_core/tf_shadow_identifier.c deleted file mode 100644 index dc9606712c..0000000000 --- a/drivers/net/bnxt/tf_core/tf_shadow_identifier.c +++ /dev/null @@ -1,190 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom - * All rights reserved. - */ - -#include - -#include "tf_shadow_identifier.h" -#include "tf_common.h" -#include "tf_util.h" -#include "tfp.h" - -/** - * Shadow identifier DB element - */ -struct tf_shadow_ident_element { - /** - * Identifier - */ - uint32_t *id; - - /** - * Reference count, array of number of identifier type entries - */ - uint32_t *ref_count; -}; - -/** - * Shadow identifier DB definition - */ -struct tf_shadow_ident_db { - /** - * Number of elements in the DB - */ - uint16_t num_entries; - - /** - * The DB consists of an array of elements - */ - struct tf_shadow_ident_element *db; -}; - -int -tf_shadow_ident_create_db(struct tf_shadow_ident_create_db_parms *parms) -{ - int rc; - int i; - struct tfp_calloc_parms cparms; - struct tf_shadow_ident_db *shadow_db; - struct tf_shadow_ident_element *db; - - TF_CHECK_PARMS1(parms); - - /* Build the shadow DB per the request */ - cparms.nitems = 1; - cparms.size = sizeof(struct tf_shadow_ident_db); - cparms.alignment = 0; - rc = tfp_calloc(&cparms); - if (rc) - return rc; - shadow_db = (void *)cparms.mem_va; - - /* Build the DB within shadow DB */ - cparms.nitems = parms->num_elements; - cparms.size = sizeof(struct tf_shadow_ident_element); - rc = tfp_calloc(&cparms); - if (rc) - return rc; - shadow_db->db = (struct tf_shadow_ident_element *)cparms.mem_va; - shadow_db->num_entries = parms->num_elements; - - db = shadow_db->db; - for (i = 0; i < parms->num_elements; i++) { - /* If the element didn't request an allocation no need - * to create a pool nor verify if we got a reservation. - */ - if (parms->cfg->alloc_cnt[i] == 0) - continue; - - /* Create array */ - cparms.nitems = parms->cfg->alloc_cnt[i]; - cparms.size = sizeof(uint32_t); - rc = tfp_calloc(&cparms); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Array alloc failed, type:%d\n", - tf_dir_2_str(parms->dir), - i); - goto fail; - } - db[i].ref_count = (uint32_t *)cparms.mem_va; - } - - *parms->tf_shadow_ident_db = (void *)shadow_db; - - return 0; -fail: - tfp_free((void *)db->ref_count); - tfp_free((void *)db); - tfp_free((void *)shadow_db); - parms->tf_shadow_ident_db = NULL; - - return -EINVAL; -} - -int -tf_shadow_ident_free_db(struct tf_shadow_ident_free_db_parms *parms) -{ - int i; - struct tf_shadow_ident_db *shadow_db; - - TF_CHECK_PARMS1(parms); - - shadow_db = (struct tf_shadow_ident_db *)parms->tf_shadow_ident_db; - for (i = 0; i < shadow_db->num_entries; i++) - tfp_free((void *)shadow_db->db[i].ref_count); - - tfp_free((void *)shadow_db->db); - tfp_free((void *)parms->tf_shadow_ident_db); - - return 0; -} - -int -tf_shadow_ident_search(struct tf_shadow_ident_search_parms *parms) -{ - struct tf_shadow_ident_db *shadow_db; - uint32_t ref_cnt = 0; - - TF_CHECK_PARMS1(parms); - - shadow_db = (struct tf_shadow_ident_db *)parms->tf_shadow_ident_db; - ref_cnt = shadow_db->db[parms->type].ref_count[parms->search_id]; - if (ref_cnt > 0) { - *parms->hit = 1; - *parms->ref_cnt = ++ref_cnt; - shadow_db->db[parms->type].ref_count[parms->search_id] = - ref_cnt; - } else { - *parms->hit = 0; - *parms->ref_cnt = 0; - } - - - return 0; -} - -#define ID_REF_CNT_MAX 0xffffffff -int -tf_shadow_ident_insert(struct tf_shadow_ident_insert_parms *parms) -{ - struct tf_shadow_ident_db *shadow_db; - - TF_CHECK_PARMS1(parms); - - shadow_db = (struct tf_shadow_ident_db *)parms->tf_shadow_ident_db; - - /* In case of overflow, ref count keeps the max value */ - if (shadow_db->db[parms->type].ref_count[parms->id] < ID_REF_CNT_MAX) - shadow_db->db[parms->type].ref_count[parms->id]++; - else - TFP_DRV_LOG(ERR, - "Identifier %d in type %d reaches the max ref_cnt\n", - parms->type, - parms->id); - - parms->ref_cnt = shadow_db->db[parms->type].ref_count[parms->id]; - - return 0; -} - -int -tf_shadow_ident_remove(struct tf_shadow_ident_remove_parms *parms) -{ - struct tf_shadow_ident_db *shadow_db; - uint32_t ref_cnt = 0; - - TF_CHECK_PARMS1(parms); - - shadow_db = (struct tf_shadow_ident_db *)parms->tf_shadow_ident_db; - ref_cnt = shadow_db->db[parms->type].ref_count[parms->id]; - if (ref_cnt > 0) - shadow_db->db[parms->type].ref_count[parms->id]--; - else - return -EINVAL; - - *parms->ref_cnt = shadow_db->db[parms->type].ref_count[parms->id]; - - return 0; -} diff --git a/drivers/net/bnxt/tf_core/tf_shadow_identifier.h b/drivers/net/bnxt/tf_core/tf_shadow_identifier.h deleted file mode 100644 index ff41eaad9f..0000000000 --- a/drivers/net/bnxt/tf_core/tf_shadow_identifier.h +++ /dev/null @@ -1,229 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom - * All rights reserved. - */ - -#ifndef _TF_SHADOW_IDENTIFIER_H_ -#define _TF_SHADOW_IDENTIFIER_H_ - -#include "tf_core.h" - -struct tf; - -/** - * The Shadow Identifier module provides shadow DB handling for identifier based - * TF types. A shadow DB provides the capability that allows for reuse - * of TF resources. - * - * A Shadow identifier DB is intended to be used by the Identifier Type module - * only. - */ - -/** - * Shadow DB configuration information for a single identifier type. - * - * It is used in an array of identifier types. The array must be ordered - * by the TF type is represents. - */ -struct tf_shadow_ident_cfg_parms { - /** - * TF Identifier type - */ - enum tf_identifier_type type; - - /** - * Number of entries the Shadow DB needs to hold - */ - int num_entries; - - /** - * Resource allocation count array. This array content - * originates from the tf_session_resources that is passed in - * on session open. - * Array size is num_elements. - */ - uint16_t *alloc_cnt; -}; - -/** - * Shadow identifier DB creation parameters - */ -struct tf_shadow_ident_create_db_parms { - /** - * [in] Receive or transmit direction. - */ - enum tf_dir dir; - /** - * [in] Configuration information for the shadow db - */ - struct tf_shadow_ident_cfg_parms *cfg; - /** - * [in] Number of elements in the parms structure - */ - uint16_t num_elements; - /** - * [out] Shadow identifier DB handle - */ - void **tf_shadow_ident_db; -}; - -/** - * Shadow identifier DB free parameters - */ -struct tf_shadow_ident_free_db_parms { - /** - * Shadow identifier DB handle - */ - void *tf_shadow_ident_db; -}; - -/** - * Shadow identifier search parameters - */ -struct tf_shadow_ident_search_parms { - /** - * [in] Shadow identifier DB handle - */ - void *tf_shadow_ident_db; - /** - * [in] Identifier type - */ - enum tf_identifier_type type; - /** - * [in] id to search - */ - uint16_t search_id; - /** - * [out] Index of the found element returned if hit - */ - bool *hit; - /** - * [out] Reference count incremented if hit - */ - uint32_t *ref_cnt; -}; - -/** - * Shadow identifier insert parameters - */ -struct tf_shadow_ident_insert_parms { - /** - * [in] Shadow identifier DB handle - */ - void *tf_shadow_ident_db; - /** - * [in] Tbl type - */ - enum tf_identifier_type type; - /** - * [in] Entry to update - */ - uint16_t id; - /** - * [out] Reference count after insert - */ - uint32_t ref_cnt; -}; - -/** - * Shadow identifier remove parameters - */ -struct tf_shadow_ident_remove_parms { - /** - * [in] Shadow identifier DB handle - */ - void *tf_shadow_ident_db; - /** - * [in] Tbl type - */ - enum tf_identifier_type type; - /** - * [in] Entry to update - */ - uint16_t id; - /** - * [out] Reference count after removal - */ - uint32_t *ref_cnt; -}; - -/** - * @page shadow_ident Shadow identifier DB - * - * @ref tf_shadow_ident_create_db - * - * @ref tf_shadow_ident_free_db - * - * @reg tf_shadow_ident_search - * - * @reg tf_shadow_ident_insert - * - * @reg tf_shadow_ident_remove - */ - -/** - * Creates and fills a Shadow identifier DB. The DB is indexed per the - * parms structure. - * - * [in] parms - * Pointer to create db parameters - * - * Returns - * - (0) if successful. - * - (-EINVAL) on failure. - */ -int tf_shadow_ident_create_db(struct tf_shadow_ident_create_db_parms *parms); - -/** - * Closes the Shadow identifier DB and frees all allocated - * resources per the associated database. - * - * [in] parms - * Pointer to the free DB parameters - * - * Returns - * - (0) if successful. - * - (-EINVAL) on failure. - */ -int tf_shadow_ident_free_db(struct tf_shadow_ident_free_db_parms *parms); - -/** - * Search Shadow identifier db for matching result - * - * [in] parms - * Pointer to the search parameters - * - * Returns - * - (0) if successful, element was found. - * - (-EINVAL) on failure. - */ -int tf_shadow_ident_search(struct tf_shadow_ident_search_parms *parms); - -/** - * Inserts an element into the Shadow identifier DB. Ref_count after insert - * will be incremented. - * - * [in] parms - * Pointer to insert parameters - * - * Returns - * - (0) if successful. - * - (-EINVAL) on failure. - */ -int tf_shadow_ident_insert(struct tf_shadow_ident_insert_parms *parms); - -/** - * Removes an element from the Shadow identifier DB. Will fail if the - * elements ref_count is 0. Ref_count after removal will be - * decremented. - * - * [in] parms - * Pointer to remove parameter - * - * Returns - * - (0) if successful. - * - (-EINVAL) on failure. - */ -int tf_shadow_ident_remove(struct tf_shadow_ident_remove_parms *parms); - -#endif /* _TF_SHADOW_IDENTIFIER_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_shadow_tcam.c b/drivers/net/bnxt/tf_core/tf_shadow_tcam.c deleted file mode 100644 index 5fcd1f9107..0000000000 --- a/drivers/net/bnxt/tf_core/tf_shadow_tcam.c +++ /dev/null @@ -1,837 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom - * All rights reserved. - */ - -#include "tf_common.h" -#include "tf_util.h" -#include "tfp.h" -#include "tf_tcam.h" -#include "tf_shadow_tcam.h" -#include "tf_hash.h" - -/** - * The implementation includes 3 tables per tcam table type. - * - hash table - * - sized so that a minimum of 4 slots per shadow entry are available to - * minimize the likelihood of collisions. - * - shadow key table - * - sized to the number of entries requested and is directly indexed - * - the index is zero based and is the tcam index - the base address - * - the key and mask are stored in the key table. - * - The stored key is the AND of the key/mask in order to eliminate the need - * to compare both the key and mask. - * - shadow result table - * - the result table is stored separately since it only needs to be accessed - * when the key matches. - * - the result has a back pointer to the hash table via the hb handle. The - * hb handle is a 32 bit representation of the hash with a valid bit, bucket - * element index, and the hash index. It is necessary to store the hb handle - * with the result since subsequent removes only provide the tcam index. - * - * - Max entries is limited in the current implementation since bit 15 is the - * valid bit in the hash table. - * - A 16bit hash is calculated and masked based on the number of entries - * - 64b wide bucket is used and broken into 4x16bit elements. - * This decision is based on quicker bucket scanning to determine if any - * elements are in use. - * - bit 15 of each bucket element is the valid, this is done to prevent having - * to read the larger key/result data for determining VALID. It also aids - * in the more efficient scanning of the bucket for slot usage. - */ - -/* - * The maximum number of shadow entries supported. The value also doubles as - * the maximum number of hash buckets. There are only 15 bits of data per - * bucket to point to the shadow tables. - */ -#define TF_SHADOW_TCAM_ENTRIES_MAX (1 << 15) - -/* The number of elements(BE) per hash bucket (HB) */ -#define TF_SHADOW_TCAM_HB_NUM_ELEM (4) -#define TF_SHADOW_TCAM_BE_VALID (1 << 15) -#define TF_SHADOW_TCAM_BE_IS_VALID(be) (((be) & TF_SHADOW_TCAM_BE_VALID) != 0) - -/** - * The hash bucket handle is 32b - * - bit 31, the Valid bit - * - bit 29-30, the element - * - bits 0-15, the hash idx (is masked based on the allocated size) - */ -#define TF_SHADOW_TCAM_HB_HANDLE_IS_VALID(hndl) (((hndl) & (1 << 31)) != 0) -#define TF_SHADOW_TCAM_HB_HANDLE_CREATE(idx, be) ((1 << 31) | \ - ((be) << 29) | (idx)) - -#define TF_SHADOW_TCAM_HB_HANDLE_BE_GET(hdl) (((hdl) >> 29) & \ - (TF_SHADOW_TCAM_HB_NUM_ELEM - 1)) - -#define TF_SHADOW_TCAM_HB_HANDLE_HASH_GET(ctxt, hdl)((hdl) & \ - (ctxt)->hash_ctxt.hid_mask) - -/** - * The idx provided by the caller is within a region, so currently the base is - * either added or subtracted from the idx to ensure it can be used as a - * compressed index - */ - -/* Convert the tcam index to a shadow index */ -#define TF_SHADOW_TCAM_IDX_TO_SHIDX(ctxt, idx) ((idx) - \ - (ctxt)->shadow_ctxt.base_addr) - -/* Convert the shadow index to a tcam index */ -#define TF_SHADOW_TCAM_SHIDX_TO_IDX(ctxt, idx) ((idx) + \ - (ctxt)->shadow_ctxt.base_addr) - -/* Simple helper masks for clearing en element from the bucket */ -#define TF_SHADOW_TCAM_BE0_MASK_CLEAR(hb) ((hb) & 0xffffffffffff0000ull) -#define TF_SHADOW_TCAM_BE1_MASK_CLEAR(hb) ((hb) & 0xffffffff0000ffffull) -#define TF_SHADOW_TCAM_BE2_MASK_CLEAR(hb) ((hb) & 0xffff0000ffffffffull) -#define TF_SHADOW_TCAM_BE3_MASK_CLEAR(hb) ((hb) & 0x0000ffffffffffffull) - -/** - * This should be coming from external, but for now it is assumed that no key - * is greater than 1K bits and no result is bigger than 128 bits. This makes - * allocation of the hash table easier without having to allocate on the fly. - */ -#define TF_SHADOW_TCAM_MAX_KEY_SZ 128 -#define TF_SHADOW_TCAM_MAX_RESULT_SZ 16 - -/* - * Local only defines for the internal data. - */ - -/** - * tf_shadow_tcam_shadow_key_entry is the key/mask entry of the key table. - * The key stored in the table is the masked version of the key. This is done - * to eliminate the need of comparing both the key and mask. - */ -struct tf_shadow_tcam_shadow_key_entry { - uint8_t key[TF_SHADOW_TCAM_MAX_KEY_SZ]; - uint8_t mask[TF_SHADOW_TCAM_MAX_KEY_SZ]; -}; - -/** - * tf_shadow_tcam_shadow_result_entry is the result table entry. - * The result table writes are broken into two phases: - * - The search phase, which stores the hb_handle and key size and - * - The set phase, which writes the result, refcnt, and result size - */ -struct tf_shadow_tcam_shadow_result_entry { - uint8_t result[TF_SHADOW_TCAM_MAX_RESULT_SZ]; - uint16_t result_size; - uint16_t key_size; - uint32_t refcnt; - uint32_t hb_handle; -}; - -/** - * tf_shadow_tcam_shadow_ctxt holds all information for accessing the key and - * result tables. - */ -struct tf_shadow_tcam_shadow_ctxt { - struct tf_shadow_tcam_shadow_key_entry *sh_key_tbl; - struct tf_shadow_tcam_shadow_result_entry *sh_res_tbl; - uint32_t base_addr; - uint16_t num_entries; - uint16_t alloc_idx; -}; - -/** - * tf_shadow_tcam_hash_ctxt holds all information related to accessing the hash - * table. - */ -struct tf_shadow_tcam_hash_ctxt { - uint64_t *hashtbl; - uint16_t hid_mask; - uint16_t hash_entries; -}; - -/** - * tf_shadow_tcam_ctxt holds the hash and shadow tables for the current shadow - * tcam db. This structure is per tcam table type as each tcam table has it's - * own shadow and hash table. - */ -struct tf_shadow_tcam_ctxt { - struct tf_shadow_tcam_shadow_ctxt shadow_ctxt; - struct tf_shadow_tcam_hash_ctxt hash_ctxt; -}; - -/** - * tf_shadow_tcam_db is the allocated db structure returned as an opaque - * void * pointer to the caller during create db. It holds the pointers for - * each tcam associated with the db. - */ -struct tf_shadow_tcam_db { - /* Each context holds the shadow and hash table information */ - struct tf_shadow_tcam_ctxt *ctxt[TF_TCAM_TBL_TYPE_MAX]; -}; - -/** - * Returns the number of entries in the contexts shadow table. - */ -static inline uint16_t -tf_shadow_tcam_sh_num_entries_get(struct tf_shadow_tcam_ctxt *ctxt) -{ - return ctxt->shadow_ctxt.num_entries; -} - -/** - * Compare the give key with the key in the shadow table. - * - * Returns 0 if the keys match - */ -static int -tf_shadow_tcam_key_cmp(struct tf_shadow_tcam_ctxt *ctxt, - uint8_t *key, - uint8_t *mask, - uint16_t sh_idx, - uint16_t size) -{ - if (size != ctxt->shadow_ctxt.sh_res_tbl[sh_idx].key_size || - sh_idx >= tf_shadow_tcam_sh_num_entries_get(ctxt) || !key || !mask) - return -1; - - return memcmp(key, ctxt->shadow_ctxt.sh_key_tbl[sh_idx].key, size); -} - -/** - * Copies the shadow result to the result. - * - * Returns 0 on failure - */ -static void * -tf_shadow_tcam_res_cpy(struct tf_shadow_tcam_ctxt *ctxt, - uint8_t *result, - uint16_t sh_idx, - uint16_t size) -{ - if (sh_idx >= tf_shadow_tcam_sh_num_entries_get(ctxt) || !result) - return 0; - - if (ctxt->shadow_ctxt.sh_res_tbl[sh_idx].result_size != size) - return 0; - - return memcpy(result, - ctxt->shadow_ctxt.sh_res_tbl[sh_idx].result, - size); -} - -/** - * Using a software based CRC function for now, but will look into using hw - * assisted in the future. - */ -static uint32_t -tf_shadow_tcam_crc32_calc(uint8_t *key, uint32_t len) -{ - return tf_hash_calc_crc32(key, len); -} - -/** - * Free the memory associated with the context. - */ -static void -tf_shadow_tcam_ctxt_delete(struct tf_shadow_tcam_ctxt *ctxt) -{ - if (!ctxt) - return; - - tfp_free(ctxt->hash_ctxt.hashtbl); - tfp_free(ctxt->shadow_ctxt.sh_key_tbl); - tfp_free(ctxt->shadow_ctxt.sh_res_tbl); -} - -/** - * The TF Shadow TCAM context is per TCAM and holds all information relating to - * managing the shadow and search capability. This routine allocated data that - * needs to be deallocated by the tf_shadow_tcam_ctxt_delete prior when deleting - * the shadow db. - */ -static int -tf_shadow_tcam_ctxt_create(struct tf_shadow_tcam_ctxt *ctxt, - uint16_t num_entries, - uint16_t base_addr) -{ - struct tfp_calloc_parms cparms; - uint16_t hash_size = 1; - uint16_t hash_mask; - int rc; - - /* Hash table is a power of two that holds the number of entries */ - if (num_entries > TF_SHADOW_TCAM_ENTRIES_MAX) { - TFP_DRV_LOG(ERR, "Too many entries for shadow %d > %d\n", - num_entries, - TF_SHADOW_TCAM_ENTRIES_MAX); - return -ENOMEM; - } - - while (hash_size < num_entries) - hash_size = hash_size << 1; - - hash_mask = hash_size - 1; - - /* Allocate the hash table */ - cparms.nitems = hash_size; - cparms.size = sizeof(uint64_t); - cparms.alignment = 0; - rc = tfp_calloc(&cparms); - if (rc) - goto error; - ctxt->hash_ctxt.hashtbl = cparms.mem_va; - ctxt->hash_ctxt.hid_mask = hash_mask; - ctxt->hash_ctxt.hash_entries = hash_size; - - /* allocate the shadow tables */ - /* allocate the shadow key table */ - cparms.nitems = num_entries; - cparms.size = sizeof(struct tf_shadow_tcam_shadow_key_entry); - cparms.alignment = 0; - rc = tfp_calloc(&cparms); - if (rc) - goto error; - ctxt->shadow_ctxt.sh_key_tbl = cparms.mem_va; - - /* allocate the shadow result table */ - cparms.nitems = num_entries; - cparms.size = sizeof(struct tf_shadow_tcam_shadow_result_entry); - cparms.alignment = 0; - rc = tfp_calloc(&cparms); - if (rc) - goto error; - ctxt->shadow_ctxt.sh_res_tbl = cparms.mem_va; - - ctxt->shadow_ctxt.num_entries = num_entries; - ctxt->shadow_ctxt.base_addr = base_addr; - - return 0; -error: - tf_shadow_tcam_ctxt_delete(ctxt); - - return -ENOMEM; -} - -/** - * Get a shadow TCAM context given the db and the TCAM type - */ -static struct tf_shadow_tcam_ctxt * -tf_shadow_tcam_ctxt_get(struct tf_shadow_tcam_db *shadow_db, - enum tf_tcam_tbl_type type) -{ - if (type >= TF_TCAM_TBL_TYPE_MAX || - !shadow_db || - !shadow_db->ctxt[type]) - return NULL; - - return shadow_db->ctxt[type]; -} - -/** - * Sets the hash entry into the table given the TCAM context, hash bucket - * handle, and shadow index. - */ -static inline int -tf_shadow_tcam_set_hash_entry(struct tf_shadow_tcam_ctxt *ctxt, - uint32_t hb_handle, - uint16_t sh_idx) -{ - uint16_t hid = TF_SHADOW_TCAM_HB_HANDLE_HASH_GET(ctxt, hb_handle); - uint16_t be = TF_SHADOW_TCAM_HB_HANDLE_BE_GET(hb_handle); - uint64_t entry = sh_idx | TF_SHADOW_TCAM_BE_VALID; - - if (hid >= ctxt->hash_ctxt.hash_entries) - return -EINVAL; - - ctxt->hash_ctxt.hashtbl[hid] |= entry << (be * 16); - return 0; -} - -/** - * Clears the hash entry given the TCAM context and hash bucket handle. - */ -static inline void -tf_shadow_tcam_clear_hash_entry(struct tf_shadow_tcam_ctxt *ctxt, - uint32_t hb_handle) -{ - uint16_t hid, be; - uint64_t *bucket; - - if (!TF_SHADOW_TCAM_HB_HANDLE_IS_VALID(hb_handle)) - return; - - hid = TF_SHADOW_TCAM_HB_HANDLE_HASH_GET(ctxt, hb_handle); - be = TF_SHADOW_TCAM_HB_HANDLE_BE_GET(hb_handle); - bucket = &ctxt->hash_ctxt.hashtbl[hid]; - - switch (be) { - case 0: - *bucket = TF_SHADOW_TCAM_BE0_MASK_CLEAR(*bucket); - break; - case 1: - *bucket = TF_SHADOW_TCAM_BE1_MASK_CLEAR(*bucket); - break; - case 2: - *bucket = TF_SHADOW_TCAM_BE2_MASK_CLEAR(*bucket); - break; - case 3: - *bucket = TF_SHADOW_TCAM_BE2_MASK_CLEAR(*bucket); - break; - default: - /* - * Since the BE_GET masks non-inclusive bits, this will not - * happen. - */ - break; - } -} - -/** - * Clears the shadow key and result entries given the TCAM context and - * shadow index. - */ -static void -tf_shadow_tcam_clear_sh_entry(struct tf_shadow_tcam_ctxt *ctxt, - uint16_t sh_idx) -{ - struct tf_shadow_tcam_shadow_key_entry *sk_entry; - struct tf_shadow_tcam_shadow_result_entry *sr_entry; - - if (sh_idx >= tf_shadow_tcam_sh_num_entries_get(ctxt)) - return; - - sk_entry = &ctxt->shadow_ctxt.sh_key_tbl[sh_idx]; - sr_entry = &ctxt->shadow_ctxt.sh_res_tbl[sh_idx]; - - /* - * memset key/result to zero for now, possibly leave the data alone - * in the future and rely on the valid bit in the hash table. - */ - memset(sk_entry, 0, sizeof(struct tf_shadow_tcam_shadow_key_entry)); - memset(sr_entry, 0, sizeof(struct tf_shadow_tcam_shadow_result_entry)); -} - -/** - * Binds the allocated tcam index with the hash and shadow tables. - * The entry will be incomplete until the set has happened with the result - * data. - */ -int -tf_shadow_tcam_bind_index(struct tf_shadow_tcam_bind_index_parms *parms) -{ - int rc; - int i; - uint16_t idx, klen; - struct tf_shadow_tcam_ctxt *ctxt; - struct tf_shadow_tcam_db *shadow_db; - struct tf_shadow_tcam_shadow_key_entry *sk_entry; - struct tf_shadow_tcam_shadow_result_entry *sr_entry; - uint8_t tkey[TF_SHADOW_TCAM_MAX_KEY_SZ]; - - if (!parms || !TF_SHADOW_TCAM_HB_HANDLE_IS_VALID(parms->hb_handle) || - !parms->key || !parms->mask) { - TFP_DRV_LOG(ERR, "Invalid parms\n"); - return -EINVAL; - } - - shadow_db = (struct tf_shadow_tcam_db *)parms->shadow_db; - ctxt = tf_shadow_tcam_ctxt_get(shadow_db, parms->type); - if (!ctxt) { - TFP_DRV_LOG(DEBUG, "%s no ctxt for table\n", - tf_tcam_tbl_2_str(parms->type)); - return -EINVAL; - } - - memset(tkey, 0, sizeof(tkey)); - idx = TF_SHADOW_TCAM_IDX_TO_SHIDX(ctxt, parms->idx); - klen = parms->key_size; - if (idx >= tf_shadow_tcam_sh_num_entries_get(ctxt) || - klen > TF_SHADOW_TCAM_MAX_KEY_SZ) { - TFP_DRV_LOG(ERR, "%s:%s Invalid len (%d) > %d || oob idx %d\n", - tf_dir_2_str(parms->dir), - tf_tcam_tbl_2_str(parms->type), - klen, - TF_SHADOW_TCAM_MAX_KEY_SZ, idx); - - return -EINVAL; - } - - rc = tf_shadow_tcam_set_hash_entry(ctxt, parms->hb_handle, idx); - if (rc) - return -EINVAL; - - sk_entry = &ctxt->shadow_ctxt.sh_key_tbl[idx]; - sr_entry = &ctxt->shadow_ctxt.sh_res_tbl[idx]; - - /* - * Write the masked key to the table for more efficient comparisons - * later. - */ - for (i = 0; i < klen; i++) - tkey[i] = parms->key[i] & parms->mask[i]; - - memcpy(sk_entry->key, tkey, klen); - memcpy(sk_entry->mask, parms->mask, klen); - - /* Write the result table */ - sr_entry->key_size = parms->key_size; - sr_entry->hb_handle = parms->hb_handle; - sr_entry->refcnt = 1; - - return 0; -} - -/** - * Deletes hash/shadow information if no more references. - * - * Returns 0 - The caller should delete the tcam entry in hardware. - * Returns non-zero - The number of references to the entry - */ -int -tf_shadow_tcam_remove(struct tf_shadow_tcam_remove_parms *parms) -{ - uint16_t idx; - uint32_t hb_handle; - struct tf_shadow_tcam_ctxt *ctxt; - struct tf_shadow_tcam_db *shadow_db; - struct tf_tcam_free_parms *fparms; - struct tf_shadow_tcam_shadow_result_entry *sr_entry; - - if (!parms || !parms->fparms) { - TFP_DRV_LOG(ERR, "Invalid parms\n"); - return -EINVAL; - } - - fparms = parms->fparms; - - /* - * Initialize the reference count to zero. It will only be changed if - * non-zero. - */ - fparms->ref_cnt = 0; - - shadow_db = (struct tf_shadow_tcam_db *)parms->shadow_db; - ctxt = tf_shadow_tcam_ctxt_get(shadow_db, fparms->type); - if (!ctxt) { - TFP_DRV_LOG(DEBUG, "%s no ctxt for table\n", - tf_tcam_tbl_2_str(fparms->type)); - return 0; - } - - idx = TF_SHADOW_TCAM_IDX_TO_SHIDX(ctxt, fparms->idx); - if (idx >= tf_shadow_tcam_sh_num_entries_get(ctxt)) { - TFP_DRV_LOG(DEBUG, "%s %d >= %d\n", - tf_tcam_tbl_2_str(fparms->type), - fparms->idx, - tf_shadow_tcam_sh_num_entries_get(ctxt)); - return 0; - } - - sr_entry = &ctxt->shadow_ctxt.sh_res_tbl[idx]; - if (sr_entry->refcnt <= 1) { - hb_handle = sr_entry->hb_handle; - tf_shadow_tcam_clear_hash_entry(ctxt, hb_handle); - tf_shadow_tcam_clear_sh_entry(ctxt, idx); - } else { - sr_entry->refcnt--; - fparms->ref_cnt = sr_entry->refcnt; - } - - return 0; -} - -int -tf_shadow_tcam_search(struct tf_shadow_tcam_search_parms *parms) -{ - uint16_t len; - uint8_t rcopy; - uint64_t bucket; - uint32_t i, hid32; - struct tf_shadow_tcam_ctxt *ctxt; - struct tf_shadow_tcam_db *shadow_db; - uint16_t hid16, hb_idx, hid_mask, shtbl_idx, shtbl_key, be_valid; - struct tf_tcam_alloc_search_parms *sparms; - uint8_t tkey[TF_SHADOW_TCAM_MAX_KEY_SZ]; - uint32_t be_avail = TF_SHADOW_TCAM_HB_NUM_ELEM; - - if (!parms || !parms->sparms) { - TFP_DRV_LOG(ERR, "tcam search with invalid parms\n"); - return -EINVAL; - } - - memset(tkey, 0, sizeof(tkey)); - sparms = parms->sparms; - - /* Initialize return values to invalid */ - sparms->hit = 0; - sparms->search_status = REJECT; - parms->hb_handle = 0; - sparms->ref_cnt = 0; - /* see if caller wanted the result */ - rcopy = sparms->result && sparms->result_size; - - shadow_db = (struct tf_shadow_tcam_db *)parms->shadow_db; - ctxt = tf_shadow_tcam_ctxt_get(shadow_db, sparms->type); - if (!ctxt) { - TFP_DRV_LOG(ERR, "%s Unable to get tcam mgr context\n", - tf_tcam_tbl_2_str(sparms->type)); - return -EINVAL; - } - - hid_mask = ctxt->hash_ctxt.hid_mask; - - len = sparms->key_size; - - if (len > TF_SHADOW_TCAM_MAX_KEY_SZ || - !sparms->key || !sparms->mask || !len) { - TFP_DRV_LOG(ERR, "%s:%s Invalid parms %d : %p : %p\n", - tf_dir_2_str(sparms->dir), - tf_tcam_tbl_2_str(sparms->type), - len, - sparms->key, - sparms->mask); - return -EINVAL; - } - - /* Combine the key and mask */ - for (i = 0; i < len; i++) - tkey[i] = sparms->key[i] & sparms->mask[i]; - - /* - * Calculate the crc32 - * Fold it to create a 16b value - * Reduce it to fit the table - */ - hid32 = tf_shadow_tcam_crc32_calc(tkey, len); - hid16 = (uint16_t)(((hid32 >> 16) & 0xffff) ^ (hid32 & 0xffff)); - hb_idx = hid16 & hid_mask; - - bucket = ctxt->hash_ctxt.hashtbl[hb_idx]; - - if (!bucket) { - /* empty bucket means a miss and available entry */ - sparms->search_status = MISS; - parms->hb_handle = TF_SHADOW_TCAM_HB_HANDLE_CREATE(hb_idx, 0); - sparms->idx = 0; - return 0; - } - - /* Set the avail to max so we can detect when there is an avail entry */ - be_avail = TF_SHADOW_TCAM_HB_NUM_ELEM; - for (i = 0; i < TF_SHADOW_TCAM_HB_NUM_ELEM; i++) { - shtbl_idx = (uint16_t)((bucket >> (i * 16)) & 0xffff); - be_valid = TF_SHADOW_TCAM_BE_IS_VALID(shtbl_idx); - if (!be_valid) { - /* The element is avail, keep going */ - be_avail = i; - continue; - } - /* There is a valid entry, compare it */ - shtbl_key = shtbl_idx & ~TF_SHADOW_TCAM_BE_VALID; - if (!tf_shadow_tcam_key_cmp(ctxt, - sparms->key, - sparms->mask, - shtbl_key, - sparms->key_size)) { - /* - * It matches, increment the ref count if the caller - * requested allocation and return the info - */ - if (sparms->alloc) - ctxt->shadow_ctxt.sh_res_tbl[shtbl_key].refcnt++; - - sparms->hit = 1; - sparms->search_status = HIT; - parms->hb_handle = - TF_SHADOW_TCAM_HB_HANDLE_CREATE(hb_idx, i); - sparms->idx = TF_SHADOW_TCAM_SHIDX_TO_IDX(ctxt, - shtbl_key); - sparms->ref_cnt = - ctxt->shadow_ctxt.sh_res_tbl[shtbl_key].refcnt; - - /* copy the result, if caller wanted it. */ - if (rcopy && - !tf_shadow_tcam_res_cpy(ctxt, - sparms->result, - shtbl_key, - sparms->result_size)) { - /* - * Should never get here, possible memory - * corruption or something unexpected. - */ - TFP_DRV_LOG(ERR, "Error copying result\n"); - return -EINVAL; - } - - return 0; - } - } - - /* No hits, return avail entry if exists */ - if (be_avail < TF_SHADOW_TCAM_HB_NUM_ELEM) { - parms->hb_handle = - TF_SHADOW_TCAM_HB_HANDLE_CREATE(hb_idx, be_avail); - sparms->search_status = MISS; - sparms->hit = 0; - sparms->idx = 0; - } else { - sparms->search_status = REJECT; - } - - return 0; -} - -int -tf_shadow_tcam_insert(struct tf_shadow_tcam_insert_parms *parms) -{ - uint16_t idx; - struct tf_shadow_tcam_ctxt *ctxt; - struct tf_tcam_set_parms *sparms; - struct tf_shadow_tcam_db *shadow_db; - struct tf_shadow_tcam_shadow_result_entry *sr_entry; - - if (!parms || !parms->sparms) { - TFP_DRV_LOG(ERR, "Null parms\n"); - return -EINVAL; - } - - sparms = parms->sparms; - if (!sparms->result || !sparms->result_size) { - TFP_DRV_LOG(ERR, "%s:%s No result to set.\n", - tf_dir_2_str(sparms->dir), - tf_tcam_tbl_2_str(sparms->type)); - return -EINVAL; - } - - shadow_db = (struct tf_shadow_tcam_db *)parms->shadow_db; - ctxt = tf_shadow_tcam_ctxt_get(shadow_db, sparms->type); - if (!ctxt) { - /* We aren't tracking this table, so return success */ - TFP_DRV_LOG(DEBUG, "%s Unable to get tcam mgr context\n", - tf_tcam_tbl_2_str(sparms->type)); - return 0; - } - - idx = TF_SHADOW_TCAM_IDX_TO_SHIDX(ctxt, sparms->idx); - if (idx >= tf_shadow_tcam_sh_num_entries_get(ctxt)) { - TFP_DRV_LOG(ERR, "%s:%s Invalid idx(0x%x)\n", - tf_dir_2_str(sparms->dir), - tf_tcam_tbl_2_str(sparms->type), - sparms->idx); - return -EINVAL; - } - - /* Write the result table, the key/hash has been written already */ - sr_entry = &ctxt->shadow_ctxt.sh_res_tbl[idx]; - - /* - * If the handle is not valid, the bind was never called. We aren't - * tracking this entry. - */ - if (!TF_SHADOW_TCAM_HB_HANDLE_IS_VALID(sr_entry->hb_handle)) - return 0; - - if (sparms->result_size > TF_SHADOW_TCAM_MAX_RESULT_SZ) { - TFP_DRV_LOG(ERR, "%s:%s Result length %d > %d\n", - tf_dir_2_str(sparms->dir), - tf_tcam_tbl_2_str(sparms->type), - sparms->result_size, - TF_SHADOW_TCAM_MAX_RESULT_SZ); - return -EINVAL; - } - - memcpy(sr_entry->result, sparms->result, sparms->result_size); - sr_entry->result_size = sparms->result_size; - - return 0; -} - -int -tf_shadow_tcam_free_db(struct tf_shadow_tcam_free_db_parms *parms) -{ - struct tf_shadow_tcam_db *shadow_db; - int i; - - TF_CHECK_PARMS1(parms); - - shadow_db = (struct tf_shadow_tcam_db *)parms->shadow_db; - if (!shadow_db) { - TFP_DRV_LOG(DEBUG, "Shadow db is NULL cannot be freed\n"); - return -EINVAL; - } - - for (i = 0; i < TF_TCAM_TBL_TYPE_MAX; i++) { - if (shadow_db->ctxt[i]) { - tf_shadow_tcam_ctxt_delete(shadow_db->ctxt[i]); - tfp_free(shadow_db->ctxt[i]); - } - } - - tfp_free(shadow_db); - - return 0; -} - -/** - * Allocate the TCAM resources for search and allocate - * - */ -int tf_shadow_tcam_create_db(struct tf_shadow_tcam_create_db_parms *parms) -{ - int rc; - int i; - uint16_t base; - struct tfp_calloc_parms cparms; - struct tf_shadow_tcam_db *shadow_db = NULL; - - TF_CHECK_PARMS1(parms); - - /* Build the shadow DB per the request */ - cparms.nitems = 1; - cparms.size = sizeof(struct tf_shadow_tcam_db); - cparms.alignment = 0; - rc = tfp_calloc(&cparms); - if (rc) - return rc; - shadow_db = (void *)cparms.mem_va; - - for (i = 0; i < TF_TCAM_TBL_TYPE_MAX; i++) { - /* If the element didn't request an allocation no need - * to create a pool nor verify if we got a reservation. - */ - if (!parms->cfg->alloc_cnt[i]) { - shadow_db->ctxt[i] = NULL; - continue; - } - - cparms.nitems = 1; - cparms.size = sizeof(struct tf_shadow_tcam_ctxt); - cparms.alignment = 0; - rc = tfp_calloc(&cparms); - if (rc) - goto error; - - shadow_db->ctxt[i] = cparms.mem_va; - base = parms->cfg->base_addr[i]; - rc = tf_shadow_tcam_ctxt_create(shadow_db->ctxt[i], - parms->cfg->alloc_cnt[i], - base); - if (rc) - goto error; - } - - *parms->shadow_db = (void *)shadow_db; - - TFP_DRV_LOG(INFO, - "TF SHADOW TCAM - initialized\n"); - - return 0; -error: - for (i = 0; i < TF_TCAM_TBL_TYPE_MAX; i++) { - if (shadow_db->ctxt[i]) { - tf_shadow_tcam_ctxt_delete(shadow_db->ctxt[i]); - tfp_free(shadow_db->ctxt[i]); - } - } - - tfp_free(shadow_db); - - return -ENOMEM; -} diff --git a/drivers/net/bnxt/tf_core/tf_shadow_tcam.h b/drivers/net/bnxt/tf_core/tf_shadow_tcam.h deleted file mode 100644 index d6506b219a..0000000000 --- a/drivers/net/bnxt/tf_core/tf_shadow_tcam.h +++ /dev/null @@ -1,195 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom - * All rights reserved. - */ - -#ifndef _TF_SHADOW_TCAM_H_ -#define _TF_SHADOW_TCAM_H_ - -#include "tf_core.h" - -/** - * Shadow DB configuration information - * - * The shadow configuration is for all tcam table types for a direction - */ -struct tf_shadow_tcam_cfg_parms { - /** - * [in] The number of elements in the alloc_cnt and base_addr - * For now, it should always be equal to TF_TCAM_TBL_TYPE_MAX - */ - int num_entries; - /** - * [in] Resource allocation count array - * This array content originates from the tf_session_resources - * that is passed in on session open - * Array size is TF_TCAM_TBL_TYPE_MAX - */ - uint16_t *alloc_cnt; - /** - * [in] The base index for each tcam table - */ - uint16_t base_addr[TF_TCAM_TBL_TYPE_MAX]; -}; - -/** - * Shadow TCAM DB creation parameters. The shadow db for this direction - * is returned - */ -struct tf_shadow_tcam_create_db_parms { - /** - * [in] Receive or transmit direction - */ - enum tf_dir dir; - /** - * [in] Configuration information for the shadow db - */ - struct tf_shadow_tcam_cfg_parms *cfg; - /** - * [out] Shadow tcam DB handle - */ - void **shadow_db; -}; - -/** - * Create the shadow db for a single direction - * - * The returned shadow db must be free using the free db API when no longer - * needed - */ -int -tf_shadow_tcam_create_db(struct tf_shadow_tcam_create_db_parms *parms); - -/** - * Shadow TCAM free parameters - */ -struct tf_shadow_tcam_free_db_parms { - /** - * [in] Shadow tcam DB handle - */ - void *shadow_db; -}; - -/** - * Free all resources associated with the shadow db - */ -int -tf_shadow_tcam_free_db(struct tf_shadow_tcam_free_db_parms *parms); - -/** - * Shadow TCAM bind index parameters - */ -struct tf_shadow_tcam_bind_index_parms { - /** - * [in] Shadow tcam DB handle - */ - void *shadow_db; - /** - * [in] receive or transmit direction - */ - enum tf_dir dir; - /** - * [in] TCAM table type - */ - enum tf_tcam_tbl_type type; - /** - * [in] index of the entry to program - */ - uint16_t idx; - /** - * [in] struct containing key - */ - uint8_t *key; - /** - * [in] struct containing mask fields - */ - uint8_t *mask; - /** - * [in] key size in bits (if search) - */ - uint16_t key_size; - /** - * [in] The hash bucket handled returned from the search - */ - uint32_t hb_handle; -}; - -/** - * Binds the allocated tcam index with the hash and shadow tables - */ -int -tf_shadow_tcam_bind_index(struct tf_shadow_tcam_bind_index_parms *parms); - -/** - * Shadow TCAM insert parameters - */ -struct tf_shadow_tcam_insert_parms { - /** - * [in] Shadow tcam DB handle - */ - void *shadow_db; - /** - * [in] The set parms from tf core - */ - struct tf_tcam_set_parms *sparms; -}; - -/** - * Set the entry into the tcam manager hash and shadow tables - * - * The search must have been used prior to setting the entry so that the - * hash has been calculated and duplicate entries will not be added - */ -int -tf_shadow_tcam_insert(struct tf_shadow_tcam_insert_parms *parms); - -/** - * Shadow TCAM remove parameters - */ -struct tf_shadow_tcam_remove_parms { - /** - * [in] Shadow tcam DB handle - */ - void *shadow_db; - /** - * [in,out] The set parms from tf core - */ - struct tf_tcam_free_parms *fparms; -}; - -/** - * Remove the entry from the tcam hash and shadow tables - * - * The search must have been used prior to setting the entry so that the - * hash has been calculated and duplicate entries will not be added - */ -int -tf_shadow_tcam_remove(struct tf_shadow_tcam_remove_parms *parms); - -/** - * Shadow TCAM search parameters - */ -struct tf_shadow_tcam_search_parms { - /** - * [in] Shadow tcam DB handle - */ - void *shadow_db; - /** - * [in,out] The search parameters from tf core - */ - struct tf_tcam_alloc_search_parms *sparms; - /** - * [out] The hash handle to use for the set - */ - uint32_t hb_handle; -}; - -/** - * Search for an entry in the tcam hash/shadow tables - * - * If there is a miss, but there is room for insertion, the hb_handle returned - * is used for insertion during the bind index API - */ -int -tf_shadow_tcam_search(struct tf_shadow_tcam_search_parms *parms); -#endif diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c index 273f20858b..1c42a6adc7 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam.c +++ b/drivers/net/bnxt/tf_core/tf_tcam.c @@ -14,20 +14,9 @@ #include "tfp.h" #include "tf_session.h" #include "tf_msg.h" -#include "tf_shadow_tcam.h" struct tf; -/** - * TCAM Shadow DBs - */ -static void *shadow_tcam_db[TF_DIR_MAX]; - -/** - * Shadow init flag, set on bind and cleared on unbind - */ -static uint8_t shadow_init; - int tf_tcam_bind(struct tf *tfp, struct tf_tcam_cfg_parms *parms) @@ -40,9 +29,6 @@ tf_tcam_bind(struct tf *tfp, struct tf_rm_create_db_parms db_cfg; struct tf_tcam_resources *tcam_cnt; struct tf_rm_get_alloc_info_parms ainfo; - struct tf_shadow_tcam_free_db_parms fshadow; - struct tf_shadow_tcam_cfg_parms shadow_cfg; - struct tf_shadow_tcam_create_db_parms shadow_cdb; uint16_t num_slices = parms->wc_num_slices; struct tf_session *tfs; struct tf_dev_info *dev; @@ -144,44 +130,6 @@ tf_tcam_bind(struct tf *tfp, } /* Initialize the TCAM manager. */ - if (parms->shadow_copy) { - for (d = 0; d < TF_DIR_MAX; d++) { - memset(&shadow_cfg, 0, sizeof(shadow_cfg)); - memset(&shadow_cdb, 0, sizeof(shadow_cdb)); - /* Get the base addresses of the tcams for tcam mgr */ - for (i = 0; i < TF_TCAM_TBL_TYPE_MAX; i++) { - memset(&info, 0, sizeof(info)); - - if (!parms->resources->tcam_cnt[d].cnt[i]) - continue; - ainfo.rm_db = tcam_db->tcam_db[d]; - ainfo.subtype = i; - ainfo.info = &info; - rc = tf_rm_get_info(&ainfo); - if (rc) - goto error; - - shadow_cfg.base_addr[i] = info.entry.start; - } - - /* Create the shadow db */ - shadow_cfg.alloc_cnt = - parms->resources->tcam_cnt[d].cnt; - shadow_cfg.num_entries = parms->num_elements; - - shadow_cdb.shadow_db = &shadow_tcam_db[d]; - shadow_cdb.cfg = &shadow_cfg; - rc = tf_shadow_tcam_create_db(&shadow_cdb); - if (rc) { - TFP_DRV_LOG(ERR, - "TCAM MGR DB creation failed " - "rc=%d\n", rc); - goto error; - } - } - shadow_init = 1; - } - TFP_DRV_LOG(INFO, "TCAM - initialized\n"); @@ -193,19 +141,10 @@ tf_tcam_bind(struct tf *tfp, fparms.rm_db = tcam_db->tcam_db[i]; /* Ignoring return here since we are in the error case */ (void)tf_rm_free_db(tfp, &fparms); - - if (parms->shadow_copy) { - fshadow.shadow_db = shadow_tcam_db[i]; - tf_shadow_tcam_free_db(&fshadow); - shadow_tcam_db[i] = NULL; - } - tcam_db->tcam_db[i] = NULL; tf_session_set_db(tfp, TF_MODULE_TYPE_TCAM, NULL); } - shadow_init = 0; - return rc; } @@ -217,7 +156,6 @@ tf_tcam_unbind(struct tf *tfp) struct tf_rm_free_db_parms fparms; struct tcam_rm_db *tcam_db; void *tcam_db_ptr = NULL; - struct tf_shadow_tcam_free_db_parms fshadow; TF_CHECK_PARMS1(tfp); rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr); @@ -237,18 +175,8 @@ tf_tcam_unbind(struct tf *tfp) return rc; tcam_db->tcam_db[i] = NULL; - - if (shadow_init) { - memset(&fshadow, 0, sizeof(fshadow)); - - fshadow.shadow_db = shadow_tcam_db[i]; - tf_shadow_tcam_free_db(&fshadow); - shadow_tcam_db[i] = NULL; - } } - shadow_init = 0; - return 0; } @@ -346,7 +274,6 @@ tf_tcam_free(struct tf *tfp, struct tf_rm_get_hcapi_parms hparms; uint16_t num_slices = 1; int allocated = 0; - struct tf_shadow_tcam_remove_parms shparms; int i; struct tcam_rm_db *tcam_db; void *tcam_db_ptr = NULL; @@ -416,35 +343,6 @@ tf_tcam_free(struct tf *tfp, return -EINVAL; } - /* - * The Shadow mgmt, if enabled, determines if the entry needs - * to be deleted. - */ - if (shadow_init) { - shparms.shadow_db = shadow_tcam_db[parms->dir]; - shparms.fparms = parms; - rc = tf_shadow_tcam_remove(&shparms); - if (rc) { - /* - * Should not get here, log it and let the entry be - * deleted. - */ - TFP_DRV_LOG(ERR, "%s: Shadow free fail, " - "type:%d index:%d deleting the entry.\n", - tf_dir_2_str(parms->dir), - parms->type, - parms->idx); - } else { - /* - * If the entry still has references, just return the - * ref count to the caller. No need to remove entry - * from rm or hw - */ - if (parms->ref_cnt >= 1) - return rc; - } - } - for (i = 0; i < num_slices; i++) { /* Free requested element */ memset(&fparms, 0, sizeof(fparms)); @@ -488,128 +386,6 @@ tf_tcam_free(struct tf *tfp, return 0; } -int -tf_tcam_alloc_search(struct tf *tfp, - struct tf_tcam_alloc_search_parms *parms) -{ - struct tf_shadow_tcam_search_parms sparms; - struct tf_shadow_tcam_bind_index_parms bparms; - struct tf_tcam_free_parms fparms; - struct tf_tcam_alloc_parms aparms; - uint16_t num_slice_per_row = 1; - struct tf_session *tfs; - struct tf_dev_info *dev; - int rc; - - TF_CHECK_PARMS2(tfp, parms); - - if (!shadow_init || !shadow_tcam_db[parms->dir]) { - TFP_DRV_LOG(ERR, "%s: TCAM Shadow not initialized for %s\n", - tf_dir_2_str(parms->dir), - tf_tcam_tbl_2_str(parms->type)); - return -EINVAL; - } - - /* Retrieve the session information */ - rc = tf_session_get_session_internal(tfp, &tfs); - if (rc) - return rc; - - /* Retrieve the device information */ - rc = tf_session_get_device(tfs, &dev); - if (rc) - return rc; - - if (dev->ops->tf_dev_get_tcam_slice_info == NULL) { - rc = -EOPNOTSUPP; - TFP_DRV_LOG(ERR, - "%s: Operation not supported, rc:%s\n", - tf_dir_2_str(parms->dir), - strerror(-rc)); - return rc; - } - - /* Need to retrieve row size etc */ - rc = dev->ops->tf_dev_get_tcam_slice_info(tfp, - parms->type, - parms->key_size, - &num_slice_per_row); - if (rc) - return rc; - - /* - * Prep the shadow search, reusing the parms from original search - * instead of copying them. Shadow will update output in there. - */ - memset(&sparms, 0, sizeof(sparms)); - sparms.sparms = parms; - sparms.shadow_db = shadow_tcam_db[parms->dir]; - - rc = tf_shadow_tcam_search(&sparms); - if (rc) - return rc; - - /* - * The app didn't request us to alloc the entry, so return now. - * The hit should have been updated in the original search parm. - */ - if (!parms->alloc || parms->search_status != MISS) - return rc; - - /* Caller desires an allocate on miss */ - if (dev->ops->tf_dev_alloc_tcam == NULL) { - rc = -EOPNOTSUPP; - TFP_DRV_LOG(ERR, - "%s: Operation not supported, rc:%s\n", - tf_dir_2_str(parms->dir), - strerror(-rc)); - return rc; - } - memset(&aparms, 0, sizeof(aparms)); - aparms.dir = parms->dir; - aparms.type = parms->type; - aparms.key_size = parms->key_size; - aparms.priority = parms->priority; - rc = dev->ops->tf_dev_alloc_tcam(tfp, &aparms); - if (rc) - return rc; - - /* Successful allocation, attempt to add it to the shadow */ - memset(&bparms, 0, sizeof(bparms)); - bparms.dir = parms->dir; - bparms.shadow_db = shadow_tcam_db[parms->dir]; - bparms.type = parms->type; - bparms.key = parms->key; - bparms.mask = parms->mask; - bparms.key_size = parms->key_size; - bparms.idx = aparms.idx; - bparms.hb_handle = sparms.hb_handle; - rc = tf_shadow_tcam_bind_index(&bparms); - if (rc) { - /* Error binding entry, need to free the allocated idx */ - if (dev->ops->tf_dev_free_tcam == NULL) { - rc = -EOPNOTSUPP; - TFP_DRV_LOG(ERR, - "%s: Operation not supported, rc:%s\n", - tf_dir_2_str(parms->dir), - strerror(-rc)); - return rc; - } - - fparms.dir = parms->dir; - fparms.type = parms->type; - fparms.idx = aparms.idx; - rc = dev->ops->tf_dev_free_tcam(tfp, &fparms); - if (rc) - return rc; - } - - /* Add the allocated index to output and done */ - parms->idx = aparms.idx; - - return 0; -} - int tf_tcam_set(struct tf *tfp __rte_unused, struct tf_tcam_set_parms *parms __rte_unused) @@ -619,7 +395,6 @@ tf_tcam_set(struct tf *tfp __rte_unused, struct tf_dev_info *dev; struct tf_rm_is_allocated_parms aparms; struct tf_rm_get_hcapi_parms hparms; - struct tf_shadow_tcam_insert_parms iparms; uint16_t num_slice_per_row = 1; int allocated = 0; struct tcam_rm_db *tcam_db; @@ -705,24 +480,6 @@ tf_tcam_set(struct tf *tfp __rte_unused, strerror(-rc)); return rc; } - - /* Successfully added to hw, now for shadow if enabled. */ - if (!shadow_init || !shadow_tcam_db[parms->dir]) - return 0; - - iparms.shadow_db = shadow_tcam_db[parms->dir]; - iparms.sparms = parms; - rc = tf_shadow_tcam_insert(&iparms); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: %s: Entry %d set failed, rc:%s", - tf_dir_2_str(parms->dir), - tf_tcam_tbl_2_str(parms->type), - parms->idx, - strerror(-rc)); - return rc; - } - return 0; } diff --git a/drivers/net/bnxt/tf_core/tf_tcam.h b/drivers/net/bnxt/tf_core/tf_tcam.h index b1e7a92b0b..0ed2250464 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam.h +++ b/drivers/net/bnxt/tf_core/tf_tcam.h @@ -27,14 +27,6 @@ struct tf_tcam_cfg_parms { * TCAM configuration array */ struct tf_rm_element_cfg *cfg; - /** - * Shadow table type configuration array - */ - struct tf_shadow_tcam_cfg *shadow_cfg; - /** - * Boolean controlling the request shadow copy. - */ - bool shadow_copy; /** * Session resource allocations */ @@ -91,11 +83,6 @@ struct tf_tcam_free_parms { * [in] Index to free */ uint16_t idx; - /** - * [out] Reference count after free, only valid if session has been - * created with shadow_copy. - */ - uint16_t ref_cnt; }; /** @@ -322,10 +309,8 @@ int tf_tcam_alloc(struct tf *tfp, struct tf_tcam_alloc_parms *parms); /** - * Free's the requested table type and returns it to the DB. If shadow - * DB is enabled its searched first and if found the element refcount - * is decremented. If refcount goes to 0 then its returned to the - * table type DB. + * Free's the requested table type and returns it to the DB. + * If refcount goes to 0 then its returned to the table type DB. * * [in] tfp * Pointer to TF handle, used for HCAPI communication @@ -340,25 +325,6 @@ int tf_tcam_alloc(struct tf *tfp, int tf_tcam_free(struct tf *tfp, struct tf_tcam_free_parms *parms); -/** - * Supported if Shadow DB is configured. Searches the Shadow DB for - * any matching element. If found the refcount in the shadow DB is - * updated accordingly. If not found a new element is allocated and - * installed into the shadow DB. - * - * [in] tfp - * Pointer to TF handle, used for HCAPI communication - * - * [in] parms - * Pointer to parameters - * - * Returns - * - (0) if successful. - * - (-EINVAL) on failure. - */ -int tf_tcam_alloc_search(struct tf *tfp, - struct tf_tcam_alloc_search_parms *parms); - /** * Configures the requested element by sending a firmware request which * then installs it into the device internal structures. diff --git a/drivers/net/bnxt/tf_core/tf_util.c b/drivers/net/bnxt/tf_core/tf_util.c index c1b9be0755..7d9de7c764 100644 --- a/drivers/net/bnxt/tf_core/tf_util.c +++ b/drivers/net/bnxt/tf_core/tf_util.c @@ -59,12 +59,10 @@ tf_tcam_tbl_2_str(enum tf_tcam_tbl_type tcam_type) return "sp_tcam"; case TF_TCAM_TBL_TYPE_CT_RULE_TCAM: return "ct_rule_tcam"; -#ifdef TF_TCAM_SHARED case TF_TCAM_TBL_TYPE_WC_TCAM_HIGH: return "wc_tcam_hi"; case TF_TCAM_TBL_TYPE_WC_TCAM_LOW: return "wc_tcam_lo"; -#endif default: return "Invalid tcam table type"; } diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 1ee21fceef..1bb38399e4 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -461,7 +461,6 @@ ulp_ctx_shared_session_open(struct bnxt *bp, return rc; } - parms.shadow_copy = true; parms.bp = bp; if (app_id == 0) parms.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW; @@ -550,8 +549,6 @@ ulp_ctx_session_open(struct bnxt *bp, return rc; } - params.shadow_copy = true; - rc = bnxt_ulp_cntxt_app_id_get(bp->ulp_ctx, &app_id); if (rc) { BNXT_TF_DBG(ERR, "Unable to get the app id from ulp.\n"); From patchwork Fri Apr 21 18:11:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Randy Schacher X-Patchwork-Id: 126406 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C94CF429A8; Fri, 21 Apr 2023 20:12:37 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4CC6842D1A; Fri, 21 Apr 2023 20:12:24 +0200 (CEST) Received: from mail-oa1-f100.google.com (mail-oa1-f100.google.com [209.85.160.100]) by mails.dpdk.org (Postfix) with ESMTP id 85AAD4114B for ; Fri, 21 Apr 2023 20:12:20 +0200 (CEST) Received: by mail-oa1-f100.google.com with SMTP id 586e51a60fabf-187993bab0cso1789262fac.3 for ; Fri, 21 Apr 2023 11:12:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1682100740; x=1684692740; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uv4lBVvITMdFStcVVOmZw3P4EdIZXohI4hB+BEKRUis=; b=gEuuxRAzRlMV79TmVzOnYy68ELn9YpHZdpNX2igQJ4jWGLNahQMAsuB4gRQo6X2zMC xrabz1qwjk5eb7KEXTi22eDaYC3JKzeTi5IzDv8VZL05oPn4Zt34PSi5JGCxN2SgDlqN +8oiKuIdwDrv67tirPxpyrAu3iRAd5+9G+We4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682100740; x=1684692740; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uv4lBVvITMdFStcVVOmZw3P4EdIZXohI4hB+BEKRUis=; b=j2A/2nFHAWkMdv0I8Sa9Fv2rRz+Xatsl8WR20KPdNTakTiypen3qhvq3F+GgDCG6tW ZlPKvnarii1xYlr/R00i8H9HTOBrtS2GEGbPjU3yW1gwF0SrnGoNAAhxa93o/g5ZNpvk 8WzTRLL5TwPQZ2Azhi3ZV808eHYBZ+rDo10jL/YFSGJfO/cszNz4UuosFc0uqIplWVGa pPrkQAIui8U7tKOoblhWitjQr1d2eh00cecuTcCXGJscLCG8B8NFteYRKXK0Y/Gaqg3O 81CHcsix/+zy16lB/Qpbl3piZVG7xwBJiO91Ty9XLcFpkO8HkplkBSrTzk8n3VDkmTbT HIvw== X-Gm-Message-State: AAQBX9d4MrEdBuvUytPvqDI8rokmBAiNz8e9/PuBIqqW65L10sZ4xa2m FeIHMVKmL7xHB9oj/CcoyAr8pE5jgWl9YEmN0BqSK+bVrqbMu2pAUwY/o2R2M8XhwGSYA0mmZCk EtnvTMOk0o4ROvA04ZTFc0TDD9jQolf/WFMg9/ZQ9BtyvF/a9O7pFEnimQn5xfmDHqTqYO/M7AK viPE/SA+CTRdF9 X-Google-Smtp-Source: AKy350Z57lHjJItN/Xvtm0Gt75goOuFsW/DuqcTkXU4kyRXolQDpuahWQdiL+6TPV0evZxG45eH9lJMPM2PV X-Received: by 2002:a05:6870:f107:b0:17a:ccda:5c04 with SMTP id k7-20020a056870f10700b0017accda5c04mr4689883oac.14.1682100739326; Fri, 21 Apr 2023 11:12:19 -0700 (PDT) Received: from r650-k2.dhcp.broadcom.net ([192.19.144.250]) by smtp-relay.gmail.com with ESMTPS id o21-20020a056870e81500b0017eb57c3417sm397528oan.19.2023.04.21.11.12.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Apr 2023 11:12:19 -0700 (PDT) X-Relaying-Domain: broadcom.com From: Randy Schacher To: dev@dpdk.org Cc: Kishore Padmanabha Subject: [PATCH v2 02/11] net/bnxt: update bnxt hsi structure Date: Fri, 21 Apr 2023 18:11:46 +0000 Message-Id: <20230421181155.2160482-3-stuart.schacher@broadcom.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230421181155.2160482-1-stuart.schacher@broadcom.com> References: <20230421181155.2160482-1-stuart.schacher@broadcom.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sync hsi structure to latest revision Signed-off-by: Randy Schacher Reviewed-by: Kishore Padmanabha --- drivers/net/bnxt/hsi_struct_def_dpdk.h | 5723 +++++++++++++++++++++--- 1 file changed, 5128 insertions(+), 595 deletions(-) diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index 380dec4d3e..9afdd056ce 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright (c) 2014-2022 Broadcom Inc. + * Copyright (c) 2014-2023 Broadcom Inc. * All rights reserved. * * DO NOT MODIFY!!! This file is automatically generated. @@ -442,6 +442,8 @@ struct cmd_nums { #define HWRM_PORT_DSC_DUMP UINT32_C(0xd9) #define HWRM_PORT_EP_TX_QCFG UINT32_C(0xda) #define HWRM_PORT_EP_TX_CFG UINT32_C(0xdb) + #define HWRM_PORT_CFG UINT32_C(0xdc) + #define HWRM_PORT_QCFG UINT32_C(0xdd) #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0) #define HWRM_REG_POWER_QUERY UINT32_C(0xe1) #define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2) @@ -480,9 +482,7 @@ struct cmd_nums { #define HWRM_CFA_FLOW_FREE UINT32_C(0x104) /* Experimental */ #define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105) - /* Experimental */ #define HWRM_CFA_FLOW_STATS UINT32_C(0x106) - /* Experimental */ #define HWRM_CFA_FLOW_INFO UINT32_C(0x107) /* Experimental */ #define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108) @@ -678,6 +678,17 @@ struct cmd_nums { #define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT UINT32_C(0x1a7) /* The is the new API to query backing store capabilities. */ #define HWRM_FUNC_BACKING_STORE_QCAPS_V2 UINT32_C(0x1a8) + /* To query doorbell pacing NQ id list configuration. */ + #define HWRM_FUNC_DBR_PACING_NQLIST_QUERY UINT32_C(0x1a9) + /* + * To notify the firmware that recovery cycle has been + * completed by host function drivers. + */ + #define HWRM_FUNC_DBR_RECOVERY_COMPLETED UINT32_C(0x1aa) + /* Configures SyncE configurations. */ + #define HWRM_FUNC_SYNCE_CFG UINT32_C(0x1ab) + /* Queries SyncE configurations. */ + #define HWRM_FUNC_SYNCE_QCFG UINT32_C(0x1ac) /* Experimental */ #define HWRM_SELFTEST_QLIST UINT32_C(0x200) /* Experimental */ @@ -747,6 +758,8 @@ struct cmd_nums { * to run. */ #define HWRM_MFG_SELFTEST_EXEC UINT32_C(0x217) + /* Queries the generic stats */ + #define HWRM_STAT_GENERIC_QSTATS UINT32_C(0x218) /* Experimental */ #define HWRM_TF UINT32_C(0x2bc) /* Experimental */ @@ -774,6 +787,10 @@ struct cmd_nums { /* Experimental */ #define HWRM_TF_SESSION_RESC_INFO UINT32_C(0x2d0) /* Experimental */ + #define HWRM_TF_SESSION_HOTUP_STATE_SET UINT32_C(0x2d1) + /* Experimental */ + #define HWRM_TF_SESSION_HOTUP_STATE_GET UINT32_C(0x2d2) + /* Experimental */ #define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2da) /* Experimental */ #define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2db) @@ -819,6 +836,54 @@ struct cmd_nums { #define HWRM_TF_IF_TBL_SET UINT32_C(0x2fe) /* Experimental */ #define HWRM_TF_IF_TBL_GET UINT32_C(0x2ff) + /* TruFlow command to check firmware table scope capabilities. */ + #define HWRM_TFC_TBL_SCOPE_QCAPS UINT32_C(0x380) + /* TruFlow command to allocate a table scope ID and create the pools. */ + #define HWRM_TFC_TBL_SCOPE_ID_ALLOC UINT32_C(0x381) + /* TruFlow command to configure the table scope memory. */ + #define HWRM_TFC_TBL_SCOPE_CONFIG UINT32_C(0x382) + /* TruFlow command to deconfigure a table scope memory. */ + #define HWRM_TFC_TBL_SCOPE_DECONFIG UINT32_C(0x383) + /* TruFlow command to add a FID to a table scope. */ + #define HWRM_TFC_TBL_SCOPE_FID_ADD UINT32_C(0x384) + /* TruFlow command to remove a FID from a table scope. */ + #define HWRM_TFC_TBL_SCOPE_FID_REM UINT32_C(0x385) + /* TruFlow command to allocate a table scope pool. */ + #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC UINT32_C(0x386) + /* TruFlow command to free a table scope pool. */ + #define HWRM_TFC_TBL_SCOPE_POOL_FREE UINT32_C(0x387) + /* Experimental */ + #define HWRM_TFC_SESSION_ID_ALLOC UINT32_C(0x388) + /* Experimental */ + #define HWRM_TFC_SESSION_FID_ADD UINT32_C(0x389) + /* Experimental */ + #define HWRM_TFC_SESSION_FID_REM UINT32_C(0x38a) + /* Experimental */ + #define HWRM_TFC_IDENT_ALLOC UINT32_C(0x38b) + /* Experimental */ + #define HWRM_TFC_IDENT_FREE UINT32_C(0x38c) + /* TruFlow command to allocate an index table entry */ + #define HWRM_TFC_IDX_TBL_ALLOC UINT32_C(0x38d) + /* TruFlow command to allocate and set an index table entry */ + #define HWRM_TFC_IDX_TBL_ALLOC_SET UINT32_C(0x38e) + /* TruFlow command to set an index table entry */ + #define HWRM_TFC_IDX_TBL_SET UINT32_C(0x38f) + /* TruFlow command to get an index table entry */ + #define HWRM_TFC_IDX_TBL_GET UINT32_C(0x390) + /* TruFlow command to free an index table entry */ + #define HWRM_TFC_IDX_TBL_FREE UINT32_C(0x391) + /* TruFlow command to allocate resources for a global id. */ + #define HWRM_TFC_GLOBAL_ID_ALLOC UINT32_C(0x392) + /* TruFlow command to set TCAM entry. */ + #define HWRM_TFC_TCAM_SET UINT32_C(0x393) + /* TruFlow command to get TCAM entry. */ + #define HWRM_TFC_TCAM_GET UINT32_C(0x394) + /* TruFlow command to allocate a TCAM entry. */ + #define HWRM_TFC_TCAM_ALLOC UINT32_C(0x395) + /* TruFlow command allocate and set TCAM entry. */ + #define HWRM_TFC_TCAM_ALLOC_SET UINT32_C(0x396) + /* TruFlow command to free a TCAM entry. */ + #define HWRM_TFC_TCAM_FREE UINT32_C(0x397) /* Experimental */ #define HWRM_SV UINT32_C(0x400) /* Experimental */ @@ -1089,8 +1154,8 @@ struct hwrm_err_output { #define HWRM_VERSION_MINOR 10 #define HWRM_VERSION_UPDATE 2 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 83 -#define HWRM_VERSION_STR "1.10.2.83" +#define HWRM_VERSION_RSVD 138 +#define HWRM_VERSION_STR "1.10.2.138" /**************** * hwrm_ver_get * @@ -1345,6 +1410,7 @@ struct hwrm_ver_get_output { * If set to 1, firmware is capable to support flow aging. * If set to 0, firmware is not capable to support flow aging. * By default, this flag should be 0 for older version of core firmware. + * (deprecated) */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \ UINT32_C(0x200) @@ -1353,6 +1419,7 @@ struct hwrm_ver_get_output { * Meter drop counters and EEM counters. * If set to 0, firmware is not capable to support advanced flow counters. * By default, this flag should be 0 for older version of core firmware. + * (deprecated) */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \ UINT32_C(0x400) @@ -1362,6 +1429,7 @@ struct hwrm_ver_get_output { * If set to 0, firmware is not capable to support the use of the * CFA EEM feature. * By default, this flag should be 0 for older version of core firmware. + * (deprecated) */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \ UINT32_C(0x800) @@ -1996,7 +2064,7 @@ struct cfa_bds_event_collect_cmd_data_msg { uint64_t host_address; } __rte_packed; -/* ce_bds_add_data_msg (size:512b/64B) */ +/* ce_bds_add_data_msg (size:576b/72B) */ struct ce_bds_add_data_msg { uint32_t version_algorithm_kid_opcode; /* @@ -2050,26 +2118,14 @@ struct ce_bds_add_data_msg { (UINT32_C(0x1) << 28) #define CE_BDS_ADD_DATA_MSG__LAST \ CE_BDS_ADD_DATA_MSG__TLS1_3 - uint8_t cmd_type_ctx_kind; - /* - * Command Type in the TLS header. HW will provide registers that - * converts the 3b encoded command type to 8b of actual command - * type in the TLS Header. This field is initialized/updated by - * this "KTLS crypto add" mid-path command. - */ - #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_MASK UINT32_C(0x7) - #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_SFT 0 - /* Application */ - #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP UINT32_C(0x0) - #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_LAST \ - CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP + uint8_t ctx_kind; /* This field selects the context kind for the request. */ - #define CE_BDS_ADD_DATA_MSG_CTX_KIND_MASK UINT32_C(0xf8) - #define CE_BDS_ADD_DATA_MSG_CTX_KIND_SFT 3 + #define CE_BDS_ADD_DATA_MSG_CTX_KIND_MASK UINT32_C(0x1f) + #define CE_BDS_ADD_DATA_MSG_CTX_KIND_SFT 0 /* Crypto key transmit context */ - #define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_TX (UINT32_C(0x11) << 3) + #define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_TX UINT32_C(0x11) /* Crypto key receive context */ - #define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_RX (UINT32_C(0x12) << 3) + #define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_RX UINT32_C(0x12) #define CE_BDS_ADD_DATA_MSG_CTX_KIND_LAST \ CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_RX uint8_t unused0[3]; @@ -2083,8 +2139,8 @@ struct ce_bds_add_data_msg { * is zero padded to 12B and then xor'ed with the 4B of salt to generate * the 12B of IV. This value is initialized by this mid-path command. */ - uint32_t salt; - uint32_t unused1; + uint8_t salt[4]; + uint8_t unused1[4]; /* * This field keeps track of the TCP sequence number that is expected as * the first byte in the next TCP packet. This field is calculated by HW @@ -2111,16 +2167,21 @@ struct ce_bds_add_data_msg { * the field after that for every record processed as it parses the TCP * packet. */ - uint32_t record_seq_num[2]; + uint64_t record_seq_num; /* * Key used for encrypting or decrypting TLS records. The Key is * exchanged during the hand-shake protocol by the client-server and * provided to HW through this mid-path BD. */ - uint32_t session_key[8]; + uint8_t session_key[32]; + /* + * Additional IV that is exchanged as part of sessions setup between + * the two end points. This field is used for TLS1.3 only. + */ + uint8_t addl_iv[8]; } __rte_packed; -/* ce_bds_delete_data_msg (size:64b/8B) */ +/* ce_bds_delete_data_msg (size:32b/4B) */ struct ce_bds_delete_data_msg { uint32_t kid_opcode_ctx_kind; /* @@ -2160,7 +2221,6 @@ struct ce_bds_delete_data_msg { #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_RX (UINT32_C(0x15) << 24) #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_LAST \ CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_RX - uint32_t unused0; } __rte_packed; /* ce_bds_resync_resp_ack_msg (size:128b/16B) */ @@ -2213,7 +2273,7 @@ struct ce_bds_resync_resp_ack_msg { * it has found since sending the resync request, update the context and * resume decrypting records. */ - uint32_t resync_record_seq_num[2]; + uint64_t resync_record_seq_num; } __rte_packed; /* ce_bds_resync_resp_nack_msg (size:64b/8B) */ @@ -2288,6 +2348,19 @@ struct crypto_presync_bd_cmd { */ #define CRYPTO_PRESYNC_BD_CMD_FLAGS_UPDATE_IN_ORDER_VAR \ UINT32_C(0x1) + /* + * When packet with an authentication TAG is lost in the network, + * During retransmission Device driver will post the entire record for + * the hardware to recalculate the TAG. Hardware is set to retransmit + * only portions of the record, it does so by looking at the Header + * TCP Sequence Number and Start TCP Sequence Number. However, there + * is a case where the header packet gets dropped in the stack for ex + * BPF packet filter and it is impossible for the Hardware to + * determine if this is a case of full replay for only the TAG + * generation. + */ + #define CRYPTO_PRESYNC_BD_CMD_FLAGS_FULL_REPLAY_RETRAN \ + UINT32_C(0x2) uint8_t unused0; uint16_t unused1; /* @@ -2331,7 +2404,7 @@ struct crypto_presync_bd_cmd { * the first TLS header. When subsequent TLS Headers are detected, the * value is extracted from packet. */ - uint32_t explicit_nonce[2]; + uint8_t explicit_nonce[8]; /* * This is sequence number for the TLS record in a particular session. In * TLS1.2, record sequence number is part of the Associated Data (AD) in @@ -2343,7 +2416,110 @@ struct crypto_presync_bd_cmd { * delivering more retransmission instruction will also update this * field. */ - uint32_t record_seq_num[2]; + uint64_t record_seq_num; +} __rte_packed; + +/* ce_bds_quic_add_data_msg (size:832b/104B) */ +struct ce_bds_quic_add_data_msg { + uint32_t ver_algo_kid_opcode; + /* + * This value selects the operation for the mid-path command for the + * crypto blocks. + */ + #define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_MASK UINT32_C(0xf) + #define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_SFT 0 + /* + * This is the add command. Using this opcode, Host Driver can add + * information required for QUIC processing. The information is + * updated in the CFCK context. + */ + #define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_ADD UINT32_C(0x1) + #define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_LAST \ + CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_ADD + /* + * This field is the Crypto Context ID. The KID is used to store + * information used by the associated QUIC offloaded connection. + */ + #define CE_BDS_QUIC_ADD_DATA_MSG_KID_MASK \ + UINT32_C(0xfffff0) + #define CE_BDS_QUIC_ADD_DATA_MSG_KID_SFT 4 + /* Algorithm used for encryption and decryption. */ + #define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_MASK \ + UINT32_C(0xf000000) + #define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_SFT 24 + /* AES_GCM_128 Algorithm. */ + #define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_AES_GCM_128 \ + (UINT32_C(0x1) << 24) + /* AES_GCM_256 Algorithm. */ + #define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_AES_GCM_256 \ + (UINT32_C(0x2) << 24) + /* Chacha20 Algorithm. */ + #define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_CHACHA20 \ + (UINT32_C(0x3) << 24) + #define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_LAST \ + CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_CHACHA20 + /* Version number of QUIC connection. */ + #define CE_BDS_QUIC_ADD_DATA_MSG_VERSION_MASK \ + UINT32_C(0xf0000000) + #define CE_BDS_QUIC_ADD_DATA_MSG_VERSION_SFT 28 + /* TLS1.2 Version */ + #define CE_BDS_QUIC_ADD_DATA_MSG__TLS1_2 \ + (UINT32_C(0x0) << 28) + /* TLS1.3 Version */ + #define CE_BDS_QUIC_ADD_DATA_MSG__TLS1_3 \ + (UINT32_C(0x1) << 28) + /* DTLS1.2 Version */ + #define CE_BDS_QUIC_ADD_DATA_MSG__DTLS1_2 \ + (UINT32_C(0x2) << 28) + /* DTLS1.2 for RoCE Version */ + #define CE_BDS_QUIC_ADD_DATA_MSG__DTLS1_2_ROCE \ + (UINT32_C(0x3) << 28) + /* QUIC Version */ + #define CE_BDS_QUIC_ADD_DATA_MSG__QUIC \ + (UINT32_C(0x4) << 28) + #define CE_BDS_QUIC_ADD_DATA_MSG__LAST \ + CE_BDS_QUIC_ADD_DATA_MSG__QUIC + uint32_t ctx_kind_dcid_width_key_phase; + /* Key phase. */ + #define CE_BDS_QUIC_ADD_DATA_MSG_KEY_PHASE UINT32_C(0x1) + /* Destination connection ID width. */ + #define CE_BDS_QUIC_ADD_DATA_MSG_DCID_WIDTH_MASK UINT32_C(0x3e) + #define CE_BDS_QUIC_ADD_DATA_MSG_DCID_WIDTH_SFT 1 + /* This field selects the context kind for the request. */ + #define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_MASK UINT32_C(0x7c0) + #define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_SFT 6 + /* QUIC key transmit context */ + #define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_QUIC_TX \ + (UINT32_C(0x14) << 6) + /* QUIC key receive context */ + #define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_QUIC_RX \ + (UINT32_C(0x15) << 6) + #define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_LAST \ + CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_QUIC_RX + uint32_t unused_0[2]; + /* + * Least-significant 64 bits (of 96) of additional IV that is + * exchanged as part of sessions setup between the two end + * points for QUIC operations. + */ + uint64_t quic_iv_lo; + /* + * Most-significant 32 bits (of 96) of additional IV that is + * exchanged as part of sessions setup between the two end + * points for QUIC operations. + */ + uint32_t quic_iv_hi; + uint32_t unused_1; + /* + * Key used for encrypting or decrypting records. The Key is exchanged + * as part of sessions setup between the two end points through this + * mid-path BD. + */ + uint32_t session_key[8]; + /* Header protection key. */ + uint32_t hp_key[8]; + /* Packet number associated with the QUIC connection. */ + uint64_t pkt_number; } __rte_packed; /* bd_base (size:64b/8B) */ @@ -3665,7 +3841,7 @@ struct cfa_dma128b_data_msg { /* ce_cmpls_cmp_data_msg (size:128b/16B) */ struct ce_cmpls_cmp_data_msg { - uint16_t status_subtype_type; + uint16_t client_subtype_type; /* * This field indicates the exact type of the completion. By * convention, the LSB identifies the length of the record in 16B @@ -3678,82 +3854,82 @@ struct ce_cmpls_cmp_data_msg { #define CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT UINT32_C(0x1e) #define CE_CMPLS_CMP_DATA_MSG_TYPE_LAST \ CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT + #define CE_CMPLS_CMP_DATA_MSG_UNUSED0_MASK UINT32_C(0xc0) + #define CE_CMPLS_CMP_DATA_MSG_UNUSED0_SFT 6 /* * This value indicates the CE sub-type operation that is being * completed. */ - #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_MASK UINT32_C(0x3c0) - #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SFT 6 + #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_MASK UINT32_C(0xf00) + #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SFT 8 /* Completion Response for a Solicited Command. */ - #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SOLICITED (UINT32_C(0x0) << 6) + #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SOLICITED (UINT32_C(0x0) << 8) /* Error Completion (Unsolicited). */ - #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_ERR (UINT32_C(0x1) << 6) + #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_ERR (UINT32_C(0x1) << 8) /* Re-Sync Completion (Unsolicited) */ - #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC (UINT32_C(0x2) << 6) + #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC (UINT32_C(0x2) << 8) #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_LAST \ CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_MASK UINT32_C(0xf000) + #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_SFT 12 + /* TX crypto engine block. */ + #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_TCE \ + (UINT32_C(0x0) << 12) + /* RX crypto engine block. */ + #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_RCE \ + (UINT32_C(0x1) << 12) + #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_LAST \ + CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_RCE + uint16_t status; /* This value indicates the status for the command. */ - #define CE_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0x3c00) - #define CE_CMPLS_CMP_DATA_MSG_STATUS_SFT 10 + #define CE_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0xf) + #define CE_CMPLS_CMP_DATA_MSG_STATUS_SFT 0 /* Completed without error. */ - #define CE_CMPLS_CMP_DATA_MSG_STATUS_OK \ - (UINT32_C(0x0) << 10) + #define CE_CMPLS_CMP_DATA_MSG_STATUS_OK UINT32_C(0x0) /* CFCK load error. */ - #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_LD_ERR \ - (UINT32_C(0x1) << 10) + #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_LD_ERR UINT32_C(0x1) /* FID check error. */ - #define CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR \ - (UINT32_C(0x2) << 10) + #define CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR UINT32_C(0x2) /* Context kind / MP version mismatch error. */ - #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_VER_ERR \ - (UINT32_C(0x3) << 10) + #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_VER_ERR UINT32_C(0x3) /* Unsupported Destination Connection ID Length. */ - #define CE_CMPLS_CMP_DATA_MSG_STATUS_DST_ID_ERR \ - (UINT32_C(0x4) << 10) + #define CE_CMPLS_CMP_DATA_MSG_STATUS_DST_ID_ERR UINT32_C(0x4) /* * Invalid MP Command [anything other than ADD or DELETE * triggers this for QUIC]. */ - #define CE_CMPLS_CMP_DATA_MSG_STATUS_MP_CMD_ERR \ - (UINT32_C(0x5) << 10) + #define CE_CMPLS_CMP_DATA_MSG_STATUS_MP_CMD_ERR UINT32_C(0x5) #define CE_CMPLS_CMP_DATA_MSG_STATUS_LAST \ CE_CMPLS_CMP_DATA_MSG_STATUS_MP_CMD_ERR - uint8_t unused0; - uint8_t mp_clients; - #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xf) - #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 0 - /* - * This field represents the Mid-Path client that generated the - * completion. - */ - #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_MASK UINT32_C(0xf0) - #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_SFT 4 - /* TX crypto engine block. */ - #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_TCE (UINT32_C(0x0) << 4) - /* RX crypto engine block. */ - #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE (UINT32_C(0x1) << 4) - #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_LAST \ - CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE + #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xfff0) + #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 4 /* * This is a copy of the opaque field from the mid path BD of this * command. */ uint32_t opaque; - /* */ - uint32_t kid_v; + uint32_t v; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes will * write 1. The odd passes will write 0. */ - #define CE_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1) + #define CE_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1) + #define CE_CMPLS_CMP_DATA_MSG_UNUSED2_MASK UINT32_C(0xfffffffe) + #define CE_CMPLS_CMP_DATA_MSG_UNUSED2_SFT 1 + uint32_t kid; /* * This field is the Crypto Context ID. The KID is used to store * information used by the associated kTLS offloaded connection. */ - #define CE_CMPLS_CMP_DATA_MSG_KID_MASK UINT32_C(0x1ffffe) - #define CE_CMPLS_CMP_DATA_MSG_KID_SFT 1 - uint32_t unused2; + #define CE_CMPLS_CMP_DATA_MSG_KID_MASK UINT32_C(0xfffff) + #define CE_CMPLS_CMP_DATA_MSG_KID_SFT 0 + #define CE_CMPLS_CMP_DATA_MSG_UNUSED3_MASK UINT32_C(0xfff00000) + #define CE_CMPLS_CMP_DATA_MSG_UNUSED3_SFT 20 } __rte_packed; /* cmpl_base (size:128b/16B) */ @@ -3783,16 +3959,11 @@ struct cmpl_base { * Completion of coalesced TX packet. Length = 16B */ #define CMPL_BASE_TYPE_TX_L2_COAL UINT32_C(0x2) - /* - * TX L2 PTP completion: - * Completion of PTP TX packet. Length = 32B - */ - #define CMPL_BASE_TYPE_TX_L2_PTP UINT32_C(0x3) /* * TX L2 Packet Timestamp completion: * Completion of an L2 Packet Timestamp Packet. Length = 16B */ - #define CMPL_BASE_TYPE_TX_L2_PTP_TS UINT32_C(0x4) + #define CMPL_BASE_TYPE_TX_L2_PKT_TS UINT32_C(0x4) /* * RX L2 TPA Start V2 Completion: * Completion of and L2 RX packet. Length = 32B @@ -4173,47 +4344,79 @@ struct tx_cmpl_coal { #define TX_CMPL_COAL_SQ_CONS_IDX_SFT 0 } __rte_packed; -/* tx_cmpl_ptp (size:128b/16B) */ -struct tx_cmpl_ptp { - uint16_t flags_type; +/* tx_cmpl_packet_timestamp (size:128b/16B) */ +struct tx_cmpl_packet_timestamp { + uint16_t ts_sub_ns_flags_type; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This field indicates the exact type of the completion. By + * convention, the LSB identifies the length of the record in 16B + * units. Even values indicate 16B records. Odd values indicate + * 32B records. */ - #define TX_CMPL_PTP_TYPE_MASK UINT32_C(0x3f) - #define TX_CMPL_PTP_TYPE_SFT 0 + #define TX_CMPL_PACKET_TIMESTAMP_TYPE_MASK UINT32_C(0x3f) + #define TX_CMPL_PACKET_TIMESTAMP_TYPE_SFT 0 /* - * TX L2 PTP completion: - * Completion of TX packet. Length = 32B + * TX L2 Packet Timestamp completion: + * Completion of an L2 Packet Timestamp Packet. Length = 16B */ - #define TX_CMPL_PTP_TYPE_TX_L2_PTP UINT32_C(0x2) - #define TX_CMPL_PTP_TYPE_LAST TX_CMPL_PTP_TYPE_TX_L2_PTP - #define TX_CMPL_PTP_FLAGS_MASK UINT32_C(0xffc0) - #define TX_CMPL_PTP_FLAGS_SFT 6 + #define TX_CMPL_PACKET_TIMESTAMP_TYPE_TX_L2_PKT_TS UINT32_C(0x4) + #define TX_CMPL_PACKET_TIMESTAMP_TYPE_LAST \ + TX_CMPL_PACKET_TIMESTAMP_TYPE_TX_L2_PKT_TS + #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_MASK UINT32_C(0xfc0) + #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_SFT 6 /* - * When this bit is '1', it indicates a packet that has an - * error of some type. Type of error is indicated in - * error_flags. + * When this bit is '1', it indicates a packet that has an error + * of some type. Type of error is indicated in error_flags. */ - #define TX_CMPL_PTP_FLAGS_ERROR UINT32_C(0x40) + #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_ERROR UINT32_C(0x40) /* - * When this bit is '1', it indicates that the packet completed - * was transmitted using the push acceleration data provided - * by the driver. When this bit is '0', it indicates that the - * packet had not push acceleration data written or was executed - * as a normal packet even though push data was provided. + * This field indicates the TX packet timestamp type that is + * represented by a TX Packet Timestamp Completion. Note that + * this field is invalid if the timestamp_invalid_error flag + * is set. */ - #define TX_CMPL_PTP_FLAGS_PUSH UINT32_C(0x80) - /* unused1 is 16 b */ - uint16_t unused_0; + #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE UINT32_C(0x80) + /* The packet timestamp came from PM. */ + #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_TS_PM \ + (UINT32_C(0x0) << 7) + /* The packet timestamp came from PA. */ + #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_TS_PA \ + (UINT32_C(0x1) << 7) + #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_LAST \ + TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_TS_PA + /* + * This flag indicates that the timestamp should have come from PM, + * but came instead from PA because all PM timestamp resources were + * in use. This can occur in the following circumstances: + * 1. The BD specified ts_2cmpl_auto and the packet was a PTP packet + * but PA could not request a PM timestamp + * 2. The BD specified ts_2cmpl_pm, but PA could not request a PM + * timestamp + */ + #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_FALLBACK UINT32_C(0x100) + /* + * For 2-step PTP timestamps, bits[3:0] of this field represent the + * sub-nanosecond portion of the packet timestamp, returned from PM + * for 2-step PTP timestamps. For PA timestamps, this field also + * represents the sub-nanosecond portion of the packet timestamp; + * however, due to synchronization uncertainties, the accuracy of + * PA timestamps is limited to approximately +/- 4 ns. Therefore + * this field is of dubious value for PA timestamps. + */ + #define TX_CMPL_PACKET_TIMESTAMP_TS_SUB_NS_MASK UINT32_C(0xf000) + #define TX_CMPL_PACKET_TIMESTAMP_TS_SUB_NS_SFT 12 + /* + * This is bits [47:32] of the nanoseconds portion of the packet + * timestamp, returned from PM for 2-step PTP timestamps or from + * PA for PA timestamps. This field is in units of 2^32 ns. + */ + uint16_t ts_ns_mid; /* * This is a copy of the opaque field from the first TX BD of this - * transmitted packet. Note that, if the packet was described by a short - * CSO or short CSO inline BD, then the 16-bit opaque field from the - * short CSO BD will appear in the bottom 16 bits of this field. + * transmitted packet. Note that, if the packet was described by a + * short CSO or short CSO inline BD, then the 16-bit opaque field + * from the short CSO BD will appear in the bottom 16 bits of this + * field. */ uint32_t opaque; uint16_t errors_v; @@ -4222,95 +4425,103 @@ struct tx_cmpl_ptp { * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define TX_CMPL_PTP_V UINT32_C(0x1) - #define TX_CMPL_PTP_ERRORS_MASK UINT32_C(0xfffe) - #define TX_CMPL_PTP_ERRORS_SFT 1 + #define TX_CMPL_PACKET_TIMESTAMP_V \ + UINT32_C(0x1) + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_MASK \ + UINT32_C(0xfffe) + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_SFT 1 /* - * This error indicates that there was some sort of problem - * with the BDs for the packet. + * This field was previously used to indicate fatal errors, which + * now result in aborting and bringing down the ring. This field + * is deprecated. */ - #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) - #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_SFT 1 - /* No error */ - #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_NO_ERROR \ + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_MASK \ + UINT32_C(0xe) + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_SFT 1 + /* No error. */ + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_NO_ERROR \ (UINT32_C(0x0) << 1) - /* - * Bad Format: - * BDs were not formatted correctly. - */ - #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT \ + /* Deprecated. */ + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_BAD_FMT \ (UINT32_C(0x2) << 1) - #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_LAST \ - TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_LAST \ + TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_BAD_FMT /* - * When this bit is '1', it indicates that the length of - * the packet was zero. No packet was transmitted. + * This error is fatal and results in aborting and bringing down the + * ring, thus is deprecated. */ - #define TX_CMPL_PTP_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10) - /* - * When this bit is '1', it indicates that the packet - * was longer than the programmed limit in TDI. No - * packet was transmitted. - */ - #define TX_CMPL_PTP_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20) + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_ZERO_LENGTH_PKT \ + UINT32_C(0x10) /* - * When this bit is '1', it indicates that one or more of the - * BDs associated with this packet generated a PCI error. - * This probably means the address was not valid. + * This error is fatal and results in aborting and bringing down the + * ring, thus is deprecated. */ - #define TX_CMPL_PTP_ERRORS_DMA_ERROR UINT32_C(0x40) + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_EXCESSIVE_BD_LENGTH \ + UINT32_C(0x20) /* - * When this bit is '1', it indicates that the packet was longer - * than indicated by the hint. No packet was transmitted. + * When this bit is '1', it indicates that one or more of the BDs + * associated with this packet generated a PCI error when accessing + * header/payload data from host memory. It most likely indicates + * that the address was not valid. Note that this bit has no meaning + * for the timestamp completion and will always be '0'. */ - #define TX_CMPL_PTP_ERRORS_HINT_TOO_SHORT UINT32_C(0x80) + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_DMA_ERROR \ + UINT32_C(0x40) /* - * When this bit is '1', it indicates that the packet was - * dropped due to Poison TLP error on one or more of the - * TLPs in the PXP completion. + * This error is fatal and results in aborting and bringing down the + * ring, thus is deprecated. */ - #define TX_CMPL_PTP_ERRORS_POISON_TLP_ERROR UINT32_C(0x100) + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_HINT_TOO_SHORT \ + UINT32_C(0x80) /* - * When this bit is '1', it indicates that the packet was dropped due - * to a transient internal error in TDC. The packet or LSO can be - * retried and may transmit successfully on a subsequent attempt. + * When this bit is '1', it indicates that the packet was dropped + * due to Poison TLP error on one or more of the TLPs in one or more + * of the associated PXP completion(s) when accessing header/payload + * data from host memory. Note that this bit has no meaning for the + * timestamp completion, and will always be '0'. */ - #define TX_CMPL_PTP_ERRORS_INTERNAL_ERROR UINT32_C(0x200) + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_POISON_TLP_ERROR \ + UINT32_C(0x100) /* - * When this bit is '1', it was not possible to collect a a timestamp - * for a PTP completion, in which case the timestamp_hi and - * timestamp_lo fields are invalid. When this bit is '0' for a PTP - * completion, the timestamp_hi and timestamp_lo fields are valid. - * RJRN will copy the value of this bit into the field of the same - * name in all TX completions, regardless of whether such - * completions are PTP completions or other TX completions. + * When this bit is '1', it indicates that the packet was dropped + * due to a transient internal error in TDC. The packet or LSO can + * be retried and may transmit successfully on a subsequent attempt. + * Note that this bit has no meaning for the timestamp completion + * and will always be '0'. */ - #define TX_CMPL_PTP_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400) - /* unused2 is 16 b */ - uint16_t unused_1; + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_INTERNAL_ERROR \ + UINT32_C(0x200) /* - * This is timestamp value (lower 32bits) read from PM for the PTP - * timestamp enabled packet. - */ - uint32_t timestamp_lo; -} __rte_packed; - -/* tx_cmpl_ptp_hi (size:128b/16B) */ -struct tx_cmpl_ptp_hi { + * When this bit is '1', it was not possible to collect a timestamp + * for a timestamp completion, in which case the ts_ns and ts_sub_ns + * fields are invalid. When this bit is '0' in a timestamp + * completion record, the ts_sub_ns, ts_ns_lo, and ts_ns_mid fields + * are valid. Note that this bit has meaning only for the timestamp + * completion. For types other than the timestamp completion, this + * bit will always be '0'. + */ + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_TIMESTAMP_INVALID_ERROR \ + UINT32_C(0x400) /* - * This is timestamp value (lower 32bits) read from PM for the PTP - * timestamp enabled packet. + * When this bit is '1', it indicates that a Timed Transmit + * SO-TXTIME packet violated the max_ttx_overtime constraint i.e., + * the time the packet was processed for transmission in TWE was + * later than the time given by (TimedTx_BD.tx_time + + * max_ttx_overtime) and as result, the packet was dropped. + * Note that max_ttx_overtime is a global configuration in TWE. + * Note that this bit has no meaning in a timestamp completion, + * and will always be '0'. */ - uint16_t timestamp_hi[3]; - uint16_t reserved16; - uint64_t v2; + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_TTX_OVERTIME_ERROR \ + UINT32_C(0x800) + /* unused2 is 16 b */ + uint16_t unused_2; /* - * This value is written by the NIC such that it will be different for - * each pass through the completion queue. - * The even passes will write 1. - * The odd passes will write 0. + * This is bits [31:0] of the nanoseconds portion of the packet + * timestamp, returned from PM for 2-step PTP timestamp or from + * PA for PA timestamps. This field is in units of ns. */ - #define TX_CMPL_PTP_HI_V2 UINT32_C(0x1) + uint32_t ts_ns_lo; } __rte_packed; /* rx_pkt_cmpl (size:128b/16B) */ @@ -9314,9 +9525,31 @@ struct hwrm_async_event_cmpl { */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD \ UINT32_C(0x46) + /* + * An event from firmware indicating that the RSS capabilities have + * changed. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RSS_CHANGE \ + UINT32_C(0x47) + /* + * An event from firmware indicating that list of nq ids used for + * doorbell pacing DBQ event notification has been updated. The driver + * needs to take appropriate action and retrieve the new list when this + * event is received from the firmware. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_NQ_UPDATE \ + UINT32_C(0x48) + /* + * An event from firmware indicating that hardware ran into an error + * while trying to read the host based doorbell copy region. The driver + * needs to take the appropriate action and maintain the corresponding + * doorbell copy region. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR \ + UINT32_C(0x49) /* Maximum Registrable event id. */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID \ - UINT32_C(0x47) + UINT32_C(0x4a) /* * A trace log message. This contains firmware trace logs string * embedded in the asynchronous message. This is an experimental @@ -11828,6 +12061,195 @@ struct hwrm_async_event_cmpl_doorbell_pacing_threshold { uint32_t event_data1; } __rte_packed; +/* hwrm_async_event_cmpl_rss_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_rss_change { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform the driver + * that the RSS capabilities have changed. The driver will need + * to query hwrm_vnic_qcaps. + */ + #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_EVENT_ID_RSS_CHANGE \ + UINT32_C(0x47) + #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_EVENT_ID_RSS_CHANGE + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; +} __rte_packed; + +/* hwrm_async_event_cmpl_doorbell_pacing_nq_update (size:128b/16B) */ +struct hwrm_async_event_cmpl_doorbell_pacing_nq_update { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * An event from firmware indicating that list of nq ids used for + * doorbell pacing DBQ event notification has been updated. The driver + * needs to take appropriate action and retrieve the new list when this + * event is received from the firmware. + */ + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_EVENT_ID_DOORBELL_PACING_NQ_UPDATE \ + UINT32_C(0x48) + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_EVENT_ID_DOORBELL_PACING_NQ_UPDATE + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; +} __rte_packed; + +/* hwrm_async_event_cmpl_hw_doorbell_recovery_read_error (size:128b/16B) */ +struct hwrm_async_event_cmpl_hw_doorbell_recovery_read_error { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform the driver + * that hardware ran into an error while trying to read the host + * based doorbell copy region. The driver will take the appropriate + * action to maintain the corresponding functions doorbell copy + * region in the correct format. + */ + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR \ + UINT32_C(0x49) + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_OPAQUE_SFT \ + 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* + * Indicates that there is an error while reading the doorbell copy + * regions. + */ + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_MASK \ + UINT32_C(0xf) + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_SFT \ + 0 + /* + * If set to 1, indicates that there is an error while reading the + * SQ doorbell copy region for this function. + */ + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_SQ_ERR \ + UINT32_C(0x1) + /* + * If set to 1, indicates that there is an error while reading the + * RQ doorbell copy region for this function. + */ + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_RQ_ERR \ + UINT32_C(0x2) + /* + * If set to 1, indicates that there is an error while reading the + * SRQ doorbell copy region for this function. + */ + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_SRQ_ERR \ + UINT32_C(0x4) + /* + * If set to 1, indicates that there is an error while reading the + * CQ doorbell copy region for this function. + */ + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_CQ_ERR \ + UINT32_C(0x8) +} __rte_packed; + /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */ struct hwrm_async_event_cmpl_fw_trace_msg { uint16_t type; @@ -12385,6 +12807,14 @@ struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold { UINT32_C(0x4) #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST \ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD + /* + * The epoch value to be sent from firmware to the driver to track + * a doorbell recovery cycle. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK \ + UINT32_C(0xffffff00) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_SFT \ + 8 } __rte_packed; /* hwrm_async_event_cmpl_error_report_thermal (size:128b/16B) */ @@ -12516,8 +12946,8 @@ struct metadata_base_msg { #define METADATA_BASE_MSG_MD_TYPE_NONE UINT32_C(0x0) /* * This setting is used when packets are coming in-order. Depending on - * the state of the receive context, the meta-data will carry different - * information. + * the state of the receive context, the meta-data will carry + * different information. */ #define METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC UINT32_C(0x1) /* @@ -12525,12 +12955,21 @@ struct metadata_base_msg { * record that it is requesting a resync on in the meta data. */ #define METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC UINT32_C(0x2) + /* This setting is used for QUIC packets. */ + #define METADATA_BASE_MSG_MD_TYPE_QUIC UINT32_C(0x3) + /* + * This setting is used for crypto packets with an unsupported + * protocol. + */ + #define METADATA_BASE_MSG_MD_TYPE_ILLEGAL UINT32_C(0x1f) #define METADATA_BASE_MSG_MD_TYPE_LAST \ - METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC + METADATA_BASE_MSG_MD_TYPE_ILLEGAL /* - * This field indicates where the next metadata block starts. It is - * counted in 16B units. A value of zero indicates that there is no - * metadata. + * This field indicates where the next metadata block starts, relative + * to the current metadata block. It is the offset to the next metadata + * header, counted in 16B units. A value of zero indicates that there is + * no additional metadata, and that the current metadata block is the + * last one. */ #define METADATA_BASE_MSG_LINK_MASK UINT32_C(0x1e0) #define METADATA_BASE_MSG_LINK_SFT 5 @@ -12544,11 +12983,12 @@ struct tls_metadata_base_msg { /* This field classifies the data present in the meta-data. */ #define TLS_METADATA_BASE_MSG_MD_TYPE_MASK \ UINT32_C(0x1f) - #define TLS_METADATA_BASE_MSG_MD_TYPE_SFT 0 + #define TLS_METADATA_BASE_MSG_MD_TYPE_SFT \ + 0 /* - * This setting is used when packets are coming in-order. Depending on - * the state of the receive context, the meta-data will carry different - * information. + * This setting is used when packets are coming in-order. Depending + * on the state of the receive context, the meta-data will carry + * different information. */ #define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC \ UINT32_C(0x1) @@ -12567,11 +13007,13 @@ struct tls_metadata_base_msg { */ #define TLS_METADATA_BASE_MSG_LINK_MASK \ UINT32_C(0x1e0) - #define TLS_METADATA_BASE_MSG_LINK_SFT 5 + #define TLS_METADATA_BASE_MSG_LINK_SFT \ + 5 /* These are flags present in the metadata. */ #define TLS_METADATA_BASE_MSG_FLAGS_MASK \ UINT32_C(0x1fffe00) - #define TLS_METADATA_BASE_MSG_FLAGS_SFT 9 + #define TLS_METADATA_BASE_MSG_FLAGS_SFT \ + 9 /* * A value of 1 implies that the packet was decrypted by HW. Otherwise * the packet is passed on as it came in on the wire. @@ -12584,7 +13026,8 @@ struct tls_metadata_base_msg { */ #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_MASK \ UINT32_C(0xc00) - #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_SFT 10 + #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_SFT \ + 10 /* * This enumeration states that the ghash is not valid in the * meta-data. @@ -12610,12 +13053,13 @@ struct tls_metadata_base_msg { /* This field indicates the status of tag authentication. */ #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_MASK \ UINT32_C(0x3000) - #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12 + #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SFT \ + 12 /* - * This enumeration is set when there is no tags present in the - * packet. + * This enumeration is set when HW was not able to authenticate a + * TAG. */ - #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_NONE \ + #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED \ (UINT32_C(0x0) << 12) /* * This enumeration states that there is at least one tag in the @@ -12638,13 +13082,61 @@ struct tls_metadata_base_msg { */ #define TLS_METADATA_BASE_MSG_FLAGS_HEADER_FLDS_VALID \ UINT32_C(0x4000) + /* + * A value of 1 indicates that the packet experienced a context load + * error. In this case, the packet is sent to the host without the + * header or payload decrypted and the context is not updated. + */ + #define TLS_METADATA_BASE_MSG_FLAGS_CTX_LOAD_ERR \ + UINT32_C(0x8000) + /* This field indicates the packet operation state. */ + #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_MASK \ + UINT32_C(0x70000) + #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_SFT \ + 16 + /* Packet is in order. */ + #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_IN_ORDER \ + (UINT32_C(0x0) << 16) + /* Packet is out of order, no header loss. */ + #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_OUT_OF_ORDER \ + (UINT32_C(0x1) << 16) + /* Packet is header search (out of order with header loss). */ + #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_HEADER_SEARCH \ + (UINT32_C(0x2) << 16) + /* Packet is resync (resync record ongoing). */ + #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC \ + (UINT32_C(0x3) << 16) + /* + * Packet is resync wait (resync record completes, waiting for + * result). + */ + #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT \ + (UINT32_C(0x4) << 16) + /* + * Packet is resync wait for partial tag (waiting for resync record + * tag). + */ + #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT_PARTIAL \ + (UINT32_C(0x5) << 16) + /* Packet is resync success (got resync record success). */ + #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS \ + (UINT32_C(0x6) << 16) + /* + * Packet is resync success wait (got midpath ACK, waiting for + * resync record success). + */ + #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT \ + (UINT32_C(0x7) << 16) + #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_LAST \ + TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT /* * This value indicates the lower 7-bit of the Crypto Key ID * associated with this operation. */ #define TLS_METADATA_BASE_MSG_KID_LO_MASK \ UINT32_C(0xfe000000) - #define TLS_METADATA_BASE_MSG_KID_LO_SFT 25 + #define TLS_METADATA_BASE_MSG_KID_LO_SFT \ + 25 uint16_t kid_hi; /* * This value indicates the upper 13-bit of the Crypto Key ID @@ -12661,11 +13153,12 @@ struct tls_metadata_insync_msg { /* This field classifies the data present in the meta-data. */ #define TLS_METADATA_INSYNC_MSG_MD_TYPE_MASK \ UINT32_C(0x1f) - #define TLS_METADATA_INSYNC_MSG_MD_TYPE_SFT 0 + #define TLS_METADATA_INSYNC_MSG_MD_TYPE_SFT \ + 0 /* * This setting is used when packets are coming in-order. Depending on - * the state of the receive context, the meta-data will carry different - * information. + * the state of the receive context, the meta-data will carry + * different information. */ #define TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC \ UINT32_C(0x1) @@ -12678,11 +13171,13 @@ struct tls_metadata_insync_msg { */ #define TLS_METADATA_INSYNC_MSG_LINK_MASK \ UINT32_C(0x1e0) - #define TLS_METADATA_INSYNC_MSG_LINK_SFT 5 + #define TLS_METADATA_INSYNC_MSG_LINK_SFT \ + 5 /* These are flags present in the metadata. */ #define TLS_METADATA_INSYNC_MSG_FLAGS_MASK \ UINT32_C(0x1fffe00) - #define TLS_METADATA_INSYNC_MSG_FLAGS_SFT 9 + #define TLS_METADATA_INSYNC_MSG_FLAGS_SFT \ + 9 /* * A value of 1 implies that the packet was decrypted by HW. Otherwise * the packet is passed on as it came in on the wire. @@ -12695,7 +13190,8 @@ struct tls_metadata_insync_msg { */ #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_MASK \ UINT32_C(0xc00) - #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_SFT 10 + #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_SFT \ + 10 /* * This enumeration states that the ghash is not valid in the * meta-data. @@ -12721,12 +13217,13 @@ struct tls_metadata_insync_msg { /* This field indicates the status of tag authentication. */ #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \ UINT32_C(0x3000) - #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12 + #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT \ + 12 /* - * This enumeration is set when there is no tags present in the - * packet. + * This enumeration is set when HW was not able to authenticate a + * TAG. */ - #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \ + #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED \ (UINT32_C(0x0) << 12) /* * This enumeration states that there is at least one tag in the @@ -12749,13 +13246,61 @@ struct tls_metadata_insync_msg { */ #define TLS_METADATA_INSYNC_MSG_FLAGS_HEADER_FLDS_VALID \ UINT32_C(0x4000) + /* + * A value of 1 indicates that the packet experienced a context load + * error. In this case, the packet is sent to the host without the + * header or payload decrypted and the context is not updated. + */ + #define TLS_METADATA_INSYNC_MSG_FLAGS_CTX_LOAD_ERR \ + UINT32_C(0x8000) + /* This field indicates the packet operation state. */ + #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_MASK \ + UINT32_C(0x70000) + #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_SFT \ + 16 + /* Packet is in order. */ + #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_IN_ORDER \ + (UINT32_C(0x0) << 16) + /* Packet is out of order, no header loss. */ + #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_OUT_OF_ORDER \ + (UINT32_C(0x1) << 16) + /* Packet is header search (out of order with header loss). */ + #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_HEADER_SEARCH \ + (UINT32_C(0x2) << 16) + /* Packet is resync (resync record ongoing). */ + #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC \ + (UINT32_C(0x3) << 16) + /* + * Packet is resync wait (resync record completes, waiting for + * result). + */ + #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT \ + (UINT32_C(0x4) << 16) + /* + * Packet is resync wait for partial tag (waiting for resync record + * tag). + */ + #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT_PARTIAL \ + (UINT32_C(0x5) << 16) + /* Packet is resync success (got resync record success). */ + #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS \ + (UINT32_C(0x6) << 16) + /* + * Packet is resync success wait (got midpath ACK, waiting for + * resync record success). + */ + #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT \ + (UINT32_C(0x7) << 16) + #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_LAST \ + TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT /* * This value indicates the lower 7-bit of the Crypto Key ID * associated with this operation. */ #define TLS_METADATA_INSYNC_MSG_KID_LO_MASK \ UINT32_C(0xfe000000) - #define TLS_METADATA_INSYNC_MSG_KID_LO_SFT 25 + #define TLS_METADATA_INSYNC_MSG_KID_LO_SFT \ + 25 uint16_t kid_hi; /* * This value indicates the upper 13-bit of the Crypto Key ID @@ -12764,14 +13309,14 @@ struct tls_metadata_insync_msg { #define TLS_METADATA_INSYNC_MSG_KID_HI_MASK UINT32_C(0x1fff) #define TLS_METADATA_INSYNC_MSG_KID_HI_SFT 0 /* - * This field is only valid when md_type is set to tls_insync. This field - * indicates the offset within the current TCP packet where the TLS header - * starts. If there are multiple TLS headers in the packet, this provides - * the offset of the last TLS header. + * This field is only valid when md_type is set to tls_insync. This + * field indicates the offset within the current TCP packet where the + * TLS header starts. If there are multiple TLS headers in the packet, + * this provides the offset of the last TLS header. * - * The field is calculated by subtracting TCP sequence number of the first - * byte of the TCP payload of the packet from the TCP sequence number of - * the last TLS header in the packet. + * The field is calculated by subtracting TCP sequence number of the + * first byte of the TCP payload of the packet from the TCP sequence + * number of the last TLS header in the packet. */ uint16_t tls_header_offset; /* @@ -12787,7 +13332,7 @@ struct tls_metadata_insync_msg { * not decrypt every packet and authenticate the record. Partial GHASH is * only sent out with packet having the TAG field. */ - uint64_t partial_ghash; + uint8_t partial_ghash[8]; } __rte_packed; /* tls_metadata_resync_msg (size:256b/32B) */ @@ -12796,7 +13341,8 @@ struct tls_metadata_resync_msg { /* This field classifies the data present in the meta-data. */ #define TLS_METADATA_RESYNC_MSG_MD_TYPE_MASK \ UINT32_C(0x1f) - #define TLS_METADATA_RESYNC_MSG_MD_TYPE_SFT 0 + #define TLS_METADATA_RESYNC_MSG_MD_TYPE_SFT \ + 0 /* * With this setting HW passes the TCP sequence number of the TLS * record that it is requesting a resync on in the meta data. @@ -12812,11 +13358,13 @@ struct tls_metadata_resync_msg { */ #define TLS_METADATA_RESYNC_MSG_LINK_MASK \ UINT32_C(0x1e0) - #define TLS_METADATA_RESYNC_MSG_LINK_SFT 5 + #define TLS_METADATA_RESYNC_MSG_LINK_SFT \ + 5 /* These are flags present in the metadata. */ #define TLS_METADATA_RESYNC_MSG_FLAGS_MASK \ UINT32_C(0x1fffe00) - #define TLS_METADATA_RESYNC_MSG_FLAGS_SFT 9 + #define TLS_METADATA_RESYNC_MSG_FLAGS_SFT \ + 9 /* * A value of 1 implies that the packet was decrypted by HW. Otherwise * the packet is passed on as it came in on the wire. @@ -12829,7 +13377,8 @@ struct tls_metadata_resync_msg { */ #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_MASK \ UINT32_C(0xc00) - #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_SFT 10 + #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_SFT \ + 10 /* * This enumeration states that the ghash is not valid in the * meta-data. @@ -12841,28 +13390,77 @@ struct tls_metadata_resync_msg { /* This field indicates the status of tag authentication. */ #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \ UINT32_C(0x3000) - #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12 + #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT \ + 12 /* - * This enumeration is set when there is no tags present in the - * packet. + * This enumeration is set when HW was not able to authenticate a + * TAG. */ - #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \ + #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED \ (UINT32_C(0x0) << 12) #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_LAST \ - TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE + TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED /* * A value of 1 indicates that this packet contains a record that * starts in the packet and extends beyond the packet. */ #define TLS_METADATA_RESYNC_MSG_FLAGS_HEADER_FLDS_VALID \ UINT32_C(0x4000) + /* + * A value of 1 indicates that the packet experienced a context load + * error. In this case, the packet is sent to the host without the + * header or payload decrypted and the context is not updated. + */ + #define TLS_METADATA_RESYNC_MSG_FLAGS_CTX_LOAD_ERR \ + UINT32_C(0x8000) + /* This field indicates the packet operation state. */ + #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_MASK \ + UINT32_C(0x70000) + #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_SFT \ + 16 + /* Packet is in order. */ + #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_IN_ORDER \ + (UINT32_C(0x0) << 16) + /* Packet is out of order, no header loss. */ + #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_OUT_OF_ORDER \ + (UINT32_C(0x1) << 16) + /* Packet is header search (out of order with header loss). */ + #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_HEADER_SEARCH \ + (UINT32_C(0x2) << 16) + /* Packet is resync (resync record ongoing). */ + #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC \ + (UINT32_C(0x3) << 16) + /* + * Packet is resync wait (resync record completes, waiting for + * result). + */ + #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT \ + (UINT32_C(0x4) << 16) + /* + * Packet is resync wait for partial tag (waiting for resync record + * tag). + */ + #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT_PARTIAL \ + (UINT32_C(0x5) << 16) + /* Packet is resync success (got resync record success). */ + #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS \ + (UINT32_C(0x6) << 16) + /* + * Packet is resync success wait (got midpath ACK, waiting for + * resync record success). + */ + #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT \ + (UINT32_C(0x7) << 16) + #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_LAST \ + TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT /* * This value indicates the lower 7-bit of the Crypto Key ID * associated with this operation. */ #define TLS_METADATA_RESYNC_MSG_KID_LO_MASK \ UINT32_C(0xfe000000) - #define TLS_METADATA_RESYNC_MSG_KID_LO_SFT 25 + #define TLS_METADATA_RESYNC_MSG_KID_LO_SFT \ + 25 uint16_t kid_hi; /* * This value indicates the upper 13-bit of the Crypto Key ID @@ -13221,7 +13819,7 @@ struct hwrm_func_vf_free_output { ********************/ -/* hwrm_func_vf_cfg_input (size:448b/56B) */ +/* hwrm_func_vf_cfg_input (size:512b/64B) */ struct hwrm_func_vf_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -13384,7 +13982,7 @@ struct hwrm_func_vf_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of TX rings) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \ @@ -13393,7 +13991,7 @@ struct hwrm_func_vf_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of RX rings) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \ @@ -13402,7 +14000,7 @@ struct hwrm_func_vf_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of CMPL rings) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \ @@ -13411,7 +14009,7 @@ struct hwrm_func_vf_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of RSS ctx) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \ @@ -13420,7 +14018,7 @@ struct hwrm_func_vf_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of ring groups) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \ @@ -13429,7 +14027,7 @@ struct hwrm_func_vf_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of stat ctx) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \ @@ -13438,7 +14036,7 @@ struct hwrm_func_vf_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of VNICs) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \ @@ -13447,7 +14045,7 @@ struct hwrm_func_vf_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of L2 ctx) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \ @@ -13486,9 +14084,10 @@ struct hwrm_func_vf_cfg_input { /* The number of HW ring groups requested for the VF. */ uint16_t num_hw_ring_grps; /* Number of Tx Key Contexts requested. */ - uint16_t num_tx_key_ctxs; + uint32_t num_tx_key_ctxs; /* Number of Rx Key Contexts requested. */ - uint16_t num_rx_key_ctxs; + uint32_t num_rx_key_ctxs; + uint8_t unused[4]; } __rte_packed; /* hwrm_func_vf_cfg_output (size:128b/16B) */ @@ -13558,7 +14157,7 @@ struct hwrm_func_qcaps_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_qcaps_output (size:768b/96B) */ +/* hwrm_func_qcaps_output (size:896b/112B) */ struct hwrm_func_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -14176,6 +14775,74 @@ struct hwrm_func_qcaps_output { /* When this bit is '1', it indicates that HW and FW support QUIC. */ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_QUIC_SUPPORTED \ UINT32_C(0x2) + /* + * When this bit is '1', it indicates that KDNet mode is + * supported on the port for this function. This bit is + * never set for a VF. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_KDNET_SUPPORTED \ + UINT32_C(0x4) + /* + * When this bit is '1', it indicates the FW is capable of + * supporting Enhanced Doorbell Pacing. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED \ + UINT32_C(0x8) + /* + * When this bit is '1', it indicates that FW is capable of + * supporting software based doorbell drop recovery. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SW_DBR_DROP_RECOVERY_SUPPORTED \ + UINT32_C(0x10) + /* + * When this bit is '1', it indicates the FW supports collection + * and query of the generic statistics. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_GENERIC_STATS_SUPPORTED \ + UINT32_C(0x20) + /* + * When this bit is '1', it indicates that the HW is capable of + * supporting UDP GSO on the function. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_UDP_GSO_SUPPORTED \ + UINT32_C(0x40) + /* + * When this bit is '1', it indicates that SyncE feature is + * supported. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SYNCE_SUPPORTED \ + UINT32_C(0x80) + /* + * When this bit is '1', it indicates the FW is capable of + * supporting doorbell pacing version 0. As doorbell pacing + * notification from hardware for Thor2 is completely different + * from Thor1, this flag is used to differentiate the doorbell + * pacing notification between Thor1 and Thor2. Thor1 uses + * dbr_pacing_supported and dbr_pacing_ext_supported flags for + * doorbell pacing whereas Thor2 uses dbr_pacing_v0_supported flag. + * These flags will never be set at the same time for Thor2. + * Based on this flag, host drivers assume doorbell pacing is needed + * for Thor2. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED \ + UINT32_C(0x100) + /* + * When this bit is '1', it indicates that the HW supports + * two-completion TX packet timestamp feature, a second completion + * carrying packet TX timestamp in addition to the standard + * completion returned for packets. Host driver should not use + * HWRM port timestamp query (HWRM_PORT_TS_QUERY) command for + * TX timestamp read when two-completion timestamp feature is + * supported. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_TX_PKT_TS_CMPL_SUPPORTED \ + UINT32_C(0x200) + /* + * When this bit is '1', it indicates that the hardware based + * link aggregation group (L2 and RoCE) feature is supported. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_HW_LAG_SUPPORTED \ + UINT32_C(0x400) uint16_t tunnel_disable_flag; /* * When this bit is '1', it indicates that the VXLAN parsing @@ -14225,7 +14892,16 @@ struct hwrm_func_qcaps_output { */ #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE \ UINT32_C(0x80) - uint8_t unused_1; + uint8_t unused_1[2]; + /* + * This value uniquely identifies the hardware NIC used by the + * function. The value returned will be the same for all functions. + * A value of 00-00-00-00-00-00-00-00 indicates no device serial number + * is currently configured. This is the same value that is returned by + * PCIe Capability Device Serial Number. + */ + uint8_t device_serial_number[8]; + uint8_t unused_2[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -14283,7 +14959,7 @@ struct hwrm_func_qcfg_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_qcfg_output (size:896b/112B) */ +/* hwrm_func_qcfg_output (size:1024b/128B) */ struct hwrm_func_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -14787,7 +15463,36 @@ struct hwrm_func_qcfg_output { */ #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_PRIMATE_ENABLED \ UINT32_C(0x10) - uint8_t unused_2[3]; + /* + * Configured doorbell page size for this function. + * This field is valid for PF only. + */ + uint8_t db_page_size; + /* DB page size is 4KB. */ + #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_4KB UINT32_C(0x0) + /* DB page size is 8KB. */ + #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_8KB UINT32_C(0x1) + /* DB page size is 16KB. */ + #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_16KB UINT32_C(0x2) + /* DB page size is 32KB. */ + #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_32KB UINT32_C(0x3) + /* DB page size is 64KB. */ + #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_64KB UINT32_C(0x4) + /* DB page size is 128KB. */ + #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_128KB UINT32_C(0x5) + /* DB page size is 256KB. */ + #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_256KB UINT32_C(0x6) + /* DB page size is 512KB. */ + #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_512KB UINT32_C(0x7) + /* DB page size is 1MB. */ + #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_1MB UINT32_C(0x8) + /* DB page size is 2MB. */ + #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_2MB UINT32_C(0x9) + /* DB page size is 4MB. */ + #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_4MB UINT32_C(0xa) + #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_LAST \ + HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_4MB + uint8_t unused_2[2]; /* * Minimum guaranteed bandwidth for the network partition made up * of the caller physical function and all its child virtual @@ -14874,11 +15579,36 @@ struct hwrm_func_qcfg_output { * value is used if ring MTU is not specified. */ uint16_t host_mtu; + uint8_t unused_3[2]; + uint8_t unused_4[2]; + /* + * KDNet mode for the port for this function. If a VF, KDNet + * mode is always disabled. + */ + uint8_t port_kdnet_mode; + /* KDNet mode is not enabled on the port for this function. */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_KDNET_MODE_DISABLED UINT32_C(0x0) + /* KDNet mode is enabled on the port for this function. */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_KDNET_MODE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_QCFG_OUTPUT_PORT_KDNET_MODE_LAST \ + HWRM_FUNC_QCFG_OUTPUT_PORT_KDNET_MODE_ENABLED + /* + * If KDNet mode is enabled, the PCI function number of the + * KDNet partition. + */ + uint8_t kdnet_pcie_function; + /* + * Function ID of the KDNET function on this port. If the + * KDNET partition does not exist and the FW supports this + * feature, 0xffff will be returned. + */ + uint16_t port_kdnet_fid; + uint8_t unused_5[2]; /* Number of Tx Key Contexts allocated. */ - uint16_t alloc_tx_key_ctxs; + uint32_t alloc_tx_key_ctxs; /* Number of Rx Key Contexts allocated. */ - uint16_t alloc_rx_key_ctxs; - uint8_t unused_3[5]; + uint32_t alloc_rx_key_ctxs; + uint8_t unused_6[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -14894,7 +15624,7 @@ struct hwrm_func_qcfg_output { *****************/ -/* hwrm_func_cfg_input (size:896b/112B) */ +/* hwrm_func_cfg_input (size:1024b/128B) */ struct hwrm_func_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -15002,7 +15732,7 @@ struct hwrm_func_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of TX rings) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \ @@ -15011,7 +15741,7 @@ struct hwrm_func_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of RX rings) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \ @@ -15020,7 +15750,7 @@ struct hwrm_func_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of CMPL rings) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \ @@ -15029,7 +15759,7 @@ struct hwrm_func_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of RSS ctx) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \ @@ -15038,7 +15768,7 @@ struct hwrm_func_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of ring groups) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \ @@ -15047,7 +15777,7 @@ struct hwrm_func_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of stat ctx) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \ @@ -15056,7 +15786,7 @@ struct hwrm_func_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of VNICs) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \ @@ -15065,7 +15795,7 @@ struct hwrm_func_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of L2 ctx) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \ @@ -15091,7 +15821,7 @@ struct hwrm_func_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of NQ rings) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \ @@ -15158,6 +15888,15 @@ struct hwrm_func_cfg_input { */ #define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_DISABLE \ UINT32_C(0x40000000) + /* + * If this bit is set to 1, the driver is requesting FW to see if + * all the assets requested in this command (i.e. number of KTLS/ + * QUIC key contexts) are available. The firmware will return an + * error if the requested assets are not available. The firmware + * will NOT reserve the assets if they are available. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_KEY_CTX_ASSETS_TEST \ + UINT32_C(0x80000000) uint32_t enables; /* * This bit must be '1' for the admin_mtu field to be @@ -15803,11 +16542,71 @@ struct hwrm_func_cfg_input { * ring that is assigned to a function has a valid mtu. */ uint16_t host_mtu; + uint8_t unused_0[4]; + uint32_t enables2; + /* + * This bit must be '1' for the kdnet_mode field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES2_KDNET UINT32_C(0x1) + /* + * This bit must be '1' for the db_page_size field to be + * configured. Legacy controller core FW may silently ignore + * the db_page_size programming request through this command. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES2_DB_PAGE_SIZE UINT32_C(0x2) + /* + * KDNet mode for the port for this function. If NPAR is + * also configured on this port, it takes precedence. KDNet + * mode is ignored for a VF. + */ + uint8_t port_kdnet_mode; + /* KDNet mode is not enabled. */ + #define HWRM_FUNC_CFG_INPUT_PORT_KDNET_MODE_DISABLED UINT32_C(0x0) + /* KDNet mode enabled. */ + #define HWRM_FUNC_CFG_INPUT_PORT_KDNET_MODE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_CFG_INPUT_PORT_KDNET_MODE_LAST \ + HWRM_FUNC_CFG_INPUT_PORT_KDNET_MODE_ENABLED + /* + * This field can be used by the PF driver to configure the doorbell + * page size. L2 driver can use different pages to ring the doorbell + * for L2 push operation. The doorbell page size should be configured + * to match the native CPU page size for proper RoCE and L2 doorbell + * operations. This value supersedes the older method of configuring + * the doorbell page size by the RoCE driver using the command queue + * method. The default is 4K. + */ + uint8_t db_page_size; + /* DB page size is 4KB. */ + #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_4KB UINT32_C(0x0) + /* DB page size is 8KB. */ + #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_8KB UINT32_C(0x1) + /* DB page size is 16KB. */ + #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_16KB UINT32_C(0x2) + /* DB page size is 32KB. */ + #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_32KB UINT32_C(0x3) + /* DB page size is 64KB. */ + #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_64KB UINT32_C(0x4) + /* DB page size is 128KB. */ + #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_128KB UINT32_C(0x5) + /* DB page size is 256KB. */ + #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_256KB UINT32_C(0x6) + /* DB page size is 512KB. */ + #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_512KB UINT32_C(0x7) + /* DB page size is 1MB. */ + #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_1MB UINT32_C(0x8) + /* DB page size is 2MB. */ + #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_2MB UINT32_C(0x9) + /* DB page size is 4MB. */ + #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_4MB UINT32_C(0xa) + #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_LAST \ + HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_4MB + uint8_t unused_1[2]; /* Number of Tx Key Contexts requested. */ - uint16_t num_tx_key_ctxs; + uint32_t num_tx_key_ctxs; /* Number of Rx Key Contexts requested. */ - uint16_t num_rx_key_ctxs; - uint8_t unused_0[4]; + uint32_t num_rx_key_ctxs; + uint8_t unused_2[4]; } __rte_packed; /* hwrm_func_cfg_output (size:128b/16B) */ @@ -15900,24 +16699,27 @@ struct hwrm_func_qstats_input { * A privileged PF can query for other function's statistics. */ uint16_t fid; - /* This flags indicates the type of statistics request. */ uint8_t flags; - /* This value is not used to avoid backward compatibility issues. */ - #define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0) /* - * flags should be set to 1 when request is for only RoCE statistics. - * This will be honored only if the caller_fid is a privileged PF. - * In all other cases FID and caller_fid should be the same. + * This bit should be set to 1 when request is for only RoCE + * statistics. This will be honored only if the caller_fid is + * a privileged PF. In all other cases FID and caller_fid should + * be the same. */ - #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1) + #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1) /* - * flags should be set to 2 when request is for the counter mask, + * This bit should be set to 1 when request is for the counter mask, * representing the width of each of the stats counters, rather * than counters themselves. */ - #define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2) - #define HWRM_FUNC_QSTATS_INPUT_FLAGS_LAST \ - HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK + #define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2) + /* + * This bit should be set to 1 when request is for only L2 + * statistics. This will be honored only if the caller_fid is + * a privileged PF. In all other cases FID and caller_fid should + * be the same. + */ + #define HWRM_FUNC_QSTATS_INPUT_FLAGS_L2_ONLY UINT32_C(0x4) uint8_t unused_0[5]; } __rte_packed; @@ -15992,7 +16794,18 @@ struct hwrm_func_qstats_output { uint64_t rx_agg_events; /* Number of aborted aggregations on the function. */ uint64_t rx_agg_aborts; - uint8_t unused_0[7]; + /* + * This field is the sequence of the statistics of a function being + * cleared. Firmware starts the sequence from zero. It increments + * the sequence number every time the statistics of the function + * are cleared, which can be triggered by a clear statistics request + * or by freeing all statistics contexts of the function. If a user + * is interested in knowing if the statistics have been cleared + * since the last query, it can keep track of this sequence number + * between queries. + */ + uint8_t clear_seq; + uint8_t unused_0[6]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -16045,24 +16858,20 @@ struct hwrm_func_qstats_ext_input { * A privileged PF can query for other function's statistics. */ uint16_t fid; - /* This flags indicates the type of statistics request. */ uint8_t flags; - /* This value is not used to avoid backward compatibility issues. */ - #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0) /* - * flags should be set to 1 when request is for only RoCE statistics. - * This will be honored only if the caller_fid is a privileged PF. - * In all other cases FID and caller_fid should be the same. + * This bit should be set to 1 when request is for only RoCE + * statistics. This will be honored only if the caller_fid is + * a privileged PF. In all other cases FID and caller_fid should + * be the same. */ - #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1) + #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1) /* - * flags should be set to 2 when request is for the counter mask + * This bit should be set to 1 when request is for the counter mask * representing the width of each of the stats counters, rather * than counters themselves. */ - #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2) - #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_LAST \ - HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK + #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2) uint8_t unused_0[1]; uint32_t enables; /* @@ -16418,6 +17227,14 @@ struct hwrm_func_drv_rgtr_input { */ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_NPAR_1_2_SUPPORT \ UINT32_C(0x200) + /* + * When this bit is 1, the function's driver is indicating the + * support for asymmetric queue configuration, such that queue + * ids and service profiles on TX side are not the same as the + * corresponding queue configuration on the RX side + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ASYM_QUEUE_CFG_SUPPORT \ + UINT32_C(0x400) uint32_t enables; /* * This bit must be '1' for the os_type field to be @@ -16979,7 +17796,7 @@ struct hwrm_func_resource_qcaps_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_resource_qcaps_output (size:512b/64B) */ +/* hwrm_func_resource_qcaps_output (size:576b/72B) */ struct hwrm_func_resource_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -17054,15 +17871,16 @@ struct hwrm_func_resource_qcaps_output { */ #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \ UINT32_C(0x1) + uint8_t unused_0[2]; /* Minimum guaranteed number of Tx Key Contexts */ - uint16_t min_tx_key_ctxs; + uint32_t min_tx_key_ctxs; /* Maximum non-guaranteed number of Tx Key Contexts */ - uint16_t max_tx_key_ctxs; + uint32_t max_tx_key_ctxs; /* Minimum guaranteed number of Rx Key Contexts */ - uint16_t min_rx_key_ctxs; + uint32_t min_rx_key_ctxs; /* Maximum non-guaranteed number of Rx Key Contexts */ - uint16_t max_rx_key_ctxs; - uint8_t unused_0[5]; + uint32_t max_rx_key_ctxs; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -17078,7 +17896,7 @@ struct hwrm_func_resource_qcaps_output { *****************************/ -/* hwrm_func_vf_resource_cfg_input (size:512b/64B) */ +/* hwrm_func_vf_resource_cfg_input (size:576b/72B) */ struct hwrm_func_vf_resource_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -17152,18 +17970,18 @@ struct hwrm_func_vf_resource_cfg_input { */ #define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED \ UINT32_C(0x1) + uint8_t unused_0[2]; /* Minimum guaranteed number of Tx Key Contexts */ - uint16_t min_tx_key_ctxs; + uint32_t min_tx_key_ctxs; /* Maximum non-guaranteed number of Tx Key Contexts */ - uint16_t max_tx_key_ctxs; + uint32_t max_tx_key_ctxs; /* Minimum guaranteed number of Rx Key Contexts */ - uint16_t min_rx_key_ctxs; + uint32_t min_rx_key_ctxs; /* Maximum non-guaranteed number of Rx Key Contexts */ - uint16_t max_rx_key_ctxs; - uint8_t unused_0[2]; + uint32_t max_rx_key_ctxs; } __rte_packed; -/* hwrm_func_vf_resource_cfg_output (size:256b/32B) */ +/* hwrm_func_vf_resource_cfg_output (size:320b/40B) */ struct hwrm_func_vf_resource_cfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -17190,10 +18008,10 @@ struct hwrm_func_vf_resource_cfg_output { /* Reserved number of ring groups */ uint16_t reserved_hw_ring_grps; /* Actual number of Tx Key Contexts reserved */ - uint16_t reserved_tx_key_ctxs; + uint32_t reserved_tx_key_ctxs; /* Actual number of Rx Key Contexts reserved */ - uint16_t reserved_rx_key_ctxs; - uint8_t unused_0[3]; + uint32_t reserved_rx_key_ctxs; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -17479,8 +18297,13 @@ struct hwrm_func_backing_store_qcaps_output { * function. */ uint32_t rkc_max_entries; + /* + * Additional number of RoCE QP context entries required for this + * function to support fast QP destroy feature. + */ + uint16_t fast_qpmd_qp_num_entries; /* Reserved for future. */ - uint8_t rsvd1[7]; + uint8_t rsvd1[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -20638,31 +21461,53 @@ struct hwrm_func_ptp_pin_qcfg_output { /* Type of function for Pin #2. */ uint8_t pin2_usage; /* No function is configured. */ - #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_NONE UINT32_C(0x0) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_NONE \ + UINT32_C(0x0) /* PPS IN is configured. */ - #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_IN \ + UINT32_C(0x1) /* PPS OUT is configured. */ - #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_OUT \ + UINT32_C(0x2) /* SYNC IN is configured. */ - #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_IN \ + UINT32_C(0x3) /* SYNC OUT is configured. */ - #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT \ + UINT32_C(0x4) + /* SYNCE primary clock OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT \ + UINT32_C(0x5) + /* SYNCE secondary clock OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT \ + UINT32_C(0x6) #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_LAST \ - HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT /* Type of function for Pin #3. */ uint8_t pin3_usage; /* No function is configured. */ - #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_NONE UINT32_C(0x0) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_NONE \ + UINT32_C(0x0) /* PPS IN is configured. */ - #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_IN \ + UINT32_C(0x1) /* PPS OUT is configured. */ - #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_OUT \ + UINT32_C(0x2) /* SYNC IN is configured. */ - #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_IN \ + UINT32_C(0x3) /* SYNC OUT is configured. */ - #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT \ + UINT32_C(0x4) + /* SYNCE primary clock OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT \ + UINT32_C(0x5) + /* SYNCE secondary OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT \ + UINT32_C(0x6) #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_LAST \ - HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT uint8_t unused_0; /* * This field is used in Output records to indicate that the output @@ -20813,17 +21658,28 @@ struct hwrm_func_ptp_pin_cfg_input { /* Configure function for TSIO pin#2. */ uint8_t pin2_usage; /* No function is configured. */ - #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_NONE UINT32_C(0x0) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_NONE \ + UINT32_C(0x0) /* PPS IN is configured. */ - #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_IN \ + UINT32_C(0x1) /* PPS OUT is configured. */ - #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_OUT \ + UINT32_C(0x2) /* SYNC IN is configured. */ - #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_IN \ + UINT32_C(0x3) /* SYNC OUT is configured. */ - #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT \ + UINT32_C(0x4) + /* SYNCE primary clock OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT \ + UINT32_C(0x5) + /* SYNCE secondary clock OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT \ + UINT32_C(0x6) #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_LAST \ - HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT /* Enable or disable functionality of Pin #3. */ uint8_t pin3_state; /* Disabled */ @@ -20835,17 +21691,28 @@ struct hwrm_func_ptp_pin_cfg_input { /* Configure function for TSIO pin#3. */ uint8_t pin3_usage; /* No function is configured. */ - #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_NONE UINT32_C(0x0) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_NONE \ + UINT32_C(0x0) /* PPS IN is configured. */ - #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_IN \ + UINT32_C(0x1) /* PPS OUT is configured. */ - #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_OUT \ + UINT32_C(0x2) /* SYNC IN is configured. */ - #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_IN \ + UINT32_C(0x3) /* SYNC OUT is configured. */ - #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT \ + UINT32_C(0x4) + /* SYNCE primary clock OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT \ + UINT32_C(0x5) + /* SYNCE secondary clock OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT \ + UINT32_C(0x6) #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_LAST \ - HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT uint8_t unused_0[4]; } __rte_packed; @@ -21130,12 +21997,25 @@ struct hwrm_func_ptp_ts_query_output { uint16_t resp_len; /* Timestamp value of last PPS event latched. */ uint64_t pps_event_ts; - /* PTM local timestamp value. */ - uint64_t ptm_res_local_ts; - /* PTM Master timestamp value. */ - uint64_t ptm_pmstr_ts; - /* PTM Master propagation delay */ - uint32_t ptm_mstr_prop_dly; + /* + * PHC timestamp value when PTM responseD request is received + * at downstream port (t4'). This is a 48 bit timestamp in nanoseconds. + */ + uint64_t ptm_local_ts; + /* + * PTM System timestamp value corresponding to t4' at + * root complex (T4'). Together with ptm_local_ts, these + * two timestamps provide the cross-trigger timestamps. + * Driver can directly use these values for cross-trigger. + * This is a 48 bit timestamp in nanoseconds. + */ + uint64_t ptm_system_ts; + /* + * PTM Link delay. This is the time taken at root complex (RC) + * between receiving PTM request and sending PTM response to + * downstream port. This is a 32 bit value in nanoseconds. + */ + uint32_t ptm_link_delay; uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output @@ -21463,7 +22343,18 @@ struct hwrm_func_key_ctx_alloc_output { uint16_t resp_len; /* Actual number of Key Contexts allocated. */ uint16_t num_key_ctxs_allocated; - uint8_t unused_0[5]; + /* Control flags. */ + uint8_t flags; + /* + * When set, it indicates that all key contexts allocated by this + * command are contiguous. As a result, the driver has to read the + * start context ID from the first entry of the DMA data buffer + * and figures out the end context ID by “start context ID + + * num_key_ctxs_allocated - 1”. + */ + #define HWRM_FUNC_KEY_CTX_ALLOC_OUTPUT_FLAGS_KEY_CTXS_CONTIGUOUS \ + UINT32_C(0x1) + uint8_t unused_0[4]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -21574,6 +22465,9 @@ struct hwrm_func_backing_store_cfg_v2_input { * Instance of the backing store type. It is zero-based, * which means "0" indicates the first instance. For backing * stores with single instance only, leave this field to 0. + * 1. If the backing store type is MPC TQM ring, use the following + * instance value to MPC client mapping: + * TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4) */ uint16_t instance; /* Control flags. */ @@ -21586,6 +22480,31 @@ struct hwrm_func_backing_store_cfg_v2_input { */ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_PREBOOT_MODE \ UINT32_C(0x1) + /* + * When set, the driver indicates that the backing store type + * to be configured in this command is the last one to do for + * the associated PF. That means all backing store type + * configurations are done for the corresponding PF after this + * command. As a result, the firmware has to do the necessary + * post configurations. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_BS_CFG_ALL_DONE \ + UINT32_C(0x2) + /* + * When set, the driver indicates extending the size of the specific + * backing store type instead of configuring the corresponding PBLs. + * The size specified in the command will be the new size to be + * configured. The operation is only valid when the specific backing + * store has been configured before. Otherwise, the firmware will + * return an error. The driver needs to zero out the “entry_size”, + * “flags”, “page_dir”, and “page_size_pbl_level” fields, and the + * firmware will ignore these inputs. Further, the firmware expects + * the “num_entries” and any valid split entries to be no less than + * the initial value that has been configured. If not, it will + * return an error code. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_BS_EXTEND \ + UINT32_C(0x4) /* Page directory. */ uint64_t page_dir; /* Number of entries */ @@ -21957,6 +22876,52 @@ struct hwrm_func_backing_store_qcfg_v2_output { uint8_t valid; } __rte_packed; +/* Common structure to cast QPC split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is QPC. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */ +/* qpc_split_entries (size:128b/16B) */ +struct qpc_split_entries { + /* Number of L2 QP backing store entries. */ + uint32_t qp_num_l2_entries; + /* Number of QP1 entries. */ + uint32_t qp_num_qp1_entries; + uint32_t rsvd[2]; +} __rte_packed; + +/* Common structure to cast SRQ split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is SRQ. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */ +/* srq_split_entries (size:128b/16B) */ +struct srq_split_entries { + /* Number of L2 SRQ backing store entries. */ + uint32_t srq_num_l2_entries; + uint32_t rsvd; + uint32_t rsvd2[2]; +} __rte_packed; + +/* Common structure to cast CQ split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is CQ. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */ +/* cq_split_entries (size:128b/16B) */ +struct cq_split_entries { + /* Number of L2 CQ backing store entries. */ + uint32_t cq_num_l2_entries; + uint32_t rsvd; + uint32_t rsvd2[2]; +} __rte_packed; + +/* Common structure to cast VNIC split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is VNIC. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */ +/* vnic_split_entries (size:128b/16B) */ +struct vnic_split_entries { + /* Number of VNIC backing store entries. */ + uint32_t vnic_num_vnic_entries; + uint32_t rsvd; + uint32_t rsvd2[2]; +} __rte_packed; + +/* Common structure to cast MRAV split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is MRAV. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */ +/* mrav_split_entries (size:128b/16B) */ +struct mrav_split_entries { + /* Number of AV backing store entries. */ + uint32_t mrav_num_av_entries; + uint32_t rsvd; + uint32_t rsvd2[2]; +} __rte_packed; + /************************************ * hwrm_func_backing_store_qcaps_v2 * ************************************/ @@ -22150,6 +23115,9 @@ struct hwrm_func_backing_store_qcaps_v2_output { /* * Bit map of the valid instances associated with the * backing store type. + * 1. If the backing store type is MPC TQM ring, use the following + * bit to MPC client mapping: + * TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4) */ uint32_t instance_bit_map; /* @@ -22506,7 +23474,7 @@ struct hwrm_func_dbr_pacing_qcfg_output { uint8_t unused_3[7]; /* * Specifies primary function’s NQ ID. - * A value of 0xFFFF indicates NQ ID is invalid. + * A value of 0xFFFF FFFF indicates NQ ID is invalid. */ uint32_t primary_nq_id; /* @@ -22585,13 +23553,13 @@ struct hwrm_func_dbr_pacing_broadcast_event_output { uint8_t valid; } __rte_packed; -/*********************** - * hwrm_func_vlan_qcfg * - ***********************/ +/************************************* + * hwrm_func_dbr_pacing_nqlist_query * + *************************************/ -/* hwrm_func_vlan_qcfg_input (size:192b/24B) */ -struct hwrm_func_vlan_qcfg_input { +/* hwrm_func_dbr_pacing_nqlist_query_input (size:128b/16B) */ +struct hwrm_func_dbr_pacing_nqlist_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22620,18 +23588,10 @@ struct hwrm_func_vlan_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Function ID of the function that is being - * configured. - * If set to 0xFF... (All Fs), then the configuration is - * for the requesting function. - */ - uint16_t fid; - uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_vlan_qcfg_output (size:320b/40B) */ -struct hwrm_func_vlan_qcfg_output { +/* hwrm_func_dbr_pacing_nqlist_query_output (size:384b/48B) */ +struct hwrm_func_dbr_pacing_nqlist_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22640,49 +23600,414 @@ struct hwrm_func_vlan_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint64_t unused_0; - /* S-TAG VLAN identifier configured for the function. */ - uint16_t stag_vid; - /* S-TAG PCP value configured for the function. */ - uint8_t stag_pcp; - uint8_t unused_1; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id0; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id1; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id2; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id3; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id4; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id5; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id6; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id7; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id8; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id9; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id10; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id11; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id12; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id13; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id14; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id15; + /* Number of consecutive NQ ring IDs populated in the response. */ + uint32_t num_nqs; + uint8_t unused_0[3]; /* - * S-TAG TPID value configured for the function. This field is specified in - * network byte order. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint16_t stag_tpid; - /* C-TAG VLAN identifier configured for the function. */ - uint16_t ctag_vid; - /* C-TAG PCP value configured for the function. */ - uint8_t ctag_pcp; - uint8_t unused_2; + uint8_t valid; +} __rte_packed; + +/************************************ + * hwrm_func_dbr_recovery_completed * + ************************************/ + + +/* hwrm_func_dbr_recovery_completed_input (size:192b/24B) */ +struct hwrm_func_dbr_recovery_completed_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * C-TAG TPID value configured for the function. This field is specified in - * network byte order. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint16_t ctag_tpid; - /* Future use. */ - uint32_t rsvd2; - /* Future use. */ - uint32_t rsvd3; - uint8_t unused_3[3]; + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Specifies the epoch value with the one that was specified by the + * firmware in the error_report_doorbell_drop_threshold async event + * corresponding to the specific recovery cycle. + */ + uint32_t epoch; + /* The epoch value. */ + #define HWRM_FUNC_DBR_RECOVERY_COMPLETED_INPUT_EPOCH_VALUE_MASK \ + UINT32_C(0xffffff) + #define HWRM_FUNC_DBR_RECOVERY_COMPLETED_INPUT_EPOCH_VALUE_SFT 0 + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_func_dbr_recovery_completed_output (size:128b/16B) */ +struct hwrm_func_dbr_recovery_completed_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/********************** - * hwrm_func_vlan_cfg * - **********************/ +/*********************** + * hwrm_func_synce_cfg * + ***********************/ -/* hwrm_func_vlan_cfg_input (size:384b/48B) */ -struct hwrm_func_vlan_cfg_input { +/* hwrm_func_synce_cfg_input (size:192b/24B) */ +struct hwrm_func_synce_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t enables; + /* + * This bit must be '1' for the freq_profile field to be + * configured. + */ + #define HWRM_FUNC_SYNCE_CFG_INPUT_ENABLES_FREQ_PROFILE \ + UINT32_C(0x1) + /* + * This bit must be '1' for the primary_clock_state field to be + * configured. + */ + #define HWRM_FUNC_SYNCE_CFG_INPUT_ENABLES_PRIMARY_CLOCK \ + UINT32_C(0x2) + /* + * This bit must be '1' for the secondary_clock_state field to be + * configured. + */ + #define HWRM_FUNC_SYNCE_CFG_INPUT_ENABLES_SECONDARY_CLOCK \ + UINT32_C(0x4) + /* Frequency profile for SyncE recovered clock. */ + uint8_t freq_profile; + /* Invalid frequency profile */ + #define HWRM_FUNC_SYNCE_CFG_INPUT_FREQ_PROFILE_INVALID UINT32_C(0x0) + /* 25MHz SyncE clock profile */ + #define HWRM_FUNC_SYNCE_CFG_INPUT_FREQ_PROFILE_25MHZ UINT32_C(0x1) + #define HWRM_FUNC_SYNCE_CFG_INPUT_FREQ_PROFILE_LAST \ + HWRM_FUNC_SYNCE_CFG_INPUT_FREQ_PROFILE_25MHZ + /* + * Enable or disable primary clock for PF/port, overriding previous + * primary clock setting. + */ + uint8_t primary_clock_state; + /* Disable clock */ + #define HWRM_FUNC_SYNCE_CFG_INPUT_PRIMARY_CLOCK_STATE_DISABLE \ + UINT32_C(0x0) + /* Enable clock */ + #define HWRM_FUNC_SYNCE_CFG_INPUT_PRIMARY_CLOCK_STATE_ENABLE \ + UINT32_C(0x1) + #define HWRM_FUNC_SYNCE_CFG_INPUT_PRIMARY_CLOCK_STATE_LAST \ + HWRM_FUNC_SYNCE_CFG_INPUT_PRIMARY_CLOCK_STATE_ENABLE + /* + * Enable or disable secondary clock for PF/port, overriding previous + * secondary clock setting. + */ + uint8_t secondary_clock_state; + /* Clock disabled */ + #define HWRM_FUNC_SYNCE_CFG_INPUT_SECONDARY_CLOCK_STATE_DISABLE \ + UINT32_C(0x0) + /* Clock enabled */ + #define HWRM_FUNC_SYNCE_CFG_INPUT_SECONDARY_CLOCK_STATE_ENABLE \ + UINT32_C(0x1) + #define HWRM_FUNC_SYNCE_CFG_INPUT_SECONDARY_CLOCK_STATE_LAST \ + HWRM_FUNC_SYNCE_CFG_INPUT_SECONDARY_CLOCK_STATE_ENABLE + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_func_synce_cfg_output (size:128b/16B) */ +struct hwrm_func_synce_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************ + * hwrm_func_synce_qcfg * + ************************/ + + +/* hwrm_func_synce_qcfg_input (size:192b/24B) */ +struct hwrm_func_synce_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t unused_0[8]; +} __rte_packed; + +/* hwrm_func_synce_qcfg_output (size:128b/16B) */ +struct hwrm_func_synce_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Frequency profile for SyncE recovered clock. */ + uint8_t freq_profile; + /* Invalid frequency profile */ + #define HWRM_FUNC_SYNCE_QCFG_OUTPUT_FREQ_PROFILE_INVALID UINT32_C(0x0) + /* 25MHz SyncE clock profile */ + #define HWRM_FUNC_SYNCE_QCFG_OUTPUT_FREQ_PROFILE_25MHZ UINT32_C(0x1) + #define HWRM_FUNC_SYNCE_QCFG_OUTPUT_FREQ_PROFILE_LAST \ + HWRM_FUNC_SYNCE_QCFG_OUTPUT_FREQ_PROFILE_25MHZ + /* SyncE recovered clock state */ + uint8_t state; + /* + * When this bit is '1', primary clock is enabled for this PF/port. + * When this bit is '0', primary clock is disabled for this PF/port. + */ + #define HWRM_FUNC_SYNCE_QCFG_OUTPUT_STATE_PRIMARY_CLOCK_ENABLED \ + UINT32_C(0x1) + /* + * When this bit is '1', secondary clock is enabled for this + * PF/port. + * When this bit is '0', secondary clock is disabled for this + * PF/port. + */ + #define HWRM_FUNC_SYNCE_QCFG_OUTPUT_STATE_SECONDARY_CLOCK_ENABLED \ + UINT32_C(0x2) + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************** + * hwrm_func_vlan_qcfg * + ***********************/ + + +/* hwrm_func_vlan_qcfg_input (size:192b/24B) */ +struct hwrm_func_vlan_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function that is being + * configured. + * If set to 0xFF... (All Fs), then the configuration is + * for the requesting function. + */ + uint16_t fid; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_func_vlan_qcfg_output (size:320b/40B) */ +struct hwrm_func_vlan_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint64_t unused_0; + /* S-TAG VLAN identifier configured for the function. */ + uint16_t stag_vid; + /* S-TAG PCP value configured for the function. */ + uint8_t stag_pcp; + uint8_t unused_1; + /* + * S-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t stag_tpid; + /* C-TAG VLAN identifier configured for the function. */ + uint16_t ctag_vid; + /* C-TAG PCP value configured for the function. */ + uint8_t ctag_pcp; + uint8_t unused_2; + /* + * C-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t ctag_tpid; + /* Future use. */ + uint32_t rsvd2; + /* Future use. */ + uint32_t rsvd3; + uint8_t unused_3[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************** + * hwrm_func_vlan_cfg * + **********************/ + + +/* hwrm_func_vlan_cfg_input (size:384b/48B) */ +struct hwrm_func_vlan_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -24576,7 +25901,7 @@ struct hwrm_port_phy_qcfg_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_port_phy_qcfg_output (size:768b/96B) */ +/* hwrm_port_phy_qcfg_output (size:832b/104B) */ struct hwrm_port_phy_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -25601,6 +26926,14 @@ struct hwrm_port_phy_qcfg_output { /* 200Gb link speed */ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB \ UINT32_C(0x4) + /* + * This field is used to indicate the reasons for link down. + * This field is set to 0, if the link down reason is unknown. + */ + uint8_t link_down_reason; + /* Remote fault */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_DOWN_REASON_RF UINT32_C(0x1) + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -26934,16 +28267,12 @@ struct hwrm_port_qstats_input { /* Port ID of port that is being queried. */ uint16_t port_id; uint8_t flags; - /* This value is not used to avoid backward compatibility issues. */ - #define HWRM_PORT_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0) /* * This bit is set to 1 when request is for a counter mask, * representing the width of each of the stats counters, rather * than counters themselves. */ - #define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) - #define HWRM_PORT_QSTATS_INPUT_FLAGS_LAST \ - HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK + #define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) uint8_t unused_0[5]; /* * This is the host address where @@ -27646,16 +28975,12 @@ struct hwrm_port_qstats_ext_input { */ uint16_t rx_stat_size; uint8_t flags; - /* This value is not used to avoid backward compatibility issues. */ - #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0) /* * This bit is set to 1 when request is for the counter mask, * representing width of each of the stats counters, rather than * counters themselves. */ - #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) - #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_LAST \ - HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK + #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) uint8_t unused_0; /* * This is the host address where @@ -27903,16 +29228,12 @@ struct hwrm_port_ecn_qstats_input { */ uint16_t ecn_stat_buf_size; uint8_t flags; - /* This value is not used to avoid backward compatibility issues. */ - #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0) /* * This bit is set to 1 when request is for a counter mask, * representing the width of each of the stats counters, rather * than counters themselves. */ - #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) - #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_LAST \ - HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK + #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) uint8_t unused_0[3]; /* * This is the host address where @@ -28398,6 +29719,12 @@ struct hwrm_port_phy_qcaps_output { */ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PFC_UNSUPPORTED \ UINT32_C(0x2) + /* + * If set to 1, then this field indicates that + * bank based addressing is supported in firmware. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_BANK_ADDR_SUPPORTED \ + UINT32_C(0x4) /* * Number of internal ports for this device. This field allows the FW * to advertise how many internal ports are present. Manufacturing @@ -29720,6 +31047,14 @@ struct hwrm_port_prbs_test_input { #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5) /* PRBS58 */ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6) + /* PRBS49 */ + #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS49 UINT32_C(0x7) + /* PRBS10 */ + #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS10 UINT32_C(0x8) + /* PRBS20 */ + #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS20 UINT32_C(0x9) + /* PRBS13 */ + #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS13 UINT32_C(0xa) /* Invalid */ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff) #define HWRM_PORT_PRBS_TEST_INPUT_POLY_LAST \ @@ -29749,6 +31084,15 @@ struct hwrm_port_prbs_test_input { */ #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID \ UINT32_C(0x4) + /* If set to 1, FEC stat t-code 0-7 registers are enabled. */ + #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_FEC_STAT_T0_T7 \ + UINT32_C(0x8) + /* + * If set to 1, FEC stat t-code 8-15 registers are enabled. + * If fec_stat_t0_t7 is set, fec_stat_t8_t15 field will be ignored. + */ + #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_FEC_STAT_T8_T15 \ + UINT32_C(0x10) /* Duration in seconds to run the PRBS test. */ uint16_t timeout; /* @@ -29777,7 +31121,15 @@ struct hwrm_port_prbs_test_output { uint16_t resp_len; /* Total length of stored data. */ uint16_t total_data_len; - uint16_t unused_0; + /* This field is used in Output records to indicate the output format */ + uint8_t ber_format; + /* BER_FORMAT_PRBS */ + #define HWRM_PORT_PRBS_TEST_OUTPUT_BER_FORMAT_PRBS UINT32_C(0x0) + /* BER_FORMAT_FEC */ + #define HWRM_PORT_PRBS_TEST_OUTPUT_BER_FORMAT_FEC UINT32_C(0x1) + #define HWRM_PORT_PRBS_TEST_OUTPUT_BER_FORMAT_LAST \ + HWRM_PORT_PRBS_TEST_OUTPUT_BER_FORMAT_FEC + uint8_t unused_0; uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output @@ -30800,6 +32152,160 @@ struct hwrm_port_ep_tx_qcfg_output { uint8_t valid; } __rte_packed; +/***************** + * hwrm_port_cfg * + *****************/ + + +/* hwrm_port_cfg_input (size:256b/32B) */ +struct hwrm_port_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + uint32_t enables; + /* + * This bit must be '1' for the tx_rate_limit field to + * be configured. + */ + #define HWRM_PORT_CFG_INPUT_ENABLES_TX_RATE_LIMIT UINT32_C(0x1) + /* Port ID of port that is to be configured. */ + uint16_t port_id; + uint16_t unused_0; + /* + * Requested setting of TX rate limit in Mbps. + * tx_rate_limit = 0 will cancel the rate limit if any. + * This field is valid only when tx_rate_limit bit in 'enables' + * field is '1'. + */ + uint32_t tx_rate_limit; +} __rte_packed; + +/* hwrm_port_cfg_output (size:128b/16B) */ +struct hwrm_port_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************** + * hwrm_port_qcfg * + ******************/ + + +/* hwrm_port_qcfg_input (size:192b/24B) */ +struct hwrm_port_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Port ID of port that is to be queried. */ + uint16_t port_id; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_port_qcfg_output (size:192b/24B) */ +struct hwrm_port_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t supported; + /* + * If set to '1', then this bit indicates that TX rate limit + * could be configured via hwrm_port_cfg command. + */ + #define HWRM_PORT_QCFG_OUTPUT_SUPPORTED_TX_RATE_LIMIT UINT32_C(0x1) + uint32_t enabled; + /* + * If set to '1', then this bit indicates that TX rate limit + * is enabled and could be found in tx_rate_limit field. + */ + #define HWRM_PORT_QCFG_OUTPUT_ENABLED_TX_RATE_LIMIT UINT32_C(0x1) + /* + * Current setting of TX rate limit in Mbps. + * This field is valid only when tx_rate_limit bit in 'enabled' + * field is '1'. + */ + uint32_t tx_rate_limit; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + /*********************** * hwrm_queue_qportcfg * ***********************/ @@ -35688,29 +37194,19 @@ struct hwrm_vnic_update_input { HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP /* * The metadata format type used in all the RX packet completions - * going through this VNIC. + * going through this VNIC. This value is product specific. Refer to + * the L2 HSI completion ring structures for the detailed + * descriptions. For Thor and Thor2, it corresponds to “meta_format” + * in “rx_pkt_cmpl_hi” and “rx_pkt_v3_cmpl_hi”, respectively. */ uint8_t metadata_format_type; - /* No metadata information. */ - #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_NONE \ - UINT32_C(0x0) - /* - * Action record pointer (table_scope[4:0], act_rec_ptr[25:0], - * vtag[19:0]). - */ - #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_ACT_RECORD_PTR \ - UINT32_C(0x1) - /* Tunnel ID (tunnel_id[31:0], vtag[19:0]) */ - #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_TUNNEL_ID \ - UINT32_C(0x2) - /* Custom header data (updated_chdr_data[31:0], vtag[19:0]) */ - #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_CUSTOM_HDR_DATA \ - UINT32_C(0x3) - /* Header offsets (hdr_offsets[31:0], vtag[19:0]) */ - #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS \ - UINT32_C(0x4) + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_0 UINT32_C(0x0) + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_1 UINT32_C(0x1) + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_2 UINT32_C(0x2) + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_3 UINT32_C(0x3) + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_4 UINT32_C(0x4) #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_LAST \ - HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS + HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_4 /* * The maximum receive unit of the vnic. * Each vnic is associated with a function. @@ -35911,6 +37407,12 @@ struct hwrm_vnic_cfg_input { */ #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \ UINT32_C(0x40) + /* + * When this bit is '1' it enables ring selection using the incoming + * spif and lcos for the packet. + */ + #define HWRM_VNIC_CFG_INPUT_FLAGS_PORTCOS_MAPPING_MODE \ + UINT32_C(0x80) uint32_t enables; /* * This bit must be '1' for the dflt_ring_grp field to be @@ -36259,6 +37761,9 @@ struct hwrm_vnic_qcfg_output { */ #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_OPERATION_STATE \ UINT32_C(0x80) + /* When this bit is '1' it indicates port cos_mapping_mode enabled. */ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_PORTCOS_MAPPING_MODE \ + UINT32_C(0x100) /* * When returned with a valid CoS Queue id, the CoS Queue/VNIC association * is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS @@ -36315,7 +37820,30 @@ struct hwrm_vnic_qcfg_output { #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_MIXED UINT32_C(0x2) #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_LAST \ HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_MIXED - uint8_t unused_1[3]; + /* + * This field conveys the metadata format type that has been + * configured. This value is product specific. Refer to the L2 HSI + * completion ring structures for the detailed descriptions. For Thor + * and Thor2, it corresponds to “meta_format” in “rx_pkt_cmpl_hi” and + * “rx_pkt_v3_cmpl_hi”, respectively. + */ + uint8_t metadata_format_type; + #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_0 UINT32_C(0x0) + #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_1 UINT32_C(0x1) + #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_2 UINT32_C(0x2) + #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_3 UINT32_C(0x3) + #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_4 UINT32_C(0x4) + #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_LAST \ + HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_4 + /* This field conveys the VNIC operation state. */ + uint8_t vnic_state; + /* Normal operation state. */ + #define HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_NORMAL UINT32_C(0x0) + /* Drop all packets. */ + #define HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_DROP UINT32_C(0x1) + #define HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_LAST \ + HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_DROP + uint8_t unused_1; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -36557,6 +38085,53 @@ struct hwrm_vnic_qcaps_output { */ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_L2_CQE_MODE_CAP \ UINT32_C(0x100000) + /* + * When this bit is '1' HW supports hash calculation + * based on IPv4 IPSEC AH SPI field. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_AH_SPI_IPV4_CAP \ + UINT32_C(0x200000) + /* + * When this bit is '1' HW supports hash calculation + * based on IPv4 IPSEC ESP SPI field. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_ESP_SPI_IPV4_CAP \ + UINT32_C(0x400000) + /* + * When this bit is '1' HW supports hash calculation + * based on IPv6 IPSEC AH SPI field. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_AH_SPI_IPV6_CAP \ + UINT32_C(0x800000) + /* + * When this bit is '1' HW supports hash calculation + * based on IPv6 IPSEC ESP SPI field. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP \ + UINT32_C(0x1000000) + /* + * When outermost_rss_cap is '1' and this bit is '1', the outermost + * RSS hash mode may be set on a PF or trusted VF. + * When outermost_rss_cap is '1' and this bit is '0', the outermost + * RSS hash mode may be set on a PF. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_TRUSTED_VF_CAP \ + UINT32_C(0x2000000) + /* + * When this bit is '1' it indicates HW is capable of enabling ring + * selection using the incoming spif and lcos for the packet. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_PORTCOS_MAPPING_MODE \ + UINT32_C(0x4000000) + /* + * When this bit is '1', it indicates controller enabled + * RSS profile TCAM mode. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_PROF_TCAM_MODE_ENABLED \ + UINT32_C(0x8000000) + /* When this bit is '1' FW supports VNIC hash mode. */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VNIC_RSS_HASH_MODE_CAP \ + UINT32_C(0x10000000) /* * This field advertises the maximum concurrent TPA aggregations * supported by the VNIC on new devices that support TPA v2 or v3. @@ -36869,6 +38444,38 @@ struct hwrm_vnic_rss_cfg_input { */ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6_FLOW_LABEL \ UINT32_C(0x40) + /* + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv4 addresses and IPSEC AH SPI field of IPSEC + * AH/IPv4 packets. Host drivers should set this bit based on + * rss_ipsec_ah_spi_ipv4_cap. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV4 \ + UINT32_C(0x80) + /* + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv4 addresses and IPSEC ESP SPI field of IPSEC + * ESP/IPv4 packets. Host drivers should set this bit based on + * rss_ipsec_esp_spi_ipv4_cap. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV4 \ + UINT32_C(0x100) + /* + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv6 addresses and IPSEC AH SPI field of IPSEC + * AH/IPv6 packets. Host drivers should set this bit based on + * rss_ipsec_ah_spi_ipv6_cap. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV6 \ + UINT32_C(0x200) + /* + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv6 addresses and IPSEC ESP SPI field of IPSEC + * ESP/IPv6 packets. Host drivers should set this bit based on + * rss_ipsec_esp_spi_ipv6_cap. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV6 \ + UINT32_C(0x400) /* VNIC ID of VNIC associated with RSS table being configured. */ uint16_t vnic_id; /* @@ -36876,11 +38483,25 @@ struct hwrm_vnic_rss_cfg_input { * Valid values range from 0 to 7. */ uint8_t ring_table_pair_index; - /* Flags to specify different RSS hash modes. */ + /* + * Flags to specify different RSS hash modes. Global RSS hash mode is + * indicated when vnic_id and rss_ctx_idx fields are set to value of + * 0xffff. Only PF can initiate global RSS hash mode setting changes. + * VNIC RSS hash mode is indicated with valid vnic_id and rss_ctx_idx, + * if FW is VNIC_RSS_HASH_MODE capable. FW configures the mode based + * on first come first serve order. Global RSS hash mode and VNIC RSS + * hash modes are mutually exclusive. FW returns invalid error + * if FW receives conflicting requests. To change the current hash + * mode, the mode associated drivers need to be unloaded and apply + * the new configuration. + */ uint8_t hash_mode_flags; /* - * When this bit is '1', it indicates using current RSS - * hash mode setting configured in the device. + * When this bit is '1' and FW is VNIC_RSS_HASH_MODE capable, + * innermost_4 and innermost_2 hash modes are used to configure + * the tuple mode. When this bit is '1' and FW is not + * VNIC_RSS_HASH_MODE capable, It indicates using current RSS hash + * mode setting configured in the device otherwise. */ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \ UINT32_C(0x1) @@ -37063,9 +38684,17 @@ struct hwrm_vnic_rss_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Index to the rss indirection table. */ + /* + * Index to the rss indirection table. This field is used as a lookup + * for chips before Thor - i.e. Cumulus and Whitney. + */ uint16_t rss_ctx_idx; - uint8_t unused_0[6]; + /* + * VNIC ID of VNIC associated with RSS table being queried. This field + * is used as a lookup for Thor and later chips. + */ + uint16_t vnic_id; + uint8_t unused_0[4]; } __rte_packed; /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */ @@ -37084,45 +38713,104 @@ struct hwrm_vnic_rss_qcfg_output { * over source and destination IPv4 addresses of IPv4 * packets. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 \ + UINT32_C(0x1) /* * When this bit is '1', the RSS hash shall be computed * over source/destination IPv4 addresses and * source/destination ports of TCP/IPv4 packets. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 \ + UINT32_C(0x2) /* * When this bit is '1', the RSS hash shall be computed * over source/destination IPv4 addresses and * source/destination ports of UDP/IPv4 packets. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 \ + UINT32_C(0x4) /* * When this bit is '1', the RSS hash shall be computed * over source and destination IPv6 addresses of IPv6 * packets. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 \ + UINT32_C(0x8) /* * When this bit is '1', the RSS hash shall be computed * over source/destination IPv6 addresses and * source/destination ports of TCP/IPv6 packets. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 \ + UINT32_C(0x10) /* * When this bit is '1', the RSS hash shall be computed * over source/destination IPv6 addresses and * source/destination ports of UDP/IPv6 packets. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 \ + UINT32_C(0x20) + /* + * When this bit is '1', the RSS hash shall be computed + * over source, destination IPv6 addresses and flow label of IPv6 + * packets. Hash type ipv6 and ipv6_flow_label are mutually + * exclusive. HW does not include the flow_label in hash + * calculation for the packets that are matching tcp_ipv6 and + * udp_ipv6 hash types. This bit will be '0' if + * rss_ipv6_flow_label_cap is '0'. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6_FLOW_LABEL \ + UINT32_C(0x40) + /* + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv4 addresses and IPSEC AH SPI field of IPSEC + * AH/IPv4 packets. This bit will be '0' if rss_ipsec_ah_spi_ipv4_cap + * is '0'. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_AH_SPI_IPV4 \ + UINT32_C(0x80) + /* + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv4 addresses and IPSEC ESP SPI field of IPSEC + * ESP/IPv4 packets. This bit will be '0' if + * rss_ipsec_esp_spi_ipv4_cap is '0'. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_ESP_SPI_IPV4 \ + UINT32_C(0x100) + /* + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv6 addresses and IPSEC AH SPI field of IPSEC + * AH/IPv6 packets. This bit will be '0' if + * rss_ipsec_ah_spi_ipv6_cap is '0'. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_AH_SPI_IPV6 \ + UINT32_C(0x200) + /* + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv6 addresses and IPSEC ESP SPI field of IPSEC + * ESP/IPv6 packets. This bit will be '0' if + * rss_ipsec_esp_spi_ipv6_cap is '0'. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_ESP_SPI_IPV6 \ + UINT32_C(0x400) uint8_t unused_0[4]; /* This is the value of rss hash key */ uint32_t hash_key[10]; - /* Flags to specify different RSS hash modes. */ + /* + * Flags to specify different RSS hash modes. Setting rss_ctx_idx to + * the value of 0xffff implies a global RSS configuration query. + * hash_mode_flags are only valid for global RSS configuration query. + * Only the PF can initiate a global RSS configuration query. + * The query request fails if any VNIC is configured with hash mode + * and rss_ctx_idx is 0xffff. + */ uint8_t hash_mode_flags; /* - * When this bit is '1', it indicates using current RSS - * hash mode setting configured in the device. + * When this bit is '1' and FW is VNIC_RSS_HASH_MODE capable, + * it indicates VNIC's configured RSS hash mode. + * When this bit is '1' and FW is not VNIC_RSS_HASH_MODE capable, + * It indicates using current RSS hash mode setting configured in the + * device. */ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \ UINT32_C(0x1) @@ -37832,6 +39520,27 @@ struct hwrm_ring_alloc_input { */ #define HWRM_RING_ALLOC_INPUT_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION \ UINT32_C(0x2) + /* + * Used with enhanced Doorbell Pacing feature, when set to '1' + * this flag indicates that the NQ id that's allocated should be + * used for DBR pacing notifications. + */ + #define HWRM_RING_ALLOC_INPUT_FLAGS_NQ_DBR_PACING \ + UINT32_C(0x4) + /* + * Host driver should set this flag bit to '1' to enable + * two-completion TX packet timestamp feature. By enabling this + * per QP flag and enabling stamp bit in TX BD lflags, host drivers + * expect two completions, one for regular TX completion and the + * other completion with timestamp. For a QP with both completion + * coalescing and timestamp completion features enabled, completion + * coalescing takes place on regular TX completions. The timestamp + * completions are not coalesced and a separate timestamp completion + * is generated for each packet with stamp bit set in the TX BD + * lflags. + */ + #define HWRM_RING_ALLOC_INPUT_FLAGS_TX_PKT_TS_CMPL_ENABLE \ + UINT32_C(0x8) /* * This value is a pointer to the page table for the * Ring. @@ -38026,7 +39735,7 @@ struct hwrm_ring_alloc_input { * completion rings are allowed. */ uint8_t int_mode; - /* Legacy INTA */ + /* Legacy INTA (deprecated) */ #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0) /* Reserved */ #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1) @@ -40371,6 +42080,9 @@ struct hwrm_cfa_l2_filter_alloc_input { */ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \ + UINT32_C(0x10) /* Any tunneled traffic */ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ UINT32_C(0xff) @@ -41239,6 +42951,9 @@ struct hwrm_cfa_tunnel_filter_alloc_input { */ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \ + UINT32_C(0x10) /* Any tunneled traffic */ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ UINT32_C(0xff) @@ -41507,6 +43222,9 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input { */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \ + UINT32_C(0x10) /* Any tunneled traffic */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ UINT32_C(0xff) @@ -41629,6 +43347,9 @@ struct hwrm_cfa_redirect_tunnel_type_free_input { */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE \ + UINT32_C(0x10) /* Any tunneled traffic */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \ UINT32_C(0xff) @@ -41743,6 +43464,9 @@ struct hwrm_cfa_redirect_tunnel_type_info_input { */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE \ + UINT32_C(0x10) /* Any tunneled traffic */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \ UINT32_C(0xff) @@ -41978,8 +43702,11 @@ struct hwrm_cfa_encap_record_alloc_input { */ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE \ + UINT32_C(0x10) #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \ - HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 + HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE uint8_t unused_0[3]; /* This value is encap data used for the given encap type. */ uint32_t encap_data[20]; @@ -42309,6 +44036,9 @@ struct hwrm_cfa_ntuple_filter_alloc_input { * Applies to UDP and TCP traffic. * 6 - TCP * 17 - UDP + * 1 - ICMP + * 58 - ICMPV6 + * 255 - RSVD */ uint8_t ip_protocol; /* invalid */ @@ -42320,8 +44050,17 @@ struct hwrm_cfa_ntuple_filter_alloc_input { /* UDP */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \ UINT32_C(0x11) + /* ICMP */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_ICMP \ + UINT32_C(0x1) + /* ICMPV6 */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_ICMPV6 \ + UINT32_C(0x3a) + /* RSVD */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_RSVD \ + UINT32_C(0xff) #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \ - HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP + HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_RSVD /* * If set, this value shall represent the * Logical VNIC ID of the destination VNIC for the RX @@ -42388,6 +44127,9 @@ struct hwrm_cfa_ntuple_filter_alloc_input { */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \ + UINT32_C(0x10) /* Any tunneled traffic */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ UINT32_C(0xff) @@ -42979,6 +44721,9 @@ struct hwrm_cfa_em_flow_alloc_input { */ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \ + UINT32_C(0x10) /* Any tunneled traffic */ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ UINT32_C(0xff) @@ -44444,6 +46189,9 @@ struct hwrm_cfa_decap_filter_alloc_input { */ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \ + UINT32_C(0x10) /* Any tunneled traffic */ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ UINT32_C(0xff) @@ -44929,6 +46677,9 @@ struct hwrm_cfa_flow_alloc_input { */ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \ + UINT32_C(0x10) /* Any tunneled traffic */ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ UINT32_C(0xff) @@ -45182,8 +46933,11 @@ struct hwrm_cfa_flow_action_data { * (IPV6oVXLANGPE) */ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE \ + UINT32_C(0x10) #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \ - HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 + HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE uint8_t unused[7]; /* This value is encap data for the associated encap type. */ uint32_t encap_data[20]; @@ -45238,6 +46992,9 @@ struct hwrm_cfa_flow_tunnel_hdr_data { */ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE \ + UINT32_C(0x10) /* Any tunneled traffic */ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \ UINT32_C(0xff) @@ -45377,19 +47134,35 @@ struct hwrm_cfa_flow_info_input { /* Max flow handle */ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \ UINT32_C(0xfff) - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0 /* CNP flow handle */ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \ UINT32_C(0x1000) /* RoCEv1 flow handle */ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \ UINT32_C(0x2000) + /* NIC flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_NIC_TX \ + UINT32_C(0x3000) /* RoCEv2 flow handle */ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \ UINT32_C(0x4000) /* Direction rx = 1 */ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \ UINT32_C(0x8000) + /* CNP flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT_RX \ + UINT32_C(0x9000) + /* RoCEv1 flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT_RX \ + UINT32_C(0xa000) + /* NIC flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_NIC_RX \ + UINT32_C(0xb000) + /* RoCEv2 flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT_RX \ + UINT32_C(0xc000) + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_LAST \ + HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT_RX uint8_t unused_0[6]; /* This value identifies a set of CFA data structures used for a flow. */ uint64_t ext_flow_handle; @@ -45629,27 +47402,67 @@ struct hwrm_cfa_flow_stats_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Flow handle. */ + /* Number of valid flows in this command. */ uint16_t num_flows; - /* Flow handle. */ + /* + * Flow handle. + * For a listing of applicable flow_handle_0 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ uint16_t flow_handle_0; - /* Flow handle. */ + /* + * Flow handle. + * For a listing of applicable flow_handle_1 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ uint16_t flow_handle_1; - /* Flow handle. */ + /* + * Flow handle. + * For a listing of applicable flow_handle_2 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ uint16_t flow_handle_2; - /* Flow handle. */ + /* + * Flow handle. + * For a listing of applicable flow_handle_3 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ uint16_t flow_handle_3; - /* Flow handle. */ + /* + * Flow handle. + * For a listing of applicable flow_handle_4 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ uint16_t flow_handle_4; - /* Flow handle. */ + /* + * Flow handle. + * For a listing of applicable flow_handle_5 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ uint16_t flow_handle_5; - /* Flow handle. */ + /* + * Flow handle. + * For a listing of applicable flow_handle_6 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ uint16_t flow_handle_6; - /* Flow handle. */ + /* + * Flow handle. + * For a listing of applicable flow_handle_7 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ uint16_t flow_handle_7; - /* Flow handle. */ + /* + * Flow handle. + * For a listing of applicable flow_handle_8 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ uint16_t flow_handle_8; - /* Flow handle. */ + /* + * Flow handle. + * For a listing of applicable flow_handle_9 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ uint16_t flow_handle_9; uint8_t unused_0[2]; /* Flow ID of a flow. */ @@ -45724,7 +47537,16 @@ struct hwrm_cfa_flow_stats_output { uint64_t byte_8; /* byte_9 is 64 b */ uint64_t byte_9; - uint8_t unused_0[7]; + /* + * If a flow has been hit, the bit representing the flow will be 1. + * Likewise, if a flow has not, the bit representing the flow + * will be 0. Mapping will match flow numbers where bitX is for flowX + * (ex: bit 0 is flow0). This only applies for NIC flows. Upon + * reading of the flow, the bit will be cleared for the flow and only + * set again when traffic is received by the flow. + */ + uint16_t flow_hits; + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -46498,27 +48320,36 @@ struct hwrm_cfa_pair_alloc_input { * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow). */ uint16_t pair_mode; - /* Pair between VF on local host with PF or VF on specified host. */ + /* + * Pair between VF on local host with PF or VF on specified host. + * (deprecated) + */ #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN \ UINT32_C(0x0) - /* Pair between REP on local host with PF or VF on specified host. */ + /* + * Pair between REP on local host with PF or VF on specified host. + * (deprecated) + */ #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN \ UINT32_C(0x1) - /* Pair between REP on local host with REP on specified host. */ + /* + * Pair between REP on local host with REP on specified host. + * (deprecated) + */ #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP \ UINT32_C(0x2) - /* Pair for the proxy interface. */ + /* Pair for the proxy interface. (deprecated) */ #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY \ UINT32_C(0x3) - /* Pair for the PF interface. */ + /* Pair for the PF interface. (deprecated) */ #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR \ UINT32_C(0x4) - /* Modify existing rep2fn pair and move pair to new PF. */ + /* Modify existing rep2fn pair and move pair to new PF. (deprecated) */ #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD \ UINT32_C(0x5) /* * Modify existing rep2fn pairs paired with same PF and move pairs - * to new PF. + * to new PF. (deprecated) */ #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL \ UINT32_C(0x6) @@ -46672,21 +48503,30 @@ struct hwrm_cfa_pair_free_input { * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow). */ uint16_t pair_mode; - /* Pair between VF on local host with PF or VF on specified host. */ + /* + * Pair between VF on local host with PF or VF on specified host. + * (deprecated) + */ #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0) - /* Pair between REP on local host with PF or VF on specified host. */ + /* + * Pair between REP on local host with PF or VF on specified host. + * (deprecated) + */ #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1) - /* Pair between REP on local host with REP on specified host. */ + /* + * Pair between REP on local host with REP on specified host. + * (deprecated) + */ #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2) - /* Pair for the proxy interface. */ + /* Pair for the proxy interface. (deprecated) */ #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PROXY UINT32_C(0x3) - /* Pair for the PF interface. */ + /* Pair for the PF interface. (deprecated) */ #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4) - /* Modify existing rep2fn pair and move pair to new PF. */ + /* Modify existing rep2fn pair and move pair to new PF. (deprecated) */ #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5) /* * Modify existing rep2fn pairs paired with same PF and move pairs - * to new PF. + * to new PF. (deprecated) */ #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6) /* @@ -46808,15 +48648,24 @@ struct hwrm_cfa_pair_info_output { uint16_t tx_cfa_action_b; /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */ uint8_t pair_mode; - /* Pair between VF on local host with PF or VF on specified host. */ + /* + * Pair between VF on local host with PF or VF on specified host. + * (deprecated) + */ #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0) - /* Pair between REP on local host with PF or VF on specified host. */ + /* + * Pair between REP on local host with PF or VF on specified host. + * (deprecated) + */ #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1) - /* Pair between REP on local host with REP on specified host. */ + /* + * Pair between REP on local host with REP on specified host. + * (deprecated) + */ #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2) - /* Pair for the proxy interface. */ + /* Pair for the proxy interface. (deprecated) */ #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3) - /* Pair for the PF interface. */ + /* Pair for the PF interface. (deprecated) */ #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4) #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \ HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR @@ -47084,6 +48933,9 @@ struct hwrm_cfa_redirect_query_tunnel_type_output { */ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \ UINT32_C(0x2000) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE \ + UINT32_C(0x4000) uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output @@ -48272,7 +50124,7 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output { * Value of 1 to indicate firmware support flow batch delete * operation through HWRM_CFA_FLOW_FLUSH command. * Value of 0 to indicate that the firmware does not support flow - * batch delete operation. + * batch delete operation. (deprecated) */ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \ UINT32_C(0x4) @@ -48280,7 +50132,7 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output { * Value of 1 to indicate that the firmware support flow reset all * operation through HWRM_CFA_FLOW_FLUSH command. * Value of 0 indicates firmware does not support flow reset all - * operation. + * operation. (deprecated) */ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \ UINT32_C(0x8) @@ -48295,12 +50147,14 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output { /* * Value of 1 to indicate that firmware supports TX EEM flows. * Value of 0 indicates firmware does not support TX EEM flows. + * (deprecated) */ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \ UINT32_C(0x20) /* * Value of 1 to indicate that firmware supports RX EEM flows. * Value of 0 indicates firmware does not support RX EEM flows. + * (deprecated) */ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \ UINT32_C(0x40) @@ -48309,6 +50163,7 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output { * allocation of an on-chip flow counter which can be used for EEM * flows. Value of 0 indicates firmware does not support the dynamic * allocation of an on-chip flow counter. + * (deprecated) */ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \ UINT32_C(0x80) @@ -48390,6 +50245,19 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output { */ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED \ UINT32_C(0x40000) + /* + * If set to 1, firmware is capable returning stats for nic flows + * in cfa_flow_stats command where flow_handle value 0xF000. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NIC_FLOW_STATS_SUPPORTED \ + UINT32_C(0x80000) + /* + * If set to 1, firmware is capable of supporting these additional + * ip_protoccols: ICMP, ICMPV6, RSVD for ntuple rules. By default, + * this flag should be 0 for older version of firmware. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_EXT_IP_PROTO_SUPPORTED \ + UINT32_C(0x100000) uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output @@ -50172,7 +52040,7 @@ struct hwrm_tf_tbl_type_get_input { uint32_t index; } __rte_packed; -/* hwrm_tf_tbl_type_get_output (size:1216b/152B) */ +/* hwrm_tf_tbl_type_get_output (size:2240b/280B) */ struct hwrm_tf_tbl_type_get_output { /* The specific error status for the command. */ uint16_t error_code; @@ -50189,7 +52057,7 @@ struct hwrm_tf_tbl_type_get_output { /* unused */ uint16_t unused0; /* Response data. */ - uint8_t data[128]; + uint8_t data[256]; /* unused */ uint8_t unused1[7]; /* @@ -50250,6 +52118,8 @@ struct hwrm_tf_tbl_type_set_input { #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX + /* Indicate table data is being sent via DMA. */ + #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DMA UINT32_C(0x2) /* unused. */ uint8_t unused0[2]; /* @@ -52298,133 +54168,2494 @@ struct hwrm_tf_if_tbl_set_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ - uint32_t fw_session_id; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX + /* unused. */ + uint8_t unused0[2]; + /* + * Type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Index of the type to set. */ + uint32_t index; + /* Size of the data to set. */ + uint16_t size; + /* unused */ + uint8_t unused1[6]; + /* Data to be set. */ + uint8_t data[88]; +} __rte_packed; + +/* hwrm_tf_if_tbl_set_output (size:128b/16B) */ +struct hwrm_tf_if_tbl_set_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/***************************** + * hwrm_tf_tbl_type_bulk_get * + *****************************/ + + +/* hwrm_tf_tbl_type_bulk_get_input (size:384b/48B) */ +struct hwrm_tf_tbl_type_bulk_get_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR \ + UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX + /* + * When set use the special access register access to clear + * the table entries on read. + */ + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ \ + UINT32_C(0x2) + /* unused. */ + uint8_t unused0[2]; + /* + * Type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Starting index of the type to retrieve. */ + uint32_t start_index; + /* Number of entries to retrieve. */ + uint32_t num_entries; + /* Number of entries to retrieve. */ + uint32_t unused1; + /* Host memory where data will be stored. */ + uint64_t host_addr; +} __rte_packed; + +/* hwrm_tf_tbl_type_bulk_get_output (size:128b/16B) */ +struct hwrm_tf_tbl_type_bulk_get_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Response code. */ + uint32_t resp_code; + /* Response size. */ + uint16_t size; + /* unused */ + uint8_t unused0; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************************** + * hwrm_tf_session_hotup_state_set * + ***********************************/ + + +/* hwrm_tf_session_hotup_state_set_input (size:192b/24B) */ +struct hwrm_tf_session_hotup_state_set_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Shared session state. */ + uint16_t state; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR \ + UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) + #define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_TX +} __rte_packed; + +/* hwrm_tf_session_hotup_state_set_output (size:128b/16B) */ +struct hwrm_tf_session_hotup_state_set_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************************** + * hwrm_tf_session_hotup_state_get * + ***********************************/ + + +/* hwrm_tf_session_hotup_state_get_input (size:192b/24B) */ +struct hwrm_tf_session_hotup_state_get_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR \ + UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) + #define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_TX + /* unused. */ + uint8_t unused0[2]; +} __rte_packed; + +/* hwrm_tf_session_hotup_state_get_output (size:128b/16B) */ +struct hwrm_tf_session_hotup_state_get_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Shared session HA state. */ + uint16_t state; + /* Shared session HA reference count. */ + uint16_t ref_cnt; + /* unused. */ + uint8_t unused0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/**************************** + * hwrm_tfc_tbl_scope_qcaps * + ****************************/ + + +/* + * TruFlow command to check if firmware is capable of + * supporting table scopes. + */ +/* hwrm_tfc_tbl_scope_qcaps_input (size:128b/16B) */ +struct hwrm_tfc_tbl_scope_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} __rte_packed; + +/* hwrm_tfc_tbl_scope_qcaps_output (size:192b/24B) */ +struct hwrm_tfc_tbl_scope_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * The maximum number of lookup records that a table scope can support. + * This field is only valid if tbl_scope_capable is not zero. + */ + uint32_t max_lkup_rec_cnt; + /* + * The maximum number of action records that a table scope can support. + * This field is only valid if tbl_scope_capable is not zero. + */ + uint32_t max_act_rec_cnt; + /* Not zero if firmware capable of table scopes. */ + uint8_t tbl_scope_capable; + /* + * log2 of the number of lookup static buckets that a table scope can + * support. This field is only valid if tbl_scope_capable is not zero. + */ + uint8_t max_lkup_static_buckets_exp; + /* unused. */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************************* + * hwrm_tfc_tbl_scope_id_alloc * + *******************************/ + + +/* + * TruFlow command to allocate a table scope ID and create the pools. + * + * There is no corresponding free command since a table scope + * ID will automatically be freed once the last FID is removed. + * That is, when the hwrm_tfc_tbl_scope_fid_rem command returns + * a fid_cnt of 0 that also means that the table scope ID has + * been freed. + */ +/* hwrm_tfc_tbl_scope_id_alloc_input (size:192b/24B) */ +struct hwrm_tfc_tbl_scope_id_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* The maximum number of pools for this table scope. */ + uint16_t max_pools; + /* Non-zero if this table scope is shared. */ + uint8_t shared; + /* + * The size of the lookup pools per direction expressed as + * log2(max_records/max_pools). That is, size=2^exp. + * + * Array is indexed by enum cfa_dir. + */ + uint8_t lkup_pool_sz_exp[2]; + /* + * The size of the action pools per direction expressed as + * log2(max_records/max_pools). That is, size=2^exp. + * + * Array is indexed by enum cfa_dir. + */ + uint8_t act_pool_sz_exp[2]; + /* unused. */ + uint8_t unused0; +} __rte_packed; + +/* hwrm_tfc_tbl_scope_id_alloc_output (size:128b/16B) */ +struct hwrm_tfc_tbl_scope_id_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* The table scope ID that was allocated. */ + uint8_t tsid; + /* + * Non-zero if this is the first FID associated with this table scope + * ID. + */ + uint8_t first; + /* unused. */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/***************************** + * hwrm_tfc_tbl_scope_config * + *****************************/ + + +/* TruFlow command to configure the table scope memory. */ +/* hwrm_tfc_tbl_scope_config_input (size:704b/88B) */ +struct hwrm_tfc_tbl_scope_config_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * The base addresses for lookup memory. + * Array is indexed by enum cfa_dir. + */ + uint64_t lkup_base_addr[2]; + /* + * The base addresses for action memory. + * Array is indexed by enum cfa_dir. + */ + uint64_t act_base_addr[2]; + /* + * The number of minimum sized lkup records per direction. + * In this usage, records are the minimum lookup memory + * allocation unit in a table scope. This value is the total + * memory required for buckets and entries. + * + * Array is indexed by enum cfa_dir. + */ + uint32_t lkup_rec_cnt[2]; + /* + * The number of minimum sized action records per direction. + * Similar to the lkup_rec_cnt, records are the minimum + * action memory allocation unit in a table scope. + * + * Array is indexed by enum cfa_dir. + */ + uint32_t act_rec_cnt[2]; + /* + * The number of static lookup buckets in the table scope. + * Array is indexed by enum cfa_dir. + */ + uint32_t lkup_static_bucket_cnt[2]; + /* The page size of the table scope. */ + uint32_t pbl_page_sz; + /* + * The PBL level for lookup memory. + * Array is indexed by enum cfa_dir. + */ + uint8_t lkup_pbl_level[2]; + /* + * The PBL level for action memory. + * Array is indexed by enum cfa_dir. + */ + uint8_t act_pbl_level[2]; + /* The table scope ID. */ + uint8_t tsid; + /* unused. */ + uint8_t unused0[7]; +} __rte_packed; + +/* hwrm_tfc_tbl_scope_config_output (size:128b/16B) */ +struct hwrm_tfc_tbl_scope_config_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************************* + * hwrm_tfc_tbl_scope_deconfig * + *******************************/ + + +/* TruFlow command to deconfigure the table scope memory. */ +/* hwrm_tfc_tbl_scope_deconfig_input (size:192b/24B) */ +struct hwrm_tfc_tbl_scope_deconfig_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* The table scope ID. */ + uint8_t tsid; + /* unused. */ + uint8_t unused0[7]; +} __rte_packed; + +/* hwrm_tfc_tbl_scope_deconfig_output (size:128b/16B) */ +struct hwrm_tfc_tbl_scope_deconfig_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************************** + * hwrm_tfc_tbl_scope_fid_add * + ******************************/ + + +/* TruFlow command to add a FID to a table scope. */ +/* hwrm_tfc_tbl_scope_fid_add_input (size:192b/24B) */ +struct hwrm_tfc_tbl_scope_fid_add_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* The table scope ID. */ + uint8_t tsid; + /* unused. */ + uint8_t unused0[7]; +} __rte_packed; + +/* hwrm_tfc_tbl_scope_fid_add_output (size:128b/16B) */ +struct hwrm_tfc_tbl_scope_fid_add_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* The number of FIDs currently in the table scope ID. */ + uint8_t fid_cnt; + /* unused. */ + uint8_t unused0[6]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************************** + * hwrm_tfc_tbl_scope_fid_rem * + ******************************/ + + +/* TruFlow command to remove a FID from a table scope. */ +/* hwrm_tfc_tbl_scope_fid_rem_input (size:192b/24B) */ +struct hwrm_tfc_tbl_scope_fid_rem_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* The table scope ID. */ + uint8_t tsid; + /* unused. */ + uint8_t unused0[7]; +} __rte_packed; + +/* hwrm_tfc_tbl_scope_fid_rem_output (size:128b/16B) */ +struct hwrm_tfc_tbl_scope_fid_rem_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* The number of FIDs remaining in the table scope ID. */ + uint16_t fid_cnt; + /* unused. */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************************* + * hwrm_tfc_tbl_scope_pool_alloc * + *********************************/ + + +/* hwrm_tfc_tbl_scope_pool_alloc_input (size:192b/24B) */ +struct hwrm_tfc_tbl_scope_pool_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Table Scope ID */ + uint8_t tsid; + /* Control flags. Direction and type. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR \ + UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) + #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR_LAST \ + HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR_TX + /* Indicates the table type. */ + #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE \ + UINT32_C(0x2) + /* Lookup table */ + #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE_LOOKUP \ + (UINT32_C(0x0) << 1) + /* Action table */ + #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE_ACTION \ + (UINT32_C(0x1) << 1) + #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE_LAST \ + HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE_ACTION + /* Unused */ + uint8_t unused[6]; +} __rte_packed; + +/* hwrm_tfc_tbl_scope_pool_alloc_output (size:128b/16B) */ +struct hwrm_tfc_tbl_scope_pool_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Pool ID */ + uint16_t pool_id; + /* Pool size exponent. An exponent of 0 indicates a failure. */ + uint8_t pool_sz_exp; + /* unused. */ + uint8_t unused1[4]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************************** + * hwrm_tfc_tbl_scope_pool_free * + ********************************/ + + +/* hwrm_tfc_tbl_scope_pool_free_input (size:192b/24B) */ +struct hwrm_tfc_tbl_scope_pool_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Table Scope ID */ + uint8_t tsid; + /* Control flags. Direction and type. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR \ + UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) + #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR_LAST \ + HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR_TX + /* Indicates the table type. */ + #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE \ + UINT32_C(0x2) + /* Lookup table */ + #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE_LOOKUP \ + (UINT32_C(0x0) << 1) + /* Action table */ + #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE_ACTION \ + (UINT32_C(0x1) << 1) + #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE_LAST \ + HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE_ACTION + /* Pool ID */ + uint16_t pool_id; + /* Unused */ + uint8_t unused[4]; +} __rte_packed; + +/* hwrm_tfc_tbl_scope_pool_free_output (size:128b/16B) */ +struct hwrm_tfc_tbl_scope_pool_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/***************************** + * hwrm_tfc_session_id_alloc * + *****************************/ + + +/* + * Allocate a TFC session. Requests the firmware to allocate a TFC + * session identifier and associate a forwarding function with the + * session. Though there's not an explicit matching free for a session + * id alloc, dis-associating the last fid from a session id (fid_cnt goes + * to 0), will result in this session id being freed automatically. + */ +/* hwrm_tfc_session_id_alloc_input (size:128b/16B) */ +struct hwrm_tfc_session_id_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} __rte_packed; + +/* hwrm_tfc_session_id_alloc_output (size:128b/16B) */ +struct hwrm_tfc_session_id_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Unique session identifier for the session created by the + * firmware. + */ + uint16_t sid; + /* Unused field */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/**************************** + * hwrm_tfc_session_fid_add * + ****************************/ + + +/* + * Associate a TFC session id with a forwarding function. The target_fid + * will be associated with the passed in sid. + */ +/* hwrm_tfc_session_fid_add_input (size:192b/24B) */ +struct hwrm_tfc_session_fid_add_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Unique session identifier for the session created by the + * firmware. + */ + uint16_t sid; + /* Unused field */ + uint8_t unused0[6]; +} __rte_packed; + +/* hwrm_tfc_session_fid_add_output (size:128b/16B) */ +struct hwrm_tfc_session_fid_add_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* The number of FIDs that share this session. */ + uint16_t fid_cnt; + /* Unused field */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/**************************** + * hwrm_tfc_session_fid_rem * + ****************************/ + + +/* + * Dis-associate a TFC session from the target_fid. + * Though there's not an explicit matching free for a + * session id alloc, dis-associating the last fid from a session id + * (fid_cnt goes to 0), will result in this session id being freed + * automatically. + */ +/* hwrm_tfc_session_fid_rem_input (size:192b/24B) */ +struct hwrm_tfc_session_fid_rem_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Unique session identifier for the session created by the + * firmware. + */ + uint16_t sid; + /* Unused field */ + uint8_t unused0[6]; +} __rte_packed; + +/* hwrm_tfc_session_fid_rem_output (size:128b/16B) */ +struct hwrm_tfc_session_fid_rem_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* The number of FIDs that share this session. */ + uint16_t fid_cnt; + /* Unused field */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/************************ + * hwrm_tfc_ident_alloc * + ************************/ + + +/* + * Allocate a TFC identifier. Requests the firmware to + * allocate a TFC identifier. The session id and track_type are passed + * in. The tracking_id is either the sid or target_fid depends on the + * track_type. The resource subtype is passed in, an id corresponding + * to all these is allocated and returned in the HWRM response. + */ +/* hwrm_tfc_ident_alloc_input (size:192b/24B) */ +struct hwrm_tfc_ident_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Unique session identifier for the session created by the + * firmware. Will be used to track this identifier. + */ + uint16_t sid; + /* Control flags. Direction. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_LAST \ + HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_TX + /* + * CFA resource subtype. For definitions, please see + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* Describes the type of tracking tag to be used */ + uint8_t track_type; + /* Invalid track type */ + #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID \ + UINT32_C(0x0) + /* Tracked by session id */ + #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID \ + UINT32_C(0x1) + /* Tracked by function id */ + #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID \ + UINT32_C(0x2) + #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_LAST \ + HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID + /* Unused field */ + uint8_t unused0[3]; +} __rte_packed; + +/* hwrm_tfc_ident_alloc_output (size:128b/16B) */ +struct hwrm_tfc_ident_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Resource identifier allocated by the firmware using + * parameters above. + */ + uint16_t ident_id; + /* Unused field */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************** + * hwrm_tfc_ident_free * + ***********************/ + + +/* + * Requests the firmware to free a TFC resource identifier. + * A resource subtype and session id are passed in. + * An identifier (previously allocated) corresponding to all these is + * freed, only after various sanity checks are completed. + */ +/* hwrm_tfc_ident_free_input (size:192b/24B) */ +struct hwrm_tfc_ident_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Unique session identifier for the session created by the + * firmware. Will be used to validate this request. + */ + uint16_t sid; + /* + * CFA resource subtype. For definitions, please see + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* Control flags. Direction. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_LAST \ + HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_TX + /* The resource identifier to be freed */ + uint16_t ident_id; + /* Reserved */ + uint8_t unused0[2]; +} __rte_packed; + +/* hwrm_tfc_ident_free_output (size:128b/16B) */ +struct hwrm_tfc_ident_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Reserved */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_tfc_idx_tbl_alloc * + **************************/ + + +/* hwrm_tfc_idx_tbl_alloc_input (size:192b/24B) */ +struct hwrm_tfc_idx_tbl_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Unique session id for the session created by the + * firmware. Will be used to track this index table entry + * only if track type is track_type_sid. + */ + uint16_t sid; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_LAST \ + HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_TX + /* + * CFA resource subtype. For definitions, please see + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* Describes the type of tracking id to be used */ + uint8_t track_type; + /* Invalid track type */ + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID \ + UINT32_C(0x0) + /* Tracked by session id */ + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID \ + UINT32_C(0x1) + /* Tracked by function id */ + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID \ + UINT32_C(0x2) + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_LAST \ + HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID + /* Reserved */ + uint8_t unused0[3]; +} __rte_packed; + +/* hwrm_tfc_idx_tbl_alloc_output (size:128b/16B) */ +struct hwrm_tfc_idx_tbl_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Index table entry allocated by the firmware using the + * parameters above. + */ + uint16_t idx_tbl_id; + /* Reserved */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************************** + * hwrm_tfc_idx_tbl_alloc_set * + ******************************/ + + +/* hwrm_tfc_idx_tbl_alloc_set_input (size:1088b/136B) */ +struct hwrm_tfc_idx_tbl_alloc_set_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Unique session id for the session created by the + * firmware. Will be used to track this index table entry + * only if track type is track_type_sid. + */ + uint16_t sid; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_TX + /* + * Indicate device data is being sent via DMA, the device + * data packing does not change. + */ + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DMA UINT32_C(0x2) + /* + * CFA resource subtype. For definitions, please see + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* Describes the type of tracking id to be used */ + uint8_t track_type; + /* Invalid track type */ + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID \ + UINT32_C(0x0) + /* Tracked by session id */ + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_SID \ + UINT32_C(0x1) + /* Tracked by function id */ + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID \ + UINT32_C(0x2) + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_LAST \ + HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID + /* Reserved */ + uint8_t unused0; + /* The size of the index table entry in bytes. */ + uint16_t data_size; + /* The location of the dma buffer */ + uint64_t dma_addr; + /* + * Index table data located at offset 0. If dma bit is set, + * then this field contains the DMA buffer pointer. + */ + uint8_t dev_data[104]; +} __rte_packed; + +/* hwrm_tfc_idx_tbl_alloc_set_output (size:128b/16B) */ +struct hwrm_tfc_idx_tbl_alloc_set_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Index table entry allocated by the firmware using the + * parameters above. + */ + uint16_t idx_tbl_id; + /* Reserved */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************ + * hwrm_tfc_idx_tbl_set * + ************************/ + + +/* hwrm_tfc_idx_tbl_set_input (size:1088b/136B) */ +struct hwrm_tfc_idx_tbl_set_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_TX + /* + * Indicate device data is being sent via DMA, the device + * data packing does not change. + */ + #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DMA UINT32_C(0x2) + /* + * CFA resource subtype. For definitions, please see + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* + * Session id associated with the firmware. Will be used + * for validation if the track type matches. + */ + uint16_t sid; + /* + * Index table index returned during alloc by the + * firmware. + */ + uint16_t idx_tbl_id; + /* The size of the index table entry in bytes. */ + uint16_t data_size; + /* The location of the dma buffer */ + uint64_t dma_addr; + /* + * Index table data located at offset 0. If dma bit is set, + * then this field contains the DMA buffer pointer. + */ + uint8_t dev_data[104]; +} __rte_packed; + +/* hwrm_tfc_idx_tbl_set_output (size:128b/16B) */ +struct hwrm_tfc_idx_tbl_set_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************ + * hwrm_tfc_idx_tbl_get * + ************************/ + + +/* hwrm_tfc_idx_tbl_get_input (size:256b/32B) */ +struct hwrm_tfc_idx_tbl_get_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR \ + UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) + #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_LAST \ + HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_TX + /* + * When set use the special access register access to clear + * the table entry on read. + */ + #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_CLEAR_ON_READ \ + UINT32_C(0x2) + /* + * CFA resource subtype. For definitions, please see + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* + * Session id associated with the firmware. Will be used + * for validation if the track type matches. + */ + uint16_t sid; + /* + * Index table index returned during alloc by the + * firmware. + */ + uint16_t idx_tbl_id; + /* The size of the index table entry buffer in bytes. */ + uint16_t buffer_size; + /* The location of the response dma buffer */ + uint64_t dma_addr; +} __rte_packed; + +/* hwrm_tfc_idx_tbl_get_output (size:128b/16B) */ +struct hwrm_tfc_idx_tbl_get_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* The size of the index table buffer returned in device size bytes. */ + uint16_t data_size; + /* unused */ + uint8_t unused1[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_tfc_idx_tbl_free * + *************************/ + + +/* hwrm_tfc_idx_tbl_free_input (size:192b/24B) */ +struct hwrm_tfc_idx_tbl_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_LAST \ + HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_TX + /* + * CFA resource subtype. For definitions, please see + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* + * Session id associated with the firmware. Will be used + * for validation if the track type matches. + */ + uint16_t sid; + /* Index table id to be freed by the firmware. */ + uint16_t idx_tbl_id; + /* Reserved */ + uint8_t unused0[2]; +} __rte_packed; + +/* hwrm_tfc_idx_tbl_free_output (size:128b/16B) */ +struct hwrm_tfc_idx_tbl_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Reserved */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/* TruFlow resources request for a global id. */ +/* tfc_global_id_hwrm_req (size:64b/8B) */ +struct tfc_global_id_hwrm_req { + /* Type of the resource, defined in enum cfa_resource_type HCAPI RM. */ + uint16_t rtype; + /* Indicates the flow direction in type of cfa_dir. */ + uint16_t dir; + /* Subtype of the resource type. */ + uint16_t subtype; + /* Number of the type of resources. */ + uint16_t cnt; +} __rte_packed; + +/* The reserved resources for the global id. */ +/* tfc_global_id_hwrm_rsp (size:64b/8B) */ +struct tfc_global_id_hwrm_rsp { + /* Type of the resource, defined in enum cfa_resource_type HCAPI RM. */ + uint16_t rtype; + /* Indicates the flow direction in type of cfa_dir. */ + uint16_t dir; + /* Subtype of the resource type. */ + uint16_t subtype; + /* The global id that the resources reserved for. */ + uint16_t id; +} __rte_packed; + +/**************************** + * hwrm_tfc_global_id_alloc * + ****************************/ + + +/* hwrm_tfc_global_id_alloc_input (size:320b/40B) */ +struct hwrm_tfc_global_id_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint16_t sid; + /* Global domain id. */ + uint16_t global_id; + /* + * Defines the array size of the provided req_addr and + * resv_addr array buffers. Should be set to the number of + * request entries. + */ + uint16_t req_cnt; + /* unused. */ + uint8_t unused0[2]; + /* + * This is the DMA address for the request input data array + * buffer. Array is of tfc_global_id_hwrm_req type. Size of the + * array buffer is provided by the 'req_cnt' field in this + * message. + */ + uint64_t req_addr; + /* + * This is the DMA address for the resc output data array + * buffer. Array is of tfc_global_id_hwrm_rsp type. Size of the array + * buffer is provided by the 'req_cnt' field in this + * message. + */ + uint64_t resc_addr; +} __rte_packed; + +/* hwrm_tfc_global_id_alloc_output (size:128b/16B) */ +struct hwrm_tfc_global_id_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Size of the returned hwrm_tfc_global_id_req data array. The value + * cannot exceed the req_cnt defined by the input msg. The data + * array is returned using the resv_addr specified DMA + * address also provided by the input msg. + */ + uint16_t rsp_cnt; + /* Non-zero if this is the first allocation for the global ID. */ + uint8_t first; + /* unused. */ + uint8_t unused0[4]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************* + * hwrm_tfc_tcam_set * + *********************/ + + +/* hwrm_tfc_tcam_set_input (size:1088b/136B) */ +struct hwrm_tfc_tcam_set_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Session id associated with the firmware. Will be used + * for validation if the track type matches. + */ + uint16_t sid; + /* Logical TCAM ID. */ + uint16_t tcam_id; + /* Number of bytes in the TCAM key. */ + uint16_t key_size; + /* Number of bytes in the TCAM result. */ + uint16_t result_size; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_TX + /* Indicate device data is being sent via DMA. */ + #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2) + /* + * Subtype of TCAM resource. See + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* unused. */ + uint8_t unused0[6]; + /* The location of the response dma buffer */ + uint64_t dma_addr; + /* + * TCAM key located at offset 0, mask located at mask_offset + * and result at result_offset for the device. + */ + uint8_t dev_data[96]; +} __rte_packed; + +/* hwrm_tfc_tcam_set_output (size:128b/16B) */ +struct hwrm_tfc_tcam_set_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************* + * hwrm_tfc_tcam_get * + *********************/ + + +/* hwrm_tfc_tcam_get_input (size:192b/24B) */ +struct hwrm_tfc_tcam_get_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_LAST \ + HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_TX + /* + * Subtype of TCAM resource See + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* + * Session id associated with the firmware. Will be used + * for validation if the track type matches. + */ + uint16_t sid; + /* Logical TCAM ID. */ + uint16_t tcam_id; + /* unused. */ + uint8_t unused0[2]; +} __rte_packed; + +/* hwrm_tfc_tcam_get_output (size:2368b/296B) */ +struct hwrm_tfc_tcam_get_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Number of bytes in the TCAM key. */ + uint16_t key_size; + /* Number of bytes in the TCAM result. */ + uint16_t result_size; + /* unused. */ + uint8_t unused0[4]; + /* + * TCAM key located at offset 0, mask located at key_size + * and result at 2 * key_size for the device. + */ + uint8_t dev_data[272]; + /* unused. */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************** + * hwrm_tfc_tcam_alloc * + ***********************/ + + +/* hwrm_tfc_tcam_alloc_input (size:256b/32B) */ +struct hwrm_tfc_tcam_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_LAST \ + HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_TX + /* + * Subtype of TCAM resource. See + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* + * Unique session id for the session created by the + * firmware. Will be used to track this index table entry + * only if track type is track_type_sid. + */ + uint16_t sid; + /* Number of bytes in the TCAM key. */ + uint16_t key_size; + /* Entry priority. */ + uint16_t priority; + /* Describes the type of tracking id to be used */ + uint8_t track_type; + /* Invalid track type */ + #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID \ + UINT32_C(0x0) + /* Tracked by session id */ + #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID \ + UINT32_C(0x1) + /* Tracked by function id */ + #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID \ + UINT32_C(0x2) + #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_LAST \ + HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID + /* Unused. */ + uint8_t unused0[7]; +} __rte_packed; + +/* hwrm_tfc_tcam_alloc_output (size:128b/16B) */ +struct hwrm_tfc_tcam_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Index table entry allocated by the firmware using the + * parameters above. + */ + uint16_t idx; + /* Reserved */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/*************************** + * hwrm_tfc_tcam_alloc_set * + ***************************/ + + +/* hwrm_tfc_tcam_alloc_set_input (size:1088b/136B) */ +struct hwrm_tfc_tcam_alloc_set_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_TX + /* Indicate device data is being sent via DMA. */ + #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DMA UINT32_C(0x2) + /* + * Subtype of TCAM resource. See + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* + * Unique session id for the session created by the + * firmware. Will be used to track this index table entry + * only if track type is track_type_sid. + */ + uint16_t sid; + /* Number of bytes in the TCAM key. */ + uint16_t key_size; + /* The size of the TCAM table entry in bytes. */ + uint16_t result_size; + /* Entry priority. */ + uint16_t priority; + /* Describes the type of tracking id to be used */ + uint8_t track_type; + /* Invalid track type */ + #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID \ + UINT32_C(0x0) + /* Tracked by session id */ + #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_SID \ + UINT32_C(0x1) + /* Tracked by function id */ + #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID \ + UINT32_C(0x2) + #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_LAST \ + HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID + /* Unused */ + uint8_t unused[5]; + /* The location of the response dma buffer */ + uint64_t dma_addr; + /* + * Index table data located at offset 0. If dma bit is set, + * then this field contains the DMA buffer pointer. + */ + uint8_t dev_data[96]; +} __rte_packed; + +/* hwrm_tfc_tcam_alloc_set_output (size:128b/16B) */ +struct hwrm_tfc_tcam_alloc_set_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Logical TCAM ID. */ + uint16_t tcam_id; + /* Reserved */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************** + * hwrm_tfc_tcam_free * + **********************/ + + +/* hwrm_tfc_tcam_free_input (size:192b/24B) */ +struct hwrm_tfc_tcam_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; /* Control flags. */ - uint16_t flags; + uint8_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \ - HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX - /* unused. */ - uint8_t unused0[2]; - /* - * Type of the resource, defined globally in the - * hwrm_tf_resc_type enum. - */ - uint32_t type; - /* Index of the type to set. */ - uint32_t index; - /* Size of the data to set. */ - uint16_t size; - /* unused */ - uint8_t unused1[6]; - /* Data to be set. */ - uint8_t data[88]; -} __rte_packed; - -/* hwrm_tf_if_tbl_set_output (size:128b/16B) */ -struct hwrm_tf_if_tbl_set_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* unused. */ - uint8_t unused0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field - * is written last. - */ - uint8_t valid; -} __rte_packed; - -/***************************** - * hwrm_tf_tbl_type_bulk_get * - *****************************/ - - -/* hwrm_tf_tbl_type_bulk_get_input (size:384b/48B) */ -struct hwrm_tf_tbl_type_bulk_get_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_LAST \ + HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_TX /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * Subtype of TCAM resource. See + * cfa_v3/include/cfa_resources.h. */ - uint16_t cmpl_ring; + uint8_t subtype; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * Session id associated with the firmware. Will be used + * for validation if the track type matches. */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ - uint32_t fw_session_id; - /* Control flags. */ - uint16_t flags; - /* Indicates the flow direction. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR \ - UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX \ - UINT32_C(0x0) - /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX \ - UINT32_C(0x1) - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \ - HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX - /* - * When set use the special access register access to clear - * the table entries on read. - */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ \ - UINT32_C(0x2) - /* unused. */ + uint16_t sid; + /* Logical TCAM ID. */ + uint16_t tcam_id; + /* Reserved */ uint8_t unused0[2]; - /* - * Type of the resource, defined globally in the - * hwrm_tf_resc_type enum. - */ - uint32_t type; - /* Starting index of the type to retrieve. */ - uint32_t start_index; - /* Number of entries to retrieve. */ - uint32_t num_entries; - /* Number of entries to retrieve. */ - uint32_t unused1; - /* Host memory where data will be stored. */ - uint64_t host_addr; } __rte_packed; -/* hwrm_tf_tbl_type_bulk_get_output (size:128b/16B) */ -struct hwrm_tf_tbl_type_bulk_get_output { +/* hwrm_tfc_tcam_free_output (size:128b/16B) */ +struct hwrm_tfc_tcam_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -52433,12 +56664,8 @@ struct hwrm_tf_tbl_type_bulk_get_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Response code. */ - uint32_t resp_code; - /* Response size. */ - uint16_t size; - /* unused */ - uint8_t unused0; + /* Reserved */ + uint8_t unused0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -52505,8 +56732,20 @@ struct hwrm_tunnel_dst_port_query_input { /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) + /* Custom GRE uses UPAR to parse customized GRE packets */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_CUSTOM_GRE \ + UINT32_C(0xd) + /* Enhanced Common Packet Radio Interface (eCPRI) */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ECPRI \ + UINT32_C(0xe) + /* IPv6 Segment Routing (SRv6) */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_SRV6 \ + UINT32_C(0xf) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE \ + UINT32_C(0x10) #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \ - HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 + HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE uint8_t unused_0[7]; } __rte_packed; @@ -52538,7 +56777,38 @@ struct hwrm_tunnel_dst_port_query_output { * configured. */ uint16_t tunnel_dst_port_val; - uint8_t unused_0[3]; + /* + * This field represents the UPAR usage status. + * Available UPARs on wh+ are UPAR0 and UPAR1 + * Available UPARs on Thor are UPAR0 to UPAR3 + * Available UPARs on Thor2 are UPAR0 to UPAR7 + */ + uint8_t upar_in_use; + /* This bit will be '1' when UPAR0 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR0 \ + UINT32_C(0x1) + /* This bit will be '1' when UPAR1 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR1 \ + UINT32_C(0x2) + /* This bit will be '1' when UPAR2 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR2 \ + UINT32_C(0x4) + /* This bit will be '1' when UPAR3 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR3 \ + UINT32_C(0x8) + /* This bit will be '1' when UPAR4 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR4 \ + UINT32_C(0x10) + /* This bit will be '1' when UPAR5 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR5 \ + UINT32_C(0x20) + /* This bit will be '1' when UPAR6 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR6 \ + UINT32_C(0x40) + /* This bit will be '1' when UPAR7 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR7 \ + UINT32_C(0x80) + uint8_t unused_0[2]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -52604,8 +56874,20 @@ struct hwrm_tunnel_dst_port_alloc_input { /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) + /* Custom GRE uses UPAR to parse customized GRE packets. This is not supported. */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_CUSTOM_GRE \ + UINT32_C(0xd) + /* Enhanced Common Packet Radio Interface (eCPRI) */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ECPRI \ + UINT32_C(0xe) + /* IPv6 Segment Routing (SRv6) */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_SRV6 \ + UINT32_C(0xf) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \ + UINT32_C(0x10) #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \ - HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 + HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE uint8_t unused_0; /* * This field represents the value of L4 destination port used @@ -52636,7 +56918,51 @@ struct hwrm_tunnel_dst_port_alloc_output { * types that has l4 destination port parameters. */ uint16_t tunnel_dst_port_id; - uint8_t unused_0[5]; + /* Error information */ + uint8_t error_info; + /* No error */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_SUCCESS \ + UINT32_C(0x0) + /* Tunnel port is already allocated */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_ALLOCATED \ + UINT32_C(0x1) + /* Out of resources error */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_NO_RESOURCE \ + UINT32_C(0x2) + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_LAST \ + HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_NO_RESOURCE + /* + * This field represents the UPAR usage status. + * Available UPARs on wh+ are UPAR0 and UPAR1 + * Available UPARs on Thor are UPAR0 to UPAR3 + * Available UPARs on Thor2 are UPAR0 to UPAR7 + */ + uint8_t upar_in_use; + /* This bit will be '1' when UPAR0 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR0 \ + UINT32_C(0x1) + /* This bit will be '1' when UPAR1 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR1 \ + UINT32_C(0x2) + /* This bit will be '1' when UPAR2 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR2 \ + UINT32_C(0x4) + /* This bit will be '1' when UPAR3 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR3 \ + UINT32_C(0x8) + /* This bit will be '1' when UPAR4 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR4 \ + UINT32_C(0x10) + /* This bit will be '1' when UPAR5 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR5 \ + UINT32_C(0x20) + /* This bit will be '1' when UPAR6 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR6 \ + UINT32_C(0x40) + /* This bit will be '1' when UPAR7 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR7 \ + UINT32_C(0x80) + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -52702,8 +57028,20 @@ struct hwrm_tunnel_dst_port_free_input { /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) + /* Custom GRE uses UPAR to parse customized GRE packets. This is not supported. */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_CUSTOM_GRE \ + UINT32_C(0xd) + /* Enhanced Common Packet Radio Interface (eCPRI) */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ECPRI \ + UINT32_C(0xe) + /* IPv6 Segment Routing (SRv6) */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_SRV6 \ + UINT32_C(0xf) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE \ + UINT32_C(0x10) #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \ - HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 + HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE uint8_t unused_0; /* * Identifier of a tunnel L4 destination port value. Only applies to tunnel @@ -52723,7 +57061,20 @@ struct hwrm_tunnel_dst_port_free_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_1[7]; + /* Error information */ + uint8_t error_info; + /* No error */ + #define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_SUCCESS \ + UINT32_C(0x0) + /* Not owner error */ + #define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_ERR_NOT_OWNER \ + UINT32_C(0x1) + /* Not allocated error */ + #define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_ERR_NOT_ALLOCATED \ + UINT32_C(0x2) + #define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_LAST \ + HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_ERR_NOT_ALLOCATED + uint8_t unused_1[6]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -53534,6 +57885,185 @@ struct pcie_ctx_hw_stats { uint64_t pcie_recovery_histogram; } __rte_packed; +/**************************** + * hwrm_stat_generic_qstats * + ****************************/ + + +/* hwrm_stat_generic_qstats_input (size:256b/32B) */ +struct hwrm_stat_generic_qstats_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * The size of the generic statistics buffer passed in the + * generic_stat_host_addr in bytes. + * Firmware will not exceed this size when it DMAs the + * statistics structure to the host. The actual DMA size + * will be returned in the response. + */ + uint16_t generic_stat_size; + uint8_t flags; + /* + * The bit should be set to 1 when request is for the counter mask + * representing the width of each of the stats counters, rather + * than counters themselves. + */ + #define HWRM_STAT_GENERIC_QSTATS_INPUT_FLAGS_COUNTER_MASK \ + UINT32_C(0x1) + uint8_t unused_0[5]; + /* + * This is the host address where + * generic statistics will be stored + */ + uint64_t generic_stat_host_addr; +} __rte_packed; + +/* hwrm_stat_generic_qstats_output (size:128b/16B) */ +struct hwrm_stat_generic_qstats_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* The size of Generic Statistics block in bytes. */ + uint16_t generic_stat_size; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/* Generic Statistic Format */ +/* generic_sw_hw_stats (size:1408b/176B) */ +struct generic_sw_hw_stats { + /* + * This is the number of TLP bytes that have been transmitted for + * the caller PF. + */ + uint64_t pcie_statistics_tx_tlp; + /* + * This is the number of TLP bytes that have been received + * for the caller PF. + */ + uint64_t pcie_statistics_rx_tlp; + /* Posted Header Flow Control credits available for the caller PF. */ + uint64_t pcie_credit_fc_hdr_posted; + /* Non-posted Header Flow Control credits available for the caller PF. */ + uint64_t pcie_credit_fc_hdr_nonposted; + /* Completion Header Flow Control credits available for the caller PF. */ + uint64_t pcie_credit_fc_hdr_cmpl; + /* Posted Data Flow Control credits available for the caller PF. */ + uint64_t pcie_credit_fc_data_posted; + /* Non-Posted Data Flow Control credits available for the caller PF. */ + uint64_t pcie_credit_fc_data_nonposted; + /* Completion Data Flow Control credits available for the caller PF. */ + uint64_t pcie_credit_fc_data_cmpl; + /* + * Available Non-posted credit for target flow control reads or + * config for the caller PF. + */ + uint64_t pcie_credit_fc_tgt_nonposted; + /* + * Available posted data credit for target flow control writes + * for the caller PF. + */ + uint64_t pcie_credit_fc_tgt_data_posted; + /* + * Available posted header credit for target flow control writes + * for the caller PF. + */ + uint64_t pcie_credit_fc_tgt_hdr_posted; + /* Available completion flow control header credits for the caller PF. */ + uint64_t pcie_credit_fc_cmpl_hdr_posted; + /* Available completion flow control data credits. */ + uint64_t pcie_credit_fc_cmpl_data_posted; + /* + * Displays Time information of the longest completon time from any of + * the 4 tags for the caller PF. The unit of time recorded is in + * microseconds. + */ + uint64_t pcie_cmpl_longest; + /* + * Displays Time information of the shortest completon time from any of + * the 4 tags for the caller PF. The unit of time recorded is in + * microseconds. + */ + uint64_t pcie_cmpl_shortest; + /* + * This field contains the total number of CFCQ 'misses' observed for + * all the PF's. + */ + uint64_t cache_miss_count_cfcq; + /* + * This field contains the total number of CFCS 'misses' observed for + * all the PF's. + */ + uint64_t cache_miss_count_cfcs; + /* + * This field contains the total number of CFCC 'misses' observed for + * all the PF's. + */ + uint64_t cache_miss_count_cfcc; + /* + * This field contains the total number of CFCM 'misses' observed + * for all the PF's. + */ + uint64_t cache_miss_count_cfcm; + /* + * Total number of Doorbell messages dropped from the DB FIFO. + * This counter is only applicable for devices that support + * the hardware based doorbell drop recovery feature. + */ + uint64_t hw_db_recov_dbs_dropped; + /* + * Total number of doorbell drops serviced. + * This counter is only applicable for devices that support + * the hardware based doorbell drop recovery feature. + */ + uint64_t hw_db_recov_drops_serviced; + /* + * Total number of dropped doorbells recovered. + * This counter is only applicable for devices that support + * the hardware based doorbell drop recovery feature. + */ + uint64_t hw_db_recov_dbs_recovered; +} __rte_packed; + /********************** * hwrm_exec_fwd_resp * **********************/ @@ -55174,8 +59704,11 @@ struct hwrm_nvm_install_update_cmd_err { /* Firmware update failed due to Anti-rollback. */ #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK \ UINT32_C(0x3) + /* Firmware update does not support voltage regulators on the device. */ + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT \ + UINT32_C(0x4) #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \ - HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK + HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT uint8_t unused_0[7]; } __rte_packed; From patchwork Fri Apr 21 18:11:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Randy Schacher X-Patchwork-Id: 126407 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DD1AC429A8; Fri, 21 Apr 2023 20:12:46 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7193A42D29; Fri, 21 Apr 2023 20:12:25 +0200 (CEST) Received: from mail-oa1-f97.google.com (mail-oa1-f97.google.com [209.85.160.97]) by mails.dpdk.org (Postfix) with ESMTP id 66D8A4114B for ; Fri, 21 Apr 2023 20:12:21 +0200 (CEST) Received: by mail-oa1-f97.google.com with SMTP id 586e51a60fabf-1879e28ab04so1792017fac.2 for ; Fri, 21 Apr 2023 11:12:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1682100741; x=1684692741; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zNa0eUmhkIRPxO3txs8W7FlZbmqlZP99uf/rIaj/SNQ=; b=VvX1lOUfO8g8mCV40oRuQsbBLUDRfrtYwcArzO4Yfqd13nKtCApGqDipkGQSzehbKp 3R6Twz3L6GKD0SmbplAb/v19lVd5ePTpnofag5Ti/tUK+nSk8EprKpe6sew3rwQjL3s3 1dWc5UkfXbNNnTcSTlqyl5zpUQ1+iVuMFqpo4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682100741; x=1684692741; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zNa0eUmhkIRPxO3txs8W7FlZbmqlZP99uf/rIaj/SNQ=; b=kzf0upKMK6qUEs9bDC8H3lKBamXTqFrZRMlRKXD8xgNbQ1R0kH8FqbtleCh5aKJ1ef 5plOZJSdRdT9a6ZU9zx6JpGSUKVarb5sFd/1T4UC4PIcmvG9p+omv4mtSd2t9Uz6AIji Et1QbYHoXR1u3eiITpQiWdluaxFFbT9K7ioODMF+x3/nXSVA2QN+yYr8F8xXIVVPOLLN k4N3SOYM/aYgzSn/RJnsp8QmIr9ejlkVNDGkwOJFn4BqAITq68yF/QKl2vwa/VDDHY4P SVPzuDjCCE2MczBHd1DcGCipeTlMUUusekKzma+IvBlnHHm+lu4hFMa7gUslb8Pa0cen e3FA== X-Gm-Message-State: AAQBX9e5T98Setz6iygsHgetXTl9ihR8q0KMz8KLCOLemCdD3fW64nXM vYvOIm90qZ2zofWlKe3TJ10Nw3BmK+Y97auR5vPlGxllNQ22JYFwp9Undug/S7jqS0MUVRpgcgG BdE4n1dKH4aeIuIoEuKblYuDuPXmTSTHiEms6iDKFBeOHGOdcq/jwEyOWG2i32oM6LXccDByROp occcwEfurBqKr0 X-Google-Smtp-Source: AKy350YTGQkgzlfFtzdYZw+VEt8lwl4e8jVxIbZrN9pTvZepIxKoNoOitslWwxVgL82pYhtm9daHzEr6r2qL X-Received: by 2002:a05:6870:b522:b0:180:3225:b33b with SMTP id v34-20020a056870b52200b001803225b33bmr4582926oap.34.1682100740398; Fri, 21 Apr 2023 11:12:20 -0700 (PDT) Received: from r650-k2.dhcp.broadcom.net ([192.19.144.250]) by smtp-relay.gmail.com with ESMTPS id o21-20020a056870e81500b0017eb57c3417sm397528oan.19.2023.04.21.11.12.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Apr 2023 11:12:20 -0700 (PDT) X-Relaying-Domain: broadcom.com From: Randy Schacher To: dev@dpdk.org Cc: Kishore Padmanabha Subject: [PATCH v2 03/11] net/bnxt: update copyright date and cleanup whitespace Date: Fri, 21 Apr 2023 18:11:47 +0000 Message-Id: <20230421181155.2160482-4-stuart.schacher@broadcom.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230421181155.2160482-1-stuart.schacher@broadcom.com> References: <20230421181155.2160482-1-stuart.schacher@broadcom.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Update the Copyright to 2023 Clean up extra blank lines Clean up other whitespace issues Signed-off-by: Randy Schacher Reviewed-by: Kishore Padmanabha --- drivers/net/bnxt/bnxt_cpr.c | 2 +- drivers/net/bnxt/bnxt_cpr.h | 2 +- drivers/net/bnxt/bnxt_filter.c | 2 +- drivers/net/bnxt/bnxt_irq.c | 2 +- drivers/net/bnxt/bnxt_irq.h | 2 +- drivers/net/bnxt/bnxt_nvm_defs.h | 2 +- drivers/net/bnxt/bnxt_reps.h | 2 +- drivers/net/bnxt/bnxt_ring.h | 2 +- drivers/net/bnxt/bnxt_rxq.h | 2 +- drivers/net/bnxt/bnxt_rxr.h | 2 +- drivers/net/bnxt/bnxt_rxtx_vec_avx2.c | 2 +- drivers/net/bnxt/bnxt_rxtx_vec_common.h | 2 +- drivers/net/bnxt/bnxt_rxtx_vec_neon.c | 2 +- drivers/net/bnxt/bnxt_rxtx_vec_sse.c | 2 +- drivers/net/bnxt/bnxt_stats.c | 2 +- drivers/net/bnxt/bnxt_stats.h | 2 +- drivers/net/bnxt/bnxt_txq.h | 2 +- drivers/net/bnxt/bnxt_util.c | 2 +- drivers/net/bnxt/bnxt_util.h | 2 +- drivers/net/bnxt/meson.build | 2 +- drivers/net/bnxt/rte_pmd_bnxt.c | 2 +- drivers/net/bnxt/rte_pmd_bnxt.h | 2 +- drivers/net/bnxt/tf_core/bitalloc.c | 3 +-- drivers/net/bnxt/tf_core/bitalloc.h | 3 +-- drivers/net/bnxt/tf_core/cfa_resource_types.h | 3 +-- drivers/net/bnxt/tf_core/dpool.c | 3 ++- drivers/net/bnxt/tf_core/dpool.h | 3 +-- drivers/net/bnxt/tf_core/ll.c | 2 +- drivers/net/bnxt/tf_core/ll.h | 2 +- drivers/net/bnxt/tf_core/lookup3.h | 1 - drivers/net/bnxt/tf_core/rand.c | 2 +- drivers/net/bnxt/tf_core/rand.h | 3 +-- drivers/net/bnxt/tf_core/stack.c | 2 +- drivers/net/bnxt/tf_core/stack.h | 3 +-- drivers/net/bnxt/tf_core/tf_common.h | 3 +-- drivers/net/bnxt/tf_core/tf_core.h | 1 - drivers/net/bnxt/tf_core/tf_device.h | 1 - drivers/net/bnxt/tf_core/tf_device_p4.h | 3 +-- drivers/net/bnxt/tf_core/tf_device_p58.h | 2 +- drivers/net/bnxt/tf_core/tf_em.h | 3 +-- drivers/net/bnxt/tf_core/tf_em_common.c | 8 +------- drivers/net/bnxt/tf_core/tf_em_common.h | 4 +--- drivers/net/bnxt/tf_core/tf_em_hash_internal.c | 2 +- drivers/net/bnxt/tf_core/tf_em_host.c | 3 +-- drivers/net/bnxt/tf_core/tf_em_internal.c | 3 ++- drivers/net/bnxt/tf_core/tf_ext_flow_handle.h | 4 +--- drivers/net/bnxt/tf_core/tf_global_cfg.c | 2 +- drivers/net/bnxt/tf_core/tf_global_cfg.h | 3 +-- drivers/net/bnxt/tf_core/tf_hash.c | 2 +- drivers/net/bnxt/tf_core/tf_hash.h | 3 +-- drivers/net/bnxt/tf_core/tf_identifier.c | 2 +- drivers/net/bnxt/tf_core/tf_identifier.h | 3 +-- drivers/net/bnxt/tf_core/tf_if_tbl.h | 3 +-- drivers/net/bnxt/tf_core/tf_msg_common.h | 3 +-- drivers/net/bnxt/tf_core/tf_project.h | 3 +-- drivers/net/bnxt/tf_core/tf_resources.h | 3 +-- drivers/net/bnxt/tf_core/tf_rm.h | 6 +----- drivers/net/bnxt/tf_core/tf_session.h | 1 - drivers/net/bnxt/tf_core/tf_sram_mgr.h | 1 - drivers/net/bnxt/tf_core/tf_tbl.h | 4 +--- drivers/net/bnxt/tf_core/tf_tbl_sram.h | 6 +----- drivers/net/bnxt/tf_core/tf_tcam.h | 3 +-- drivers/net/bnxt/tf_core/tf_tcam_shared.h | 1 - drivers/net/bnxt/tf_core/tf_util.c | 3 +-- drivers/net/bnxt/tf_core/tf_util.h | 3 +-- drivers/net/bnxt/tf_core/tfp.c | 2 +- drivers/net/bnxt/tf_core/tfp.h | 4 +--- drivers/net/bnxt/tf_ulp/bnxt_tf_common.h | 3 +-- drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h | 1 - drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 1 - drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h | 1 - drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 1 - drivers/net/bnxt/tf_ulp/ulp_gen_hash.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_gen_hash.h | 3 +-- drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h | 1 - drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h | 1 - drivers/net/bnxt/tf_ulp/ulp_mapper.h | 1 - drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h | 3 +-- drivers/net/bnxt/tf_ulp/ulp_matcher.h | 3 +-- drivers/net/bnxt/tf_ulp/ulp_port_db.h | 1 - drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 1 - drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 1 - drivers/net/bnxt/tf_ulp/ulp_tun.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_tun.h | 3 +-- drivers/net/bnxt/tf_ulp/ulp_utils.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_utils.h | 3 +-- 87 files changed, 73 insertions(+), 135 deletions(-) diff --git a/drivers/net/bnxt/bnxt_cpr.c b/drivers/net/bnxt/bnxt_cpr.c index 5bb376d4d5..0733cf4df2 100644 --- a/drivers/net/bnxt/bnxt_cpr.c +++ b/drivers/net/bnxt/bnxt_cpr.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/bnxt_cpr.h b/drivers/net/bnxt/bnxt_cpr.h index dab6bed2ae..2de154322d 100644 --- a/drivers/net/bnxt/bnxt_cpr.h +++ b/drivers/net/bnxt/bnxt_cpr.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/bnxt_filter.c b/drivers/net/bnxt/bnxt_filter.c index b0c3bbd1b2..ff563f08bb 100644 --- a/drivers/net/bnxt/bnxt_filter.c +++ b/drivers/net/bnxt/bnxt_filter.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/bnxt_irq.c b/drivers/net/bnxt/bnxt_irq.c index 508abfc844..71d1565e08 100644 --- a/drivers/net/bnxt/bnxt_irq.c +++ b/drivers/net/bnxt/bnxt_irq.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/bnxt_irq.h b/drivers/net/bnxt/bnxt_irq.h index 53d9198858..e498578968 100644 --- a/drivers/net/bnxt/bnxt_irq.h +++ b/drivers/net/bnxt/bnxt_irq.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/bnxt_nvm_defs.h b/drivers/net/bnxt/bnxt_nvm_defs.h index bb45d7e472..f5ac4e8c84 100644 --- a/drivers/net/bnxt/bnxt_nvm_defs.h +++ b/drivers/net/bnxt/bnxt_nvm_defs.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/bnxt_reps.h b/drivers/net/bnxt/bnxt_reps.h index 01e57ee5b5..3f2db9d1ae 100644 --- a/drivers/net/bnxt/bnxt_reps.h +++ b/drivers/net/bnxt/bnxt_reps.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/bnxt_ring.h b/drivers/net/bnxt/bnxt_ring.h index ef9586e64e..3d747aba54 100644 --- a/drivers/net/bnxt/bnxt_ring.h +++ b/drivers/net/bnxt/bnxt_ring.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/bnxt_rxq.h b/drivers/net/bnxt/bnxt_rxq.h index a97037c6e0..b9908be5f4 100644 --- a/drivers/net/bnxt/bnxt_rxq.h +++ b/drivers/net/bnxt/bnxt_rxq.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/bnxt_rxr.h b/drivers/net/bnxt/bnxt_rxr.h index a84f016609..e132166a18 100644 --- a/drivers/net/bnxt/bnxt_rxr.h +++ b/drivers/net/bnxt/bnxt_rxr.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/bnxt_rxtx_vec_avx2.c b/drivers/net/bnxt/bnxt_rxtx_vec_avx2.c index 34bd22edf0..d4e8e8eb87 100644 --- a/drivers/net/bnxt/bnxt_rxtx_vec_avx2.c +++ b/drivers/net/bnxt/bnxt_rxtx_vec_avx2.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright(c) 2019-2021 Broadcom All rights reserved. */ +/* Copyright(c) 2019-2023 Broadcom All rights reserved. */ #include #include diff --git a/drivers/net/bnxt/bnxt_rxtx_vec_common.h b/drivers/net/bnxt/bnxt_rxtx_vec_common.h index 0627fd212d..2294f0aa3c 100644 --- a/drivers/net/bnxt/bnxt_rxtx_vec_common.h +++ b/drivers/net/bnxt/bnxt_rxtx_vec_common.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2020-2021 Broadcom + * Copyright(c) 2020-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/bnxt_rxtx_vec_neon.c b/drivers/net/bnxt/bnxt_rxtx_vec_neon.c index 6a4ece681b..aa1b1ab8bb 100644 --- a/drivers/net/bnxt/bnxt_rxtx_vec_neon.c +++ b/drivers/net/bnxt/bnxt_rxtx_vec_neon.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright(c) 2019-2021 Broadcom All rights reserved. */ +/* Copyright(c) 2019-2023 Broadcom All rights reserved. */ #include #include diff --git a/drivers/net/bnxt/bnxt_rxtx_vec_sse.c b/drivers/net/bnxt/bnxt_rxtx_vec_sse.c index ffd560166c..2ad8591b90 100644 --- a/drivers/net/bnxt/bnxt_rxtx_vec_sse.c +++ b/drivers/net/bnxt/bnxt_rxtx_vec_sse.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright(c) 2019-2021 Broadcom All rights reserved. */ +/* Copyright(c) 2019-2023 Broadcom All rights reserved. */ #include #include diff --git a/drivers/net/bnxt/bnxt_stats.c b/drivers/net/bnxt/bnxt_stats.c index 72169e8b35..0e25207fc3 100644 --- a/drivers/net/bnxt/bnxt_stats.c +++ b/drivers/net/bnxt/bnxt_stats.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/bnxt_stats.h b/drivers/net/bnxt/bnxt_stats.h index 1ca9b9c594..e46c05eed3 100644 --- a/drivers/net/bnxt/bnxt_stats.h +++ b/drivers/net/bnxt/bnxt_stats.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/bnxt_txq.h b/drivers/net/bnxt/bnxt_txq.h index f3a03812ad..3a483ad5c3 100644 --- a/drivers/net/bnxt/bnxt_txq.h +++ b/drivers/net/bnxt/bnxt_txq.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/bnxt_util.c b/drivers/net/bnxt/bnxt_util.c index 3167894789..47dd5fa6ff 100644 --- a/drivers/net/bnxt/bnxt_util.c +++ b/drivers/net/bnxt/bnxt_util.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/bnxt_util.h b/drivers/net/bnxt/bnxt_util.h index b243c21ec2..3437dc75ae 100644 --- a/drivers/net/bnxt/bnxt_util.h +++ b/drivers/net/bnxt/bnxt_util.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/meson.build b/drivers/net/bnxt/meson.build index 0288ed6262..f6fb097102 100644 --- a/drivers/net/bnxt/meson.build +++ b/drivers/net/bnxt/meson.build @@ -1,6 +1,6 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2018 Intel Corporation -# Copyright(c) 2020 Broadcom +# Copyright(c) 2023 Broadcom if is_windows build = false diff --git a/drivers/net/bnxt/rte_pmd_bnxt.c b/drivers/net/bnxt/rte_pmd_bnxt.c index ffa1114046..964a5aeb05 100644 --- a/drivers/net/bnxt/rte_pmd_bnxt.c +++ b/drivers/net/bnxt/rte_pmd_bnxt.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2017-2021 Broadcom + * Copyright(c) 2017-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/rte_pmd_bnxt.h b/drivers/net/bnxt/rte_pmd_bnxt.h index 174c18a0f3..2077026903 100644 --- a/drivers/net/bnxt/rte_pmd_bnxt.h +++ b/drivers/net/bnxt/rte_pmd_bnxt.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2017-2021 Broadcom + * Copyright(c) 2017-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_core/bitalloc.c b/drivers/net/bnxt/tf_core/bitalloc.c index e253cfc3a6..136263b6a4 100644 --- a/drivers/net/bnxt/tf_core/bitalloc.c +++ b/drivers/net/bnxt/tf_core/bitalloc.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -7,7 +7,6 @@ #define BITALLOC_MAX_LEVELS 6 - /* Finds the last bit set plus 1, equivalent to gcc __builtin_fls */ static int ba_fls(bitalloc_word_t v) diff --git a/drivers/net/bnxt/tf_core/bitalloc.h b/drivers/net/bnxt/tf_core/bitalloc.h index db8a09abdd..bf15cbc87b 100644 --- a/drivers/net/bnxt/tf_core/bitalloc.h +++ b/drivers/net/bnxt/tf_core/bitalloc.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -121,5 +121,4 @@ int ba_free_count(struct bitalloc *pool); * Returns the pool's in use count */ int ba_inuse_count(struct bitalloc *pool); - #endif /* _BITALLOC_H_ */ diff --git a/drivers/net/bnxt/tf_core/cfa_resource_types.h b/drivers/net/bnxt/tf_core/cfa_resource_types.h index 36a55d4e17..874d7b834f 100644 --- a/drivers/net/bnxt/tf_core/cfa_resource_types.h +++ b/drivers/net/bnxt/tf_core/cfa_resource_types.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -256,5 +256,4 @@ /* Table Scope */ #define CFA_RESOURCE_TYPE_P4_TBL_SCOPE 0x22UL #define CFA_RESOURCE_TYPE_P4_LAST CFA_RESOURCE_TYPE_P4_TBL_SCOPE - #endif /* _CFA_RESOURCE_TYPES_H_ */ diff --git a/drivers/net/bnxt/tf_core/dpool.c b/drivers/net/bnxt/tf_core/dpool.c index 5c03f775a5..f60c04e949 100644 --- a/drivers/net/bnxt/tf_core/dpool.c +++ b/drivers/net/bnxt/tf_core/dpool.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ #include @@ -55,6 +55,7 @@ static int dpool_move(struct dpool *dpool, { uint32_t size; uint32_t i; + if (DP_IS_FREE(dpool->entry[dst_index].flags)) { size = DP_FLAGS_SIZE(dpool->entry[src_index].flags); diff --git a/drivers/net/bnxt/tf_core/dpool.h b/drivers/net/bnxt/tf_core/dpool.h index fb79c7be4b..2e64916bf6 100644 --- a/drivers/net/bnxt/tf_core/dpool.h +++ b/drivers/net/bnxt/tf_core/dpool.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -305,5 +305,4 @@ void dpool_dump(struct dpool *dpool); int dpool_defrag(struct dpool *dpool, uint32_t entry_size, uint8_t defrag); - #endif /* _DPOOL_H_ */ diff --git a/drivers/net/bnxt/tf_core/ll.c b/drivers/net/bnxt/tf_core/ll.c index f2bdff6b9e..75b096aa08 100644 --- a/drivers/net/bnxt/tf_core/ll.c +++ b/drivers/net/bnxt/tf_core/ll.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_core/ll.h b/drivers/net/bnxt/tf_core/ll.h index 9cf8f64ec2..89271b7243 100644 --- a/drivers/net/bnxt/tf_core/ll.h +++ b/drivers/net/bnxt/tf_core/ll.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_core/lookup3.h b/drivers/net/bnxt/tf_core/lookup3.h index 743c4d9c4f..a937de4a16 100644 --- a/drivers/net/bnxt/tf_core/lookup3.h +++ b/drivers/net/bnxt/tf_core/lookup3.h @@ -157,5 +157,4 @@ static inline uint32_t hashword(const uint32_t *k, /*------------------------------------------------- report the result */ return c; } - #endif /* _LOOKUP3_H_ */ diff --git a/drivers/net/bnxt/tf_core/rand.c b/drivers/net/bnxt/tf_core/rand.c index d419d7257b..07d4aff750 100644 --- a/drivers/net/bnxt/tf_core/rand.c +++ b/drivers/net/bnxt/tf_core/rand.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_core/rand.h b/drivers/net/bnxt/tf_core/rand.h index 80b2ab3ecd..656bd58868 100644 --- a/drivers/net/bnxt/tf_core/rand.h +++ b/drivers/net/bnxt/tf_core/rand.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -32,5 +32,4 @@ uint32_t rand32(void); * */ void rand_init(void); - #endif /* __RAND_H__ */ diff --git a/drivers/net/bnxt/tf_core/stack.c b/drivers/net/bnxt/tf_core/stack.c index db79461db9..d2e200b4f4 100644 --- a/drivers/net/bnxt/tf_core/stack.c +++ b/drivers/net/bnxt/tf_core/stack.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_core/stack.h b/drivers/net/bnxt/tf_core/stack.h index 358233279c..f9a748574c 100644 --- a/drivers/net/bnxt/tf_core/stack.h +++ b/drivers/net/bnxt/tf_core/stack.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ #ifndef _STACK_H_ @@ -113,5 +113,4 @@ int stack_pop(struct stack *st, uint32_t *x); * none */ void stack_dump(struct stack *st); - #endif /* _STACK_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_common.h b/drivers/net/bnxt/tf_core/tf_common.h index abdd390b4f..0bfb7f1f33 100644 --- a/drivers/net/bnxt/tf_core/tf_common.h +++ b/drivers/net/bnxt/tf_core/tf_common.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2020-2021 Broadcom + * Copyright(c) 2020-2023 Broadcom * All rights reserved. */ @@ -39,5 +39,4 @@ return -EINVAL; \ } \ } while (0) - #endif /* _TF_COMMON_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index 814eff68da..f5fe0a9098 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -2481,5 +2481,4 @@ struct tf_get_sram_policy_parms { */ int tf_get_sram_policy(struct tf *tfp, struct tf_get_sram_policy_parms *parms); - #endif /* _TF_CORE_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index bc6de60423..5a42180719 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -1142,5 +1142,4 @@ extern const struct tf_dev_ops tf_dev_ops_p58; */ extern const struct tf_hcapi_resource_map tf_hcapi_res_map_p4[CFA_RESOURCE_TYPE_P4_LAST + 1]; extern const struct tf_hcapi_resource_map tf_hcapi_res_map_p58[CFA_RESOURCE_TYPE_P58_LAST + 1]; - #endif /* _TF_DEVICE_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h index 86de525995..20da2f97db 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.h +++ b/drivers/net/bnxt/tf_core/tf_device_p4.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -181,5 +181,4 @@ const struct tf_hcapi_resource_map tf_hcapi_res_map_p4[CFA_RESOURCE_TYPE_P4_LAST TF_MODULE_TYPE_EM, 1 << TF_EM_TBL_TYPE_TBL_SCOPE }, }; - #endif /* _TF_DEVICE_P4_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h index 61c856b767..858d975f11 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.h +++ b/drivers/net/bnxt/tf_core/tf_device_p58.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_core/tf_em.h b/drivers/net/bnxt/tf_core/tf_em.h index 074c128651..97cdb48f14 100644 --- a/drivers/net/bnxt/tf_core/tf_em.h +++ b/drivers/net/bnxt/tf_core/tf_em.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -8,7 +8,6 @@ #include "tf_core.h" #include "tf_session.h" - #include "tf_em_common.h" #include "hcapi_cfa_defs.h" diff --git a/drivers/net/bnxt/tf_core/tf_em_common.c b/drivers/net/bnxt/tf_core/tf_em_common.c index 3bdfc14e05..b56b7cc188 100644 --- a/drivers/net/bnxt/tf_core/tf_em_common.c +++ b/drivers/net/bnxt/tf_core/tf_em_common.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -9,7 +9,6 @@ #include #include #include - #include "tf_core.h" #include "tf_util.h" #include "tf_common.h" @@ -20,10 +19,8 @@ #include "tf_device.h" #include "tf_ext_flow_handle.h" #include "hcapi_cfa.h" - #include "bnxt.h" - /** Invalid table scope id */ #define TF_TBL_SCOPE_INVALID 0xffffffff @@ -285,7 +282,6 @@ tf_em_create_key_entry(struct cfa_p4_eem_entry_hdr *result, memcpy(key_entry->key, in_key, TF_P4_HW_EM_KEY_MAX_SIZE + 4); } - /** * Return the number of page table pages needed to * reference the given number of next level pages. @@ -908,7 +904,6 @@ tf_em_delete_ext_entry(struct tf *tfp, return tf_delete_eem_entry(tbl_scope_cb, parms); } - int tf_em_ext_common_bind(struct tf *tfp, struct tf_em_cfg_parms *parms) @@ -1204,7 +1199,6 @@ int tf_em_ext_map_tbl_scope(struct tf *tfp, gcfg_parms.config_mask = (uint8_t *)mask; gcfg_parms.config_sz_in_bytes = sizeof(uint64_t); - rc = tf_msg_set_global_cfg(tfp, &gcfg_parms); if (rc) { TFP_DRV_LOG(ERR, diff --git a/drivers/net/bnxt/tf_core/tf_em_common.h b/drivers/net/bnxt/tf_core/tf_em_common.h index 7f215adef2..0ae95f260a 100644 --- a/drivers/net/bnxt/tf_core/tf_em_common.h +++ b/drivers/net/bnxt/tf_core/tf_em_common.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -178,7 +178,6 @@ int tf_em_validate_num_entries(struct tf_tbl_scope_cb *tbl_scope_cb, int tf_em_size_table(struct hcapi_cfa_em_table *tbl, uint32_t page_size); - /** * Look up table scope control block using tbl_scope_id from * tf_session @@ -196,5 +195,4 @@ int tf_em_size_table(struct hcapi_cfa_em_table *tbl, struct tf_tbl_scope_cb * tf_em_ext_common_tbl_scope_find(struct tf *tfp, uint32_t tbl_scope_id); - #endif /* _TF_EM_COMMON_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_em_hash_internal.c b/drivers/net/bnxt/tf_core/tf_em_hash_internal.c index 60273a798c..d72ac83295 100644 --- a/drivers/net/bnxt/tf_core/tf_em_hash_internal.c +++ b/drivers/net/bnxt/tf_core/tf_em_hash_internal.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_core/tf_em_host.c b/drivers/net/bnxt/tf_core/tf_em_host.c index 869a78e904..9efffe4ee5 100644 --- a/drivers/net/bnxt/tf_core/tf_em_host.c +++ b/drivers/net/bnxt/tf_core/tf_em_host.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -376,7 +376,6 @@ tf_em_ext_alloc(struct tf *tfp, void *ext_ptr = NULL; uint16_t pf; - rc = tf_session_get_session_internal(tfp, &tfs); if (rc) { TFP_DRV_LOG(ERR, "Failed to get tf_session, rc:%s\n", diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c index 67ba011eae..8ea5d93672 100644 --- a/drivers/net/bnxt/tf_core/tf_em_internal.c +++ b/drivers/net/bnxt/tf_core/tf_em_internal.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -15,6 +15,7 @@ #include "tf_msg.h" #include "tfp.h" #include "tf_ext_flow_handle.h" + #include "bnxt.h" #define TF_EM_DB_EM_REC 0 diff --git a/drivers/net/bnxt/tf_core/tf_ext_flow_handle.h b/drivers/net/bnxt/tf_core/tf_ext_flow_handle.h index bf6dbcd238..8f967c5c85 100644 --- a/drivers/net/bnxt/tf_core/tf_ext_flow_handle.h +++ b/drivers/net/bnxt/tf_core/tf_ext_flow_handle.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -184,6 +184,4 @@ do { \ type = (((gfid) & TF_HASH_TYPE_GFID_MASK) >> \ TF_HASH_TYPE_GFID_SFT); \ } while (0) - - #endif /* _TF_EXT_FLOW_HANDLE_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_global_cfg.c b/drivers/net/bnxt/tf_core/tf_global_cfg.c index d83e7db315..3a8030a2fb 100644 --- a/drivers/net/bnxt/tf_core/tf_global_cfg.c +++ b/drivers/net/bnxt/tf_core/tf_global_cfg.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_core/tf_global_cfg.h b/drivers/net/bnxt/tf_core/tf_global_cfg.h index c14e5e9109..f57f3313da 100644 --- a/drivers/net/bnxt/tf_core/tf_global_cfg.h +++ b/drivers/net/bnxt/tf_core/tf_global_cfg.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -146,5 +146,4 @@ int tf_global_cfg_set(struct tf *tfp, */ int tf_global_cfg_get(struct tf *tfp, struct tf_global_cfg_parms *parms); - #endif /* TF_GLOBAL_CFG_H */ diff --git a/drivers/net/bnxt/tf_core/tf_hash.c b/drivers/net/bnxt/tf_core/tf_hash.c index a722821f05..b402dc8a12 100644 --- a/drivers/net/bnxt/tf_core/tf_hash.c +++ b/drivers/net/bnxt/tf_core/tf_hash.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_core/tf_hash.h b/drivers/net/bnxt/tf_core/tf_hash.h index d128269b54..0c082f5fd6 100644 --- a/drivers/net/bnxt/tf_core/tf_hash.h +++ b/drivers/net/bnxt/tf_core/tf_hash.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -23,5 +23,4 @@ tf_hash_calc_crc32i(uint32_t init, uint8_t *buf, uint32_t len); */ uint32_t tf_hash_calc_crc32(uint8_t *buf, uint32_t len); - #endif diff --git a/drivers/net/bnxt/tf_core/tf_identifier.c b/drivers/net/bnxt/tf_core/tf_identifier.c index 8131d8754d..1846675916 100644 --- a/drivers/net/bnxt/tf_core/tf_identifier.c +++ b/drivers/net/bnxt/tf_core/tf_identifier.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_core/tf_identifier.h b/drivers/net/bnxt/tf_core/tf_identifier.h index 285ff11ce2..48ca63a58d 100644 --- a/drivers/net/bnxt/tf_core/tf_identifier.h +++ b/drivers/net/bnxt/tf_core/tf_identifier.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -212,5 +212,4 @@ int tf_ident_search(struct tf *tfp, */ int tf_ident_get_resc_info(struct tf *tfp, struct tf_identifier_resource_info *parms); - #endif /* _TF_IDENTIFIER_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_if_tbl.h b/drivers/net/bnxt/tf_core/tf_if_tbl.h index bea2f07324..bb536c31d1 100644 --- a/drivers/net/bnxt/tf_core/tf_if_tbl.h +++ b/drivers/net/bnxt/tf_core/tf_if_tbl.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -224,5 +224,4 @@ int tf_if_tbl_set(struct tf *tfp, */ int tf_if_tbl_get(struct tf *tfp, struct tf_if_tbl_get_parms *parms); - #endif /* TF_IF_TBL_TYPE_H */ diff --git a/drivers/net/bnxt/tf_core/tf_msg_common.h b/drivers/net/bnxt/tf_core/tf_msg_common.h index 49f334717d..949062a42f 100644 --- a/drivers/net/bnxt/tf_core/tf_msg_common.h +++ b/drivers/net/bnxt/tf_core/tf_msg_common.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -40,5 +40,4 @@ parms.resp_size = 0; \ parms.resp_data = NULL; \ } while (0) - #endif /* _TF_MSG_COMMON_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_project.h b/drivers/net/bnxt/tf_core/tf_project.h index 57285508fb..6357760f16 100644 --- a/drivers/net/bnxt/tf_core/tf_project.h +++ b/drivers/net/bnxt/tf_core/tf_project.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -20,5 +20,4 @@ #ifndef TF_SHARED #define TF_SHARED 0 #endif - #endif /* _TF_PROJECT_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_resources.h b/drivers/net/bnxt/tf_core/tf_resources.h index 2c1d738755..8c28d3dc68 100644 --- a/drivers/net/bnxt/tf_core/tf_resources.h +++ b/drivers/net/bnxt/tf_core/tf_resources.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -7,5 +7,4 @@ #define _TF_RESOURCES_H_ #define TF_NUM_TBL_SCOPE 16 /* < Number of TBL scopes */ - #endif /* _TF_RESOURCES_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_rm.h b/drivers/net/bnxt/tf_core/tf_rm.h index da7d0c7211..a4187891f4 100644 --- a/drivers/net/bnxt/tf_core/tf_rm.h +++ b/drivers/net/bnxt/tf_core/tf_rm.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -43,7 +43,6 @@ struct tf; * support module, not called directly. */ - /** * RM Element configuration enumeration. Used by the Device to * indicate how the RM elements the DB consists off, are to be @@ -75,8 +74,6 @@ enum tf_rm_elem_cfg_type { * HCAPI type. Child accesses the parent db. */ TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - - TF_RM_TYPE_MAX }; @@ -581,5 +578,4 @@ tf_rm_check_indexes_in_range(struct tf_rm_check_indexes_in_range_parms *parms); */ int tf_rm_get_slices(struct tf_rm_get_slices_parms *parms); - #endif /* TF_RM_NEW_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_session.h b/drivers/net/bnxt/tf_core/tf_session.h index a6716dfff4..5a94b941fa 100644 --- a/drivers/net/bnxt/tf_core/tf_session.h +++ b/drivers/net/bnxt/tf_core/tf_session.h @@ -716,5 +716,4 @@ tf_session_set_if_tbl_db(struct tf *tfp, int tf_session_get_if_tbl_db(struct tf *tfp, void **if_tbl_handle); - #endif /* _TF_SESSION_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_sram_mgr.h b/drivers/net/bnxt/tf_core/tf_sram_mgr.h index eb2156456a..fc78426130 100644 --- a/drivers/net/bnxt/tf_core/tf_sram_mgr.h +++ b/drivers/net/bnxt/tf_core/tf_sram_mgr.h @@ -303,5 +303,4 @@ const char */ const char *tf_sram_bank_2_str(enum tf_sram_bank_id bank_id); - #endif /* _TF_SRAM_MGR_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_tbl.h b/drivers/net/bnxt/tf_core/tf_tbl.h index 2483718e5d..dfa3bcaa14 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.h +++ b/drivers/net/bnxt/tf_core/tf_tbl.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -15,7 +15,6 @@ struct tf; * The Table module provides processing of Internal TF table types. */ - /** * Table configuration parameters */ @@ -327,5 +326,4 @@ int tf_tbl_bulk_get(struct tf *tfp, int tf_tbl_get_resc_info(struct tf *tfp, struct tf_tbl_resource_info *tbl); - #endif /* TF_TBL_TYPE_H */ diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.h b/drivers/net/bnxt/tf_core/tf_tbl_sram.h index 32001e34a9..c109210ce9 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl_sram.h +++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -9,12 +9,10 @@ #include "tf_core.h" #include "stack.h" - /** * The SRAM Table module provides processing of managed SRAM types. */ - /** * @page tblsram SRAM Table * @@ -99,7 +97,6 @@ int tf_tbl_sram_alloc(struct tf *tfp, int tf_tbl_sram_free(struct tf *tfp, struct tf_tbl_free_parms *parms); - /** * Configures the requested element by sending a firmware request which * then installs it into the device internal structures. @@ -150,5 +147,4 @@ int tf_tbl_sram_get(struct tf *tfp, */ int tf_tbl_sram_bulk_get(struct tf *tfp, struct tf_tbl_get_bulk_parms *parms); - #endif /* TF_TBL_SRAM_H */ diff --git a/drivers/net/bnxt/tf_core/tf_tcam.h b/drivers/net/bnxt/tf_core/tf_tcam.h index 0ed2250464..1807edd092 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam.h +++ b/drivers/net/bnxt/tf_core/tf_tcam.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -374,5 +374,4 @@ int tf_tcam_get(struct tf *tfp, */ int tf_tcam_get_resc_info(struct tf *tfp, struct tf_tcam_resource_info *parms); - #endif /* _TF_TCAM_H */ diff --git a/drivers/net/bnxt/tf_core/tf_tcam_shared.h b/drivers/net/bnxt/tf_core/tf_tcam_shared.h index 020763af6b..524631f262 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam_shared.h +++ b/drivers/net/bnxt/tf_core/tf_tcam_shared.h @@ -179,5 +179,4 @@ int tf_tcam_shared_move_p58(struct tf *tfp, */ int tf_tcam_shared_clear(struct tf *tfp, struct tf_clear_tcam_shared_entries_parms *parms); - #endif /* _TF_TCAM_SHARED_H */ diff --git a/drivers/net/bnxt/tf_core/tf_util.c b/drivers/net/bnxt/tf_core/tf_util.c index 7d9de7c764..8ce8238b4a 100644 --- a/drivers/net/bnxt/tf_core/tf_util.c +++ b/drivers/net/bnxt/tf_core/tf_util.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ #include - #include "tf_util.h" const char * diff --git a/drivers/net/bnxt/tf_core/tf_util.h b/drivers/net/bnxt/tf_core/tf_util.h index 854c51931a..f46480868b 100644 --- a/drivers/net/bnxt/tf_core/tf_util.h +++ b/drivers/net/bnxt/tf_core/tf_util.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ @@ -93,5 +93,4 @@ const char *tf_module_subtype_2_str(enum tf_module_type module, * Pointer to a char string holding the string for the EM type */ const char *tf_module_2_str(enum tf_module_type module); - #endif /* _TF_UTIL_H_ */ diff --git a/drivers/net/bnxt/tf_core/tfp.c b/drivers/net/bnxt/tf_core/tfp.c index a967a9ccf2..604141b689 100644 --- a/drivers/net/bnxt/tf_core/tfp.c +++ b/drivers/net/bnxt/tf_core/tfp.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: BSD-3-Clause * see the individual elements. - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_core/tfp.h b/drivers/net/bnxt/tf_core/tfp.h index 5a99c7a06e..92f76004da 100644 --- a/drivers/net/bnxt/tf_core/tfp.h +++ b/drivers/net/bnxt/tf_core/tfp.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -185,7 +185,6 @@ void tfp_spinlock_unlock(struct tfp_spinlock_parms *slock); */ int tfp_get_fid(struct tf *tfp, uint16_t *fw_fid); - /* * @ref tfp_cpu_to_le_16 * @ref tfp_le_to_cpu_16 @@ -232,5 +231,4 @@ int tfp_get_fid(struct tf *tfp, uint16_t *fw_fid); * */ int tfp_get_pf(struct tf *tfp, uint16_t *pf); - #endif /* _TFP_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h index d006464a75..cd4cd8ac74 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ @@ -68,5 +68,4 @@ bnxt_ulp_cntxt_ptr2_mark_db_get(struct bnxt_ulp_context *ulp_ctx); int32_t bnxt_ulp_cntxt_ptr2_mark_db_set(struct bnxt_ulp_context *ulp_ctx, struct bnxt_ulp_mark_tbl *mark_tbl); - #endif /* _BNXT_TF_COMMON_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h index 229e21814b..d6d7a1f0af 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h @@ -25,5 +25,4 @@ uint16_t bnxt_pmd_get_phy_port_id(uint16_t port); uint16_t bnxt_pmd_get_vport(uint16_t port); enum bnxt_ulp_intf_type bnxt_pmd_get_interface_type(uint16_t port); int32_t bnxt_pmd_set_unicast_rxmask(struct rte_eth_dev *eth_dev); - #endif /* _BNXT_TF_PMD_ABSTRACT_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index 05a98b14e6..906d933af5 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -317,5 +317,4 @@ bnxt_ulp_cntxt_num_shared_clients_get(struct bnxt_ulp_context *ulp_ctx); struct bnxt_flow_app_tun_ent * bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp); - #endif /* _BNXT_ULP_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h index 9825ed2a27..9df5ae51a3 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h +++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h @@ -184,5 +184,4 @@ int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt, enum tf_dir dir, uint32_t hw_cntr_id, uint32_t pc_idx); - #endif /* _ULP_FC_MGR_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h index 2b02836a40..ada34c0e6c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h +++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h @@ -410,5 +410,4 @@ ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt); */ void ulp_flow_db_shared_session_set(struct ulp_flow_db_res_params *res, enum bnxt_ulp_shared_session shared); - #endif /* _ULP_FLOW_DB_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c b/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c index 84c83de35c..d746fbbd4e 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c +++ b/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_hash.h b/drivers/net/bnxt/tf_ulp/ulp_gen_hash.h index 543ef79d30..d3f3840cbe 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_gen_hash.h +++ b/drivers/net/bnxt/tf_ulp/ulp_gen_hash.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ @@ -162,5 +162,4 @@ ulp_gen_hash_tbl_list_add(struct ulp_gen_hash_tbl *hash_tbl, int32_t ulp_gen_hash_tbl_list_del(struct ulp_gen_hash_tbl *hash_tbl, struct ulp_gen_hash_entry_params *entry); - #endif /* _ULP_GEN_HASH_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h index f245825142..3060072967 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h +++ b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h @@ -167,5 +167,4 @@ int32_t ulp_mapper_gen_tbl_hash_entry_add(struct ulp_mapper_gen_tbl_list *tbl_list, struct ulp_gen_hash_entry_params *hash_entry, struct ulp_mapper_gen_tbl_entry *gen_tbl_ent); - #endif /* _ULP_EN_TBL_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h index 793511564a..ded967a0af 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h +++ b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h @@ -63,5 +63,4 @@ ulp_ha_mgr_close(struct bnxt_ulp_context *ulp_ctx); int32_t ulp_ha_mgr_region_get(struct bnxt_ulp_context *ulp_ctx, enum ulp_ha_mgr_region *region); - #endif /* _ULP_HA_MGR_H_*/ diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h index 4d6ba0f73a..b7e6f3ada2 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h @@ -133,5 +133,4 @@ ulp_mapper_get_shared_fid(struct bnxt_ulp_context *ulp, uint32_t id, uint16_t key, uint32_t *fid); - #endif /* _ULP_MAPPER_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c index 9dffaef73b..1cfb21782c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h index d9d82d4644..2a1f3ad615 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h +++ b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ @@ -112,5 +112,4 @@ int32_t ulp_mark_db_mark_del(struct bnxt_ulp_context *ctxt, uint32_t mark_flag, uint32_t gfid); - #endif /* _ULP_MARK_MGR_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_matcher.h b/drivers/net/bnxt/tf_ulp/ulp_matcher.h index dc2487889c..47a9e8e0eb 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_matcher.h +++ b/drivers/net/bnxt/tf_ulp/ulp_matcher.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ @@ -27,5 +27,4 @@ ulp_matcher_pattern_match(struct ulp_rte_parser_params *params, int32_t ulp_matcher_action_match(struct ulp_rte_parser_params *params, uint32_t *act_id); - #endif /* ULP_MATCHER_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.h b/drivers/net/bnxt/tf_ulp/ulp_port_db.h index b112f1a216..f575a3c2e2 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_port_db.h +++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.h @@ -326,5 +326,4 @@ ulp_port_db_parent_vnic_get(struct bnxt_ulp_context *ulp_ctxt, int32_t ulp_port_db_phy_port_get(struct bnxt_ulp_context *ulp_ctxt, uint32_t port_id, uint16_t *phy_port); - #endif /* _ULP_PORT_DB_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h index f59b10e88b..b0b2b4f33f 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h @@ -259,5 +259,4 @@ ulp_vendor_vxlan_decap_act_handler(const struct rte_flow_action *action_item, int32_t ulp_rte_vendor_vxlan_decap_hdr_handler(const struct rte_flow_item *item, struct ulp_rte_parser_params *params); - #endif /* _ULP_RTE_PARSER_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index 7d1bc06a3e..3dcc6dbc0c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -441,5 +441,4 @@ extern struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[]; * that could be reused by other templates. */ extern uint32_t ulp_glb_template_tbl[]; - #endif /* _ULP_TEMPLATE_STRUCT_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.c b/drivers/net/bnxt/tf_ulp/ulp_tun.c index 7ce6740633..3be3475a83 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_tun.c +++ b/drivers/net/bnxt/tf_ulp/ulp_tun.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.h b/drivers/net/bnxt/tf_ulp/ulp_tun.h index 0fc2ac39d1..b60aa1efbe 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_tun.h +++ b/drivers/net/bnxt/tf_ulp/ulp_tun.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ @@ -57,5 +57,4 @@ ulp_tunnel_offload_entry_clear(struct bnxt_tun_cache_entry *tun_tbl, int32_t ulp_tunnel_offload_process(struct ulp_rte_parser_params *params); - #endif diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c index c60d81d14a..6fb2e3f2ad 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_utils.c +++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.h b/drivers/net/bnxt/tf_ulp/ulp_utils.h index 68a537fa0a..e9ccee7bf4 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_utils.h +++ b/drivers/net/bnxt/tf_ulp/ulp_utils.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ @@ -522,5 +522,4 @@ uint32_t ulp_bitmap_notzero(const uint8_t *bitmap, int32_t size); /* returns 0 if input is power of 2 */ int32_t ulp_util_is_power_of_2(uint64_t x); - #endif /* _ULP_UTILS_H_ */ From patchwork Fri Apr 21 18:11:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Randy Schacher X-Patchwork-Id: 126408 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C4E58429A8; Fri, 21 Apr 2023 20:13:00 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7E9F542D40; Fri, 21 Apr 2023 20:12:27 +0200 (CEST) Received: from mail-oa1-f97.google.com (mail-oa1-f97.google.com [209.85.160.97]) by mails.dpdk.org (Postfix) with ESMTP id B05EC42C4D for ; Fri, 21 Apr 2023 20:12:22 +0200 (CEST) Received: by mail-oa1-f97.google.com with SMTP id 586e51a60fabf-187b70ab997so12504084fac.0 for ; Fri, 21 Apr 2023 11:12:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1682100742; x=1684692742; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8a+ENX/kWiCGPw9rUYaufOU1QHIFYozhpyefgvitJH8=; b=TUGpBTBQBLBQanJA7emBzlzOrInzJv2Af6v3Hn81r0l8CS018qn8KT66wbi+jF21QR UNG+ZAK/nXnrg1EMintieAVJApL+V00CQ8pqKJCgOVFMSGx1D9qXTv0rmL5KU0y35TrK Vs2URWbLRKcuWGPy4KQAGZc0pqOcPl+1ibOuo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682100742; x=1684692742; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8a+ENX/kWiCGPw9rUYaufOU1QHIFYozhpyefgvitJH8=; b=BjWjLQOfC64/Q92eoq1tcJv9V8U3/6coVWs5TOnmbslNhYaaZpInUiI67CJD2OmntX hV2QvyoaDXVTg/IEDRu70/5szhIwJEkC0kGy3q3tk/kYrjjjzOmBQSkLsdyLa3s56Y9f gVNdbM7vlsh6yTjcZLRAY2HKAJ5dmYF7hfeTnmoTEouWJvzCBiNw3k4HHr4arUjwj1sP KNmN9SWpdW9+IwONlOQr6KmoHlHvCtHGKCJk6Y41b6CcxuQxr/ywUDz+Fbp3EbldC2fT F2O9odjz3PftuF+lp9jGjFlbyu47esVJdfA43rzdZ07kQ88wzyK2pTO+SaGcRioIwdKo rRKg== X-Gm-Message-State: AAQBX9etOn19cXtefjzpm9WC7400P2FOHJtL0tZGBGOlQ/ZPOf/18IyC 3n4mRQ+VslZ8X1TfkepX75Ph3Mm7PWTI2UNAugg3Vwl1uVe6f7+XSkWQUhwD3kHScOP2JIiEM4J uAfjCbojxy/0LempykohQv6IjMHaa/9q63MeDDW+LVmaqe2FEHcBs30JKQre8iNF/W19KlOSTIj gqjWa9iPQNmWt/ X-Google-Smtp-Source: AKy350ajy34e0Gk/ZZfSMlEuoo8qUMeWEdW7L9xqBnm6zKYkMb1q6bSaCfUNEeCNBwWAjcUH1quCXIuJwda0 X-Received: by 2002:a05:6870:559e:b0:177:b3dd:6139 with SMTP id n30-20020a056870559e00b00177b3dd6139mr3242691oao.27.1682100741626; Fri, 21 Apr 2023 11:12:21 -0700 (PDT) Received: from r650-k2.dhcp.broadcom.net ([192.19.144.250]) by smtp-relay.gmail.com with ESMTPS id o21-20020a056870e81500b0017eb57c3417sm397528oan.19.2023.04.21.11.12.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Apr 2023 11:12:21 -0700 (PDT) X-Relaying-Domain: broadcom.com From: Randy Schacher To: dev@dpdk.org Cc: Farah Smith , Shahaji Bhosle Subject: [PATCH v2 04/11] net/bnxt: update Truflow core Date: Fri, 21 Apr 2023 18:11:48 +0000 Message-Id: <20230421181155.2160482-5-stuart.schacher@broadcom.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230421181155.2160482-1-stuart.schacher@broadcom.com> References: <20230421181155.2160482-1-stuart.schacher@broadcom.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org - Add shared session management - Add SRAM session management - Add dynamic TCAM management - Add shared TCAM session management - Add Hot Upgrade support - Update copyright Signed-off-by: Randy Schacher Signed-off-by: Farah Smith Reviewed-by: Shahaji Bhosle --- drivers/net/bnxt/bnxt.h | 1 - drivers/net/bnxt/bnxt_irq.h | 1 - drivers/net/bnxt/bnxt_nvm_defs.h | 1 - drivers/net/bnxt/bnxt_ring.h | 1 - drivers/net/bnxt/bnxt_rxr.h | 1 - drivers/net/bnxt/bnxt_txr.h | 1 - drivers/net/bnxt/bnxt_util.h | 1 - drivers/net/bnxt/tf_core/cfa_resource_types.h | 2 - drivers/net/bnxt/tf_core/cfa_tcam_mgr.c | 2116 +++++++++++++++++ drivers/net/bnxt/tf_core/cfa_tcam_mgr.h | 523 ++++ .../net/bnxt/tf_core/cfa_tcam_mgr_device.h | 101 + .../net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.c | 201 ++ .../net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.h | 28 + drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c | 921 +++++++ drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.h | 20 + drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c | 926 ++++++++ drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.h | 20 + drivers/net/bnxt/tf_core/cfa_tcam_mgr_sbmp.h | 126 + .../net/bnxt/tf_core/cfa_tcam_mgr_session.c | 377 +++ .../net/bnxt/tf_core/cfa_tcam_mgr_session.h | 54 + drivers/net/bnxt/tf_core/meson.build | 36 +- drivers/net/bnxt/tf_core/tf_core.c | 54 +- drivers/net/bnxt/tf_core/tf_core.h | 97 +- drivers/net/bnxt/tf_core/tf_device.c | 18 +- drivers/net/bnxt/tf_core/tf_device.h | 2 +- drivers/net/bnxt/tf_core/tf_device_p4.c | 14 +- drivers/net/bnxt/tf_core/tf_device_p58.c | 84 +- drivers/net/bnxt/tf_core/tf_em_common.c | 2 +- drivers/net/bnxt/tf_core/tf_em_internal.c | 10 +- drivers/net/bnxt/tf_core/tf_identifier.c | 1 + drivers/net/bnxt/tf_core/tf_if_tbl.c | 59 +- drivers/net/bnxt/tf_core/tf_msg.c | 217 +- drivers/net/bnxt/tf_core/tf_msg.h | 38 +- drivers/net/bnxt/tf_core/tf_rm.c | 117 +- drivers/net/bnxt/tf_core/tf_session.c | 112 +- drivers/net/bnxt/tf_core/tf_session.h | 65 +- drivers/net/bnxt/tf_core/tf_sram_mgr.c | 117 +- drivers/net/bnxt/tf_core/tf_sram_mgr.h | 22 +- drivers/net/bnxt/tf_core/tf_tbl.c | 8 +- drivers/net/bnxt/tf_core/tf_tbl_sram.c | 25 +- drivers/net/bnxt/tf_core/tf_tcam.c | 226 +- drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c | 286 +++ drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.h | 49 + drivers/net/bnxt/tf_core/tf_tcam_shared.c | 1146 +-------- drivers/net/bnxt/tf_core/tf_tcam_shared.h | 3 +- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 8 +- 46 files changed, 6686 insertions(+), 1552 deletions(-) create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr.c create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr.h create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_device.h create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.c create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.h create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.h create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.h create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_sbmp.h create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.c create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.h create mode 100644 drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c create mode 100644 drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.h diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 48bd8f2418..2bccdec7e0 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -1044,5 +1044,4 @@ int bnxt_flow_ops_get_op(struct rte_eth_dev *dev, int bnxt_dev_start_op(struct rte_eth_dev *eth_dev); int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev); void bnxt_handle_vf_cfg_change(void *arg); - #endif diff --git a/drivers/net/bnxt/bnxt_irq.h b/drivers/net/bnxt/bnxt_irq.h index e498578968..e2d61bae7a 100644 --- a/drivers/net/bnxt/bnxt_irq.h +++ b/drivers/net/bnxt/bnxt_irq.h @@ -20,5 +20,4 @@ void bnxt_enable_int(struct bnxt *bp); int bnxt_setup_int(struct bnxt *bp); int bnxt_request_int(struct bnxt *bp); void bnxt_int_handler(void *param); - #endif diff --git a/drivers/net/bnxt/bnxt_nvm_defs.h b/drivers/net/bnxt/bnxt_nvm_defs.h index f5ac4e8c84..57ddefa7a1 100644 --- a/drivers/net/bnxt/bnxt_nvm_defs.h +++ b/drivers/net/bnxt/bnxt_nvm_defs.h @@ -66,5 +66,4 @@ enum bnxnvm_pkglog_field_index { BNX_PKG_LOG_FIELD_IDX_INSTALLED_ITEMS = 5, BNX_PKG_LOG_FIELD_IDX_INSTALLED_MASK = 6 }; - #endif /* Don't add anything after this line */ diff --git a/drivers/net/bnxt/bnxt_ring.h b/drivers/net/bnxt/bnxt_ring.h index 3d747aba54..baa60b2627 100644 --- a/drivers/net/bnxt/bnxt_ring.h +++ b/drivers/net/bnxt/bnxt_ring.h @@ -142,5 +142,4 @@ static inline void bnxt_db_cq(struct bnxt_cp_ring_info *cpr) B_CP_DIS_DB(cpr, cp_raw_cons); } } - #endif diff --git a/drivers/net/bnxt/bnxt_rxr.h b/drivers/net/bnxt/bnxt_rxr.h index e132166a18..8e722b7bf0 100644 --- a/drivers/net/bnxt/bnxt_rxr.h +++ b/drivers/net/bnxt/bnxt_rxr.h @@ -386,5 +386,4 @@ bnxt_parse_pkt_type_v2(struct rte_mbuf *mbuf, mbuf->packet_type = pkt_type; } - #endif /* _BNXT_RXR_H_ */ diff --git a/drivers/net/bnxt/bnxt_txr.h b/drivers/net/bnxt/bnxt_txr.h index e11343c082..75456df5bd 100644 --- a/drivers/net/bnxt/bnxt_txr.h +++ b/drivers/net/bnxt/bnxt_txr.h @@ -90,5 +90,4 @@ int bnxt_flush_tx_cmp(struct bnxt_cp_ring_info *cpr); TX_BD_LONG_LFLAGS_IP_CHKSUM) #define TX_BD_FLG_TIP_TCP_UDP_CHKSUM (TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM | \ TX_BD_LONG_LFLAGS_T_IP_CHKSUM) - #endif diff --git a/drivers/net/bnxt/bnxt_util.h b/drivers/net/bnxt/bnxt_util.h index 3437dc75ae..7f5b4c160e 100644 --- a/drivers/net/bnxt/bnxt_util.h +++ b/drivers/net/bnxt/bnxt_util.h @@ -17,5 +17,4 @@ int bnxt_check_zero_bytes(const uint8_t *bytes, int len); void bnxt_eth_hw_addr_random(uint8_t *mac_addr); - #endif /* _BNXT_UTIL_H_ */ diff --git a/drivers/net/bnxt/tf_core/cfa_resource_types.h b/drivers/net/bnxt/tf_core/cfa_resource_types.h index 874d7b834f..8431c778e4 100644 --- a/drivers/net/bnxt/tf_core/cfa_resource_types.h +++ b/drivers/net/bnxt/tf_core/cfa_resource_types.h @@ -63,7 +63,6 @@ #define CFA_RESOURCE_TYPE_P59_VEB_TCAM 0x18UL #define CFA_RESOURCE_TYPE_P59_LAST CFA_RESOURCE_TYPE_P59_VEB_TCAM - /* Meter */ #define CFA_RESOURCE_TYPE_P58_METER 0x0UL /* SRAM_Bank_0 */ @@ -184,7 +183,6 @@ #define CFA_RESOURCE_TYPE_P45_TBL_SCOPE 0x23UL #define CFA_RESOURCE_TYPE_P45_LAST CFA_RESOURCE_TYPE_P45_TBL_SCOPE - /* Multicast Group */ #define CFA_RESOURCE_TYPE_P4_MCG 0x0UL /* Encap 8 byte record */ diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c new file mode 100644 index 0000000000..f26d93e7a9 --- /dev/null +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c @@ -0,0 +1,2116 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2021-2023 Broadcom + * All rights reserved. + */ + +#include +#include + +#include "hcapi_cfa_defs.h" + +#include "tfp.h" +#include "tf_session.h" +#include "tf_util.h" +#include "cfa_tcam_mgr.h" +#include "cfa_tcam_mgr_hwop_msg.h" +#include "cfa_tcam_mgr_device.h" +#include "cfa_tcam_mgr_session.h" +#include "cfa_tcam_mgr_p58.h" +#include "cfa_tcam_mgr_p4.h" + +#define TF_TCAM_SLICE_INVALID (-1) + +/* + * The following macros are for setting the entry status in a row entry. + * row is (struct cfa_tcam_mgr_table_rows_0 *) + */ +#define ROW_ENTRY_INUSE(row, entry) ((row)->entry_inuse & (1U << (entry))) +#define ROW_ENTRY_SET(row, entry) ((row)->entry_inuse |= (1U << (entry))) +#define ROW_ENTRY_CLEAR(row, entry) ((row)->entry_inuse &= ~(1U << (entry))) +#define ROW_INUSE(row) ((row)->entry_inuse != 0) + +static struct cfa_tcam_mgr_entry_data *entry_data[TF_TCAM_MAX_SESSIONS]; + +static int global_data_initialized[TF_TCAM_MAX_SESSIONS]; +int cfa_tcam_mgr_max_entries[TF_TCAM_MAX_SESSIONS]; + +struct cfa_tcam_mgr_table_data +cfa_tcam_mgr_tables[TF_TCAM_MAX_SESSIONS][TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX]; + +static int physical_table_types[CFA_TCAM_MGR_TBL_TYPE_MAX] = { + [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS] = + TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS] = + TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS] = + TF_TCAM_TBL_TYPE_PROF_TCAM, + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS] = + TF_TCAM_TBL_TYPE_WC_TCAM, + [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS] = + TF_TCAM_TBL_TYPE_SP_TCAM, + [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS] = + TF_TCAM_TBL_TYPE_CT_RULE_TCAM, + [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS] = + TF_TCAM_TBL_TYPE_VEB_TCAM, + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS] = + TF_TCAM_TBL_TYPE_WC_TCAM_HIGH, + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS] = + TF_TCAM_TBL_TYPE_WC_TCAM_LOW, +}; + +int +cfa_tcam_mgr_get_phys_table_type(enum cfa_tcam_mgr_tbl_type type) +{ + if (type >= CFA_TCAM_MGR_TBL_TYPE_MAX) + assert(0); + else + return physical_table_types[type]; +} + +const char * +cfa_tcam_mgr_tbl_2_str(enum cfa_tcam_mgr_tbl_type tcam_type) +{ + switch (tcam_type) { + case CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM: + return "l2_ctxt_tcam_high AFM"; + case CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS: + return "l2_ctxt_tcam_high Apps"; + case CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_AFM: + return "l2_ctxt_tcam_low AFM"; + case CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS: + return "l2_ctxt_tcam_low Apps"; + case CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_AFM: + return "prof_tcam AFM"; + case CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS: + return "prof_tcam Apps"; + case CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_AFM: + return "wc_tcam AFM"; + case CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS: + return "wc_tcam Apps"; + case CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_AFM: + return "veb_tcam AFM"; + case CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS: + return "veb_tcam Apps"; + case CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_AFM: + return "sp_tcam AFM"; + case CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS: + return "sp_tcam Apps"; + case CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_AFM: + return "ct_rule_tcam AFM"; + case CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS: + return "ct_rule_tcam Apps"; + case CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_AFM: + return "wc_tcam_high AFM"; + case CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS: + return "wc_tcam_high Apps"; + case CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_AFM: + return "wc_tcam_low AFM"; + case CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS: + return "wc_tcam_low Apps"; + default: + return "Invalid tcam table type"; + } +} + +/* key_size and slice_width are in bytes */ +static int +cfa_tcam_mgr_get_num_slices(unsigned int key_size, unsigned int slice_width) +{ + int num_slices = 0; + + if (key_size == 0) + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + + num_slices = ((key_size - 1U) / slice_width) + 1U; + /* Round up to next highest power of 2 */ + /* This is necessary since, for example, 3 slices is not a valid entry + * width. + */ + num_slices--; + /* Repeat to maximum number of bits actually used */ + /* This fills in all the bits. */ + num_slices |= num_slices >> 1; + num_slices |= num_slices >> 2; + num_slices |= num_slices >> 4; + /* + * If the maximum number of slices that are supported by the HW + * increases, then additional shifts are needed. + */ + num_slices++; + return num_slices; +} + +static struct cfa_tcam_mgr_entry_data * +cfa_tcam_mgr_entry_get(int sess_idx, uint16_t id) +{ + if (id > cfa_tcam_mgr_max_entries[sess_idx]) + return NULL; + + return &entry_data[sess_idx][id]; +} + +/* Insert an entry into the entry table */ +static int +cfa_tcam_mgr_entry_insert(int sess_idx, uint16_t id, + struct cfa_tcam_mgr_entry_data *entry) +{ + if (id > cfa_tcam_mgr_max_entries[sess_idx]) + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + + memcpy(&entry_data[sess_idx][id], entry, + sizeof(entry_data[sess_idx][id])); + + return 0; +} + +/* Delete an entry from the entry table */ +static int +cfa_tcam_mgr_entry_delete(int sess_idx, uint16_t id) +{ + if (id > cfa_tcam_mgr_max_entries[sess_idx]) + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + + memset(&entry_data[sess_idx][id], 0, sizeof(entry_data[sess_idx][id])); + + return 0; +} + +/* Returns the size of the row structure taking into account how many slices a + * TCAM supports. + */ +static int +cfa_tcam_mgr_row_size_get(int sess_idx, enum tf_dir dir, + enum cfa_tcam_mgr_tbl_type type) +{ + return sizeof(struct cfa_tcam_mgr_table_rows_0) + + (cfa_tcam_mgr_tables[sess_idx][dir][type].max_slices * + sizeof(((struct cfa_tcam_mgr_table_rows_0 *)0)->entries[0])); +} + +static void * +cfa_tcam_mgr_row_ptr_get(void *base, int index, int row_size) +{ + return (uint8_t *)base + (index * row_size); +} + +/* + * Searches a table to find the direction and type of an entry. + */ +static int +cfa_tcam_mgr_entry_find_in_table(int sess_idx, int id, enum tf_dir dir, + enum cfa_tcam_mgr_tbl_type type) +{ + struct cfa_tcam_mgr_table_data *table_data; + struct cfa_tcam_mgr_table_rows_0 *row; + int max_slices, row_idx, row_size, slice; + + table_data = &cfa_tcam_mgr_tables[sess_idx][dir][type]; + if (table_data->max_entries > 0 && + table_data->hcapi_type > 0) { + max_slices = table_data->max_slices; + row_size = cfa_tcam_mgr_row_size_get(sess_idx, dir, type); + for (row_idx = table_data->start_row; + row_idx <= table_data->end_row; + row_idx++) { + row = cfa_tcam_mgr_row_ptr_get(table_data->tcam_rows, + row_idx, row_size); + if (!ROW_INUSE(row)) + continue; + for (slice = 0; + slice < (max_slices / row->entry_size); + slice++) { + if (!ROW_ENTRY_INUSE(row, slice)) + continue; + if (row->entries[slice] == id) + return 0; + } + } + } + + return -CFA_TCAM_MGR_ERR_CODE(NOENT); +} + +/* + * Searches all the tables to find the direction and type of an entry. + */ +static int +cfa_tcam_mgr_entry_find(int sess_idx, int id, enum tf_dir *tbl_dir, + enum cfa_tcam_mgr_tbl_type *tbl_type) +{ + enum tf_dir dir; + enum cfa_tcam_mgr_tbl_type type; + int rc = -CFA_TCAM_MGR_ERR_CODE(NOENT); + + for (dir = TF_DIR_RX; dir < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx]); dir++) { + for (type = CFA_TCAM_MGR_TBL_TYPE_START; + type < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx][dir]); + type++) { + rc = cfa_tcam_mgr_entry_find_in_table(sess_idx, id, dir, type); + if (rc == 0) { + *tbl_dir = dir; + *tbl_type = type; + return rc; + } + } + } + + return rc; +} + +static int +cfa_tcam_mgr_row_is_entry_free(struct cfa_tcam_mgr_table_rows_0 *row, + int max_slices, + int key_slices) +{ + int j; + + if (ROW_INUSE(row) && + row->entry_size == key_slices) { + for (j = 0; j < (max_slices / row->entry_size); j++) { + if (!ROW_ENTRY_INUSE(row, j)) + return j; + } + } + return -1; +} + +static int +cfa_tcam_mgr_entry_move(int sess_idx, struct cfa_tcam_mgr_context *context, + enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type, + int entry_id, + struct cfa_tcam_mgr_table_data *table_data, + int dest_row_index, int dest_row_slice, + struct cfa_tcam_mgr_table_rows_0 *dest_row, + int source_row_index, + struct cfa_tcam_mgr_table_rows_0 *source_row, + bool free_source_entry) +{ + struct cfa_tcam_mgr_get_parms gparms = { 0 }; + struct cfa_tcam_mgr_set_parms sparms = { 0 }; + struct cfa_tcam_mgr_free_parms fparms = { 0 }; + struct cfa_tcam_mgr_entry_data *entry; + uint8_t key[CFA_TCAM_MGR_MAX_KEY_SIZE]; + uint8_t mask[CFA_TCAM_MGR_MAX_KEY_SIZE]; + uint8_t result[CFA_TCAM_MGR_MAX_KEY_SIZE]; + + int j, rc; + + entry = cfa_tcam_mgr_entry_get(sess_idx, entry_id); + if (entry == NULL) + return -1; + + gparms.dir = dir; + gparms.type = type; + gparms.hcapi_type = table_data->hcapi_type; + gparms.key = key; + gparms.mask = mask; + gparms.result = result; + gparms.id = source_row->entries[entry->slice]; + gparms.key_size = sizeof(key); + gparms.result_size = sizeof(result); + + rc = cfa_tcam_mgr_entry_get_msg(sess_idx, context, &gparms, + source_row_index, + entry->slice * source_row->entry_size, + table_data->max_slices); + if (rc != 0) + return rc; + + sparms.dir = dir; + sparms.type = type; + sparms.hcapi_type = table_data->hcapi_type; + sparms.key = key; + sparms.mask = mask; + sparms.result = result; + sparms.id = gparms.id; + sparms.key_size = gparms.key_size; + sparms.result_size = gparms.result_size; + + /* Slice in destination row not specified. Find first free slice. */ + if (dest_row_slice < 0) + for (j = 0; + j < (table_data->max_slices / dest_row->entry_size); + j++) { + if (!ROW_ENTRY_INUSE(dest_row, j)) { + dest_row_slice = j; + break; + } + } + + /* If no free slice found, return error. */ + if (dest_row_slice < 0) + return -CFA_TCAM_MGR_ERR_CODE(PERM); + + rc = cfa_tcam_mgr_entry_set_msg(sess_idx, context, &sparms, + dest_row_index, + dest_row_slice * dest_row->entry_size, + table_data->max_slices); + if (rc != 0) + return rc; + + if (free_source_entry) { + fparms.dir = dir; + fparms.type = type; + fparms.hcapi_type = table_data->hcapi_type; + rc = cfa_tcam_mgr_entry_free_msg(sess_idx, context, &fparms, + source_row_index, + entry->slice * + dest_row->entry_size, + table_data->row_width / + table_data->max_slices * + source_row->entry_size, + table_data->result_size, + table_data->max_slices); + if (rc != 0) { + CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, + dir, type, + "Failed to free entry ID %d at" + " row %d, slice %d for sess_idx %d. rc: %d.\n", + gparms.id, + source_row_index, + entry->slice, + sess_idx, + -rc); + } + } + + ROW_ENTRY_SET(dest_row, dest_row_slice); + dest_row->entries[dest_row_slice] = entry_id; + ROW_ENTRY_CLEAR(source_row, entry->slice); + entry->row = dest_row_index; + entry->slice = dest_row_slice; + + return 0; +} + +static int +cfa_tcam_mgr_row_move(int sess_idx, struct cfa_tcam_mgr_context *context, + enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type, + struct cfa_tcam_mgr_table_data *table_data, + int dest_row_index, + struct cfa_tcam_mgr_table_rows_0 *dest_row, + int source_row_index, + struct cfa_tcam_mgr_table_rows_0 *source_row) +{ + struct cfa_tcam_mgr_free_parms fparms = { 0 }; + int j, rc; + + dest_row->priority = source_row->priority; + dest_row->entry_size = source_row->entry_size; + dest_row->entry_inuse = 0; + + fparms.dir = dir; + fparms.type = type; + fparms.hcapi_type = table_data->hcapi_type; + + for (j = 0; + j < (table_data->max_slices / source_row->entry_size); + j++) { + if (ROW_ENTRY_INUSE(source_row, j)) { + cfa_tcam_mgr_entry_move(sess_idx, context, dir, type, + source_row->entries[j], + table_data, + dest_row_index, j, dest_row, + source_row_index, source_row, + true); + } else { + /* Slice not in use, write an empty slice. */ + rc = cfa_tcam_mgr_entry_free_msg(sess_idx, context, &fparms, + dest_row_index, + j * + dest_row->entry_size, + table_data->row_width / + table_data->max_slices * + dest_row->entry_size, + table_data->result_size, + table_data->max_slices); + if (rc != 0) + return rc; + } + } + + return 0; +} + +/* Install entry into in-memory tables, not into TCAM (yet). */ +static void +cfa_tcam_mgr_row_entry_install(int sess_idx, + struct cfa_tcam_mgr_table_rows_0 *row, + struct cfa_tcam_mgr_alloc_parms *parms, + struct cfa_tcam_mgr_entry_data *entry, + uint16_t id, + int key_slices, + int row_index, int slice) +{ + if (global_data_initialized[sess_idx] == 0) { + CFA_TCAM_MGR_LOG(INFO, "PANIC: No TCAM data created for sess_idx %d\n", + sess_idx); + return; + } + + if (slice == TF_TCAM_SLICE_INVALID) { + slice = 0; + row->entry_size = key_slices; + row->priority = parms->priority; + } + + ROW_ENTRY_SET(row, slice); + row->entries[slice] = id; + entry->row = row_index; + entry->slice = slice; +} + +/* Finds an empty row that can be used and reserve for entry. If necessary, + * entries will be shuffled in order to make room. + */ +static struct cfa_tcam_mgr_table_rows_0 * +cfa_tcam_mgr_empty_row_alloc(int sess_idx, struct cfa_tcam_mgr_context *context, + struct cfa_tcam_mgr_alloc_parms *parms, + struct cfa_tcam_mgr_entry_data *entry, + uint16_t id, + int key_slices) +{ + struct cfa_tcam_mgr_table_rows_0 *tcam_rows; + struct cfa_tcam_mgr_table_rows_0 *from_row; + struct cfa_tcam_mgr_table_rows_0 *to_row; + struct cfa_tcam_mgr_table_rows_0 *row; + struct cfa_tcam_mgr_table_data *table_data; + int i, max_slices, row_size; + int to_row_idx, from_row_idx, slice, start_row, end_row; + int empty_row = -1; + int target_row = -1; + + table_data = &cfa_tcam_mgr_tables[sess_idx][parms->dir][parms->type]; + + start_row = table_data->start_row; + end_row = table_data->end_row; + max_slices = table_data->max_slices; + tcam_rows = table_data->tcam_rows; + + row_size = cfa_tcam_mgr_row_size_get(sess_idx, parms->dir, parms->type); + + /* + * First check for partially used entries, but only if the key needs + * fewer slices than there are in a row. + */ + if (key_slices < max_slices) { + for (i = start_row; i <= end_row; i++) { + row = cfa_tcam_mgr_row_ptr_get(tcam_rows, i, row_size); + if (!ROW_INUSE(row)) + continue; + if (row->priority < parms->priority) + break; + if (row->priority > parms->priority) + continue; + slice = cfa_tcam_mgr_row_is_entry_free(row, + max_slices, + key_slices); + if (slice >= 0) { + cfa_tcam_mgr_row_entry_install(sess_idx, row, parms, + entry, id, + key_slices, + i, slice); + return row; + } + } + } + + /* No partially used rows available. Find an empty row, if any. */ + + /* + * All max priority entries are placed in the beginning of the TCAM. It + * should not be necessary to shuffle any of these entries. All other + * priorities are placed from the end of the TCAM and may require + * shuffling. + */ + if (parms->priority == TF_TCAM_PRIORITY_MAX) { + /* Handle max priority first. */ + for (i = start_row; i <= end_row; i++) { + row = cfa_tcam_mgr_row_ptr_get(tcam_rows, i, row_size); + if (!ROW_INUSE(row)) { + cfa_tcam_mgr_row_entry_install(sess_idx, + row, parms, + entry, + id, key_slices, + i, + TF_TCAM_SLICE_INVALID); + return row; + } + if (row->priority < parms->priority) { + /* + * No free entries before priority change, table + * is full. + */ + return NULL; + } + } + /* No free entries found, table is full. */ + return NULL; + } + + /* Use the highest available entry */ + for (i = end_row; i >= start_row; i--) { + row = cfa_tcam_mgr_row_ptr_get(tcam_rows, i, row_size); + if (!ROW_INUSE(row)) { + empty_row = i; + break; + } + + if (row->priority > parms->priority && + target_row < 0) + target_row = i; + } + + if (empty_row < 0) { + /* No free entries found, table is full. */ + return NULL; + } + + if (target_row < 0) { + /* + * Did not find a row with higher priority before unused row so + * just install new entry in empty_row. + */ + row = cfa_tcam_mgr_row_ptr_get(tcam_rows, empty_row, row_size); + cfa_tcam_mgr_row_entry_install(sess_idx, row, parms, entry, id, + key_slices, empty_row, + TF_TCAM_SLICE_INVALID); + return row; + } + + to_row_idx = empty_row; + to_row = cfa_tcam_mgr_row_ptr_get(tcam_rows, to_row_idx, row_size); + while (to_row_idx < target_row) { + from_row_idx = to_row_idx + 1; + from_row = cfa_tcam_mgr_row_ptr_get(tcam_rows, from_row_idx, + row_size); + /* + * Find the highest row with the same priority as the initial + * source row (from_row). It's only necessary to copy one row + * of each priority. + */ + for (i = from_row_idx + 1; i <= target_row; i++) { + row = cfa_tcam_mgr_row_ptr_get(tcam_rows, i, row_size); + if (row->priority != from_row->priority) + break; + from_row_idx = i; + from_row = row; + } + cfa_tcam_mgr_row_move(sess_idx, context, parms->dir, parms->type, + table_data, to_row_idx, to_row, + from_row_idx, from_row); + to_row = from_row; + to_row_idx = from_row_idx; + } + to_row = cfa_tcam_mgr_row_ptr_get(tcam_rows, target_row, row_size); + memset(to_row, 0, row_size); + cfa_tcam_mgr_row_entry_install(sess_idx, to_row, parms, entry, id, + key_slices, target_row, + TF_TCAM_SLICE_INVALID); + + return row; +} + +/* + * This function will combine rows when possible to result in the fewest rows + * used necessary for the entries that are installed. + */ +static void +cfa_tcam_mgr_rows_combine(int sess_idx, struct cfa_tcam_mgr_context *context, + struct cfa_tcam_mgr_free_parms *parms, + struct cfa_tcam_mgr_table_data *table_data, + int changed_row_index) +{ + struct cfa_tcam_mgr_table_rows_0 *from_row = NULL; + struct cfa_tcam_mgr_table_rows_0 *to_row; + struct cfa_tcam_mgr_table_rows_0 *tcam_rows; + int i, j, row_size; + int to_row_idx, from_row_idx, start_row, end_row, max_slices; + bool entry_moved = false; + + start_row = table_data->start_row; + end_row = table_data->end_row; + max_slices = table_data->max_slices; + tcam_rows = table_data->tcam_rows; + + row_size = cfa_tcam_mgr_row_size_get(sess_idx, parms->dir, parms->type); + + from_row_idx = changed_row_index; + from_row = cfa_tcam_mgr_row_ptr_get(tcam_rows, from_row_idx, row_size); + + if (ROW_INUSE(from_row)) { + /* + * Row is still in partial use. See if remaining entry(s) can + * be moved to free up a row. + */ + for (i = 0; i < (max_slices / from_row->entry_size); i++) { + if (!ROW_ENTRY_INUSE(from_row, i)) + continue; + for (to_row_idx = end_row; + to_row_idx >= start_row; + to_row_idx--) { + to_row = cfa_tcam_mgr_row_ptr_get(tcam_rows, + to_row_idx, + row_size); + if (!ROW_INUSE(to_row)) + continue; + if (to_row->priority > from_row->priority) + break; + if (to_row->priority != from_row->priority) + continue; + if (to_row->entry_size != from_row->entry_size) + continue; + if (to_row_idx == changed_row_index) + continue; + for (j = 0; + j < (max_slices / to_row->entry_size); + j++) { + if (!ROW_ENTRY_INUSE(to_row, j)) { + cfa_tcam_mgr_entry_move + (sess_idx, + context, + parms->dir, + parms->type, + from_row->entries[i], + table_data, + to_row_idx, + -1, to_row, + from_row_idx, + from_row, + true); + entry_moved = true; + break; + } + } + if (entry_moved) + break; + } + if (ROW_INUSE(from_row)) + entry_moved = false; + else + break; + } + } +} + +/* + * This function will ensure that all rows, except those of the highest + * priority, at the end of the table. When this function is finished, all the + * empty rows should be between the highest priority rows at the beginning of + * the table and the rest of the rows with lower priorities. + */ +/* + * Will need to free the row left newly empty as a result of moving. + * + * Return row to free to caller. If new_row_to_free < 0, then no new row to + * free. + */ +static void +cfa_tcam_mgr_rows_compact(int sess_idx, struct cfa_tcam_mgr_context *context, + struct cfa_tcam_mgr_free_parms *parms, + struct cfa_tcam_mgr_table_data *table_data, + int *new_row_to_free, + int changed_row_index) +{ + struct cfa_tcam_mgr_table_rows_0 *from_row = NULL; + struct cfa_tcam_mgr_table_rows_0 *to_row; + struct cfa_tcam_mgr_table_rows_0 *row; + struct cfa_tcam_mgr_table_rows_0 *tcam_rows; + int i, row_size, priority; + int to_row_idx = 0, from_row_idx = 0, start_row = 0, end_row = 0; + + *new_row_to_free = -1; + + start_row = table_data->start_row; + end_row = table_data->end_row; + tcam_rows = table_data->tcam_rows; + + row_size = cfa_tcam_mgr_row_size_get(sess_idx, parms->dir, parms->type); + + /* + * The row is no longer in use, so see if rows need to be moved in order + * to not leave any gaps. + */ + to_row_idx = changed_row_index; + to_row = cfa_tcam_mgr_row_ptr_get(tcam_rows, to_row_idx, row_size); + + priority = to_row->priority; + if (priority == TF_TCAM_PRIORITY_MAX) { + if (changed_row_index == end_row) + /* + * Nothing to move - the last row in the TCAM is being + * deleted. + */ + return; + for (i = changed_row_index + 1; i <= end_row; i++) { + row = cfa_tcam_mgr_row_ptr_get(tcam_rows, i, row_size); + if (!ROW_INUSE(row)) + break; + + if (row->priority < priority) + break; + + from_row = row; + from_row_idx = i; + } + } else { + if (changed_row_index == start_row) + /* + * Nothing to move - the first row in the TCAM is being + * deleted. + */ + return; + for (i = changed_row_index - 1; i >= start_row; i--) { + row = cfa_tcam_mgr_row_ptr_get(tcam_rows, i, row_size); + if (!ROW_INUSE(row)) + break; + + if (row->priority > priority) { + /* Don't move the highest priority rows. */ + if (row->priority == TF_TCAM_PRIORITY_MAX) + break; + /* + * If from_row is NULL, that means that there + * were no rows of the deleted priority. + * Nothing to move yet. + * + * If from_row is not NULL, then it is the last + * row with the same priority and must be moved + * to fill the newly empty (by free or by move) + * row. + */ + if (from_row != NULL) { + cfa_tcam_mgr_row_move(sess_idx, context, + parms->dir, + parms->type, + table_data, + to_row_idx, to_row, + from_row_idx, + from_row); + *new_row_to_free = from_row_idx; + to_row = from_row; + to_row_idx = from_row_idx; + } + + priority = row->priority; + } + from_row = row; + from_row_idx = i; + } + } + + if (from_row != NULL) { + cfa_tcam_mgr_row_move(sess_idx, context, parms->dir, parms->type, + table_data, + to_row_idx, to_row, + from_row_idx, from_row); + *new_row_to_free = from_row_idx; + } +} + +/* + * This function is to set table limits for the logical TCAM tables. + */ +static int +cfa_tcam_mgr_table_limits_set(int sess_idx, struct cfa_tcam_mgr_init_parms *parms) +{ + struct cfa_tcam_mgr_table_data *table_data; + unsigned int dir, type; + int start, stride; + + if (parms == NULL) + return 0; + + for (dir = 0; dir < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx]); dir++) + for (type = 0; + type < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx][dir]); + type++) { + table_data = &cfa_tcam_mgr_tables[sess_idx][dir][type]; + /* + * If num_rows is zero, then TCAM Manager did not + * allocate any row storage for that table so cannot + * manage it. + */ + if (table_data->num_rows == 0) + continue; + start = parms->resc[dir][type].start; + stride = parms->resc[dir][type].stride; + if (start % table_data->max_slices > 0) { + CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, dir, type, + "Start of resources (%d) for table (%d) " + "does not begin on row boundary.\n", + start, sess_idx); + CFA_TCAM_MGR_LOG_DIR(ERR, dir, + "Start is %d, number of slices " + "is %d.\n", + start, + table_data->max_slices); + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + } + if (stride % table_data->max_slices > 0) { + CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, dir, type, + "Stride of resources (%d) for table (%d)" + " does not end on row boundary.\n", + stride, sess_idx); + CFA_TCAM_MGR_LOG_DIR(ERR, dir, + "Stride is %d, number of " + "slices is %d.\n", + stride, + table_data->max_slices); + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + } + if (stride == 0) { + table_data->start_row = 0; + table_data->end_row = 0; + table_data->max_entries = 0; + } else { + table_data->start_row = start / + table_data->max_slices; + table_data->end_row = table_data->start_row + + (stride / table_data->max_slices) - 1; + table_data->max_entries = + table_data->max_slices * + (table_data->end_row - + table_data->start_row + 1); + } + } + + return 0; +} + +int +cfa_tcam_mgr_init(int sess_idx, enum cfa_tcam_mgr_device_type type, + struct cfa_tcam_mgr_init_parms *parms) +{ + struct cfa_tcam_mgr_table_data *table_data; + unsigned int dir, tbl_type; + int rc; + + switch (type) { + case CFA_TCAM_MGR_DEVICE_TYPE_P4: + case CFA_TCAM_MGR_DEVICE_TYPE_SR: + rc = cfa_tcam_mgr_init_p4(sess_idx, &entry_data[sess_idx]); + break; + case CFA_TCAM_MGR_DEVICE_TYPE_P5: + rc = cfa_tcam_mgr_init_p58(sess_idx, &entry_data[sess_idx]); + break; + default: + CFA_TCAM_MGR_LOG(ERR, "No such device %d for sess_idx %d\n", + type, sess_idx); + return -CFA_TCAM_MGR_ERR_CODE(NODEV); + } + if (rc < 0) + return rc; + + rc = cfa_tcam_mgr_table_limits_set(sess_idx, parms); + if (rc < 0) + return rc; + + /* Now calculate the max entries per table and global max entries based + * on the updated table limits. + */ + for (dir = 0; dir < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx]); dir++) + for (tbl_type = 0; + tbl_type < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx][dir]); + tbl_type++) { + table_data = &cfa_tcam_mgr_tables[sess_idx][dir][tbl_type]; + /* + * If num_rows is zero, then TCAM Manager did not + * allocate any row storage for that table so cannot + * manage it. + */ + if (table_data->num_rows == 0) { + table_data->start_row = 0; + table_data->end_row = 0; + table_data->max_entries = 0; + } else if (table_data->end_row >= + table_data->num_rows) { + CFA_TCAM_MGR_LOG_DIR_TYPE(EMERG, dir, tbl_type, + "End row is out of " + "range (%d >= %d) for sess_idx %d\n", + table_data->end_row, + table_data->num_rows, + sess_idx); + return -CFA_TCAM_MGR_ERR_CODE(FAULT); + } else if (table_data->max_entries == 0 && + table_data->start_row == 0 && + table_data->end_row == 0) { + /* Nothing to do */ + } else { + table_data->max_entries = + table_data->max_slices * + (table_data->end_row - + table_data->start_row + 1); + } + cfa_tcam_mgr_max_entries[sess_idx] += table_data->max_entries; + } + + rc = cfa_tcam_mgr_hwops_init(type); + if (rc < 0) + return rc; + + rc = cfa_tcam_mgr_session_init(sess_idx, type); + if (rc < 0) + return rc; + + global_data_initialized[sess_idx] = 1; + + if (parms != NULL) + parms->max_entries = cfa_tcam_mgr_max_entries[sess_idx]; + + CFA_TCAM_MGR_LOG(INFO, "Global TCAM table initialized for sess_idx %d.\n", + sess_idx); + + return 0; +} + +int +cfa_tcam_mgr_qcaps(struct cfa_tcam_mgr_context *context __rte_unused, + struct cfa_tcam_mgr_qcaps_parms *parms) +{ + unsigned int type; + int rc, sess_idx; + uint32_t session_id; + + CFA_TCAM_MGR_CHECK_PARMS2(context, parms); + + rc = cfa_tcam_mgr_get_session_from_context(context, &session_id); + if (rc < 0) + return rc; + + sess_idx = cfa_tcam_mgr_session_find(session_id); + if (sess_idx < 0) { + CFA_TCAM_MGR_LOG_0(ERR, "Session not found.\n"); + return sess_idx; + } + + if (global_data_initialized[sess_idx] == 0) { + CFA_TCAM_MGR_LOG(ERR, "PANIC: No TCAM data created for sess_idx %d\n", + sess_idx); + return -CFA_TCAM_MGR_ERR_CODE(PERM); + } + + /* + * This code will indicate if TCAM Manager is managing a logical TCAM + * table or not. If not, then the physical TCAM will have to be + * accessed using the traditional methods. + */ + parms->rx_tcam_supported = 0; + parms->tx_tcam_supported = 0; + for (type = 0; type < CFA_TCAM_MGR_TBL_TYPE_MAX; type++) { + if (cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX][type].max_entries > 0 && + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX][type].hcapi_type > 0) + parms->rx_tcam_supported |= 1 << cfa_tcam_mgr_get_phys_table_type(type); + if (cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX][type].max_entries > 0 && + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX][type].hcapi_type > 0) + parms->tx_tcam_supported |= 1 << cfa_tcam_mgr_get_phys_table_type(type); + } + + return 0; +} + +/* + * Manipulate the tables to split the WC TCAM into HIGH and LOW ranges + * and also update the sizes in the tcam count array + */ +static int +cfa_tcam_mgr_shared_wc_bind(uint32_t sess_idx, bool dual_ha_app, + uint16_t tcam_cnt[][CFA_TCAM_MGR_TBL_TYPE_MAX]) +{ + uint16_t start_row, end_row, max_entries, slices; + uint16_t num_pools = dual_ha_app ? 4 : 2; + enum tf_dir dir; + int rc; + + for (dir = 0; dir < TF_DIR_MAX; dir++) { + rc = cfa_tcam_mgr_tables_get(sess_idx, dir, + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS, + &start_row, &end_row, &max_entries, &slices); + if (rc) + return rc; + if (max_entries) { + rc = cfa_tcam_mgr_tables_set(sess_idx, dir, + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS, + start_row, + start_row + + ((max_entries / slices) / num_pools) - 1, + max_entries / num_pools); + if (rc) + return rc; + rc = cfa_tcam_mgr_tables_set(sess_idx, dir, + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS, + start_row + + ((max_entries / slices) / num_pools), + start_row + + (max_entries / slices) - 1, + max_entries / num_pools); + if (rc) + return rc; + rc = cfa_tcam_mgr_tables_set(sess_idx, dir, + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS, + 0, 0, 0); + if (rc) + return rc; + tcam_cnt[dir][CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS] = + max_entries / num_pools; + tcam_cnt[dir][CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS] = + max_entries / num_pools; + tcam_cnt[dir][CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS] = 0; + } + } + + return 0; +} + +int +cfa_tcam_mgr_bind(struct cfa_tcam_mgr_context *context, + struct cfa_tcam_mgr_cfg_parms *parms) +{ + struct cfa_tcam_mgr_table_data *table_data; + struct tf_dev_info *dev; + unsigned int dir; + int rc, sess_idx; + uint32_t session_id; + struct tf_session *tfs; + unsigned int type; + int prev_max_entries; + int start, stride; + enum cfa_tcam_mgr_device_type device_type; + + CFA_TCAM_MGR_CHECK_PARMS2(context, parms); + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(context->tfp, &tfs); + if (rc) + return rc; + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) + return rc; + + switch (dev->type) { + case TF_DEVICE_TYPE_P4: + device_type = CFA_TCAM_MGR_DEVICE_TYPE_P4; + break; + case TF_DEVICE_TYPE_SR: + device_type = CFA_TCAM_MGR_DEVICE_TYPE_SR; + break; + case TF_DEVICE_TYPE_P5: + device_type = CFA_TCAM_MGR_DEVICE_TYPE_P5; + break; + default: + CFA_TCAM_MGR_LOG(ERR, "No such device %d\n", dev->type); + return -CFA_TCAM_MGR_ERR_CODE(NODEV); + } + + rc = cfa_tcam_mgr_get_session_from_context(context, &session_id); + if (rc < 0) + return rc; + + sess_idx = cfa_tcam_mgr_session_add(session_id); + if (sess_idx < 0) + return sess_idx; + + if (global_data_initialized[sess_idx] == 0) { + rc = cfa_tcam_mgr_init(sess_idx, device_type, NULL); + if (rc < 0) + return rc; + } + + if (parms->num_elements != ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx][dir])) { + CFA_TCAM_MGR_LOG(ERR, + "Session element count (%d) differs " + "from table count (%zu) for sess_idx %d.\n", + parms->num_elements, + ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx][dir]), + sess_idx); + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + } + + /* + * Only managing one session. resv_res contains the resources allocated + * to this session by the resource manager. Update the limits on TCAMs. + */ + for (dir = 0; dir < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx]); dir++) { + for (type = 0; + type < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx][dir]); + type++) { + table_data = &cfa_tcam_mgr_tables[sess_idx][dir][type]; + prev_max_entries = table_data->max_entries; + /* + * In AFM logical tables, max_entries is initialized to + * zero. These logical tables are not used when TCAM + * Manager is in the core so skip. + */ + if (prev_max_entries == 0) + continue; + start = parms->resv_res[dir][type].start; + stride = parms->resv_res[dir][type].stride; + if (start % table_data->max_slices > 0) { + CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, dir, type, + "Start of resources (%d) for table(%d) " + "does not begin on row boundary.\n", + start, sess_idx); + CFA_TCAM_MGR_LOG_DIR(ERR, dir, + "Start is %d, number of slices " + "is %d.\n", + start, + table_data->max_slices); + (void)cfa_tcam_mgr_session_free(session_id, context); + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + } + if (stride % table_data->max_slices > 0) { + CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, dir, type, + "Stride of resources (%d) for table(%d) " + "does not end on row boundary.\n", + stride, sess_idx); + CFA_TCAM_MGR_LOG_DIR(ERR, dir, + "Stride is %d, number of " + "slices is %d.\n", + stride, + table_data->max_slices); + (void)cfa_tcam_mgr_session_free(session_id, context); + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + } + if (stride == 0) { + table_data->start_row = 0; + table_data->end_row = 0; + table_data->max_entries = 0; + } else { + table_data->start_row = start / + table_data->max_slices; + table_data->end_row = table_data->start_row + + (stride / table_data->max_slices) - 1; + table_data->max_entries = + table_data->max_slices * + (table_data->end_row - + table_data->start_row + 1); + } + cfa_tcam_mgr_max_entries[sess_idx] += (table_data->max_entries - + prev_max_entries); + } + } + + if (tf_session_is_shared_hotup_session(tfs)) { + rc = cfa_tcam_mgr_shared_wc_bind(sess_idx, false, parms->tcam_cnt); + if (rc) { + (void)cfa_tcam_mgr_session_free(session_id, context); + return rc; + } + } + + rc = cfa_tcam_mgr_session_cfg(session_id, parms->tcam_cnt); + if (rc < 0) { + (void)cfa_tcam_mgr_session_free(session_id, context); + return rc; + } + + return 0; +} + +int +cfa_tcam_mgr_unbind(struct cfa_tcam_mgr_context *context) +{ + int rc, sess_idx; + uint32_t session_id; + + CFA_TCAM_MGR_CHECK_PARMS1(context); + + rc = cfa_tcam_mgr_get_session_from_context(context, &session_id); + if (rc < 0) + return rc; + + sess_idx = cfa_tcam_mgr_session_find(session_id); + if (sess_idx < 0) { + CFA_TCAM_MGR_LOG_0(ERR, "Session not found.\n"); + return sess_idx; + } + + if (global_data_initialized[sess_idx] == 0) { + CFA_TCAM_MGR_LOG(INFO, "PANIC: No TCAM data created for sess_idx %d\n", + sess_idx); + return -CFA_TCAM_MGR_ERR_CODE(PERM); + } + + (void)cfa_tcam_mgr_session_free(session_id, context); + + global_data_initialized[sess_idx] = 0; + return 0; +} + +int +cfa_tcam_mgr_alloc(struct cfa_tcam_mgr_context *context, + struct cfa_tcam_mgr_alloc_parms *parms) +{ + struct cfa_tcam_mgr_entry_data entry; + struct cfa_tcam_mgr_table_rows_0 *row; + struct cfa_tcam_mgr_table_data *table_data; + int dir, tbl_type; + int key_slices, rc, sess_idx; + int new_entry_id; + uint32_t session_id; + + CFA_TCAM_MGR_CHECK_PARMS2(context, parms); + + dir = parms->dir; + tbl_type = parms->type; + + if (dir >= TF_DIR_MAX) { + CFA_TCAM_MGR_LOG(ERR, "Invalid direction: %d.\n", dir); + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + } + + if (tbl_type >= CFA_TCAM_MGR_TBL_TYPE_MAX) { + CFA_TCAM_MGR_LOG_DIR(ERR, dir, + "Invalid table type: %d.\n", + tbl_type); + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + } + +#if TF_TCAM_PRIORITY_MAX < UINT16_MAX + if (parms->priority > TF_TCAM_PRIORITY_MAX) { + CFA_TCAM_MGR_LOG_DIR(ERR, dir, + "Priority (%u) out of range (%u -%u).\n", + parms->priority, + TF_TCAM_PRIORITY_MIN, + TF_TCAM_PRIORITY_MAX); + } +#endif + + /* Check for session limits */ + rc = cfa_tcam_mgr_get_session_from_context(context, &session_id); + if (rc < 0) + return rc; + + sess_idx = cfa_tcam_mgr_session_find(session_id); + if (sess_idx < 0) { + CFA_TCAM_MGR_LOG(ERR, "Session 0x%08x not found.\n", + session_id); + return -CFA_TCAM_MGR_ERR_CODE(NODEV); + } + + if (global_data_initialized[sess_idx] == 0) { + CFA_TCAM_MGR_LOG(ERR, "PANIC: No TCAM data created for sess_idx %d\n", + sess_idx); + return -CFA_TCAM_MGR_ERR_CODE(PERM); + } + + table_data = &cfa_tcam_mgr_tables[sess_idx][dir][tbl_type]; + + if (parms->key_size == 0 || + parms->key_size > table_data->row_width) { + CFA_TCAM_MGR_LOG_DIR(ERR, dir, + "Invalid key size:%d (range 1-%d) sess_idx %d.\n", + parms->key_size, + table_data->row_width, + sess_idx); + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + } + + /* Check global limits */ + if (table_data->used_entries >= + table_data->max_entries) { + CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, dir, tbl_type, + "Table full sess_idx %d.\n", + sess_idx); + return -CFA_TCAM_MGR_ERR_CODE(NOSPC); + } + + /* There is room, now increment counts and allocate an entry. */ + new_entry_id = cfa_tcam_mgr_session_entry_alloc(session_id, + parms->dir, + parms->type); + if (new_entry_id < 0) + return new_entry_id; + + memset(&entry, 0, sizeof(entry)); + entry.ref_cnt++; + + key_slices = cfa_tcam_mgr_get_num_slices(parms->key_size, + (table_data->row_width / + table_data->max_slices)); + + row = cfa_tcam_mgr_empty_row_alloc(sess_idx, context, parms, &entry, + new_entry_id, key_slices); + if (row == NULL) { + CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, parms->dir, parms->type, + "Table full (HW) sess_idx %d.\n", + sess_idx); + (void)cfa_tcam_mgr_session_entry_free(session_id, new_entry_id, + parms->dir, parms->type); + return -CFA_TCAM_MGR_ERR_CODE(NOSPC); + } + + memcpy(&entry_data[sess_idx][new_entry_id], + &entry, + sizeof(entry_data[sess_idx][new_entry_id])); + table_data->used_entries += 1; + + cfa_tcam_mgr_entry_insert(sess_idx, new_entry_id, &entry); + + parms->id = new_entry_id; + + return 0; +} + +int +cfa_tcam_mgr_free(struct cfa_tcam_mgr_context *context, + struct cfa_tcam_mgr_free_parms *parms) +{ + struct cfa_tcam_mgr_entry_data *entry; + struct cfa_tcam_mgr_table_rows_0 *row; + struct cfa_tcam_mgr_table_data *table_data; + int row_size, rc, sess_idx, new_row_to_free; + uint32_t session_id; + uint16_t id; + + CFA_TCAM_MGR_CHECK_PARMS2(context, parms); + + rc = cfa_tcam_mgr_get_session_from_context(context, &session_id); + if (rc < 0) + return rc; + + sess_idx = cfa_tcam_mgr_session_find(session_id); + if (sess_idx < 0) { + CFA_TCAM_MGR_LOG(ERR, "Session 0x%08x not found.\n", + session_id); + return sess_idx; + } + + if (global_data_initialized[sess_idx] == 0) { + CFA_TCAM_MGR_LOG(INFO, "PANIC: No TCAM data created for sess_idx %d\n", + sess_idx); + return -CFA_TCAM_MGR_ERR_CODE(PERM); + } + + id = parms->id; + entry = cfa_tcam_mgr_entry_get(sess_idx, id); + if (entry == NULL) { + CFA_TCAM_MGR_LOG(INFO, "Entry %d not found for sess_idx %d.\n", + id, sess_idx); + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + } + + if (entry->ref_cnt == 0) { + CFA_TCAM_MGR_LOG(ERR, "Entry %d not in use for sess_idx %d.\n", + id, sess_idx); + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + } + + /* + * If the TCAM type is CFA_TCAM_MGR_TBL_TYPE_MAX, that implies that the + * caller does not know the table or direction of the entry and TCAM + * Manager must search the tables to find out which table has the entry + * installed. + * + * This would be the case if RM has informed TCAM Mgr that an entry must + * be freed. Clients (sessions, AFM) should always know the type and + * direction of the table where an entry is installed. + */ + if (parms->type == CFA_TCAM_MGR_TBL_TYPE_MAX) { + /* Need to search for the entry in the tables */ + rc = cfa_tcam_mgr_entry_find(sess_idx, id, &parms->dir, &parms->type); + if (rc < 0) { + CFA_TCAM_MGR_LOG(ERR, "Entry %d not in tables for sess_idx %d.\n", + id, sess_idx); + return rc; + } + } + + table_data = &cfa_tcam_mgr_tables[sess_idx][parms->dir][parms->type]; + parms->hcapi_type = table_data->hcapi_type; + + row_size = cfa_tcam_mgr_row_size_get(sess_idx, parms->dir, parms->type); + + row = cfa_tcam_mgr_row_ptr_get(table_data->tcam_rows, entry->row, + row_size); + + entry->ref_cnt--; + + (void)cfa_tcam_mgr_session_entry_free(session_id, id, + parms->dir, parms->type); + + if (entry->ref_cnt == 0) { + cfa_tcam_mgr_entry_free_msg(sess_idx, context, parms, + entry->row, + entry->slice * row->entry_size, + table_data->row_width / + table_data->max_slices * + row->entry_size, + table_data->result_size, + table_data->max_slices); + ROW_ENTRY_CLEAR(row, entry->slice); + + new_row_to_free = entry->row; + cfa_tcam_mgr_rows_combine(sess_idx, context, parms, table_data, + new_row_to_free); + + if (!ROW_INUSE(row)) { + cfa_tcam_mgr_rows_compact(sess_idx, context, + parms, table_data, + &new_row_to_free, + new_row_to_free); + if (new_row_to_free >= 0) + cfa_tcam_mgr_entry_free_msg(sess_idx, context, parms, + new_row_to_free, 0, + table_data->row_width, + table_data->result_size, + table_data->max_slices); + } + + cfa_tcam_mgr_entry_delete(sess_idx, id); + table_data->used_entries -= 1; + } + + return 0; +} + +int +cfa_tcam_mgr_set(struct cfa_tcam_mgr_context *context, + struct cfa_tcam_mgr_set_parms *parms) +{ + struct cfa_tcam_mgr_entry_data *entry; + struct cfa_tcam_mgr_table_rows_0 *row; + struct cfa_tcam_mgr_table_data *table_data; + int rc; + int row_size, sess_idx; + int entry_size_in_bytes; + uint32_t session_id; + + CFA_TCAM_MGR_CHECK_PARMS2(context, parms); + + rc = cfa_tcam_mgr_get_session_from_context(context, &session_id); + if (rc < 0) + return rc; + + sess_idx = cfa_tcam_mgr_session_find(session_id); + if (sess_idx < 0) { + CFA_TCAM_MGR_LOG(ERR, "Session 0x%08x not found.\n", + session_id); + return sess_idx; + } + + if (global_data_initialized[sess_idx] == 0) { + CFA_TCAM_MGR_LOG(ERR, "PANIC: No TCAM data created for sess_idx %d\n", + sess_idx); + return -CFA_TCAM_MGR_ERR_CODE(PERM); + } + + entry = cfa_tcam_mgr_entry_get(sess_idx, parms->id); + if (entry == NULL) { + CFA_TCAM_MGR_LOG(ERR, "Entry %d not found for sess_idx %d.\n", + parms->id, sess_idx); + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + } + + table_data = &cfa_tcam_mgr_tables[sess_idx][parms->dir][parms->type]; + parms->hcapi_type = table_data->hcapi_type; + + row_size = cfa_tcam_mgr_row_size_get(sess_idx, parms->dir, parms->type); + row = cfa_tcam_mgr_row_ptr_get(table_data->tcam_rows, entry->row, + row_size); + + entry_size_in_bytes = table_data->row_width / + table_data->max_slices * + row->entry_size; + if (parms->key_size != entry_size_in_bytes) { + CFA_TCAM_MGR_LOG(ERR, + "Key size(%d) is different from entry " + "size(%d).\n", + parms->key_size, + entry_size_in_bytes); + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + } + + rc = cfa_tcam_mgr_entry_set_msg(sess_idx, context, parms, + entry->row, + entry->slice * row->entry_size, + table_data->max_slices); + if (rc < 0) { + CFA_TCAM_MGR_LOG_0(ERR, "Failed to set TCAM data.\n"); + return rc; + } + + return 0; +} + +int +cfa_tcam_mgr_get(struct cfa_tcam_mgr_context *context __rte_unused, + struct cfa_tcam_mgr_get_parms *parms) +{ + struct cfa_tcam_mgr_entry_data *entry; + struct cfa_tcam_mgr_table_rows_0 *row; + struct cfa_tcam_mgr_table_data *table_data; + int rc; + int row_size, sess_idx; + uint32_t session_id; + + CFA_TCAM_MGR_CHECK_PARMS2(context, parms); + + rc = cfa_tcam_mgr_get_session_from_context(context, &session_id); + if (rc < 0) + return rc; + + sess_idx = cfa_tcam_mgr_session_find(session_id); + if (sess_idx < 0) { + CFA_TCAM_MGR_LOG(ERR, "Session 0x%08x not found.\n", + session_id); + return sess_idx; + } + + if (global_data_initialized[sess_idx] == 0) { + CFA_TCAM_MGR_LOG(ERR, "PANIC: No TCAM data created for sess_idx %d\n", + sess_idx); + return -CFA_TCAM_MGR_ERR_CODE(PERM); + } + + entry = cfa_tcam_mgr_entry_get(sess_idx, parms->id); + if (entry == NULL) { + CFA_TCAM_MGR_LOG(ERR, "Entry %d not found.\n", parms->id); + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + } + + table_data = &cfa_tcam_mgr_tables[sess_idx][parms->dir][parms->type]; + parms->hcapi_type = table_data->hcapi_type; + + row_size = cfa_tcam_mgr_row_size_get(sess_idx, parms->dir, parms->type); + row = cfa_tcam_mgr_row_ptr_get(table_data->tcam_rows, entry->row, + row_size); + + rc = cfa_tcam_mgr_entry_get_msg(sess_idx, context, parms, + entry->row, + entry->slice * row->entry_size, + table_data->max_slices); + if (rc < 0) { + CFA_TCAM_MGR_LOG_0(ERR, "Failed to read from TCAM.\n"); + return rc; + } + + return 0; +} + +int cfa_tcam_mgr_shared_clear(struct cfa_tcam_mgr_context *context, + struct cfa_tcam_mgr_shared_clear_parms *parms) +{ + int rc; + uint16_t row, slice = 0; + int sess_idx; + uint32_t session_id; + struct cfa_tcam_mgr_free_parms fparms; + struct cfa_tcam_mgr_table_data *table_data; + uint16_t start_row, end_row, max_entries, max_slices; + + CFA_TCAM_MGR_CHECK_PARMS2(context, parms); + + rc = cfa_tcam_mgr_get_session_from_context(context, &session_id); + if (rc < 0) + return rc; + + sess_idx = cfa_tcam_mgr_session_find(session_id); + if (sess_idx < 0) { + CFA_TCAM_MGR_LOG(ERR, "Session 0x%08x not found.\n", + session_id); + return sess_idx; + } + + if (global_data_initialized[sess_idx] == 0) { + CFA_TCAM_MGR_LOG(ERR, "PANIC: No TCAM data created for sess_idx %d\n", + sess_idx); + return -CFA_TCAM_MGR_ERR_CODE(PERM); + } + + table_data = &cfa_tcam_mgr_tables[sess_idx][parms->dir][parms->type]; + fparms.dir = parms->dir; + fparms.type = parms->type; + fparms.hcapi_type = table_data->hcapi_type; + fparms.id = 0; + + rc = cfa_tcam_mgr_tables_get(sess_idx, parms->dir, parms->type, + &start_row, &end_row, &max_entries, &max_slices); + if (rc) + return rc; + + for (row = start_row; row <= end_row; row++) { + cfa_tcam_mgr_entry_free_msg(sess_idx, context, &fparms, + row, + slice, + table_data->row_width, + table_data->result_size, + table_data->max_slices); + } + return rc; +} + +static void +cfa_tcam_mgr_mv_used_entries_cnt(int sess_idx, enum tf_dir dir, + struct cfa_tcam_mgr_table_data *dst_table_data, + struct cfa_tcam_mgr_table_data *src_table_data) +{ + dst_table_data->used_entries++; + src_table_data->used_entries--; + + cfa_tcam_mgr_mv_session_used_entries_cnt(sess_idx, dir, + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS, + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS); +} + +/* + * Move HI WC TCAM entries to LOW TCAM region for HA + * This happens when secondary is becoming primary + */ +static int +cfa_tcam_mgr_shared_entry_move(int sess_idx, struct cfa_tcam_mgr_context *context, + enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type, + int entry_id, + struct cfa_tcam_mgr_table_data *dst_table_data, + struct cfa_tcam_mgr_table_data *table_data, + int dst_row_index, int dst_row_slice, + struct cfa_tcam_mgr_table_rows_0 *dst_row, + int src_row_index, + struct cfa_tcam_mgr_table_rows_0 *src_row) +{ + struct cfa_tcam_mgr_get_parms gparms = { 0 }; + struct cfa_tcam_mgr_set_parms sparms = { 0 }; + struct cfa_tcam_mgr_free_parms fparms = { 0 }; + struct cfa_tcam_mgr_entry_data *entry; + uint8_t key[CFA_TCAM_MGR_MAX_KEY_SIZE]; + uint8_t mask[CFA_TCAM_MGR_MAX_KEY_SIZE]; + uint8_t result[CFA_TCAM_MGR_MAX_KEY_SIZE]; + + int rc; + + entry = cfa_tcam_mgr_entry_get(sess_idx, entry_id); + if (entry == NULL) + return -1; + + gparms.dir = dir; + gparms.type = type; + gparms.hcapi_type = table_data->hcapi_type; + gparms.key = key; + gparms.mask = mask; + gparms.result = result; + gparms.id = src_row->entries[entry->slice]; + gparms.key_size = sizeof(key); + gparms.result_size = sizeof(result); + + rc = cfa_tcam_mgr_entry_get_msg(sess_idx, context, &gparms, + src_row_index, + entry->slice * src_row->entry_size, + table_data->max_slices); + if (rc != 0) + return rc; + + sparms.dir = dir; + sparms.type = CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS; + sparms.hcapi_type = table_data->hcapi_type; + sparms.key = key; + sparms.mask = mask; + sparms.result = result; + sparms.id = gparms.id; + sparms.key_size = gparms.key_size; + sparms.result_size = gparms.result_size; + + rc = cfa_tcam_mgr_entry_set_msg(sess_idx, context, &sparms, + dst_row_index, + dst_row_slice * dst_row->entry_size, + table_data->max_slices); + if (rc != 0) + return rc; + + fparms.dir = dir; + fparms.type = type; + fparms.hcapi_type = table_data->hcapi_type; + rc = cfa_tcam_mgr_entry_free_msg(sess_idx, context, &fparms, + src_row_index, + entry->slice * + dst_row->entry_size, + table_data->row_width / + table_data->max_slices * + src_row->entry_size, + table_data->result_size, + table_data->max_slices); + if (rc != 0) { + CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, + dir, type, + "Failed to free entry ID %d at" + " row %d, slice %d for sess_idx %d. rc: %d.\n", + gparms.id, + src_row_index, + entry->slice, + sess_idx, + -rc); + } + +#ifdef CFA_TCAM_MGR_TRACING + CFA_TCAM_MGR_TRACE(INFO, "Moved entry %d from row %d, slice %d to " + "row %d, slice %d.\n", + entry_id, src_row_index, entry->slice, + dst_row_index, dst_row_slice); +#endif + + ROW_ENTRY_SET(dst_row, dst_row_slice); + dst_row->entries[dst_row_slice] = entry_id; + dst_row->entry_size = src_row->entry_size; + dst_row->priority = src_row->priority; + ROW_ENTRY_CLEAR(src_row, entry->slice); + entry->row = dst_row_index; + entry->slice = dst_row_slice; + + cfa_tcam_mgr_mv_used_entries_cnt(sess_idx, dir, dst_table_data, table_data); + +#ifdef CFA_TCAM_MGR_TRACING + cfa_tcam_mgr_rows_dump(sess_idx, dir, type); + cfa_tcam_mgr_rows_dump(sess_idx, dir, CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS); +#endif + + return 0; +} + +int cfa_tcam_mgr_shared_move(struct cfa_tcam_mgr_context *context, + struct cfa_tcam_mgr_shared_move_parms *parms) +{ + int rc; + int sess_idx; + uint32_t session_id; + uint16_t src_row, dst_row, row_size, slice; + struct cfa_tcam_mgr_table_rows_0 *src_table_row; + struct cfa_tcam_mgr_table_rows_0 *dst_table_row; + struct cfa_tcam_mgr_table_data *src_table_data; + struct cfa_tcam_mgr_table_data *dst_table_data; + + CFA_TCAM_MGR_CHECK_PARMS2(context, parms); + + rc = cfa_tcam_mgr_get_session_from_context(context, &session_id); + if (rc < 0) + return rc; + + sess_idx = cfa_tcam_mgr_session_find(session_id); + if (sess_idx < 0) { + CFA_TCAM_MGR_LOG(ERR, "Session 0x%08x not found.\n", + session_id); + return sess_idx; + } + + if (global_data_initialized[sess_idx] == 0) { + CFA_TCAM_MGR_LOG(ERR, "PANIC: No TCAM data created for sess_idx %d\n", + sess_idx); + return -CFA_TCAM_MGR_ERR_CODE(PERM); + } + + src_table_data = + &cfa_tcam_mgr_tables[sess_idx][parms->dir][CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS]; + dst_table_data = + &cfa_tcam_mgr_tables[sess_idx][parms->dir][CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS]; + + row_size = + cfa_tcam_mgr_row_size_get(sess_idx, + parms->dir, + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS); + + for (src_row = src_table_data->start_row, + dst_row = dst_table_data->start_row; + src_row <= src_table_data->end_row; + src_row++, dst_row++) { + src_table_row = cfa_tcam_mgr_row_ptr_get(src_table_data->tcam_rows, + src_row, row_size); + dst_table_row = cfa_tcam_mgr_row_ptr_get(dst_table_data->tcam_rows, + dst_row, row_size); + if (ROW_INUSE(src_table_row)) { + for (slice = 0; + slice < src_table_data->max_slices / src_table_row->entry_size; + slice++) { + if (ROW_ENTRY_INUSE(src_table_row, slice)) { +#ifdef CFA_TCAM_MGR_TRACING + CFA_TCAM_MGR_TRACE(INFO, "Move entry id %d " + "from src_row %d, slice %d " + "to dst_row %d, slice %d.\n", + src_table_row->entries[slice], + src_row, slice, + dst_row, slice); +#endif + rc = cfa_tcam_mgr_shared_entry_move(sess_idx, + context, + parms->dir, + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS, + src_table_row->entries[slice], + dst_table_data, + src_table_data, + dst_row, slice, + dst_table_row, + src_row, + src_table_row); + } + } + } + } + + return rc; +} + +static void +cfa_tcam_mgr_tbl_get(int sess_idx, enum tf_dir dir, + enum cfa_tcam_mgr_tbl_type type, + uint16_t *start_row, + uint16_t *end_row, + uint16_t *max_entries, + uint16_t *slices) +{ + struct cfa_tcam_mgr_table_data *table_data = + &cfa_tcam_mgr_tables[sess_idx][dir][type]; + + /* Get start, end and max for tcam type*/ + *start_row = table_data->start_row; + *end_row = table_data->end_row; + *max_entries = table_data->max_entries; + *slices = table_data->max_slices; +} + +int +cfa_tcam_mgr_tables_get(int sess_idx, enum tf_dir dir, + enum cfa_tcam_mgr_tbl_type type, + uint16_t *start_row, + uint16_t *end_row, + uint16_t *max_entries, + uint16_t *slices) +{ + CFA_TCAM_MGR_CHECK_PARMS3(start_row, end_row, max_entries); + + if (global_data_initialized[sess_idx] == 0) { + CFA_TCAM_MGR_LOG(ERR, "PANIC: TCAM not initialized for sess_idx %d.\n", + sess_idx); + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + } + + if (dir >= TF_DIR_MAX) { + CFA_TCAM_MGR_LOG(ERR, "Must specify valid dir (0-%d) forsess_idx %d.\n", + TF_DIR_MAX - 1, sess_idx); + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + } + + if (type >= CFA_TCAM_MGR_TBL_TYPE_MAX) { + CFA_TCAM_MGR_LOG(ERR, "Must specify valid tbl type (0-%d) forsess_idx %d.\n", + CFA_TCAM_MGR_TBL_TYPE_MAX - 1, sess_idx); + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + } + + cfa_tcam_mgr_tbl_get(sess_idx, dir, + type, + start_row, + end_row, + max_entries, + slices); + return 0; +} + +static void +cfa_tcam_mgr_tbl_set(int sess_idx, enum tf_dir dir, + enum cfa_tcam_mgr_tbl_type type, + uint16_t start_row, + uint16_t end_row, + uint16_t max_entries) +{ + struct cfa_tcam_mgr_table_data *table_data = + &cfa_tcam_mgr_tables[sess_idx][dir][type]; + + /* Update start, end and max for tcam type*/ + table_data->start_row = start_row; + table_data->end_row = end_row; + table_data->max_entries = max_entries; +} + +int +cfa_tcam_mgr_tables_set(int sess_idx, enum tf_dir dir, + enum cfa_tcam_mgr_tbl_type type, + uint16_t start_row, + uint16_t end_row, + uint16_t max_entries) +{ + if (global_data_initialized[sess_idx] == 0) { + CFA_TCAM_MGR_LOG(ERR, "PANIC: TCAM not initialized for sess_idx %d.\n", + sess_idx); + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + } + + if (dir >= TF_DIR_MAX) { + CFA_TCAM_MGR_LOG(ERR, "Must specify valid dir (0-%d) forsess_idx %d.\n", + TF_DIR_MAX - 1, sess_idx); + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + } + + if (type >= CFA_TCAM_MGR_TBL_TYPE_MAX) { + CFA_TCAM_MGR_LOG(ERR, "Must specify valid tbl type (0-%d) forsess_idx %d.\n", + CFA_TCAM_MGR_TBL_TYPE_MAX - 1, sess_idx); + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + } + + cfa_tcam_mgr_tbl_set(sess_idx, dir, + type, + start_row, + end_row, + max_entries); + return 0; +} + +void +cfa_tcam_mgr_rows_dump(int sess_idx, enum tf_dir dir, + enum cfa_tcam_mgr_tbl_type type) +{ + struct cfa_tcam_mgr_table_data *table_data; + struct cfa_tcam_mgr_table_rows_0 *table_row; + int i, row, row_size; + bool row_found = false; + bool empty_row = false; + + if (global_data_initialized[sess_idx] == 0) { + printf("PANIC: TCAM not initialized for sess_idx %d.\n", sess_idx); + return; + } + + if (dir >= TF_DIR_MAX) { + printf("Must specify a valid direction (0-%d).\n", + TF_DIR_MAX - 1); + return; + } + if (type >= CFA_TCAM_MGR_TBL_TYPE_MAX) { + printf("Must specify a valid type (0-%d).\n", + CFA_TCAM_MGR_TBL_TYPE_MAX - 1); + return; + } + + table_data = &cfa_tcam_mgr_tables[sess_idx][dir][type]; + row_size = cfa_tcam_mgr_row_size_get(sess_idx, dir, type); + + printf("\nTCAM Rows:\n"); + printf("Rows for direction %s, Logical table type %s\n", + tf_dir_2_str(dir), cfa_tcam_mgr_tbl_2_str(type)); + printf("Managed rows %d-%d for sess_idx %d:\n", + table_data->start_row, table_data->end_row, sess_idx); + + printf("Index Pri Size Entry IDs\n"); + printf(" Sl 0"); + for (i = 1; i < table_data->max_slices; i++) + printf(" Sl %d", i); + printf("\n"); + for (row = table_data->start_row; row <= table_data->end_row; row++) { + table_row = cfa_tcam_mgr_row_ptr_get(table_data->tcam_rows, row, + row_size); + if (ROW_INUSE(table_row)) { + empty_row = false; + printf("%5u %5u %4u", + row, + TF_TCAM_PRIORITY_MAX - table_row->priority - 1, + table_row->entry_size); + for (i = 0; + i < table_data->max_slices / table_row->entry_size; + i++) { + if (ROW_ENTRY_INUSE(table_row, i)) + printf(" %5u", table_row->entries[i]); + else + printf(" x"); + } + printf("\n"); + row_found = true; + } else if (!empty_row) { + empty_row = true; + printf("\n"); + } + } + + if (!row_found) + printf("No rows in use.\n"); +} + +static void +cfa_tcam_mgr_table_dump(int sess_idx, enum tf_dir dir, + enum cfa_tcam_mgr_tbl_type type) +{ + struct cfa_tcam_mgr_table_data *table_data = + &cfa_tcam_mgr_tables[sess_idx][dir][type]; + + printf("%3s %-22s %5u %5u %5u %5u %6u %7u %2u\n", + tf_dir_2_str(dir), + cfa_tcam_mgr_tbl_2_str(type), + table_data->row_width, + table_data->num_rows, + table_data->start_row, + table_data->end_row, + table_data->max_entries, + table_data->used_entries, + table_data->max_slices); +} + +#define TABLE_DUMP_HEADER \ + "Dir Table Width Rows Start End " \ + "MaxEnt UsedEnt Slices\n" + +void +cfa_tcam_mgr_tables_dump(int sess_idx, enum tf_dir dir, + enum cfa_tcam_mgr_tbl_type type) +{ + if (global_data_initialized[sess_idx] == 0) { + printf("PANIC: TCAM not initialized for sess_idx %d.\n", sess_idx); + return; + } + + printf("\nTCAM Table(s) for sess_idx %d:\n", sess_idx); + printf(TABLE_DUMP_HEADER); + if (dir >= TF_DIR_MAX) { + /* Iterate over all directions */ + for (dir = 0; dir < TF_DIR_MAX; dir++) { + if (type >= CFA_TCAM_MGR_TBL_TYPE_MAX) { + /* Iterate over all types */ + for (type = 0; + type < CFA_TCAM_MGR_TBL_TYPE_MAX; + type++) { + cfa_tcam_mgr_table_dump(sess_idx, dir, type); + } + } else { + /* Display a specific type */ + cfa_tcam_mgr_table_dump(sess_idx, dir, type); + } + } + } else if (type >= CFA_TCAM_MGR_TBL_TYPE_MAX) { + /* Iterate over all types for a direction */ + for (type = 0; type < CFA_TCAM_MGR_TBL_TYPE_MAX; type++) + cfa_tcam_mgr_table_dump(sess_idx, dir, type); + } else { + /* Display a specific direction and type */ + cfa_tcam_mgr_table_dump(sess_idx, dir, type); + } +} + +#define ENTRY_DUMP_HEADER "Entry RefCnt Row Slice\n" + +void +cfa_tcam_mgr_entries_dump(int sess_idx) +{ + struct cfa_tcam_mgr_entry_data *entry; + bool entry_found = false; + uint16_t id; + + if (global_data_initialized[sess_idx] == 0) { + CFA_TCAM_MGR_LOG(INFO, "PANIC: No TCAM data created for sess_idx %d\n", + sess_idx); + return; + } + + printf("\nGlobal Maximum Entries: %d\n\n", + cfa_tcam_mgr_max_entries[sess_idx]); + printf("TCAM Entry Table:\n"); + for (id = 0; id < cfa_tcam_mgr_max_entries[sess_idx]; id++) { + if (entry_data[sess_idx][id].ref_cnt > 0) { + entry = &entry_data[sess_idx][id]; + if (!entry_found) + printf(ENTRY_DUMP_HEADER); + printf("%5u %5u %5u %5u", + id, entry->ref_cnt, + entry->row, entry->slice); + printf("\n"); + entry_found = true; + } + } + + if (!entry_found) + printf("No entries found.\n"); +} diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.h new file mode 100644 index 0000000000..40bfe8e225 --- /dev/null +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.h @@ -0,0 +1,523 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2021-2023 Broadcom + * All rights reserved. + */ + +#ifndef _CFA_TCAM_MGR_H_ +#define _CFA_TCAM_MGR_H_ + +#include +#include "rte_common.h" +#include "hsi_struct_def_dpdk.h" +#include "tf_core.h" + +#ifndef __rte_unused +#define __rte_unused __attribute__((unused)) +#endif + +/** + * The TCAM module provides processing of Internal TCAM types. + */ + +#ifndef TF_TCAM_MAX_SESSIONS +#define TF_TCAM_MAX_SESSIONS 16 +#endif + +#define ENTRY_ID_INVALID UINT16_MAX + +#define TF_TCAM_PRIORITY_MIN 0 +#define TF_TCAM_PRIORITY_MAX UINT16_MAX + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(_array) (sizeof(_array) / sizeof(_array[0])) +#endif + +/* Use TFP_DRV_LOG definition in tfp.h */ +#define CFA_TCAM_MGR_LOG(level, fmt, args...) \ + TFP_DRV_LOG(level, fmt, ## args) +#define CFA_TCAM_MGR_LOG_DIR(level, dir, fmt, args...) \ + TFP_DRV_LOG(level, "%s: " fmt, tf_dir_2_str(dir), ## args) +#define CFA_TCAM_MGR_LOG_DIR_TYPE(level, dir, type, fmt, args...) \ + TFP_DRV_LOG(level, "%s: %s " fmt, tf_dir_2_str(dir), \ + cfa_tcam_mgr_tbl_2_str(type), ## args) + +#define CFA_TCAM_MGR_LOG_0(level, fmt) \ + TFP_DRV_LOG(level, fmt) +#define CFA_TCAM_MGR_LOG_DIR_0(level, dir, fmt) \ + TFP_DRV_LOG(level, "%s: " fmt, tf_dir_2_str(dir)) +#define CFA_TCAM_MGR_LOG_DIR_TYPE_0(level, dir, type, fmt) \ + TFP_DRV_LOG(level, "%s: %s " fmt, tf_dir_2_str(dir), \ + cfa_tcam_mgr_tbl_2_str(type)) + +#define CFA_TCAM_MGR_ERR_CODE(type) E ## type + +/** + * Checks 1 parameter against NULL. + */ +#define CFA_TCAM_MGR_CHECK_PARMS1(parms) do { \ + if ((parms) == NULL) { \ + CFA_TCAM_MGR_LOG_0(ERR, "Invalid Argument(s)\n"); \ + return -CFA_TCAM_MGR_ERR_CODE(INVAL); \ + } \ + } while (0) + +/** + * Checks 2 parameters against NULL. + */ +#define CFA_TCAM_MGR_CHECK_PARMS2(parms1, parms2) do { \ + if ((parms1) == NULL || (parms2) == NULL) { \ + CFA_TCAM_MGR_LOG_0(ERR, "Invalid Argument(s)\n"); \ + return -CFA_TCAM_MGR_ERR_CODE(INVAL); \ + } \ + } while (0) + +/** + * Checks 3 parameters against NULL. + */ +#define CFA_TCAM_MGR_CHECK_PARMS3(parms1, parms2, parms3) do { \ + if ((parms1) == NULL || \ + (parms2) == NULL || \ + (parms3) == NULL) { \ + CFA_TCAM_MGR_LOG_0(ERR, "Invalid Argument(s)\n"); \ + return -CFA_TCAM_MGR_ERR_CODE(INVAL); \ + } \ + } while (0) + +enum cfa_tcam_mgr_tbl_type { + /* Logical TCAM tables */ + CFA_TCAM_MGR_TBL_TYPE_START, + CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM = + CFA_TCAM_MGR_TBL_TYPE_START, + CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS, + CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_AFM, + CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS, + CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_AFM, + CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS, + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_AFM, + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS, + CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_AFM, + CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS, + CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_AFM, + CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS, + CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_AFM, + CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS, + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_AFM, + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS, + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_AFM, + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS, + CFA_TCAM_MGR_TBL_TYPE_MAX +}; + +enum cfa_tcam_mgr_device_type { + CFA_TCAM_MGR_DEVICE_TYPE_P4 = 0, + CFA_TCAM_MGR_DEVICE_TYPE_SR, + CFA_TCAM_MGR_DEVICE_TYPE_P5, + CFA_TCAM_MGR_DEVICE_TYPE_MAX +}; + +struct cfa_tcam_mgr_context { + struct tf *tfp; +}; + +/** + * TCAM Manager initialization parameters + */ +struct cfa_tcam_mgr_init_parms { + /** + * [in] TCAM resources reserved + * type element is not used. + */ + struct tf_rm_resc_entry resc[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX]; + /** + * [out] maximum number of entries available. + */ + uint32_t max_entries; +}; + +/** + * TCAM Manager initialization parameters + */ +struct cfa_tcam_mgr_qcaps_parms { + /** + * [out] Bitmasks. Set if TCAM Manager is managing a logical TCAM. + * Each bitmask is indexed by logical TCAM table ID. + */ + uint32_t rx_tcam_supported; + uint32_t tx_tcam_supported; +}; + +/** + * TCAM Manager configuration parameters + */ +struct cfa_tcam_mgr_cfg_parms { + /** + * [in] Number of tcam types in each of the configuration arrays + */ + uint16_t num_elements; + /** + * [in] Session resource allocations + */ + uint16_t tcam_cnt[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX]; + + /** + * [in] TCAM Locations reserved + */ + struct tf_rm_resc_entry (*resv_res)[CFA_TCAM_MGR_TBL_TYPE_MAX]; +}; + +/** + * TCAM Manager allocation parameters + */ +struct cfa_tcam_mgr_alloc_parms { + /** + * [in] Receive or transmit direction + */ + enum tf_dir dir; + /** + * [in] Type of the allocation + */ + enum cfa_tcam_mgr_tbl_type type; + /** + * [in] Type of HCAPI + */ + uint16_t hcapi_type; + /** + * [in] key size (bytes) + */ + uint16_t key_size; + /** + * [in] Priority of entry requested (definition TBD) + */ + uint16_t priority; + /** + * [out] Id of allocated entry or found entry (if search_enable) + */ + uint16_t id; +}; + +/** + * TCAM Manager free parameters + */ +struct cfa_tcam_mgr_free_parms { + /** + * [in] Receive or transmit direction + */ + enum tf_dir dir; + /** + * [in] Type of the allocation + * If the type is not known, set the type to CFA_TCAM_MGR_TBL_TYPE_MAX. + */ + enum cfa_tcam_mgr_tbl_type type; + /** + * [in] Type of HCAPI + */ + uint16_t hcapi_type; + /** + * [in] Entry ID to free + */ + uint16_t id; +}; + +/** + * TCAM Manager set parameters + */ +struct cfa_tcam_mgr_set_parms { + /** + * [in] Receive or transmit direction + */ + enum tf_dir dir; + /** + * [in] Type of object to set + */ + enum cfa_tcam_mgr_tbl_type type; + /** + * [in] Type of HCAPI + */ + uint16_t hcapi_type; + /** + * [in] Entry ID to write to + */ + uint16_t id; + /** + * [in] array containing key + */ + uint8_t *key; + /** + * [in] array containing mask fields + */ + uint8_t *mask; + /** + * [in] key size (bytes) + */ + uint16_t key_size; + /** + * [in] array containing result + */ + uint8_t *result; + /** + * [in] result size (bytes) + */ + uint16_t result_size; +}; + +/** + * TCAM Manager get parameters + */ +struct cfa_tcam_mgr_get_parms { + /** + * [in] Receive or transmit direction + */ + enum tf_dir dir; + /** + * [in] Type of object to get + */ + enum cfa_tcam_mgr_tbl_type type; + /** + * [in] Type of HCAPI + */ + uint16_t hcapi_type; + /** + * [in] Entry ID to read + */ + uint16_t id; + /** + * [out] array containing key + */ + uint8_t *key; + /** + * [out] array containing mask fields + */ + uint8_t *mask; + /** + * [out] key size (bytes) + */ + uint16_t key_size; + /** + * [out] array containing result + */ + uint8_t *result; + /** + * [out] result size (bytes) + */ + uint16_t result_size; +}; + +/** + * cfa_tcam_mgr_shared_clear_parms parameter definition + */ +struct cfa_tcam_mgr_shared_clear_parms { + /** + * [in] receive or transmit direction + */ + enum tf_dir dir; + /** + * [in] TCAM table type + */ + enum cfa_tcam_mgr_tbl_type type; +}; + +/** + * cfa_tcam_mgr_shared_move_parms parameter definition + */ +struct cfa_tcam_mgr_shared_move_parms { + /** + * [in] receive or transmit direction + */ + enum tf_dir dir; + /** + * [in] TCAM table type + */ + enum cfa_tcam_mgr_tbl_type type; +}; + +/** + * @page tcam TCAM Manager + * + * @ref cfa_tcam_mgr_init + * + * @ref cfa_tcam_mgr_get_phys_table_type + * + * @ref cfa_tcam_mgr_bind + * + * @ref cfa_tcam_mgr_unbind + * + * @ref cfa_tcam_mgr_alloc + * + * @ref cfa_tcam_mgr_free + * + * @ref cfa_tcam_mgr_set + * + * @ref cfa_tcam_mgr_get + * + */ + +const char * +cfa_tcam_mgr_tbl_2_str(enum cfa_tcam_mgr_tbl_type tcam_type); + +/** + * Initializes the TCAM Manager + * + * [in] type + * Device type + * + * Returns + * - (0) if successful. + * - (<0) on failure. + */ +int +cfa_tcam_mgr_init(int sess_idx, enum cfa_tcam_mgr_device_type type, + struct cfa_tcam_mgr_init_parms *parms); + +/** + * Returns the physical TCAM table that a logical TCAM table uses. + * + * [in] type + * Logical table type + * + * Returns + * - (tf_tcam_tbl_type) if successful. + * - (<0) on failure. + */ +int +cfa_tcam_mgr_get_phys_table_type(enum cfa_tcam_mgr_tbl_type type); + +/** + * Queries the capabilities of TCAM Manager. + * + * [in] context + * Pointer to context information + * + * [out] parms + * Pointer to parameters to be returned + * + * Returns + * - (0) if successful. + * - (<0) on failure. + */ +int +cfa_tcam_mgr_qcaps(struct cfa_tcam_mgr_context *context __rte_unused, + struct cfa_tcam_mgr_qcaps_parms *parms); + +/** + * Initializes the TCAM module with the requested DBs. Must be + * invoked as the first thing before any of the access functions. + * + * [in] context + * Pointer to context information + * + * [in] parms + * Pointer to parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int cfa_tcam_mgr_bind(struct cfa_tcam_mgr_context *context, + struct cfa_tcam_mgr_cfg_parms *parms); + +/** + * Cleans up the private DBs and releases all the data. + * + * [in] context + * Pointer to context information + * + * [in] parms + * Pointer to parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int cfa_tcam_mgr_unbind(struct cfa_tcam_mgr_context *context); + +/** + * Allocates the requested tcam type from the internal RM DB. + * + * [in] context + * Pointer to context information + * + * [in] parms + * Pointer to parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int cfa_tcam_mgr_alloc(struct cfa_tcam_mgr_context *context, + struct cfa_tcam_mgr_alloc_parms *parms); + +/** + * Free's the requested table type and returns it to the DB. + * If refcount goes to 0 then it is returned to the table type DB. + * + * [in] context + * Pointer to context information + * + * [in] parms + * Pointer to parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int cfa_tcam_mgr_free(struct cfa_tcam_mgr_context *context, + struct cfa_tcam_mgr_free_parms *parms); + +/** + * Configures the requested element by sending a firmware request which + * then installs it into the device internal structures. + * + * [in] context + * Pointer to context information + * + * [in] parms + * Pointer to parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int cfa_tcam_mgr_set(struct cfa_tcam_mgr_context *context, + struct cfa_tcam_mgr_set_parms *parms); + +/** + * Retrieves the requested element by sending a firmware request to get + * the element. + * + * [in] context + * Pointer to context information + * + * [in] parms + * Pointer to parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int cfa_tcam_mgr_get(struct cfa_tcam_mgr_context *context, + struct cfa_tcam_mgr_get_parms *parms); + +int +cfa_tcam_mgr_tables_get(int sess_idx, enum tf_dir dir, + enum cfa_tcam_mgr_tbl_type type, + uint16_t *start_row, + uint16_t *end_row, + uint16_t *max_entries, + uint16_t *slices); +int +cfa_tcam_mgr_tables_set(int sess_idx, enum tf_dir dir, + enum cfa_tcam_mgr_tbl_type type, + uint16_t start_row, + uint16_t end_row, + uint16_t max_entries); + +int cfa_tcam_mgr_shared_clear(struct cfa_tcam_mgr_context *context, + struct cfa_tcam_mgr_shared_clear_parms *parms); + +int cfa_tcam_mgr_shared_move(struct cfa_tcam_mgr_context *context, + struct cfa_tcam_mgr_shared_move_parms *parms); + +void cfa_tcam_mgr_rows_dump(int sess_idx, enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type); +void cfa_tcam_mgr_tables_dump(int sess_idx, enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type); +void cfa_tcam_mgr_entries_dump(int sess_idx); +#endif /* _CFA_TCAM_MGR_H */ diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_device.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_device.h new file mode 100644 index 0000000000..6ab9b5e118 --- /dev/null +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_device.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2021-2023 Broadcom + * All rights reserved. + */ + +#ifndef CFA_TCAM_MGR_DEVICE_H +#define CFA_TCAM_MGR_DEVICE_H + +#include +#include "cfa_tcam_mgr.h" + +/* + * This identifier is to be used for one-off variable sizes. Do not use it for + * sizing keys in an array. + */ +#define CFA_TCAM_MGR_MAX_KEY_SIZE 96 + +/* Note that this macro's arguments are not macro expanded due to + * concatenation. + */ +#define TF_TCAM_TABLE_ROWS_DEF(_slices) \ + struct cfa_tcam_mgr_table_rows_ ## _slices { \ + uint16_t priority; \ + uint8_t entry_size; /* Slices per entry */ \ + uint8_t entry_inuse; /* bit[entry] set if in use */ \ + uint16_t entries[_slices]; \ + } + +/* + * Have to explicitly declare this struct since some compilers don't accept the + * GNU C extension of zero length arrays. + */ +struct cfa_tcam_mgr_table_rows_0 { + uint16_t priority; + uint8_t entry_size; /* Slices per entry */ + uint8_t entry_inuse; /* bit[entry] set if in use */ + uint16_t entries[]; +}; + +TF_TCAM_TABLE_ROWS_DEF(1); +TF_TCAM_TABLE_ROWS_DEF(2); +TF_TCAM_TABLE_ROWS_DEF(4); +TF_TCAM_TABLE_ROWS_DEF(8); + +#define TF_TCAM_MAX_ENTRIES (L2_CTXT_TCAM_RX_MAX_ENTRIES + \ + L2_CTXT_TCAM_TX_MAX_ENTRIES + \ + PROF_TCAM_RX_MAX_ENTRIES + \ + PROF_TCAM_TX_MAX_ENTRIES + \ + WC_TCAM_RX_MAX_ENTRIES + \ + WC_TCAM_TX_MAX_ENTRIES + \ + SP_TCAM_RX_MAX_ENTRIES + \ + SP_TCAM_TX_MAX_ENTRIES + \ + CT_RULE_TCAM_RX_MAX_ENTRIES + \ + CT_RULE_TCAM_TX_MAX_ENTRIES + \ + VEB_TCAM_RX_MAX_ENTRIES + \ + VEB_TCAM_TX_MAX_ENTRIES) + +struct cfa_tcam_mgr_entry_data { + uint16_t row; + uint8_t slice; + uint8_t ref_cnt; +}; + +struct cfa_tcam_mgr_table_data { + struct cfa_tcam_mgr_table_rows_0 *tcam_rows; + uint16_t hcapi_type; + uint16_t num_rows; /* Rows in physical TCAM */ + uint16_t start_row; /* Where the logical TCAM starts */ + uint16_t end_row; /* Where the logical TCAM ends */ + uint16_t max_entries; + uint16_t used_entries; + uint8_t row_width; /* bytes */ + uint8_t result_size; /* bytes */ + uint8_t max_slices; +}; + +extern int cfa_tcam_mgr_max_entries[TF_TCAM_MAX_SESSIONS]; + +extern struct cfa_tcam_mgr_table_data +cfa_tcam_mgr_tables[TF_TCAM_MAX_SESSIONS][TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX]; + +/* HW OP definitions begin here */ +typedef int (*cfa_tcam_mgr_hwop_set_func_t)(int sess_idx, + struct cfa_tcam_mgr_set_parms + *parms, int row, int slice, + int max_slices); +typedef int (*cfa_tcam_mgr_hwop_get_func_t)(int sess_idx, + struct cfa_tcam_mgr_get_parms + *parms, int row, int slice, + int max_slices); +typedef int (*cfa_tcam_mgr_hwop_free_func_t)(int sess_idx, + struct cfa_tcam_mgr_free_parms + *parms, int row, int slice, + int max_slices); + +struct cfa_tcam_mgr_hwops_funcs { + cfa_tcam_mgr_hwop_set_func_t set; + cfa_tcam_mgr_hwop_get_func_t get; + cfa_tcam_mgr_hwop_free_func_t free; +}; +#endif /* CFA_TCAM_MGR_DEVICE_H */ diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.c b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.c new file mode 100644 index 0000000000..0fb5563cc3 --- /dev/null +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.c @@ -0,0 +1,201 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2021-2023 Broadcom + * All rights reserved. + */ + +/* + * This file will "do the right thing" for each of the primitives set, get and + * free. The TCAM manager is running in the core, so the tables will be cached. + * Set and free messages will also be sent to the firmware. Instead of sending + * get messages, the entry will be read from the cached copy thus saving a + * firmware message. + */ + +#include "tf_tcam.h" +#include "hcapi_cfa_defs.h" +#include "cfa_tcam_mgr.h" +#include "cfa_tcam_mgr_hwop_msg.h" +#include "cfa_tcam_mgr_device.h" +#include "cfa_tcam_mgr_p58.h" +#include "cfa_tcam_mgr_p4.h" +#include "tf_session.h" +#include "tf_msg.h" +#include "tfp.h" +#include "tf_util.h" + +/* + * The free hwop will free more than a single slice so cannot be used. + */ +struct cfa_tcam_mgr_hwops_funcs hwop_funcs; + +int +cfa_tcam_mgr_hwops_init(enum cfa_tcam_mgr_device_type type) +{ + switch (type) { + case CFA_TCAM_MGR_DEVICE_TYPE_P4: + case CFA_TCAM_MGR_DEVICE_TYPE_SR: + return cfa_tcam_mgr_hwops_get_funcs_p4(&hwop_funcs); + case CFA_TCAM_MGR_DEVICE_TYPE_P5: + return cfa_tcam_mgr_hwops_get_funcs_p58(&hwop_funcs); + default: + CFA_TCAM_MGR_LOG(ERR, "No such device\n"); + return -CFA_TCAM_MGR_ERR_CODE(NODEV); + } +} + +/* + * This is the glue between the TCAM manager and the firmware HW operations. It + * is intended to abstract out the location of the TCAM manager so that the TCAM + * manager code will be the same whether or not it is actually using the + * firmware. + */ + +int +cfa_tcam_mgr_entry_set_msg(int sess_idx, struct cfa_tcam_mgr_context *context + __rte_unused, + struct cfa_tcam_mgr_set_parms *parms, + int row, int slice, + int max_slices __rte_unused) +{ + cfa_tcam_mgr_hwop_set_func_t set_func; + + set_func = hwop_funcs.set; + if (set_func == NULL) + return -CFA_TCAM_MGR_ERR_CODE(PERM); + + struct tf_tcam_set_parms sparms; + struct tf_session *tfs; + struct tf_dev_info *dev; + int rc; + enum tf_tcam_tbl_type type = + cfa_tcam_mgr_get_phys_table_type(parms->type); + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(context->tfp, &tfs); + if (rc) + return rc; + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) + return rc; + + memset(&sparms, 0, sizeof(sparms)); + sparms.dir = parms->dir; + sparms.type = type; + sparms.hcapi_type = parms->hcapi_type; + sparms.idx = (row * max_slices) + slice; + sparms.key = parms->key; + sparms.mask = parms->mask; + sparms.key_size = parms->key_size; + sparms.result = parms->result; + sparms.result_size = parms->result_size; + + rc = tf_msg_tcam_entry_set(context->tfp, dev, &sparms); + if (rc) { + /* Log error */ + CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, parms->dir, parms->type, + "Entry %d set failed, rc:%d\n", + parms->id, -rc); + return rc; + } + + return set_func(sess_idx, parms, row, slice, max_slices); +} + +int +cfa_tcam_mgr_entry_get_msg(int sess_idx, struct cfa_tcam_mgr_context *context + __rte_unused, + struct cfa_tcam_mgr_get_parms *parms, + int row, int slice, + int max_slices __rte_unused) +{ + cfa_tcam_mgr_hwop_get_func_t get_func; + + get_func = hwop_funcs.get; + if (get_func == NULL) + return -CFA_TCAM_MGR_ERR_CODE(PERM); + + return get_func(sess_idx, parms, row, slice, max_slices); +} + +int +cfa_tcam_mgr_entry_free_msg(int sess_idx, struct cfa_tcam_mgr_context *context + __rte_unused, + struct cfa_tcam_mgr_free_parms *parms, + int row, int slice, + int key_size, + int result_size, + int max_slices) +{ + cfa_tcam_mgr_hwop_free_func_t free_func; + + free_func = hwop_funcs.free; + if (free_func == NULL) + return -CFA_TCAM_MGR_ERR_CODE(PERM); + + struct tf_dev_info *dev; + struct tf_session *tfs; + int rc; + enum tf_tcam_tbl_type type = + cfa_tcam_mgr_get_phys_table_type(parms->type); + + /* Free will clear an entire row. */ + /* Use set message to clear an individual entry */ + struct tf_tcam_set_parms sparms; + uint8_t key[CFA_TCAM_MGR_MAX_KEY_SIZE] = { 0 }; + uint8_t mask[CFA_TCAM_MGR_MAX_KEY_SIZE] = { 0 }; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(context->tfp, &tfs); + if (rc) + return rc; + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) + return rc; + + if (key_size > CFA_TCAM_MGR_MAX_KEY_SIZE) { + CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, parms->dir, parms->type, + "Entry %d key size is %d greater than:%d\n", + parms->id, key_size, + CFA_TCAM_MGR_MAX_KEY_SIZE); + return -EINVAL; + } + + if (result_size > CFA_TCAM_MGR_MAX_KEY_SIZE) { + CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, parms->dir, parms->type, + "Entry %d result size is %d greater than:%d\n", + parms->id, result_size, + CFA_TCAM_MGR_MAX_KEY_SIZE); + return -EINVAL; + } + + memset(&sparms, 0, sizeof(sparms)); + memset(&key, 0, sizeof(key)); + memset(&mask, 0xff, sizeof(mask)); + + sparms.dir = parms->dir; + sparms.type = type; + sparms.hcapi_type = parms->hcapi_type; + sparms.key = key; + sparms.mask = mask; + sparms.result = key; + sparms.idx = (row * max_slices) + slice; + sparms.key_size = key_size; + sparms.result_size = result_size; + + rc = tf_msg_tcam_entry_set(context->tfp, dev, &sparms); + if (rc) { + /* Log error */ + CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, parms->dir, parms->type, + "Row %d, slice %d set failed, " + "rc:%d.\n", + row, + slice, + rc); + return rc; + } + return free_func(sess_idx, parms, row, slice, max_slices); +} diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.h new file mode 100644 index 0000000000..f7ba625c07 --- /dev/null +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2021-2023 Broadcom + * All rights reserved. + */ + +#ifndef CFA_TCAM_MGR_HWOP_MSG_H +#define CFA_TCAM_MGR_HWOP_MSG_H + +int +cfa_tcam_mgr_hwops_init(enum cfa_tcam_mgr_device_type type); + +int +cfa_tcam_mgr_entry_set_msg(int sess_idx, + struct cfa_tcam_mgr_context *context, + struct cfa_tcam_mgr_set_parms *parms, + int row, int slice, int max_slices); +int +cfa_tcam_mgr_entry_get_msg(int sess_idx, + struct cfa_tcam_mgr_context *context, + struct cfa_tcam_mgr_get_parms *parms, + int row, int slice, int max_slices); +int +cfa_tcam_mgr_entry_free_msg(int sess_idx, + struct cfa_tcam_mgr_context *context, + struct cfa_tcam_mgr_free_parms *parms, + int row, int slice, int key_size, + int result_size, int max_slices); +#endif /* CFA_TCAM_MGR_HWOP_MSG_H */ diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c new file mode 100644 index 0000000000..63c84c5938 --- /dev/null +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c @@ -0,0 +1,921 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2021-2023 Broadcom + * All rights reserved. + */ + +#include "hcapi_cfa_defs.h" + +#include "cfa_tcam_mgr.h" +#include "cfa_tcam_mgr_p4.h" +#include "cfa_tcam_mgr_device.h" +#include "cfa_resource_types.h" +#include "tfp.h" +#include "assert.h" +#include "tf_util.h" + +/* + * Sizings of the TCAMs on P4 + */ + +#define MAX_ROW_WIDTH 48 +#define MAX_RESULT_SIZE 8 + +#if MAX_ROW_WIDTH > CFA_TCAM_MGR_MAX_KEY_SIZE +#error MAX_ROW_WIDTH > CFA_TCAM_MGR_MAX_KEY_SIZE +#endif + +/* + * TCAM definitions + * + * These define the TCAMs in HW. + * + * Note: Set xxx_TCAM_[R|T]X_NUM_ROWS to zero if a TCAM is either not supported + * by HW or not supported by TCAM Manager. + */ + +/** L2 Context TCAM */ +#define L2_CTXT_TCAM_RX_MAX_SLICES 1 +#define L2_CTXT_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_WORD_ALIGN(167) +#define L2_CTXT_TCAM_RX_NUM_ROWS 1024 +#define L2_CTXT_TCAM_RX_MAX_ENTRIES (L2_CTXT_TCAM_RX_MAX_SLICES * \ + L2_CTXT_TCAM_RX_NUM_ROWS) +#define L2_CTXT_TCAM_RX_RESULT_SIZE 8 + +#define L2_CTXT_TCAM_TX_MAX_SLICES L2_CTXT_TCAM_RX_MAX_SLICES +#define L2_CTXT_TCAM_TX_ROW_WIDTH L2_CTXT_TCAM_RX_ROW_WIDTH +#define L2_CTXT_TCAM_TX_NUM_ROWS L2_CTXT_TCAM_RX_NUM_ROWS +#define L2_CTXT_TCAM_TX_MAX_ENTRIES L2_CTXT_TCAM_RX_MAX_ENTRIES +#define L2_CTXT_TCAM_TX_RESULT_SIZE L2_CTXT_TCAM_RX_RESULT_SIZE + +/** Profile TCAM */ +#define PROF_TCAM_RX_MAX_SLICES 1 +#define PROF_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_WORD_ALIGN(81) +#define PROF_TCAM_RX_NUM_ROWS 1024 +#define PROF_TCAM_RX_MAX_ENTRIES (PROF_TCAM_RX_MAX_SLICES * \ + PROF_TCAM_RX_NUM_ROWS) +#define PROF_TCAM_RX_RESULT_SIZE 8 + +#define PROF_TCAM_TX_MAX_SLICES PROF_TCAM_RX_MAX_SLICES +#define PROF_TCAM_TX_ROW_WIDTH PROF_TCAM_RX_ROW_WIDTH +#define PROF_TCAM_TX_NUM_ROWS PROF_TCAM_RX_NUM_ROWS +#define PROF_TCAM_TX_MAX_ENTRIES PROF_TCAM_RX_MAX_ENTRIES +#define PROF_TCAM_TX_RESULT_SIZE PROF_TCAM_RX_RESULT_SIZE + +/** Wildcard TCAM */ +#define WC_TCAM_RX_MAX_SLICES 4 +/* 82 bits per slice */ +#define WC_TCAM_RX_ROW_WIDTH (TF_BITS2BYTES_WORD_ALIGN(82) * \ + WC_TCAM_RX_MAX_SLICES) +#define WC_TCAM_RX_NUM_ROWS 256 +#define WC_TCAM_RX_MAX_ENTRIES (WC_TCAM_RX_MAX_SLICES * WC_TCAM_RX_NUM_ROWS) +#define WC_TCAM_RX_RESULT_SIZE 4 + +#define WC_TCAM_TX_MAX_SLICES WC_TCAM_RX_MAX_SLICES +#define WC_TCAM_TX_ROW_WIDTH WC_TCAM_RX_ROW_WIDTH +#define WC_TCAM_TX_NUM_ROWS WC_TCAM_RX_NUM_ROWS +#define WC_TCAM_TX_MAX_ENTRIES WC_TCAM_RX_MAX_ENTRIES +#define WC_TCAM_TX_RESULT_SIZE WC_TCAM_RX_RESULT_SIZE + +/** Source Properties TCAM */ +#define SP_TCAM_RX_MAX_SLICES 1 +#define SP_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_WORD_ALIGN(89) +#define SP_TCAM_RX_NUM_ROWS 512 +#define SP_TCAM_RX_MAX_ENTRIES (SP_TCAM_RX_MAX_SLICES * SP_TCAM_RX_NUM_ROWS) +#define SP_TCAM_RX_RESULT_SIZE 8 + +#define SP_TCAM_TX_MAX_SLICES SP_TCAM_RX_MAX_SLICES +#define SP_TCAM_TX_ROW_WIDTH SP_TCAM_RX_ROW_WIDTH +#define SP_TCAM_TX_NUM_ROWS SP_TCAM_RX_NUM_ROWS +#define SP_TCAM_TX_MAX_ENTRIES SP_TCAM_RX_MAX_ENTRIES +#define SP_TCAM_TX_RESULT_SIZE SP_TCAM_RX_RESULT_SIZE + +/** Connection Tracking Rule TCAM */ +#define CT_RULE_TCAM_RX_MAX_SLICES 1 +#define CT_RULE_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_WORD_ALIGN(16) +#define CT_RULE_TCAM_RX_NUM_ROWS 0 +#define CT_RULE_TCAM_RX_MAX_ENTRIES (CT_RULE_TCAM_RX_MAX_SLICES * \ + CT_RULE_TCAM_RX_NUM_ROWS) +#define CT_RULE_TCAM_RX_RESULT_SIZE 8 + +#define CT_RULE_TCAM_TX_MAX_SLICES CT_RULE_TCAM_RX_MAX_SLICES +#define CT_RULE_TCAM_TX_ROW_WIDTH CT_RULE_TCAM_RX_ROW_WIDTH +#define CT_RULE_TCAM_TX_NUM_ROWS CT_RULE_TCAM_RX_NUM_ROWS +#define CT_RULE_TCAM_TX_MAX_ENTRIES CT_RULE_TCAM_RX_MAX_ENTRIES +#define CT_RULE_TCAM_TX_RESULT_SIZE CT_RULE_TCAM_RX_RESULT_SIZE + +/** Virtual Edge Bridge TCAM */ +#define VEB_TCAM_RX_MAX_SLICES 1 +#define VEB_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_WORD_ALIGN(78) +/* Tx only */ +#define VEB_TCAM_RX_NUM_ROWS 0 +#define VEB_TCAM_RX_MAX_ENTRIES (VEB_TCAM_RX_MAX_SLICES * VEB_TCAM_RX_NUM_ROWS) +#define VEB_TCAM_RX_RESULT_SIZE 8 + +#define VEB_TCAM_TX_MAX_SLICES VEB_TCAM_RX_MAX_SLICES +#define VEB_TCAM_TX_ROW_WIDTH VEB_TCAM_RX_ROW_WIDTH +#define VEB_TCAM_TX_NUM_ROWS 1024 +#define VEB_TCAM_TX_MAX_ENTRIES (VEB_TCAM_TX_MAX_SLICES * VEB_TCAM_TX_NUM_ROWS) +#define VEB_TCAM_TX_RESULT_SIZE VEB_TCAM_RX_RESULT_SIZE + +/* Declare the table rows for each table here. If new tables are added to the + * enum tf_tcam_tbl_type, then new declarations will be needed here. + * + * The numeric suffix of the structure type indicates how many slices a + * particular TCAM supports. + * + * Array sizes have 1 added to avoid zero length arrays. + */ + +static struct cfa_tcam_mgr_table_rows_1 + cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[TF_TCAM_MAX_SESSIONS][L2_CTXT_TCAM_RX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_1 + cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[TF_TCAM_MAX_SESSIONS][L2_CTXT_TCAM_TX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_1 + cfa_tcam_mgr_table_rows_PROF_TCAM_RX[TF_TCAM_MAX_SESSIONS][PROF_TCAM_RX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_1 + cfa_tcam_mgr_table_rows_PROF_TCAM_TX[TF_TCAM_MAX_SESSIONS][PROF_TCAM_TX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_4 + cfa_tcam_mgr_table_rows_WC_TCAM_RX[TF_TCAM_MAX_SESSIONS][WC_TCAM_RX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_4 + cfa_tcam_mgr_table_rows_WC_TCAM_TX[TF_TCAM_MAX_SESSIONS][WC_TCAM_TX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_1 + cfa_tcam_mgr_table_rows_SP_TCAM_RX[TF_TCAM_MAX_SESSIONS][SP_TCAM_RX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_1 + cfa_tcam_mgr_table_rows_SP_TCAM_TX[TF_TCAM_MAX_SESSIONS][SP_TCAM_TX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_1 + cfa_tcam_mgr_table_rows_CT_RULE_TCAM_RX[TF_TCAM_MAX_SESSIONS][CT_RULE_TCAM_RX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_1 + cfa_tcam_mgr_table_rows_CT_RULE_TCAM_TX[TF_TCAM_MAX_SESSIONS][CT_RULE_TCAM_TX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_1 + cfa_tcam_mgr_table_rows_VEB_TCAM_RX[TF_TCAM_MAX_SESSIONS][VEB_TCAM_RX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_1 + cfa_tcam_mgr_table_rows_VEB_TCAM_TX[TF_TCAM_MAX_SESSIONS][VEB_TCAM_TX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_4 + cfa_tcam_mgr_table_rows_WC_TCAM_RX_HIGH[TF_TCAM_MAX_SESSIONS][WC_TCAM_RX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_4 + cfa_tcam_mgr_table_rows_WC_TCAM_RX_LOW[TF_TCAM_MAX_SESSIONS][WC_TCAM_RX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_4 + cfa_tcam_mgr_table_rows_WC_TCAM_TX_HIGH[TF_TCAM_MAX_SESSIONS][WC_TCAM_TX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_4 + cfa_tcam_mgr_table_rows_WC_TCAM_TX_LOW[TF_TCAM_MAX_SESSIONS][WC_TCAM_TX_NUM_ROWS + 1]; + +struct cfa_tcam_mgr_table_data +cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { + { /* RX */ + { /* High AFM */ + .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES, + .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH, + .num_rows = L2_CTXT_TCAM_RX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH, + }, + { /* High APPS */ + .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES, + .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH, + .num_rows = L2_CTXT_TCAM_RX_NUM_ROWS, + .start_row = 0, + .end_row = (L2_CTXT_TCAM_RX_NUM_ROWS / 2) - 1, + .max_entries = (L2_CTXT_TCAM_RX_MAX_ENTRIES / 2), + .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH, + }, + { /* Low AFM */ + .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES, + .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH, + .num_rows = L2_CTXT_TCAM_RX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW, + }, + { /* Low APPS */ + .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES, + .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH, + .num_rows = L2_CTXT_TCAM_RX_NUM_ROWS, + .start_row = (L2_CTXT_TCAM_RX_NUM_ROWS / 2), + .end_row = L2_CTXT_TCAM_RX_NUM_ROWS - 1, + .max_entries = (L2_CTXT_TCAM_RX_MAX_ENTRIES / 2), + .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW, + }, + { /* AFM */ + .max_slices = PROF_TCAM_RX_MAX_SLICES, + .row_width = PROF_TCAM_RX_ROW_WIDTH, + .num_rows = PROF_TCAM_RX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = PROF_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P4_PROF_TCAM, + }, + { /* APPS */ + .max_slices = PROF_TCAM_RX_MAX_SLICES, + .row_width = PROF_TCAM_RX_ROW_WIDTH, + .num_rows = PROF_TCAM_RX_NUM_ROWS, + .start_row = 0, + .end_row = PROF_TCAM_RX_NUM_ROWS - 1, + .max_entries = PROF_TCAM_RX_MAX_ENTRIES, + .result_size = PROF_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P4_PROF_TCAM, + }, + { /* AFM */ + .max_slices = WC_TCAM_RX_MAX_SLICES, + .row_width = WC_TCAM_RX_ROW_WIDTH, + .num_rows = WC_TCAM_RX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = WC_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM, + }, + { /* APPS */ + .max_slices = WC_TCAM_RX_MAX_SLICES, + .row_width = WC_TCAM_RX_ROW_WIDTH, + .num_rows = WC_TCAM_RX_NUM_ROWS, + .start_row = 0, + .end_row = WC_TCAM_RX_NUM_ROWS - 1, + .max_entries = WC_TCAM_RX_MAX_ENTRIES, + .result_size = WC_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM, + }, + { /* AFM */ + .max_slices = SP_TCAM_RX_MAX_SLICES, + .row_width = SP_TCAM_RX_ROW_WIDTH, + .num_rows = SP_TCAM_RX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = SP_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P4_SP_TCAM, + }, + { /* APPS */ + .max_slices = SP_TCAM_RX_MAX_SLICES, + .row_width = SP_TCAM_RX_ROW_WIDTH, + .num_rows = SP_TCAM_RX_NUM_ROWS, + .start_row = 0, + .end_row = SP_TCAM_RX_NUM_ROWS - 1, + .max_entries = SP_TCAM_RX_MAX_ENTRIES, + .result_size = SP_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P4_SP_TCAM, + }, + { /* AFM */ + .max_slices = CT_RULE_TCAM_RX_MAX_SLICES, + .row_width = CT_RULE_TCAM_RX_ROW_WIDTH, + .num_rows = CT_RULE_TCAM_RX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = CT_RULE_TCAM_RX_RESULT_SIZE, + }, + { /* APPS */ + .max_slices = CT_RULE_TCAM_RX_MAX_SLICES, + .row_width = CT_RULE_TCAM_RX_ROW_WIDTH, + .num_rows = CT_RULE_TCAM_RX_NUM_ROWS, + .start_row = 0, +#if CT_RULE_TCAM_RX_NUM_ROWS > 0 + .end_row = CT_RULE_TCAM_RX_NUM_ROWS - 1, +#else + .end_row = CT_RULE_TCAM_RX_NUM_ROWS, +#endif + .max_entries = CT_RULE_TCAM_RX_MAX_ENTRIES, + .result_size = CT_RULE_TCAM_RX_RESULT_SIZE, + }, + { /* AFM */ + .max_slices = VEB_TCAM_RX_MAX_SLICES, + .row_width = VEB_TCAM_RX_ROW_WIDTH, + .num_rows = VEB_TCAM_RX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = VEB_TCAM_RX_RESULT_SIZE, + }, + { /* APPS */ + .max_slices = VEB_TCAM_RX_MAX_SLICES, + .row_width = VEB_TCAM_RX_ROW_WIDTH, + .num_rows = VEB_TCAM_RX_NUM_ROWS, + .start_row = 0, +#if VEB_TCAM_RX_NUM_ROWS > 0 + .end_row = VEB_TCAM_RX_NUM_ROWS - 1, +#else + .end_row = VEB_TCAM_RX_NUM_ROWS, +#endif + .max_entries = VEB_TCAM_RX_MAX_ENTRIES, + .result_size = VEB_TCAM_RX_RESULT_SIZE, + }, + { /* AFM */ + .max_slices = WC_TCAM_RX_MAX_SLICES, + .row_width = WC_TCAM_RX_ROW_WIDTH, + .num_rows = WC_TCAM_RX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = WC_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM, + }, + { /* APPS */ + .max_slices = WC_TCAM_RX_MAX_SLICES, + .row_width = WC_TCAM_RX_ROW_WIDTH, + .num_rows = WC_TCAM_RX_NUM_ROWS, + .start_row = 0, + .end_row = WC_TCAM_RX_NUM_ROWS - 1, + .max_entries = WC_TCAM_RX_MAX_ENTRIES, + .result_size = WC_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM, + }, + { /* AFM */ + .max_slices = WC_TCAM_RX_MAX_SLICES, + .row_width = WC_TCAM_RX_ROW_WIDTH, + .num_rows = WC_TCAM_RX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = WC_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM, + }, + { /* APPS */ + .max_slices = WC_TCAM_RX_MAX_SLICES, + .row_width = WC_TCAM_RX_ROW_WIDTH, + .num_rows = WC_TCAM_RX_NUM_ROWS, + .start_row = 0, + .end_row = WC_TCAM_RX_NUM_ROWS - 1, + .max_entries = WC_TCAM_RX_MAX_ENTRIES, + .result_size = WC_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM, + }, + }, + { /* TX */ + { /* AFM */ + .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES, + .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH, + .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH, + }, + { /* APPS */ + .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES, + .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH, + .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = (L2_CTXT_TCAM_TX_NUM_ROWS / 2) - 1, + .max_entries = (L2_CTXT_TCAM_TX_MAX_ENTRIES / 2), + .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH, + }, + { /* AFM */ + .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES, + .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH, + .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW, + }, + { /* APPS */ + .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES, + .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH, + .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS, + .start_row = (L2_CTXT_TCAM_TX_NUM_ROWS / 2), + .end_row = L2_CTXT_TCAM_TX_NUM_ROWS - 1, + .max_entries = (L2_CTXT_TCAM_TX_MAX_ENTRIES / 2), + .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW, + }, + { /* AFM */ + .max_slices = PROF_TCAM_TX_MAX_SLICES, + .row_width = PROF_TCAM_TX_ROW_WIDTH, + .num_rows = PROF_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = PROF_TCAM_TX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P4_PROF_TCAM, + }, + { /* APPS */ + .max_slices = PROF_TCAM_TX_MAX_SLICES, + .row_width = PROF_TCAM_TX_ROW_WIDTH, + .num_rows = PROF_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = PROF_TCAM_TX_NUM_ROWS - 1, + .max_entries = PROF_TCAM_TX_MAX_ENTRIES, + .result_size = PROF_TCAM_TX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P4_PROF_TCAM, + }, + { /* AFM */ + .max_slices = WC_TCAM_TX_MAX_SLICES, + .row_width = WC_TCAM_TX_ROW_WIDTH, + .num_rows = WC_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = WC_TCAM_TX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM, + }, + { /* APPS */ + .max_slices = WC_TCAM_TX_MAX_SLICES, + .row_width = WC_TCAM_TX_ROW_WIDTH, + .num_rows = WC_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = WC_TCAM_TX_NUM_ROWS - 1, + .max_entries = WC_TCAM_TX_MAX_ENTRIES, + .result_size = WC_TCAM_TX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM, + }, + { /* AFM */ + .max_slices = SP_TCAM_TX_MAX_SLICES, + .row_width = SP_TCAM_TX_ROW_WIDTH, + .num_rows = SP_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = SP_TCAM_TX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P4_SP_TCAM, + }, + { /* APPS */ + .max_slices = SP_TCAM_TX_MAX_SLICES, + .row_width = SP_TCAM_TX_ROW_WIDTH, + .num_rows = SP_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = SP_TCAM_TX_NUM_ROWS - 1, + .max_entries = SP_TCAM_TX_MAX_ENTRIES, + .result_size = SP_TCAM_TX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P4_SP_TCAM, + }, + { /* AFM */ + .max_slices = CT_RULE_TCAM_TX_MAX_SLICES, + .row_width = CT_RULE_TCAM_TX_ROW_WIDTH, + .num_rows = CT_RULE_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = CT_RULE_TCAM_RX_RESULT_SIZE, + }, + { /* APPS */ + .max_slices = CT_RULE_TCAM_TX_MAX_SLICES, + .row_width = CT_RULE_TCAM_TX_ROW_WIDTH, + .num_rows = CT_RULE_TCAM_TX_NUM_ROWS, + .start_row = 0, +#if CT_RULE_TCAM_TX_NUM_ROWS > 0 + .end_row = CT_RULE_TCAM_TX_NUM_ROWS - 1, +#else + .end_row = CT_RULE_TCAM_TX_NUM_ROWS, +#endif + .max_entries = CT_RULE_TCAM_TX_MAX_ENTRIES, + .result_size = CT_RULE_TCAM_RX_RESULT_SIZE, + }, + { /* AFM */ + .max_slices = VEB_TCAM_TX_MAX_SLICES, + .row_width = VEB_TCAM_TX_ROW_WIDTH, + .num_rows = VEB_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = VEB_TCAM_RX_RESULT_SIZE, + }, + { /* APPS */ + .max_slices = VEB_TCAM_TX_MAX_SLICES, + .row_width = VEB_TCAM_TX_ROW_WIDTH, + .num_rows = VEB_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = VEB_TCAM_TX_NUM_ROWS - 1, + .max_entries = VEB_TCAM_TX_MAX_ENTRIES, + .result_size = VEB_TCAM_RX_RESULT_SIZE, + }, + { /* AFM */ + .max_slices = WC_TCAM_TX_MAX_SLICES, + .row_width = WC_TCAM_TX_ROW_WIDTH, + .num_rows = WC_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = WC_TCAM_TX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM, + }, + { /* APPS */ + .max_slices = WC_TCAM_TX_MAX_SLICES, + .row_width = WC_TCAM_TX_ROW_WIDTH, + .num_rows = WC_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = WC_TCAM_TX_NUM_ROWS - 1, + .max_entries = WC_TCAM_TX_MAX_ENTRIES, + .result_size = WC_TCAM_TX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM, + }, + { /* AFM */ + .max_slices = WC_TCAM_TX_MAX_SLICES, + .row_width = WC_TCAM_TX_ROW_WIDTH, + .num_rows = WC_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = WC_TCAM_TX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM, + }, + { /* APPS */ + .max_slices = WC_TCAM_TX_MAX_SLICES, + .row_width = WC_TCAM_TX_ROW_WIDTH, + .num_rows = WC_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = WC_TCAM_TX_NUM_ROWS - 1, + .max_entries = WC_TCAM_TX_MAX_ENTRIES, + .result_size = WC_TCAM_TX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM, + }, + }, +}; + +static struct cfa_tcam_mgr_entry_data entry_data_p4[TF_TCAM_MAX_SESSIONS][TF_TCAM_MAX_ENTRIES]; + +static struct sbmp session_bmp_p4[TF_TCAM_MAX_SESSIONS][TF_TCAM_MAX_ENTRIES]; + +int +cfa_tcam_mgr_sess_table_get_p4(int sess_idx, struct sbmp **session_bmp) +{ + *session_bmp = session_bmp_p4[sess_idx]; + return 0; +} + +int +cfa_tcam_mgr_init_p4(int sess_idx, struct cfa_tcam_mgr_entry_data **global_entry_data) +{ + int max_row_width = 0; + int max_result_size = 0; + int dir, type; + + *global_entry_data = entry_data_p4[sess_idx]; + + memcpy(&cfa_tcam_mgr_tables[sess_idx], + &cfa_tcam_mgr_tables_p4, + sizeof(cfa_tcam_mgr_tables[sess_idx])); + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_PROF_TCAM_RX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_PROF_TCAM_RX[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_PROF_TCAM_TX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_PROF_TCAM_TX[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_WC_TCAM_RX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_WC_TCAM_RX[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_WC_TCAM_TX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_WC_TCAM_TX[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_SP_TCAM_RX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_SP_TCAM_RX[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_SP_TCAM_TX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_SP_TCAM_TX[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_RX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_RX[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_TX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_TX[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_VEB_TCAM_RX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_VEB_TCAM_RX[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_VEB_TCAM_TX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_VEB_TCAM_TX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_WC_TCAM_RX_HIGH[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_WC_TCAM_RX_HIGH[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_WC_TCAM_TX_HIGH[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_WC_TCAM_TX_HIGH[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_WC_TCAM_RX_LOW[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_WC_TCAM_RX_LOW[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_WC_TCAM_TX_LOW[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_WC_TCAM_TX_LOW[sess_idx]; + + for (dir = 0; dir < TF_DIR_MAX; dir++) { + for (type = 0; type < CFA_TCAM_MGR_TBL_TYPE_MAX; type++) { + if (cfa_tcam_mgr_tables[sess_idx][dir][type].row_width > + max_row_width) + max_row_width = + cfa_tcam_mgr_tables[sess_idx][dir][type].row_width; + if (cfa_tcam_mgr_tables[sess_idx][dir][type].result_size > + max_result_size) + max_result_size = + cfa_tcam_mgr_tables[sess_idx][dir][type].result_size; + } + } + + if (max_row_width != MAX_ROW_WIDTH) { + CFA_TCAM_MGR_LOG(ERR, + "MAX_ROW_WIDTH (%d) does not match actual " + "value (%d).\n", + MAX_ROW_WIDTH, + max_row_width); + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + } + if (max_result_size != MAX_RESULT_SIZE) { + CFA_TCAM_MGR_LOG(ERR, + "MAX_RESULT_SIZE (%d) does not match actual " + "value (%d).\n", + MAX_RESULT_SIZE, + max_result_size); + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + } + return 0; +} + +/* HW OP declarations begin here */ +struct cfa_tcam_mgr_TCAM_row_data { + int key_size; + int result_size; + uint8_t key[MAX_ROW_WIDTH]; + uint8_t mask[MAX_ROW_WIDTH]; + uint8_t result[MAX_RESULT_SIZE]; +}; + +/* These macros are only needed to avoid exceeding 80 columns */ +#define L2_CTXT_RX_MAX_ROWS \ + (L2_CTXT_TCAM_RX_MAX_SLICES * L2_CTXT_TCAM_RX_NUM_ROWS) +#define PROF_RX_MAX_ROWS (PROF_TCAM_RX_MAX_SLICES * PROF_TCAM_RX_NUM_ROWS) +#define WC_RX_MAX_ROWS (WC_TCAM_RX_MAX_SLICES * WC_TCAM_RX_NUM_ROWS) +#define SP_RX_MAX_ROWS (SP_TCAM_RX_MAX_SLICES * SP_TCAM_RX_NUM_ROWS) +#define CT_RULE_RX_MAX_ROWS \ + (CT_RULE_TCAM_RX_MAX_SLICES * CT_RULE_TCAM_RX_NUM_ROWS) +#define VEB_RX_MAX_ROWS (VEB_TCAM_RX_MAX_SLICES * VEB_TCAM_RX_NUM_ROWS) + +#define L2_CTXT_TX_MAX_ROWS \ + (L2_CTXT_TCAM_TX_MAX_SLICES * L2_CTXT_TCAM_TX_NUM_ROWS) +#define PROF_TX_MAX_ROWS (PROF_TCAM_TX_MAX_SLICES * PROF_TCAM_TX_NUM_ROWS) +#define WC_TX_MAX_ROWS (WC_TCAM_TX_MAX_SLICES * WC_TCAM_TX_NUM_ROWS) +#define SP_TX_MAX_ROWS (SP_TCAM_TX_MAX_SLICES * SP_TCAM_TX_NUM_ROWS) +#define CT_RULE_TX_MAX_ROWS \ + (CT_RULE_TCAM_TX_MAX_SLICES * CT_RULE_TCAM_TX_NUM_ROWS) +#define VEB_TX_MAX_ROWS (VEB_TCAM_TX_MAX_SLICES * VEB_TCAM_TX_NUM_ROWS) + +static int cfa_tcam_mgr_max_rows[TF_TCAM_TBL_TYPE_MAX] = { + L2_CTXT_RX_MAX_ROWS, + L2_CTXT_RX_MAX_ROWS, + PROF_RX_MAX_ROWS, + WC_RX_MAX_ROWS, + SP_RX_MAX_ROWS, + CT_RULE_RX_MAX_ROWS, + VEB_RX_MAX_ROWS, + WC_RX_MAX_ROWS, + WC_RX_MAX_ROWS +}; +static struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][L2_CTXT_RX_MAX_ROWS]; +static struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_PROF_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][PROF_RX_MAX_ROWS]; +static struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_WC_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][WC_RX_MAX_ROWS]; +static struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_SP_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][SP_RX_MAX_ROWS]; +static struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_CT_RULE_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][CT_RULE_RX_MAX_ROWS]; +static struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_VEB_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][VEB_RX_MAX_ROWS]; +static struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_WC_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][WC_RX_MAX_ROWS]; + +static struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][L2_CTXT_TX_MAX_ROWS]; +static struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_PROF_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][PROF_TX_MAX_ROWS]; +static struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_WC_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][WC_TX_MAX_ROWS]; +static struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_SP_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][SP_TX_MAX_ROWS]; +static struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_CT_RULE_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][CT_RULE_TX_MAX_ROWS]; +static struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_VEB_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][VEB_TX_MAX_ROWS]; +static struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_WC_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][WC_TX_MAX_ROWS]; + +static struct cfa_tcam_mgr_TCAM_row_data * +row_tables[TF_DIR_MAX][TF_TCAM_TBL_TYPE_MAX] = { + { + cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[0], + cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[0], + cfa_tcam_mgr_PROF_TCAM_RX_row_data[0], + cfa_tcam_mgr_WC_TCAM_RX_row_data[0], + cfa_tcam_mgr_SP_TCAM_RX_row_data[0], + cfa_tcam_mgr_CT_RULE_TCAM_RX_row_data[0], + cfa_tcam_mgr_VEB_TCAM_RX_row_data[0], + cfa_tcam_mgr_WC_TCAM_RX_row_data[0], + cfa_tcam_mgr_WC_TCAM_RX_row_data[0], + }, + { + cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[0], + cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[0], + cfa_tcam_mgr_PROF_TCAM_TX_row_data[0], + cfa_tcam_mgr_WC_TCAM_TX_row_data[0], + cfa_tcam_mgr_SP_TCAM_TX_row_data[0], + cfa_tcam_mgr_CT_RULE_TCAM_TX_row_data[0], + cfa_tcam_mgr_VEB_TCAM_TX_row_data[0], + cfa_tcam_mgr_WC_TCAM_TX_row_data[0], + cfa_tcam_mgr_WC_TCAM_TX_row_data[0], + } +}; + +static int cfa_tcam_mgr_get_max_rows(enum tf_tcam_tbl_type type) +{ + if (type >= TF_TCAM_TBL_TYPE_MAX) + assert(0); + else + return cfa_tcam_mgr_max_rows[type]; +} + +static int cfa_tcam_mgr_hwop_set(int sess_idx, + struct cfa_tcam_mgr_set_parms *parms, int row, + int slice, int max_slices) +{ + struct cfa_tcam_mgr_TCAM_row_data *this_table; + struct cfa_tcam_mgr_TCAM_row_data *this_row; + this_table = row_tables[parms->dir] + [cfa_tcam_mgr_get_phys_table_type(parms->type)]; + this_table += (sess_idx * + cfa_tcam_mgr_get_max_rows(cfa_tcam_mgr_get_phys_table_type(parms->type))); + this_row = &this_table[row * max_slices + slice]; + this_row->key_size = parms->key_size; + memcpy(&this_row->key, parms->key, parms->key_size); + memcpy(&this_row->mask, parms->mask, parms->key_size); + this_row->result_size = parms->result_size; + if (parms->result != ((void *)0)) + memcpy(&this_row->result, parms->result, parms->result_size); + return 0; +}; + +static int cfa_tcam_mgr_hwop_get(int sess_idx, + struct cfa_tcam_mgr_get_parms *parms, int row, + int slice, int max_slices) +{ + struct cfa_tcam_mgr_TCAM_row_data *this_table; + struct cfa_tcam_mgr_TCAM_row_data *this_row; + this_table = row_tables[parms->dir] + [cfa_tcam_mgr_get_phys_table_type(parms->type)]; + this_table += (sess_idx * + cfa_tcam_mgr_get_max_rows(cfa_tcam_mgr_get_phys_table_type(parms->type))); + this_row = &this_table[row * max_slices + slice]; + parms->key_size = this_row->key_size; + parms->result_size = this_row->result_size; + if (parms->key != ((void *)0)) + memcpy(parms->key, &this_row->key, parms->key_size); + if (parms->mask != ((void *)0)) + memcpy(parms->mask, &this_row->mask, parms->key_size); + if (parms->result != ((void *)0)) + memcpy(parms->result, &this_row->result, parms->result_size); + return 0; +}; + +static int cfa_tcam_mgr_hwop_free(int sess_idx, + struct cfa_tcam_mgr_free_parms *parms, + int row, int slice, int max_slices) +{ + struct cfa_tcam_mgr_TCAM_row_data *this_table; + struct cfa_tcam_mgr_TCAM_row_data *this_row; + this_table = row_tables[parms->dir] + [cfa_tcam_mgr_get_phys_table_type(parms->type)]; + this_table += (sess_idx * + cfa_tcam_mgr_get_max_rows(cfa_tcam_mgr_get_phys_table_type(parms->type))); + this_row = &this_table[row * max_slices + slice]; + memset(&this_row->key, 0, sizeof(this_row->key)); + memset(&this_row->mask, 0, sizeof(this_row->mask)); + memset(&this_row->result, 0, sizeof(this_row->result)); + this_row->key_size = 0; + this_row->result_size = 0; + return 0; +}; + +int cfa_tcam_mgr_hwops_get_funcs_p4(struct cfa_tcam_mgr_hwops_funcs *hwop_funcs) +{ + hwop_funcs->set = cfa_tcam_mgr_hwop_set; + hwop_funcs->get = cfa_tcam_mgr_hwop_get; + hwop_funcs->free = cfa_tcam_mgr_hwop_free; + return 0; +} diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.h new file mode 100644 index 0000000000..3ca59b2aeb --- /dev/null +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2021-2023 Broadcom + * All rights reserved. + */ + +#ifndef CFA_TCAM_MGR_P4_H +#define CFA_TCAM_MGR_P4_H + +#include "cfa_tcam_mgr_device.h" +#include "cfa_tcam_mgr_sbmp.h" + +int +cfa_tcam_mgr_init_p4(int sess_idx, struct cfa_tcam_mgr_entry_data **global_entry_data); + +int +cfa_tcam_mgr_sess_table_get_p4(int sess_idx, struct sbmp **session_bmp); + +int +cfa_tcam_mgr_hwops_get_funcs_p4(struct cfa_tcam_mgr_hwops_funcs *hwop_funcs); +#endif /* CFA_TCAM_MGR_P4_H */ diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c new file mode 100644 index 0000000000..c9a04dc4e9 --- /dev/null +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c @@ -0,0 +1,926 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2021-2023 Broadcom + * All rights reserved. + */ + +#include "hcapi_cfa_defs.h" + +#include "cfa_tcam_mgr.h" +#include "cfa_tcam_mgr_p58.h" +#include "cfa_tcam_mgr.h" +#include "cfa_tcam_mgr_device.h" +#include "cfa_resource_types.h" +#include "tfp.h" +#include "assert.h" +#include "tf_util.h" + +/* + * Sizings of the TCAMs on P5 + */ + +#define MAX_ROW_WIDTH 96 +#define MAX_RESULT_SIZE 8 + +#if MAX_ROW_WIDTH > CFA_TCAM_MGR_MAX_KEY_SIZE +#error MAX_ROW_WIDTH > CFA_TCAM_MGR_MAX_KEY_SIZE +#endif + +/* + * TCAM definitions + * + * These define the TCAMs in HW. + * + * Note: Set xxx_TCAM_[R|T]X_NUM_ROWS to zero if a TCAM is either not supported + * by HW or not supported by TCAM Manager. + */ + +/** L2 Context TCAM */ +#define L2_CTXT_TCAM_RX_MAX_SLICES 1 +#define L2_CTXT_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_64B_WORD_ALIGN(214) +#define L2_CTXT_TCAM_RX_NUM_ROWS 1024 +#define L2_CTXT_TCAM_RX_MAX_ENTRIES (L2_CTXT_TCAM_RX_MAX_SLICES * \ + L2_CTXT_TCAM_RX_NUM_ROWS) +#define L2_CTXT_TCAM_RX_RESULT_SIZE 8 + +#define L2_CTXT_TCAM_TX_MAX_SLICES L2_CTXT_TCAM_RX_MAX_SLICES +#define L2_CTXT_TCAM_TX_ROW_WIDTH L2_CTXT_TCAM_RX_ROW_WIDTH +#define L2_CTXT_TCAM_TX_NUM_ROWS L2_CTXT_TCAM_RX_NUM_ROWS +#define L2_CTXT_TCAM_TX_MAX_ENTRIES L2_CTXT_TCAM_RX_MAX_ENTRIES +#define L2_CTXT_TCAM_TX_RESULT_SIZE L2_CTXT_TCAM_RX_RESULT_SIZE + +/** Profile TCAM */ +#define PROF_TCAM_RX_MAX_SLICES 1 +#define PROF_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_64B_WORD_ALIGN(94) +#define PROF_TCAM_RX_NUM_ROWS 256 +#define PROF_TCAM_RX_MAX_ENTRIES (PROF_TCAM_RX_MAX_SLICES * \ + PROF_TCAM_RX_NUM_ROWS) +#define PROF_TCAM_RX_RESULT_SIZE 8 + +#define PROF_TCAM_TX_MAX_SLICES PROF_TCAM_RX_MAX_SLICES +#define PROF_TCAM_TX_ROW_WIDTH PROF_TCAM_RX_ROW_WIDTH +#define PROF_TCAM_TX_NUM_ROWS PROF_TCAM_RX_NUM_ROWS +#define PROF_TCAM_TX_MAX_ENTRIES PROF_TCAM_RX_MAX_ENTRIES +#define PROF_TCAM_TX_RESULT_SIZE PROF_TCAM_RX_RESULT_SIZE + +/** Wildcard TCAM */ +#define WC_TCAM_RX_MAX_SLICES 4 +/* 162 bits per slice */ +#define WC_TCAM_RX_ROW_WIDTH (TF_BITS2BYTES_64B_WORD_ALIGN(162) * \ + WC_TCAM_RX_MAX_SLICES) +#define WC_TCAM_RX_NUM_ROWS 2048 +#define WC_TCAM_RX_MAX_ENTRIES (WC_TCAM_RX_MAX_SLICES * WC_TCAM_RX_NUM_ROWS) +#define WC_TCAM_RX_RESULT_SIZE 8 + +#define WC_TCAM_TX_MAX_SLICES WC_TCAM_RX_MAX_SLICES +#define WC_TCAM_TX_ROW_WIDTH WC_TCAM_RX_ROW_WIDTH +#define WC_TCAM_TX_NUM_ROWS WC_TCAM_RX_NUM_ROWS +#define WC_TCAM_TX_MAX_ENTRIES WC_TCAM_RX_MAX_ENTRIES +#define WC_TCAM_TX_RESULT_SIZE WC_TCAM_RX_RESULT_SIZE + +/** Source Properties TCAM */ +#define SP_TCAM_RX_MAX_SLICES 1 +#define SP_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_64B_WORD_ALIGN(89) +#define SP_TCAM_RX_NUM_ROWS 0 +#define SP_TCAM_RX_MAX_ENTRIES (SP_TCAM_RX_MAX_SLICES * SP_TCAM_RX_NUM_ROWS) +#define SP_TCAM_RX_RESULT_SIZE 8 + +#define SP_TCAM_TX_MAX_SLICES SP_TCAM_RX_MAX_SLICES +#define SP_TCAM_TX_ROW_WIDTH SP_TCAM_RX_ROW_WIDTH +#define SP_TCAM_TX_NUM_ROWS SP_TCAM_RX_NUM_ROWS +#define SP_TCAM_TX_MAX_ENTRIES SP_TCAM_RX_MAX_ENTRIES +#define SP_TCAM_TX_RESULT_SIZE SP_TCAM_RX_RESULT_SIZE + +/** Connection Tracking Rule TCAM */ +#define CT_RULE_TCAM_RX_MAX_SLICES 1 +#define CT_RULE_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_64B_WORD_ALIGN(16) +#define CT_RULE_TCAM_RX_NUM_ROWS 0 +#define CT_RULE_TCAM_RX_MAX_ENTRIES (CT_RULE_TCAM_RX_MAX_SLICES * \ + CT_RULE_TCAM_RX_NUM_ROWS) +#define CT_RULE_TCAM_RX_RESULT_SIZE 8 + +#define CT_RULE_TCAM_TX_MAX_SLICES CT_RULE_TCAM_RX_MAX_SLICES +#define CT_RULE_TCAM_TX_ROW_WIDTH CT_RULE_TCAM_RX_ROW_WIDTH +#define CT_RULE_TCAM_TX_NUM_ROWS CT_RULE_TCAM_RX_NUM_ROWS +#define CT_RULE_TCAM_TX_MAX_ENTRIES CT_RULE_TCAM_RX_MAX_ENTRIES +#define CT_RULE_TCAM_TX_RESULT_SIZE CT_RULE_TCAM_RX_RESULT_SIZE + +/** Virtual Edge Bridge TCAM */ +#define VEB_TCAM_RX_MAX_SLICES 1 +#define VEB_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_WORD_ALIGN(79) +/* Tx only */ +#define VEB_TCAM_RX_NUM_ROWS 0 +#define VEB_TCAM_RX_MAX_ENTRIES (VEB_TCAM_RX_MAX_SLICES * VEB_TCAM_RX_NUM_ROWS) +#define VEB_TCAM_RX_RESULT_SIZE 8 + +#define VEB_TCAM_TX_MAX_SLICES VEB_TCAM_RX_MAX_SLICES +#define VEB_TCAM_TX_ROW_WIDTH VEB_TCAM_RX_ROW_WIDTH +#define VEB_TCAM_TX_NUM_ROWS 1024 +#define VEB_TCAM_TX_MAX_ENTRIES (VEB_TCAM_TX_MAX_SLICES * VEB_TCAM_TX_NUM_ROWS) +#define VEB_TCAM_TX_RESULT_SIZE VEB_TCAM_RX_RESULT_SIZE + +/* Declare the table rows for each table here. If new tables are added to the + * enum tf_tcam_tbl_type, then new declarations will be needed here. + * + * The numeric suffix of the structure type indicates how many slices a + * particular TCAM supports. + * + * Array sizes have 1 added to avoid zero length arrays. + */ + +static struct cfa_tcam_mgr_table_rows_1 + cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[TF_TCAM_MAX_SESSIONS][L2_CTXT_TCAM_RX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_1 + cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[TF_TCAM_MAX_SESSIONS][L2_CTXT_TCAM_TX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_1 + cfa_tcam_mgr_table_rows_PROF_TCAM_RX[TF_TCAM_MAX_SESSIONS][PROF_TCAM_RX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_1 + cfa_tcam_mgr_table_rows_PROF_TCAM_TX[TF_TCAM_MAX_SESSIONS][PROF_TCAM_TX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_4 + cfa_tcam_mgr_table_rows_WC_TCAM_RX[TF_TCAM_MAX_SESSIONS][WC_TCAM_RX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_4 + cfa_tcam_mgr_table_rows_WC_TCAM_TX[TF_TCAM_MAX_SESSIONS][WC_TCAM_TX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_1 + cfa_tcam_mgr_table_rows_SP_TCAM_RX[TF_TCAM_MAX_SESSIONS][SP_TCAM_RX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_1 + cfa_tcam_mgr_table_rows_SP_TCAM_TX[TF_TCAM_MAX_SESSIONS][SP_TCAM_TX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_1 + cfa_tcam_mgr_table_rows_CT_RULE_TCAM_RX[TF_TCAM_MAX_SESSIONS][CT_RULE_TCAM_RX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_1 + cfa_tcam_mgr_table_rows_CT_RULE_TCAM_TX[TF_TCAM_MAX_SESSIONS][CT_RULE_TCAM_TX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_1 + cfa_tcam_mgr_table_rows_VEB_TCAM_RX[TF_TCAM_MAX_SESSIONS][VEB_TCAM_RX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_1 + cfa_tcam_mgr_table_rows_VEB_TCAM_TX[TF_TCAM_MAX_SESSIONS][VEB_TCAM_TX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_4 + cfa_tcam_mgr_table_rows_WC_TCAM_RX_HIGH[TF_TCAM_MAX_SESSIONS][WC_TCAM_RX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_4 + cfa_tcam_mgr_table_rows_WC_TCAM_RX_LOW[TF_TCAM_MAX_SESSIONS][WC_TCAM_RX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_4 + cfa_tcam_mgr_table_rows_WC_TCAM_TX_HIGH[TF_TCAM_MAX_SESSIONS][WC_TCAM_TX_NUM_ROWS + 1]; +static struct cfa_tcam_mgr_table_rows_4 + cfa_tcam_mgr_table_rows_WC_TCAM_TX_LOW[TF_TCAM_MAX_SESSIONS][WC_TCAM_TX_NUM_ROWS + 1]; + +struct cfa_tcam_mgr_table_data +cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = { + { /* RX */ + { /* High AFM */ + .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES, + .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH, + .num_rows = 0, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH, + }, + { /* High APPS */ + .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES, + .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH, + .num_rows = L2_CTXT_TCAM_RX_NUM_ROWS, + .start_row = 0, + .end_row = (L2_CTXT_TCAM_RX_NUM_ROWS / 2) - 1, + .max_entries = (L2_CTXT_TCAM_RX_MAX_ENTRIES / 2), + .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH, + }, + { /* Low AFM */ + .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES, + .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH, + .num_rows = 0, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW, + }, + { /* Low APPS */ + .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES, + .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH, + .num_rows = L2_CTXT_TCAM_RX_NUM_ROWS, + .start_row = (L2_CTXT_TCAM_RX_NUM_ROWS / 2), + .end_row = L2_CTXT_TCAM_RX_NUM_ROWS - 1, + .max_entries = (L2_CTXT_TCAM_RX_MAX_ENTRIES / 2), + .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW, + }, + { /* AFM */ + .max_slices = PROF_TCAM_RX_MAX_SLICES, + .row_width = PROF_TCAM_RX_ROW_WIDTH, + .num_rows = 0, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = PROF_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P58_PROF_TCAM, + }, + { /* APPS */ + .max_slices = PROF_TCAM_RX_MAX_SLICES, + .row_width = PROF_TCAM_RX_ROW_WIDTH, + .num_rows = PROF_TCAM_RX_NUM_ROWS, + .start_row = 0, + .end_row = PROF_TCAM_RX_NUM_ROWS - 1, + .max_entries = PROF_TCAM_RX_MAX_ENTRIES, + .result_size = PROF_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P58_PROF_TCAM, + }, + { /* AFM */ + .max_slices = WC_TCAM_RX_MAX_SLICES, + .row_width = WC_TCAM_RX_ROW_WIDTH, + .num_rows = WC_TCAM_RX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = WC_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM, + }, + { /* APPS */ + .max_slices = WC_TCAM_RX_MAX_SLICES, + .row_width = WC_TCAM_RX_ROW_WIDTH, + .num_rows = WC_TCAM_RX_NUM_ROWS, + .start_row = 0, + .end_row = WC_TCAM_RX_NUM_ROWS - 1, + .max_entries = WC_TCAM_RX_MAX_ENTRIES, + .result_size = WC_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM, + }, + { /* AFM */ + .max_slices = SP_TCAM_RX_MAX_SLICES, + .row_width = SP_TCAM_RX_ROW_WIDTH, + .num_rows = 0, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = SP_TCAM_RX_RESULT_SIZE, + }, + { /* APPS */ + .max_slices = SP_TCAM_RX_MAX_SLICES, + .row_width = SP_TCAM_RX_ROW_WIDTH, + .num_rows = SP_TCAM_RX_NUM_ROWS, + .start_row = 0, + .end_row = SP_TCAM_RX_NUM_ROWS - 1, + .max_entries = SP_TCAM_RX_MAX_ENTRIES, + .result_size = SP_TCAM_RX_RESULT_SIZE, + }, + { /* AFM */ + .max_slices = CT_RULE_TCAM_RX_MAX_SLICES, + .row_width = CT_RULE_TCAM_RX_ROW_WIDTH, + .num_rows = CT_RULE_TCAM_RX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = CT_RULE_TCAM_RX_RESULT_SIZE, + }, + { /* APPS */ + .max_slices = CT_RULE_TCAM_RX_MAX_SLICES, + .row_width = CT_RULE_TCAM_RX_ROW_WIDTH, + .num_rows = CT_RULE_TCAM_RX_NUM_ROWS, + .start_row = 0, +#if CT_RULE_TCAM_RX_NUM_ROWS > 0 + .end_row = CT_RULE_TCAM_RX_NUM_ROWS - 1, +#else + .end_row = CT_RULE_TCAM_RX_NUM_ROWS, +#endif + .max_entries = CT_RULE_TCAM_RX_MAX_ENTRIES, + .result_size = CT_RULE_TCAM_RX_RESULT_SIZE, + }, + { /* AFM */ + .max_slices = VEB_TCAM_RX_MAX_SLICES, + .row_width = VEB_TCAM_RX_ROW_WIDTH, + .num_rows = VEB_TCAM_RX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = VEB_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P58_VEB_TCAM, + }, + { /* APPS */ + .max_slices = VEB_TCAM_RX_MAX_SLICES, + .row_width = VEB_TCAM_RX_ROW_WIDTH, + .num_rows = VEB_TCAM_RX_NUM_ROWS, + .start_row = 0, +#if VEB_TCAM_RX_NUM_ROWS > 0 + .end_row = VEB_TCAM_RX_NUM_ROWS - 1, +#else + .end_row = VEB_TCAM_RX_NUM_ROWS, +#endif + .max_entries = VEB_TCAM_RX_MAX_ENTRIES, + .result_size = VEB_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P58_VEB_TCAM, + }, + { /* AFM */ + .max_slices = WC_TCAM_RX_MAX_SLICES, + .row_width = WC_TCAM_RX_ROW_WIDTH, + .num_rows = WC_TCAM_RX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = WC_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM, + }, + { /* APPS */ + .max_slices = WC_TCAM_RX_MAX_SLICES, + .row_width = WC_TCAM_RX_ROW_WIDTH, + .num_rows = WC_TCAM_RX_NUM_ROWS, + .start_row = 0, + .end_row = WC_TCAM_RX_NUM_ROWS - 1, + .max_entries = WC_TCAM_RX_MAX_ENTRIES, + .result_size = WC_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM, + }, + { /* AFM */ + .max_slices = WC_TCAM_RX_MAX_SLICES, + .row_width = WC_TCAM_RX_ROW_WIDTH, + .num_rows = WC_TCAM_RX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = WC_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM, + }, + { /* APPS */ + .max_slices = WC_TCAM_RX_MAX_SLICES, + .row_width = WC_TCAM_RX_ROW_WIDTH, + .num_rows = WC_TCAM_RX_NUM_ROWS, + .start_row = 0, + .end_row = WC_TCAM_RX_NUM_ROWS - 1, + .max_entries = WC_TCAM_RX_MAX_ENTRIES, + .result_size = WC_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM, + }, + }, + { /* TX */ + { /* AFM */ + .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES, + .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH, + .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH, + }, + { /* APPS */ + .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES, + .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH, + .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = (L2_CTXT_TCAM_TX_NUM_ROWS / 2) - 1, + .max_entries = (L2_CTXT_TCAM_TX_MAX_ENTRIES / 2), + .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH, + }, + { /* AFM */ + .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES, + .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH, + .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW, + }, + { /* APPS */ + .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES, + .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH, + .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS, + .start_row = (L2_CTXT_TCAM_TX_NUM_ROWS / 2), + .end_row = L2_CTXT_TCAM_TX_NUM_ROWS - 1, + .max_entries = (L2_CTXT_TCAM_TX_MAX_ENTRIES / 2), + .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW, + }, + { /* AFM */ + .max_slices = PROF_TCAM_TX_MAX_SLICES, + .row_width = PROF_TCAM_TX_ROW_WIDTH, + .num_rows = PROF_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = PROF_TCAM_TX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P58_PROF_TCAM, + }, + { /* APPS */ + .max_slices = PROF_TCAM_TX_MAX_SLICES, + .row_width = PROF_TCAM_TX_ROW_WIDTH, + .num_rows = PROF_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = PROF_TCAM_TX_NUM_ROWS - 1, + .max_entries = PROF_TCAM_TX_MAX_ENTRIES, + .result_size = PROF_TCAM_TX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P58_PROF_TCAM, + }, + { /* AFM */ + .max_slices = WC_TCAM_TX_MAX_SLICES, + .row_width = WC_TCAM_TX_ROW_WIDTH, + .num_rows = WC_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = WC_TCAM_TX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM, + }, + { /* APPS */ + .max_slices = WC_TCAM_TX_MAX_SLICES, + .row_width = WC_TCAM_TX_ROW_WIDTH, + .num_rows = WC_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = WC_TCAM_TX_NUM_ROWS - 1, + .max_entries = WC_TCAM_TX_MAX_ENTRIES, + .result_size = WC_TCAM_TX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM, + }, + { /* AFM */ + .max_slices = SP_TCAM_TX_MAX_SLICES, + .row_width = SP_TCAM_TX_ROW_WIDTH, + .num_rows = SP_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = SP_TCAM_TX_RESULT_SIZE, + }, + { /* APPS */ + .max_slices = SP_TCAM_TX_MAX_SLICES, + .row_width = SP_TCAM_TX_ROW_WIDTH, + .num_rows = SP_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = SP_TCAM_TX_NUM_ROWS - 1, + .max_entries = SP_TCAM_TX_MAX_ENTRIES, + .result_size = SP_TCAM_TX_RESULT_SIZE, + }, + { /* AFM */ + .max_slices = CT_RULE_TCAM_TX_MAX_SLICES, + .row_width = CT_RULE_TCAM_TX_ROW_WIDTH, + .num_rows = CT_RULE_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = CT_RULE_TCAM_RX_RESULT_SIZE, + }, + { /* APPS */ + .max_slices = CT_RULE_TCAM_TX_MAX_SLICES, + .row_width = CT_RULE_TCAM_TX_ROW_WIDTH, + .num_rows = CT_RULE_TCAM_TX_NUM_ROWS, + .start_row = 0, +#if CT_RULE_TCAM_TX_NUM_ROWS > 0 + .end_row = CT_RULE_TCAM_TX_NUM_ROWS - 1, +#else + .end_row = CT_RULE_TCAM_TX_NUM_ROWS, +#endif + .max_entries = CT_RULE_TCAM_TX_MAX_ENTRIES, + .result_size = CT_RULE_TCAM_RX_RESULT_SIZE, + }, + { /* AFM */ + .max_slices = VEB_TCAM_TX_MAX_SLICES, + .row_width = VEB_TCAM_TX_ROW_WIDTH, + .num_rows = VEB_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = VEB_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P58_VEB_TCAM, + }, + { /* APPS */ + .max_slices = VEB_TCAM_TX_MAX_SLICES, + .row_width = VEB_TCAM_TX_ROW_WIDTH, + .num_rows = VEB_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = VEB_TCAM_TX_NUM_ROWS - 1, + .max_entries = VEB_TCAM_TX_MAX_ENTRIES, + .result_size = VEB_TCAM_RX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P58_VEB_TCAM, + }, + { /* AFM */ + .max_slices = WC_TCAM_TX_MAX_SLICES, + .row_width = WC_TCAM_TX_ROW_WIDTH, + .num_rows = WC_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = WC_TCAM_TX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM, + }, + { /* APPS */ + .max_slices = WC_TCAM_TX_MAX_SLICES, + .row_width = WC_TCAM_TX_ROW_WIDTH, + .num_rows = WC_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = WC_TCAM_TX_NUM_ROWS - 1, + .max_entries = WC_TCAM_TX_MAX_ENTRIES, + .result_size = WC_TCAM_TX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM, + }, + { /* AFM */ + .max_slices = WC_TCAM_TX_MAX_SLICES, + .row_width = WC_TCAM_TX_ROW_WIDTH, + .num_rows = WC_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = 0, + .max_entries = 0, + .result_size = WC_TCAM_TX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM, + }, + { /* APPS */ + .max_slices = WC_TCAM_TX_MAX_SLICES, + .row_width = WC_TCAM_TX_ROW_WIDTH, + .num_rows = WC_TCAM_TX_NUM_ROWS, + .start_row = 0, + .end_row = WC_TCAM_TX_NUM_ROWS - 1, + .max_entries = WC_TCAM_TX_MAX_ENTRIES, + .result_size = WC_TCAM_TX_RESULT_SIZE, + .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM, + }, + }, +}; + +static struct cfa_tcam_mgr_entry_data entry_data_p58[TF_TCAM_MAX_SESSIONS][TF_TCAM_MAX_ENTRIES]; + +static struct sbmp session_bmp_p58[TF_TCAM_MAX_SESSIONS][TF_TCAM_MAX_ENTRIES]; + +int +cfa_tcam_mgr_sess_table_get_p58(int sess_idx, struct sbmp **session_bmp) +{ + *session_bmp = session_bmp_p58[sess_idx]; + return 0; +} + +int +cfa_tcam_mgr_init_p58(int sess_idx, struct cfa_tcam_mgr_entry_data **global_entry_data) +{ + int max_row_width = 0; + int max_result_size = 0; + int dir, type; + + *global_entry_data = entry_data_p58[sess_idx]; + + memcpy(&cfa_tcam_mgr_tables[sess_idx], + &cfa_tcam_mgr_tables_p58, + sizeof(cfa_tcam_mgr_tables[sess_idx])); + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_PROF_TCAM_RX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_PROF_TCAM_RX[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_PROF_TCAM_TX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_PROF_TCAM_TX[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_WC_TCAM_RX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_WC_TCAM_RX[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_WC_TCAM_TX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_WC_TCAM_TX[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_SP_TCAM_RX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_SP_TCAM_RX[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_SP_TCAM_TX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_SP_TCAM_TX[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_RX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_RX[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_TX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_TX[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_VEB_TCAM_RX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_VEB_TCAM_RX[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_VEB_TCAM_TX[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_VEB_TCAM_TX[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_WC_TCAM_RX_HIGH[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_WC_TCAM_RX_HIGH[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_WC_TCAM_TX_HIGH[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_WC_TCAM_TX_HIGH[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_WC_TCAM_RX_LOW[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX] + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_WC_TCAM_RX_LOW[sess_idx]; + + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_AFM].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_WC_TCAM_TX_LOW[sess_idx]; + cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX] + [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS].tcam_rows = + (struct cfa_tcam_mgr_table_rows_0 *) + &cfa_tcam_mgr_table_rows_WC_TCAM_TX_LOW[sess_idx]; + + for (dir = 0; dir < TF_DIR_MAX; dir++) { + for (type = 0; type < CFA_TCAM_MGR_TBL_TYPE_MAX; type++) { + if (cfa_tcam_mgr_tables[sess_idx][dir][type].row_width > + max_row_width) + max_row_width = + cfa_tcam_mgr_tables[sess_idx][dir][type].row_width; + if (cfa_tcam_mgr_tables[sess_idx][dir][type].result_size > + max_result_size) + max_result_size = + cfa_tcam_mgr_tables[sess_idx][dir][type].result_size; + } + } + + if (max_row_width != MAX_ROW_WIDTH) { + CFA_TCAM_MGR_LOG(ERR, + "MAX_ROW_WIDTH (%d) does not match actual " + "value (%d).\n", + MAX_ROW_WIDTH, + max_row_width); + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + } + if (max_result_size != MAX_RESULT_SIZE) { + CFA_TCAM_MGR_LOG(ERR, + "MAX_RESULT_SIZE (%d) does not match actual " + "value (%d).\n", + MAX_RESULT_SIZE, + max_result_size); + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + } + return 0; +} + +/* HW OP declarations begin here */ + +struct cfa_tcam_mgr_TCAM_row_data { + int key_size; + int result_size; + uint8_t key[MAX_ROW_WIDTH]; + uint8_t mask[MAX_ROW_WIDTH]; + uint8_t result[MAX_RESULT_SIZE]; +}; + +/* These macros are only needed to avoid exceeding 80 columns */ +#define L2_CTXT_RX_MAX_ROWS \ + (L2_CTXT_TCAM_RX_MAX_SLICES * L2_CTXT_TCAM_RX_NUM_ROWS) +#define PROF_RX_MAX_ROWS (PROF_TCAM_RX_MAX_SLICES * PROF_TCAM_RX_NUM_ROWS) +#define WC_RX_MAX_ROWS (WC_TCAM_RX_MAX_SLICES * WC_TCAM_RX_NUM_ROWS) +#define SP_RX_MAX_ROWS (SP_TCAM_RX_MAX_SLICES * SP_TCAM_RX_NUM_ROWS) +#define CT_RULE_RX_MAX_ROWS \ + (CT_RULE_TCAM_RX_MAX_SLICES * CT_RULE_TCAM_RX_NUM_ROWS) +#define VEB_RX_MAX_ROWS (VEB_TCAM_RX_MAX_SLICES * VEB_TCAM_RX_NUM_ROWS) + +#define L2_CTXT_TX_MAX_ROWS \ + (L2_CTXT_TCAM_TX_MAX_SLICES * L2_CTXT_TCAM_TX_NUM_ROWS) +#define PROF_TX_MAX_ROWS (PROF_TCAM_TX_MAX_SLICES * PROF_TCAM_TX_NUM_ROWS) +#define WC_TX_MAX_ROWS (WC_TCAM_TX_MAX_SLICES * WC_TCAM_TX_NUM_ROWS) +#define SP_TX_MAX_ROWS (SP_TCAM_TX_MAX_SLICES * SP_TCAM_TX_NUM_ROWS) +#define CT_RULE_TX_MAX_ROWS \ + (CT_RULE_TCAM_TX_MAX_SLICES * CT_RULE_TCAM_TX_NUM_ROWS) +#define VEB_TX_MAX_ROWS (VEB_TCAM_TX_MAX_SLICES * VEB_TCAM_TX_NUM_ROWS) + +static int cfa_tcam_mgr_max_rows[TF_TCAM_TBL_TYPE_MAX] = { + L2_CTXT_RX_MAX_ROWS, + L2_CTXT_RX_MAX_ROWS, + PROF_RX_MAX_ROWS, + WC_RX_MAX_ROWS, + SP_RX_MAX_ROWS, + CT_RULE_RX_MAX_ROWS, + VEB_RX_MAX_ROWS, + WC_RX_MAX_ROWS, + WC_RX_MAX_ROWS +}; + +static struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][L2_CTXT_RX_MAX_ROWS]; +static struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_PROF_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][PROF_RX_MAX_ROWS]; +static struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_WC_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][WC_RX_MAX_ROWS]; +static struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_SP_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][SP_RX_MAX_ROWS]; +static struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_CT_RULE_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][CT_RULE_RX_MAX_ROWS]; +static struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_VEB_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][VEB_RX_MAX_ROWS]; +static struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_WC_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][WC_RX_MAX_ROWS]; + +static struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][L2_CTXT_TX_MAX_ROWS]; +static struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_PROF_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][PROF_TX_MAX_ROWS]; +static struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_WC_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][WC_TX_MAX_ROWS]; +static struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_SP_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][SP_TX_MAX_ROWS]; +static struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_CT_RULE_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][CT_RULE_TX_MAX_ROWS]; +static struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_VEB_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][VEB_TX_MAX_ROWS]; +static struct cfa_tcam_mgr_TCAM_row_data + cfa_tcam_mgr_WC_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][WC_TX_MAX_ROWS]; + +static struct cfa_tcam_mgr_TCAM_row_data * +row_tables[TF_DIR_MAX][TF_TCAM_TBL_TYPE_MAX] = { + { + cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[0], + cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[0], + cfa_tcam_mgr_PROF_TCAM_RX_row_data[0], + cfa_tcam_mgr_WC_TCAM_RX_row_data[0], + cfa_tcam_mgr_SP_TCAM_RX_row_data[0], + cfa_tcam_mgr_CT_RULE_TCAM_RX_row_data[0], + cfa_tcam_mgr_VEB_TCAM_RX_row_data[0], + cfa_tcam_mgr_WC_TCAM_RX_row_data[0], + cfa_tcam_mgr_WC_TCAM_RX_row_data[0], + }, + { + cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[0], + cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[0], + cfa_tcam_mgr_PROF_TCAM_TX_row_data[0], + cfa_tcam_mgr_WC_TCAM_TX_row_data[0], + cfa_tcam_mgr_SP_TCAM_TX_row_data[0], + cfa_tcam_mgr_CT_RULE_TCAM_TX_row_data[0], + cfa_tcam_mgr_VEB_TCAM_TX_row_data[0], + cfa_tcam_mgr_WC_TCAM_TX_row_data[0], + cfa_tcam_mgr_WC_TCAM_TX_row_data[0], + } +}; + +static int cfa_tcam_mgr_get_max_rows(enum tf_tcam_tbl_type type) +{ + if (type >= TF_TCAM_TBL_TYPE_MAX) + assert(0); + else + return cfa_tcam_mgr_max_rows[type]; +} + +static int cfa_tcam_mgr_hwop_set(int sess_idx, + struct cfa_tcam_mgr_set_parms *parms, int row, + int slice, int max_slices) +{ + struct cfa_tcam_mgr_TCAM_row_data *this_table; + struct cfa_tcam_mgr_TCAM_row_data *this_row; + this_table = row_tables[parms->dir] + [cfa_tcam_mgr_get_phys_table_type(parms->type)]; + this_table += (sess_idx * + cfa_tcam_mgr_get_max_rows(cfa_tcam_mgr_get_phys_table_type(parms->type))); + this_row = &this_table[row * max_slices + slice]; + this_row->key_size = parms->key_size; + memcpy(&this_row->key, parms->key, parms->key_size); + memcpy(&this_row->mask, parms->mask, parms->key_size); + this_row->result_size = parms->result_size; + if (parms->result != ((void *)0)) + memcpy(&this_row->result, parms->result, parms->result_size); + return 0; +}; + +static int cfa_tcam_mgr_hwop_get(int sess_idx, + struct cfa_tcam_mgr_get_parms *parms, int row, + int slice, int max_slices) +{ + struct cfa_tcam_mgr_TCAM_row_data *this_table; + struct cfa_tcam_mgr_TCAM_row_data *this_row; + this_table = row_tables[parms->dir] + [cfa_tcam_mgr_get_phys_table_type(parms->type)]; + this_table += (sess_idx * + cfa_tcam_mgr_get_max_rows(cfa_tcam_mgr_get_phys_table_type(parms->type))); + this_row = &this_table[row * max_slices + slice]; + parms->key_size = this_row->key_size; + parms->result_size = this_row->result_size; + if (parms->key != ((void *)0)) + memcpy(parms->key, &this_row->key, parms->key_size); + if (parms->mask != ((void *)0)) + memcpy(parms->mask, &this_row->mask, parms->key_size); + if (parms->result != ((void *)0)) + memcpy(parms->result, &this_row->result, parms->result_size); + return 0; +}; + +static int cfa_tcam_mgr_hwop_free(int sess_idx, + struct cfa_tcam_mgr_free_parms *parms, + int row, int slice, int max_slices) +{ + struct cfa_tcam_mgr_TCAM_row_data *this_table; + struct cfa_tcam_mgr_TCAM_row_data *this_row; + this_table = row_tables[parms->dir] + [cfa_tcam_mgr_get_phys_table_type(parms->type)]; + this_table += (sess_idx * + cfa_tcam_mgr_get_max_rows(cfa_tcam_mgr_get_phys_table_type(parms->type))); + this_row = &this_table[row * max_slices + slice]; + memset(&this_row->key, 0, sizeof(this_row->key)); + memset(&this_row->mask, 0, sizeof(this_row->mask)); + memset(&this_row->result, 0, sizeof(this_row->result)); + this_row->key_size = 0; + this_row->result_size = 0; + return 0; +}; + +int cfa_tcam_mgr_hwops_get_funcs_p58(struct cfa_tcam_mgr_hwops_funcs + *hwop_funcs) +{ + hwop_funcs->set = cfa_tcam_mgr_hwop_set; + hwop_funcs->get = cfa_tcam_mgr_hwop_get; + hwop_funcs->free = cfa_tcam_mgr_hwop_free; + return 0; +} diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.h new file mode 100644 index 0000000000..7640f91911 --- /dev/null +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2021-2023 Broadcom + * All rights reserved. + */ + +#ifndef CFA_TCAM_MGR_P58_H +#define CFA_TCAM_MGR_P58_H + +#include "cfa_tcam_mgr_device.h" +#include "cfa_tcam_mgr_sbmp.h" + +int +cfa_tcam_mgr_init_p58(int sess_idx, struct cfa_tcam_mgr_entry_data **global_entry_data); + +int +cfa_tcam_mgr_sess_table_get_p58(int sess_idx, struct sbmp **session_bmp); + +int +cfa_tcam_mgr_hwops_get_funcs_p58(struct cfa_tcam_mgr_hwops_funcs *hwop_funcs); +#endif /* CFA_TCAM_MGR_P58_H */ diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_sbmp.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_sbmp.h new file mode 100644 index 0000000000..6ad158abe8 --- /dev/null +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_sbmp.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2021-2023 Broadcom + * All rights reserved. + */ + +#ifndef CFA_TCAM_MGR_SBMP_H +#define CFA_TCAM_MGR_SBMP_H + +#include + +#include "cfa_tcam_mgr.h" + +#define SBMP_SESSION_MAX TF_TCAM_MAX_SESSIONS +#if SBMP_SESSION_MAX <= 16 +#define SBMP_WORD_WIDTH 16 +#else +#define SBMP_WORD_WIDTH 32 +#endif + +#define SBMP_WIDTH (((SBMP_SESSION_MAX + SBMP_WORD_WIDTH - 1) / \ + SBMP_WORD_WIDTH) * SBMP_WORD_WIDTH) +#define SBMP_WORD_MAX ((SBMP_WIDTH + SBMP_WORD_WIDTH - 1) / SBMP_WORD_WIDTH) + +struct sbmp { +#if SBMP_WORD_WIDTH == 16 + uint16_t bits[SBMP_WORD_MAX]; +#elif SBMP_WORD_WIDTH == 32 + uint32_t bits[SBMP_WORD_MAX]; +#else + uint64_t bits[SBMP_WORD_MAX]; +#endif +}; + +#define SBMP_WORD_GET(bm, word) ((bm).bits[(word)]) + +#if SBMP_WORD_MAX == 1 +#define SBMP_WENT(session) (0) +#define SBMP_WBIT(session) (1U << (session)) +#define SBMP_CLEAR(bm) (SBMP_WORD_GET(bm, 0) = 0) +#define SBMP_IS_NULL(bm) (SBMP_WORD_GET(bm, 0) == 0) +#define SBMP_COUNT(bm, count) \ + (count = __builtin_popcount(SBMP_WORD_GET(bm, 0))) +#elif SBMP_WORD_MAX == 2 +#define SBMP_WENT(session) ((session) / SBMP_WORD_WIDTH) +#define SBMP_WBIT(session) (1U << ((session) % SBMP_WORD_WIDTH)) +#define SBMP_CLEAR(bm) \ + do { \ + typeof(bm) *_bm = &(bm); \ + SBMP_WORD_GET(*_bm, 0) = SBMP_WORD_GET(*_bm, 1) = 0; \ + } while (0) +#define SBMP_IS_NULL(bm) \ + (SBMP_WORD_GET(bm, 0) == 0 && SBMP_WORD_GET(bm, 1) == 0) +#define SBMP_COUNT(bm, count) \ + do { \ + typeof(bm) *_bm = &(bm); \ + count = __builtin_popcount(SBMP_WORD_GET(*_bm, 0)) + \ + __builtin_popcount(SBMP_WORD_GET(*_bm, 1))); \ + } while (0) +#elif SBMP_WORD_MAX == 3 +#define SBMP_WENT(session) ((session) / SBMP_WORD_WIDTH) +#define SBMP_WBIT(session) (1U << ((session) % SBMP_WORD_WIDTH)) +#define SBMP_CLEAR(bm) \ + do { \ + typeof(bm) *_bm = &(bm); \ + SBMP_WORD_GET(*_bm, 0) = SBMP_WORD_GET(*_bm, 1) = \ + SBMP_WORD_GET(*_bm, 2) = 0; \ + } while (0) +#define SBMP_IS_NULL(bm) \ + (SBMP_WORD_GET(bm, 0) == 0 && SBMP_WORD_GET(bm, 1) == 0 && \ + SBMP_WORD_GET(bm, 2) == 0) +#define SBMP_COUNT(bm, count) \ + do { \ + typeof(bm) *_bm = &(bm); \ + count = __builtin_popcount(SBMP_WORD_GET(*_bm, 0)) + \ + __builtin_popcount(SBMP_WORD_GET(*_bm, 1)) + \ + __builtin_popcount(SBMP_WORD_GET(*_bm, 2)); \ + } while (0) +#else /* SBMP_WORD_MAX > 3 */ +#define SBMP_WENT(session) ((session) / SBMP_WORD_WIDTH) +#define SBMP_WBIT(session) (1U << ((session) % SBMP_WORD_WIDTH)) +#define SBMP_CLEAR(bm) \ + do { \ + typeof(bm) *_bm = &(bm); \ + int _w; \ + for (_w = 0; _w < SBMP_WORD_MAX; _w++) { \ + SBMP_WORD_GET(*_bm, _w) = 0; \ + } \ + } while (0) +#define SBMP_IS_NULL(bm) (sbmp_bmnull(&(bm))) +#define SBMP_COUNT(bm, count) \ + do { \ + typeof(bm) *_bm = &(bm); \ + int _count, _w; \ + _count = 0; \ + for (_w = 0; _w < SBMP_WORD_MAX; _w++) { \ + _count += __builtin_popcount(SBMP_WORD_GET(*_bm, _w)); \ + } \ + count = _count; \ + } while (0) + +/* Only needed if SBMP_WORD_MAX > 3 */ +static int +sbmp_bmnull(struct ebmp *bmp) +{ + int i; + + for (i = 0; i < SBMP_WORD_MAX; i++) { + if (SBMP_WORD_GET(*bmp, i) != 0) + return 0; + } + return 1; +} +#endif + +/* generics that use the previously defined helpers */ +#define SBMP_NOT_NULL(bm) (!SBMP_IS_NULL(bm)) + +#define SBMP_ENTRY(bm, session) \ + (SBMP_WORD_GET(bm, SBMP_WENT(session))) +#define SBMP_MEMBER(bm, session) \ + ((SBMP_ENTRY(bm, session) & SBMP_WBIT(session)) != 0) +#define SBMP_SESSION_ADD(bm, session) \ + (SBMP_ENTRY(bm, session) |= SBMP_WBIT(session)) +#define SBMP_SESSION_REMOVE(bm, session) \ + (SBMP_ENTRY(bm, session) &= ~SBMP_WBIT(session)) +#endif /* CFA_TCAM_MGR_SBMP_H */ diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.c b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.c new file mode 100644 index 0000000000..3d085bc69e --- /dev/null +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.c @@ -0,0 +1,377 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2021-2023 Broadcom + * All rights reserved. + */ + +#include +#include "hcapi_cfa_defs.h" +#include "tf_util.h" +#include "cfa_tcam_mgr.h" +#include "cfa_tcam_mgr_device.h" +#include "cfa_tcam_mgr_session.h" +#include "cfa_tcam_mgr_sbmp.h" +#include "tfp.h" +#include "cfa_tcam_mgr_p58.h" +#include "cfa_tcam_mgr_p4.h" + +struct cfa_tcam_mgr_session_data { + uint32_t session_id; + /* The following are per-session values */ + uint16_t max_entries[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX]; + uint16_t used_entries[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX]; +}; + +static struct cfa_tcam_mgr_session_data session_data[TF_TCAM_MAX_SESSIONS]; + +static uint16_t last_entry_id; + +static struct sbmp *session_bmp[TF_TCAM_MAX_SESSIONS]; + +int +cfa_tcam_mgr_session_init(int sess_idx, enum cfa_tcam_mgr_device_type type) +{ + int rc; + + switch (type) { + case CFA_TCAM_MGR_DEVICE_TYPE_P4: + case CFA_TCAM_MGR_DEVICE_TYPE_SR: + rc = cfa_tcam_mgr_sess_table_get_p4(sess_idx, &session_bmp[sess_idx]); + break; + case CFA_TCAM_MGR_DEVICE_TYPE_P5: + rc = cfa_tcam_mgr_sess_table_get_p58(sess_idx, &session_bmp[sess_idx]); + break; + default: + CFA_TCAM_MGR_LOG(ERR, "No such device %d\n", type); + rc = -CFA_TCAM_MGR_ERR_CODE(NODEV); + } + + return rc; +} + +int +cfa_tcam_mgr_get_session_from_context(struct cfa_tcam_mgr_context *context, + uint32_t *session_id) +{ + if (context == NULL) { + CFA_TCAM_MGR_LOG_0(ERR, "context passed as NULL pointer.\n"); + return -CFA_TCAM_MGR_ERR_CODE(INVAL); + } + + *session_id = context->tfp->session->session_id.id; + return 0; +} + +int +cfa_tcam_mgr_session_find(unsigned int session_id) +{ + unsigned int sess_idx; + + for (sess_idx = 0; sess_idx < ARRAY_SIZE(session_data); sess_idx++) { + if (session_data[sess_idx].session_id == session_id) + return sess_idx; + } + + return -CFA_TCAM_MGR_ERR_CODE(INVAL); +} + +int +cfa_tcam_mgr_session_add(unsigned int session_id) +{ + int sess_idx; + + sess_idx = cfa_tcam_mgr_session_find(session_id); + if (sess_idx >= 0) { + CFA_TCAM_MGR_LOG_0(ERR, "Session is already bound.\n"); + return -CFA_TCAM_MGR_ERR_CODE(BUSY); + } + + /* Session not found in table, find first empty entry. */ + for (sess_idx = 0; + sess_idx < (signed int)ARRAY_SIZE(session_data); + sess_idx++) { + if (session_data[sess_idx].session_id == 0) + break; + } + + if (sess_idx >= (signed int)ARRAY_SIZE(session_data)) { + /* No room in the session table */ + CFA_TCAM_MGR_LOG_0(ERR, "Session table is full.\n"); + return -CFA_TCAM_MGR_ERR_CODE(NOMEM); + } + + session_data[sess_idx].session_id = session_id; + + return sess_idx; +} + +int +cfa_tcam_mgr_session_free(unsigned int session_id, + struct cfa_tcam_mgr_context *context) +{ + struct cfa_tcam_mgr_free_parms free_parms; + int entry_id; + int sess_idx = cfa_tcam_mgr_session_find(session_id); + + if (sess_idx < 0) + return sess_idx; + + memset(&free_parms, 0, sizeof(free_parms)); + /* Since we are freeing all pending TCAM entries (which is typically + * done during tcam_unbind), we don't know the type of each entry. + * So we set the type to MAX as a hint to cfa_tcam_mgr_free() to + * figure out the actual type. We need to set it through each + * iteration in the loop below; otherwise, the type determined for + * the first entry would be used for subsequent entries that may or + * may not be of the same type, resulting in errors. + */ + for (entry_id = 0; entry_id < cfa_tcam_mgr_max_entries[sess_idx]; entry_id++) { + if (SBMP_MEMBER(session_bmp[sess_idx][entry_id], sess_idx)) { + SBMP_SESSION_REMOVE(session_bmp[sess_idx][entry_id], sess_idx); + + free_parms.id = entry_id; + free_parms.type = CFA_TCAM_MGR_TBL_TYPE_MAX; + cfa_tcam_mgr_free(context, &free_parms); + } + } + + memset(&session_data[sess_idx], 0, sizeof(session_data[sess_idx])); + return 0; +} + +int +cfa_tcam_mgr_session_cfg(unsigned int session_id, + uint16_t tcam_cnt[][CFA_TCAM_MGR_TBL_TYPE_MAX]) +{ + struct cfa_tcam_mgr_table_data *table_data; + struct cfa_tcam_mgr_session_data *session_entry; + unsigned int dir, type; + int sess_idx = cfa_tcam_mgr_session_find(session_id); + uint16_t requested_cnt; + + if (sess_idx < 0) + return sess_idx; + + session_entry = &session_data[sess_idx]; + + /* Validate session request */ + for (dir = 0; dir < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx]); dir++) { + for (type = 0; + type < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx][dir]); + type++) { + table_data = &cfa_tcam_mgr_tables[sess_idx][dir][type]; + requested_cnt = tcam_cnt[dir][type]; + /* + * Only check if table supported (max_entries > 0). + */ + if (table_data->max_entries > 0 && + requested_cnt > table_data->max_entries) { + CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, dir, type, + "Requested %d, available %d.\n", + requested_cnt, + table_data->max_entries); + return -CFA_TCAM_MGR_ERR_CODE(NOSPC); + } + } + } + + memcpy(session_entry->max_entries, tcam_cnt, + sizeof(session_entry->max_entries)); + return 0; +} + +void +cfa_tcam_mgr_mv_session_used_entries_cnt(int sess_idx, enum tf_dir dir, + enum cfa_tcam_mgr_tbl_type dst_type, + enum cfa_tcam_mgr_tbl_type src_type) +{ + session_data[sess_idx].used_entries[dir][dst_type]++; + session_data[sess_idx].used_entries[dir][src_type]--; +} + +int +cfa_tcam_mgr_session_entry_alloc(unsigned int session_id, + enum tf_dir dir, + enum cfa_tcam_mgr_tbl_type type) +{ + int sess_idx; + + sess_idx = cfa_tcam_mgr_session_find(session_id); + if (sess_idx < 0) { + CFA_TCAM_MGR_LOG_0(ERR, "Session not found.\n"); + return -CFA_TCAM_MGR_ERR_CODE(NODEV); + } + + if (session_data[sess_idx].used_entries[dir][type] >= + session_data[sess_idx].max_entries[dir][type]) { + CFA_TCAM_MGR_LOG_0(ERR, "Table full (session).\n"); + return -CFA_TCAM_MGR_ERR_CODE(NOSPC); + } + + do { + last_entry_id++; + if (cfa_tcam_mgr_max_entries[sess_idx] <= last_entry_id) + last_entry_id = 0; + } while (!SBMP_IS_NULL(session_bmp[sess_idx][last_entry_id])); + + SBMP_SESSION_ADD(session_bmp[sess_idx][last_entry_id], sess_idx); + + session_data[sess_idx].used_entries[dir][type] += 1; + + return last_entry_id; +} + +int +cfa_tcam_mgr_session_entry_free(unsigned int session_id, + unsigned int entry_id, + enum tf_dir dir, + enum cfa_tcam_mgr_tbl_type type) +{ + int sess_idx; + + sess_idx = cfa_tcam_mgr_session_find(session_id); + if (sess_idx < 0) { + CFA_TCAM_MGR_LOG_0(ERR, "Session not found.\n"); + return -CFA_TCAM_MGR_ERR_CODE(NODEV); + } + + SBMP_SESSION_REMOVE(session_bmp[sess_idx][entry_id], sess_idx); + session_data[sess_idx].used_entries[dir][type] -= 1; + + return 0; +} + +#if SBMP_WORD_WIDTH == 16 +#define SBMP_FORMAT PRIX16 +#define SBMP_PRECISION "4" +#elif SBMP_WORD_WIDTH == 32 +#define SBMP_FORMAT PRIX32 +#define SBMP_PRECISION "8" +#elif SBMP_WORD_WIDTH == 64 +#define SBMP_FORMAT PRIX64 +#define SBMP_PRECISION "16" +#else +#error "Invalid value for SBMP_WORD_WIDTH." +#endif + +static void +cfa_tcam_mgr_session_bitmap_print(struct sbmp *session_bmp) +{ + unsigned int i; + + printf("0x"); + for (i = 0; + i < ARRAY_SIZE(session_bmp->bits); + i++) { + printf("%0" SBMP_PRECISION SBMP_FORMAT, + session_bmp->bits[i]); + } +} + +#define SESSION_DUMP_HEADER_1 " RX TX\n" +#define SESSION_DUMP_HEADER_2 \ + " Max Used Max Used\n" + +static void +cfa_tcam_mgr_session_printf(struct cfa_tcam_mgr_session_data *session, + enum cfa_tcam_mgr_tbl_type tbl_type) +{ + printf("%-22s: %5u %5u %5u %5u\n", + cfa_tcam_mgr_tbl_2_str(tbl_type), + session->max_entries[TF_DIR_RX][tbl_type], + session->used_entries[TF_DIR_RX][tbl_type], + session->max_entries[TF_DIR_TX][tbl_type], + session->used_entries[TF_DIR_TX][tbl_type]); +} + +void +cfa_tcam_mgr_sessions_dump(void) +{ + struct cfa_tcam_mgr_session_data *session; + unsigned int sess_idx; + bool sess_found = false; + enum cfa_tcam_mgr_tbl_type tbl_type; + + printf("\nTCAM Sessions Table:\n"); + for (sess_idx = 0; sess_idx < ARRAY_SIZE(session_data); sess_idx++) { + if (session_data[sess_idx].session_id != 0) { + session = &session_data[sess_idx]; + if (!sess_found) { + printf(SESSION_DUMP_HEADER_1); + printf(SESSION_DUMP_HEADER_2); + } + printf("Session 0x%08x:\n", + session->session_id); + for (tbl_type = CFA_TCAM_MGR_TBL_TYPE_START; + tbl_type < CFA_TCAM_MGR_TBL_TYPE_MAX; + tbl_type++) { + cfa_tcam_mgr_session_printf(session, tbl_type); + } + sess_found = true; + } + } + + if (!sess_found) + printf("No sessions found.\n"); +} + +/* This dumps all the sessions using an entry */ +void +cfa_tcam_mgr_entry_sessions_dump(int sess_idx, uint16_t id) +{ + bool session_found = false; + + if (id >= cfa_tcam_mgr_max_entries[sess_idx]) { + printf("Entry ID %u out of range for sess_idx %d. Max ID %u.\n", + id, sess_idx, cfa_tcam_mgr_max_entries[sess_idx] - 1); + return; + } + + if (!SBMP_IS_NULL(session_bmp[sess_idx][id])) { + printf("Sessions using entry ID %u:\n", id); + for (sess_idx = 0; sess_idx < SBMP_SESSION_MAX; sess_idx++) + if (SBMP_MEMBER(session_bmp[sess_idx][id], (sess_idx))) { + if (session_data[sess_idx].session_id != 0) { + printf("0x%08x (index %d)\n", + session_data[sess_idx].session_id, + sess_idx); + session_found = true; + } else { + printf("Error! Entry ID %u used by " + "session index %d which is not " + "in use.\n", + id, sess_idx); + } + } + if (!session_found) + printf("No sessions using entry ID %u.\n", id); + } else { + printf("Entry ID %u not in use.\n", + id); + return; + } +} + +/* This dumps all the entries in use by any session */ +void +cfa_tcam_mgr_session_entries_dump(int sess_idx) +{ + bool entry_found = false; + uint16_t id; + + printf("\nGlobal Maximum Entries for sess_idx %d: %d\n\n", + sess_idx, cfa_tcam_mgr_max_entries[sess_idx]); + printf("TCAM Session Entry Table:\n"); + for (id = 0; id < cfa_tcam_mgr_max_entries[sess_idx]; id++) { + if (!SBMP_IS_NULL(session_bmp[sess_idx][id])) { + if (!entry_found) + printf(" EID Session bitmap\n"); + printf("%5u ", id); + cfa_tcam_mgr_session_bitmap_print(&session_bmp[sess_idx][id]); + printf("\n"); + entry_found = true; + } + } + + if (!entry_found) + printf("No entries found.\n"); +} diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.h new file mode 100644 index 0000000000..69311b7e1d --- /dev/null +++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019-2023 Broadcom + * All rights reserved. + */ + +#ifndef CFA_TCAM_MGR_SESSION_H +#define CFA_TCAM_MGR_SESSION_H + +#include +#include "cfa_tcam_mgr.h" + +int +cfa_tcam_mgr_session_init(int sess_idx, enum cfa_tcam_mgr_device_type type); + +int +cfa_tcam_mgr_get_session_from_context(struct cfa_tcam_mgr_context *context, + uint32_t *session_id); + +int +cfa_tcam_mgr_session_find(unsigned int session_id); + +int +cfa_tcam_mgr_session_add(unsigned int session_id); + +int +cfa_tcam_mgr_session_free(unsigned int session_id, + struct cfa_tcam_mgr_context *context); + +int +cfa_tcam_mgr_session_cfg(unsigned int session_id, + uint16_t tcam_cnt[][CFA_TCAM_MGR_TBL_TYPE_MAX]); + +int +cfa_tcam_mgr_session_entry_alloc(unsigned int session_id, + enum tf_dir dir, + enum cfa_tcam_mgr_tbl_type type); +int +cfa_tcam_mgr_session_entry_free(unsigned int session_id, + unsigned int entry_id, + enum tf_dir dir, + enum cfa_tcam_mgr_tbl_type type); + +void +cfa_tcam_mgr_sessions_dump(void); +void +cfa_tcam_mgr_entry_sessions_dump(int sess_idx, uint16_t id); +void +cfa_tcam_mgr_session_entries_dump(int sess_idx); + +void +cfa_tcam_mgr_mv_session_used_entries_cnt(int sess_idx, enum tf_dir dir, + enum cfa_tcam_mgr_tbl_type dst_type, + enum cfa_tcam_mgr_tbl_type src_type); +#endif /* CFA_TCAM_MGR_SESSION_H */ diff --git a/drivers/net/bnxt/tf_core/meson.build b/drivers/net/bnxt/tf_core/meson.build index f812e471d1..ae44aa34cf 100644 --- a/drivers/net/bnxt/tf_core/meson.build +++ b/drivers/net/bnxt/tf_core/meson.build @@ -1,36 +1,42 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2018 Intel Corporation -# Copyright(c) 2021 Broadcom +# Copyright(c) 2023 Broadcom #Include the folder for headers includes += include_directories('.') #Add the source files sources += files( - 'tf_core.c', 'bitalloc.c', - 'tf_msg.c', - 'll.c', + 'cfa_tcam_mgr.c', + 'cfa_tcam_mgr_hwop_msg.c', + 'cfa_tcam_mgr_p4.c', + 'cfa_tcam_mgr_p58.c', + 'cfa_tcam_mgr_session.c', 'dpool.c', + 'll.c', 'rand.c', 'stack.c', - 'tf_rm.c', - 'tf_tbl.c', - 'tf_tbl_sram.c', - 'tf_sram_mgr.c', + 'tf_core.c', + 'tf_device.c', + 'tf_device_p4.c', + 'tf_device_p58.c', 'tf_em_common.c', + 'tf_em_hash_internal.c', 'tf_em_host.c', 'tf_em_internal.c', - 'tf_em_hash_internal.c', - 'tfp.c', - 'tf_util.c', - 'tf_device.c', - 'tf_device_p4.c', 'tf_global_cfg.c', + 'tf_hash.c', 'tf_identifier.c', 'tf_if_tbl.c', + 'tf_msg.c', + 'tfp.c', + 'tf_rm.c', 'tf_session.c', + 'tf_sram_mgr.c', + 'tf_tbl.c', + 'tf_tbl_sram.c', 'tf_tcam.c', + 'tf_tcam_mgr_msg.c', 'tf_tcam_shared.c', - 'tf_hash.c', - 'tf_device_p58.c') + 'tf_util.c') diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index 038e439101..3a812bee3a 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -34,8 +34,8 @@ tf_open_session(struct tf *tfp, * side. It is assumed that the Firmware will be supported if * firmware open session succeeds. */ - if (parms->device_type != TF_DEVICE_TYPE_WH && - parms->device_type != TF_DEVICE_TYPE_THOR && + if (parms->device_type != TF_DEVICE_TYPE_P4 && + parms->device_type != TF_DEVICE_TYPE_P5 && parms->device_type != TF_DEVICE_TYPE_SR) { TFP_DRV_LOG(ERR, "Unsupported device type %d\n", @@ -83,7 +83,7 @@ tf_open_session(struct tf *tfp, return rc; TFP_DRV_LOG(INFO, - "domain:%d, bus:%d, device:%u\n", + "domain:%x, bus:%x, device:%u\n", parms->session_id.internal.domain, parms->session_id.internal.bus, parms->session_id.internal.device); @@ -176,7 +176,7 @@ tf_close_session(struct tf *tfp) return rc; TFP_DRV_LOG(INFO, - "domain:%d, bus:%d, device:%d\n", + "domain:%d, bus:%x, device:%d\n", cparms.session_id->internal.domain, cparms.session_id->internal.bus, cparms.session_id->internal.device); @@ -742,7 +742,6 @@ tf_set_tcam_entry(struct tf *tfp, memset(&sparms, 0, sizeof(struct tf_tcam_set_parms)); - /* Retrieve the session information */ rc = tf_session_get_session(tfp, &tfs); if (rc) { @@ -790,6 +789,10 @@ tf_set_tcam_entry(struct tf *tfp, strerror(-rc)); return rc; } + TFP_DRV_LOG(DEBUG, + "%s: TCAM type %d set idx:%d key size %d result size %d\n", + tf_dir_2_str(parms->dir), sparms.type, + sparms.idx, sparms.key_size, sparms.result_size); return 0; } @@ -807,7 +810,6 @@ tf_get_tcam_entry(struct tf *tfp __rte_unused, memset(&gparms, 0, sizeof(struct tf_tcam_get_parms)); - /* Retrieve the session information */ rc = tf_session_get_session(tfp, &tfs); if (rc) { @@ -1812,8 +1814,8 @@ int tf_get_version(struct tf *tfp, /* This function can be called before open session, filter * out any non-supported device types on the Core side. */ - if (parms->device_type != TF_DEVICE_TYPE_WH && - parms->device_type != TF_DEVICE_TYPE_THOR && + if (parms->device_type != TF_DEVICE_TYPE_P4 && + parms->device_type != TF_DEVICE_TYPE_P5 && parms->device_type != TF_DEVICE_TYPE_SR) { TFP_DRV_LOG(ERR, "Unsupported device type %d\n", @@ -1845,7 +1847,7 @@ int tf_query_sram_resources(struct tf *tfp, /* This function can be called before open session, filter * out any non-supported device types on the Core side. */ - if (parms->device_type != TF_DEVICE_TYPE_THOR) { + if (parms->device_type != TF_DEVICE_TYPE_P5) { TFP_DRV_LOG(ERR, "Unsupported device type %d\n", parms->device_type); @@ -1927,7 +1929,7 @@ int tf_set_sram_policy(struct tf *tfp, /* This function can be called before open session, filter * out any non-supported device types on the Core side. */ - if (parms->device_type != TF_DEVICE_TYPE_THOR) { + if (parms->device_type != TF_DEVICE_TYPE_P5) { TFP_DRV_LOG(ERR, "Unsupported device type %d\n", parms->device_type); @@ -1968,7 +1970,7 @@ int tf_get_sram_policy(struct tf *tfp, /* This function can be called before open session, filter * out any non-supported device types on the Core side. */ - if (parms->device_type != TF_DEVICE_TYPE_THOR) { + if (parms->device_type != TF_DEVICE_TYPE_P5) { TFP_DRV_LOG(ERR, "Unsupported device type %d\n", parms->device_type); @@ -1997,3 +1999,31 @@ int tf_get_sram_policy(struct tf *tfp, return rc; } + +int tf_set_session_hotup_state(struct tf *tfp, + struct tf_set_session_hotup_state_parms *parms) +{ + int rc = 0; + + TF_CHECK_PARMS1(tfp); + + rc = tf_session_set_hotup_state(tfp, parms); + if (rc) + return rc; + + return rc; +} + +int tf_get_session_hotup_state(struct tf *tfp, + struct tf_get_session_hotup_state_parms *parms) +{ + int rc = 0; + + TF_CHECK_PARMS1(tfp); + + rc = tf_session_get_hotup_state(tfp, parms); + if (rc) + return rc; + + return rc; +} diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index f5fe0a9098..3da1d2a5ca 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -112,6 +112,10 @@ enum tf_sram_bank_id { * @ref tf_attach_session * * @ref tf_close_session + * + * @ref tf_get_session_info + * + * @ref tf_get_session_info */ /** @@ -188,10 +192,10 @@ struct tf_session_version { * Session supported device types */ enum tf_device_type { - TF_DEVICE_TYPE_WH = 0, /**< Whitney+ */ - TF_DEVICE_TYPE_SR, /**< Stingray */ - TF_DEVICE_TYPE_THOR, /**< Thor */ - TF_DEVICE_TYPE_MAX /**< Maximum */ + TF_DEVICE_TYPE_P4 = 0, + TF_DEVICE_TYPE_SR, + TF_DEVICE_TYPE_P5, + TF_DEVICE_TYPE_MAX }; /** @@ -286,6 +290,8 @@ enum tf_tbl_type { TF_TBL_TYPE_ACT_ENCAP_32B, /** Wh+/SR/TH Action Encap 64 Bytes */ TF_TBL_TYPE_ACT_ENCAP_64B, + /* TH Action Encap 128 Bytes */ + TF_TBL_TYPE_ACT_ENCAP_128B, /** WH+/SR/TH Action Source Properties SMAC */ TF_TBL_TYPE_ACT_SP_SMAC, /** Wh+/SR/TH Action Source Properties SMAC IPv4 */ @@ -331,7 +337,7 @@ enum tf_tbl_type { * External table type - initially 1 poolsize entries. * All External table types are associated with a table * scope. Internal types are not. Currently this is - * a pool of 64B entries. + * a pool of 128B entries. */ TF_TBL_TYPE_EXT, TF_TBL_TYPE_MAX @@ -914,6 +920,71 @@ int tf_attach_session(struct tf *tfp, */ int tf_close_session(struct tf *tfp); +/** + * tf_set_session_hotup_state parameter definition. + */ +struct tf_set_session_hotup_state_parms { + /** + * [in] the structure is used to set the state of + * the hotup shared session. + * + */ + uint16_t state; +}; + +/** + * set hot upgrade shared session state + * + * This API is used to set the state of the shared session. + * + * [in] tfp + * Pointer to TF handle + * + * [in] parms + * Pointer to set hotup state parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int tf_set_session_hotup_state(struct tf *tfp, + struct tf_set_session_hotup_state_parms *parms); + +/** + * tf_get_session_hotup_state parameter definition. + */ +struct tf_get_session_hotup_state_parms { + /** + * [out] the structure is used to get the state of + * the hotup shared session. + * + */ + uint16_t state; + /** + * [out] get the ref_cnt of the hotup shared session. + * + */ + uint16_t ref_cnt; +}; + +/** + * get hot upgrade shared session state + * + * This API is used to set the state of the shared session. + * + * [in] tfp + * Pointer to TF handle + * + * [in] parms + * Pointer to get hotup state parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int tf_get_session_hotup_state(struct tf *tfp, + struct tf_get_session_hotup_state_parms *parms); + /** * @page ident Identity Management * @@ -1192,8 +1263,6 @@ int tf_free_tbl_scope(struct tf *tfp, * * @ref tf_get_tcam_entry * - * @ref tf_free_tcam_entry - * * @ref tf_move_tcam_shared_entries * * @ref tf_clear_tcam_shared_entries @@ -1258,7 +1327,7 @@ struct tf_search_tcam_entry_parms { }; /** - * search TCAM entry (experimental) + * search TCAM entry * * Search for a TCAM entry * @@ -1732,7 +1801,7 @@ struct tf_get_shared_tbl_increment_parms { * tf_get_shared_tbl_increment * * This API is currently only required for use in the shared - * session for Thor (p58) actions. An increment count is returned per + * session for P5 actions. An increment count is returned per * type to indicate how much to increment the start by for each * entry (see tf_resource_info) * @@ -1898,6 +1967,7 @@ struct tf_insert_em_entry_parms { */ uint64_t flow_id; }; + /** * tf_delete_em_entry parameter definition */ @@ -1927,6 +1997,7 @@ struct tf_delete_em_entry_parms { */ uint64_t flow_handle; }; + /** * tf_move_em_entry parameter definition */ @@ -1969,6 +2040,7 @@ struct tf_move_em_entry_parms { */ uint64_t flow_handle; }; + /** * tf_search_em_entry parameter definition (Future) */ @@ -2108,6 +2180,7 @@ int tf_search_em_entry(struct tf *tfp, * * @ref tf_get_global_cfg */ + /** * Tunnel Encapsulation Offsets */ @@ -2121,6 +2194,7 @@ enum tf_tunnel_encap_offsets { TF_TUNNEL_ENCAP_GRE, TF_TUNNEL_ENCAP_FULL_GENERIC }; + /** * Global Configuration Table Types */ @@ -2193,9 +2267,8 @@ int tf_set_global_cfg(struct tf *tfp, * @ref tf_set_if_tbl_entry * * @ref tf_get_if_tbl_entry - * - * @ref tf_restore_if_tbl_entry */ + /** * Enumeration of TruFlow interface table types. */ diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c index 1c97218b5b..02a9ebd7b2 100644 --- a/drivers/net/bnxt/tf_core/tf_device.c +++ b/drivers/net/bnxt/tf_core/tf_device.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -332,7 +332,7 @@ tf_dev_unbind_p4(struct tf *tfp) } /** - * Device specific bind function, THOR + * Device specific bind function, P5 * * [in] tfp * Pointer to TF handle @@ -504,7 +504,7 @@ tf_dev_bind_p58(struct tf *tfp, } /** - * Device specific unbind function, THOR + * Device specific unbind function, P5 * * [in] tfp * Pointer to TF handle @@ -602,14 +602,14 @@ tf_dev_bind(struct tf *tfp __rte_unused, struct tf_dev_info *dev_handle) { switch (type) { - case TF_DEVICE_TYPE_WH: + case TF_DEVICE_TYPE_P4: case TF_DEVICE_TYPE_SR: dev_handle->type = type; return tf_dev_bind_p4(tfp, resources, dev_handle, wc_num_slices); - case TF_DEVICE_TYPE_THOR: + case TF_DEVICE_TYPE_P5: dev_handle->type = type; return tf_dev_bind_p58(tfp, resources, @@ -627,11 +627,11 @@ tf_dev_bind_ops(enum tf_device_type type, struct tf_dev_info *dev_handle) { switch (type) { - case TF_DEVICE_TYPE_WH: + case TF_DEVICE_TYPE_P4: case TF_DEVICE_TYPE_SR: dev_handle->ops = &tf_dev_ops_p4_init; break; - case TF_DEVICE_TYPE_THOR: + case TF_DEVICE_TYPE_P5: dev_handle->ops = &tf_dev_ops_p58_init; break; default: @@ -648,10 +648,10 @@ tf_dev_unbind(struct tf *tfp, struct tf_dev_info *dev_handle) { switch (dev_handle->type) { - case TF_DEVICE_TYPE_WH: + case TF_DEVICE_TYPE_P4: case TF_DEVICE_TYPE_SR: return tf_dev_unbind_p4(tfp); - case TF_DEVICE_TYPE_THOR: + case TF_DEVICE_TYPE_P5: return tf_dev_unbind_p58(tfp); default: TFP_DRV_LOG(ERR, diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index 5a42180719..06c17a7212 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index 72c6b1cde8..911ea92471 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -296,11 +296,15 @@ tf_dev_p4_get_tcam_slice_info(struct tf *tfp, return rc; /* Single slice support */ -#define CFA_P4_WC_TCAM_SLICE_SIZE 12 - +#define CFA_P4_WC_TCAM_SLICE_SIZE (12) if (type == TF_TCAM_TBL_TYPE_WC_TCAM) { - *num_slices_per_row = tfs->wc_num_slices_per_row; - if (key_sz > *num_slices_per_row * CFA_P4_WC_TCAM_SLICE_SIZE) + if (key_sz <= 1 * CFA_P4_WC_TCAM_SLICE_SIZE) + *num_slices_per_row = TF_WC_TCAM_1_SLICE_PER_ROW; + else if (key_sz <= 2 * CFA_P4_WC_TCAM_SLICE_SIZE) + *num_slices_per_row = TF_WC_TCAM_2_SLICE_PER_ROW; + else if (key_sz <= 4 * CFA_P4_WC_TCAM_SLICE_SIZE) + *num_slices_per_row = TF_WC_TCAM_4_SLICE_PER_ROW; + else return -ENOTSUP; } else { /* for other type of tcam */ *num_slices_per_row = 1; diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index f8b424ebc9..6916c50fdc 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -16,6 +16,7 @@ #include "tfp.h" #include "tf_msg_common.h" #include "tf_tbl_sram.h" +#include "tf_util.h" #define TF_DEV_P58_PARIF_MAX 16 #define TF_DEV_P58_PF_MASK 0xfUL @@ -79,33 +80,39 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_DIR_MAX][TF_TBL_TYPE_MAX] = { [TF_DIR_RX][TF_TBL_TYPE_FULL_ACT_RECORD] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, - .slices = 4, + .slices = 8, }, [TF_DIR_RX][TF_TBL_TYPE_COMPACT_ACT_RECORD] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, - .slices = 8, + .slices = 16, }, /* Policy - Encaps in bank 2 */ [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_8B] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 8, + .slices = 16, }, [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_16B] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 4, + .slices = 8, }, [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_32B] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 2, + .slices = 4, }, [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_64B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 2, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_128B] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, @@ -116,49 +123,49 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_DIR_MAX][TF_TBL_TYPE_MAX] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 8, + .slices = 16, }, [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_16B] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 4, + .slices = 8, }, [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_32B] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 2, + .slices = 4, }, [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_64B] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 1, + .slices = 2, }, /* Policy - SP in bank 0 */ [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, - .slices = 8, + .slices = 16, }, [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, - .slices = 4, + .slices = 8, }, [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, - .slices = 2, + .slices = 4, }, /* Policy - Stats in bank 3 */ [TF_DIR_RX][TF_TBL_TYPE_ACT_STATS_64] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3, - .slices = 8, + .slices = 16, }, [TF_DIR_TX][TF_TBL_TYPE_EM_FKB] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB, @@ -192,33 +199,39 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_DIR_MAX][TF_TBL_TYPE_MAX] = { [TF_DIR_TX][TF_TBL_TYPE_FULL_ACT_RECORD] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, - .slices = 4, + .slices = 8, }, [TF_DIR_TX][TF_TBL_TYPE_COMPACT_ACT_RECORD] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, - .slices = 8, + .slices = 16, }, /* Policy - Encaps in bank 2 */ [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_8B] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 8, + .slices = 16, }, [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_16B] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 4, + .slices = 8, }, [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_32B] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 2, + .slices = 4, }, [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_64B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 2, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_128B] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, @@ -229,49 +242,49 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_DIR_MAX][TF_TBL_TYPE_MAX] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 8, + .slices = 16, }, [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_16B] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 4, + .slices = 8, }, [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_32B] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 2, + .slices = 4, }, [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_64B] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 1, + .slices = 2, }, /* Policy - SP in bank 0 */ [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, - .slices = 8, + .slices = 16, }, [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, - .slices = 4, + .slices = 8, }, [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, - .slices = 2, + .slices = 4, }, /* Policy - Stats in bank 3 */ [TF_DIR_TX][TF_TBL_TYPE_ACT_STATS_64] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3, - .slices = 8, + .slices = 16, }, }; @@ -406,10 +419,15 @@ tf_dev_p58_get_tcam_slice_info(struct tf *tfp, if (rc) return rc; -#define CFA_P58_WC_TCAM_SLICE_SIZE 24 +#define CFA_P58_WC_TCAM_SLICE_SIZE (24) if (type == TF_TCAM_TBL_TYPE_WC_TCAM) { - *num_slices_per_row = tfs->wc_num_slices_per_row; - if (key_sz > *num_slices_per_row * CFA_P58_WC_TCAM_SLICE_SIZE) + if (key_sz <= 1 * CFA_P58_WC_TCAM_SLICE_SIZE) + *num_slices_per_row = TF_WC_TCAM_1_SLICE_PER_ROW; + else if (key_sz <= 2 * CFA_P58_WC_TCAM_SLICE_SIZE) + *num_slices_per_row = TF_WC_TCAM_2_SLICE_PER_ROW; + else if (key_sz <= 4 * CFA_P58_WC_TCAM_SLICE_SIZE) + *num_slices_per_row = TF_WC_TCAM_4_SLICE_PER_ROW; + else return -ENOTSUP; } else { /* for other type of tcam */ *num_slices_per_row = 1; @@ -452,6 +470,7 @@ static int tf_dev_p58_get_shared_tbl_increment(struct tf *tfp __rte_unused, case TF_TBL_TYPE_ACT_ENCAP_16B: case TF_TBL_TYPE_ACT_ENCAP_32B: case TF_TBL_TYPE_ACT_ENCAP_64B: + case TF_TBL_TYPE_ACT_ENCAP_128B: case TF_TBL_TYPE_ACT_SP_SMAC: case TF_TBL_TYPE_ACT_SP_SMAC_IPV4: case TF_TBL_TYPE_ACT_SP_SMAC_IPV6: @@ -461,7 +480,7 @@ static int tf_dev_p58_get_shared_tbl_increment(struct tf *tfp __rte_unused, case TF_TBL_TYPE_ACT_MODIFY_16B: case TF_TBL_TYPE_ACT_MODIFY_32B: case TF_TBL_TYPE_ACT_MODIFY_64B: - parms->increment_cnt = 8; + parms->increment_cnt = 16; break; default: parms->increment_cnt = 1; @@ -493,6 +512,7 @@ static bool tf_dev_p58_is_sram_managed(struct tf *tfp __rte_unused, case TF_TBL_TYPE_ACT_ENCAP_16B: case TF_TBL_TYPE_ACT_ENCAP_32B: case TF_TBL_TYPE_ACT_ENCAP_64B: + case TF_TBL_TYPE_ACT_ENCAP_128B: case TF_TBL_TYPE_ACT_SP_SMAC: case TF_TBL_TYPE_ACT_SP_SMAC_IPV4: case TF_TBL_TYPE_ACT_SP_SMAC_IPV6: @@ -527,7 +547,7 @@ static bool tf_dev_p58_is_sram_managed(struct tf *tfp __rte_unused, * * [in/out] shift * Pointer to the factor to be used as a multiplier to translate - * between the RM units to the user address. SRAM manages 64B entries + * between the RM units to the user address. SRAM manages 128B entries * Addresses must be shifted to an 8B address. * * Returns diff --git a/drivers/net/bnxt/tf_core/tf_em_common.c b/drivers/net/bnxt/tf_core/tf_em_common.c index b56b7cc188..c518150d1f 100644 --- a/drivers/net/bnxt/tf_core/tf_em_common.c +++ b/drivers/net/bnxt/tf_core/tf_em_common.c @@ -1000,8 +1000,8 @@ tf_em_ext_common_unbind(struct tf *tfp) strerror(-rc)); return rc; } - ext_db = (struct em_ext_db *)ext_ptr; + ext_db = (struct em_ext_db *)ext_ptr; if (ext_db != NULL) { entry = ext_db->tbl_scope_ll.head; while (entry != NULL) { diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c index 8ea5d93672..46de63a9da 100644 --- a/drivers/net/bnxt/tf_core/tf_em_internal.c +++ b/drivers/net/bnxt/tf_core/tf_em_internal.c @@ -7,7 +7,6 @@ #include #include #include - #include "tf_core.h" #include "tf_util.h" #include "tf_common.h" @@ -63,7 +62,6 @@ tf_em_insert_int_entry(struct tf *tfp, return -1; } - rptr_index = index; rc = tf_msg_insert_em_internal_entry(tfp, parms, @@ -75,6 +73,7 @@ tf_em_insert_int_entry(struct tf *tfp, dpool_free(pool, index); return -1; } + TF_SET_GFID(gfid, ((rptr_index << TF_EM_INTERNAL_INDEX_SHIFT) | rptr_entry), @@ -95,7 +94,6 @@ tf_em_insert_int_entry(struct tf *tfp, return 0; } - /** Delete EM internal entry API * * returns: @@ -253,7 +251,6 @@ tf_em_int_bind(struct tf *tfp, return db_rc[TF_DIR_RX]; } - if (!tf_session_is_shared_session(tfs)) { for (i = 0; i < TF_DIR_MAX; i++) { iparms.rm_db = em_db->em_db[i]; @@ -335,11 +332,10 @@ tf_em_int_unbind(struct tf *tfp) } rc = tf_session_get_db(tfp, TF_MODULE_TYPE_EM, &em_db_ptr); - if (rc) { + if (rc) return 0; - } - em_db = (struct em_rm_db *)em_db_ptr; + em_db = (struct em_rm_db *)em_db_ptr; for (i = 0; i < TF_DIR_MAX; i++) { if (em_db->em_db[i] == NULL) continue; diff --git a/drivers/net/bnxt/tf_core/tf_identifier.c b/drivers/net/bnxt/tf_core/tf_identifier.c index 1846675916..7d9d9595dd 100644 --- a/drivers/net/bnxt/tf_core/tf_identifier.c +++ b/drivers/net/bnxt/tf_core/tf_identifier.c @@ -89,6 +89,7 @@ tf_ident_unbind(struct tf *tfp) rc = tf_session_get_db(tfp, TF_MODULE_TYPE_IDENTIFIER, &ident_db_ptr); if (rc) return 0; + ident_db = (struct ident_rm_db *)ident_db_ptr; for (i = 0; i < TF_DIR_MAX; i++) { diff --git a/drivers/net/bnxt/tf_core/tf_if_tbl.c b/drivers/net/bnxt/tf_core/tf_if_tbl.c index e667d6fa6d..578d361417 100644 --- a/drivers/net/bnxt/tf_core/tf_if_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_if_tbl.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -21,12 +21,6 @@ struct tf_if_tbl_db { struct tf_if_tbl_cfg *if_tbl_cfg_db[TF_DIR_MAX]; }; -/** - * Init flag, set on bind and cleared on unbind - * TODO: Store this data in session db - */ -static uint8_t init; - /** * Convert if_tbl_type to hwrm type. * @@ -80,8 +74,6 @@ tf_if_tbl_bind(struct tf *tfp, if_tbl_db->if_tbl_cfg_db[TF_DIR_TX] = parms->cfg; tf_session_set_if_tbl_db(tfp, (void *)if_tbl_db); - init = 1; - TFP_DRV_LOG(INFO, "Table Type - initialized\n"); @@ -92,14 +84,7 @@ int tf_if_tbl_unbind(struct tf *tfp) { int rc; - struct tf_if_tbl_db *if_tbl_db_ptr; - - /* Bail if nothing has been initialized */ - if (!init) { - TFP_DRV_LOG(INFO, - "No Table DBs created\n"); - return 0; - } + struct tf_if_tbl_db *if_tbl_db_ptr = NULL; TF_CHECK_PARMS1(tfp); @@ -108,9 +93,15 @@ tf_if_tbl_unbind(struct tf *tfp) TFP_DRV_LOG(INFO, "No IF Table DBs initialized\n"); return 0; } + /* Bail if nothing has been initialized */ + if (!if_tbl_db_ptr) { + TFP_DRV_LOG(INFO, + "No Table DBs created\n"); + return 0; + } tfp_free((void *)if_tbl_db_ptr); - init = 0; + tf_session_set_if_tbl_db(tfp, NULL); return 0; } @@ -120,24 +111,24 @@ tf_if_tbl_set(struct tf *tfp, struct tf_if_tbl_set_parms *parms) { int rc; - struct tf_if_tbl_db *if_tbl_db_ptr; + struct tf_if_tbl_db *if_tbl_db_ptr = NULL; struct tf_if_tbl_get_hcapi_parms hparms; TF_CHECK_PARMS3(tfp, parms, parms->data); - if (!init) { - TFP_DRV_LOG(ERR, - "%s: No Table DBs created\n", - tf_dir_2_str(parms->dir)); - return -EINVAL; - } - rc = tf_session_get_if_tbl_db(tfp, (void **)&if_tbl_db_ptr); if (rc) { TFP_DRV_LOG(INFO, "No IF Table DBs initialized\n"); return 0; } + if (!if_tbl_db_ptr) { + TFP_DRV_LOG(ERR, + "%s: No Table DBs created\n", + tf_dir_2_str(parms->dir)); + return -EINVAL; + } + /* Convert TF type to HCAPI type */ hparms.tbl_db = if_tbl_db_ptr->if_tbl_cfg_db[parms->dir]; hparms.db_index = parms->type; @@ -163,24 +154,24 @@ tf_if_tbl_get(struct tf *tfp, struct tf_if_tbl_get_parms *parms) { int rc = 0; - struct tf_if_tbl_db *if_tbl_db_ptr; + struct tf_if_tbl_db *if_tbl_db_ptr = NULL; struct tf_if_tbl_get_hcapi_parms hparms; TF_CHECK_PARMS3(tfp, parms, parms->data); - if (!init) { - TFP_DRV_LOG(ERR, - "%s: No Table DBs created\n", - tf_dir_2_str(parms->dir)); - return -EINVAL; - } - rc = tf_session_get_if_tbl_db(tfp, (void **)&if_tbl_db_ptr); if (rc) { TFP_DRV_LOG(INFO, "No IF Table DBs initialized\n"); return 0; } + if (!if_tbl_db_ptr) { + TFP_DRV_LOG(ERR, + "%s: No Table DBs created\n", + tf_dir_2_str(parms->dir)); + return -EINVAL; + } + /* Convert TF type to HCAPI type */ hparms.tbl_db = if_tbl_db_ptr->if_tbl_cfg_db[parms->dir]; hparms.db_index = parms->type; diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index fbc96d374c..1c66c7e01a 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -47,7 +47,6 @@ static_assert(sizeof(struct hwrm_tf_global_cfg_set_input) == static_assert(sizeof(struct hwrm_tf_em_insert_input) == TF_MSG_SIZE_HWRM_TF_EM_INSERT, "HWRM message size changed: hwrm_tf_em_insert_input"); - #define TF_MSG_SIZE_HWRM_TF_TBL_TYPE_SET 128 static_assert(sizeof(struct hwrm_tf_tbl_type_set_input) == TF_MSG_SIZE_HWRM_TF_TBL_TYPE_SET, @@ -61,13 +60,18 @@ static_assert(sizeof(struct hwrm_tf_tbl_type_set_input) == /** * This is the length of shared session name "tf_share" */ -#define TF_SHARED_SESSION_NAME_LEN 8 +#define TF_SHARED_SESSION_NAME_LEN 9 /** * This is the length of tcam shared session name "tf_shared-wc_tcam" */ #define TF_TCAM_SHARED_SESSION_NAME_LEN 17 +/** + * This is the length of tcam shared session name "tf_shared-poolx" + */ +#define TF_POOL_SHARED_SESSION_NAME_LEN 16 + /** * If data bigger than TF_PCI_BUF_SIZE_MAX then use DMA method */ @@ -135,18 +139,30 @@ tf_msg_session_open(struct bnxt *bp, struct hwrm_tf_session_open_input req = { 0 }; struct hwrm_tf_session_open_output resp = { 0 }; struct tfp_send_msg_parms parms = { 0 }; - int name_len; char *session_name; char *tcam_session_name; + char *pool_session_name; - /* Populate the request */ - name_len = strnlen(ctrl_chan_name, TF_SESSION_NAME_MAX); - session_name = &ctrl_chan_name[name_len - strlen("tf_shared")]; - tcam_session_name = &ctrl_chan_name[name_len - strlen("tf_shared-wc_tcam")]; - if (!strncmp(tcam_session_name, "tf_shared-wc_tcam", strlen("tf_shared-wc_tcam"))) - tfp_memcpy(&req.session_name, tcam_session_name, TF_TCAM_SHARED_SESSION_NAME_LEN); - else if (!strncmp(session_name, "tf_shared", strlen("tf_shared"))) - tfp_memcpy(&req.session_name, session_name, TF_SHARED_SESSION_NAME_LEN); + /* + * "tf_shared-wc_tcam" is defined for tf_fw version 1.0.0. + * "tf_shared-pool" is defined for version 1.0.1. + * "tf_shared" is used by both verions. + */ + tcam_session_name = strstr(ctrl_chan_name, "tf_shared-wc_tcam"); + pool_session_name = strstr(ctrl_chan_name, "tf_shared-pool"); + session_name = strstr(ctrl_chan_name, "tf_shared"); + if (tcam_session_name) + tfp_memcpy(&req.session_name, + tcam_session_name, + TF_TCAM_SHARED_SESSION_NAME_LEN); + else if (pool_session_name) + tfp_memcpy(&req.session_name, + pool_session_name, + TF_POOL_SHARED_SESSION_NAME_LEN); + else if (session_name) + tfp_memcpy(&req.session_name, + session_name, + TF_SHARED_SESSION_NAME_LEN); else tfp_memcpy(&req.session_name, ctrl_chan_name, TF_SESSION_NAME_MAX); @@ -191,9 +207,9 @@ tf_msg_session_client_register(struct tf *tfp, struct tfp_send_msg_parms parms = { 0 }; uint8_t fw_session_id; struct tf_dev_info *dev; - int name_len; char *session_name; char *tcam_session_name; + char *pool_session_name; /* Retrieve the device information */ rc = tf_session_get_device(tfs, &dev); @@ -214,24 +230,31 @@ tf_msg_session_client_register(struct tf *tfp, /* Populate the request */ req.fw_session_id = tfp_cpu_to_le_32(fw_session_id); - name_len = strnlen(ctrl_channel_name, TF_SESSION_NAME_MAX); - session_name = &ctrl_channel_name[name_len - strlen("tf_shared")]; - tcam_session_name = &ctrl_channel_name[name_len - - strlen("tf_shared-wc_tcam")]; - if (!strncmp(tcam_session_name, - "tf_shared-wc_tcam", - strlen("tf_shared-wc_tcam"))) + + /* + * "tf_shared-wc_tcam" is defined for tf_fw version 1.0.0. + * "tf_shared-pool" is defined for version 1.0.1. + * "tf_shared" is used by both verions. + */ + tcam_session_name = strstr(ctrl_channel_name, "tf_shared-wc_tcam"); + pool_session_name = strstr(ctrl_channel_name, "tf_shared-pool"); + session_name = strstr(ctrl_channel_name, "tf_shared"); + if (tcam_session_name) + tfp_memcpy(&req.session_client_name, + tcam_session_name, + TF_TCAM_SHARED_SESSION_NAME_LEN); + else if (pool_session_name) tfp_memcpy(&req.session_client_name, - tcam_session_name, - TF_TCAM_SHARED_SESSION_NAME_LEN); - else if (!strncmp(session_name, "tf_shared", strlen("tf_shared"))) + pool_session_name, + TF_POOL_SHARED_SESSION_NAME_LEN); + else if (session_name) tfp_memcpy(&req.session_client_name, - session_name, - TF_SHARED_SESSION_NAME_LEN); + session_name, + TF_SHARED_SESSION_NAME_LEN); else tfp_memcpy(&req.session_client_name, - ctrl_channel_name, - TF_SESSION_NAME_MAX); + ctrl_channel_name, + TF_SESSION_NAME_MAX); parms.tf_type = HWRM_TF_SESSION_REGISTER; parms.req_data = (uint32_t *)&req; @@ -431,7 +454,6 @@ tf_msg_session_resc_qcaps(struct tf *tfp, /* Post process the response */ data = (struct tf_rm_resc_req_entry *)qcaps_buf.va_addr; - for (i = 0; i < resp.size; i++) { query[i].type = tfp_le_to_cpu_32(data[i].type); query[i].min = tfp_le_to_cpu_16(data[i].min); @@ -1757,6 +1779,7 @@ tf_msg_set_tbl_entry(struct tf *tfp, struct hwrm_tf_tbl_type_set_input req = { 0 }; struct hwrm_tf_tbl_type_set_output resp = { 0 }; struct tfp_send_msg_parms parms = { 0 }; + struct tf_msg_dma_buf buf = { 0 }; uint8_t fw_session_id; struct tf_dev_info *dev; struct tf_session *tfs; @@ -1802,18 +1825,19 @@ tf_msg_set_tbl_entry(struct tf *tfp, /* Check for data size conformity */ if (size > TF_MSG_TBL_TYPE_SET_DATA_SIZE) { - rc = -EINVAL; - TFP_DRV_LOG(ERR, - "%s: Invalid parameters for msg type, rc:%s\n", - tf_dir_2_str(dir), - strerror(-rc)); - return rc; + /* use dma buffer */ + req.flags |= HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DMA; + rc = tf_msg_alloc_dma_buf(&buf, size); + if (rc) + goto cleanup; + tfp_memcpy(buf.va_addr, data, size); + tfp_memcpy(&req.data[0], + &buf.pa_addr, + sizeof(buf.pa_addr)); + } else { + tfp_memcpy(&req.data, data, size); } - tfp_memcpy(&req.data, - data, - size); - parms.tf_type = HWRM_TF_TBL_TYPE_SET; parms.req_data = (uint32_t *)&req; parms.req_size = sizeof(req); @@ -1823,10 +1847,10 @@ tf_msg_set_tbl_entry(struct tf *tfp, rc = tfp_send_msg_direct(tf_session_get_bp(tfp), &parms); - if (rc) - return rc; +cleanup: + tf_msg_free_dma_buf(&buf); - return 0; + return rc; } int @@ -2325,3 +2349,114 @@ tf_msg_get_version(struct bnxt *bp, return rc; } + +int +tf_msg_session_set_hotup_state(struct tf *tfp, uint16_t state) +{ + int rc; + struct hwrm_tf_session_hotup_state_set_input req = { 0 }; + struct hwrm_tf_session_hotup_state_set_output resp = { 0 }; + struct tfp_send_msg_parms parms = { 0 }; + uint8_t fw_session_id; + struct tf_dev_info *dev; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to lookup session, rc:%s\n", + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to lookup device, rc:%s\n", + strerror(-rc)); + return rc; + } + + rc = tf_session_get_fw_session_id(tfp, &fw_session_id); + if (rc) { + TFP_DRV_LOG(ERR, + "Unable to lookup FW id, rc:%s\n", + strerror(-rc)); + return rc; + } + + /* Populate the request */ + req.fw_session_id = tfp_cpu_to_le_32(fw_session_id); + req.state = tfp_cpu_to_le_16(state); + + parms.tf_type = HWRM_TF_SESSION_HOTUP_STATE_SET; + parms.req_data = (uint32_t *)&req; + parms.req_size = sizeof(req); + parms.resp_data = (uint32_t *)&resp; + parms.resp_size = sizeof(resp); + parms.mailbox = dev->ops->tf_dev_get_mailbox(); + + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), + &parms); + return rc; +} + +int +tf_msg_session_get_hotup_state(struct tf *tfp, + uint16_t *state, + uint16_t *ref_cnt) +{ + int rc; + struct hwrm_tf_session_hotup_state_get_input req = { 0 }; + struct hwrm_tf_session_hotup_state_get_output resp = { 0 }; + struct tfp_send_msg_parms parms = { 0 }; + uint8_t fw_session_id; + struct tf_dev_info *dev; + struct tf_session *tfs; + + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to lookup session, rc:%s\n", + strerror(-rc)); + return rc; + } + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to lookup device, rc:%s\n", + strerror(-rc)); + return rc; + } + + rc = tf_session_get_fw_session_id(tfp, &fw_session_id); + if (rc) { + TFP_DRV_LOG(ERR, + "Unable to lookup FW id, rc:%s\n", + strerror(-rc)); + return rc; + } + + /* Populate the request */ + req.fw_session_id = tfp_cpu_to_le_32(fw_session_id); + + parms.tf_type = HWRM_TF_SESSION_HOTUP_STATE_GET; + parms.req_data = (uint32_t *)&req; + parms.req_size = sizeof(req); + parms.resp_data = (uint32_t *)&resp; + parms.resp_size = sizeof(resp); + parms.mailbox = dev->ops->tf_dev_get_mailbox(); + + rc = tfp_send_msg_direct(tf_session_get_bp(tfp), + &parms); + + *state = tfp_le_to_cpu_16(resp.state); + *ref_cnt = tfp_le_to_cpu_16(resp.ref_cnt); + + return rc; +} diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h index 188b361d71..24d0ae5f43 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.h +++ b/drivers/net/bnxt/tf_core/tf_msg.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -761,4 +761,40 @@ int tf_msg_get_version(struct bnxt *bp, struct tf_dev_info *dev, struct tf_get_version_parms *parms); + +/** + * Send set hot upgrade state request to the firmware. + * + * [in] tfp + * Pointer to session handle + * + * [in] state + * Hot upgrade session state + * + * Returns: + * 0 on Success else internal Truflow error + */ +int +tf_msg_session_set_hotup_state(struct tf *tfp, + uint16_t state); + +/** + * Send get hot upgrade state request to the firmware. + * + * [in] tfp + * Pointer to session handle + * + * [out] state + * Pointer to hot upgrade session state + * + * [out] ref_cnt + * Pointer to hot upgrade session reference count + * + * Returns: + * 0 on Success else internal Truflow error + */ +int +tf_msg_session_get_hotup_state(struct tf *tfp, + uint16_t *state, + uint16_t *ref_cnt); #endif /* _TF_MSG_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c index d2045921b9..1fccb698d0 100644 --- a/drivers/net/bnxt/tf_core/tf_rm.c +++ b/drivers/net/bnxt/tf_core/tf_rm.c @@ -1,15 +1,12 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ #include - #include #include - #include - #include "tf_rm.h" #include "tf_common.h" #include "tf_util.h" @@ -18,9 +15,6 @@ #include "tfp.h" #include "tf_msg.h" -/* Logging defines */ -#define TF_RM_DEBUG 0 - /** * Generic RM Element data type that an RM DB is build upon. */ @@ -210,45 +204,6 @@ tf_rm_adjust_index(struct tf_rm_element *db, return rc; } -/** - * Logs an array of found residual entries to the console. - * - * [in] dir - * Receive or transmit direction - * - * [in] module - * Type of Device Module - * - * [in] count - * Number of entries in the residual array - * - * [in] residuals - * Pointer to an array of residual entries. Array is index same as - * the DB in which this function is used. Each entry holds residual - * value for that entry. - */ -#if (TF_RM_DEBUG == 1) -static void -tf_rm_log_residuals(enum tf_dir dir, - enum tf_module_type module, - uint16_t count, - uint16_t *residuals) -{ - int i; - - /* Walk the residual array and log the types that wasn't - * cleaned up to the console. - */ - for (i = 0; i < count; i++) { - if (residuals[i] != 0) - TFP_DRV_LOG(INFO, - "%s, %s was not cleaned up, %d outstanding\n", - tf_dir_2_str(dir), - tf_module_subtype_2_str(module, i), - residuals[i]); - } -} -#endif /* TF_RM_DEBUG == 1 */ /** * Performs a check of the passed in DB for any lingering elements. If * a resource type was found to not have been cleaned up by the caller @@ -364,12 +319,6 @@ tf_rm_check_residuals(struct tf_rm_new_db *rm_db, *resv_size = found; } -#if (TF_RM_DEBUG == 1) - tf_rm_log_residuals(rm_db->dir, - rm_db->module, - rm_db->num_entries, - residuals); -#endif tfp_free((void *)residuals); *resv = local_resv; @@ -419,7 +368,7 @@ tf_rm_update_parent_reservations(struct tf *tfp, bool shared_session) { int parent, child; - const char *type_str; + const char *type_str = NULL; /* Search through all the elements */ for (parent = 0; parent < num_elements; parent++) { @@ -444,11 +393,6 @@ tf_rm_update_parent_reservations(struct tf *tfp, dev->ops->tf_dev_get_resource_str(tfp, cfg[parent].hcapi_type, &type_str); -#if (TF_RM_DEBUG == 1) - printf("%s:%s cnt(%d) slices(%d)\n", - type_str, tf_tbl_type_2_str(parent), - alloc_cnt[parent], p_slices); -#endif /* (TF_RM_DEBUG == 1) */ } /* Search again through all the elements */ @@ -469,13 +413,7 @@ tf_rm_update_parent_reservations(struct tf *tfp, dev->ops->tf_dev_get_resource_str(tfp, cfg[child].hcapi_type, &type_str); -#if (TF_RM_DEBUG == 1) - printf("%s:%s cnt(%d) slices(%d)\n", - type_str, - tf_tbl_type_2_str(child), - alloc_cnt[child], - c_slices); -#endif /* (TF_RM_DEBUG == 1) */ + /* Increment the parents combined count * with each child's count adjusted for * number of slices per RM alloc item. @@ -492,10 +430,6 @@ tf_rm_update_parent_reservations(struct tf *tfp, } /* Save the parent count to be requested */ req_cnt[parent] = combined_cnt; -#if (TF_RM_DEBUG == 1) - printf("%s calculated total:%d\n\n", - type_str, req_cnt[parent]); -#endif /* (TF_RM_DEBUG == 1) */ } } return 0; @@ -595,12 +529,6 @@ tf_rm_create_db(struct tf *tfp, &hcapi_items); if (hcapi_items == 0) { -#if (TF_RM_DEBUG == 1) - TFP_DRV_LOG(INFO, - "%s: module: %s Empty RM DB create request\n", - tf_dir_2_str(parms->dir), - tf_module_2_str(parms->module)); -#endif parms->rm_db = NULL; return -ENOMEM; } @@ -746,7 +674,7 @@ tf_rm_create_db(struct tf *tfp, rc = ba_init(db[i].pool, resv[j].stride, - !tf_session_is_shared_session(tfs)); + true); if (rc) { TFP_DRV_LOG(ERR, "%s: Pool init failed, type:%d:%s\n", @@ -773,13 +701,6 @@ tf_rm_create_db(struct tf *tfp, rm_db->module = parms->module; *parms->rm_db = (void *)rm_db; -#if (TF_RM_DEBUG == 1) - - printf("%s: module:%s\n", - tf_dir_2_str(parms->dir), - tf_module_2_str(parms->module)); -#endif /* (TF_RM_DEBUG == 1) */ - tfp_free((void *)req); tfp_free((void *)resv); tfp_free((void *)req_cnt); @@ -812,6 +733,7 @@ tf_rm_create_db_no_reservation(struct tf *tfp, struct tf_rm_new_db *rm_db; struct tf_rm_element *db; uint32_t pool_size; + bool shared_session = 0; TF_CHECK_PARMS2(tfp, parms); @@ -841,6 +763,16 @@ tf_rm_create_db_no_reservation(struct tf *tfp, tfp_memcpy(req_cnt, parms->alloc_cnt, parms->num_elements * sizeof(uint16_t)); + shared_session = tf_session_is_shared_session(tfs); + + /* Update the req_cnt based upon the element configuration + */ + tf_rm_update_parent_reservations(tfp, dev, parms->cfg, + parms->alloc_cnt, + parms->num_elements, + req_cnt, + shared_session); + /* Process capabilities against DB requirements. However, as a * DB can hold elements that are not HCAPI we can reduce the * req msg content by removing those out of the request yet @@ -855,11 +787,6 @@ tf_rm_create_db_no_reservation(struct tf *tfp, &hcapi_items); if (hcapi_items == 0) { - TFP_DRV_LOG(ERR, - "%s: module:%s Empty RM DB create request\n", - tf_dir_2_str(parms->dir), - tf_module_2_str(parms->module)); - parms->rm_db = NULL; return -ENOMEM; } @@ -938,6 +865,7 @@ tf_rm_create_db_no_reservation(struct tf *tfp, db[i].cfg_type = cfg->cfg_type; db[i].hcapi_type = cfg->hcapi_type; + db[i].slices = cfg->slices; /* Save the parent subtype for later use to find the pool */ @@ -986,7 +914,7 @@ tf_rm_create_db_no_reservation(struct tf *tfp, rc = ba_init(db[i].pool, resv[j].stride, - !tf_session_is_shared_session(tfs)); + true); if (rc) { TFP_DRV_LOG(ERR, "%s: Pool init failed, type:%d:%s\n", @@ -1013,13 +941,6 @@ tf_rm_create_db_no_reservation(struct tf *tfp, rm_db->module = parms->module; *parms->rm_db = (void *)rm_db; -#if (TF_RM_DEBUG == 1) - - printf("%s: module:%s\n", - tf_dir_2_str(parms->dir), - tf_module_2_str(parms->module)); -#endif /* (TF_RM_DEBUG == 1) */ - tfp_free((void *)req); tfp_free((void *)resv); tfp_free((void *)req_cnt); @@ -1036,6 +957,7 @@ tf_rm_create_db_no_reservation(struct tf *tfp, return -EINVAL; } + int tf_rm_free_db(struct tf *tfp, struct tf_rm_free_db_parms *parms) @@ -1110,6 +1032,7 @@ tf_rm_free_db(struct tf *tfp, return rc; } + /** * Get the bit allocator pool associated with the subtype and the db * @@ -1388,6 +1311,7 @@ tf_rm_get_hcapi_type(struct tf_rm_get_hcapi_parms *parms) return 0; } + int tf_rm_get_slices(struct tf_rm_get_slices_parms *parms) { @@ -1440,6 +1364,7 @@ tf_rm_get_inuse_count(struct tf_rm_get_inuse_count_parms *parms) return rc; } + /* Only used for table bulk get at this time */ int diff --git a/drivers/net/bnxt/tf_core/tf_session.c b/drivers/net/bnxt/tf_core/tf_session.c index d0a0916c6a..253d716572 100644 --- a/drivers/net/bnxt/tf_core/tf_session.c +++ b/drivers/net/bnxt/tf_core/tf_session.c @@ -1,12 +1,10 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ #include - #include - #include "tf_session.h" #include "tf_common.h" #include "tf_msg.h" @@ -59,8 +57,9 @@ tf_session_create(struct tf *tfp, union tf_session_id *session_id; struct tf_dev_info dev; bool shared_session_creator; - int name_len; - char *name; + char *shared_name; + char *tcam_session_name; + char *pool_session_name; TF_CHECK_PARMS2(tfp, parms); @@ -180,16 +179,18 @@ tf_session_create(struct tf *tfp, session->em_ext_db_handle = NULL; /* Populate the request */ - name_len = strnlen(parms->open_cfg->ctrl_chan_name, - TF_SESSION_NAME_MAX); - name = &parms->open_cfg->ctrl_chan_name[name_len - strlen("tf_shared")]; - if (!strncmp(name, "tf_shared", strlen("tf_shared"))) - session->shared_session = true; - - name = &parms->open_cfg->ctrl_chan_name[name_len - - strlen("tf_shared-wc_tcam")]; - if (!strncmp(name, "tf_shared-wc_tcam", strlen("tf_shared-wc_tcam"))) + shared_name = strstr(parms->open_cfg->ctrl_chan_name, "tf_shared"); + if (shared_name) { session->shared_session = true; + /* + * "tf_shared-wc_tcam" is defined for tf_fw version 1.0.0. + * "tf_shared-pool" is defined for version 1.0.1. + */ + tcam_session_name = strstr(parms->open_cfg->ctrl_chan_name, "tf_shared-wc_tcam"); + pool_session_name = strstr(parms->open_cfg->ctrl_chan_name, "tf_shared-pool"); + if (tcam_session_name || pool_session_name) + session->shared_session_hotup = true; + } if (session->shared_session && shared_session_creator) { session->shared_session_creator = true; @@ -342,7 +343,6 @@ tf_session_client_create(struct tf *tfp, return rc; } - /** * Destroys a Session Client on an existing Session. * @@ -441,7 +441,7 @@ tf_session_open_session(struct tf *tfp, TFP_DRV_LOG(INFO, "Session created, session_client_id:%d," - "session_id:0x%08x, fw_session_id:%d\n", + " session_id:0x%08x, fw_session_id:%d\n", parms->open_cfg->session_client_id.id, parms->open_cfg->session_id.id, parms->open_cfg->session_id.internal.fw_session_id); @@ -462,7 +462,7 @@ tf_session_open_session(struct tf *tfp, } TFP_DRV_LOG(INFO, - "Session Client:%d registered on session:0x%8x\n", + "Session Client:%d registered on session:0x%08x\n", scparms.session_client_id->internal.fw_session_client_id, tfp->session->session_id.id); } @@ -535,6 +535,11 @@ tf_session_close_session(struct tf *tfp, return rc; } + /* Record the session we're closing so the caller knows the + * details. + */ + *parms->session_id = tfs->session_id; + /* In case multiple clients we chose to close those first */ if (tfs->ref_count > 1) { /* Linaro gcc can't static init this structure */ @@ -567,11 +572,6 @@ tf_session_close_session(struct tf *tfp, return 0; } - /* Record the session we're closing so the caller knows the - * details. - */ - *parms->session_id = tfs->session_id; - rc = tf_session_get_device(tfs, &tfd); if (rc) { TFP_DRV_LOG(ERR, @@ -1140,3 +1140,71 @@ tf_session_set_if_tbl_db(struct tf *tfp, tfs->if_tbl_db_handle = if_tbl_handle; return rc; } + +int +tf_session_set_hotup_state(struct tf *tfp, + struct tf_set_session_hotup_state_parms *parms) +{ + int rc = 0; + struct tf_session *tfs = NULL; + + rc = tf_session_get_session(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "Session lookup failed, rc:%s\n", + strerror(-rc)); + return rc; + } + + if (!tf_session_is_shared_session(tfs)) { + rc = -EINVAL; + TFP_DRV_LOG(ERR, + "Only shared session able to set state, rc:%s\n", + strerror(-rc)); + return rc; + } + + rc = tf_msg_session_set_hotup_state(tfp, parms->state); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "Set session hot upgrade state failed, rc:%s\n", + strerror(-rc)); + } + + return rc; +} + +int +tf_session_get_hotup_state(struct tf *tfp, + struct tf_get_session_hotup_state_parms *parms) +{ + int rc = 0; + struct tf_session *tfs = NULL; + + rc = tf_session_get_session(tfp, &tfs); + if (rc) { + TFP_DRV_LOG(ERR, + "Session lookup failed, rc:%s\n", + strerror(-rc)); + return rc; + } + + if (!tf_session_is_shared_session(tfs)) { + rc = -EINVAL; + TFP_DRV_LOG(ERR, + "Only shared session able to get state, rc:%s\n", + strerror(-rc)); + return rc; + } + + rc = tf_msg_session_get_hotup_state(tfp, &parms->state, &parms->ref_cnt); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "Get session hot upgrade state failed, rc:%s\n", + strerror(-rc)); + } + + return rc; +} diff --git a/drivers/net/bnxt/tf_core/tf_session.h b/drivers/net/bnxt/tf_core/tf_session.h index 5a94b941fa..9bbbccf125 100644 --- a/drivers/net/bnxt/tf_core/tf_session.h +++ b/drivers/net/bnxt/tf_core/tf_session.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -8,7 +8,6 @@ #include #include - #include "bitalloc.h" #include "tf_core.h" #include "tf_device.h" @@ -48,7 +47,7 @@ * * Shared memory containing private TruFlow session information. * Through this structure the session can keep track of resource - * allocations. It also holds info about Session Clients. + * allocations. It also holds info about Session Clients. * * Memory is assigned to the Truflow instance by way of * tf_open_session. Memory is allocated and owned by i.e. ULP. @@ -78,6 +77,11 @@ struct tf_session { */ bool shared_session; + /** + * Boolean controlling the split of hardware resources for hotupgrade. + */ + bool shared_session_hotup; + /** * This flag indicates the shared session on firmware side is created * by this session. Some privileges may be assigned to this session. @@ -169,6 +173,12 @@ struct tf_session { * Number of slices per row for WC TCAM */ uint16_t wc_num_slices_per_row; + + /** + * Indicates if TCAM is controlled by TCAM Manager + */ + int tcam_mgr_control[TF_DIR_MAX][TF_TCAM_TBL_TYPE_MAX]; + }; /** @@ -276,11 +286,9 @@ struct tf_session_close_session_parms { * * @ref tf_session_is_shared_session * - * #define TF_SHARED * @ref tf_session_get_tcam_shared_db * * @ref tf_session_set_tcam_shared_db - * #endif * * @ref tf_session_get_sram_db * @@ -588,6 +596,21 @@ tf_session_is_shared_session(struct tf_session *tfs) return tfs->shared_session; } +/** + * Check if the session is shared session for hot upgrade. + * + * [in] session, pointer to the session + * + * Returns: + * - true if it is shared session for hot upgrade + * - false if it is not shared session for hot upgrade + */ +static inline bool +tf_session_is_shared_hotup_session(struct tf_session *tfs) +{ + return tfs->shared_session_hotup; +} + /** * Check if the session is the shared session creator * @@ -716,4 +739,36 @@ tf_session_set_if_tbl_db(struct tf *tfp, int tf_session_get_if_tbl_db(struct tf *tfp, void **if_tbl_handle); + +/** + * Set hot upgrade session state. + * + * [in] tfp + * Pointer to session handle + * + * [in] parms + * Hot upgrade session state parms + * + * Returns: + * 0 on Success else internal Truflow error + */ +int +tf_session_set_hotup_state(struct tf *tfp, + struct tf_set_session_hotup_state_parms *parms); + +/** + * Get hot upgrade session state. + * + * [in] tfp + * Pointer to session handle + * + * [out] parms + * Pointer to hot upgrade session state parms + * + * Returns: + * 0 on Success else internal Truflow error + */ +int +tf_session_get_hotup_state(struct tf *tfp, + struct tf_get_session_hotup_state_parms *parms); #endif /* _TF_SESSION_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_sram_mgr.c b/drivers/net/bnxt/tf_core/tf_sram_mgr.c index acb3372486..87e8882fed 100644 --- a/drivers/net/bnxt/tf_core/tf_sram_mgr.c +++ b/drivers/net/bnxt/tf_core/tf_sram_mgr.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ #include @@ -21,7 +21,7 @@ /** * TF SRAM block info * - * Contains all the information about a particular 64B SRAM + * Contains all the information about a particular 128B SRAM * block and the slices within it. */ struct tf_sram_block { @@ -36,9 +36,9 @@ struct tf_sram_block { * If a bit is set, it indicates the slice * in the row is in use. */ - uint8_t in_use_mask; + uint16_t in_use_mask; - /** Block id - this is a 64B offset + /** Block id - this is a 128B offset */ uint16_t block_id; }; @@ -46,7 +46,7 @@ struct tf_sram_block { /** * TF SRAM block list * - * List of 64B SRAM blocks used for fixed size slices (8, 16, 32, 64B) + * List of 128B SRAM blocks used for fixed size slices (8, 16, 32, 64B, 128B) */ struct tf_sram_slice_list { /** Pointer to head of linked list of blocks. @@ -70,7 +70,6 @@ struct tf_sram_slice_list { enum tf_sram_slice_size size; }; - /** * TF SRAM bank info consists of lists of different slice sizes per bank */ @@ -111,6 +110,8 @@ const char return "32B slice"; case TF_SRAM_SLICE_SIZE_64B: return "64B slice"; + case TF_SRAM_SLICE_SIZE_128B: + return "128B slice"; default: return "Invalid slice size"; } @@ -179,8 +180,8 @@ static void tf_sram_offset_2_block_id(enum tf_sram_bank_id bank_id, uint16_t offset, uint16_t *block_id, uint16_t *slice_offset) { - *slice_offset = offset & 0x7; - *block_id = ((offset & ~0x7) >> 3) - + *slice_offset = offset & 0xf; + *block_id = ((offset & ~0xf) >> 3) - tf_sram_bank_2_base_offset[bank_id]; } @@ -232,31 +233,37 @@ tf_sram_free_slice(enum tf_sram_slice_size slice_size, bool *block_is_empty) { int rc = 0; - uint8_t shift; - uint8_t slice_mask = 0; + uint16_t shift; + uint16_t slice_mask = 0; TF_CHECK_PARMS2(block, block_is_empty); switch (slice_size) { case TF_SRAM_SLICE_SIZE_8B: shift = slice_offset >> 0; - assert(shift < 8); + assert(shift < 16); slice_mask = 1 << shift; break; case TF_SRAM_SLICE_SIZE_16B: shift = slice_offset >> 1; - assert(shift < 4); + assert(shift < 8); slice_mask = 1 << shift; break; case TF_SRAM_SLICE_SIZE_32B: shift = slice_offset >> 2; - assert(shift < 2); + assert(shift < 4); slice_mask = 1 << shift; break; case TF_SRAM_SLICE_SIZE_64B: + shift = slice_offset >> 3; + assert(shift < 2); + slice_mask = 1 << shift; + break; + + case TF_SRAM_SLICE_SIZE_128B: default: shift = slice_offset >> 0; assert(shift < 1); @@ -294,27 +301,32 @@ tf_sram_get_next_slice_in_block(struct tf_sram_block *block, bool *block_is_full) { int rc, free_id = -1; - uint8_t shift, max_slices, mask, i, full_mask; + uint16_t shift, max_slices, mask, i, full_mask; TF_CHECK_PARMS3(block, slice_offset, block_is_full); switch (slice_size) { case TF_SRAM_SLICE_SIZE_8B: shift = 0; - max_slices = 8; - full_mask = 0xff; + max_slices = 16; + full_mask = 0xffff; break; case TF_SRAM_SLICE_SIZE_16B: shift = 1; - max_slices = 4; - full_mask = 0xf; + max_slices = 8; + full_mask = 0xff; break; case TF_SRAM_SLICE_SIZE_32B: shift = 2; + max_slices = 4; + full_mask = 0xf; + break; + case TF_SRAM_SLICE_SIZE_64B: + shift = 3; max_slices = 2; full_mask = 0x3; break; - case TF_SRAM_SLICE_SIZE_64B: + case TF_SRAM_SLICE_SIZE_128B: default: shift = 0; max_slices = 1; @@ -338,7 +350,6 @@ tf_sram_get_next_slice_in_block(struct tf_sram_block *block, else *block_is_full = false; - if (free_id >= 0) { *slice_offset = free_id << shift; rc = 0; @@ -362,8 +373,8 @@ tf_sram_is_slice_allocated_in_block(struct tf_sram_block *block, bool *is_allocated) { int rc = 0; - uint8_t shift; - uint8_t slice_mask = 0; + uint16_t shift; + uint16_t slice_mask = 0; TF_CHECK_PARMS2(block, is_allocated); @@ -372,23 +383,29 @@ tf_sram_is_slice_allocated_in_block(struct tf_sram_block *block, switch (slice_size) { case TF_SRAM_SLICE_SIZE_8B: shift = slice_offset >> 0; - assert(shift < 8); + assert(shift < 16); slice_mask = 1 << shift; break; case TF_SRAM_SLICE_SIZE_16B: shift = slice_offset >> 1; - assert(shift < 4); + assert(shift < 8); slice_mask = 1 << shift; break; case TF_SRAM_SLICE_SIZE_32B: shift = slice_offset >> 2; - assert(shift < 2); + assert(shift < 4); slice_mask = 1 << shift; break; case TF_SRAM_SLICE_SIZE_64B: + shift = slice_offset >> 3; + assert(shift < 2); + slice_mask = 1 << shift; + break; + + case TF_SRAM_SLICE_SIZE_128B: default: shift = slice_offset >> 0; assert(shift < 1); @@ -416,7 +433,6 @@ tf_sram_get_block_cnt(struct tf_sram_slice_list *slice_list) return slice_list->cnt; } - /** * Free a block data structure - does not free to the RM */ @@ -508,22 +524,26 @@ tf_sram_find_first_not_full_block(struct tf_sram_slice_list *slice_list, struct tf_sram_block **first_not_full_block) { struct tf_sram_block *block = slice_list->head; - uint8_t slice_mask, mask; + uint16_t slice_mask, mask; switch (slice_size) { case TF_SRAM_SLICE_SIZE_8B: - slice_mask = 0xff; + slice_mask = 0xffff; break; case TF_SRAM_SLICE_SIZE_16B: - slice_mask = 0xf; + slice_mask = 0xff; break; case TF_SRAM_SLICE_SIZE_32B: - slice_mask = 0x3; + slice_mask = 0xf; break; case TF_SRAM_SLICE_SIZE_64B: + slice_mask = 0x3; + break; + + case TF_SRAM_SLICE_SIZE_128B: default: slice_mask = 0x1; break; @@ -543,7 +563,7 @@ tf_sram_find_first_not_full_block(struct tf_sram_slice_list *slice_list, static void tf_sram_dump_block(struct tf_sram_block *block) { - TFP_DRV_LOG(INFO, "block_id(0x%x) in_use_mask(0x%02x)\n", + TFP_DRV_LOG(INFO, "block_id(0x%x) in_use_mask(0x%04x)\n", block->block_id, block->in_use_mask); } @@ -631,9 +651,10 @@ int tf_sram_mgr_alloc(void *sram_handle, struct tf_sram *sram; struct tf_sram_slice_list *slice_list; uint16_t block_id, slice_offset = 0; - uint32_t index; + uint32_t index, next_index; struct tf_sram_block *block; struct tf_rm_allocate_parms aparms = { 0 }; + struct tf_rm_free_parms fparms = { 0 }; bool block_is_full; uint16_t block_offset; @@ -662,11 +683,34 @@ int tf_sram_mgr_alloc(void *sram_handle, aparms.subtype = parms->tbl_type; aparms.rm_db = parms->rm_db; rc = tf_rm_allocate(&aparms); + if (rc) + return rc; + /* to support 128B block rows, we are allocating + * 2 sequential 64B blocks from RM, if they are not next to + * each other we are going to have issues + */ + aparms.index = &next_index; + rc = tf_rm_allocate(&aparms); if (rc) return rc; + /* make sure we do get the next 64B block, else free the + * allocated indexes and return error + */ + if (unlikely(index + 1 != next_index)) { + fparms.index = index; + fparms.subtype = parms->tbl_type; + fparms.rm_db = parms->rm_db; + tf_rm_free(&fparms); + fparms.index = next_index; + tf_rm_free(&fparms); + TFP_DRV_LOG(ERR, + "Could not allocate two sequential 64B blocks\n"); + return -ENOMEM; + } block_id = index; block = tf_sram_alloc_block(slice_list, block_id); + } else { /* Block exists */ @@ -742,7 +786,7 @@ tf_sram_mgr_free(void *sram_handle, } #if (STATS_CLEAR_ON_READ_SUPPORT == 0) /* If this is a counter, clear it. In the future we need to switch to - * using the special access registers on Thor to automatically clear on + * using the special access registers on P5 to automatically clear on * read. */ /* If this is counter table, clear the entry on free */ @@ -794,6 +838,13 @@ tf_sram_mgr_free(void *sram_handle, TFP_DRV_LOG(ERR, "Free block_id(%d) failed error(%s)\n", block_id, strerror(-rc)); } + fparms.index = block_id + 1; + rc = tf_rm_free(&fparms); + + if (rc) { + TFP_DRV_LOG(ERR, "Free next block_id(%d) failed error(%s)\n", + block_id + 1, strerror(-rc)); + } /* Free local entry regardless */ tf_sram_free_block(slice_list, block); diff --git a/drivers/net/bnxt/tf_core/tf_sram_mgr.h b/drivers/net/bnxt/tf_core/tf_sram_mgr.h index fc78426130..878195c404 100644 --- a/drivers/net/bnxt/tf_core/tf_sram_mgr.h +++ b/drivers/net/bnxt/tf_core/tf_sram_mgr.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -26,28 +26,28 @@ */ #define STATS_CLEAR_ON_READ_SUPPORT 0 -#define TF_SRAM_MGR_BLOCK_SZ_BYTES 64 +#define TF_SRAM_MGR_BLOCK_SZ_BYTES 128 #define TF_SRAM_MGR_MIN_SLICE_BYTES 8 /** * TF slice size. * - * A slice is part of a 64B row + * A slice is part of a 128B row * * Each slice is a multiple of 8B */ enum tf_sram_slice_size { - TF_SRAM_SLICE_SIZE_8B, /**< 8 byte SRAM slice */ - TF_SRAM_SLICE_SIZE_16B, /**< 16 byte SRAM slice */ - TF_SRAM_SLICE_SIZE_32B, /**< 32 byte SRAM slice */ - TF_SRAM_SLICE_SIZE_64B, /**< 64 byte SRAM slice */ - TF_SRAM_SLICE_SIZE_MAX /**< slice limit */ + TF_SRAM_SLICE_SIZE_8B, /**< 8 byte SRAM slice */ + TF_SRAM_SLICE_SIZE_16B, /**< 16 byte SRAM slice */ + TF_SRAM_SLICE_SIZE_32B, /**< 32 byte SRAM slice */ + TF_SRAM_SLICE_SIZE_64B, /**< 64 byte SRAM slice */ + TF_SRAM_SLICE_SIZE_128B, /**< 128 byte SRAM slice */ + TF_SRAM_SLICE_SIZE_MAX /**< slice limit */ }; - /** Initialize the SRAM slice manager * - * The SRAM slice manager manages slices within 64B rows. Slices are of size + * The SRAM slice manager manages slices within 128B rows. Slices are of size * tf_sram_slice_size. This function provides a handle to the SRAM manager * data. * @@ -181,7 +181,7 @@ struct tf_sram_mgr_free_parms { /** * Free an SRAM Slice * - * Free an SRAM slice to the indicated bank. This may result in a 64B row + * Free an SRAM slice to the indicated bank. This may result in a 128B row * being returned to the RM SRAM bank pool. * * [in] sram_handle diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c index f18e4ba346..f5f3889934 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_tbl.c @@ -1,12 +1,11 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ /* Truflow Table APIs and supporting code */ #include - #include "tf_tbl.h" #include "tf_common.h" #include "tf_rm.h" @@ -18,8 +17,8 @@ struct tf; -#define TF_TBL_RM_TO_PTR(new_idx, idx, base, shift) { \ - *(new_idx) = (((idx) + (base)) << (shift)); \ +#define TF_TBL_RM_TO_PTR(new_idx, idx, base, shift) { \ + *(new_idx) = (((idx) + (base)) << (shift)); \ } int @@ -98,6 +97,7 @@ tf_tbl_unbind(struct tf *tfp) rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr); if (rc) return 0; + tbl_db = (struct tbl_rm_db *)tbl_db_ptr; for (i = 0; i < TF_DIR_MAX; i++) { diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.c b/drivers/net/bnxt/tf_core/tf_tbl_sram.c index 567f912dfa..3a6f1c68c7 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl_sram.c +++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -73,11 +73,12 @@ const uint16_t tf_tbl_sram_hcapi_2_bank[CFA_RESOURCE_TYPE_P58_LAST] = { * Translate HCAPI type to SRAM Manager bank */ const uint8_t tf_tbl_sram_slices_2_size[TF_TBL_SRAM_SLICES_MAX + 1] = { - [0] = TF_SRAM_SLICE_SIZE_64B, /* if 0 slices assume 1 64B block */ - [1] = TF_SRAM_SLICE_SIZE_64B, /* 1 slice per 64B block */ - [2] = TF_SRAM_SLICE_SIZE_32B, /* 2 slices per 64B block */ - [4] = TF_SRAM_SLICE_SIZE_16B, /* 4 slices per 64B block */ - [8] = TF_SRAM_SLICE_SIZE_8B /* 8 slices per 64B block */ + [0] = TF_SRAM_SLICE_SIZE_128B, /* if 0 slices assume 1 128B block */ + [1] = TF_SRAM_SLICE_SIZE_128B, /* 1 slice per 128B block */ + [2] = TF_SRAM_SLICE_SIZE_64B, /* 2 slice per 128B block */ + [4] = TF_SRAM_SLICE_SIZE_32B, /* 4 slices per 128B block */ + [8] = TF_SRAM_SLICE_SIZE_16B, /* 8 slices per 128B block */ + [16] = TF_SRAM_SLICE_SIZE_8B /* 16 slices per 128B block */ }; /** @@ -340,7 +341,7 @@ tf_tbl_sram_free(struct tf *tfp __rte_unused, rc = tf_sram_mgr_is_allocated(sram_handle, &aparms); if (rc || !allocated) { TFP_DRV_LOG(ERR, - "%s: Free of invalid entry:%s idx(%d):(%s)\n", + "%s: Free of invalid entry:%s idx(0x%x):(%s)\n", tf_dir_2_str(parms->dir), tf_tbl_type_2_str(parms->type), parms->idx, @@ -361,7 +362,7 @@ tf_tbl_sram_free(struct tf *tfp __rte_unused, rc = tf_sram_mgr_free(sram_handle, &fparms); if (rc) { TFP_DRV_LOG(ERR, - "%s: Failed to free entry:%s idx(%d)\n", + "%s: Failed to free entry:%s idx(0x%x)\n", tf_dir_2_str(parms->dir), tf_tbl_type_2_str(parms->type), parms->idx); @@ -469,7 +470,7 @@ tf_tbl_sram_set(struct tf *tfp, if (rallocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { TFP_DRV_LOG(ERR, - "%s, Invalid or not allocated index, type:%s, idx:%d\n", + "%s, Invalid or not allocated index, type:%s, idx:0x%x\n", tf_dir_2_str(parms->dir), tf_tbl_type_2_str(parms->type), parms->idx); @@ -484,7 +485,7 @@ tf_tbl_sram_set(struct tf *tfp, rc = tf_sram_mgr_is_allocated(sram_handle, &aparms); if (rc || !allocated) { TFP_DRV_LOG(ERR, - "%s: Entry not allocated:%s idx(%d):(%s)\n", + "%s: Entry not allocated:%s idx(0x%x):(%s)\n", tf_dir_2_str(parms->dir), tf_tbl_type_2_str(parms->type), parms->idx, @@ -587,7 +588,7 @@ tf_tbl_sram_get(struct tf *tfp, rc = tf_sram_mgr_is_allocated(sram_handle, &aparms); if (rc || !allocated) { TFP_DRV_LOG(ERR, - "%s: Entry not allocated:%s idx(%d):(%s)\n", + "%s: Entry not allocated:%s idx(0x%x):(%s)\n", tf_dir_2_str(parms->dir), tf_tbl_type_2_str(parms->type), parms->idx, @@ -711,7 +712,7 @@ tf_tbl_sram_bulk_get(struct tf *tfp, rc = tf_sram_mgr_is_allocated(sram_handle, &aparms); if (rc || !allocated) { TFP_DRV_LOG(ERR, - "%s: Entry not allocated:%s last_idx(%d):(%s)\n", + "%s: Entry not allocated:%s last_idx(0x%x):(%s)\n", tf_dir_2_str(parms->dir), tf_tbl_type_2_str(parms->type), idx, diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c index 1c42a6adc7..9e0671d47b 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam.c +++ b/drivers/net/bnxt/tf_core/tf_tcam.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -14,6 +14,7 @@ #include "tfp.h" #include "tf_session.h" #include "tf_msg.h" +#include "tf_tcam_mgr_msg.h" struct tf; @@ -23,17 +24,22 @@ tf_tcam_bind(struct tf *tfp, { int rc; int db_rc[TF_DIR_MAX] = { 0 }; - int i, d; + int d, t; struct tf_rm_alloc_info info; struct tf_rm_free_db_parms fparms; struct tf_rm_create_db_parms db_cfg; + struct tf_tcam_resources local_tcam_cnt[TF_DIR_MAX]; struct tf_tcam_resources *tcam_cnt; struct tf_rm_get_alloc_info_parms ainfo; - uint16_t num_slices = parms->wc_num_slices; + uint16_t num_slices = 1; struct tf_session *tfs; struct tf_dev_info *dev; struct tcam_rm_db *tcam_db; struct tfp_calloc_parms cparms; + struct tf_resource_info resv_res[TF_DIR_MAX][TF_TCAM_TBL_TYPE_MAX]; + uint32_t rx_supported; + uint32_t tx_supported; + bool no_req = true; TF_CHECK_PARMS2(tfp, parms); @@ -47,7 +53,7 @@ tf_tcam_bind(struct tf *tfp, if (rc) return rc; - if (dev->ops->tf_dev_set_tcam_slice_info == NULL) { + if (dev->ops->tf_dev_get_tcam_slice_info == NULL) { rc = -EOPNOTSUPP; TFP_DRV_LOG(ERR, "Operation not supported, rc:%s\n", @@ -55,18 +61,28 @@ tf_tcam_bind(struct tf *tfp, return rc; } - rc = dev->ops->tf_dev_set_tcam_slice_info(tfp, - num_slices); + tcam_cnt = parms->resources->tcam_cnt; + + for (d = 0; d < TF_DIR_MAX; d++) { + for (t = 0; t < TF_TCAM_TBL_TYPE_MAX; t++) { + rc = dev->ops->tf_dev_get_tcam_slice_info(tfp, t, 0, + &num_slices); if (rc) return rc; - tcam_cnt = parms->resources->tcam_cnt; - if ((tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] % num_slices) || - (tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] % num_slices)) { - TFP_DRV_LOG(ERR, - "Requested num of WC TCAM entries has to be multiple %d\n", - num_slices); - return -EINVAL; + if (num_slices == 1) + continue; + + if (tcam_cnt[d].cnt[t] % num_slices) { + TFP_DRV_LOG(ERR, + "%s: Requested num of %s entries " + "has to be multiple of %d\n", + tf_dir_2_str(d), + tf_tcam_tbl_2_str(t), + num_slices); + return -EINVAL; + } + } } memset(&db_cfg, 0, sizeof(db_cfg)); @@ -80,8 +96,8 @@ tf_tcam_bind(struct tf *tfp, } tcam_db = cparms.mem_va; - for (i = 0; i < TF_DIR_MAX; i++) - tcam_db->tcam_db[i] = NULL; + for (d = 0; d < TF_DIR_MAX; d++) + tcam_db->tcam_db[d] = NULL; tf_session_set_db(tfp, TF_MODULE_TYPE_TCAM, tcam_db); db_cfg.module = TF_MODULE_TYPE_TCAM; @@ -90,7 +106,7 @@ tf_tcam_bind(struct tf *tfp, for (d = 0; d < TF_DIR_MAX; d++) { db_cfg.dir = d; - db_cfg.alloc_cnt = parms->resources->tcam_cnt[d].cnt; + db_cfg.alloc_cnt = tcam_cnt[d].cnt; db_cfg.rm_db = (void *)&tcam_db->tcam_db[d]; if (tf_session_is_shared_session(tfs) && (!tf_session_is_shared_session_creator(tfs))) @@ -98,53 +114,112 @@ tf_tcam_bind(struct tf *tfp, else db_rc[d] = tf_rm_create_db(tfp, &db_cfg); } - /* No db created */ if (db_rc[TF_DIR_RX] && db_rc[TF_DIR_TX]) { TFP_DRV_LOG(ERR, "No TCAM DB created\n"); return db_rc[TF_DIR_RX]; } - /* check if reserved resource for WC is multiple of num_slices */ + /* Collect info on which entries were reserved. */ for (d = 0; d < TF_DIR_MAX; d++) { - if (!tcam_db->tcam_db[d]) - continue; + for (t = 0; t < TF_TCAM_TBL_TYPE_MAX; t++) { + memset(&info, 0, sizeof(info)); + if (tcam_cnt[d].cnt[t] == 0) { + resv_res[d][t].start = 0; + resv_res[d][t].stride = 0; + continue; + } + ainfo.rm_db = tcam_db->tcam_db[d]; + ainfo.subtype = t; + ainfo.info = &info; + rc = tf_rm_get_info(&ainfo); + if (rc) + goto error; + + rc = dev->ops->tf_dev_get_tcam_slice_info(tfp, t, 0, + &num_slices); + if (rc) + return rc; + + if (num_slices > 1) { + /* check if reserved resource for is multiple of + * num_slices + */ + if (info.entry.start % num_slices != 0 || + info.entry.stride % num_slices != 0) { + TFP_DRV_LOG(ERR, + "%s: %s reserved resource" + " is not multiple of %d\n", + tf_dir_2_str(d), + tf_tcam_tbl_2_str(t), + num_slices); + rc = -EINVAL; + goto error; + } + } + + resv_res[d][t].start = info.entry.start; + resv_res[d][t].stride = info.entry.stride; + } + } - memset(&info, 0, sizeof(info)); - ainfo.rm_db = tcam_db->tcam_db[d]; - ainfo.subtype = TF_TCAM_TBL_TYPE_WC_TCAM; - ainfo.info = &info; - rc = tf_rm_get_info(&ainfo); - if (rc) - goto error; - - if (info.entry.start % num_slices != 0 || - info.entry.stride % num_slices != 0) { - TFP_DRV_LOG(ERR, - "%s: TCAM reserved resource is not multiple of %d\n", - tf_dir_2_str(d), - num_slices); - rc = -EINVAL; - goto error; + rc = tf_tcam_mgr_bind_msg(tfp, dev, parms, resv_res); + if (rc) + return rc; + + rc = tf_tcam_mgr_qcaps_msg(tfp, dev, + &rx_supported, &tx_supported); + if (rc) + return rc; + + for (t = 0; t < TF_TCAM_TBL_TYPE_MAX; t++) { + if (rx_supported & 1 << t) + tfs->tcam_mgr_control[TF_DIR_RX][t] = 1; + if (tx_supported & 1 << t) + tfs->tcam_mgr_control[TF_DIR_TX][t] = 1; + } + + /* + * Make a local copy of tcam_cnt with only resources not managed by TCAM + * Manager requested. + */ + memcpy(&local_tcam_cnt, tcam_cnt, sizeof(local_tcam_cnt)); + tcam_cnt = local_tcam_cnt; + for (d = 0; d < TF_DIR_MAX; d++) { + for (t = 0; t < TF_TCAM_TBL_TYPE_MAX; t++) { + /* If controlled by TCAM Manager */ + if (tfs->tcam_mgr_control[d][t]) + tcam_cnt[d].cnt[t] = 0; + else if (tcam_cnt[d].cnt[t] > 0) + no_req = false; } } - /* Initialize the TCAM manager. */ + /* If no resources left to request */ + if (no_req) + goto finished; + +finished: TFP_DRV_LOG(INFO, "TCAM - initialized\n"); return 0; error: - for (i = 0; i < TF_DIR_MAX; i++) { - memset(&fparms, 0, sizeof(fparms)); - fparms.dir = i; - fparms.rm_db = tcam_db->tcam_db[i]; - /* Ignoring return here since we are in the error case */ - (void)tf_rm_free_db(tfp, &fparms); - tcam_db->tcam_db[i] = NULL; + for (d = 0; d < TF_DIR_MAX; d++) { + if (tcam_db->tcam_db[d] != NULL) { + memset(&fparms, 0, sizeof(fparms)); + fparms.dir = d; + fparms.rm_db = tcam_db->tcam_db[d]; + /* + * Ignoring return here since we are in the error case + */ + (void)tf_rm_free_db(tfp, &fparms); + + tcam_db->tcam_db[d] = NULL; + } + tcam_db->tcam_db[d] = NULL; tf_session_set_db(tfp, TF_MODULE_TYPE_TCAM, NULL); } - return rc; } @@ -156,27 +231,43 @@ tf_tcam_unbind(struct tf *tfp) struct tf_rm_free_db_parms fparms; struct tcam_rm_db *tcam_db; void *tcam_db_ptr = NULL; + struct tf_session *tfs; + struct tf_dev_info *dev; TF_CHECK_PARMS1(tfp); + /* Retrieve the session information */ + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) + return rc; rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr); - if (rc) { + if (rc) return 0; - } + tcam_db = (struct tcam_rm_db *)tcam_db_ptr; for (i = 0; i < TF_DIR_MAX; i++) { - if (tcam_db->tcam_db[i] == NULL) - continue; - memset(&fparms, 0, sizeof(fparms)); - fparms.dir = i; - fparms.rm_db = tcam_db->tcam_db[i]; - rc = tf_rm_free_db(tfp, &fparms); - if (rc) - return rc; + if (tcam_db->tcam_db[i] != NULL) { + memset(&fparms, 0, sizeof(fparms)); + fparms.dir = i; + fparms.rm_db = tcam_db->tcam_db[i]; + rc = tf_rm_free_db(tfp, &fparms); + if (rc) + return rc; + + tcam_db->tcam_db[i] = NULL; + } - tcam_db->tcam_db[i] = NULL; } + rc = tf_tcam_mgr_unbind_msg(tfp, dev); + if (rc) + return rc; + return 0; } @@ -222,6 +313,9 @@ tf_tcam_alloc(struct tf *tfp, if (rc) return rc; + /* If TCAM controlled by TCAM Manager */ + if (tfs->tcam_mgr_control[parms->dir][parms->type]) + return tf_tcam_mgr_alloc_msg(tfp, dev, parms); rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr); if (rc) { TFP_DRV_LOG(ERR, @@ -251,12 +345,8 @@ tf_tcam_alloc(struct tf *tfp, } /* return the start index of each row */ - if (parms->priority == 0) { if (i == 0) parms->idx = index; - } else { - parms->idx = index; - } } return 0; @@ -307,6 +397,14 @@ tf_tcam_free(struct tf *tfp, if (rc) return rc; + /* If TCAM controlled by TCAM Manager */ + if (tfs->tcam_mgr_control[parms->dir][parms->type]) + /* + * If a session can have multiple references to an entry, check + * the reference count here before actually freeing the entry. + */ + return tf_tcam_mgr_free_msg(tfp, dev, parms); + if (parms->idx % num_slices) { TFP_DRV_LOG(ERR, "%s: TCAM reserved resource is not multiple of %d\n", @@ -429,6 +527,10 @@ tf_tcam_set(struct tf *tfp __rte_unused, if (rc) return rc; + /* If TCAM controlled by TCAM Manager */ + if (tfs->tcam_mgr_control[parms->dir][parms->type]) + return tf_tcam_mgr_set_msg(tfp, dev, parms); + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr); if (rc) { TFP_DRV_LOG(ERR, @@ -508,6 +610,10 @@ tf_tcam_get(struct tf *tfp __rte_unused, if (rc) return rc; + /* If TCAM controlled by TCAM Manager */ + if (tfs->tcam_mgr_control[parms->dir][parms->type]) + return tf_tcam_mgr_get_msg(tfp, dev, parms); + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr); if (rc) { TFP_DRV_LOG(ERR, diff --git a/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c b/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c new file mode 100644 index 0000000000..c535f4f4f6 --- /dev/null +++ b/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c @@ -0,0 +1,286 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2021-2023 Broadcom + * All rights reserved. + */ + +#include + +#include "tfp.h" +#include "tf_tcam.h" +#include "cfa_tcam_mgr.h" +#include "tf_tcam_mgr_msg.h" + +/* + * Table to convert TCAM type to logical TCAM type for applications. + * Index is tf_tcam_tbl_type. + */ +static enum cfa_tcam_mgr_tbl_type tcam_types[TF_TCAM_TBL_TYPE_MAX] = { + [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = + CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS, + [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = + CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS, + [TF_TCAM_TBL_TYPE_PROF_TCAM] = + CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS, + [TF_TCAM_TBL_TYPE_WC_TCAM] = + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS, + [TF_TCAM_TBL_TYPE_SP_TCAM] = + CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS, + [TF_TCAM_TBL_TYPE_CT_RULE_TCAM] = + CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS, + [TF_TCAM_TBL_TYPE_VEB_TCAM] = + CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS, + [TF_TCAM_TBL_TYPE_WC_TCAM_HIGH] = + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS, + [TF_TCAM_TBL_TYPE_WC_TCAM_LOW] = + CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS, +}; + +static uint16_t hcapi_type[TF_TCAM_TBL_TYPE_MAX]; + +/* + * This is the glue between the core tf_tcam and the TCAM manager. It is + * intended to abstract out the location of the TCAM manager so that the core + * code will be the same if the TCAM manager is in the core or in firmware. + * + * If the TCAM manager is in the core, then this file will just translate to + * TCAM manager APIs. If TCAM manager is in firmware, then this file will cause + * messages to be sent (except for bind and unbind). + */ + +int +tf_tcam_mgr_qcaps_msg(struct tf *tfp, + struct tf_dev_info *dev __rte_unused, + uint32_t *rx_tcam_supported, + uint32_t *tx_tcam_supported) +{ + struct cfa_tcam_mgr_context context; + struct cfa_tcam_mgr_qcaps_parms mgr_parms; + int rc; + + context.tfp = tfp; + memset(&mgr_parms, 0, sizeof(mgr_parms)); + rc = cfa_tcam_mgr_qcaps(&context, &mgr_parms); + if (rc >= 0) { + *rx_tcam_supported = mgr_parms.rx_tcam_supported; + *tx_tcam_supported = mgr_parms.tx_tcam_supported; + } + return rc; +} + +int +tf_tcam_mgr_bind_msg(struct tf *tfp, + struct tf_dev_info *dev __rte_unused, + struct tf_tcam_cfg_parms *parms, + struct tf_resource_info resv_res[][TF_TCAM_TBL_TYPE_MAX] + __rte_unused + ) +{ + /* Common Code */ + int type; + + if (parms->num_elements != TF_TCAM_TBL_TYPE_MAX) { + TFP_DRV_LOG(ERR, + "Invalid number of elements in bind request.\n"); + TFP_DRV_LOG(ERR, + "Expected %d, received %d.\n", + TF_TCAM_TBL_TYPE_MAX, + parms->num_elements); + return -EINVAL; + } + + for (type = 0; type < TF_TCAM_TBL_TYPE_MAX; type++) + hcapi_type[type] = parms->cfg[type].hcapi_type; + + struct cfa_tcam_mgr_context context; + struct cfa_tcam_mgr_cfg_parms mgr_parms; + struct tf_rm_resc_entry + mgr_resv_res[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX]; + int dir, rc; + + context.tfp = tfp; + + memset(&mgr_parms, 0, sizeof(mgr_parms)); + + mgr_parms.num_elements = CFA_TCAM_MGR_TBL_TYPE_MAX; + + /* Convert the data to logical tables */ + for (dir = 0; dir < TF_DIR_MAX; dir++) { + for (type = 0; type < TF_TCAM_TBL_TYPE_MAX; type++) { + mgr_parms.tcam_cnt[dir][tcam_types[type]] = + parms->resources->tcam_cnt[dir].cnt[type]; + mgr_resv_res[dir][tcam_types[type]].start = + resv_res[dir][type].start; + mgr_resv_res[dir][tcam_types[type]].stride = + resv_res[dir][type].stride; + } + } + mgr_parms.resv_res = mgr_resv_res; + + rc = cfa_tcam_mgr_bind(&context, &mgr_parms); + + return rc; +} + +int +tf_tcam_mgr_unbind_msg(struct tf *tfp, + struct tf_dev_info *dev __rte_unused) +{ + struct cfa_tcam_mgr_context context; + + context.tfp = tfp; + + return cfa_tcam_mgr_unbind(&context); +} + +int +tf_tcam_mgr_alloc_msg(struct tf *tfp, + struct tf_dev_info *dev __rte_unused, + struct tf_tcam_alloc_parms *parms) +{ + struct cfa_tcam_mgr_context context; + struct cfa_tcam_mgr_alloc_parms mgr_parms; + int rc; + + if (parms->type >= TF_TCAM_TBL_TYPE_MAX) { + TFP_DRV_LOG(ERR, + "No such TCAM table %d.\n", + parms->type); + return -EINVAL; + } + + context.tfp = tfp; + + mgr_parms.dir = parms->dir; + mgr_parms.type = tcam_types[parms->type]; + mgr_parms.hcapi_type = hcapi_type[parms->type]; + mgr_parms.key_size = parms->key_size; + if (parms->priority > TF_TCAM_PRIORITY_MAX) + mgr_parms.priority = 0; + else + mgr_parms.priority = TF_TCAM_PRIORITY_MAX - parms->priority - 1; + + rc = cfa_tcam_mgr_alloc(&context, &mgr_parms); + if (rc) + return rc; + + parms->idx = mgr_parms.id; + return 0; +} + +int +tf_tcam_mgr_free_msg(struct tf *tfp, + struct tf_dev_info *dev __rte_unused, + struct tf_tcam_free_parms *parms) +{ + struct cfa_tcam_mgr_context context; + struct cfa_tcam_mgr_free_parms mgr_parms; + + if (parms->type >= TF_TCAM_TBL_TYPE_MAX) { + TFP_DRV_LOG(ERR, + "No such TCAM table %d.\n", + parms->type); + return -EINVAL; + } + + context.tfp = tfp; + mgr_parms.dir = parms->dir; + mgr_parms.type = tcam_types[parms->type]; + mgr_parms.hcapi_type = hcapi_type[parms->type]; + mgr_parms.id = parms->idx; + + return cfa_tcam_mgr_free(&context, &mgr_parms); +} + +int +tf_tcam_mgr_set_msg(struct tf *tfp, + struct tf_dev_info *dev __rte_unused, + struct tf_tcam_set_parms *parms) +{ + struct cfa_tcam_mgr_context context; + struct cfa_tcam_mgr_set_parms mgr_parms; + + if (parms->type >= TF_TCAM_TBL_TYPE_MAX) { + TFP_DRV_LOG(ERR, + "No such TCAM table %d.\n", + parms->type); + return -EINVAL; + } + + context.tfp = tfp; + mgr_parms.dir = parms->dir; + mgr_parms.type = tcam_types[parms->type]; + mgr_parms.hcapi_type = hcapi_type[parms->type]; + mgr_parms.id = parms->idx; + mgr_parms.key = parms->key; + mgr_parms.mask = parms->mask; + mgr_parms.key_size = parms->key_size; + mgr_parms.result = parms->result; + mgr_parms.result_size = parms->result_size; + + return cfa_tcam_mgr_set(&context, &mgr_parms); +} + +int +tf_tcam_mgr_get_msg(struct tf *tfp, + struct tf_dev_info *dev __rte_unused, + struct tf_tcam_get_parms *parms) +{ + int rc; + struct cfa_tcam_mgr_context context; + struct cfa_tcam_mgr_get_parms mgr_parms; + + if (parms->type >= TF_TCAM_TBL_TYPE_MAX) { + TFP_DRV_LOG(ERR, + "No such TCAM table %d.\n", + parms->type); + return -EINVAL; + } + + context.tfp = tfp; + mgr_parms.dir = parms->dir; + mgr_parms.type = tcam_types[parms->type]; + mgr_parms.hcapi_type = hcapi_type[parms->type]; + mgr_parms.id = parms->idx; + mgr_parms.key = parms->key; + mgr_parms.mask = parms->mask; + mgr_parms.key_size = parms->key_size; + mgr_parms.result = parms->result; + mgr_parms.result_size = parms->result_size; + + rc = cfa_tcam_mgr_get(&context, &mgr_parms); + if (rc) + return rc; + + parms->key_size = mgr_parms.key_size; + parms->result_size = mgr_parms.result_size; + + return rc; +} + +int +tf_tcam_mgr_shared_clear_msg(struct tf *tfp, + struct tf_clear_tcam_shared_entries_parms *parms) +{ + struct cfa_tcam_mgr_context context; + struct cfa_tcam_mgr_shared_clear_parms mgr_parms; + + context.tfp = tfp; + mgr_parms.dir = parms->dir; + mgr_parms.type = tcam_types[parms->tcam_tbl_type]; + + return cfa_tcam_mgr_shared_clear(&context, &mgr_parms); +} + +int +tf_tcam_mgr_shared_move_msg(struct tf *tfp, + struct tf_move_tcam_shared_entries_parms *parms) +{ + struct cfa_tcam_mgr_context context; + struct cfa_tcam_mgr_shared_move_parms mgr_parms; + + context.tfp = tfp; + mgr_parms.dir = parms->dir; + mgr_parms.type = tcam_types[parms->tcam_tbl_type]; + + return cfa_tcam_mgr_shared_move(&context, &mgr_parms); +} diff --git a/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.h b/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.h new file mode 100644 index 0000000000..8a8d136f5e --- /dev/null +++ b/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2021-2023 Broadcom + * All rights reserved. + */ + +#ifndef _TF_TCAM_MGR_MSG_H_ +#define _TF_TCAM_MGR_MSG_H_ + +#include "tf_tcam.h" +#include "tf_rm.h" + +int +tf_tcam_mgr_qcaps_msg(struct tf *tfp, + struct tf_dev_info *dev __rte_unused, + uint32_t *rx_tcam_supported, + uint32_t *tx_tcam_supported); + +int +tf_tcam_mgr_bind_msg(struct tf *tfp, + struct tf_dev_info *dev, + struct tf_tcam_cfg_parms *parms, + struct tf_resource_info resv_res[][TF_TCAM_TBL_TYPE_MAX]); +int +tf_tcam_mgr_unbind_msg(struct tf *tfp, + struct tf_dev_info *dev); +int +tf_tcam_mgr_alloc_msg(struct tf *tfp, + struct tf_dev_info *dev, + struct tf_tcam_alloc_parms *parms); +int +tf_tcam_mgr_free_msg(struct tf *tfp, + struct tf_dev_info *dev, + struct tf_tcam_free_parms *parms); +int +tf_tcam_mgr_set_msg(struct tf *tfp, + struct tf_dev_info *dev, + struct tf_tcam_set_parms *parms); +int +tf_tcam_mgr_get_msg(struct tf *tfp, + struct tf_dev_info *dev, + struct tf_tcam_get_parms *parms); +int +tf_tcam_mgr_shared_clear_msg(struct tf *tfp, + struct tf_clear_tcam_shared_entries_parms *parms); + +int +tf_tcam_mgr_shared_move_msg(struct tf *tfp, + struct tf_move_tcam_shared_entries_parms *parms); +#endif /* _TF_TCAM_MGR_MSG_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_tcam_shared.c b/drivers/net/bnxt/tf_core/tf_tcam_shared.c index c120c6f577..e853f616f9 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam_shared.c +++ b/drivers/net/bnxt/tf_core/tf_tcam_shared.c @@ -1,11 +1,13 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ #include #include +#include "tf_core.h" + #include "tf_tcam_shared.h" #include "tf_tcam.h" #include "tf_common.h" @@ -16,229 +18,8 @@ #include "tf_session.h" #include "tf_msg.h" #include "bitalloc.h" -#include "tf_core.h" - -/** Shared WC TCAM pool identifiers - */ -enum tf_tcam_shared_wc_pool_id { - TF_TCAM_SHARED_WC_POOL_HI = 0, - TF_TCAM_SHARED_WC_POOL_LO = 1, - TF_TCAM_SHARED_WC_POOL_MAX = 2 -}; - -/** Get string representation of a WC TCAM shared pool id - */ -static const char * -tf_pool_2_str(enum tf_tcam_shared_wc_pool_id id) -{ - switch (id) { - case TF_TCAM_SHARED_WC_POOL_HI: - return "TCAM_SHARED_WC_POOL_HI"; - case TF_TCAM_SHARED_WC_POOL_LO: - return "TCAM_SHARED_WC_POOL_LO"; - default: - return "Invalid TCAM_SHARED_WC_POOL"; - } -} - -/** The WC TCAM shared pool datastructure - */ -struct tf_tcam_shared_wc_pool { - /** Start and stride data */ - struct tf_resource_info info; - /** bitalloc pool */ - struct bitalloc *pool; -}; - -struct tf_tcam_shared_wc_pools { - struct tf_tcam_shared_wc_pool db[TF_DIR_MAX][TF_TCAM_SHARED_WC_POOL_MAX]; -}; - -/** The WC TCAM shared pool declarations - */ -/* struct tf_tcam_shared_wc_pool tcam_shared_wc[TF_DIR_MAX][TF_TCAM_SHARED_WC_POOL_MAX]; */ - -static int -tf_tcam_shared_create_db(struct tf_tcam_shared_wc_pools **db) -{ - struct tfp_calloc_parms cparms; - int rc = 0; - - cparms.nitems = 1; - cparms.alignment = 0; - cparms.size = sizeof(struct tf_tcam_shared_wc_pools); - rc = tfp_calloc(&cparms); - if (rc) { - TFP_DRV_LOG(ERR, - "TCAM shared db allocation failed (%s)\n", - strerror(-rc)); - return rc; - } - *db = cparms.mem_va; - - return rc; -} - -/** Create a WC TCAM shared pool - */ -static int -tf_tcam_shared_create_wc_pool(int dir, - enum tf_tcam_shared_wc_pool_id id, - int start, - int stride, - struct tf_tcam_shared_wc_pools *tcam_shared_wc) -{ - int rc = 0; - bool free = true; - struct tfp_calloc_parms cparms; - uint32_t pool_size; - - /* Create pool */ - pool_size = (BITALLOC_SIZEOF(stride) / sizeof(struct bitalloc)); - cparms.nitems = pool_size; - cparms.alignment = 0; - cparms.size = sizeof(struct bitalloc); - rc = tfp_calloc(&cparms); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: pool memory alloc failed %s:%s\n", - tf_dir_2_str(dir), tf_pool_2_str(id), - strerror(-rc)); - return rc; - } - tcam_shared_wc->db[dir][id].pool = (struct bitalloc *)cparms.mem_va; - - rc = ba_init(tcam_shared_wc->db[dir][id].pool, - stride, - free); - - if (rc) { - TFP_DRV_LOG(ERR, - "%s: pool bitalloc failed %s\n", - tf_dir_2_str(dir), tf_pool_2_str(id)); - return rc; - } - - tcam_shared_wc->db[dir][id].info.start = start; - tcam_shared_wc->db[dir][id].info.stride = stride; - - return rc; -} -/** Free a WC TCAM shared pool - */ -static int -tf_tcam_shared_free_wc_pool(int dir, - enum tf_tcam_shared_wc_pool_id id, - struct tf_tcam_shared_wc_pools *tcam_shared_wc) -{ - int rc = 0; - TF_CHECK_PARMS1(tcam_shared_wc); - - tcam_shared_wc->db[dir][id].info.start = 0; - tcam_shared_wc->db[dir][id].info.stride = 0; - - if (tcam_shared_wc->db[dir][id].pool) - tfp_free((void *)tcam_shared_wc->db[dir][id].pool); - return rc; -} - -/** Get the number of WC TCAM slices allocated during 1 allocation/free - */ -static int -tf_tcam_shared_get_slices(struct tf *tfp, - struct tf_dev_info *dev, - uint16_t *num_slices) -{ - int rc; - - if (dev->ops->tf_dev_get_tcam_slice_info == NULL) { - rc = -EOPNOTSUPP; - TFP_DRV_LOG(ERR, - "Operation not supported, rc:%s\n", strerror(-rc)); - return rc; - } - rc = dev->ops->tf_dev_get_tcam_slice_info(tfp, - TF_TCAM_TBL_TYPE_WC_TCAM, - 0, - num_slices); - return rc; -} - -static bool -tf_tcam_db_valid(struct tf *tfp, - enum tf_dir dir) -{ - struct tcam_rm_db *tcam_db; - void *tcam_db_ptr = NULL; - int rc; - - TF_CHECK_PARMS1(tfp); - - rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr); - if (rc) - return false; - - tcam_db = (struct tcam_rm_db *)tcam_db_ptr; - - if (tcam_db->tcam_db[dir]) - return true; - - return false; -} - -static int -tf_tcam_shared_get_rm_info(struct tf *tfp, - enum tf_dir dir, - uint16_t *hcapi_type, - struct tf_rm_alloc_info *info) -{ - int rc; - struct tcam_rm_db *tcam_db; - void *tcam_db_ptr = NULL; - struct tf_rm_get_alloc_info_parms ainfo; - struct tf_rm_get_hcapi_parms hparms; - - TF_CHECK_PARMS3(tfp, hcapi_type, info); - - rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr); - if (rc) { - TFP_DRV_LOG(INFO, - "Tcam_db is not initialized, rc:%s\n", - strerror(-rc)); - return 0; - } - tcam_db = (struct tcam_rm_db *)tcam_db_ptr; - - /* Convert TF type to HCAPI RM type */ - memset(&hparms, 0, sizeof(hparms)); - hparms.rm_db = tcam_db->tcam_db[dir]; - hparms.subtype = TF_TCAM_TBL_TYPE_WC_TCAM; - hparms.hcapi_type = hcapi_type; - - rc = tf_rm_get_hcapi_type(&hparms); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Get RM hcapi type failed %s\n", - tf_dir_2_str(dir), - strerror(-rc)); - return rc; - } - - memset(info, 0, sizeof(struct tf_rm_alloc_info)); - ainfo.rm_db = tcam_db->tcam_db[dir]; - ainfo.subtype = TF_TCAM_TBL_TYPE_WC_TCAM; - ainfo.info = info; - - rc = tf_rm_get_info(&ainfo); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: TCAM rm info get failed %s\n", - tf_dir_2_str(dir), - strerror(-rc)); - return rc; - } - return rc; -} +#include "tf_rm.h" +#include "tf_tcam_mgr_msg.h" /** * tf_tcam_shared_bind @@ -247,92 +28,15 @@ int tf_tcam_shared_bind(struct tf *tfp, struct tf_tcam_cfg_parms *parms) { - int rc, dir; - struct tf_session *tfs; - struct tf_dev_info *dev; - struct tf_rm_alloc_info info; - uint16_t start, stride; - uint16_t num_slices; - uint16_t hcapi_type; - struct tf_tcam_shared_wc_pools *tcam_shared_wc = NULL; + int rc; TF_CHECK_PARMS2(tfp, parms); /* Perform normal bind */ rc = tf_tcam_bind(tfp, parms); - if (rc) - return rc; - - /* After the normal TCAM bind, if this is a shared session - * create all required databases for the WC_HI and WC_LO pools - */ - rc = tf_session_get_session_internal(tfp, &tfs); - if (rc) { - TFP_DRV_LOG(ERR, - "Session access failure: %s\n", strerror(-rc)); - return rc; - } - if (tf_session_is_shared_session(tfs)) { - /* Retrieve the device information */ - rc = tf_session_get_device(tfs, &dev); - if (rc) - return rc; - - tf_tcam_shared_create_db(&tcam_shared_wc); - - - /* If there are WC TCAM entries, create 2 pools each with 1/2 - * the total number of entries - */ - for (dir = 0; dir < TF_DIR_MAX; dir++) { - if (!tf_tcam_db_valid(tfp, dir)) - continue; - - rc = tf_tcam_shared_get_rm_info(tfp, - dir, - &hcapi_type, - &info); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: TCAM rm info get failed\n", - tf_dir_2_str(dir)); - goto done; - } - - start = info.entry.start; - stride = info.entry.stride / 2; - - tf_tcam_shared_create_wc_pool(dir, - TF_TCAM_SHARED_WC_POOL_HI, - start, - stride, - tcam_shared_wc); - - start += stride; - tf_tcam_shared_create_wc_pool(dir, - TF_TCAM_SHARED_WC_POOL_LO, - start, - stride, - tcam_shared_wc); - - tf_session_set_tcam_shared_db(tfp, (void *)tcam_shared_wc); - } - - rc = tf_tcam_shared_get_slices(tfp, - dev, - &num_slices); - if (rc) - return rc; - - if (num_slices > 1) { - TFP_DRV_LOG(ERR, - "Only single slice supported\n"); - return -EOPNOTSUPP; - } - } -done: return rc; + } /** * tf_tcam_shared_unbind @@ -340,132 +44,10 @@ tf_tcam_shared_bind(struct tf *tfp, int tf_tcam_shared_unbind(struct tf *tfp) { - int rc, dir; - struct tf_dev_info *dev; - struct tf_session *tfs; - void *tcam_shared_db_ptr = NULL; - struct tf_tcam_shared_wc_pools *tcam_shared_wc; - enum tf_tcam_shared_wc_pool_id pool_id; - struct tf_tcam_free_parms parms; - struct bitalloc *pool; - uint16_t start; - int log_idx, phy_idx; - uint16_t hcapi_type; - struct tf_rm_alloc_info info; - int i, pool_cnt; + int rc; TF_CHECK_PARMS1(tfp); - /* Retrieve the session information */ - rc = tf_session_get_session_internal(tfp, &tfs); - if (rc) - return rc; - - /* If not the shared session, call the normal - * tcam unbind and exit - */ - if (!tf_session_is_shared_session(tfs)) { - rc = tf_tcam_unbind(tfp); - return rc; - } - - /* We must be a shared session, get the database - */ - rc = tf_session_get_tcam_shared_db(tfp, - (void *)&tcam_shared_db_ptr); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to get tcam_shared_db, rc:%s\n", - strerror(-rc)); - return rc; - } - - tcam_shared_wc = - (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr; - - - /* Get the device - */ - rc = tf_session_get_device(tfs, &dev); - if (rc) - return rc; - - - /* If there are WC TCAM entries allocated, free them - */ - for (dir = 0; dir < TF_DIR_MAX; dir++) { - /* If the database is invalid, skip - */ - if (!tf_tcam_db_valid(tfp, dir)) - continue; - - rc = tf_tcam_shared_get_rm_info(tfp, - dir, - &hcapi_type, - &info); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: TCAM shared rm info get failed\n", - tf_dir_2_str(dir)); - return rc; - } - - for (pool_id = TF_TCAM_SHARED_WC_POOL_HI; - pool_id < TF_TCAM_SHARED_WC_POOL_MAX; - pool_id++) { - pool = tcam_shared_wc->db[dir][pool_id].pool; - start = tcam_shared_wc->db[dir][pool_id].info.start; - pool_cnt = ba_inuse_count(pool); - - if (pool_cnt) { - TFP_DRV_LOG(INFO, - "%s: %s: %d residuals found, freeing\n", - tf_dir_2_str(dir), - tf_pool_2_str(pool_id), - pool_cnt); - } - - log_idx = 0; - - for (i = 0; i < pool_cnt; i++) { - log_idx = ba_find_next_inuse(pool, log_idx); - - if (log_idx < 0) { - TFP_DRV_LOG(ERR, - "Expected a found %s entry %d\n", - tf_pool_2_str(pool_id), - i); - /* attempt normal unbind - */ - goto done; - } - phy_idx = start + log_idx; - - parms.type = TF_TCAM_TBL_TYPE_WC_TCAM; - parms.hcapi_type = hcapi_type; - parms.idx = phy_idx; - parms.dir = dir; - rc = tf_msg_tcam_entry_free(tfp, dev, &parms); - if (rc) { - /* Log error */ - TFP_DRV_LOG(ERR, - "%s: %s: %d free failed, rc:%s\n", - tf_dir_2_str(parms.dir), - tf_tcam_tbl_2_str(parms.type), - phy_idx, - strerror(-rc)); - return rc; - } - } - /* Free the pool once all the entries - * have been cleared - */ - tf_tcam_shared_free_wc_pool(dir, - pool_id, - tcam_shared_wc); - } - } -done: rc = tf_tcam_unbind(tfp); return rc; } @@ -478,79 +60,11 @@ tf_tcam_shared_alloc(struct tf *tfp, struct tf_tcam_alloc_parms *parms) { int rc; - struct tf_session *tfs; - struct tf_dev_info *dev; - int log_idx; - struct bitalloc *pool; - enum tf_tcam_shared_wc_pool_id id; - struct tf_tcam_shared_wc_pools *tcam_shared_wc; - void *tcam_shared_db_ptr = NULL; TF_CHECK_PARMS2(tfp, parms); - /* Retrieve the session information */ - rc = tf_session_get_session_internal(tfp, &tfs); - if (rc) - return rc; - - /* If we aren't the shared session or the type is - * not one of the special WC TCAM types, call the normal - * allocation. - */ - if (!tf_session_is_shared_session(tfs) || - (parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_HIGH && - parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_LOW)) { - /* Perform normal alloc - */ - rc = tf_tcam_alloc(tfp, parms); - return rc; - } - - if (!tf_tcam_db_valid(tfp, parms->dir)) { - TFP_DRV_LOG(ERR, - "%s: tcam shared pool doesn't exist\n", - tf_dir_2_str(parms->dir)); - return -ENOMEM; - } - - rc = tf_session_get_tcam_shared_db(tfp, (void *)&tcam_shared_db_ptr); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to get tcam_shared_db from session, rc:%s\n", - strerror(-rc)); - return rc; - } - tcam_shared_wc = (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr; - - if (parms->type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH) - id = TF_TCAM_SHARED_WC_POOL_HI; - else - id = TF_TCAM_SHARED_WC_POOL_LO; - - /* Retrieve the device information */ - rc = tf_session_get_device(tfs, &dev); - if (rc) - return rc; - - pool = tcam_shared_wc->db[parms->dir][id].pool; - - /* - * priority 0: allocate from top of the tcam i.e. high - * priority !0: allocate index from bottom i.e lowest - */ - if (parms->priority) - log_idx = ba_alloc_reverse(pool); - else - log_idx = ba_alloc(pool); - if (log_idx == BA_FAIL) { - TFP_DRV_LOG(ERR, - "%s: Allocation failed, rc:%s\n", - tf_dir_2_str(parms->dir), - strerror(ENOMEM)); - return -ENOMEM; - } - parms->idx = log_idx; - return 0; + rc = tf_tcam_alloc(tfp, parms); + return rc; } int @@ -558,118 +72,11 @@ tf_tcam_shared_free(struct tf *tfp, struct tf_tcam_free_parms *parms) { int rc; - struct tf_session *tfs; - struct tf_dev_info *dev; - int allocated = 0; - uint16_t start; - int phy_idx; - struct bitalloc *pool; - enum tf_tcam_shared_wc_pool_id id; - struct tf_tcam_free_parms nparms; - uint16_t hcapi_type; - struct tf_rm_alloc_info info; - void *tcam_shared_db_ptr = NULL; - struct tf_tcam_shared_wc_pools *tcam_shared_wc; TF_CHECK_PARMS2(tfp, parms); - /* Retrieve the session information */ - rc = tf_session_get_session_internal(tfp, &tfs); - if (rc) - return rc; - - /* If we aren't the shared session or the type is - * not one of the special WC TCAM types, call the normal - * allocation. - */ - if (!tf_session_is_shared_session(tfs) || - (parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_HIGH && - parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_LOW)) { - /* Perform normal free - */ - rc = tf_tcam_free(tfp, parms); - return rc; - } - - if (!tf_tcam_db_valid(tfp, parms->dir)) { - TFP_DRV_LOG(ERR, - "%s: tcam shared pool doesn't exist\n", - tf_dir_2_str(parms->dir)); - return -ENOMEM; - } - - rc = tf_session_get_tcam_shared_db(tfp, (void *)&tcam_shared_db_ptr); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to get tcam_shared_db from session, rc:%s\n", - strerror(-rc)); - return rc; - } - tcam_shared_wc = (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr; - - - if (parms->type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH) - id = TF_TCAM_SHARED_WC_POOL_HI; - else - id = TF_TCAM_SHARED_WC_POOL_LO; - - /* Retrieve the device information */ - rc = tf_session_get_device(tfs, &dev); - if (rc) - return rc; - - rc = tf_tcam_shared_get_rm_info(tfp, - parms->dir, - &hcapi_type, - &info); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: TCAM rm info get failed\n", - tf_dir_2_str(parms->dir)); - return rc; - } - - pool = tcam_shared_wc->db[parms->dir][id].pool; - start = tcam_shared_wc->db[parms->dir][id].info.start; - - phy_idx = parms->idx + start; - allocated = ba_inuse(pool, parms->idx); - - if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { - TFP_DRV_LOG(ERR, - "%s: Entry already free, type:%d, idx:%d\n", - tf_dir_2_str(parms->dir), parms->type, parms->idx); - return -EINVAL; - } - - rc = ba_free(pool, parms->idx); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Free failed, type:%s, idx:%d\n", - tf_dir_2_str(parms->dir), - tf_tcam_tbl_2_str(parms->type), - parms->idx); - return rc; - } - - /* Override HI/LO type with parent WC TCAM type */ - nparms = *parms; - nparms.type = TF_TCAM_TBL_TYPE_WC_TCAM; - nparms.hcapi_type = hcapi_type; - nparms.idx = phy_idx; - - rc = tf_msg_tcam_entry_free(tfp, dev, &nparms); - if (rc) { - /* Log error */ - TFP_DRV_LOG(ERR, - "%s: %s: log%d free failed, rc:%s\n", - tf_dir_2_str(nparms.dir), - tf_tcam_tbl_2_str(nparms.type), - phy_idx, - strerror(-rc)); - return rc; - } - return 0; + rc = tf_tcam_free(tfp, parms); + return rc; } int @@ -677,109 +84,11 @@ tf_tcam_shared_set(struct tf *tfp __rte_unused, struct tf_tcam_set_parms *parms __rte_unused) { int rc; - struct tf_session *tfs; - struct tf_dev_info *dev; - int allocated = 0; - int phy_idx, log_idx; - struct tf_tcam_set_parms nparms; - struct bitalloc *pool; - uint16_t start; - enum tf_tcam_shared_wc_pool_id id; - uint16_t hcapi_type; - struct tf_rm_alloc_info info; - struct tf_tcam_shared_wc_pools *tcam_shared_wc; - void *tcam_shared_db_ptr = NULL; - TF_CHECK_PARMS2(tfp, parms); - /* Retrieve the session information */ - rc = tf_session_get_session_internal(tfp, &tfs); - if (rc) - return rc; - - /* If we aren't the shared session or one of our - * special types - */ - if (!tf_session_is_shared_session(tfs) || - (parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_HIGH && - parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_LOW)) { - /* Perform normal set and exit - */ - rc = tf_tcam_set(tfp, parms); - return rc; - } - - if (!tf_tcam_db_valid(tfp, parms->dir)) { - TFP_DRV_LOG(ERR, - "%s: tcam shared pool doesn't exist\n", - tf_dir_2_str(parms->dir)); - return -ENOMEM; - } - - /* Retrieve the device information */ - rc = tf_session_get_device(tfs, &dev); - if (rc) - return rc; - - if (parms->type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH) - id = TF_TCAM_SHARED_WC_POOL_HI; - else - id = TF_TCAM_SHARED_WC_POOL_LO; - - rc = tf_session_get_tcam_shared_db(tfp, (void *)&tcam_shared_db_ptr); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to get tcam_shared_db from session, rc:%s\n", - strerror(-rc)); - return rc; - } - tcam_shared_wc = (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr; - - pool = tcam_shared_wc->db[parms->dir][id].pool; - start = tcam_shared_wc->db[parms->dir][id].info.start; - - log_idx = parms->idx; - phy_idx = parms->idx + start; - allocated = ba_inuse(pool, parms->idx); - - if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { - TFP_DRV_LOG(ERR, - "%s: Entry is not allocated, type:%d, logid:%d\n", - tf_dir_2_str(parms->dir), parms->type, log_idx); - return -EINVAL; - } - - rc = tf_tcam_shared_get_rm_info(tfp, - parms->dir, - &hcapi_type, - &info); - if (rc) - return rc; - - /* Override HI/LO type with parent WC TCAM type */ - nparms.hcapi_type = hcapi_type; - nparms.dir = parms->dir; - nparms.type = TF_TCAM_TBL_TYPE_WC_TCAM; - nparms.idx = phy_idx; - nparms.key = parms->key; - nparms.mask = parms->mask; - nparms.key_size = parms->key_size; - nparms.result = parms->result; - nparms.result_size = parms->result_size; - - rc = tf_msg_tcam_entry_set(tfp, dev, &nparms); - if (rc) { - /* Log error */ - TFP_DRV_LOG(ERR, - "%s: %s: phy entry %d set failed, rc:%s", - tf_dir_2_str(parms->dir), - tf_tcam_tbl_2_str(nparms.type), - phy_idx, - strerror(-rc)); - return rc; - } - return 0; + rc = tf_tcam_set(tfp, parms); + return rc; } int @@ -787,226 +96,10 @@ tf_tcam_shared_get(struct tf *tfp __rte_unused, struct tf_tcam_get_parms *parms) { int rc; - struct tf_session *tfs; - struct tf_dev_info *dev; - int allocated = 0; - int phy_idx, log_idx; - struct tf_tcam_get_parms nparms; - struct bitalloc *pool; - uint16_t start; - enum tf_tcam_shared_wc_pool_id id; - uint16_t hcapi_type; - struct tf_rm_alloc_info info; - struct tf_tcam_shared_wc_pools *tcam_shared_wc; - void *tcam_shared_db_ptr = NULL; TF_CHECK_PARMS2(tfp, parms); - /* Retrieve the session information */ - rc = tf_session_get_session_internal(tfp, &tfs); - if (rc) - return rc; - - /* If we aren't the shared session or one of our - * special types - */ - if (!tf_session_is_shared_session(tfs) || - (parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_HIGH && - parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_LOW)) { - /* Perform normal get and exit - */ - rc = tf_tcam_get(tfp, parms); - return rc; - } - - if (!tf_tcam_db_valid(tfp, parms->dir)) { - TFP_DRV_LOG(ERR, - "%s: tcam shared pool doesn't exist\n", - tf_dir_2_str(parms->dir)); - return -ENOMEM; - } - - /* Retrieve the device information */ - rc = tf_session_get_device(tfs, &dev); - if (rc) - return rc; - if (parms->type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH) - id = TF_TCAM_SHARED_WC_POOL_HI; - else - id = TF_TCAM_SHARED_WC_POOL_LO; - - - rc = tf_session_get_tcam_shared_db(tfp, (void *)&tcam_shared_db_ptr); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to get tcam_shared_db from session, rc:%s\n", - strerror(-rc)); - return rc; - } - tcam_shared_wc = (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr; - - pool = tcam_shared_wc->db[parms->dir][id].pool; - start = tcam_shared_wc->db[parms->dir][id].info.start; - - log_idx = parms->idx; - phy_idx = parms->idx + start; - allocated = ba_inuse(pool, parms->idx); - - if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { - TFP_DRV_LOG(ERR, - "%s: Entry is not allocated, type:%d, logid:%d\n", - tf_dir_2_str(parms->dir), parms->type, log_idx); - return -EINVAL; - } - - rc = tf_tcam_shared_get_rm_info(tfp, - parms->dir, - &hcapi_type, - &info); - if (rc) - return rc; - - /* Override HI/LO type with parent WC TCAM type */ - nparms = *parms; - nparms.type = TF_TCAM_TBL_TYPE_WC_TCAM; - nparms.hcapi_type = hcapi_type; - nparms.idx = phy_idx; - - rc = tf_msg_tcam_entry_get(tfp, dev, &nparms); - if (rc) { - /* Log error */ - TFP_DRV_LOG(ERR, - "%s: %s: Entry %d set failed, rc:%s", - tf_dir_2_str(nparms.dir), - tf_tcam_tbl_2_str(nparms.type), - nparms.idx, - strerror(-rc)); - return rc; - } - return 0; -} - -/* Normally, device specific code wouldn't reside here, it belongs - * in a separate device specific function in tf_device_pxx.c. - * But this code is placed here as it is not a long term solution - * and we would like to have this code centrally located for easy - * removal - */ -#define TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P4 12 -#define TF_TCAM_SHARED_REMAP_SZ_BYTES_P4 4 -#define TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P58 24 -#define TF_TCAM_SHARED_REMAP_SZ_BYTES_P58 8 - -/* Temporary builder defines pulled in here and adjusted - * for max WC TCAM values - */ -union tf_tmp_field_obj { - uint32_t words[(TF_TCAM_SHARED_REMAP_SZ_BYTES_P58 + 3) / 4]; - uint8_t bytes[TF_TCAM_SHARED_REMAP_SZ_BYTES_P58]; -}; - -union tf_tmp_key { - uint32_t words[(TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P58 + 3) / 4]; - uint8_t bytes[TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P58]; -}; - -/** p58 has an enable bit, p4 does not - */ -#define TF_TCAM_SHARED_ENTRY_ENABLE 0x8 - -/** Move a WC TCAM entry from the high offset to the same low offset - */ -static int -tf_tcam_shared_move_entry(struct tf *tfp, - struct tf_dev_info *dev, - uint16_t hcapi_type, - enum tf_dir dir, - int sphy_idx, - int dphy_idx, - int key_sz_bytes, - int remap_sz_bytes, - bool set_enable_bit) -{ - int rc = 0; - struct tf_tcam_get_parms gparms; - struct tf_tcam_set_parms sparms; - struct tf_tcam_free_parms fparms; - union tf_tmp_key tcam_key_obj; - union tf_tmp_key tcam_key_msk_obj; - union tf_tmp_field_obj tcam_remap_obj; - - memset(&tcam_key_obj, 0, sizeof(tcam_key_obj)); - memset(&tcam_key_msk_obj, 0, sizeof(tcam_key_msk_obj)); - memset(&tcam_remap_obj, 0, sizeof(tcam_remap_obj)); - memset(&gparms, 0, sizeof(gparms)); - - gparms.hcapi_type = hcapi_type; - gparms.dir = dir; - gparms.type = TF_TCAM_TBL_TYPE_WC_TCAM; - gparms.idx = sphy_idx; - gparms.key = (uint8_t *)&tcam_key_obj; - gparms.key_size = key_sz_bytes; - gparms.mask = (uint8_t *)&tcam_key_msk_obj; - gparms.result = (uint8_t *)&tcam_remap_obj; - gparms.result_size = remap_sz_bytes; - - rc = tf_msg_tcam_entry_get(tfp, dev, &gparms); - if (rc) { - /* Log error */ - TFP_DRV_LOG(ERR, - "%s: %s: phyid(%d) get failed, rc:%s\n", - tf_tcam_tbl_2_str(gparms.type), - tf_dir_2_str(dir), - gparms.idx, - strerror(-rc)); - return rc; - } - - if (set_enable_bit) - tcam_key_obj.bytes[0] |= TF_TCAM_SHARED_ENTRY_ENABLE; - - /* Override HI/LO type with parent WC TCAM type */ - sparms.hcapi_type = hcapi_type; - sparms.dir = dir; - sparms.type = TF_TCAM_TBL_TYPE_WC_TCAM; - sparms.idx = dphy_idx; - sparms.key = gparms.key; - sparms.mask = gparms.mask; - sparms.key_size = key_sz_bytes; - sparms.result = gparms.result; - sparms.result_size = remap_sz_bytes; - - rc = tf_msg_tcam_entry_set(tfp, dev, &sparms); - if (rc) { - /* Log error */ - TFP_DRV_LOG(ERR, - "%s: %s phyid(%d/0x%x) set failed, rc:%s\n", - tf_tcam_tbl_2_str(sparms.type), - tf_dir_2_str(dir), - sparms.idx, - sparms.idx, - strerror(-rc)); - return rc; - } - - /* Override HI/LO type with parent WC TCAM type */ - fparms.dir = dir; - fparms.type = TF_TCAM_TBL_TYPE_WC_TCAM; - fparms.hcapi_type = hcapi_type; - fparms.idx = sphy_idx; - - rc = tf_msg_tcam_entry_free(tfp, dev, &fparms); - if (rc) { - /* Log error */ - TFP_DRV_LOG(ERR, - "%s: %s: phyid(%d/0x%x) free failed, rc:%s\n", - tf_dir_2_str(dir), - tf_tcam_tbl_2_str(fparms.type), - sphy_idx, - sphy_idx, - strerror(-rc)); - return rc; - } + rc = tf_tcam_get(tfp, parms); return rc; } @@ -1015,23 +108,10 @@ tf_tcam_shared_move_entry(struct tf *tfp, */ static int tf_tcam_shared_move(struct tf *tfp, - struct tf_move_tcam_shared_entries_parms *parms, - int key_sz_bytes, - int remap_sz_bytes, - bool set_enable_bit) + struct tf_move_tcam_shared_entries_parms *parms) { - int rc; struct tf_session *tfs; - struct tf_dev_info *dev; - int log_idx; - struct bitalloc *hi_pool, *lo_pool; - uint16_t hi_start, lo_start; - enum tf_tcam_shared_wc_pool_id hi_id, lo_id; - uint16_t hcapi_type; - struct tf_rm_alloc_info info; - int hi_cnt, i; - struct tf_tcam_shared_wc_pools *tcam_shared_wc; - void *tcam_shared_db_ptr = NULL; + int rc; TF_CHECK_PARMS2(tfp, parms); @@ -1052,104 +132,7 @@ int tf_tcam_shared_move(struct tf *tfp, return -EOPNOTSUPP; } - if (!tf_tcam_db_valid(tfp, parms->dir)) { - TFP_DRV_LOG(ERR, - "%s: tcam shared pool doesn't exist\n", - tf_dir_2_str(parms->dir)); - return -ENOMEM; - } - - /* Retrieve the device information */ - rc = tf_session_get_device(tfs, &dev); - if (rc) { - /* TODO print amazing error */ - return rc; - } - - rc = tf_tcam_shared_get_rm_info(tfp, - parms->dir, - &hcapi_type, - &info); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: TCAM rm info get failed\n", - tf_dir_2_str(parms->dir)); - return rc; - } - - rc = tf_session_get_tcam_shared_db(tfp, (void *)&tcam_shared_db_ptr); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to get tcam_shared_db from session, rc:%s\n", - strerror(-rc)); - return rc; - } - tcam_shared_wc = (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr; - - hi_id = TF_TCAM_SHARED_WC_POOL_HI; - hi_pool = tcam_shared_wc->db[parms->dir][hi_id].pool; - hi_start = tcam_shared_wc->db[parms->dir][hi_id].info.start; - - lo_id = TF_TCAM_SHARED_WC_POOL_LO; - lo_pool = tcam_shared_wc->db[parms->dir][lo_id].pool; - lo_start = tcam_shared_wc->db[parms->dir][lo_id].info.start; - - if (hi_pool == NULL || lo_pool == NULL) - return -ENOMEM; - - /* Get the total count of in use entries in the high pool - */ - hi_cnt = ba_inuse_count(hi_pool); - - /* Copy each valid entry to the same low pool logical offset - */ - log_idx = 0; - - for (i = 0; i < hi_cnt; i++) { - /* Find next free index starting from where we left off - */ - log_idx = ba_find_next_inuse(hi_pool, log_idx); - if (log_idx < 0) { - TFP_DRV_LOG(ERR, - "Expected a found %s entry %d\n", - tf_pool_2_str(hi_id), - i); - goto done; - } - /* The user should have never allocated from the low - * pool because the move only happens when switching - * from the high to the low pool - */ - if (ba_alloc_index(lo_pool, log_idx) < 0) { - TFP_DRV_LOG(ERR, - "Warning %s index %d already allocated\n", - tf_pool_2_str(lo_id), - i); - - /* Since already allocated, continue with move - */ - } - - rc = tf_tcam_shared_move_entry(tfp, dev, - hcapi_type, - parms->dir, - hi_start + log_idx, - lo_start + log_idx, - key_sz_bytes, - remap_sz_bytes, - set_enable_bit); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Move error %s to %s index %d\n", - tf_dir_2_str(parms->dir), - tf_pool_2_str(hi_id), - tf_pool_2_str(lo_id), - i); - goto done; - } - ba_free(hi_pool, log_idx); - } -done: + rc = tf_tcam_mgr_shared_move_msg(tfp, parms); return rc; } @@ -1159,24 +142,17 @@ tf_tcam_shared_move_p4(struct tf *tfp, { int rc = 0; rc = tf_tcam_shared_move(tfp, - parms, - TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P4, - TF_TCAM_SHARED_REMAP_SZ_BYTES_P4, - false); /* no enable bit */ + parms); return rc; } - int tf_tcam_shared_move_p58(struct tf *tfp, struct tf_move_tcam_shared_entries_parms *parms) { int rc = 0; rc = tf_tcam_shared_move(tfp, - parms, - TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P58, - TF_TCAM_SHARED_REMAP_SZ_BYTES_P58, - true); /* set enable bit */ + parms); return rc; } @@ -1186,16 +162,6 @@ tf_tcam_shared_clear(struct tf *tfp, { int rc = 0; struct tf_session *tfs; - struct tf_dev_info *dev; - uint16_t start; - int phy_idx; - enum tf_tcam_shared_wc_pool_id id; - struct tf_tcam_free_parms nparms; - uint16_t hcapi_type; - struct tf_rm_alloc_info info; - void *tcam_shared_db_ptr = NULL; - struct tf_tcam_shared_wc_pools *tcam_shared_wc; - int i, cnt; TF_CHECK_PARMS2(tfp, parms); @@ -1209,74 +175,6 @@ tf_tcam_shared_clear(struct tf *tfp, parms->tcam_tbl_type != TF_TCAM_TBL_TYPE_WC_TCAM_LOW)) return -EOPNOTSUPP; - if (!tf_tcam_db_valid(tfp, parms->dir)) { - TFP_DRV_LOG(ERR, - "%s: tcam shared pool doesn't exist\n", - tf_dir_2_str(parms->dir)); - return -ENOMEM; - } - - rc = tf_session_get_tcam_shared_db(tfp, (void *)&tcam_shared_db_ptr); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to get tcam_shared_db from session, rc:%s\n", - strerror(-rc)); - return rc; - } - tcam_shared_wc = (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr; - - - if (parms->tcam_tbl_type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH) - id = TF_TCAM_SHARED_WC_POOL_HI; - else - id = TF_TCAM_SHARED_WC_POOL_LO; - - - /* Retrieve the device information */ - rc = tf_session_get_device(tfs, &dev); - if (rc) - return rc; - - rc = tf_tcam_shared_get_rm_info(tfp, - parms->dir, - &hcapi_type, - &info); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: TCAM rm info get failed\n", - tf_dir_2_str(parms->dir)); - return rc; - } - - start = tcam_shared_wc->db[parms->dir][id].info.start; - cnt = tcam_shared_wc->db[parms->dir][id].info.stride; - - /* Override HI/LO type with parent WC TCAM type */ - nparms.dir = parms->dir; - nparms.type = TF_TCAM_TBL_TYPE_WC_TCAM; - nparms.hcapi_type = hcapi_type; - - for (i = 0; i < cnt; i++) { - phy_idx = start + i; - nparms.idx = phy_idx; - - /* Clear entry */ - rc = tf_msg_tcam_entry_free(tfp, dev, &nparms); - if (rc) { - /* Log error */ - TFP_DRV_LOG(ERR, - "%s: %s: log%d free failed, rc:%s\n", - tf_dir_2_str(nparms.dir), - tf_tcam_tbl_2_str(nparms.type), - phy_idx, - strerror(-rc)); - return rc; - } - } - - TFP_DRV_LOG(DEBUG, - "%s: TCAM shared clear pool(%s)\n", - tf_dir_2_str(nparms.dir), - tf_pool_2_str(id)); - return 0; + rc = tf_tcam_mgr_shared_clear_msg(tfp, parms); + return rc; } diff --git a/drivers/net/bnxt/tf_core/tf_tcam_shared.h b/drivers/net/bnxt/tf_core/tf_tcam_shared.h index 524631f262..e25babcd18 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam_shared.h +++ b/drivers/net/bnxt/tf_core/tf_tcam_shared.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -129,7 +129,6 @@ int tf_tcam_shared_set(struct tf *tfp, int tf_tcam_shared_get(struct tf *tfp, struct tf_tcam_get_parms *parms); - /** * Moves entries from the WC_TCAM_HI to the WC_TCAM_LO shared pools * for the P4 device. diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 1bb38399e4..8513ee06a9 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -448,13 +448,13 @@ ulp_ctx_shared_session_open(struct bnxt *bp, switch (ulp_dev_id) { case BNXT_ULP_DEVICE_ID_WH_PLUS: - parms.device_type = TF_DEVICE_TYPE_WH; + parms.device_type = TF_DEVICE_TYPE_P5; break; case BNXT_ULP_DEVICE_ID_STINGRAY: parms.device_type = TF_DEVICE_TYPE_SR; break; case BNXT_ULP_DEVICE_ID_THOR: - parms.device_type = TF_DEVICE_TYPE_THOR; + parms.device_type = TF_DEVICE_TYPE_P4; break; default: BNXT_TF_DBG(ERR, "Unable to determine dev for opening session.\n"); @@ -563,13 +563,13 @@ ulp_ctx_session_open(struct bnxt *bp, switch (ulp_dev_id) { case BNXT_ULP_DEVICE_ID_WH_PLUS: - params.device_type = TF_DEVICE_TYPE_WH; + params.device_type = TF_DEVICE_TYPE_P5; break; case BNXT_ULP_DEVICE_ID_STINGRAY: params.device_type = TF_DEVICE_TYPE_SR; break; case BNXT_ULP_DEVICE_ID_THOR: - params.device_type = TF_DEVICE_TYPE_THOR; + params.device_type = TF_DEVICE_TYPE_P4; break; default: BNXT_TF_DBG(ERR, "Unable to determine device for opening session.\n"); From patchwork Fri Apr 21 18:11:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Randy Schacher X-Patchwork-Id: 126435 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EED90429C5; Sun, 23 Apr 2023 15:25:35 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BB6A7410DE; Sun, 23 Apr 2023 15:25:35 +0200 (CEST) Received: from mail-ot1-f97.google.com (mail-ot1-f97.google.com [209.85.210.97]) by mails.dpdk.org (Postfix) with ESMTP id 7A6C142D0B for ; Fri, 21 Apr 2023 20:12:28 +0200 (CEST) Received: by mail-ot1-f97.google.com with SMTP id 46e09a7af769-6a60630574aso2023717a34.1 for ; Fri, 21 Apr 2023 11:12:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1682100747; x=1684692747; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ha5OnMaHxUJH/FFYpbjz+ex6eDJEvv6yccFek3htcj0=; b=Utk7nF7yUYB2jljbJTI6kRaIBPICYJOZ4zzcb1132Pfg7NqMkxS043tv7cDREISgro STux2n08+KhzIUJlR6uHNY4u9KI3MJ2Og6UrUVLUfkMOA38wqqBxwCuYW1SLra6Lt3sj 42kMKzsf6N/j43Iriz08hPxO9nPHtMvGp3Vf4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682100747; x=1684692747; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ha5OnMaHxUJH/FFYpbjz+ex6eDJEvv6yccFek3htcj0=; b=JSpka0DJNVW4JfAb6UNLjxz08ofsKwehqUfZT6mVlnM70eTFIg/tted0dzo8g8acCE zJThvrmue/lU56qUQso2soEUXVT2k7mQsP+1hCO7r6iU3h6HRhpmkyEtAwWOSFUsuRlJ 4B6rwJWaMuv7ib94216wEghQF64dfGa6rLUbqRyKb26a16YBL/ncDdRp9qmOD/MqztyQ Vo6HzXSQ5pBCZ6tmD3gMRmzU+5Ti+6Jp8WylcGtj6FzUJ6X/3UR85/8xp4rrDshSVW6s 2KW45X6mvp5U7lFNk1PAv2RTnBEh8b1s8CdOh4GoCyxHXm0dAqcKmJF0gi3xAclsKUJw F6Nw== X-Gm-Message-State: AAQBX9e4X7LxRzQKFO2sI/RLX6BZh3VYsUhd7x4ZqzQDlAutOknUT/y3 Zfzn3XCdbO/7bGmF8ljW6/veZ/IJKd/WsOKJ/mz+w42FR0aPtGsdJKL4wvOA5n1R757atgfcSG5 wLvskh5itRqgxZMcLWUhMpv7W+MskRqd4j5rznORzFrNK4L2XtB1h5js1w+daglsg5UPK4jxAYn w5dEPgeMZXrGd9 X-Google-Smtp-Source: AKy350Z/5JmcSzV5/0SyWX5c1LGvpXrwhIz6EI2sObohfR6GZRWj9VgXxMe/cOVYpBl1K19s7OvHQl1Hww9Z X-Received: by 2002:a05:6870:c0c6:b0:184:832b:baf9 with SMTP id e6-20020a056870c0c600b00184832bbaf9mr4834796oad.3.1682100746212; Fri, 21 Apr 2023 11:12:26 -0700 (PDT) Received: from r650-k2.dhcp.broadcom.net ([192.19.144.250]) by smtp-relay.gmail.com with ESMTPS id o21-20020a056870e81500b0017eb57c3417sm397528oan.19.2023.04.21.11.12.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Apr 2023 11:12:26 -0700 (PDT) X-Relaying-Domain: broadcom.com From: Randy Schacher To: dev@dpdk.org Cc: Kishore Padmanabha , Shahaji Bhosle Subject: [PATCH v2 05/11] net/bnxt: update ULP shared session support Date: Fri, 21 Apr 2023 18:11:49 +0000 Message-Id: <20230421181155.2160482-6-stuart.schacher@broadcom.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230421181155.2160482-1-stuart.schacher@broadcom.com> References: <20230421181155.2160482-1-stuart.schacher@broadcom.com> MIME-Version: 1.0 X-Mailman-Approved-At: Sun, 23 Apr 2023 15:25:34 +0200 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org - Update ulp generic templates - Modify code to support shared sessions Signed-off-by: Randy Schacher Signed-off-by: Kishore Padmanabha Reviewed-by: Shahaji Bhosle --- drivers/net/bnxt/bnxt.h | 16 +- drivers/net/bnxt/bnxt_ethdev.c | 8 +- drivers/net/bnxt/bnxt_reps.c | 4 +- drivers/net/bnxt/tf_core/tf_rm.c | 28 +- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 548 +- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 109 +- .../bnxt/tf_ulp/generic_templates/meson.build | 18 +- .../generic_templates/ulp_template_db_act.c | 7000 +++- .../generic_templates/ulp_template_db_class.c | 33556 +++++++++++----- .../generic_templates/ulp_template_db_enum.h | 4366 +- .../generic_templates/ulp_template_db_field.h | 689 +- .../generic_templates/ulp_template_db_tbl.c | 16055 ++++++-- .../ulp_template_db_thor_act.c | 8714 ++-- .../ulp_template_db_thor_class.c | 10746 +++-- .../ulp_template_db_wh_plus_act.c | 1157 +- .../ulp_template_db_wh_plus_class.c | 288 +- drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 16 +- drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 25 +- drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h | 7 +- drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 29 +- drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 15 +- drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c | 10 +- drivers/net/bnxt/tf_ulp/ulp_mapper.c | 281 +- drivers/net/bnxt/tf_ulp/ulp_port_db.c | 6 +- drivers/net/bnxt/tf_ulp/ulp_port_db.h | 10 +- drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 17 +- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 22 +- 27 files changed, 63079 insertions(+), 20661 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 2bccdec7e0..bb2e7fe003 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ @@ -633,6 +633,13 @@ struct bnxt_ring_stats { uint64_t rx_agg_aborts; }; +enum bnxt_session_type { + BNXT_SESSION_TYPE_REGULAR = 0, + BNXT_SESSION_TYPE_SHARED_COMMON, + BNXT_SESSION_TYPE_SHARED_WC, + BNXT_SESSION_TYPE_LAST +}; + struct bnxt { void *bar0; @@ -690,6 +697,9 @@ struct bnxt { #define BNXT_FLAGS2_PTP_ALARM_SCHEDULED BIT(1) #define BNXT_P5_PTP_TIMESYNC_ENABLED(bp) \ ((bp)->flags2 & BNXT_FLAGS2_PTP_TIMESYNC_ENABLED) +#define BNXT_FLAGS2_TESTPMD_EN BIT(3) +#define BNXT_TESTPMD_EN(bp) \ + ((bp)->flags2 & BNXT_FLAGS2_TESTPMD_EN) uint16_t chip_num; #define CHIP_NUM_58818 0xd818 @@ -855,8 +865,7 @@ struct bnxt { uint16_t func_svif; uint16_t port_svif; - struct tf tfp; - struct tf tfp_shared; + struct tf tfp[BNXT_SESSION_TYPE_LAST]; struct bnxt_ulp_context *ulp_ctx; struct bnxt_flow_stat_info *flow_stat; uint16_t max_num_kflows; @@ -1044,4 +1053,5 @@ int bnxt_flow_ops_get_op(struct rte_eth_dev *dev, int bnxt_dev_start_op(struct rte_eth_dev *eth_dev); int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev); void bnxt_handle_vf_cfg_change(void *arg); +struct tf *bnxt_get_tfp_session(struct bnxt *bp, enum bnxt_session_type type); #endif diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index ef7b8859d9..bcde44bb14 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ @@ -6415,6 +6415,12 @@ bool is_bnxt_supported(struct rte_eth_dev *dev) return is_device_supported(dev, &bnxt_rte_pmd); } +struct tf *bnxt_get_tfp_session(struct bnxt *bp, enum bnxt_session_type type) +{ + return (type >= BNXT_SESSION_TYPE_LAST) ? + &bp->tfp[BNXT_SESSION_TYPE_REGULAR] : &bp->tfp[type]; +} + RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE); RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map); diff --git a/drivers/net/bnxt/bnxt_reps.c b/drivers/net/bnxt/bnxt_reps.c index 8a5b777793..78337431af 100644 --- a/drivers/net/bnxt/bnxt_reps.c +++ b/drivers/net/bnxt/bnxt_reps.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ @@ -327,7 +327,7 @@ static int bnxt_tf_vfr_alloc(struct rte_eth_dev *vfr_ethdev) (void)bnxt_hwrm_cfa_pair_free(parent_bp, vfr); /* Update the ULP portdata base with the new VFR interface */ - rc = ulp_port_db_dev_port_intf_update(parent_bp->ulp_ctx, vfr_ethdev); + rc = ulp_port_db_port_update(parent_bp->ulp_ctx, vfr_ethdev); if (rc) { BNXT_TF_DBG(ERR, "Failed to update ulp port details vfr:%u\n", vfr->vf_id); diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c index 1fccb698d0..9b85f5397d 100644 --- a/drivers/net/bnxt/tf_core/tf_rm.c +++ b/drivers/net/bnxt/tf_core/tf_rm.c @@ -364,8 +364,7 @@ tf_rm_update_parent_reservations(struct tf *tfp, struct tf_rm_element_cfg *cfg, uint16_t *alloc_cnt, uint16_t num_elements, - uint16_t *req_cnt, - bool shared_session) + uint16_t *req_cnt) { int parent, child; const char *type_str = NULL; @@ -376,11 +375,7 @@ tf_rm_update_parent_reservations(struct tf *tfp, /* If I am a parent */ if (cfg[parent].cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_PARENT) { - uint8_t p_slices = 1; - - /* Shared session doesn't support slices */ - if (!shared_session) - p_slices = cfg[parent].slices; + uint8_t p_slices = cfg[parent].slices; RTE_ASSERT(p_slices); @@ -402,12 +397,9 @@ tf_rm_update_parent_reservations(struct tf *tfp, TF_RM_ELEM_CFG_HCAPI_BA_CHILD && cfg[child].parent_subtype == parent && alloc_cnt[child]) { - uint8_t c_slices = 1; + uint8_t c_slices = cfg[child].slices; uint16_t cnt = 0; - if (!shared_session) - c_slices = cfg[child].slices; - RTE_ASSERT(c_slices); dev->ops->tf_dev_get_resource_str(tfp, @@ -429,7 +421,7 @@ tf_rm_update_parent_reservations(struct tf *tfp, } } /* Save the parent count to be requested */ - req_cnt[parent] = combined_cnt; + req_cnt[parent] = combined_cnt * 2; } } return 0; @@ -452,7 +444,6 @@ tf_rm_create_db(struct tf *tfp, struct tf_rm_new_db *rm_db; struct tf_rm_element *db; uint32_t pool_size; - bool shared_session = 0; TF_CHECK_PARMS2(tfp, parms); @@ -505,15 +496,12 @@ tf_rm_create_db(struct tf *tfp, tfp_memcpy(req_cnt, parms->alloc_cnt, parms->num_elements * sizeof(uint16_t)); - shared_session = tf_session_is_shared_session(tfs); - /* Update the req_cnt based upon the element configuration */ tf_rm_update_parent_reservations(tfp, dev, parms->cfg, parms->alloc_cnt, parms->num_elements, - req_cnt, - shared_session); + req_cnt); /* Process capabilities against DB requirements. However, as a * DB can hold elements that are not HCAPI we can reduce the @@ -733,7 +721,6 @@ tf_rm_create_db_no_reservation(struct tf *tfp, struct tf_rm_new_db *rm_db; struct tf_rm_element *db; uint32_t pool_size; - bool shared_session = 0; TF_CHECK_PARMS2(tfp, parms); @@ -763,15 +750,12 @@ tf_rm_create_db_no_reservation(struct tf *tfp, tfp_memcpy(req_cnt, parms->alloc_cnt, parms->num_elements * sizeof(uint16_t)); - shared_session = tf_session_is_shared_session(tfs); - /* Update the req_cnt based upon the element configuration */ tf_rm_update_parent_reservations(tfp, dev, parms->cfg, parms->alloc_cnt, parms->num_elements, - req_cnt, - shared_session); + req_cnt); /* Process capabilities against DB requirements. However, as a * DB can hold elements that are not HCAPI we can reduce the diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 8513ee06a9..109bd0652a 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -13,6 +13,7 @@ #include "bnxt.h" #include "bnxt_ulp.h" #include "bnxt_tf_common.h" +#include "hsi_struct_def_dpdk.h" #include "tf_core.h" #include "tf_ext_flow_handle.h" @@ -26,6 +27,7 @@ #include "ulp_tun.h" #include "ulp_ha_mgr.h" #include "bnxt_tf_pmd_shim.h" +#include "ulp_template_db_tbl.h" /* Linked list of all TF sessions. */ STAILQ_HEAD(, bnxt_ulp_session_state) bnxt_ulp_session_list = @@ -91,6 +93,17 @@ bnxt_ulp_app_cap_list_get(uint32_t *num_entries) return ulp_app_cap_info_list; } +struct bnxt_ulp_shared_act_info * +bnxt_ulp_shared_act_info_get(uint32_t *num_entries) +{ + if (!num_entries) + return NULL; + + *num_entries = BNXT_ULP_GEN_TBL_MAX_SZ; + + return ulp_shared_act_info; +} + static struct bnxt_ulp_resource_resv_info * bnxt_ulp_app_resource_resv_list_get(uint32_t *num_entries) { @@ -122,6 +135,7 @@ static int32_t bnxt_ulp_named_resources_calc(struct bnxt_ulp_context *ulp_ctx, struct bnxt_ulp_glb_resource_info *info, uint32_t num, + enum bnxt_ulp_session_type stype, struct tf_session_resources *res) { uint32_t dev_id = BNXT_ULP_DEVICE_ID_LAST, res_type, i; @@ -149,6 +163,11 @@ bnxt_ulp_named_resources_calc(struct bnxt_ulp_context *ulp_ctx, for (i = 0; i < num; i++) { if (dev_id != info[i].device_id || app_id != info[i].app_id) continue; + /* check to see if the session type matches only then include */ + if ((stype || info[i].session_type) && + !(info[i].session_type & stype)) + continue; + dir = info[i].direction; res_type = info[i].resource_type; @@ -179,6 +198,7 @@ static int32_t bnxt_ulp_unnamed_resources_calc(struct bnxt_ulp_context *ulp_ctx, struct bnxt_ulp_resource_resv_info *info, uint32_t num, + enum bnxt_ulp_session_type stype, struct tf_session_resources *res) { uint32_t dev_id, res_type, i; @@ -206,6 +226,12 @@ bnxt_ulp_unnamed_resources_calc(struct bnxt_ulp_context *ulp_ctx, for (i = 0; i < num; i++) { if (app_id != info[i].app_id || dev_id != info[i].device_id) continue; + + /* check to see if the session type matches only then include */ + if ((stype || info[i].session_type) && + !(info[i].session_type & stype)) + continue; + dir = info[i].direction; res_type = info[i].resource_type; @@ -231,6 +257,7 @@ bnxt_ulp_unnamed_resources_calc(struct bnxt_ulp_context *ulp_ctx, static int32_t bnxt_ulp_tf_resources_get(struct bnxt_ulp_context *ulp_ctx, + enum bnxt_ulp_session_type stype, struct tf_session_resources *res) { struct bnxt_ulp_resource_resv_info *unnamed = NULL; @@ -242,13 +269,18 @@ bnxt_ulp_tf_resources_get(struct bnxt_ulp_context *ulp_ctx, return -EINVAL; } + /* use DEFAULT_NON_HA instead of DEFAULT resources if HA is disabled */ + if (ULP_APP_HA_IS_DYNAMIC(ulp_ctx)) + stype = ulp_ctx->cfg_data->def_session_type; + unnamed = bnxt_ulp_resource_resv_list_get(&unum); if (unnamed == NULL) { BNXT_TF_DBG(ERR, "Unable to get resource resv list.\n"); return -EINVAL; } - rc = bnxt_ulp_unnamed_resources_calc(ulp_ctx, unnamed, unum, res); + rc = bnxt_ulp_unnamed_resources_calc(ulp_ctx, unnamed, unum, stype, + res); if (rc) BNXT_TF_DBG(ERR, "Unable to calc resources for session.\n"); @@ -257,6 +289,7 @@ bnxt_ulp_tf_resources_get(struct bnxt_ulp_context *ulp_ctx, static int32_t bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx, + enum bnxt_ulp_session_type stype, struct tf_session_resources *res) { struct bnxt_ulp_resource_resv_info *unnamed; @@ -272,6 +305,10 @@ bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx, /* Make sure the resources are zero before accumulating. */ memset(res, 0, sizeof(struct tf_session_resources)); + if (bnxt_ulp_cntxt_ha_enabled(ulp_ctx) && + stype == BNXT_ULP_SESSION_TYPE_SHARED) + stype = ulp_ctx->cfg_data->hu_session_type; + /* * Shared resources are comprised of both named and unnamed resources. * First get the unnamed counts, and then add the named to the result. @@ -282,9 +319,11 @@ bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx, BNXT_TF_DBG(ERR, "Unable to get shared resource resv list.\n"); return -EINVAL; } - rc = bnxt_ulp_unnamed_resources_calc(ulp_ctx, unnamed, unum, res); + rc = bnxt_ulp_unnamed_resources_calc(ulp_ctx, unnamed, unum, stype, + res); if (rc) { - BNXT_TF_DBG(ERR, "Unable to calc resources for shared session.\n"); + BNXT_TF_DBG(ERR, + "Unable to calc resources for shared session.\n"); return -EINVAL; } @@ -294,7 +333,7 @@ bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx, BNXT_TF_DBG(ERR, "Unable to get app global resource list\n"); return -EINVAL; } - rc = bnxt_ulp_named_resources_calc(ulp_ctx, named, nnum, res); + rc = bnxt_ulp_named_resources_calc(ulp_ctx, named, nnum, stype, res); if (rc) BNXT_TF_DBG(ERR, "Unable to calc named resources\n"); @@ -356,17 +395,127 @@ bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp, return 0; } +/* Function to set the number for vxlan_ip (custom vxlan) port into the context */ +int +bnxt_ulp_vxlan_ip_port_set(struct bnxt_ulp_context *ulp_ctx, + uint32_t vxlan_ip_port) +{ + if (!ulp_ctx || !ulp_ctx->cfg_data) + return -EINVAL; + + ulp_ctx->cfg_data->vxlan_ip_port = vxlan_ip_port; + + return 0; +} + +/* Function to retrieve the vxlan_ip (custom vxlan) port from the context. */ +unsigned int +bnxt_ulp_vxlan_ip_port_get(struct bnxt_ulp_context *ulp_ctx) +{ + if (!ulp_ctx || !ulp_ctx->cfg_data) + return 0; + + return (unsigned int)ulp_ctx->cfg_data->vxlan_ip_port; +} + +/* Function to set the number for vxlan port into the context */ +int +bnxt_ulp_vxlan_port_set(struct bnxt_ulp_context *ulp_ctx, + uint32_t vxlan_port) +{ + if (!ulp_ctx || !ulp_ctx->cfg_data) + return -EINVAL; + + ulp_ctx->cfg_data->vxlan_port = vxlan_port; + + return 0; +} + +/* Function to retrieve the vxlan port from the context. */ +unsigned int +bnxt_ulp_vxlan_port_get(struct bnxt_ulp_context *ulp_ctx) +{ + if (!ulp_ctx || !ulp_ctx->cfg_data) + return 0; + + return (unsigned int)ulp_ctx->cfg_data->vxlan_port; +} + +static inline uint32_t +bnxt_ulp_session_idx_get(enum bnxt_ulp_session_type session_type) { + if (session_type & BNXT_ULP_SESSION_TYPE_SHARED) + return 1; + else if (session_type & BNXT_ULP_SESSION_TYPE_SHARED_WC) + return 2; + return 0; +} + +/* Function to set the tfp session details in session */ +static int32_t +bnxt_ulp_session_tfp_set(struct bnxt_ulp_session_state *session, + enum bnxt_ulp_session_type session_type, + struct tf *tfp) +{ + uint32_t idx = bnxt_ulp_session_idx_get(session_type); + int32_t rc = 0; + + if (!session->session_opened[idx]) { + session->g_tfp[idx] = rte_zmalloc("bnxt_ulp_session_tfp", + sizeof(struct tf), 0); + if (!session->g_tfp[idx]) { + BNXT_TF_DBG(DEBUG, "Failed to alloc session tfp\n"); + return -ENOMEM; + } + session->g_tfp[idx]->session = tfp->session; + session->session_opened[idx] = 1; + } + return rc; +} + +/* Function to get the tfp session details in session */ +static struct tf_session_info * +bnxt_ulp_session_tfp_get(struct bnxt_ulp_session_state *session, + enum bnxt_ulp_session_type session_type) +{ + uint32_t idx = bnxt_ulp_session_idx_get(session_type); + + if (session->session_opened[idx]) + return session->g_tfp[idx]->session; + return NULL; +} + +static uint32_t +bnxt_ulp_session_is_open(struct bnxt_ulp_session_state *session, + enum bnxt_ulp_session_type session_type) +{ + uint32_t idx = bnxt_ulp_session_idx_get(session_type); + + return session->session_opened[idx]; +} + +/* Function to reset the tfp session details in session */ +static void +bnxt_ulp_session_tfp_reset(struct bnxt_ulp_session_state *session, + enum bnxt_ulp_session_type session_type) +{ + uint32_t idx = bnxt_ulp_session_idx_get(session_type); + + if (session->session_opened[idx]) { + session->session_opened[idx] = 0; + rte_free(session->g_tfp[idx]); + session->g_tfp[idx] = NULL; + } +} + static void ulp_ctx_shared_session_close(struct bnxt *bp, + enum bnxt_ulp_session_type session_type, struct bnxt_ulp_session_state *session) { struct tf *tfp; int32_t rc; - if (!bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx)) - return; - - tfp = bnxt_ulp_cntxt_shared_tfp_get(bp->ulp_ctx); + tfp = bnxt_ulp_cntxt_tfp_get(bp->ulp_ctx, session_type); if (!tfp) { /* * Log it under debug since this is likely a case of the @@ -380,29 +529,26 @@ ulp_ctx_shared_session_close(struct bnxt *bp, if (rc) BNXT_TF_DBG(ERR, "Failed to close the shared session rc=%d.\n", rc); - (void)bnxt_ulp_cntxt_shared_tfp_set(bp->ulp_ctx, NULL); - - session->g_shared_tfp.session = NULL; + (void)bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, session_type, NULL); + bnxt_ulp_session_tfp_reset(session, session_type); } static int32_t ulp_ctx_shared_session_open(struct bnxt *bp, + enum bnxt_ulp_session_type session_type, struct bnxt_ulp_session_state *session) { struct rte_eth_dev *ethdev = bp->eth_dev; struct tf_session_resources *resources; struct tf_open_session_parms parms; - size_t copy_nbytes; + size_t nb; uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST; int32_t rc = 0; uint8_t app_id; - - /* only perform this if shared session is enabled. */ - if (!bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx)) - return 0; + struct tf *tfp; + uint8_t pool_id; memset(&parms, 0, sizeof(parms)); - rc = rte_eth_dev_get_name_by_port(ethdev->data->port_id, parms.ctrl_chan_name); if (rc) { @@ -416,21 +562,39 @@ ulp_ctx_shared_session_open(struct bnxt *bp, * Need to account for size of ctrl_chan_name and 1 extra for Null * terminator */ - copy_nbytes = sizeof(parms.ctrl_chan_name) - - strlen(parms.ctrl_chan_name) - 1; + nb = sizeof(parms.ctrl_chan_name) - strlen(parms.ctrl_chan_name) - 1; /* * Build the ctrl_chan_name with shared token. * When HA is enabled, the WC TCAM needs extra management by the core, * so add the wc_tcam string to the control channel. */ - if (bnxt_ulp_cntxt_ha_enabled(bp->ulp_ctx)) - strncat(parms.ctrl_chan_name, "-tf_shared-wc_tcam", - copy_nbytes); - else - strncat(parms.ctrl_chan_name, "-tf_shared", copy_nbytes); + pool_id = bp->ulp_ctx->cfg_data->ha_pool_id; + if (!bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) { + if (bnxt_ulp_cntxt_ha_enabled(bp->ulp_ctx)) + strncat(parms.ctrl_chan_name, "-tf_shared-wc_tcam", nb); + else + strncat(parms.ctrl_chan_name, "-tf_shared", nb); + } else if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) { + if (session_type == BNXT_ULP_SESSION_TYPE_SHARED) { + strncat(parms.ctrl_chan_name, "-tf_shared", nb); + } else if (session_type == BNXT_ULP_SESSION_TYPE_SHARED_WC) { + char session_pool_name[64]; + + sprintf(session_pool_name, "-tf_shared-pool%d", + pool_id); + + if (nb >= strlen(session_pool_name)) { + strncat(parms.ctrl_chan_name, session_pool_name, nb); + } else { + BNXT_TF_DBG(ERR, "No space left for session_name\n"); + return -EINVAL; + } + } + } - rc = bnxt_ulp_tf_shared_session_resources_get(bp->ulp_ctx, resources); + rc = bnxt_ulp_tf_shared_session_resources_get(bp->ulp_ctx, session_type, + resources); if (rc) return rc; @@ -446,32 +610,15 @@ ulp_ctx_shared_session_open(struct bnxt *bp, return rc; } - switch (ulp_dev_id) { - case BNXT_ULP_DEVICE_ID_WH_PLUS: - parms.device_type = TF_DEVICE_TYPE_P5; - break; - case BNXT_ULP_DEVICE_ID_STINGRAY: - parms.device_type = TF_DEVICE_TYPE_SR; - break; - case BNXT_ULP_DEVICE_ID_THOR: - parms.device_type = TF_DEVICE_TYPE_P4; - break; - default: - BNXT_TF_DBG(ERR, "Unable to determine dev for opening session.\n"); - return rc; - } - + tfp = bnxt_ulp_bp_tfp_get(bp, session_type); + parms.device_type = bnxt_ulp_cntxt_convert_dev_id(ulp_dev_id); parms.bp = bp; - if (app_id == 0) - parms.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW; - else - parms.wc_num_slices = TF_WC_TCAM_1_SLICE_PER_ROW; /* * Open the session here, but the collect the resources during the * mapper initialization. */ - rc = tf_open_session(&bp->tfp_shared, &parms); + rc = tf_open_session(tfp, &parms); if (rc) return rc; @@ -481,40 +628,70 @@ ulp_ctx_shared_session_open(struct bnxt *bp, BNXT_TF_DBG(DEBUG, "Shared session attached.\n"); /* Save the shared session in global data */ - if (!session->g_shared_tfp.session) - session->g_shared_tfp.session = bp->tfp_shared.session; + rc = bnxt_ulp_session_tfp_set(session, session_type, tfp); + if (rc) { + BNXT_TF_DBG(ERR, "Failed to add shared tfp to session\n"); + return rc; + } - rc = bnxt_ulp_cntxt_shared_tfp_set(bp->ulp_ctx, &bp->tfp_shared); - if (rc) + rc = bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, session_type, tfp); + if (rc) { BNXT_TF_DBG(ERR, "Failed to add shared tfp to ulp (%d)\n", rc); + return rc; + } return rc; } static int32_t ulp_ctx_shared_session_attach(struct bnxt *bp, - struct bnxt_ulp_session_state *session) + struct bnxt_ulp_session_state *ses) { + enum bnxt_ulp_session_type type; + struct tf *tfp; int32_t rc = 0; /* Simply return success if shared session not enabled */ if (bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx)) { - bp->tfp_shared.session = session->g_shared_tfp.session; - rc = ulp_ctx_shared_session_open(bp, session); + type = BNXT_ULP_SESSION_TYPE_SHARED; + tfp = bnxt_ulp_bp_tfp_get(bp, type); + tfp->session = bnxt_ulp_session_tfp_get(ses, type); + rc = ulp_ctx_shared_session_open(bp, type, ses); + } + + if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) { + type = BNXT_ULP_SESSION_TYPE_SHARED_WC; + tfp = bnxt_ulp_bp_tfp_get(bp, type); + tfp->session = bnxt_ulp_session_tfp_get(ses, type); + rc = ulp_ctx_shared_session_open(bp, type, ses); } + if (!rc) + bnxt_ulp_cntxt_num_shared_clients_set(bp->ulp_ctx, true); + return rc; } static void ulp_ctx_shared_session_detach(struct bnxt *bp) { + struct tf *tfp; + if (bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx)) { - if (bp->tfp_shared.session) { - tf_close_session(&bp->tfp_shared); - bp->tfp_shared.session = NULL; + tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_SHARED); + if (tfp->session) { + tf_close_session(tfp); + tfp->session = NULL; } } + if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) { + tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_SHARED_WC); + if (tfp->session) { + tf_close_session(tfp); + tfp->session = NULL; + } + } + bnxt_ulp_cntxt_num_shared_clients_set(bp->ulp_ctx, false); } /* @@ -538,6 +715,7 @@ ulp_ctx_session_open(struct bnxt *bp, struct tf_session_resources *resources; uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST; uint8_t app_id; + struct tf *tfp; memset(¶ms, 0, sizeof(params)); @@ -561,43 +739,29 @@ ulp_ctx_session_open(struct bnxt *bp, return rc; } - switch (ulp_dev_id) { - case BNXT_ULP_DEVICE_ID_WH_PLUS: - params.device_type = TF_DEVICE_TYPE_P5; - break; - case BNXT_ULP_DEVICE_ID_STINGRAY: - params.device_type = TF_DEVICE_TYPE_SR; - break; - case BNXT_ULP_DEVICE_ID_THOR: - params.device_type = TF_DEVICE_TYPE_P4; - break; - default: - BNXT_TF_DBG(ERR, "Unable to determine device for opening session.\n"); - return rc; - } - + params.device_type = bnxt_ulp_cntxt_convert_dev_id(ulp_dev_id); resources = ¶ms.resources; - rc = bnxt_ulp_tf_resources_get(bp->ulp_ctx, resources); + rc = bnxt_ulp_tf_resources_get(bp->ulp_ctx, + BNXT_ULP_SESSION_TYPE_DEFAULT, + resources); if (rc) return rc; params.bp = bp; - if (app_id == 0) - params.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW; - else - params.wc_num_slices = TF_WC_TCAM_1_SLICE_PER_ROW; - rc = tf_open_session(&bp->tfp, ¶ms); + tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT); + rc = tf_open_session(tfp, ¶ms); if (rc) { BNXT_TF_DBG(ERR, "Failed to open TF session - %s, rc = %d\n", params.ctrl_chan_name, rc); return -EINVAL; } - if (!session->session_opened) { - session->session_opened = 1; - session->g_tfp = rte_zmalloc("bnxt_ulp_session_tfp", - sizeof(struct tf), 0); - session->g_tfp->session = bp->tfp.session; + rc = bnxt_ulp_session_tfp_set(session, + BNXT_ULP_SESSION_TYPE_DEFAULT, tfp); + if (rc) { + BNXT_TF_DBG(ERR, "Failed to set TF session - %s, rc = %d\n", + params.ctrl_chan_name, rc); + return -EINVAL; } return rc; } @@ -610,12 +774,14 @@ static void ulp_ctx_session_close(struct bnxt *bp, struct bnxt_ulp_session_state *session) { + struct tf *tfp; + /* close the session in the hardware */ - if (session->session_opened) - tf_close_session(&bp->tfp); - session->session_opened = 0; - rte_free(session->g_tfp); - session->g_tfp = NULL; + if (bnxt_ulp_session_is_open(session, BNXT_ULP_SESSION_TYPE_DEFAULT)) { + tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT); + tf_close_session(tfp); + } + bnxt_ulp_session_tfp_reset(session, BNXT_ULP_SESSION_TYPE_DEFAULT); } static void @@ -678,6 +844,7 @@ ulp_eem_tbl_scope_init(struct bnxt *bp) struct bnxt_ulp_device_params *dparms; enum bnxt_ulp_flow_mem_type mtype; uint32_t dev_id; + struct tf *tfp; int rc; /* Get the dev specific number of flows that needed to be supported. */ @@ -700,12 +867,14 @@ ulp_eem_tbl_scope_init(struct bnxt *bp) } bnxt_init_tbl_scope_parms(bp, ¶ms); - rc = tf_alloc_tbl_scope(&bp->tfp, ¶ms); + tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT); + rc = tf_alloc_tbl_scope(tfp, ¶ms); if (rc) { BNXT_TF_DBG(ERR, "Unable to allocate eem table scope rc = %d\n", rc); return rc; } + rc = bnxt_ulp_cntxt_tbl_scope_id_set(bp->ulp_ctx, params.tbl_scope_id); if (rc) { BNXT_TF_DBG(ERR, "Unable to set table scope id\n"); @@ -729,7 +898,7 @@ ulp_eem_tbl_scope_deinit(struct bnxt *bp, struct bnxt_ulp_context *ulp_ctx) if (!ulp_ctx || !ulp_ctx->cfg_data) return -EINVAL; - tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_NO); + tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT); if (!tfp) { BNXT_TF_DBG(ERR, "Failed to get the truflow pointer\n"); return -EINVAL; @@ -777,7 +946,16 @@ ulp_ctx_deinit(struct bnxt *bp, ulp_ctx_session_close(bp, session); /* The shared session must be closed last. */ - ulp_ctx_shared_session_close(bp, session); + if (bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx)) + ulp_ctx_shared_session_close(bp, BNXT_ULP_SESSION_TYPE_SHARED, + session); + + if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) + ulp_ctx_shared_session_close(bp, + BNXT_ULP_SESSION_TYPE_SHARED_WC, + session); + + bnxt_ulp_cntxt_num_shared_clients_set(bp->ulp_ctx, false); /* Free the contents */ if (session->cfg_data) { @@ -796,6 +974,8 @@ ulp_ctx_init(struct bnxt *bp, struct bnxt_ulp_data *ulp_data; int32_t rc = 0; enum bnxt_ulp_device_id devid; + enum bnxt_ulp_session_type stype; + struct tf *tfp; /* Initialize the context entries list */ bnxt_ulp_cntxt_list_init(); @@ -851,22 +1031,42 @@ ulp_ctx_init(struct bnxt *bp, * Shared session must be created before first regular session but after * the ulp_ctx is valid. */ - rc = ulp_ctx_shared_session_open(bp, session); - if (rc) { - BNXT_TF_DBG(ERR, "Unable to open shared session (%d)\n", rc); - goto error_deinit; + if (bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx)) { + rc = ulp_ctx_shared_session_open(bp, + BNXT_ULP_SESSION_TYPE_SHARED, + session); + if (rc) { + BNXT_TF_DBG(ERR, "Unable to open shared session (%d)\n", + rc); + goto error_deinit; + } } + /* Multiple session support */ + if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) { + stype = BNXT_ULP_SESSION_TYPE_SHARED_WC; + rc = ulp_ctx_shared_session_open(bp, stype, session); + if (rc) { + BNXT_TF_DBG(ERR, + "Unable to open shared wc session (%d)\n", + rc); + goto error_deinit; + } + } + bnxt_ulp_cntxt_num_shared_clients_set(bp->ulp_ctx, true); + + /* Open the ulp session. */ rc = ulp_ctx_session_open(bp, session); if (rc) goto error_deinit; - bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, &bp->tfp); + tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT); + bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT, tfp); return rc; error_deinit: - session->session_opened = 1; + session->session_opened[BNXT_ULP_SESSION_TYPE_DEFAULT] = 1; (void)ulp_ctx_deinit(bp, session); return rc; } @@ -932,6 +1132,7 @@ ulp_ctx_attach(struct bnxt *bp, { int32_t rc = 0; uint32_t flags, dev_id = BNXT_ULP_DEVICE_ID_LAST; + struct tf *tfp; uint8_t app_id; /* Increment the ulp context data reference count usage. */ @@ -939,7 +1140,9 @@ ulp_ctx_attach(struct bnxt *bp, bp->ulp_ctx->cfg_data->ref_cnt++; /* update the session details in bnxt tfp */ - bp->tfp.session = session->g_tfp->session; + tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT); + tfp->session = bnxt_ulp_session_tfp_get(session, + BNXT_ULP_SESSION_TYPE_DEFAULT); /* Add the context to the context entries list */ rc = bnxt_ulp_cntxt_list_add(bp->ulp_ctx); @@ -975,20 +1178,23 @@ ulp_ctx_attach(struct bnxt *bp, rc = ulp_ctx_session_open(bp, session); if (rc) { PMD_DRV_LOG(ERR, "Failed to open ctxt session, rc:%d\n", rc); - bp->tfp.session = NULL; + tfp->session = NULL; return rc; } - bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, &bp->tfp); + bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT, tfp); return rc; } static void ulp_ctx_detach(struct bnxt *bp) { - if (bp->tfp.session) { - tf_close_session(&bp->tfp); - bp->tfp.session = NULL; + struct tf *tfp; + + tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT); + if (tfp->session) { + tf_close_session(tfp); + tfp->session = NULL; } } @@ -1121,6 +1327,7 @@ bnxt_ulp_global_cfg_update(struct bnxt *bp, uint32_t global_cfg = 0; int rc; struct tf_global_cfg_parms parms = { 0 }; + struct tf *tfp; /* Initialize the params */ parms.dir = dir, @@ -1129,7 +1336,8 @@ bnxt_ulp_global_cfg_update(struct bnxt *bp, parms.config = (uint8_t *)&global_cfg, parms.config_sz_in_bytes = sizeof(global_cfg); - rc = tf_get_global_cfg(&bp->tfp, &parms); + tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT); + rc = tf_get_global_cfg(tfp, &parms); if (rc) { BNXT_TF_DBG(ERR, "Failed to get global cfg 0x%x rc:%d\n", type, rc); @@ -1142,7 +1350,7 @@ bnxt_ulp_global_cfg_update(struct bnxt *bp, global_cfg &= ~value; /* SET the register RE_CFA_REG_ACT_TECT */ - rc = tf_set_global_cfg(&bp->tfp, &parms); + rc = tf_set_global_cfg(tfp, &parms); if (rc) { BNXT_TF_DBG(ERR, "Failed to set global cfg 0x%x rc:%d\n", type, rc); @@ -1473,7 +1681,7 @@ bnxt_ulp_port_init(struct bnxt *bp) } /* update the port database for the given interface */ - rc = ulp_port_db_dev_port_intf_update(bp->ulp_ctx, bp->eth_dev); + rc = ulp_port_db_port_update(bp->ulp_ctx, bp->eth_dev); if (rc) { BNXT_TF_DBG(ERR, "Failed to update port database\n"); goto jump_to_error; @@ -1624,6 +1832,12 @@ bnxt_ulp_cntxt_shared_session_enabled(struct bnxt_ulp_context *ulp_ctx) return ULP_SHARED_SESSION_IS_ENABLED(ulp_ctx->cfg_data->ulp_flags); } +bool +bnxt_ulp_cntxt_multi_shared_session_enabled(struct bnxt_ulp_context *ulp_ctx) +{ + return ULP_MULTI_SHARED_IS_SUPPORTED(ulp_ctx); +} + int32_t bnxt_ulp_cntxt_app_id_set(struct bnxt_ulp_context *ulp_ctx, uint8_t app_id) { @@ -1721,74 +1935,86 @@ bnxt_ulp_cntxt_tbl_scope_id_set(struct bnxt_ulp_context *ulp_ctx, return -EINVAL; } -/* Function to set the shared tfp session details from the ulp context. */ -int32_t -bnxt_ulp_cntxt_shared_tfp_set(struct bnxt_ulp_context *ulp, struct tf *tfp) -{ - if (!ulp) { - BNXT_TF_DBG(ERR, "Invalid arguments\n"); - return -EINVAL; - } - - if (tfp == NULL) { - if (ulp->cfg_data->num_shared_clients > 0) - ulp->cfg_data->num_shared_clients--; - } else { - ulp->cfg_data->num_shared_clients++; - } - - ulp->g_shared_tfp = tfp; - return 0; -} - -/* Function to get the shared tfp session details from the ulp context. */ -struct tf * -bnxt_ulp_cntxt_shared_tfp_get(struct bnxt_ulp_context *ulp) +/* Function to get the number of shared clients attached */ +uint8_t +bnxt_ulp_cntxt_num_shared_clients_get(struct bnxt_ulp_context *ulp) { - if (!ulp) { + if (ulp == NULL || ulp->cfg_data == NULL) { BNXT_TF_DBG(ERR, "Invalid arguments\n"); - return NULL; + return 0; } - return ulp->g_shared_tfp; + return ulp->cfg_data->num_shared_clients; } -/* Function to get the number of shared clients attached */ -uint8_t -bnxt_ulp_cntxt_num_shared_clients_get(struct bnxt_ulp_context *ulp) +/* Function to set the number of shared clients */ +int +bnxt_ulp_cntxt_num_shared_clients_set(struct bnxt_ulp_context *ulp, bool incr) { if (ulp == NULL || ulp->cfg_data == NULL) { BNXT_TF_DBG(ERR, "Invalid arguments\n"); return 0; } - return ulp->cfg_data->num_shared_clients; + if (incr) + ulp->cfg_data->num_shared_clients++; + else if (ulp->cfg_data->num_shared_clients) + ulp->cfg_data->num_shared_clients--; + + BNXT_TF_DBG(DEBUG, "%d:clients(%d)\n", incr, + ulp->cfg_data->num_shared_clients); + + return 0; } /* Function to set the tfp session details from the ulp context. */ int32_t -bnxt_ulp_cntxt_tfp_set(struct bnxt_ulp_context *ulp, struct tf *tfp) +bnxt_ulp_cntxt_tfp_set(struct bnxt_ulp_context *ulp, + enum bnxt_ulp_session_type s_type, + struct tf *tfp) { + uint32_t idx = 0; + if (!ulp) { BNXT_TF_DBG(ERR, "Invalid arguments\n"); return -EINVAL; } + if (ULP_MULTI_SHARED_IS_SUPPORTED(ulp)) { + if (s_type & BNXT_ULP_SESSION_TYPE_SHARED) + idx = 1; + else if (s_type & BNXT_ULP_SESSION_TYPE_SHARED_WC) + idx = 2; + + } else { + if ((s_type & BNXT_ULP_SESSION_TYPE_SHARED) || + (s_type & BNXT_ULP_SESSION_TYPE_SHARED_WC)) + idx = 1; + } - ulp->g_tfp = tfp; + ulp->g_tfp[idx] = tfp; return 0; } /* Function to get the tfp session details from the ulp context. */ struct tf * bnxt_ulp_cntxt_tfp_get(struct bnxt_ulp_context *ulp, - enum bnxt_ulp_shared_session shared) + enum bnxt_ulp_session_type s_type) { + uint32_t idx = 0; + if (!ulp) { BNXT_TF_DBG(ERR, "Invalid arguments\n"); return NULL; } - if (shared) - return ulp->g_shared_tfp; - else - return ulp->g_tfp; + if (ULP_MULTI_SHARED_IS_SUPPORTED(ulp)) { + if (s_type & BNXT_ULP_SESSION_TYPE_SHARED) + idx = 1; + else if (s_type & BNXT_ULP_SESSION_TYPE_SHARED_WC) + idx = 2; + } else { + if ((s_type & BNXT_ULP_SESSION_TYPE_SHARED) || + (s_type & BNXT_ULP_SESSION_TYPE_SHARED_WC)) + idx = 1; + } + return ulp->g_tfp[idx]; } /* @@ -2079,3 +2305,41 @@ bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp) return ulp->cfg_data->app_tun; } + +/* Function to convert ulp dev id to regular dev id. */ +uint32_t +bnxt_ulp_cntxt_convert_dev_id(uint32_t ulp_dev_id) +{ + enum tf_device_type type = 0; + + switch (ulp_dev_id) { + case BNXT_ULP_DEVICE_ID_WH_PLUS: + type = TF_DEVICE_TYPE_P4; + break; + case BNXT_ULP_DEVICE_ID_STINGRAY: + type = TF_DEVICE_TYPE_SR; + break; + case BNXT_ULP_DEVICE_ID_THOR: + type = TF_DEVICE_TYPE_P5; + break; + default: + BNXT_TF_DBG(ERR, "Invalid device id\n"); + break; + } + return type; +} + +struct tf* +bnxt_ulp_bp_tfp_get(struct bnxt *bp, enum bnxt_ulp_session_type type) +{ + enum bnxt_session_type btype; + + if (type & BNXT_ULP_SESSION_TYPE_SHARED) + btype = BNXT_SESSION_TYPE_SHARED_COMMON; + else if (type & BNXT_ULP_SESSION_TYPE_SHARED_WC) + btype = BNXT_SESSION_TYPE_SHARED_WC; + else + btype = BNXT_SESSION_TYPE_REGULAR; + + return bnxt_get_tfp_session(bp, btype); +} diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index 906d933af5..9b30851b13 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ @@ -35,6 +35,11 @@ #define BNXT_ULP_HIGH_AVAIL_ENABLED 0x8 #define BNXT_ULP_APP_UNICAST_ONLY 0x10 #define BNXT_ULP_APP_SOCKET_DIRECT 0x20 +#define BNXT_ULP_APP_TOS_PROTO_SUPPORT 0x40 +#define BNXT_ULP_APP_BC_MC_SUPPORT 0x80 +#define BNXT_ULP_CUST_VXLAN_SUPPORT 0x100 +#define BNXT_ULP_MULTI_SHARED_SUPPORT 0x200 +#define BNXT_ULP_APP_HA_DYNAMIC 0x400 #define ULP_VF_REP_IS_ENABLED(flag) ((flag) & BNXT_ULP_VF_REP_ENABLED) #define ULP_SHARED_SESSION_IS_ENABLED(flag) ((flag) &\ @@ -43,6 +48,17 @@ BNXT_ULP_APP_DEV_UNSUPPORTED) #define ULP_HIGH_AVAIL_IS_ENABLED(flag) ((flag) & BNXT_ULP_HIGH_AVAIL_ENABLED) #define ULP_SOCKET_DIRECT_IS_ENABLED(flag) ((flag) & BNXT_ULP_APP_SOCKET_DIRECT) +#define ULP_APP_TOS_PROTO_SUPPORT(ctx) ((ctx)->cfg_data->ulp_flags &\ + BNXT_ULP_APP_TOS_PROTO_SUPPORT) +#define ULP_APP_BC_MC_SUPPORT(ctx) ((ctx)->cfg_data->ulp_flags &\ + BNXT_ULP_APP_BC_MC_SUPPORT) +#define ULP_MULTI_SHARED_IS_SUPPORTED(ctx) ((ctx)->cfg_data->ulp_flags &\ + BNXT_ULP_MULTI_SHARED_SUPPORT) +#define ULP_APP_HA_IS_DYNAMIC(ctx) ((ctx)->cfg_data->ulp_flags &\ + BNXT_ULP_APP_HA_DYNAMIC) + +#define ULP_APP_CUST_VXLAN_SUPPORT(ctx) ((ctx)->cfg_data->vxlan_port != 0) +#define ULP_APP_CUST_VXLAN_IP_SUPPORT(ctx) ((ctx)->cfg_data->vxlan_ip_port != 0) enum bnxt_ulp_flow_mem_type { BNXT_ULP_FLOW_MEM_TYPE_INT = 0, @@ -95,12 +111,19 @@ struct bnxt_ulp_data { uint8_t app_id; uint8_t num_shared_clients; struct bnxt_flow_app_tun_ent app_tun[BNXT_ULP_MAX_TUN_CACHE_ENTRIES]; + uint32_t vxlan_port; + uint32_t vxlan_ip_port; + uint8_t hu_reg_state; + uint8_t hu_reg_cnt; + uint32_t hu_session_type; + uint8_t ha_pool_id; + enum bnxt_ulp_session_type def_session_type; }; +#define BNXT_ULP_SESSION_MAX 3 struct bnxt_ulp_context { struct bnxt_ulp_data *cfg_data; - struct tf *g_tfp; - struct tf *g_shared_tfp; + struct tf *g_tfp[BNXT_ULP_SESSION_MAX]; }; struct bnxt_ulp_pci_info { @@ -110,13 +133,12 @@ struct bnxt_ulp_pci_info { struct bnxt_ulp_session_state { STAILQ_ENTRY(bnxt_ulp_session_state) next; - bool bnxt_ulp_init; - pthread_mutex_t bnxt_ulp_mutex; - struct bnxt_ulp_pci_info pci_info; - struct bnxt_ulp_data *cfg_data; - struct tf *g_tfp; - struct tf g_shared_tfp; - uint32_t session_opened; + bool bnxt_ulp_init; + pthread_mutex_t bnxt_ulp_mutex; + struct bnxt_ulp_pci_info pci_info; + struct bnxt_ulp_data *cfg_data; + struct tf *g_tfp[BNXT_ULP_SESSION_MAX]; + uint32_t session_opened[BNXT_ULP_SESSION_MAX]; }; /* ULP flow id structure */ @@ -172,20 +194,14 @@ bnxt_ulp_cntxt_tbl_scope_id_get(struct bnxt_ulp_context *ulp_ctx, /* Function to set the tfp session details in the ulp context. */ int32_t -bnxt_ulp_cntxt_shared_tfp_set(struct bnxt_ulp_context *ulp, struct tf *tfp); - -/* Function to get the tfp session details from ulp context. */ -struct tf * -bnxt_ulp_cntxt_shared_tfp_get(struct bnxt_ulp_context *ulp); - -/* Function to set the tfp session details in the ulp context. */ -int32_t -bnxt_ulp_cntxt_tfp_set(struct bnxt_ulp_context *ulp, struct tf *tfp); +bnxt_ulp_cntxt_tfp_set(struct bnxt_ulp_context *ulp, + enum bnxt_ulp_session_type s_type, + struct tf *tfp); /* Function to get the tfp session details from ulp context. */ struct tf * bnxt_ulp_cntxt_tfp_get(struct bnxt_ulp_context *ulp, - enum bnxt_ulp_shared_session shared); + enum bnxt_ulp_session_type s_type); /* Get the device table entry based on the device id. */ struct bnxt_ulp_device_params * @@ -238,6 +254,7 @@ int32_t ulp_default_flow_create(struct rte_eth_dev *eth_dev, struct ulp_tlv_param *param_list, uint32_t ulp_class_tid, + uint16_t port_id, uint32_t *flow_id); /* Function to destroy default flows. */ @@ -274,6 +291,20 @@ bnxt_ulp_cntxt_acquire_fdb_lock(struct bnxt_ulp_context *ulp_ctx); void bnxt_ulp_cntxt_release_fdb_lock(struct bnxt_ulp_context *ulp_ctx); +int32_t +bnxt_get_action_handle_type(const struct rte_flow_action_handle *handle, + uint32_t *action_handle_type); + +struct bnxt_ulp_shared_act_info * +bnxt_ulp_shared_act_info_get(uint32_t *num_entries); + +int32_t +bnxt_get_action_handle_direction(const struct rte_flow_action_handle *handle, + uint32_t *dir); + +uint32_t +bnxt_get_action_handle_index(const struct rte_flow_action_handle *handle); + struct bnxt_ulp_glb_resource_info * bnxt_ulp_app_glb_resource_info_list_get(uint32_t *num_entries); @@ -286,6 +317,9 @@ bnxt_ulp_cntxt_app_id_get(struct bnxt_ulp_context *ulp_ctx, uint8_t *app_id); bool bnxt_ulp_cntxt_shared_session_enabled(struct bnxt_ulp_context *ulp_ctx); +bool +bnxt_ulp_cntxt_multi_shared_session_enabled(struct bnxt_ulp_context *ulp_ctx); + struct bnxt_ulp_app_capabilities_info * bnxt_ulp_app_cap_list_get(uint32_t *num_entries); @@ -315,6 +349,41 @@ bnxt_ulp_cntxt_entry_release(void); uint8_t bnxt_ulp_cntxt_num_shared_clients_get(struct bnxt_ulp_context *ulp_ctx); +int +bnxt_ulp_cntxt_num_shared_clients_set(struct bnxt_ulp_context *ulp_ctx, + bool incr); + struct bnxt_flow_app_tun_ent * bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp); + +/* Function to get the truflow app id. This defined in the build file */ +uint32_t +bnxt_ulp_default_app_id_get(void); + +int +bnxt_ulp_vxlan_port_set(struct bnxt_ulp_context *ulp_ctx, + uint32_t vxlan_port); +unsigned int +bnxt_ulp_vxlan_port_get(struct bnxt_ulp_context *ulp_ctx); +int +bnxt_ulp_vxlan_ip_port_set(struct bnxt_ulp_context *ulp_ctx, + uint32_t vxlan_ip_port); +unsigned int +bnxt_ulp_vxlan_ip_port_get(struct bnxt_ulp_context *ulp_ctx); + +uint32_t +bnxt_ulp_cntxt_convert_dev_id(uint32_t ulp_dev_id); + +int32_t +bnxt_ulp_ha_reg_set(struct bnxt_ulp_context *ulp_ctx, + uint8_t state, uint8_t cnt); + +uint32_t +bnxt_ulp_ha_reg_state_get(struct bnxt_ulp_context *ulp_ctx); + +uint32_t +bnxt_ulp_ha_reg_cnt_get(struct bnxt_ulp_context *ulp_ctx); + +struct tf* +bnxt_ulp_bp_tfp_get(struct bnxt *bp, enum bnxt_ulp_session_type type); #endif /* _BNXT_ULP_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/meson.build b/drivers/net/bnxt/tf_ulp/generic_templates/meson.build index 4ace838a3c..b1b92e61ab 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/meson.build +++ b/drivers/net/bnxt/tf_ulp/generic_templates/meson.build @@ -2,15 +2,13 @@ # Copyright(c) 2018 Intel Corporation # Copyright(c) 2020 Broadcom -#Include the folder for headers includes += include_directories('.') - -#Add the source files sources += files( - 'ulp_template_db_class.c', - 'ulp_template_db_act.c', - 'ulp_template_db_tbl.c', - 'ulp_template_db_wh_plus_act.c', - 'ulp_template_db_wh_plus_class.c', - 'ulp_template_db_thor_act.c', - 'ulp_template_db_thor_class.c') + 'ulp_template_db_class.c', + 'ulp_template_db_act.c', + 'ulp_template_db_tbl.c', + 'ulp_template_db_wh_plus_act.c', + 'ulp_template_db_wh_plus_class.c', + 'ulp_template_db_thor_act.c', + 'ulp_template_db_thor_class.c') + diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c index ce878d8e02..c626fc64f5 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c @@ -1,10 +1,8 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ -/* date: Wed Aug 25 14:37:06 2021 */ - #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" #include "ulp_template_struct.h" @@ -16,98 +14,550 @@ */ uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = { [BNXT_ULP_ACT_HID_0000] = 1, - [BNXT_ULP_ACT_HID_0001] = 2, - [BNXT_ULP_ACT_HID_0400] = 3, - [BNXT_ULP_ACT_HID_01ab] = 4, - [BNXT_ULP_ACT_HID_0010] = 5, - [BNXT_ULP_ACT_HID_05ab] = 6, - [BNXT_ULP_ACT_HID_01bb] = 7, - [BNXT_ULP_ACT_HID_0002] = 8, - [BNXT_ULP_ACT_HID_0003] = 9, - [BNXT_ULP_ACT_HID_0402] = 10, - [BNXT_ULP_ACT_HID_01ad] = 11, - [BNXT_ULP_ACT_HID_0012] = 12, - [BNXT_ULP_ACT_HID_05ad] = 13, - [BNXT_ULP_ACT_HID_01bd] = 14, - [BNXT_ULP_ACT_HID_0613] = 15, - [BNXT_ULP_ACT_HID_02a9] = 16, - [BNXT_ULP_ACT_HID_0054] = 17, - [BNXT_ULP_ACT_HID_0622] = 18, - [BNXT_ULP_ACT_HID_0454] = 19, - [BNXT_ULP_ACT_HID_0064] = 20, - [BNXT_ULP_ACT_HID_0614] = 21, - [BNXT_ULP_ACT_HID_0615] = 22, - [BNXT_ULP_ACT_HID_02ab] = 23, - [BNXT_ULP_ACT_HID_0056] = 24, - [BNXT_ULP_ACT_HID_0624] = 25, - [BNXT_ULP_ACT_HID_0456] = 26, - [BNXT_ULP_ACT_HID_0066] = 27, - [BNXT_ULP_ACT_HID_048d] = 28, - [BNXT_ULP_ACT_HID_048f] = 29, - [BNXT_ULP_ACT_HID_04bc] = 30, - [BNXT_ULP_ACT_HID_00a9] = 31, - [BNXT_ULP_ACT_HID_020f] = 32, - [BNXT_ULP_ACT_HID_0153] = 33, - [BNXT_ULP_ACT_HID_04a9] = 34, - [BNXT_ULP_ACT_HID_01fc] = 35, - [BNXT_ULP_ACT_HID_04be] = 36, - [BNXT_ULP_ACT_HID_00ab] = 37, - [BNXT_ULP_ACT_HID_0211] = 38, - [BNXT_ULP_ACT_HID_0155] = 39, - [BNXT_ULP_ACT_HID_04ab] = 40, - [BNXT_ULP_ACT_HID_01fe] = 41, - [BNXT_ULP_ACT_HID_0667] = 42, - [BNXT_ULP_ACT_HID_0254] = 43, - [BNXT_ULP_ACT_HID_03ba] = 44, - [BNXT_ULP_ACT_HID_02fe] = 45, - [BNXT_ULP_ACT_HID_0654] = 46, - [BNXT_ULP_ACT_HID_03a7] = 47, - [BNXT_ULP_ACT_HID_0669] = 48, - [BNXT_ULP_ACT_HID_0256] = 49, - [BNXT_ULP_ACT_HID_03bc] = 50, - [BNXT_ULP_ACT_HID_0300] = 51, - [BNXT_ULP_ACT_HID_0656] = 52, - [BNXT_ULP_ACT_HID_03a9] = 53, - [BNXT_ULP_ACT_HID_021b] = 54, - [BNXT_ULP_ACT_HID_021c] = 55, - [BNXT_ULP_ACT_HID_021e] = 56, - [BNXT_ULP_ACT_HID_063f] = 57, - [BNXT_ULP_ACT_HID_0510] = 58, - [BNXT_ULP_ACT_HID_03c6] = 59, - [BNXT_ULP_ACT_HID_0082] = 60, - [BNXT_ULP_ACT_HID_06bb] = 61, - [BNXT_ULP_ACT_HID_021d] = 62, - [BNXT_ULP_ACT_HID_0641] = 63, - [BNXT_ULP_ACT_HID_0512] = 64, - [BNXT_ULP_ACT_HID_03c8] = 65, - [BNXT_ULP_ACT_HID_0084] = 66, - [BNXT_ULP_ACT_HID_06bd] = 67, - [BNXT_ULP_ACT_HID_06d7] = 68, - [BNXT_ULP_ACT_HID_02c4] = 69, - [BNXT_ULP_ACT_HID_042a] = 70, - [BNXT_ULP_ACT_HID_036e] = 71, - [BNXT_ULP_ACT_HID_06c4] = 72, - [BNXT_ULP_ACT_HID_0417] = 73, - [BNXT_ULP_ACT_HID_06d9] = 74, - [BNXT_ULP_ACT_HID_02c6] = 75, - [BNXT_ULP_ACT_HID_042c] = 76, - [BNXT_ULP_ACT_HID_0370] = 77, - [BNXT_ULP_ACT_HID_06c6] = 78, - [BNXT_ULP_ACT_HID_0419] = 79, - [BNXT_ULP_ACT_HID_0119] = 80, - [BNXT_ULP_ACT_HID_046f] = 81, - [BNXT_ULP_ACT_HID_05d5] = 82, - [BNXT_ULP_ACT_HID_0519] = 83, - [BNXT_ULP_ACT_HID_0106] = 84, - [BNXT_ULP_ACT_HID_05c2] = 85, - [BNXT_ULP_ACT_HID_011b] = 86, - [BNXT_ULP_ACT_HID_0471] = 87, - [BNXT_ULP_ACT_HID_05d7] = 88, - [BNXT_ULP_ACT_HID_051b] = 89, - [BNXT_ULP_ACT_HID_0108] = 90, - [BNXT_ULP_ACT_HID_05c4] = 91, - [BNXT_ULP_ACT_HID_00a2] = 92, - [BNXT_ULP_ACT_HID_00a4] = 93 + [BNXT_ULP_ACT_HID_0008] = 2, + [BNXT_ULP_ACT_HID_2000] = 3, + [BNXT_ULP_ACT_HID_1988] = 4, + [BNXT_ULP_ACT_HID_0080] = 5, + [BNXT_ULP_ACT_HID_3988] = 6, + [BNXT_ULP_ACT_HID_1a08] = 7, + [BNXT_ULP_ACT_HID_0010] = 8, + [BNXT_ULP_ACT_HID_0040] = 9, + [BNXT_ULP_ACT_HID_0050] = 10, + [BNXT_ULP_ACT_HID_0018] = 11, + [BNXT_ULP_ACT_HID_2010] = 12, + [BNXT_ULP_ACT_HID_1998] = 13, + [BNXT_ULP_ACT_HID_0090] = 14, + [BNXT_ULP_ACT_HID_3998] = 15, + [BNXT_ULP_ACT_HID_1a18] = 16, + [BNXT_ULP_ACT_HID_32ea] = 17, + [BNXT_ULP_ACT_HID_32f2] = 18, + [BNXT_ULP_ACT_HID_52ea] = 19, + [BNXT_ULP_ACT_HID_4c72] = 20, + [BNXT_ULP_ACT_HID_336a] = 21, + [BNXT_ULP_ACT_HID_6c72] = 22, + [BNXT_ULP_ACT_HID_4cf2] = 23, + [BNXT_ULP_ACT_HID_32fa] = 24, + [BNXT_ULP_ACT_HID_3302] = 25, + [BNXT_ULP_ACT_HID_52fa] = 26, + [BNXT_ULP_ACT_HID_4c82] = 27, + [BNXT_ULP_ACT_HID_337a] = 28, + [BNXT_ULP_ACT_HID_6c82] = 29, + [BNXT_ULP_ACT_HID_4d02] = 30, + [BNXT_ULP_ACT_HID_0808] = 31, + [BNXT_ULP_ACT_HID_1008] = 32, + [BNXT_ULP_ACT_HID_1808] = 33, + [BNXT_ULP_ACT_HID_0818] = 34, + [BNXT_ULP_ACT_HID_1018] = 35, + [BNXT_ULP_ACT_HID_1818] = 36, + [BNXT_ULP_ACT_HID_0880] = 37, + [BNXT_ULP_ACT_HID_1080] = 38, + [BNXT_ULP_ACT_HID_1880] = 39, + [BNXT_ULP_ACT_HID_0890] = 40, + [BNXT_ULP_ACT_HID_1090] = 41, + [BNXT_ULP_ACT_HID_1890] = 42, + [BNXT_ULP_ACT_HID_3af2] = 43, + [BNXT_ULP_ACT_HID_42f2] = 44, + [BNXT_ULP_ACT_HID_4af2] = 45, + [BNXT_ULP_ACT_HID_3b02] = 46, + [BNXT_ULP_ACT_HID_4302] = 47, + [BNXT_ULP_ACT_HID_4b02] = 48, + [BNXT_ULP_ACT_HID_3b6a] = 49, + [BNXT_ULP_ACT_HID_436a] = 50, + [BNXT_ULP_ACT_HID_4b6a] = 51, + [BNXT_ULP_ACT_HID_3b7a] = 52, + [BNXT_ULP_ACT_HID_437a] = 53, + [BNXT_ULP_ACT_HID_4b7a] = 54, + [BNXT_ULP_ACT_HID_640d] = 55, + [BNXT_ULP_ACT_HID_641d] = 56, + [BNXT_ULP_ACT_HID_071a] = 57, + [BNXT_ULP_ACT_HID_0800] = 58, + [BNXT_ULP_ACT_HID_1000] = 59, + [BNXT_ULP_ACT_HID_1800] = 60, + [BNXT_ULP_ACT_HID_0810] = 61, + [BNXT_ULP_ACT_HID_1010] = 62, + [BNXT_ULP_ACT_HID_1810] = 63, + [BNXT_ULP_ACT_HID_1110] = 64, + [BNXT_ULP_ACT_HID_4420] = 65, + [BNXT_ULP_ACT_HID_2220] = 66, + [BNXT_ULP_ACT_HID_0c84] = 67, + [BNXT_ULP_ACT_HID_3f94] = 68, + [BNXT_ULP_ACT_HID_3330] = 69, + [BNXT_ULP_ACT_HID_50a4] = 70, + [BNXT_ULP_ACT_HID_1910] = 71, + [BNXT_ULP_ACT_HID_4c20] = 72, + [BNXT_ULP_ACT_HID_2a20] = 73, + [BNXT_ULP_ACT_HID_1484] = 74, + [BNXT_ULP_ACT_HID_4794] = 75, + [BNXT_ULP_ACT_HID_3b30] = 76, + [BNXT_ULP_ACT_HID_58a4] = 77, + [BNXT_ULP_ACT_HID_2110] = 78, + [BNXT_ULP_ACT_HID_5420] = 79, + [BNXT_ULP_ACT_HID_3220] = 80, + [BNXT_ULP_ACT_HID_1c84] = 81, + [BNXT_ULP_ACT_HID_4f94] = 82, + [BNXT_ULP_ACT_HID_4330] = 83, + [BNXT_ULP_ACT_HID_60a4] = 84, + [BNXT_ULP_ACT_HID_2910] = 85, + [BNXT_ULP_ACT_HID_5c20] = 86, + [BNXT_ULP_ACT_HID_3a20] = 87, + [BNXT_ULP_ACT_HID_2484] = 88, + [BNXT_ULP_ACT_HID_5794] = 89, + [BNXT_ULP_ACT_HID_4b30] = 90, + [BNXT_ULP_ACT_HID_68a4] = 91, + [BNXT_ULP_ACT_HID_1120] = 92, + [BNXT_ULP_ACT_HID_4430] = 93, + [BNXT_ULP_ACT_HID_2230] = 94, + [BNXT_ULP_ACT_HID_0c94] = 95, + [BNXT_ULP_ACT_HID_3fa4] = 96, + [BNXT_ULP_ACT_HID_3340] = 97, + [BNXT_ULP_ACT_HID_50b4] = 98, + [BNXT_ULP_ACT_HID_1920] = 99, + [BNXT_ULP_ACT_HID_4c30] = 100, + [BNXT_ULP_ACT_HID_2a30] = 101, + [BNXT_ULP_ACT_HID_1494] = 102, + [BNXT_ULP_ACT_HID_47a4] = 103, + [BNXT_ULP_ACT_HID_3b40] = 104, + [BNXT_ULP_ACT_HID_58b4] = 105, + [BNXT_ULP_ACT_HID_2120] = 106, + [BNXT_ULP_ACT_HID_5430] = 107, + [BNXT_ULP_ACT_HID_3230] = 108, + [BNXT_ULP_ACT_HID_1c94] = 109, + [BNXT_ULP_ACT_HID_4fa4] = 110, + [BNXT_ULP_ACT_HID_4340] = 111, + [BNXT_ULP_ACT_HID_60b4] = 112, + [BNXT_ULP_ACT_HID_2920] = 113, + [BNXT_ULP_ACT_HID_5c30] = 114, + [BNXT_ULP_ACT_HID_3a30] = 115, + [BNXT_ULP_ACT_HID_2494] = 116, + [BNXT_ULP_ACT_HID_57a4] = 117, + [BNXT_ULP_ACT_HID_4b40] = 118, + [BNXT_ULP_ACT_HID_68b4] = 119, + [BNXT_ULP_ACT_HID_2a98] = 120, + [BNXT_ULP_ACT_HID_5da8] = 121, + [BNXT_ULP_ACT_HID_3ba8] = 122, + [BNXT_ULP_ACT_HID_260c] = 123, + [BNXT_ULP_ACT_HID_591c] = 124, + [BNXT_ULP_ACT_HID_6a2c] = 125, + [BNXT_ULP_ACT_HID_2aa8] = 126, + [BNXT_ULP_ACT_HID_5db8] = 127, + [BNXT_ULP_ACT_HID_3bb8] = 128, + [BNXT_ULP_ACT_HID_261c] = 129, + [BNXT_ULP_ACT_HID_592c] = 130, + [BNXT_ULP_ACT_HID_6a3c] = 131, + [BNXT_ULP_ACT_HID_3298] = 132, + [BNXT_ULP_ACT_HID_65a8] = 133, + [BNXT_ULP_ACT_HID_43a8] = 134, + [BNXT_ULP_ACT_HID_2e0c] = 135, + [BNXT_ULP_ACT_HID_611c] = 136, + [BNXT_ULP_ACT_HID_722c] = 137, + [BNXT_ULP_ACT_HID_32a8] = 138, + [BNXT_ULP_ACT_HID_65b8] = 139, + [BNXT_ULP_ACT_HID_43b8] = 140, + [BNXT_ULP_ACT_HID_2e1c] = 141, + [BNXT_ULP_ACT_HID_612c] = 142, + [BNXT_ULP_ACT_HID_723c] = 143, + [BNXT_ULP_ACT_HID_3a98] = 144, + [BNXT_ULP_ACT_HID_6da8] = 145, + [BNXT_ULP_ACT_HID_4ba8] = 146, + [BNXT_ULP_ACT_HID_360c] = 147, + [BNXT_ULP_ACT_HID_691c] = 148, + [BNXT_ULP_ACT_HID_7a2c] = 149, + [BNXT_ULP_ACT_HID_3aa8] = 150, + [BNXT_ULP_ACT_HID_6db8] = 151, + [BNXT_ULP_ACT_HID_4bb8] = 152, + [BNXT_ULP_ACT_HID_361c] = 153, + [BNXT_ULP_ACT_HID_692c] = 154, + [BNXT_ULP_ACT_HID_7a3c] = 155, + [BNXT_ULP_ACT_HID_4298] = 156, + [BNXT_ULP_ACT_HID_75a8] = 157, + [BNXT_ULP_ACT_HID_53a8] = 158, + [BNXT_ULP_ACT_HID_3e0c] = 159, + [BNXT_ULP_ACT_HID_711c] = 160, + [BNXT_ULP_ACT_HID_0670] = 161, + [BNXT_ULP_ACT_HID_42a8] = 162, + [BNXT_ULP_ACT_HID_75b8] = 163, + [BNXT_ULP_ACT_HID_53b8] = 164, + [BNXT_ULP_ACT_HID_3e1c] = 165, + [BNXT_ULP_ACT_HID_712c] = 166, + [BNXT_ULP_ACT_HID_0680] = 167, + [BNXT_ULP_ACT_HID_3aea] = 168, + [BNXT_ULP_ACT_HID_42ea] = 169, + [BNXT_ULP_ACT_HID_4aea] = 170, + [BNXT_ULP_ACT_HID_3afa] = 171, + [BNXT_ULP_ACT_HID_42fa] = 172, + [BNXT_ULP_ACT_HID_4afa] = 173, + [BNXT_ULP_ACT_HID_43fa] = 174, + [BNXT_ULP_ACT_HID_770a] = 175, + [BNXT_ULP_ACT_HID_550a] = 176, + [BNXT_ULP_ACT_HID_3f6e] = 177, + [BNXT_ULP_ACT_HID_727e] = 178, + [BNXT_ULP_ACT_HID_661a] = 179, + [BNXT_ULP_ACT_HID_07d2] = 180, + [BNXT_ULP_ACT_HID_4bfa] = 181, + [BNXT_ULP_ACT_HID_034e] = 182, + [BNXT_ULP_ACT_HID_5d0a] = 183, + [BNXT_ULP_ACT_HID_476e] = 184, + [BNXT_ULP_ACT_HID_7a7e] = 185, + [BNXT_ULP_ACT_HID_6e1a] = 186, + [BNXT_ULP_ACT_HID_0fd2] = 187, + [BNXT_ULP_ACT_HID_53fa] = 188, + [BNXT_ULP_ACT_HID_0b4e] = 189, + [BNXT_ULP_ACT_HID_650a] = 190, + [BNXT_ULP_ACT_HID_4f6e] = 191, + [BNXT_ULP_ACT_HID_06c2] = 192, + [BNXT_ULP_ACT_HID_761a] = 193, + [BNXT_ULP_ACT_HID_17d2] = 194, + [BNXT_ULP_ACT_HID_5bfa] = 195, + [BNXT_ULP_ACT_HID_134e] = 196, + [BNXT_ULP_ACT_HID_6d0a] = 197, + [BNXT_ULP_ACT_HID_576e] = 198, + [BNXT_ULP_ACT_HID_0ec2] = 199, + [BNXT_ULP_ACT_HID_025e] = 200, + [BNXT_ULP_ACT_HID_1fd2] = 201, + [BNXT_ULP_ACT_HID_440a] = 202, + [BNXT_ULP_ACT_HID_771a] = 203, + [BNXT_ULP_ACT_HID_551a] = 204, + [BNXT_ULP_ACT_HID_3f7e] = 205, + [BNXT_ULP_ACT_HID_728e] = 206, + [BNXT_ULP_ACT_HID_662a] = 207, + [BNXT_ULP_ACT_HID_07e2] = 208, + [BNXT_ULP_ACT_HID_4c0a] = 209, + [BNXT_ULP_ACT_HID_035e] = 210, + [BNXT_ULP_ACT_HID_5d1a] = 211, + [BNXT_ULP_ACT_HID_477e] = 212, + [BNXT_ULP_ACT_HID_7a8e] = 213, + [BNXT_ULP_ACT_HID_6e2a] = 214, + [BNXT_ULP_ACT_HID_0fe2] = 215, + [BNXT_ULP_ACT_HID_540a] = 216, + [BNXT_ULP_ACT_HID_0b5e] = 217, + [BNXT_ULP_ACT_HID_651a] = 218, + [BNXT_ULP_ACT_HID_4f7e] = 219, + [BNXT_ULP_ACT_HID_06d2] = 220, + [BNXT_ULP_ACT_HID_762a] = 221, + [BNXT_ULP_ACT_HID_17e2] = 222, + [BNXT_ULP_ACT_HID_5c0a] = 223, + [BNXT_ULP_ACT_HID_135e] = 224, + [BNXT_ULP_ACT_HID_6d1a] = 225, + [BNXT_ULP_ACT_HID_577e] = 226, + [BNXT_ULP_ACT_HID_0ed2] = 227, + [BNXT_ULP_ACT_HID_026e] = 228, + [BNXT_ULP_ACT_HID_1fe2] = 229, + [BNXT_ULP_ACT_HID_5d82] = 230, + [BNXT_ULP_ACT_HID_14d6] = 231, + [BNXT_ULP_ACT_HID_6e92] = 232, + [BNXT_ULP_ACT_HID_58f6] = 233, + [BNXT_ULP_ACT_HID_104a] = 234, + [BNXT_ULP_ACT_HID_215a] = 235, + [BNXT_ULP_ACT_HID_5d92] = 236, + [BNXT_ULP_ACT_HID_14e6] = 237, + [BNXT_ULP_ACT_HID_6ea2] = 238, + [BNXT_ULP_ACT_HID_5906] = 239, + [BNXT_ULP_ACT_HID_105a] = 240, + [BNXT_ULP_ACT_HID_216a] = 241, + [BNXT_ULP_ACT_HID_6582] = 242, + [BNXT_ULP_ACT_HID_1cd6] = 243, + [BNXT_ULP_ACT_HID_7692] = 244, + [BNXT_ULP_ACT_HID_60f6] = 245, + [BNXT_ULP_ACT_HID_184a] = 246, + [BNXT_ULP_ACT_HID_295a] = 247, + [BNXT_ULP_ACT_HID_6592] = 248, + [BNXT_ULP_ACT_HID_1ce6] = 249, + [BNXT_ULP_ACT_HID_76a2] = 250, + [BNXT_ULP_ACT_HID_6106] = 251, + [BNXT_ULP_ACT_HID_185a] = 252, + [BNXT_ULP_ACT_HID_296a] = 253, + [BNXT_ULP_ACT_HID_6d82] = 254, + [BNXT_ULP_ACT_HID_24d6] = 255, + [BNXT_ULP_ACT_HID_02d6] = 256, + [BNXT_ULP_ACT_HID_68f6] = 257, + [BNXT_ULP_ACT_HID_204a] = 258, + [BNXT_ULP_ACT_HID_315a] = 259, + [BNXT_ULP_ACT_HID_6d92] = 260, + [BNXT_ULP_ACT_HID_24e6] = 261, + [BNXT_ULP_ACT_HID_02e6] = 262, + [BNXT_ULP_ACT_HID_6906] = 263, + [BNXT_ULP_ACT_HID_205a] = 264, + [BNXT_ULP_ACT_HID_316a] = 265, + [BNXT_ULP_ACT_HID_7582] = 266, + [BNXT_ULP_ACT_HID_2cd6] = 267, + [BNXT_ULP_ACT_HID_0ad6] = 268, + [BNXT_ULP_ACT_HID_70f6] = 269, + [BNXT_ULP_ACT_HID_284a] = 270, + [BNXT_ULP_ACT_HID_395a] = 271, + [BNXT_ULP_ACT_HID_7592] = 272, + [BNXT_ULP_ACT_HID_2ce6] = 273, + [BNXT_ULP_ACT_HID_0ae6] = 274, + [BNXT_ULP_ACT_HID_7106] = 275, + [BNXT_ULP_ACT_HID_285a] = 276, + [BNXT_ULP_ACT_HID_396a] = 277, + [BNXT_ULP_ACT_HID_0020] = 278, + [BNXT_ULP_ACT_HID_0030] = 279, + [BNXT_ULP_ACT_HID_65d4] = 280, + [BNXT_ULP_ACT_HID_65e4] = 281, + [BNXT_ULP_ACT_HID_330a] = 282, + [BNXT_ULP_ACT_HID_331a] = 283, + [BNXT_ULP_ACT_HID_1cfe] = 284, + [BNXT_ULP_ACT_HID_1d0e] = 285, + [BNXT_ULP_ACT_HID_1474] = 286, + [BNXT_ULP_ACT_HID_4838] = 287, + [BNXT_ULP_ACT_HID_6458] = 288, + [BNXT_ULP_ACT_HID_1c68] = 289, + [BNXT_ULP_ACT_HID_6c34] = 290, + [BNXT_ULP_ACT_HID_5d08] = 291, + [BNXT_ULP_ACT_HID_5d10] = 292, + [BNXT_ULP_ACT_HID_5d20] = 293, + [BNXT_ULP_ACT_HID_2e18] = 294, + [BNXT_ULP_ACT_HID_29d4] = 295, + [BNXT_ULP_ACT_HID_7690] = 296, + [BNXT_ULP_ACT_HID_47a0] = 297, + [BNXT_ULP_ACT_HID_435c] = 298, + [BNXT_ULP_ACT_HID_5d18] = 299, + [BNXT_ULP_ACT_HID_2e28] = 300, + [BNXT_ULP_ACT_HID_29e4] = 301, + [BNXT_ULP_ACT_HID_76a0] = 302, + [BNXT_ULP_ACT_HID_47b0] = 303, + [BNXT_ULP_ACT_HID_436c] = 304, + [BNXT_ULP_ACT_HID_1436] = 305, + [BNXT_ULP_ACT_HID_143e] = 306, + [BNXT_ULP_ACT_HID_144e] = 307, + [BNXT_ULP_ACT_HID_6102] = 308, + [BNXT_ULP_ACT_HID_5cbe] = 309, + [BNXT_ULP_ACT_HID_2dbe] = 310, + [BNXT_ULP_ACT_HID_7a8a] = 311, + [BNXT_ULP_ACT_HID_7646] = 312, + [BNXT_ULP_ACT_HID_1446] = 313, + [BNXT_ULP_ACT_HID_6112] = 314, + [BNXT_ULP_ACT_HID_5cce] = 315, + [BNXT_ULP_ACT_HID_2dce] = 316, + [BNXT_ULP_ACT_HID_7a9a] = 317, + [BNXT_ULP_ACT_HID_7656] = 318, + [BNXT_ULP_ACT_HID_6508] = 319, + [BNXT_ULP_ACT_HID_6d08] = 320, + [BNXT_ULP_ACT_HID_7508] = 321, + [BNXT_ULP_ACT_HID_6518] = 322, + [BNXT_ULP_ACT_HID_6d18] = 323, + [BNXT_ULP_ACT_HID_7518] = 324, + [BNXT_ULP_ACT_HID_6e18] = 325, + [BNXT_ULP_ACT_HID_256c] = 326, + [BNXT_ULP_ACT_HID_036c] = 327, + [BNXT_ULP_ACT_HID_698c] = 328, + [BNXT_ULP_ACT_HID_20e0] = 329, + [BNXT_ULP_ACT_HID_31f0] = 330, + [BNXT_ULP_ACT_HID_7618] = 331, + [BNXT_ULP_ACT_HID_2d6c] = 332, + [BNXT_ULP_ACT_HID_0b6c] = 333, + [BNXT_ULP_ACT_HID_718c] = 334, + [BNXT_ULP_ACT_HID_28e0] = 335, + [BNXT_ULP_ACT_HID_39f0] = 336, + [BNXT_ULP_ACT_HID_025c] = 337, + [BNXT_ULP_ACT_HID_356c] = 338, + [BNXT_ULP_ACT_HID_136c] = 339, + [BNXT_ULP_ACT_HID_798c] = 340, + [BNXT_ULP_ACT_HID_30e0] = 341, + [BNXT_ULP_ACT_HID_41f0] = 342, + [BNXT_ULP_ACT_HID_0a5c] = 343, + [BNXT_ULP_ACT_HID_3d6c] = 344, + [BNXT_ULP_ACT_HID_1b6c] = 345, + [BNXT_ULP_ACT_HID_05d0] = 346, + [BNXT_ULP_ACT_HID_38e0] = 347, + [BNXT_ULP_ACT_HID_49f0] = 348, + [BNXT_ULP_ACT_HID_6e28] = 349, + [BNXT_ULP_ACT_HID_257c] = 350, + [BNXT_ULP_ACT_HID_037c] = 351, + [BNXT_ULP_ACT_HID_699c] = 352, + [BNXT_ULP_ACT_HID_20f0] = 353, + [BNXT_ULP_ACT_HID_3200] = 354, + [BNXT_ULP_ACT_HID_7628] = 355, + [BNXT_ULP_ACT_HID_2d7c] = 356, + [BNXT_ULP_ACT_HID_0b7c] = 357, + [BNXT_ULP_ACT_HID_719c] = 358, + [BNXT_ULP_ACT_HID_28f0] = 359, + [BNXT_ULP_ACT_HID_3a00] = 360, + [BNXT_ULP_ACT_HID_026c] = 361, + [BNXT_ULP_ACT_HID_357c] = 362, + [BNXT_ULP_ACT_HID_137c] = 363, + [BNXT_ULP_ACT_HID_799c] = 364, + [BNXT_ULP_ACT_HID_30f0] = 365, + [BNXT_ULP_ACT_HID_4200] = 366, + [BNXT_ULP_ACT_HID_0a6c] = 367, + [BNXT_ULP_ACT_HID_3d7c] = 368, + [BNXT_ULP_ACT_HID_1b7c] = 369, + [BNXT_ULP_ACT_HID_05e0] = 370, + [BNXT_ULP_ACT_HID_38f0] = 371, + [BNXT_ULP_ACT_HID_4a00] = 372, + [BNXT_ULP_ACT_HID_0be4] = 373, + [BNXT_ULP_ACT_HID_3ef4] = 374, + [BNXT_ULP_ACT_HID_1cf4] = 375, + [BNXT_ULP_ACT_HID_0758] = 376, + [BNXT_ULP_ACT_HID_3a68] = 377, + [BNXT_ULP_ACT_HID_4b78] = 378, + [BNXT_ULP_ACT_HID_0bf4] = 379, + [BNXT_ULP_ACT_HID_3f04] = 380, + [BNXT_ULP_ACT_HID_1d04] = 381, + [BNXT_ULP_ACT_HID_0768] = 382, + [BNXT_ULP_ACT_HID_3a78] = 383, + [BNXT_ULP_ACT_HID_4b88] = 384, + [BNXT_ULP_ACT_HID_46f4] = 385, + [BNXT_ULP_ACT_HID_24f4] = 386, + [BNXT_ULP_ACT_HID_0f58] = 387, + [BNXT_ULP_ACT_HID_13e4] = 388, + [BNXT_ULP_ACT_HID_4268] = 389, + [BNXT_ULP_ACT_HID_5378] = 390, + [BNXT_ULP_ACT_HID_13f4] = 391, + [BNXT_ULP_ACT_HID_4704] = 392, + [BNXT_ULP_ACT_HID_2504] = 393, + [BNXT_ULP_ACT_HID_0f68] = 394, + [BNXT_ULP_ACT_HID_4278] = 395, + [BNXT_ULP_ACT_HID_5388] = 396, + [BNXT_ULP_ACT_HID_1be4] = 397, + [BNXT_ULP_ACT_HID_4ef4] = 398, + [BNXT_ULP_ACT_HID_2cf4] = 399, + [BNXT_ULP_ACT_HID_1758] = 400, + [BNXT_ULP_ACT_HID_4a68] = 401, + [BNXT_ULP_ACT_HID_5b78] = 402, + [BNXT_ULP_ACT_HID_1bf4] = 403, + [BNXT_ULP_ACT_HID_4f04] = 404, + [BNXT_ULP_ACT_HID_2d04] = 405, + [BNXT_ULP_ACT_HID_1768] = 406, + [BNXT_ULP_ACT_HID_4a78] = 407, + [BNXT_ULP_ACT_HID_5b88] = 408, + [BNXT_ULP_ACT_HID_23e4] = 409, + [BNXT_ULP_ACT_HID_56f4] = 410, + [BNXT_ULP_ACT_HID_34f4] = 411, + [BNXT_ULP_ACT_HID_1f58] = 412, + [BNXT_ULP_ACT_HID_5268] = 413, + [BNXT_ULP_ACT_HID_6378] = 414, + [BNXT_ULP_ACT_HID_23f4] = 415, + [BNXT_ULP_ACT_HID_5704] = 416, + [BNXT_ULP_ACT_HID_3504] = 417, + [BNXT_ULP_ACT_HID_1f68] = 418, + [BNXT_ULP_ACT_HID_5278] = 419, + [BNXT_ULP_ACT_HID_6388] = 420, + [BNXT_ULP_ACT_HID_1c36] = 421, + [BNXT_ULP_ACT_HID_2436] = 422, + [BNXT_ULP_ACT_HID_2c36] = 423, + [BNXT_ULP_ACT_HID_1c46] = 424, + [BNXT_ULP_ACT_HID_2446] = 425, + [BNXT_ULP_ACT_HID_2c46] = 426, + [BNXT_ULP_ACT_HID_2546] = 427, + [BNXT_ULP_ACT_HID_5856] = 428, + [BNXT_ULP_ACT_HID_3656] = 429, + [BNXT_ULP_ACT_HID_20ba] = 430, + [BNXT_ULP_ACT_HID_53ca] = 431, + [BNXT_ULP_ACT_HID_64da] = 432, + [BNXT_ULP_ACT_HID_2d46] = 433, + [BNXT_ULP_ACT_HID_6056] = 434, + [BNXT_ULP_ACT_HID_3e56] = 435, + [BNXT_ULP_ACT_HID_28ba] = 436, + [BNXT_ULP_ACT_HID_5bca] = 437, + [BNXT_ULP_ACT_HID_6cda] = 438, + [BNXT_ULP_ACT_HID_3546] = 439, + [BNXT_ULP_ACT_HID_6856] = 440, + [BNXT_ULP_ACT_HID_4656] = 441, + [BNXT_ULP_ACT_HID_30ba] = 442, + [BNXT_ULP_ACT_HID_63ca] = 443, + [BNXT_ULP_ACT_HID_74da] = 444, + [BNXT_ULP_ACT_HID_3d46] = 445, + [BNXT_ULP_ACT_HID_7056] = 446, + [BNXT_ULP_ACT_HID_4e56] = 447, + [BNXT_ULP_ACT_HID_38ba] = 448, + [BNXT_ULP_ACT_HID_6bca] = 449, + [BNXT_ULP_ACT_HID_011e] = 450, + [BNXT_ULP_ACT_HID_2556] = 451, + [BNXT_ULP_ACT_HID_5866] = 452, + [BNXT_ULP_ACT_HID_3666] = 453, + [BNXT_ULP_ACT_HID_20ca] = 454, + [BNXT_ULP_ACT_HID_53da] = 455, + [BNXT_ULP_ACT_HID_64ea] = 456, + [BNXT_ULP_ACT_HID_2d56] = 457, + [BNXT_ULP_ACT_HID_6066] = 458, + [BNXT_ULP_ACT_HID_3e66] = 459, + [BNXT_ULP_ACT_HID_28ca] = 460, + [BNXT_ULP_ACT_HID_5bda] = 461, + [BNXT_ULP_ACT_HID_6cea] = 462, + [BNXT_ULP_ACT_HID_3556] = 463, + [BNXT_ULP_ACT_HID_6866] = 464, + [BNXT_ULP_ACT_HID_4666] = 465, + [BNXT_ULP_ACT_HID_30ca] = 466, + [BNXT_ULP_ACT_HID_63da] = 467, + [BNXT_ULP_ACT_HID_74ea] = 468, + [BNXT_ULP_ACT_HID_3d56] = 469, + [BNXT_ULP_ACT_HID_7066] = 470, + [BNXT_ULP_ACT_HID_4e66] = 471, + [BNXT_ULP_ACT_HID_38ca] = 472, + [BNXT_ULP_ACT_HID_6bda] = 473, + [BNXT_ULP_ACT_HID_012e] = 474, + [BNXT_ULP_ACT_HID_3ece] = 475, + [BNXT_ULP_ACT_HID_71de] = 476, + [BNXT_ULP_ACT_HID_4fde] = 477, + [BNXT_ULP_ACT_HID_3a42] = 478, + [BNXT_ULP_ACT_HID_6d52] = 479, + [BNXT_ULP_ACT_HID_02a6] = 480, + [BNXT_ULP_ACT_HID_3ede] = 481, + [BNXT_ULP_ACT_HID_71ee] = 482, + [BNXT_ULP_ACT_HID_4fee] = 483, + [BNXT_ULP_ACT_HID_3a52] = 484, + [BNXT_ULP_ACT_HID_6d62] = 485, + [BNXT_ULP_ACT_HID_02b6] = 486, + [BNXT_ULP_ACT_HID_79de] = 487, + [BNXT_ULP_ACT_HID_57de] = 488, + [BNXT_ULP_ACT_HID_4242] = 489, + [BNXT_ULP_ACT_HID_46ce] = 490, + [BNXT_ULP_ACT_HID_7552] = 491, + [BNXT_ULP_ACT_HID_0aa6] = 492, + [BNXT_ULP_ACT_HID_46de] = 493, + [BNXT_ULP_ACT_HID_79ee] = 494, + [BNXT_ULP_ACT_HID_57ee] = 495, + [BNXT_ULP_ACT_HID_4252] = 496, + [BNXT_ULP_ACT_HID_7562] = 497, + [BNXT_ULP_ACT_HID_0ab6] = 498, + [BNXT_ULP_ACT_HID_4ece] = 499, + [BNXT_ULP_ACT_HID_0622] = 500, + [BNXT_ULP_ACT_HID_5fde] = 501, + [BNXT_ULP_ACT_HID_4a42] = 502, + [BNXT_ULP_ACT_HID_0196] = 503, + [BNXT_ULP_ACT_HID_12a6] = 504, + [BNXT_ULP_ACT_HID_4ede] = 505, + [BNXT_ULP_ACT_HID_0632] = 506, + [BNXT_ULP_ACT_HID_5fee] = 507, + [BNXT_ULP_ACT_HID_4a52] = 508, + [BNXT_ULP_ACT_HID_01a6] = 509, + [BNXT_ULP_ACT_HID_12b6] = 510, + [BNXT_ULP_ACT_HID_56ce] = 511, + [BNXT_ULP_ACT_HID_0e22] = 512, + [BNXT_ULP_ACT_HID_67de] = 513, + [BNXT_ULP_ACT_HID_5242] = 514, + [BNXT_ULP_ACT_HID_0996] = 515, + [BNXT_ULP_ACT_HID_1aa6] = 516, + [BNXT_ULP_ACT_HID_56de] = 517, + [BNXT_ULP_ACT_HID_0e32] = 518, + [BNXT_ULP_ACT_HID_67ee] = 519, + [BNXT_ULP_ACT_HID_5252] = 520, + [BNXT_ULP_ACT_HID_09a6] = 521, + [BNXT_ULP_ACT_HID_1ab6] = 522, + [BNXT_ULP_ACT_HID_31d0] = 523, + [BNXT_ULP_ACT_HID_31e0] = 524, + [BNXT_ULP_ACT_HID_39d0] = 525, + [BNXT_ULP_ACT_HID_39e0] = 526, + [BNXT_ULP_ACT_HID_41d0] = 527, + [BNXT_ULP_ACT_HID_41e0] = 528, + [BNXT_ULP_ACT_HID_49d0] = 529, + [BNXT_ULP_ACT_HID_49e0] = 530, + [BNXT_ULP_ACT_HID_64ba] = 531, + [BNXT_ULP_ACT_HID_64ca] = 532, + [BNXT_ULP_ACT_HID_6cba] = 533, + [BNXT_ULP_ACT_HID_6cca] = 534, + [BNXT_ULP_ACT_HID_74ba] = 535, + [BNXT_ULP_ACT_HID_74ca] = 536, + [BNXT_ULP_ACT_HID_00fe] = 537, + [BNXT_ULP_ACT_HID_010e] = 538, + [BNXT_ULP_ACT_HID_331c] = 539, + [BNXT_ULP_ACT_HID_332c] = 540, + [BNXT_ULP_ACT_HID_6706] = 541, + [BNXT_ULP_ACT_HID_6716] = 542, + [BNXT_ULP_ACT_HID_1b6d] = 543, + [BNXT_ULP_ACT_HID_1b7d] = 544, + [BNXT_ULP_ACT_HID_641a] = 545 }; /* Array for the act matcher list */ @@ -121,7 +571,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [2] = { - .act_hid = BNXT_ULP_ACT_HID_0001, + .act_hid = BNXT_ULP_ACT_HID_0008, .act_pattern_id = 1, .app_sig = 0, .act_sig = { .bits = @@ -130,7 +580,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [3] = { - .act_hid = BNXT_ULP_ACT_HID_0400, + .act_hid = BNXT_ULP_ACT_HID_2000, .act_pattern_id = 2, .app_sig = 0, .act_sig = { .bits = @@ -139,7 +589,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [4] = { - .act_hid = BNXT_ULP_ACT_HID_01ab, + .act_hid = BNXT_ULP_ACT_HID_1988, .act_pattern_id = 3, .app_sig = 0, .act_sig = { .bits = @@ -148,7 +598,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [5] = { - .act_hid = BNXT_ULP_ACT_HID_0010, + .act_hid = BNXT_ULP_ACT_HID_0080, .act_pattern_id = 4, .app_sig = 0, .act_sig = { .bits = @@ -157,7 +607,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [6] = { - .act_hid = BNXT_ULP_ACT_HID_05ab, + .act_hid = BNXT_ULP_ACT_HID_3988, .act_pattern_id = 5, .app_sig = 0, .act_sig = { .bits = @@ -167,7 +617,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [7] = { - .act_hid = BNXT_ULP_ACT_HID_01bb, + .act_hid = BNXT_ULP_ACT_HID_1a08, .act_pattern_id = 6, .app_sig = 0, .act_sig = { .bits = @@ -177,7 +627,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [8] = { - .act_hid = BNXT_ULP_ACT_HID_0002, + .act_hid = BNXT_ULP_ACT_HID_0010, .act_pattern_id = 7, .app_sig = 0, .act_sig = { .bits = @@ -186,902 +636,6269 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 1 }, [9] = { - .act_hid = BNXT_ULP_ACT_HID_0003, + .act_hid = BNXT_ULP_ACT_HID_0040, .act_pattern_id = 8, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DROP | + BNXT_ULP_ACT_BIT_METER | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [10] = { - .act_hid = BNXT_ULP_ACT_HID_0402, + .act_hid = BNXT_ULP_ACT_HID_0050, .act_pattern_id = 9, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_POP_VLAN | + BNXT_ULP_ACT_BIT_METER | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [11] = { - .act_hid = BNXT_ULP_ACT_HID_01ad, + .act_hid = BNXT_ULP_ACT_HID_0018, .act_pattern_id = 10, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_DROP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [12] = { - .act_hid = BNXT_ULP_ACT_HID_0012, + .act_hid = BNXT_ULP_ACT_HID_2010, .act_pattern_id = 11, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | + BNXT_ULP_ACT_BIT_POP_VLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [13] = { - .act_hid = BNXT_ULP_ACT_HID_05ad, + .act_hid = BNXT_ULP_ACT_HID_1998, .act_pattern_id = 12, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_POP_VLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [14] = { - .act_hid = BNXT_ULP_ACT_HID_01bd, + .act_hid = BNXT_ULP_ACT_HID_0090, .act_pattern_id = 13, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [15] = { - .act_hid = BNXT_ULP_ACT_HID_0613, + .act_hid = BNXT_ULP_ACT_HID_3998, .act_pattern_id = 14, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DROP | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_POP_VLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [16] = { - .act_hid = BNXT_ULP_ACT_HID_02a9, + .act_hid = BNXT_ULP_ACT_HID_1a18, .act_pattern_id = 15, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_POP_VLAN | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_VXLAN_DECAP | + BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [17] = { - .act_hid = BNXT_ULP_ACT_HID_0054, + .act_hid = BNXT_ULP_ACT_HID_32ea, .act_pattern_id = 16, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [18] = { - .act_hid = BNXT_ULP_ACT_HID_0622, + .act_hid = BNXT_ULP_ACT_HID_32f2, .act_pattern_id = 17, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | + BNXT_ULP_ACT_BIT_DROP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [19] = { - .act_hid = BNXT_ULP_ACT_HID_0454, + .act_hid = BNXT_ULP_ACT_HID_52ea, .act_pattern_id = 18, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_POP_VLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [20] = { - .act_hid = BNXT_ULP_ACT_HID_0064, + .act_hid = BNXT_ULP_ACT_HID_4c72, .act_pattern_id = 19, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [21] = { - .act_hid = BNXT_ULP_ACT_HID_0614, + .act_hid = BNXT_ULP_ACT_HID_336a, .act_pattern_id = 20, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_VXLAN_DECAP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [22] = { - .act_hid = BNXT_ULP_ACT_HID_0615, + .act_hid = BNXT_ULP_ACT_HID_6c72, .act_pattern_id = 21, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DROP | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_POP_VLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [23] = { - .act_hid = BNXT_ULP_ACT_HID_02ab, + .act_hid = BNXT_ULP_ACT_HID_4cf2, .act_pattern_id = 22, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_POP_VLAN | + BNXT_ULP_ACT_BIT_VXLAN_DECAP | + BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [24] = { - .act_hid = BNXT_ULP_ACT_HID_0056, + .act_hid = BNXT_ULP_ACT_HID_32fa, .act_pattern_id = 23, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [25] = { - .act_hid = BNXT_ULP_ACT_HID_0624, + .act_hid = BNXT_ULP_ACT_HID_3302, .act_pattern_id = 24, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | + BNXT_ULP_ACT_BIT_DROP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [26] = { - .act_hid = BNXT_ULP_ACT_HID_0456, + .act_hid = BNXT_ULP_ACT_HID_52fa, .act_pattern_id = 25, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_POP_VLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [27] = { - .act_hid = BNXT_ULP_ACT_HID_0066, + .act_hid = BNXT_ULP_ACT_HID_4c82, .act_pattern_id = 26, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [28] = { - .act_hid = BNXT_ULP_ACT_HID_048d, - .act_pattern_id = 0, + .act_hid = BNXT_ULP_ACT_HID_337a, + .act_pattern_id = 27, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED | - BNXT_ULP_ACT_BIT_SAMPLE | + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_VXLAN_DECAP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 2 + .act_tid = 1 }, [29] = { - .act_hid = BNXT_ULP_ACT_HID_048f, - .act_pattern_id = 1, + .act_hid = BNXT_ULP_ACT_HID_6c82, + .act_pattern_id = 28, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED | - BNXT_ULP_ACT_BIT_SAMPLE | + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_POP_VLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 2 + .act_tid = 1 }, [30] = { - .act_hid = BNXT_ULP_ACT_HID_04bc, - .act_pattern_id = 0, + .act_hid = BNXT_ULP_ACT_HID_4d02, + .act_pattern_id = 29, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_VXLAN_DECAP | + BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 + .act_tid = 1 }, [31] = { - .act_hid = BNXT_ULP_ACT_HID_00a9, - .act_pattern_id = 1, + .act_hid = BNXT_ULP_ACT_HID_0808, + .act_pattern_id = 30, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DROP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 + .act_tid = 1 }, [32] = { - .act_hid = BNXT_ULP_ACT_HID_020f, - .act_pattern_id = 2, + .act_hid = BNXT_ULP_ACT_HID_1008, + .act_pattern_id = 31, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DROP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 + .act_tid = 1 }, [33] = { - .act_hid = BNXT_ULP_ACT_HID_0153, - .act_pattern_id = 3, + .act_hid = BNXT_ULP_ACT_HID_1808, + .act_pattern_id = 32, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DROP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 + .act_tid = 1 }, [34] = { - .act_hid = BNXT_ULP_ACT_HID_04a9, - .act_pattern_id = 4, + .act_hid = BNXT_ULP_ACT_HID_0818, + .act_pattern_id = 33, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_DROP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 + .act_tid = 1 }, [35] = { - .act_hid = BNXT_ULP_ACT_HID_01fc, - .act_pattern_id = 5, + .act_hid = BNXT_ULP_ACT_HID_1018, + .act_pattern_id = 34, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_DROP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 + .act_tid = 1 }, [36] = { - .act_hid = BNXT_ULP_ACT_HID_04be, - .act_pattern_id = 6, + .act_hid = BNXT_ULP_ACT_HID_1818, + .act_pattern_id = 35, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_DROP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 + .act_tid = 1 }, [37] = { - .act_hid = BNXT_ULP_ACT_HID_00ab, - .act_pattern_id = 7, + .act_hid = BNXT_ULP_ACT_HID_0880, + .act_pattern_id = 36, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_VXLAN_DECAP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 + .act_tid = 1 }, [38] = { - .act_hid = BNXT_ULP_ACT_HID_0211, - .act_pattern_id = 8, + .act_hid = BNXT_ULP_ACT_HID_1080, + .act_pattern_id = 37, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_VXLAN_DECAP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 + .act_tid = 1 }, [39] = { - .act_hid = BNXT_ULP_ACT_HID_0155, - .act_pattern_id = 9, + .act_hid = BNXT_ULP_ACT_HID_1880, + .act_pattern_id = 38, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_VXLAN_DECAP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 + .act_tid = 1 }, [40] = { - .act_hid = BNXT_ULP_ACT_HID_04ab, - .act_pattern_id = 10, + .act_hid = BNXT_ULP_ACT_HID_0890, + .act_pattern_id = 39, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_ACT_BIT_VXLAN_DECAP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 + .act_tid = 1 }, [41] = { - .act_hid = BNXT_ULP_ACT_HID_01fe, - .act_pattern_id = 11, + .act_hid = BNXT_ULP_ACT_HID_1090, + .act_pattern_id = 40, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_ACT_BIT_VXLAN_DECAP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 + .act_tid = 1 }, [42] = { - .act_hid = BNXT_ULP_ACT_HID_0667, - .act_pattern_id = 12, + .act_hid = BNXT_ULP_ACT_HID_1890, + .act_pattern_id = 41, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_VXLAN_DECAP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 + .act_tid = 1 }, [43] = { - .act_hid = BNXT_ULP_ACT_HID_0254, - .act_pattern_id = 13, + .act_hid = BNXT_ULP_ACT_HID_3af2, + .act_pattern_id = 42, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DROP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 + .act_tid = 1 }, [44] = { - .act_hid = BNXT_ULP_ACT_HID_03ba, - .act_pattern_id = 14, + .act_hid = BNXT_ULP_ACT_HID_42f2, + .act_pattern_id = 43, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DROP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 + .act_tid = 1 }, [45] = { - .act_hid = BNXT_ULP_ACT_HID_02fe, - .act_pattern_id = 15, + .act_hid = BNXT_ULP_ACT_HID_4af2, + .act_pattern_id = 44, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DROP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 + .act_tid = 1 }, [46] = { - .act_hid = BNXT_ULP_ACT_HID_0654, - .act_pattern_id = 16, + .act_hid = BNXT_ULP_ACT_HID_3b02, + .act_pattern_id = 45, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_DROP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 + .act_tid = 1 }, [47] = { - .act_hid = BNXT_ULP_ACT_HID_03a7, - .act_pattern_id = 17, + .act_hid = BNXT_ULP_ACT_HID_4302, + .act_pattern_id = 46, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_DROP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 + .act_tid = 1 }, [48] = { - .act_hid = BNXT_ULP_ACT_HID_0669, - .act_pattern_id = 18, + .act_hid = BNXT_ULP_ACT_HID_4b02, + .act_pattern_id = 47, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_DROP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 + .act_tid = 1 }, [49] = { - .act_hid = BNXT_ULP_ACT_HID_0256, - .act_pattern_id = 19, + .act_hid = BNXT_ULP_ACT_HID_3b6a, + .act_pattern_id = 48, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_VXLAN_DECAP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 + .act_tid = 1 }, [50] = { - .act_hid = BNXT_ULP_ACT_HID_03bc, - .act_pattern_id = 20, + .act_hid = BNXT_ULP_ACT_HID_436a, + .act_pattern_id = 49, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_VXLAN_DECAP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 + .act_tid = 1 }, [51] = { - .act_hid = BNXT_ULP_ACT_HID_0300, - .act_pattern_id = 21, + .act_hid = BNXT_ULP_ACT_HID_4b6a, + .act_pattern_id = 50, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_VXLAN_DECAP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 + .act_tid = 1 }, [52] = { - .act_hid = BNXT_ULP_ACT_HID_0656, - .act_pattern_id = 22, + .act_hid = BNXT_ULP_ACT_HID_3b7a, + .act_pattern_id = 51, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_ACT_BIT_VXLAN_DECAP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 + .act_tid = 1 }, [53] = { - .act_hid = BNXT_ULP_ACT_HID_03a9, - .act_pattern_id = 23, + .act_hid = BNXT_ULP_ACT_HID_437a, + .act_pattern_id = 52, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_ACT_BIT_VXLAN_DECAP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 + .act_tid = 1 }, [54] = { - .act_hid = BNXT_ULP_ACT_HID_021b, - .act_pattern_id = 0, + .act_hid = BNXT_ULP_ACT_HID_4b7a, + .act_pattern_id = 53, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 4 + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_VXLAN_DECAP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 1 }, [55] = { - .act_hid = BNXT_ULP_ACT_HID_021c, - .act_pattern_id = 1, + .act_hid = BNXT_ULP_ACT_HID_640d, + .act_pattern_id = 0, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + BNXT_ULP_ACT_BIT_SHARED | + BNXT_ULP_ACT_BIT_SAMPLE | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 2 + }, + [56] = { + .act_hid = BNXT_ULP_ACT_HID_641d, + .act_pattern_id = 1, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED | + BNXT_ULP_ACT_BIT_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 2 + }, + [57] = { + .act_hid = BNXT_ULP_ACT_HID_071a, + .act_pattern_id = 2, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DELETE | + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 2 + }, + [58] = { + .act_hid = BNXT_ULP_ACT_HID_0800, + .act_pattern_id = 0, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [59] = { + .act_hid = BNXT_ULP_ACT_HID_1000, + .act_pattern_id = 1, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [60] = { + .act_hid = BNXT_ULP_ACT_HID_1800, + .act_pattern_id = 2, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [61] = { + .act_hid = BNXT_ULP_ACT_HID_0810, + .act_pattern_id = 3, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [62] = { + .act_hid = BNXT_ULP_ACT_HID_1010, + .act_pattern_id = 4, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [63] = { + .act_hid = BNXT_ULP_ACT_HID_1810, + .act_pattern_id = 5, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [64] = { + .act_hid = BNXT_ULP_ACT_HID_1110, + .act_pattern_id = 6, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [65] = { + .act_hid = BNXT_ULP_ACT_HID_4420, + .act_pattern_id = 7, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [66] = { + .act_hid = BNXT_ULP_ACT_HID_2220, + .act_pattern_id = 8, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [67] = { + .act_hid = BNXT_ULP_ACT_HID_0c84, + .act_pattern_id = 9, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [68] = { + .act_hid = BNXT_ULP_ACT_HID_3f94, + .act_pattern_id = 10, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [69] = { + .act_hid = BNXT_ULP_ACT_HID_3330, + .act_pattern_id = 11, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [70] = { + .act_hid = BNXT_ULP_ACT_HID_50a4, + .act_pattern_id = 12, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [71] = { + .act_hid = BNXT_ULP_ACT_HID_1910, + .act_pattern_id = 13, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [72] = { + .act_hid = BNXT_ULP_ACT_HID_4c20, + .act_pattern_id = 14, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [73] = { + .act_hid = BNXT_ULP_ACT_HID_2a20, + .act_pattern_id = 15, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [74] = { + .act_hid = BNXT_ULP_ACT_HID_1484, + .act_pattern_id = 16, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [75] = { + .act_hid = BNXT_ULP_ACT_HID_4794, + .act_pattern_id = 17, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [76] = { + .act_hid = BNXT_ULP_ACT_HID_3b30, + .act_pattern_id = 18, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [77] = { + .act_hid = BNXT_ULP_ACT_HID_58a4, + .act_pattern_id = 19, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [78] = { + .act_hid = BNXT_ULP_ACT_HID_2110, + .act_pattern_id = 20, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [79] = { + .act_hid = BNXT_ULP_ACT_HID_5420, + .act_pattern_id = 21, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [80] = { + .act_hid = BNXT_ULP_ACT_HID_3220, + .act_pattern_id = 22, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [81] = { + .act_hid = BNXT_ULP_ACT_HID_1c84, + .act_pattern_id = 23, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [82] = { + .act_hid = BNXT_ULP_ACT_HID_4f94, + .act_pattern_id = 24, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [83] = { + .act_hid = BNXT_ULP_ACT_HID_4330, + .act_pattern_id = 25, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [84] = { + .act_hid = BNXT_ULP_ACT_HID_60a4, + .act_pattern_id = 26, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [85] = { + .act_hid = BNXT_ULP_ACT_HID_2910, + .act_pattern_id = 27, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [86] = { + .act_hid = BNXT_ULP_ACT_HID_5c20, + .act_pattern_id = 28, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [87] = { + .act_hid = BNXT_ULP_ACT_HID_3a20, + .act_pattern_id = 29, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [88] = { + .act_hid = BNXT_ULP_ACT_HID_2484, + .act_pattern_id = 30, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [89] = { + .act_hid = BNXT_ULP_ACT_HID_5794, + .act_pattern_id = 31, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [90] = { + .act_hid = BNXT_ULP_ACT_HID_4b30, + .act_pattern_id = 32, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [91] = { + .act_hid = BNXT_ULP_ACT_HID_68a4, + .act_pattern_id = 33, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [92] = { + .act_hid = BNXT_ULP_ACT_HID_1120, + .act_pattern_id = 34, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [93] = { + .act_hid = BNXT_ULP_ACT_HID_4430, + .act_pattern_id = 35, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [94] = { + .act_hid = BNXT_ULP_ACT_HID_2230, + .act_pattern_id = 36, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [95] = { + .act_hid = BNXT_ULP_ACT_HID_0c94, + .act_pattern_id = 37, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [96] = { + .act_hid = BNXT_ULP_ACT_HID_3fa4, + .act_pattern_id = 38, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [97] = { + .act_hid = BNXT_ULP_ACT_HID_3340, + .act_pattern_id = 39, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [98] = { + .act_hid = BNXT_ULP_ACT_HID_50b4, + .act_pattern_id = 40, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [99] = { + .act_hid = BNXT_ULP_ACT_HID_1920, + .act_pattern_id = 41, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [100] = { + .act_hid = BNXT_ULP_ACT_HID_4c30, + .act_pattern_id = 42, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [101] = { + .act_hid = BNXT_ULP_ACT_HID_2a30, + .act_pattern_id = 43, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [102] = { + .act_hid = BNXT_ULP_ACT_HID_1494, + .act_pattern_id = 44, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [103] = { + .act_hid = BNXT_ULP_ACT_HID_47a4, + .act_pattern_id = 45, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [104] = { + .act_hid = BNXT_ULP_ACT_HID_3b40, + .act_pattern_id = 46, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [105] = { + .act_hid = BNXT_ULP_ACT_HID_58b4, + .act_pattern_id = 47, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [106] = { + .act_hid = BNXT_ULP_ACT_HID_2120, + .act_pattern_id = 48, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [107] = { + .act_hid = BNXT_ULP_ACT_HID_5430, + .act_pattern_id = 49, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [108] = { + .act_hid = BNXT_ULP_ACT_HID_3230, + .act_pattern_id = 50, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [109] = { + .act_hid = BNXT_ULP_ACT_HID_1c94, + .act_pattern_id = 51, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [110] = { + .act_hid = BNXT_ULP_ACT_HID_4fa4, + .act_pattern_id = 52, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [111] = { + .act_hid = BNXT_ULP_ACT_HID_4340, + .act_pattern_id = 53, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [112] = { + .act_hid = BNXT_ULP_ACT_HID_60b4, + .act_pattern_id = 54, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [113] = { + .act_hid = BNXT_ULP_ACT_HID_2920, + .act_pattern_id = 55, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [114] = { + .act_hid = BNXT_ULP_ACT_HID_5c30, + .act_pattern_id = 56, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [115] = { + .act_hid = BNXT_ULP_ACT_HID_3a30, + .act_pattern_id = 57, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [116] = { + .act_hid = BNXT_ULP_ACT_HID_2494, + .act_pattern_id = 58, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [117] = { + .act_hid = BNXT_ULP_ACT_HID_57a4, + .act_pattern_id = 59, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [118] = { + .act_hid = BNXT_ULP_ACT_HID_4b40, + .act_pattern_id = 60, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [119] = { + .act_hid = BNXT_ULP_ACT_HID_68b4, + .act_pattern_id = 61, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [120] = { + .act_hid = BNXT_ULP_ACT_HID_2a98, + .act_pattern_id = 62, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [121] = { + .act_hid = BNXT_ULP_ACT_HID_5da8, + .act_pattern_id = 63, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [122] = { + .act_hid = BNXT_ULP_ACT_HID_3ba8, + .act_pattern_id = 64, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [123] = { + .act_hid = BNXT_ULP_ACT_HID_260c, + .act_pattern_id = 65, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [124] = { + .act_hid = BNXT_ULP_ACT_HID_591c, + .act_pattern_id = 66, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [125] = { + .act_hid = BNXT_ULP_ACT_HID_6a2c, + .act_pattern_id = 67, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [126] = { + .act_hid = BNXT_ULP_ACT_HID_2aa8, + .act_pattern_id = 68, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [127] = { + .act_hid = BNXT_ULP_ACT_HID_5db8, + .act_pattern_id = 69, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [128] = { + .act_hid = BNXT_ULP_ACT_HID_3bb8, + .act_pattern_id = 70, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [129] = { + .act_hid = BNXT_ULP_ACT_HID_261c, + .act_pattern_id = 71, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [130] = { + .act_hid = BNXT_ULP_ACT_HID_592c, + .act_pattern_id = 72, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [131] = { + .act_hid = BNXT_ULP_ACT_HID_6a3c, + .act_pattern_id = 73, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [132] = { + .act_hid = BNXT_ULP_ACT_HID_3298, + .act_pattern_id = 74, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [133] = { + .act_hid = BNXT_ULP_ACT_HID_65a8, + .act_pattern_id = 75, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [134] = { + .act_hid = BNXT_ULP_ACT_HID_43a8, + .act_pattern_id = 76, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [135] = { + .act_hid = BNXT_ULP_ACT_HID_2e0c, + .act_pattern_id = 77, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [136] = { + .act_hid = BNXT_ULP_ACT_HID_611c, + .act_pattern_id = 78, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [137] = { + .act_hid = BNXT_ULP_ACT_HID_722c, + .act_pattern_id = 79, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [138] = { + .act_hid = BNXT_ULP_ACT_HID_32a8, + .act_pattern_id = 80, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [139] = { + .act_hid = BNXT_ULP_ACT_HID_65b8, + .act_pattern_id = 81, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [140] = { + .act_hid = BNXT_ULP_ACT_HID_43b8, + .act_pattern_id = 82, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [141] = { + .act_hid = BNXT_ULP_ACT_HID_2e1c, + .act_pattern_id = 83, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [142] = { + .act_hid = BNXT_ULP_ACT_HID_612c, + .act_pattern_id = 84, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [143] = { + .act_hid = BNXT_ULP_ACT_HID_723c, + .act_pattern_id = 85, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [144] = { + .act_hid = BNXT_ULP_ACT_HID_3a98, + .act_pattern_id = 86, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [145] = { + .act_hid = BNXT_ULP_ACT_HID_6da8, + .act_pattern_id = 87, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [146] = { + .act_hid = BNXT_ULP_ACT_HID_4ba8, + .act_pattern_id = 88, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [147] = { + .act_hid = BNXT_ULP_ACT_HID_360c, + .act_pattern_id = 89, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [148] = { + .act_hid = BNXT_ULP_ACT_HID_691c, + .act_pattern_id = 90, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [149] = { + .act_hid = BNXT_ULP_ACT_HID_7a2c, + .act_pattern_id = 91, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [150] = { + .act_hid = BNXT_ULP_ACT_HID_3aa8, + .act_pattern_id = 92, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [151] = { + .act_hid = BNXT_ULP_ACT_HID_6db8, + .act_pattern_id = 93, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [152] = { + .act_hid = BNXT_ULP_ACT_HID_4bb8, + .act_pattern_id = 94, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [153] = { + .act_hid = BNXT_ULP_ACT_HID_361c, + .act_pattern_id = 95, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [154] = { + .act_hid = BNXT_ULP_ACT_HID_692c, + .act_pattern_id = 96, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [155] = { + .act_hid = BNXT_ULP_ACT_HID_7a3c, + .act_pattern_id = 97, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [156] = { + .act_hid = BNXT_ULP_ACT_HID_4298, + .act_pattern_id = 98, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [157] = { + .act_hid = BNXT_ULP_ACT_HID_75a8, + .act_pattern_id = 99, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [158] = { + .act_hid = BNXT_ULP_ACT_HID_53a8, + .act_pattern_id = 100, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [159] = { + .act_hid = BNXT_ULP_ACT_HID_3e0c, + .act_pattern_id = 101, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [160] = { + .act_hid = BNXT_ULP_ACT_HID_711c, + .act_pattern_id = 102, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [161] = { + .act_hid = BNXT_ULP_ACT_HID_0670, + .act_pattern_id = 103, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [162] = { + .act_hid = BNXT_ULP_ACT_HID_42a8, + .act_pattern_id = 104, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [163] = { + .act_hid = BNXT_ULP_ACT_HID_75b8, + .act_pattern_id = 105, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [164] = { + .act_hid = BNXT_ULP_ACT_HID_53b8, + .act_pattern_id = 106, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [165] = { + .act_hid = BNXT_ULP_ACT_HID_3e1c, + .act_pattern_id = 107, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [166] = { + .act_hid = BNXT_ULP_ACT_HID_712c, + .act_pattern_id = 108, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [167] = { + .act_hid = BNXT_ULP_ACT_HID_0680, + .act_pattern_id = 109, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [168] = { + .act_hid = BNXT_ULP_ACT_HID_3aea, + .act_pattern_id = 110, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [169] = { + .act_hid = BNXT_ULP_ACT_HID_42ea, + .act_pattern_id = 111, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [170] = { + .act_hid = BNXT_ULP_ACT_HID_4aea, + .act_pattern_id = 112, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [171] = { + .act_hid = BNXT_ULP_ACT_HID_3afa, + .act_pattern_id = 113, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [172] = { + .act_hid = BNXT_ULP_ACT_HID_42fa, + .act_pattern_id = 114, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [173] = { + .act_hid = BNXT_ULP_ACT_HID_4afa, + .act_pattern_id = 115, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [174] = { + .act_hid = BNXT_ULP_ACT_HID_43fa, + .act_pattern_id = 116, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [175] = { + .act_hid = BNXT_ULP_ACT_HID_770a, + .act_pattern_id = 117, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [176] = { + .act_hid = BNXT_ULP_ACT_HID_550a, + .act_pattern_id = 118, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [177] = { + .act_hid = BNXT_ULP_ACT_HID_3f6e, + .act_pattern_id = 119, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [178] = { + .act_hid = BNXT_ULP_ACT_HID_727e, + .act_pattern_id = 120, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [179] = { + .act_hid = BNXT_ULP_ACT_HID_661a, + .act_pattern_id = 121, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [180] = { + .act_hid = BNXT_ULP_ACT_HID_07d2, + .act_pattern_id = 122, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [181] = { + .act_hid = BNXT_ULP_ACT_HID_4bfa, + .act_pattern_id = 123, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [182] = { + .act_hid = BNXT_ULP_ACT_HID_034e, + .act_pattern_id = 124, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [183] = { + .act_hid = BNXT_ULP_ACT_HID_5d0a, + .act_pattern_id = 125, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [184] = { + .act_hid = BNXT_ULP_ACT_HID_476e, + .act_pattern_id = 126, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [185] = { + .act_hid = BNXT_ULP_ACT_HID_7a7e, + .act_pattern_id = 127, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [186] = { + .act_hid = BNXT_ULP_ACT_HID_6e1a, + .act_pattern_id = 128, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [187] = { + .act_hid = BNXT_ULP_ACT_HID_0fd2, + .act_pattern_id = 129, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [188] = { + .act_hid = BNXT_ULP_ACT_HID_53fa, + .act_pattern_id = 130, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [189] = { + .act_hid = BNXT_ULP_ACT_HID_0b4e, + .act_pattern_id = 131, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [190] = { + .act_hid = BNXT_ULP_ACT_HID_650a, + .act_pattern_id = 132, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [191] = { + .act_hid = BNXT_ULP_ACT_HID_4f6e, + .act_pattern_id = 133, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [192] = { + .act_hid = BNXT_ULP_ACT_HID_06c2, + .act_pattern_id = 134, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [193] = { + .act_hid = BNXT_ULP_ACT_HID_761a, + .act_pattern_id = 135, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [194] = { + .act_hid = BNXT_ULP_ACT_HID_17d2, + .act_pattern_id = 136, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [195] = { + .act_hid = BNXT_ULP_ACT_HID_5bfa, + .act_pattern_id = 137, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [196] = { + .act_hid = BNXT_ULP_ACT_HID_134e, + .act_pattern_id = 138, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [197] = { + .act_hid = BNXT_ULP_ACT_HID_6d0a, + .act_pattern_id = 139, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [198] = { + .act_hid = BNXT_ULP_ACT_HID_576e, + .act_pattern_id = 140, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [199] = { + .act_hid = BNXT_ULP_ACT_HID_0ec2, + .act_pattern_id = 141, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [200] = { + .act_hid = BNXT_ULP_ACT_HID_025e, + .act_pattern_id = 142, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [201] = { + .act_hid = BNXT_ULP_ACT_HID_1fd2, + .act_pattern_id = 143, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [202] = { + .act_hid = BNXT_ULP_ACT_HID_440a, + .act_pattern_id = 144, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [203] = { + .act_hid = BNXT_ULP_ACT_HID_771a, + .act_pattern_id = 145, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [204] = { + .act_hid = BNXT_ULP_ACT_HID_551a, + .act_pattern_id = 146, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [205] = { + .act_hid = BNXT_ULP_ACT_HID_3f7e, + .act_pattern_id = 147, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [206] = { + .act_hid = BNXT_ULP_ACT_HID_728e, + .act_pattern_id = 148, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [207] = { + .act_hid = BNXT_ULP_ACT_HID_662a, + .act_pattern_id = 149, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [208] = { + .act_hid = BNXT_ULP_ACT_HID_07e2, + .act_pattern_id = 150, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [209] = { + .act_hid = BNXT_ULP_ACT_HID_4c0a, + .act_pattern_id = 151, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [210] = { + .act_hid = BNXT_ULP_ACT_HID_035e, + .act_pattern_id = 152, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [211] = { + .act_hid = BNXT_ULP_ACT_HID_5d1a, + .act_pattern_id = 153, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [212] = { + .act_hid = BNXT_ULP_ACT_HID_477e, + .act_pattern_id = 154, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [213] = { + .act_hid = BNXT_ULP_ACT_HID_7a8e, + .act_pattern_id = 155, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [214] = { + .act_hid = BNXT_ULP_ACT_HID_6e2a, + .act_pattern_id = 156, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [215] = { + .act_hid = BNXT_ULP_ACT_HID_0fe2, + .act_pattern_id = 157, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [216] = { + .act_hid = BNXT_ULP_ACT_HID_540a, + .act_pattern_id = 158, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [217] = { + .act_hid = BNXT_ULP_ACT_HID_0b5e, + .act_pattern_id = 159, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [218] = { + .act_hid = BNXT_ULP_ACT_HID_651a, + .act_pattern_id = 160, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [219] = { + .act_hid = BNXT_ULP_ACT_HID_4f7e, + .act_pattern_id = 161, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [220] = { + .act_hid = BNXT_ULP_ACT_HID_06d2, + .act_pattern_id = 162, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [221] = { + .act_hid = BNXT_ULP_ACT_HID_762a, + .act_pattern_id = 163, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [222] = { + .act_hid = BNXT_ULP_ACT_HID_17e2, + .act_pattern_id = 164, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [223] = { + .act_hid = BNXT_ULP_ACT_HID_5c0a, + .act_pattern_id = 165, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [224] = { + .act_hid = BNXT_ULP_ACT_HID_135e, + .act_pattern_id = 166, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [225] = { + .act_hid = BNXT_ULP_ACT_HID_6d1a, + .act_pattern_id = 167, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [226] = { + .act_hid = BNXT_ULP_ACT_HID_577e, + .act_pattern_id = 168, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [227] = { + .act_hid = BNXT_ULP_ACT_HID_0ed2, + .act_pattern_id = 169, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [228] = { + .act_hid = BNXT_ULP_ACT_HID_026e, + .act_pattern_id = 170, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [229] = { + .act_hid = BNXT_ULP_ACT_HID_1fe2, + .act_pattern_id = 171, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [230] = { + .act_hid = BNXT_ULP_ACT_HID_5d82, + .act_pattern_id = 172, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [231] = { + .act_hid = BNXT_ULP_ACT_HID_14d6, + .act_pattern_id = 173, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [232] = { + .act_hid = BNXT_ULP_ACT_HID_6e92, + .act_pattern_id = 174, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [233] = { + .act_hid = BNXT_ULP_ACT_HID_58f6, + .act_pattern_id = 175, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [234] = { + .act_hid = BNXT_ULP_ACT_HID_104a, + .act_pattern_id = 176, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [235] = { + .act_hid = BNXT_ULP_ACT_HID_215a, + .act_pattern_id = 177, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [236] = { + .act_hid = BNXT_ULP_ACT_HID_5d92, + .act_pattern_id = 178, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [237] = { + .act_hid = BNXT_ULP_ACT_HID_14e6, + .act_pattern_id = 179, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [238] = { + .act_hid = BNXT_ULP_ACT_HID_6ea2, + .act_pattern_id = 180, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [239] = { + .act_hid = BNXT_ULP_ACT_HID_5906, + .act_pattern_id = 181, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [240] = { + .act_hid = BNXT_ULP_ACT_HID_105a, + .act_pattern_id = 182, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [241] = { + .act_hid = BNXT_ULP_ACT_HID_216a, + .act_pattern_id = 183, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [242] = { + .act_hid = BNXT_ULP_ACT_HID_6582, + .act_pattern_id = 184, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [243] = { + .act_hid = BNXT_ULP_ACT_HID_1cd6, + .act_pattern_id = 185, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [244] = { + .act_hid = BNXT_ULP_ACT_HID_7692, + .act_pattern_id = 186, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [245] = { + .act_hid = BNXT_ULP_ACT_HID_60f6, + .act_pattern_id = 187, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [246] = { + .act_hid = BNXT_ULP_ACT_HID_184a, + .act_pattern_id = 188, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [247] = { + .act_hid = BNXT_ULP_ACT_HID_295a, + .act_pattern_id = 189, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [248] = { + .act_hid = BNXT_ULP_ACT_HID_6592, + .act_pattern_id = 190, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [249] = { + .act_hid = BNXT_ULP_ACT_HID_1ce6, + .act_pattern_id = 191, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [250] = { + .act_hid = BNXT_ULP_ACT_HID_76a2, + .act_pattern_id = 192, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [251] = { + .act_hid = BNXT_ULP_ACT_HID_6106, + .act_pattern_id = 193, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [252] = { + .act_hid = BNXT_ULP_ACT_HID_185a, + .act_pattern_id = 194, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [253] = { + .act_hid = BNXT_ULP_ACT_HID_296a, + .act_pattern_id = 195, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [254] = { + .act_hid = BNXT_ULP_ACT_HID_6d82, + .act_pattern_id = 196, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [255] = { + .act_hid = BNXT_ULP_ACT_HID_24d6, + .act_pattern_id = 197, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [256] = { + .act_hid = BNXT_ULP_ACT_HID_02d6, + .act_pattern_id = 198, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [257] = { + .act_hid = BNXT_ULP_ACT_HID_68f6, + .act_pattern_id = 199, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [258] = { + .act_hid = BNXT_ULP_ACT_HID_204a, + .act_pattern_id = 200, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [259] = { + .act_hid = BNXT_ULP_ACT_HID_315a, + .act_pattern_id = 201, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [260] = { + .act_hid = BNXT_ULP_ACT_HID_6d92, + .act_pattern_id = 202, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [261] = { + .act_hid = BNXT_ULP_ACT_HID_24e6, + .act_pattern_id = 203, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [262] = { + .act_hid = BNXT_ULP_ACT_HID_02e6, + .act_pattern_id = 204, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [263] = { + .act_hid = BNXT_ULP_ACT_HID_6906, + .act_pattern_id = 205, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [264] = { + .act_hid = BNXT_ULP_ACT_HID_205a, + .act_pattern_id = 206, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [265] = { + .act_hid = BNXT_ULP_ACT_HID_316a, + .act_pattern_id = 207, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [266] = { + .act_hid = BNXT_ULP_ACT_HID_7582, + .act_pattern_id = 208, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [267] = { + .act_hid = BNXT_ULP_ACT_HID_2cd6, + .act_pattern_id = 209, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [268] = { + .act_hid = BNXT_ULP_ACT_HID_0ad6, + .act_pattern_id = 210, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [269] = { + .act_hid = BNXT_ULP_ACT_HID_70f6, + .act_pattern_id = 211, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [270] = { + .act_hid = BNXT_ULP_ACT_HID_284a, + .act_pattern_id = 212, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [271] = { + .act_hid = BNXT_ULP_ACT_HID_395a, + .act_pattern_id = 213, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [272] = { + .act_hid = BNXT_ULP_ACT_HID_7592, + .act_pattern_id = 214, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [273] = { + .act_hid = BNXT_ULP_ACT_HID_2ce6, + .act_pattern_id = 215, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [274] = { + .act_hid = BNXT_ULP_ACT_HID_0ae6, + .act_pattern_id = 216, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [275] = { + .act_hid = BNXT_ULP_ACT_HID_7106, + .act_pattern_id = 217, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [276] = { + .act_hid = BNXT_ULP_ACT_HID_285a, + .act_pattern_id = 218, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [277] = { + .act_hid = BNXT_ULP_ACT_HID_396a, + .act_pattern_id = 219, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [278] = { + .act_hid = BNXT_ULP_ACT_HID_0020, + .act_pattern_id = 0, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_RSS | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 4 + }, + [279] = { + .act_hid = BNXT_ULP_ACT_HID_0030, + .act_pattern_id = 1, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_RSS | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 4 + }, + [280] = { + .act_hid = BNXT_ULP_ACT_HID_65d4, + .act_pattern_id = 2, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_QUEUE | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 4 + }, + [281] = { + .act_hid = BNXT_ULP_ACT_HID_65e4, + .act_pattern_id = 3, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_QUEUE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 4 + }, + [282] = { + .act_hid = BNXT_ULP_ACT_HID_330a, + .act_pattern_id = 4, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_RSS | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 4 + }, + [283] = { + .act_hid = BNXT_ULP_ACT_HID_331a, + .act_pattern_id = 5, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_RSS | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 4 + }, + [284] = { + .act_hid = BNXT_ULP_ACT_HID_1cfe, + .act_pattern_id = 6, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_QUEUE | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 4 + }, + [285] = { + .act_hid = BNXT_ULP_ACT_HID_1d0e, + .act_pattern_id = 7, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_QUEUE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 4 }, - [56] = { - .act_hid = BNXT_ULP_ACT_HID_021e, - .act_pattern_id = 2, + [286] = { + .act_hid = BNXT_ULP_ACT_HID_1474, + .act_pattern_id = 0, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_METER_PROFILE | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 5 + }, + [287] = { + .act_hid = BNXT_ULP_ACT_HID_4838, + .act_pattern_id = 1, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_METER | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 5 + }, + [288] = { + .act_hid = BNXT_ULP_ACT_HID_6458, + .act_pattern_id = 2, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DELETE | + BNXT_ULP_ACT_BIT_METER_PROFILE | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 5 + }, + [289] = { + .act_hid = BNXT_ULP_ACT_HID_1c68, + .act_pattern_id = 3, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DELETE | + BNXT_ULP_ACT_BIT_SHARED_METER | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 5 + }, + [290] = { + .act_hid = BNXT_ULP_ACT_HID_6c34, + .act_pattern_id = 4, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_UPDATE | + BNXT_ULP_ACT_BIT_SHARED_METER | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 5 + }, + [291] = { + .act_hid = BNXT_ULP_ACT_HID_5d08, + .act_pattern_id = 0, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [292] = { + .act_hid = BNXT_ULP_ACT_HID_5d10, + .act_pattern_id = 1, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DROP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [293] = { + .act_hid = BNXT_ULP_ACT_HID_5d20, + .act_pattern_id = 2, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DROP | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [294] = { + .act_hid = BNXT_ULP_ACT_HID_2e18, + .act_pattern_id = 3, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_VLAN_PCP | + BNXT_ULP_ACT_BIT_SET_VLAN_VID | + BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [295] = { + .act_hid = BNXT_ULP_ACT_HID_29d4, + .act_pattern_id = 4, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_VLAN_VID | + BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [296] = { + .act_hid = BNXT_ULP_ACT_HID_7690, + .act_pattern_id = 5, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [297] = { + .act_hid = BNXT_ULP_ACT_HID_47a0, + .act_pattern_id = 6, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_VLAN_PCP | + BNXT_ULP_ACT_BIT_SET_VLAN_VID | + BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [298] = { + .act_hid = BNXT_ULP_ACT_HID_435c, + .act_pattern_id = 7, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_VLAN_VID | + BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [299] = { + .act_hid = BNXT_ULP_ACT_HID_5d18, + .act_pattern_id = 8, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [300] = { + .act_hid = BNXT_ULP_ACT_HID_2e28, + .act_pattern_id = 9, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_VLAN_PCP | + BNXT_ULP_ACT_BIT_SET_VLAN_VID | + BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [301] = { + .act_hid = BNXT_ULP_ACT_HID_29e4, + .act_pattern_id = 10, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_VLAN_VID | + BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [302] = { + .act_hid = BNXT_ULP_ACT_HID_76a0, + .act_pattern_id = 11, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [303] = { + .act_hid = BNXT_ULP_ACT_HID_47b0, + .act_pattern_id = 12, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_VLAN_PCP | + BNXT_ULP_ACT_BIT_SET_VLAN_VID | + BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [304] = { + .act_hid = BNXT_ULP_ACT_HID_436c, + .act_pattern_id = 13, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_VLAN_VID | + BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [305] = { + .act_hid = BNXT_ULP_ACT_HID_1436, + .act_pattern_id = 14, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [306] = { + .act_hid = BNXT_ULP_ACT_HID_143e, + .act_pattern_id = 15, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_DROP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [307] = { + .act_hid = BNXT_ULP_ACT_HID_144e, + .act_pattern_id = 16, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_DROP | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [308] = { + .act_hid = BNXT_ULP_ACT_HID_6102, + .act_pattern_id = 17, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_VLAN_PCP | + BNXT_ULP_ACT_BIT_SET_VLAN_VID | + BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [309] = { + .act_hid = BNXT_ULP_ACT_HID_5cbe, + .act_pattern_id = 18, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_VLAN_VID | + BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [310] = { + .act_hid = BNXT_ULP_ACT_HID_2dbe, + .act_pattern_id = 19, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [311] = { + .act_hid = BNXT_ULP_ACT_HID_7a8a, + .act_pattern_id = 20, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_VLAN_PCP | + BNXT_ULP_ACT_BIT_SET_VLAN_VID | + BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [312] = { + .act_hid = BNXT_ULP_ACT_HID_7646, + .act_pattern_id = 21, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_VLAN_VID | + BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [313] = { + .act_hid = BNXT_ULP_ACT_HID_1446, + .act_pattern_id = 22, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [314] = { + .act_hid = BNXT_ULP_ACT_HID_6112, + .act_pattern_id = 23, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_VLAN_PCP | + BNXT_ULP_ACT_BIT_SET_VLAN_VID | + BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [315] = { + .act_hid = BNXT_ULP_ACT_HID_5cce, + .act_pattern_id = 24, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_VLAN_VID | + BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [316] = { + .act_hid = BNXT_ULP_ACT_HID_2dce, + .act_pattern_id = 25, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [317] = { + .act_hid = BNXT_ULP_ACT_HID_7a9a, + .act_pattern_id = 26, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_VLAN_PCP | + BNXT_ULP_ACT_BIT_SET_VLAN_VID | + BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [318] = { + .act_hid = BNXT_ULP_ACT_HID_7656, + .act_pattern_id = 27, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_VLAN_VID | + BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [319] = { + .act_hid = BNXT_ULP_ACT_HID_6508, + .act_pattern_id = 0, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [320] = { + .act_hid = BNXT_ULP_ACT_HID_6d08, + .act_pattern_id = 1, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [321] = { + .act_hid = BNXT_ULP_ACT_HID_7508, + .act_pattern_id = 2, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [322] = { + .act_hid = BNXT_ULP_ACT_HID_6518, + .act_pattern_id = 3, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [323] = { + .act_hid = BNXT_ULP_ACT_HID_6d18, + .act_pattern_id = 4, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [324] = { + .act_hid = BNXT_ULP_ACT_HID_7518, + .act_pattern_id = 5, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [325] = { + .act_hid = BNXT_ULP_ACT_HID_6e18, + .act_pattern_id = 6, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [326] = { + .act_hid = BNXT_ULP_ACT_HID_256c, + .act_pattern_id = 7, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [327] = { + .act_hid = BNXT_ULP_ACT_HID_036c, + .act_pattern_id = 8, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [328] = { + .act_hid = BNXT_ULP_ACT_HID_698c, + .act_pattern_id = 9, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [329] = { + .act_hid = BNXT_ULP_ACT_HID_20e0, + .act_pattern_id = 10, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [330] = { + .act_hid = BNXT_ULP_ACT_HID_31f0, + .act_pattern_id = 11, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [331] = { + .act_hid = BNXT_ULP_ACT_HID_7618, + .act_pattern_id = 12, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [332] = { + .act_hid = BNXT_ULP_ACT_HID_2d6c, + .act_pattern_id = 13, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [333] = { + .act_hid = BNXT_ULP_ACT_HID_0b6c, + .act_pattern_id = 14, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [334] = { + .act_hid = BNXT_ULP_ACT_HID_718c, + .act_pattern_id = 15, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [335] = { + .act_hid = BNXT_ULP_ACT_HID_28e0, + .act_pattern_id = 16, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [336] = { + .act_hid = BNXT_ULP_ACT_HID_39f0, + .act_pattern_id = 17, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [337] = { + .act_hid = BNXT_ULP_ACT_HID_025c, + .act_pattern_id = 18, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [338] = { + .act_hid = BNXT_ULP_ACT_HID_356c, + .act_pattern_id = 19, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [339] = { + .act_hid = BNXT_ULP_ACT_HID_136c, + .act_pattern_id = 20, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [340] = { + .act_hid = BNXT_ULP_ACT_HID_798c, + .act_pattern_id = 21, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [341] = { + .act_hid = BNXT_ULP_ACT_HID_30e0, + .act_pattern_id = 22, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [342] = { + .act_hid = BNXT_ULP_ACT_HID_41f0, + .act_pattern_id = 23, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [343] = { + .act_hid = BNXT_ULP_ACT_HID_0a5c, + .act_pattern_id = 24, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [344] = { + .act_hid = BNXT_ULP_ACT_HID_3d6c, + .act_pattern_id = 25, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [345] = { + .act_hid = BNXT_ULP_ACT_HID_1b6c, + .act_pattern_id = 26, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [346] = { + .act_hid = BNXT_ULP_ACT_HID_05d0, + .act_pattern_id = 27, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [347] = { + .act_hid = BNXT_ULP_ACT_HID_38e0, + .act_pattern_id = 28, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [348] = { + .act_hid = BNXT_ULP_ACT_HID_49f0, + .act_pattern_id = 29, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [349] = { + .act_hid = BNXT_ULP_ACT_HID_6e28, + .act_pattern_id = 30, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [350] = { + .act_hid = BNXT_ULP_ACT_HID_257c, + .act_pattern_id = 31, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [351] = { + .act_hid = BNXT_ULP_ACT_HID_037c, + .act_pattern_id = 32, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [352] = { + .act_hid = BNXT_ULP_ACT_HID_699c, + .act_pattern_id = 33, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [353] = { + .act_hid = BNXT_ULP_ACT_HID_20f0, + .act_pattern_id = 34, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [354] = { + .act_hid = BNXT_ULP_ACT_HID_3200, + .act_pattern_id = 35, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [355] = { + .act_hid = BNXT_ULP_ACT_HID_7628, + .act_pattern_id = 36, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [356] = { + .act_hid = BNXT_ULP_ACT_HID_2d7c, + .act_pattern_id = 37, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [357] = { + .act_hid = BNXT_ULP_ACT_HID_0b7c, + .act_pattern_id = 38, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [358] = { + .act_hid = BNXT_ULP_ACT_HID_719c, + .act_pattern_id = 39, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [359] = { + .act_hid = BNXT_ULP_ACT_HID_28f0, + .act_pattern_id = 40, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [360] = { + .act_hid = BNXT_ULP_ACT_HID_3a00, + .act_pattern_id = 41, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [361] = { + .act_hid = BNXT_ULP_ACT_HID_026c, + .act_pattern_id = 42, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [362] = { + .act_hid = BNXT_ULP_ACT_HID_357c, + .act_pattern_id = 43, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [363] = { + .act_hid = BNXT_ULP_ACT_HID_137c, + .act_pattern_id = 44, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [364] = { + .act_hid = BNXT_ULP_ACT_HID_799c, + .act_pattern_id = 45, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [365] = { + .act_hid = BNXT_ULP_ACT_HID_30f0, + .act_pattern_id = 46, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [366] = { + .act_hid = BNXT_ULP_ACT_HID_4200, + .act_pattern_id = 47, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [367] = { + .act_hid = BNXT_ULP_ACT_HID_0a6c, + .act_pattern_id = 48, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [368] = { + .act_hid = BNXT_ULP_ACT_HID_3d7c, + .act_pattern_id = 49, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [369] = { + .act_hid = BNXT_ULP_ACT_HID_1b7c, + .act_pattern_id = 50, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [370] = { + .act_hid = BNXT_ULP_ACT_HID_05e0, + .act_pattern_id = 51, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [371] = { + .act_hid = BNXT_ULP_ACT_HID_38f0, + .act_pattern_id = 52, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [372] = { + .act_hid = BNXT_ULP_ACT_HID_4a00, + .act_pattern_id = 53, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [373] = { + .act_hid = BNXT_ULP_ACT_HID_0be4, + .act_pattern_id = 54, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [374] = { + .act_hid = BNXT_ULP_ACT_HID_3ef4, + .act_pattern_id = 55, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [375] = { + .act_hid = BNXT_ULP_ACT_HID_1cf4, + .act_pattern_id = 56, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [376] = { + .act_hid = BNXT_ULP_ACT_HID_0758, + .act_pattern_id = 57, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [377] = { + .act_hid = BNXT_ULP_ACT_HID_3a68, + .act_pattern_id = 58, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [378] = { + .act_hid = BNXT_ULP_ACT_HID_4b78, + .act_pattern_id = 59, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [379] = { + .act_hid = BNXT_ULP_ACT_HID_0bf4, + .act_pattern_id = 60, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [380] = { + .act_hid = BNXT_ULP_ACT_HID_3f04, + .act_pattern_id = 61, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [381] = { + .act_hid = BNXT_ULP_ACT_HID_1d04, + .act_pattern_id = 62, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [382] = { + .act_hid = BNXT_ULP_ACT_HID_0768, + .act_pattern_id = 63, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [383] = { + .act_hid = BNXT_ULP_ACT_HID_3a78, + .act_pattern_id = 64, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [384] = { + .act_hid = BNXT_ULP_ACT_HID_4b88, + .act_pattern_id = 65, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [385] = { + .act_hid = BNXT_ULP_ACT_HID_46f4, + .act_pattern_id = 66, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [386] = { + .act_hid = BNXT_ULP_ACT_HID_24f4, + .act_pattern_id = 67, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [387] = { + .act_hid = BNXT_ULP_ACT_HID_0f58, + .act_pattern_id = 68, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [388] = { + .act_hid = BNXT_ULP_ACT_HID_13e4, + .act_pattern_id = 69, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [389] = { + .act_hid = BNXT_ULP_ACT_HID_4268, + .act_pattern_id = 70, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [390] = { + .act_hid = BNXT_ULP_ACT_HID_5378, + .act_pattern_id = 71, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [391] = { + .act_hid = BNXT_ULP_ACT_HID_13f4, + .act_pattern_id = 72, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [392] = { + .act_hid = BNXT_ULP_ACT_HID_4704, + .act_pattern_id = 73, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [393] = { + .act_hid = BNXT_ULP_ACT_HID_2504, + .act_pattern_id = 74, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [394] = { + .act_hid = BNXT_ULP_ACT_HID_0f68, + .act_pattern_id = 75, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [395] = { + .act_hid = BNXT_ULP_ACT_HID_4278, + .act_pattern_id = 76, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [396] = { + .act_hid = BNXT_ULP_ACT_HID_5388, + .act_pattern_id = 77, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [397] = { + .act_hid = BNXT_ULP_ACT_HID_1be4, + .act_pattern_id = 78, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [398] = { + .act_hid = BNXT_ULP_ACT_HID_4ef4, + .act_pattern_id = 79, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [399] = { + .act_hid = BNXT_ULP_ACT_HID_2cf4, + .act_pattern_id = 80, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [400] = { + .act_hid = BNXT_ULP_ACT_HID_1758, + .act_pattern_id = 81, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [401] = { + .act_hid = BNXT_ULP_ACT_HID_4a68, + .act_pattern_id = 82, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [402] = { + .act_hid = BNXT_ULP_ACT_HID_5b78, + .act_pattern_id = 83, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [403] = { + .act_hid = BNXT_ULP_ACT_HID_1bf4, + .act_pattern_id = 84, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [404] = { + .act_hid = BNXT_ULP_ACT_HID_4f04, + .act_pattern_id = 85, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [405] = { + .act_hid = BNXT_ULP_ACT_HID_2d04, + .act_pattern_id = 86, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [406] = { + .act_hid = BNXT_ULP_ACT_HID_1768, + .act_pattern_id = 87, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [407] = { + .act_hid = BNXT_ULP_ACT_HID_4a78, + .act_pattern_id = 88, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [408] = { + .act_hid = BNXT_ULP_ACT_HID_5b88, + .act_pattern_id = 89, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [409] = { + .act_hid = BNXT_ULP_ACT_HID_23e4, + .act_pattern_id = 90, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [410] = { + .act_hid = BNXT_ULP_ACT_HID_56f4, + .act_pattern_id = 91, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [411] = { + .act_hid = BNXT_ULP_ACT_HID_34f4, + .act_pattern_id = 92, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [412] = { + .act_hid = BNXT_ULP_ACT_HID_1f58, + .act_pattern_id = 93, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [413] = { + .act_hid = BNXT_ULP_ACT_HID_5268, + .act_pattern_id = 94, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [414] = { + .act_hid = BNXT_ULP_ACT_HID_6378, + .act_pattern_id = 95, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [415] = { + .act_hid = BNXT_ULP_ACT_HID_23f4, + .act_pattern_id = 96, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [416] = { + .act_hid = BNXT_ULP_ACT_HID_5704, + .act_pattern_id = 97, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [417] = { + .act_hid = BNXT_ULP_ACT_HID_3504, + .act_pattern_id = 98, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [418] = { + .act_hid = BNXT_ULP_ACT_HID_1f68, + .act_pattern_id = 99, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [419] = { + .act_hid = BNXT_ULP_ACT_HID_5278, + .act_pattern_id = 100, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [420] = { + .act_hid = BNXT_ULP_ACT_HID_6388, + .act_pattern_id = 101, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [421] = { + .act_hid = BNXT_ULP_ACT_HID_1c36, + .act_pattern_id = 102, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [422] = { + .act_hid = BNXT_ULP_ACT_HID_2436, + .act_pattern_id = 103, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [423] = { + .act_hid = BNXT_ULP_ACT_HID_2c36, + .act_pattern_id = 104, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [424] = { + .act_hid = BNXT_ULP_ACT_HID_1c46, + .act_pattern_id = 105, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [425] = { + .act_hid = BNXT_ULP_ACT_HID_2446, + .act_pattern_id = 106, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [426] = { + .act_hid = BNXT_ULP_ACT_HID_2c46, + .act_pattern_id = 107, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [427] = { + .act_hid = BNXT_ULP_ACT_HID_2546, + .act_pattern_id = 108, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [428] = { + .act_hid = BNXT_ULP_ACT_HID_5856, + .act_pattern_id = 109, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [429] = { + .act_hid = BNXT_ULP_ACT_HID_3656, + .act_pattern_id = 110, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [430] = { + .act_hid = BNXT_ULP_ACT_HID_20ba, + .act_pattern_id = 111, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [431] = { + .act_hid = BNXT_ULP_ACT_HID_53ca, + .act_pattern_id = 112, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [432] = { + .act_hid = BNXT_ULP_ACT_HID_64da, + .act_pattern_id = 113, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [433] = { + .act_hid = BNXT_ULP_ACT_HID_2d46, + .act_pattern_id = 114, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [434] = { + .act_hid = BNXT_ULP_ACT_HID_6056, + .act_pattern_id = 115, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [435] = { + .act_hid = BNXT_ULP_ACT_HID_3e56, + .act_pattern_id = 116, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [436] = { + .act_hid = BNXT_ULP_ACT_HID_28ba, + .act_pattern_id = 117, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [437] = { + .act_hid = BNXT_ULP_ACT_HID_5bca, + .act_pattern_id = 118, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [438] = { + .act_hid = BNXT_ULP_ACT_HID_6cda, + .act_pattern_id = 119, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [439] = { + .act_hid = BNXT_ULP_ACT_HID_3546, + .act_pattern_id = 120, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [440] = { + .act_hid = BNXT_ULP_ACT_HID_6856, + .act_pattern_id = 121, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [441] = { + .act_hid = BNXT_ULP_ACT_HID_4656, + .act_pattern_id = 122, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [442] = { + .act_hid = BNXT_ULP_ACT_HID_30ba, + .act_pattern_id = 123, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [443] = { + .act_hid = BNXT_ULP_ACT_HID_63ca, + .act_pattern_id = 124, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [444] = { + .act_hid = BNXT_ULP_ACT_HID_74da, + .act_pattern_id = 125, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [445] = { + .act_hid = BNXT_ULP_ACT_HID_3d46, + .act_pattern_id = 126, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [446] = { + .act_hid = BNXT_ULP_ACT_HID_7056, + .act_pattern_id = 127, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [447] = { + .act_hid = BNXT_ULP_ACT_HID_4e56, + .act_pattern_id = 128, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [448] = { + .act_hid = BNXT_ULP_ACT_HID_38ba, + .act_pattern_id = 129, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [449] = { + .act_hid = BNXT_ULP_ACT_HID_6bca, + .act_pattern_id = 130, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [450] = { + .act_hid = BNXT_ULP_ACT_HID_011e, + .act_pattern_id = 131, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [451] = { + .act_hid = BNXT_ULP_ACT_HID_2556, + .act_pattern_id = 132, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [452] = { + .act_hid = BNXT_ULP_ACT_HID_5866, + .act_pattern_id = 133, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [453] = { + .act_hid = BNXT_ULP_ACT_HID_3666, + .act_pattern_id = 134, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [454] = { + .act_hid = BNXT_ULP_ACT_HID_20ca, + .act_pattern_id = 135, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [455] = { + .act_hid = BNXT_ULP_ACT_HID_53da, + .act_pattern_id = 136, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [456] = { + .act_hid = BNXT_ULP_ACT_HID_64ea, + .act_pattern_id = 137, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [457] = { + .act_hid = BNXT_ULP_ACT_HID_2d56, + .act_pattern_id = 138, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [458] = { + .act_hid = BNXT_ULP_ACT_HID_6066, + .act_pattern_id = 139, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [459] = { + .act_hid = BNXT_ULP_ACT_HID_3e66, + .act_pattern_id = 140, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [460] = { + .act_hid = BNXT_ULP_ACT_HID_28ca, + .act_pattern_id = 141, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [461] = { + .act_hid = BNXT_ULP_ACT_HID_5bda, + .act_pattern_id = 142, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [462] = { + .act_hid = BNXT_ULP_ACT_HID_6cea, + .act_pattern_id = 143, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [463] = { + .act_hid = BNXT_ULP_ACT_HID_3556, + .act_pattern_id = 144, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [464] = { + .act_hid = BNXT_ULP_ACT_HID_6866, + .act_pattern_id = 145, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [465] = { + .act_hid = BNXT_ULP_ACT_HID_4666, + .act_pattern_id = 146, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [466] = { + .act_hid = BNXT_ULP_ACT_HID_30ca, + .act_pattern_id = 147, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [467] = { + .act_hid = BNXT_ULP_ACT_HID_63da, + .act_pattern_id = 148, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [468] = { + .act_hid = BNXT_ULP_ACT_HID_74ea, + .act_pattern_id = 149, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [469] = { + .act_hid = BNXT_ULP_ACT_HID_3d56, + .act_pattern_id = 150, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DROP | + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 4 + .act_tid = 7 }, - [57] = { - .act_hid = BNXT_ULP_ACT_HID_063f, - .act_pattern_id = 3, + [470] = { + .act_hid = BNXT_ULP_ACT_HID_7066, + .act_pattern_id = 151, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_VLAN_PCP | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 4 + .act_tid = 7 }, - [58] = { - .act_hid = BNXT_ULP_ACT_HID_0510, - .act_pattern_id = 4, + [471] = { + .act_hid = BNXT_ULP_ACT_HID_4e66, + .act_pattern_id = 152, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 4 + .act_tid = 7 }, - [59] = { - .act_hid = BNXT_ULP_ACT_HID_03c6, - .act_pattern_id = 5, + [472] = { + .act_hid = BNXT_ULP_ACT_HID_38ca, + .act_pattern_id = 153, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [473] = { + .act_hid = BNXT_ULP_ACT_HID_6bda, + .act_pattern_id = 154, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [474] = { + .act_hid = BNXT_ULP_ACT_HID_012e, + .act_pattern_id = 155, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [475] = { + .act_hid = BNXT_ULP_ACT_HID_3ece, + .act_pattern_id = 156, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 4 + .act_tid = 7 }, - [60] = { - .act_hid = BNXT_ULP_ACT_HID_0082, - .act_pattern_id = 6, + [476] = { + .act_hid = BNXT_ULP_ACT_HID_71de, + .act_pattern_id = 157, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_VLAN_PCP | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 4 + .act_tid = 7 }, - [61] = { - .act_hid = BNXT_ULP_ACT_HID_06bb, - .act_pattern_id = 7, + [477] = { + .act_hid = BNXT_ULP_ACT_HID_4fde, + .act_pattern_id = 158, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 4 + .act_tid = 7 }, - [62] = { - .act_hid = BNXT_ULP_ACT_HID_021d, - .act_pattern_id = 8, + [478] = { + .act_hid = BNXT_ULP_ACT_HID_3a42, + .act_pattern_id = 159, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [479] = { + .act_hid = BNXT_ULP_ACT_HID_6d52, + .act_pattern_id = 160, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [480] = { + .act_hid = BNXT_ULP_ACT_HID_02a6, + .act_pattern_id = 161, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [481] = { + .act_hid = BNXT_ULP_ACT_HID_3ede, + .act_pattern_id = 162, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 4 + .act_tid = 7 }, - [63] = { - .act_hid = BNXT_ULP_ACT_HID_0641, - .act_pattern_id = 9, + [482] = { + .act_hid = BNXT_ULP_ACT_HID_71ee, + .act_pattern_id = 163, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_VLAN_PCP | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 4 + .act_tid = 7 }, - [64] = { - .act_hid = BNXT_ULP_ACT_HID_0512, - .act_pattern_id = 10, + [483] = { + .act_hid = BNXT_ULP_ACT_HID_4fee, + .act_pattern_id = 164, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 4 + .act_tid = 7 }, - [65] = { - .act_hid = BNXT_ULP_ACT_HID_03c8, - .act_pattern_id = 11, + [484] = { + .act_hid = BNXT_ULP_ACT_HID_3a52, + .act_pattern_id = 165, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [485] = { + .act_hid = BNXT_ULP_ACT_HID_6d62, + .act_pattern_id = 166, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [486] = { + .act_hid = BNXT_ULP_ACT_HID_02b6, + .act_pattern_id = 167, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 4 + .act_tid = 7 }, - [66] = { - .act_hid = BNXT_ULP_ACT_HID_0084, - .act_pattern_id = 12, + [487] = { + .act_hid = BNXT_ULP_ACT_HID_79de, + .act_pattern_id = 168, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [488] = { + .act_hid = BNXT_ULP_ACT_HID_57de, + .act_pattern_id = 169, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [489] = { + .act_hid = BNXT_ULP_ACT_HID_4242, + .act_pattern_id = 170, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [490] = { + .act_hid = BNXT_ULP_ACT_HID_46ce, + .act_pattern_id = 171, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [491] = { + .act_hid = BNXT_ULP_ACT_HID_7552, + .act_pattern_id = 172, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [492] = { + .act_hid = BNXT_ULP_ACT_HID_0aa6, + .act_pattern_id = 173, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [493] = { + .act_hid = BNXT_ULP_ACT_HID_46de, + .act_pattern_id = 174, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [494] = { + .act_hid = BNXT_ULP_ACT_HID_79ee, + .act_pattern_id = 175, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_VLAN_PCP | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 4 + .act_tid = 7 }, - [67] = { - .act_hid = BNXT_ULP_ACT_HID_06bd, - .act_pattern_id = 13, + [495] = { + .act_hid = BNXT_ULP_ACT_HID_57ee, + .act_pattern_id = 176, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [496] = { + .act_hid = BNXT_ULP_ACT_HID_4252, + .act_pattern_id = 177, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [497] = { + .act_hid = BNXT_ULP_ACT_HID_7562, + .act_pattern_id = 178, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 4 + .act_tid = 7 }, - [68] = { - .act_hid = BNXT_ULP_ACT_HID_06d7, - .act_pattern_id = 0, + [498] = { + .act_hid = BNXT_ULP_ACT_HID_0ab6, + .act_pattern_id = 179, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 7 + }, + [499] = { + .act_hid = BNXT_ULP_ACT_HID_4ece, + .act_pattern_id = 180, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 + .act_tid = 7 }, - [69] = { - .act_hid = BNXT_ULP_ACT_HID_02c4, - .act_pattern_id = 1, + [500] = { + .act_hid = BNXT_ULP_ACT_HID_0622, + .act_pattern_id = 181, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 + .act_tid = 7 }, - [70] = { - .act_hid = BNXT_ULP_ACT_HID_042a, - .act_pattern_id = 2, + [501] = { + .act_hid = BNXT_ULP_ACT_HID_5fde, + .act_pattern_id = 182, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 + .act_tid = 7 }, - [71] = { - .act_hid = BNXT_ULP_ACT_HID_036e, - .act_pattern_id = 3, + [502] = { + .act_hid = BNXT_ULP_ACT_HID_4a42, + .act_pattern_id = 183, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_ACT_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 + .act_tid = 7 }, - [72] = { - .act_hid = BNXT_ULP_ACT_HID_06c4, - .act_pattern_id = 4, + [503] = { + .act_hid = BNXT_ULP_ACT_HID_0196, + .act_pattern_id = 184, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_ACT_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 + .act_tid = 7 }, - [73] = { - .act_hid = BNXT_ULP_ACT_HID_0417, - .act_pattern_id = 5, + [504] = { + .act_hid = BNXT_ULP_ACT_HID_12a6, + .act_pattern_id = 185, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_ACT_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 + .act_tid = 7 }, - [74] = { - .act_hid = BNXT_ULP_ACT_HID_06d9, - .act_pattern_id = 6, + [505] = { + .act_hid = BNXT_ULP_ACT_HID_4ede, + .act_pattern_id = 186, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 + .act_tid = 7 }, - [75] = { - .act_hid = BNXT_ULP_ACT_HID_02c6, - .act_pattern_id = 7, + [506] = { + .act_hid = BNXT_ULP_ACT_HID_0632, + .act_pattern_id = 187, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 + .act_tid = 7 }, - [76] = { - .act_hid = BNXT_ULP_ACT_HID_042c, - .act_pattern_id = 8, + [507] = { + .act_hid = BNXT_ULP_ACT_HID_5fee, + .act_pattern_id = 188, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 + .act_tid = 7 }, - [77] = { - .act_hid = BNXT_ULP_ACT_HID_0370, - .act_pattern_id = 9, + [508] = { + .act_hid = BNXT_ULP_ACT_HID_4a52, + .act_pattern_id = 189, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_ACT_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 + .act_tid = 7 }, - [78] = { - .act_hid = BNXT_ULP_ACT_HID_06c6, - .act_pattern_id = 10, + [509] = { + .act_hid = BNXT_ULP_ACT_HID_01a6, + .act_pattern_id = 190, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_ACT_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 + .act_tid = 7 }, - [79] = { - .act_hid = BNXT_ULP_ACT_HID_0419, - .act_pattern_id = 11, + [510] = { + .act_hid = BNXT_ULP_ACT_HID_12b6, + .act_pattern_id = 191, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_ACT_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 + .act_tid = 7 }, - [80] = { - .act_hid = BNXT_ULP_ACT_HID_0119, - .act_pattern_id = 12, + [511] = { + .act_hid = BNXT_ULP_ACT_HID_56ce, + .act_pattern_id = 192, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 + .act_tid = 7 }, - [81] = { - .act_hid = BNXT_ULP_ACT_HID_046f, - .act_pattern_id = 13, + [512] = { + .act_hid = BNXT_ULP_ACT_HID_0e22, + .act_pattern_id = 193, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 + .act_tid = 7 }, - [82] = { - .act_hid = BNXT_ULP_ACT_HID_05d5, - .act_pattern_id = 14, + [513] = { + .act_hid = BNXT_ULP_ACT_HID_67de, + .act_pattern_id = 194, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 + .act_tid = 7 }, - [83] = { - .act_hid = BNXT_ULP_ACT_HID_0519, - .act_pattern_id = 15, + [514] = { + .act_hid = BNXT_ULP_ACT_HID_5242, + .act_pattern_id = 195, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_ACT_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 + .act_tid = 7 }, - [84] = { - .act_hid = BNXT_ULP_ACT_HID_0106, - .act_pattern_id = 16, + [515] = { + .act_hid = BNXT_ULP_ACT_HID_0996, + .act_pattern_id = 196, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_ACT_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 + .act_tid = 7 }, - [85] = { - .act_hid = BNXT_ULP_ACT_HID_05c2, - .act_pattern_id = 17, + [516] = { + .act_hid = BNXT_ULP_ACT_HID_1aa6, + .act_pattern_id = 197, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_ACT_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 + .act_tid = 7 }, - [86] = { - .act_hid = BNXT_ULP_ACT_HID_011b, - .act_pattern_id = 18, + [517] = { + .act_hid = BNXT_ULP_ACT_HID_56de, + .act_pattern_id = 198, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 + .act_tid = 7 }, - [87] = { - .act_hid = BNXT_ULP_ACT_HID_0471, - .act_pattern_id = 19, + [518] = { + .act_hid = BNXT_ULP_ACT_HID_0e32, + .act_pattern_id = 199, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 + .act_tid = 7 }, - [88] = { - .act_hid = BNXT_ULP_ACT_HID_05d7, - .act_pattern_id = 20, + [519] = { + .act_hid = BNXT_ULP_ACT_HID_67ee, + .act_pattern_id = 200, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 + .act_tid = 7 }, - [89] = { - .act_hid = BNXT_ULP_ACT_HID_051b, - .act_pattern_id = 21, + [520] = { + .act_hid = BNXT_ULP_ACT_HID_5252, + .act_pattern_id = 201, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_ACT_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 + .act_tid = 7 }, - [90] = { - .act_hid = BNXT_ULP_ACT_HID_0108, - .act_pattern_id = 22, + [521] = { + .act_hid = BNXT_ULP_ACT_HID_09a6, + .act_pattern_id = 202, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_ACT_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 + .act_tid = 7 }, - [91] = { - .act_hid = BNXT_ULP_ACT_HID_05c4, - .act_pattern_id = 23, + [522] = { + .act_hid = BNXT_ULP_ACT_HID_1ab6, + .act_pattern_id = 203, .app_sig = 0, .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -1089,25 +6906,256 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_ACT_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 5 + .act_tid = 7 }, - [92] = { - .act_hid = BNXT_ULP_ACT_HID_00a2, + [523] = { + .act_hid = BNXT_ULP_ACT_HID_31d0, .act_pattern_id = 0, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_VXLAN_ENCAP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 + .act_tid = 8 }, - [93] = { - .act_hid = BNXT_ULP_ACT_HID_00a4, + [524] = { + .act_hid = BNXT_ULP_ACT_HID_31e0, .act_pattern_id = 1, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_VXLAN_ENCAP | BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 + .act_tid = 8 + }, + [525] = { + .act_hid = BNXT_ULP_ACT_HID_39d0, + .act_pattern_id = 2, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_VXLAN_ENCAP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 8 + }, + [526] = { + .act_hid = BNXT_ULP_ACT_HID_39e0, + .act_pattern_id = 3, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_VXLAN_ENCAP | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 8 + }, + [527] = { + .act_hid = BNXT_ULP_ACT_HID_41d0, + .act_pattern_id = 4, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_VXLAN_ENCAP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 8 + }, + [528] = { + .act_hid = BNXT_ULP_ACT_HID_41e0, + .act_pattern_id = 5, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_VXLAN_ENCAP | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 8 + }, + [529] = { + .act_hid = BNXT_ULP_ACT_HID_49d0, + .act_pattern_id = 6, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_VXLAN_ENCAP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 8 + }, + [530] = { + .act_hid = BNXT_ULP_ACT_HID_49e0, + .act_pattern_id = 7, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_VXLAN_ENCAP | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 8 + }, + [531] = { + .act_hid = BNXT_ULP_ACT_HID_64ba, + .act_pattern_id = 8, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_VXLAN_ENCAP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 8 + }, + [532] = { + .act_hid = BNXT_ULP_ACT_HID_64ca, + .act_pattern_id = 9, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_VXLAN_ENCAP | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 8 + }, + [533] = { + .act_hid = BNXT_ULP_ACT_HID_6cba, + .act_pattern_id = 10, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_VXLAN_ENCAP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 8 + }, + [534] = { + .act_hid = BNXT_ULP_ACT_HID_6cca, + .act_pattern_id = 11, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_VXLAN_ENCAP | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 8 + }, + [535] = { + .act_hid = BNXT_ULP_ACT_HID_74ba, + .act_pattern_id = 12, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_VXLAN_ENCAP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 8 + }, + [536] = { + .act_hid = BNXT_ULP_ACT_HID_74ca, + .act_pattern_id = 13, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_VXLAN_ENCAP | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 8 + }, + [537] = { + .act_hid = BNXT_ULP_ACT_HID_00fe, + .act_pattern_id = 14, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_VXLAN_ENCAP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 8 + }, + [538] = { + .act_hid = BNXT_ULP_ACT_HID_010e, + .act_pattern_id = 15, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_SET_MAC_SRC | + BNXT_ULP_ACT_BIT_SET_MAC_DST | + BNXT_ULP_ACT_BIT_VXLAN_ENCAP | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 8 + }, + [539] = { + .act_hid = BNXT_ULP_ACT_HID_331c, + .act_pattern_id = 0, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_VF_TO_VF | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 9 + }, + [540] = { + .act_hid = BNXT_ULP_ACT_HID_332c, + .act_pattern_id = 1, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_VF_TO_VF | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 9 + }, + [541] = { + .act_hid = BNXT_ULP_ACT_HID_6706, + .act_pattern_id = 2, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_VF_TO_VF | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 9 + }, + [542] = { + .act_hid = BNXT_ULP_ACT_HID_6716, + .act_pattern_id = 3, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_ACT_BIT_VF_TO_VF | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 9 + }, + [543] = { + .act_hid = BNXT_ULP_ACT_HID_1b6d, + .act_pattern_id = 0, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED | + BNXT_ULP_ACT_BIT_SAMPLE | + BNXT_ULP_ACT_BIT_VF_TO_VF | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 10 + }, + [544] = { + .act_hid = BNXT_ULP_ACT_HID_1b7d, + .act_pattern_id = 1, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SHARED | + BNXT_ULP_ACT_BIT_SAMPLE | + BNXT_ULP_ACT_BIT_VF_TO_VF | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 10 + }, + [545] = { + .act_hid = BNXT_ULP_ACT_HID_641a, + .act_pattern_id = 2, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DELETE | + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 10 } }; + diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c index c127a53b32..70409edb68 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c @@ -1,10 +1,8 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2021 Broadcom + * Copyright(c) 2014-2023 Broadcom * All rights reserved. */ -/* date: Wed Nov 24 17:15:38 2021 */ - #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" #include "ulp_template_struct.h" @@ -16,1308 +14,1918 @@ * maps hash id to ulp_class_match_list[] index */ uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = { - [BNXT_ULP_CLASS_HID_55dd] = 1, - [BNXT_ULP_CLASS_HID_1df1] = 2, - [BNXT_ULP_CLASS_HID_3e55] = 3, - [BNXT_ULP_CLASS_HID_0649] = 4, - [BNXT_ULP_CLASS_HID_1011] = 5, - [BNXT_ULP_CLASS_HID_40e9] = 6, - [BNXT_ULP_CLASS_HID_3e99] = 7, - [BNXT_ULP_CLASS_HID_06ad] = 8, - [BNXT_ULP_CLASS_HID_38c7] = 9, - [BNXT_ULP_CLASS_HID_00fb] = 10, - [BNXT_ULP_CLASS_HID_24d3] = 11, - [BNXT_ULP_CLASS_HID_559b] = 12, - [BNXT_ULP_CLASS_HID_5003] = 13, - [BNXT_ULP_CLASS_HID_1837] = 14, - [BNXT_ULP_CLASS_HID_3bef] = 15, - [BNXT_ULP_CLASS_HID_0403] = 16, - [BNXT_ULP_CLASS_HID_3d3f] = 17, - [BNXT_ULP_CLASS_HID_0543] = 18, - [BNXT_ULP_CLASS_HID_292b] = 19, - [BNXT_ULP_CLASS_HID_59e3] = 20, - [BNXT_ULP_CLASS_HID_5d3b] = 21, - [BNXT_ULP_CLASS_HID_254f] = 22, - [BNXT_ULP_CLASS_HID_4917] = 23, - [BNXT_ULP_CLASS_HID_113b] = 24, - [BNXT_ULP_CLASS_HID_55fd] = 25, - [BNXT_ULP_CLASS_HID_1dd1] = 26, - [BNXT_ULP_CLASS_HID_3e75] = 27, - [BNXT_ULP_CLASS_HID_0669] = 28, - [BNXT_ULP_CLASS_HID_1ba1] = 29, - [BNXT_ULP_CLASS_HID_4c69] = 30, - [BNXT_ULP_CLASS_HID_0439] = 31, - [BNXT_ULP_CLASS_HID_34e1] = 32, - [BNXT_ULP_CLASS_HID_0465] = 33, - [BNXT_ULP_CLASS_HID_352d] = 34, - [BNXT_ULP_CLASS_HID_55b1] = 35, - [BNXT_ULP_CLASS_HID_1da5] = 36, - [BNXT_ULP_CLASS_HID_32fd] = 37, - [BNXT_ULP_CLASS_HID_63a5] = 38, - [BNXT_ULP_CLASS_HID_1b75] = 39, - [BNXT_ULP_CLASS_HID_4c3d] = 40, - [BNXT_ULP_CLASS_HID_1031] = 41, - [BNXT_ULP_CLASS_HID_40c9] = 42, - [BNXT_ULP_CLASS_HID_3eb9] = 43, - [BNXT_ULP_CLASS_HID_068d] = 44, - [BNXT_ULP_CLASS_HID_5039] = 45, - [BNXT_ULP_CLASS_HID_180d] = 46, - [BNXT_ULP_CLASS_HID_15fd] = 47, - [BNXT_ULP_CLASS_HID_46b5] = 48, - [BNXT_ULP_CLASS_HID_303d] = 49, - [BNXT_ULP_CLASS_HID_60f5] = 50, - [BNXT_ULP_CLASS_HID_5ea5] = 51, - [BNXT_ULP_CLASS_HID_2689] = 52, - [BNXT_ULP_CLASS_HID_0771] = 53, - [BNXT_ULP_CLASS_HID_3809] = 54, - [BNXT_ULP_CLASS_HID_35f9] = 55, - [BNXT_ULP_CLASS_HID_66b1] = 56, - [BNXT_ULP_CLASS_HID_559d] = 57, - [BNXT_ULP_CLASS_HID_1db1] = 58, - [BNXT_ULP_CLASS_HID_3e15] = 59, - [BNXT_ULP_CLASS_HID_0609] = 60, - [BNXT_ULP_CLASS_HID_1bc1] = 61, - [BNXT_ULP_CLASS_HID_4c09] = 62, - [BNXT_ULP_CLASS_HID_0459] = 63, - [BNXT_ULP_CLASS_HID_3481] = 64, - [BNXT_ULP_CLASS_HID_0405] = 65, - [BNXT_ULP_CLASS_HID_354d] = 66, - [BNXT_ULP_CLASS_HID_55d1] = 67, - [BNXT_ULP_CLASS_HID_1dc5] = 68, - [BNXT_ULP_CLASS_HID_329d] = 69, - [BNXT_ULP_CLASS_HID_63c5] = 70, - [BNXT_ULP_CLASS_HID_1b15] = 71, - [BNXT_ULP_CLASS_HID_4c5d] = 72, - [BNXT_ULP_CLASS_HID_1051] = 73, - [BNXT_ULP_CLASS_HID_40a9] = 74, - [BNXT_ULP_CLASS_HID_3ed9] = 75, - [BNXT_ULP_CLASS_HID_06ed] = 76, - [BNXT_ULP_CLASS_HID_5059] = 77, - [BNXT_ULP_CLASS_HID_186d] = 78, - [BNXT_ULP_CLASS_HID_159d] = 79, - [BNXT_ULP_CLASS_HID_46d5] = 80, - [BNXT_ULP_CLASS_HID_305d] = 81, - [BNXT_ULP_CLASS_HID_6095] = 82, - [BNXT_ULP_CLASS_HID_5ec5] = 83, - [BNXT_ULP_CLASS_HID_26e9] = 84, - [BNXT_ULP_CLASS_HID_0711] = 85, - [BNXT_ULP_CLASS_HID_3869] = 86, - [BNXT_ULP_CLASS_HID_3599] = 87, - [BNXT_ULP_CLASS_HID_66d1] = 88, - [BNXT_ULP_CLASS_HID_38e7] = 89, - [BNXT_ULP_CLASS_HID_00db] = 90, - [BNXT_ULP_CLASS_HID_24f3] = 91, - [BNXT_ULP_CLASS_HID_55bb] = 92, - [BNXT_ULP_CLASS_HID_5023] = 93, - [BNXT_ULP_CLASS_HID_1817] = 94, - [BNXT_ULP_CLASS_HID_3bcf] = 95, - [BNXT_ULP_CLASS_HID_0423] = 96, - [BNXT_ULP_CLASS_HID_58e3] = 97, - [BNXT_ULP_CLASS_HID_20d7] = 98, - [BNXT_ULP_CLASS_HID_448f] = 99, - [BNXT_ULP_CLASS_HID_0ce3] = 100, - [BNXT_ULP_CLASS_HID_076b] = 101, - [BNXT_ULP_CLASS_HID_3813] = 102, - [BNXT_ULP_CLASS_HID_5bcb] = 103, - [BNXT_ULP_CLASS_HID_243f] = 104, - [BNXT_ULP_CLASS_HID_144b] = 105, - [BNXT_ULP_CLASS_HID_4573] = 106, - [BNXT_ULP_CLASS_HID_0057] = 107, - [BNXT_ULP_CLASS_HID_311f] = 108, - [BNXT_ULP_CLASS_HID_2b87] = 109, - [BNXT_ULP_CLASS_HID_5c4f] = 110, - [BNXT_ULP_CLASS_HID_1793] = 111, - [BNXT_ULP_CLASS_HID_485b] = 112, - [BNXT_ULP_CLASS_HID_3447] = 113, - [BNXT_ULP_CLASS_HID_650f] = 114, - [BNXT_ULP_CLASS_HID_2053] = 115, - [BNXT_ULP_CLASS_HID_511b] = 116, - [BNXT_ULP_CLASS_HID_4b83] = 117, - [BNXT_ULP_CLASS_HID_13f7] = 118, - [BNXT_ULP_CLASS_HID_37af] = 119, - [BNXT_ULP_CLASS_HID_6857] = 120, - [BNXT_ULP_CLASS_HID_3d1f] = 121, - [BNXT_ULP_CLASS_HID_0563] = 122, - [BNXT_ULP_CLASS_HID_290b] = 123, - [BNXT_ULP_CLASS_HID_59c3] = 124, - [BNXT_ULP_CLASS_HID_5d1b] = 125, - [BNXT_ULP_CLASS_HID_256f] = 126, - [BNXT_ULP_CLASS_HID_4937] = 127, - [BNXT_ULP_CLASS_HID_111b] = 128, - [BNXT_ULP_CLASS_HID_25f4b] = 129, - [BNXT_ULP_CLASS_HID_2275f] = 130, - [BNXT_ULP_CLASS_HID_24b67] = 131, - [BNXT_ULP_CLASS_HID_2134b] = 132, - [BNXT_ULP_CLASS_HID_21683] = 133, - [BNXT_ULP_CLASS_HID_2475b] = 134, - [BNXT_ULP_CLASS_HID_202bf] = 135, - [BNXT_ULP_CLASS_HID_23377] = 136, - [BNXT_ULP_CLASS_HID_119db] = 137, - [BNXT_ULP_CLASS_HID_14a93] = 138, - [BNXT_ULP_CLASS_HID_105f7] = 139, - [BNXT_ULP_CLASS_HID_1368f] = 140, - [BNXT_ULP_CLASS_HID_139c7] = 141, - [BNXT_ULP_CLASS_HID_1022b] = 142, - [BNXT_ULP_CLASS_HID_125f3] = 143, - [BNXT_ULP_CLASS_HID_1568b] = 144, - [BNXT_ULP_CLASS_HID_33c37] = 145, - [BNXT_ULP_CLASS_HID_3041b] = 146, - [BNXT_ULP_CLASS_HID_32823] = 147, - [BNXT_ULP_CLASS_HID_358fb] = 148, - [BNXT_ULP_CLASS_HID_35c33] = 149, - [BNXT_ULP_CLASS_HID_32407] = 150, - [BNXT_ULP_CLASS_HID_3482f] = 151, - [BNXT_ULP_CLASS_HID_31033] = 152, - [BNXT_ULP_CLASS_HID_3887] = 153, - [BNXT_ULP_CLASS_HID_00bb] = 154, - [BNXT_ULP_CLASS_HID_2493] = 155, - [BNXT_ULP_CLASS_HID_55db] = 156, - [BNXT_ULP_CLASS_HID_5043] = 157, - [BNXT_ULP_CLASS_HID_1877] = 158, - [BNXT_ULP_CLASS_HID_3baf] = 159, - [BNXT_ULP_CLASS_HID_0443] = 160, - [BNXT_ULP_CLASS_HID_5883] = 161, - [BNXT_ULP_CLASS_HID_20b7] = 162, - [BNXT_ULP_CLASS_HID_44ef] = 163, - [BNXT_ULP_CLASS_HID_0c83] = 164, - [BNXT_ULP_CLASS_HID_070b] = 165, - [BNXT_ULP_CLASS_HID_3873] = 166, - [BNXT_ULP_CLASS_HID_5bab] = 167, - [BNXT_ULP_CLASS_HID_245f] = 168, - [BNXT_ULP_CLASS_HID_142b] = 169, - [BNXT_ULP_CLASS_HID_4513] = 170, - [BNXT_ULP_CLASS_HID_0037] = 171, - [BNXT_ULP_CLASS_HID_317f] = 172, - [BNXT_ULP_CLASS_HID_2be7] = 173, - [BNXT_ULP_CLASS_HID_5c2f] = 174, - [BNXT_ULP_CLASS_HID_17f3] = 175, - [BNXT_ULP_CLASS_HID_483b] = 176, - [BNXT_ULP_CLASS_HID_3427] = 177, - [BNXT_ULP_CLASS_HID_656f] = 178, - [BNXT_ULP_CLASS_HID_2033] = 179, - [BNXT_ULP_CLASS_HID_517b] = 180, - [BNXT_ULP_CLASS_HID_4be3] = 181, - [BNXT_ULP_CLASS_HID_1397] = 182, - [BNXT_ULP_CLASS_HID_37cf] = 183, - [BNXT_ULP_CLASS_HID_6837] = 184, - [BNXT_ULP_CLASS_HID_3d7f] = 185, - [BNXT_ULP_CLASS_HID_0503] = 186, - [BNXT_ULP_CLASS_HID_296b] = 187, - [BNXT_ULP_CLASS_HID_59a3] = 188, - [BNXT_ULP_CLASS_HID_5d7b] = 189, - [BNXT_ULP_CLASS_HID_250f] = 190, - [BNXT_ULP_CLASS_HID_4957] = 191, - [BNXT_ULP_CLASS_HID_117b] = 192, - [BNXT_ULP_CLASS_HID_25f2b] = 193, - [BNXT_ULP_CLASS_HID_2273f] = 194, - [BNXT_ULP_CLASS_HID_24b07] = 195, - [BNXT_ULP_CLASS_HID_2132b] = 196, - [BNXT_ULP_CLASS_HID_216e3] = 197, - [BNXT_ULP_CLASS_HID_2473b] = 198, - [BNXT_ULP_CLASS_HID_202df] = 199, - [BNXT_ULP_CLASS_HID_23317] = 200, - [BNXT_ULP_CLASS_HID_119bb] = 201, - [BNXT_ULP_CLASS_HID_14af3] = 202, - [BNXT_ULP_CLASS_HID_10597] = 203, - [BNXT_ULP_CLASS_HID_136ef] = 204, - [BNXT_ULP_CLASS_HID_139a7] = 205, - [BNXT_ULP_CLASS_HID_1024b] = 206, - [BNXT_ULP_CLASS_HID_12593] = 207, - [BNXT_ULP_CLASS_HID_156eb] = 208, - [BNXT_ULP_CLASS_HID_33c57] = 209, - [BNXT_ULP_CLASS_HID_3047b] = 210, - [BNXT_ULP_CLASS_HID_32843] = 211, - [BNXT_ULP_CLASS_HID_3589b] = 212, - [BNXT_ULP_CLASS_HID_35c53] = 213, - [BNXT_ULP_CLASS_HID_32467] = 214, - [BNXT_ULP_CLASS_HID_3484f] = 215, - [BNXT_ULP_CLASS_HID_31053] = 216, - [BNXT_ULP_CLASS_HID_5ce1] = 217, - [BNXT_ULP_CLASS_HID_4579] = 218, - [BNXT_ULP_CLASS_HID_1735] = 219, - [BNXT_ULP_CLASS_HID_45bd] = 220, - [BNXT_ULP_CLASS_HID_3feb] = 221, - [BNXT_ULP_CLASS_HID_2bf7] = 222, - [BNXT_ULP_CLASS_HID_5727] = 223, - [BNXT_ULP_CLASS_HID_4333] = 224, - [BNXT_ULP_CLASS_HID_4453] = 225, - [BNXT_ULP_CLASS_HID_304f] = 226, - [BNXT_ULP_CLASS_HID_645f] = 227, - [BNXT_ULP_CLASS_HID_504b] = 228, - [BNXT_ULP_CLASS_HID_5cc1] = 229, - [BNXT_ULP_CLASS_HID_4559] = 230, - [BNXT_ULP_CLASS_HID_2285] = 231, - [BNXT_ULP_CLASS_HID_0b1d] = 232, - [BNXT_ULP_CLASS_HID_0b49] = 233, - [BNXT_ULP_CLASS_HID_5c95] = 234, - [BNXT_ULP_CLASS_HID_39c1] = 235, - [BNXT_ULP_CLASS_HID_2259] = 236, - [BNXT_ULP_CLASS_HID_1715] = 237, - [BNXT_ULP_CLASS_HID_459d] = 238, - [BNXT_ULP_CLASS_HID_571d] = 239, - [BNXT_ULP_CLASS_HID_1cd1] = 240, - [BNXT_ULP_CLASS_HID_3711] = 241, - [BNXT_ULP_CLASS_HID_6599] = 242, - [BNXT_ULP_CLASS_HID_0e55] = 243, - [BNXT_ULP_CLASS_HID_3cdd] = 244, - [BNXT_ULP_CLASS_HID_5ca1] = 245, - [BNXT_ULP_CLASS_HID_4539] = 246, - [BNXT_ULP_CLASS_HID_22e5] = 247, - [BNXT_ULP_CLASS_HID_0b7d] = 248, - [BNXT_ULP_CLASS_HID_0b29] = 249, - [BNXT_ULP_CLASS_HID_5cf5] = 250, - [BNXT_ULP_CLASS_HID_39a1] = 251, - [BNXT_ULP_CLASS_HID_2239] = 252, - [BNXT_ULP_CLASS_HID_1775] = 253, - [BNXT_ULP_CLASS_HID_45fd] = 254, - [BNXT_ULP_CLASS_HID_577d] = 255, - [BNXT_ULP_CLASS_HID_1cb1] = 256, - [BNXT_ULP_CLASS_HID_3771] = 257, - [BNXT_ULP_CLASS_HID_65f9] = 258, - [BNXT_ULP_CLASS_HID_0e35] = 259, - [BNXT_ULP_CLASS_HID_3cbd] = 260, - [BNXT_ULP_CLASS_HID_3fcb] = 261, - [BNXT_ULP_CLASS_HID_2bd7] = 262, - [BNXT_ULP_CLASS_HID_5707] = 263, - [BNXT_ULP_CLASS_HID_4313] = 264, - [BNXT_ULP_CLASS_HID_5fc7] = 265, - [BNXT_ULP_CLASS_HID_4bd3] = 266, - [BNXT_ULP_CLASS_HID_0e4f] = 267, - [BNXT_ULP_CLASS_HID_632f] = 268, - [BNXT_ULP_CLASS_HID_1baf] = 269, - [BNXT_ULP_CLASS_HID_07bb] = 270, - [BNXT_ULP_CLASS_HID_32eb] = 271, - [BNXT_ULP_CLASS_HID_1ef7] = 272, - [BNXT_ULP_CLASS_HID_3bab] = 273, - [BNXT_ULP_CLASS_HID_27b7] = 274, - [BNXT_ULP_CLASS_HID_52e7] = 275, - [BNXT_ULP_CLASS_HID_3ef3] = 276, - [BNXT_ULP_CLASS_HID_4473] = 277, - [BNXT_ULP_CLASS_HID_306f] = 278, - [BNXT_ULP_CLASS_HID_647f] = 279, - [BNXT_ULP_CLASS_HID_506b] = 280, - [BNXT_ULP_CLASS_HID_266af] = 281, - [BNXT_ULP_CLASS_HID_2525b] = 282, - [BNXT_ULP_CLASS_HID_21de7] = 283, - [BNXT_ULP_CLASS_HID_20993] = 284, - [BNXT_ULP_CLASS_HID_1213f] = 285, - [BNXT_ULP_CLASS_HID_10d2b] = 286, - [BNXT_ULP_CLASS_HID_1413b] = 287, - [BNXT_ULP_CLASS_HID_12cd7] = 288, - [BNXT_ULP_CLASS_HID_3436b] = 289, - [BNXT_ULP_CLASS_HID_32f07] = 290, - [BNXT_ULP_CLASS_HID_36317] = 291, - [BNXT_ULP_CLASS_HID_34f03] = 292, - [BNXT_ULP_CLASS_HID_3fab] = 293, - [BNXT_ULP_CLASS_HID_2bb7] = 294, - [BNXT_ULP_CLASS_HID_5767] = 295, - [BNXT_ULP_CLASS_HID_4373] = 296, - [BNXT_ULP_CLASS_HID_5fa7] = 297, - [BNXT_ULP_CLASS_HID_4bb3] = 298, - [BNXT_ULP_CLASS_HID_0e2f] = 299, - [BNXT_ULP_CLASS_HID_634f] = 300, - [BNXT_ULP_CLASS_HID_1bcf] = 301, - [BNXT_ULP_CLASS_HID_07db] = 302, - [BNXT_ULP_CLASS_HID_328b] = 303, - [BNXT_ULP_CLASS_HID_1e97] = 304, - [BNXT_ULP_CLASS_HID_3bcb] = 305, - [BNXT_ULP_CLASS_HID_27d7] = 306, - [BNXT_ULP_CLASS_HID_5287] = 307, - [BNXT_ULP_CLASS_HID_3e93] = 308, - [BNXT_ULP_CLASS_HID_4413] = 309, - [BNXT_ULP_CLASS_HID_300f] = 310, - [BNXT_ULP_CLASS_HID_641f] = 311, - [BNXT_ULP_CLASS_HID_500b] = 312, - [BNXT_ULP_CLASS_HID_266cf] = 313, - [BNXT_ULP_CLASS_HID_2523b] = 314, - [BNXT_ULP_CLASS_HID_21d87] = 315, - [BNXT_ULP_CLASS_HID_209f3] = 316, - [BNXT_ULP_CLASS_HID_1215f] = 317, - [BNXT_ULP_CLASS_HID_10d4b] = 318, - [BNXT_ULP_CLASS_HID_1415b] = 319, - [BNXT_ULP_CLASS_HID_12cb7] = 320, - [BNXT_ULP_CLASS_HID_3430b] = 321, - [BNXT_ULP_CLASS_HID_32f67] = 322, - [BNXT_ULP_CLASS_HID_36377] = 323, - [BNXT_ULP_CLASS_HID_34f63] = 324, - [BNXT_ULP_CLASS_HID_29b5] = 325, - [BNXT_ULP_CLASS_HID_29ad] = 326, - [BNXT_ULP_CLASS_HID_29b7] = 327, - [BNXT_ULP_CLASS_HID_1583] = 328, - [BNXT_ULP_CLASS_HID_29af] = 329, - [BNXT_ULP_CLASS_HID_159b] = 330, - [BNXT_ULP_CLASS_HID_2995] = 331, - [BNXT_ULP_CLASS_HID_298d] = 332, - [BNXT_ULP_CLASS_HID_29f5] = 333, - [BNXT_ULP_CLASS_HID_29ed] = 334, - [BNXT_ULP_CLASS_HID_2997] = 335, - [BNXT_ULP_CLASS_HID_15a3] = 336, - [BNXT_ULP_CLASS_HID_298f] = 337, - [BNXT_ULP_CLASS_HID_15bb] = 338, - [BNXT_ULP_CLASS_HID_29f7] = 339, - [BNXT_ULP_CLASS_HID_15c3] = 340, - [BNXT_ULP_CLASS_HID_29ef] = 341, - [BNXT_ULP_CLASS_HID_15db] = 342, - [BNXT_ULP_CLASS_HID_1151] = 343, - [BNXT_ULP_CLASS_HID_315d] = 344, - [BNXT_ULP_CLASS_HID_3612] = 345, - [BNXT_ULP_CLASS_HID_66da] = 346, - [BNXT_ULP_CLASS_HID_243ca] = 347, - [BNXT_ULP_CLASS_HID_20d8e] = 348, - [BNXT_ULP_CLASS_HID_2e082] = 349, - [BNXT_ULP_CLASS_HID_2ab46] = 350, - [BNXT_ULP_CLASS_HID_25226] = 351, - [BNXT_ULP_CLASS_HID_25cea] = 352, - [BNXT_ULP_CLASS_HID_2c82a] = 353, - [BNXT_ULP_CLASS_HID_2f9a2] = 354, - [BNXT_ULP_CLASS_HID_23b56] = 355, - [BNXT_ULP_CLASS_HID_205da] = 356, - [BNXT_ULP_CLASS_HID_2d8ce] = 357, - [BNXT_ULP_CLASS_HID_2a2d2] = 358, - [BNXT_ULP_CLASS_HID_24a72] = 359, - [BNXT_ULP_CLASS_HID_25476] = 360, - [BNXT_ULP_CLASS_HID_2c076] = 361, - [BNXT_ULP_CLASS_HID_2f1ee] = 362, - [BNXT_ULP_CLASS_HID_20bb6] = 363, - [BNXT_ULP_CLASS_HID_23d2e] = 364, - [BNXT_ULP_CLASS_HID_2a96e] = 365, - [BNXT_ULP_CLASS_HID_2dae6] = 366, - [BNXT_ULP_CLASS_HID_25af2] = 367, - [BNXT_ULP_CLASS_HID_24c6a] = 368, - [BNXT_ULP_CLASS_HID_2c7aa] = 369, - [BNXT_ULP_CLASS_HID_2c26e] = 370, - [BNXT_ULP_CLASS_HID_203e2] = 371, - [BNXT_ULP_CLASS_HID_2357a] = 372, - [BNXT_ULP_CLASS_HID_2a0fa] = 373, - [BNXT_ULP_CLASS_HID_2d272] = 374, - [BNXT_ULP_CLASS_HID_2527e] = 375, - [BNXT_ULP_CLASS_HID_243f6] = 376, - [BNXT_ULP_CLASS_HID_2fff6] = 377, - [BNXT_ULP_CLASS_HID_2e16e] = 378, - [BNXT_ULP_CLASS_HID_2422d] = 379, - [BNXT_ULP_CLASS_HID_20c69] = 380, - [BNXT_ULP_CLASS_HID_2e165] = 381, - [BNXT_ULP_CLASS_HID_2aaa1] = 382, - [BNXT_ULP_CLASS_HID_253c1] = 383, - [BNXT_ULP_CLASS_HID_25d0d] = 384, - [BNXT_ULP_CLASS_HID_2c9cd] = 385, - [BNXT_ULP_CLASS_HID_2f845] = 386, - [BNXT_ULP_CLASS_HID_25afd] = 387, - [BNXT_ULP_CLASS_HID_22439] = 388, - [BNXT_ULP_CLASS_HID_290f9] = 389, - [BNXT_ULP_CLASS_HID_2c371] = 390, - [BNXT_ULP_CLASS_HID_24355] = 391, - [BNXT_ULP_CLASS_HID_275dd] = 392, - [BNXT_ULP_CLASS_HID_2e19d] = 393, - [BNXT_ULP_CLASS_HID_2d015] = 394, - [BNXT_ULP_CLASS_HID_2560d] = 395, - [BNXT_ULP_CLASS_HID_21049] = 396, - [BNXT_ULP_CLASS_HID_28c09] = 397, - [BNXT_ULP_CLASS_HID_2be89] = 398, - [BNXT_ULP_CLASS_HID_267a9] = 399, - [BNXT_ULP_CLASS_HID_261ed] = 400, - [BNXT_ULP_CLASS_HID_2ddad] = 401, - [BNXT_ULP_CLASS_HID_2cc2d] = 402, - [BNXT_ULP_CLASS_HID_26edd] = 403, - [BNXT_ULP_CLASS_HID_22819] = 404, - [BNXT_ULP_CLASS_HID_2a4d9] = 405, - [BNXT_ULP_CLASS_HID_2d759] = 406, - [BNXT_ULP_CLASS_HID_2573d] = 407, - [BNXT_ULP_CLASS_HID_279bd] = 408, - [BNXT_ULP_CLASS_HID_2f27d] = 409, - [BNXT_ULP_CLASS_HID_2e4fd] = 410, - [BNXT_ULP_CLASS_HID_24fbe] = 411, - [BNXT_ULP_CLASS_HID_201fa] = 412, - [BNXT_ULP_CLASS_HID_2ecf6] = 413, - [BNXT_ULP_CLASS_HID_2a732] = 414, - [BNXT_ULP_CLASS_HID_25e52] = 415, - [BNXT_ULP_CLASS_HID_2509e] = 416, - [BNXT_ULP_CLASS_HID_2c45e] = 417, - [BNXT_ULP_CLASS_HID_2f5d6] = 418, - [BNXT_ULP_CLASS_HID_23722] = 419, - [BNXT_ULP_CLASS_HID_209ae] = 420, - [BNXT_ULP_CLASS_HID_2d4ba] = 421, - [BNXT_ULP_CLASS_HID_2aea6] = 422, - [BNXT_ULP_CLASS_HID_24606] = 423, - [BNXT_ULP_CLASS_HID_25802] = 424, - [BNXT_ULP_CLASS_HID_2cc02] = 425, - [BNXT_ULP_CLASS_HID_2fd9a] = 426, - [BNXT_ULP_CLASS_HID_207c2] = 427, - [BNXT_ULP_CLASS_HID_2315a] = 428, - [BNXT_ULP_CLASS_HID_2a51a] = 429, - [BNXT_ULP_CLASS_HID_2d692] = 430, - [BNXT_ULP_CLASS_HID_25686] = 431, - [BNXT_ULP_CLASS_HID_2401e] = 432, - [BNXT_ULP_CLASS_HID_2cbde] = 433, - [BNXT_ULP_CLASS_HID_2ce1a] = 434, - [BNXT_ULP_CLASS_HID_20f96] = 435, - [BNXT_ULP_CLASS_HID_2390e] = 436, - [BNXT_ULP_CLASS_HID_2ac8e] = 437, - [BNXT_ULP_CLASS_HID_2de06] = 438, - [BNXT_ULP_CLASS_HID_25e0a] = 439, - [BNXT_ULP_CLASS_HID_24f82] = 440, - [BNXT_ULP_CLASS_HID_2f382] = 441, - [BNXT_ULP_CLASS_HID_2ed1a] = 442, - [BNXT_ULP_CLASS_HID_2576e] = 443, - [BNXT_ULP_CLASS_HID_229aa] = 444, - [BNXT_ULP_CLASS_HID_29d6a] = 445, - [BNXT_ULP_CLASS_HID_2cee2] = 446, - [BNXT_ULP_CLASS_HID_24ec6] = 447, - [BNXT_ULP_CLASS_HID_2784e] = 448, - [BNXT_ULP_CLASS_HID_2ec0e] = 449, - [BNXT_ULP_CLASS_HID_2dd86] = 450, - [BNXT_ULP_CLASS_HID_25f22] = 451, - [BNXT_ULP_CLASS_HID_2112e] = 452, - [BNXT_ULP_CLASS_HID_2852e] = 453, - [BNXT_ULP_CLASS_HID_2b6a6] = 454, - [BNXT_ULP_CLASS_HID_26d86] = 455, - [BNXT_ULP_CLASS_HID_26002] = 456, - [BNXT_ULP_CLASS_HID_2eb82] = 457, - [BNXT_ULP_CLASS_HID_2c50a] = 458, - [BNXT_ULP_CLASS_HID_22f82] = 459, - [BNXT_ULP_CLASS_HID_2590a] = 460, - [BNXT_ULP_CLASS_HID_2ccca] = 461, - [BNXT_ULP_CLASS_HID_28706] = 462, - [BNXT_ULP_CLASS_HID_27e46] = 463, - [BNXT_ULP_CLASS_HID_26fce] = 464, - [BNXT_ULP_CLASS_HID_2d38e] = 465, - [BNXT_ULP_CLASS_HID_2d5ca] = 466, - [BNXT_ULP_CLASS_HID_21706] = 467, - [BNXT_ULP_CLASS_HID_2408e] = 468, - [BNXT_ULP_CLASS_HID_2b48e] = 469, - [BNXT_ULP_CLASS_HID_28e8a] = 470, - [BNXT_ULP_CLASS_HID_2660a] = 471, - [BNXT_ULP_CLASS_HID_25782] = 472, - [BNXT_ULP_CLASS_HID_2db02] = 473, - [BNXT_ULP_CLASS_HID_2dd8e] = 474, - [BNXT_ULP_CLASS_HID_25b9e] = 475, - [BNXT_ULP_CLASS_HID_21dda] = 476, - [BNXT_ULP_CLASS_HID_2819a] = 477, - [BNXT_ULP_CLASS_HID_2b31a] = 478, - [BNXT_ULP_CLASS_HID_26a3a] = 479, - [BNXT_ULP_CLASS_HID_26c7e] = 480, - [BNXT_ULP_CLASS_HID_2d03e] = 481, - [BNXT_ULP_CLASS_HID_2c1be] = 482, - [BNXT_ULP_CLASS_HID_2430a] = 483, - [BNXT_ULP_CLASS_HID_2058e] = 484, - [BNXT_ULP_CLASS_HID_2890e] = 485, - [BNXT_ULP_CLASS_HID_2ba8e] = 486, - [BNXT_ULP_CLASS_HID_251ae] = 487, - [BNXT_ULP_CLASS_HID_2542a] = 488, - [BNXT_ULP_CLASS_HID_2dfaa] = 489, - [BNXT_ULP_CLASS_HID_2c93a] = 490, - [BNXT_ULP_CLASS_HID_213ca] = 491, - [BNXT_ULP_CLASS_HID_24d5a] = 492, - [BNXT_ULP_CLASS_HID_2b11a] = 493, - [BNXT_ULP_CLASS_HID_28b4e] = 494, - [BNXT_ULP_CLASS_HID_2624e] = 495, - [BNXT_ULP_CLASS_HID_253de] = 496, - [BNXT_ULP_CLASS_HID_2c79e] = 497, - [BNXT_ULP_CLASS_HID_2d9da] = 498, - [BNXT_ULP_CLASS_HID_21b1e] = 499, - [BNXT_ULP_CLASS_HID_2350e] = 500, - [BNXT_ULP_CLASS_HID_2b88e] = 501, - [BNXT_ULP_CLASS_HID_2ea0e] = 502, - [BNXT_ULP_CLASS_HID_26a0a] = 503, - [BNXT_ULP_CLASS_HID_25b8a] = 504, - [BNXT_ULP_CLASS_HID_2cf0a] = 505, - [BNXT_ULP_CLASS_HID_2c18e] = 506, - [BNXT_ULP_CLASS_HID_2634e] = 507, - [BNXT_ULP_CLASS_HID_2258a] = 508, - [BNXT_ULP_CLASS_HID_2a94a] = 509, - [BNXT_ULP_CLASS_HID_2daca] = 510, - [BNXT_ULP_CLASS_HID_25aae] = 511, - [BNXT_ULP_CLASS_HID_2742e] = 512, - [BNXT_ULP_CLASS_HID_2ffee] = 513, - [BNXT_ULP_CLASS_HID_2e96e] = 514, - [BNXT_ULP_CLASS_HID_26b0a] = 515, - [BNXT_ULP_CLASS_HID_22d0e] = 516, - [BNXT_ULP_CLASS_HID_2910e] = 517, - [BNXT_ULP_CLASS_HID_2c28e] = 518, - [BNXT_ULP_CLASS_HID_2422a] = 519, - [BNXT_ULP_CLASS_HID_273aa] = 520, - [BNXT_ULP_CLASS_HID_2e7aa] = 521, - [BNXT_ULP_CLASS_HID_2d12a] = 522, - [BNXT_ULP_CLASS_HID_23b8a] = 523, - [BNXT_ULP_CLASS_HID_2550a] = 524, - [BNXT_ULP_CLASS_HID_2d8ca] = 525, - [BNXT_ULP_CLASS_HID_2930e] = 526, - [BNXT_ULP_CLASS_HID_24a0e] = 527, - [BNXT_ULP_CLASS_HID_24c4a] = 528, - [BNXT_ULP_CLASS_HID_2ef4e] = 529, - [BNXT_ULP_CLASS_HID_2e18a] = 530, - [BNXT_ULP_CLASS_HID_2230e] = 531, - [BNXT_ULP_CLASS_HID_25c8e] = 532, - [BNXT_ULP_CLASS_HID_2c08e] = 533, - [BNXT_ULP_CLASS_HID_29a8a] = 534, - [BNXT_ULP_CLASS_HID_2718a] = 535, - [BNXT_ULP_CLASS_HID_2630a] = 536, - [BNXT_ULP_CLASS_HID_2d70a] = 537, - [BNXT_ULP_CLASS_HID_2e90e] = 538, - [BNXT_ULP_CLASS_HID_24e91] = 539, - [BNXT_ULP_CLASS_HID_200d5] = 540, - [BNXT_ULP_CLASS_HID_2edd9] = 541, - [BNXT_ULP_CLASS_HID_2a61d] = 542, - [BNXT_ULP_CLASS_HID_25f7d] = 543, - [BNXT_ULP_CLASS_HID_251b1] = 544, - [BNXT_ULP_CLASS_HID_2c571] = 545, - [BNXT_ULP_CLASS_HID_2f4f9] = 546, - [BNXT_ULP_CLASS_HID_25641] = 547, - [BNXT_ULP_CLASS_HID_22885] = 548, - [BNXT_ULP_CLASS_HID_29c45] = 549, - [BNXT_ULP_CLASS_HID_2cfcd] = 550, - [BNXT_ULP_CLASS_HID_24fe9] = 551, - [BNXT_ULP_CLASS_HID_27961] = 552, - [BNXT_ULP_CLASS_HID_2ed21] = 553, - [BNXT_ULP_CLASS_HID_2dca9] = 554, - [BNXT_ULP_CLASS_HID_25ab1] = 555, - [BNXT_ULP_CLASS_HID_21cf5] = 556, - [BNXT_ULP_CLASS_HID_280b5] = 557, - [BNXT_ULP_CLASS_HID_2b235] = 558, - [BNXT_ULP_CLASS_HID_26b15] = 559, - [BNXT_ULP_CLASS_HID_26d51] = 560, - [BNXT_ULP_CLASS_HID_2d111] = 561, - [BNXT_ULP_CLASS_HID_2c091] = 562, - [BNXT_ULP_CLASS_HID_26261] = 563, - [BNXT_ULP_CLASS_HID_224a5] = 564, - [BNXT_ULP_CLASS_HID_2a865] = 565, - [BNXT_ULP_CLASS_HID_2dbe5] = 566, - [BNXT_ULP_CLASS_HID_25b81] = 567, - [BNXT_ULP_CLASS_HID_27501] = 568, - [BNXT_ULP_CLASS_HID_2fec1] = 569, - [BNXT_ULP_CLASS_HID_2e841] = 570, - [BNXT_ULP_CLASS_HID_24085] = 571, - [BNXT_ULP_CLASS_HID_21ac5] = 572, - [BNXT_ULP_CLASS_HID_28e85] = 573, - [BNXT_ULP_CLASS_HID_2b80d] = 574, - [BNXT_ULP_CLASS_HID_2516d] = 575, - [BNXT_ULP_CLASS_HID_26ba5] = 576, - [BNXT_ULP_CLASS_HID_2df65] = 577, - [BNXT_ULP_CLASS_HID_2ceed] = 578, - [BNXT_ULP_CLASS_HID_26845] = 579, - [BNXT_ULP_CLASS_HID_22285] = 580, - [BNXT_ULP_CLASS_HID_29645] = 581, - [BNXT_ULP_CLASS_HID_2c1cd] = 582, - [BNXT_ULP_CLASS_HID_2418d] = 583, - [BNXT_ULP_CLASS_HID_27365] = 584, - [BNXT_ULP_CLASS_HID_2e725] = 585, - [BNXT_ULP_CLASS_HID_2d6ad] = 586, - [BNXT_ULP_CLASS_HID_25ca5] = 587, - [BNXT_ULP_CLASS_HID_216e5] = 588, - [BNXT_ULP_CLASS_HID_29aa5] = 589, - [BNXT_ULP_CLASS_HID_2b425] = 590, - [BNXT_ULP_CLASS_HID_26d05] = 591, - [BNXT_ULP_CLASS_HID_26745] = 592, - [BNXT_ULP_CLASS_HID_2eb05] = 593, - [BNXT_ULP_CLASS_HID_2da85] = 594, - [BNXT_ULP_CLASS_HID_20cc5] = 595, - [BNXT_ULP_CLASS_HID_23ea5] = 596, - [BNXT_ULP_CLASS_HID_2a265] = 597, - [BNXT_ULP_CLASS_HID_2dde5] = 598, - [BNXT_ULP_CLASS_HID_25da5] = 599, - [BNXT_ULP_CLASS_HID_24f05] = 600, - [BNXT_ULP_CLASS_HID_2f0c5] = 601, - [BNXT_ULP_CLASS_HID_2e245] = 602, - [BNXT_ULP_CLASS_HID_24d8b] = 603, - [BNXT_ULP_CLASS_HID_207cf] = 604, - [BNXT_ULP_CLASS_HID_28b8f] = 605, - [BNXT_ULP_CLASS_HID_2a517] = 606, - [BNXT_ULP_CLASS_HID_25277] = 607, - [BNXT_ULP_CLASS_HID_254ab] = 608, - [BNXT_ULP_CLASS_HID_2d86b] = 609, - [BNXT_ULP_CLASS_HID_2cbf3] = 610, - [BNXT_ULP_CLASS_HID_2554b] = 611, - [BNXT_ULP_CLASS_HID_22f8f] = 612, - [BNXT_ULP_CLASS_HID_2934f] = 613, - [BNXT_ULP_CLASS_HID_2c2c7] = 614, - [BNXT_ULP_CLASS_HID_242e3] = 615, - [BNXT_ULP_CLASS_HID_27c6b] = 616, - [BNXT_ULP_CLASS_HID_2e02b] = 617, - [BNXT_ULP_CLASS_HID_2d3a3] = 618, - [BNXT_ULP_CLASS_HID_259a3] = 619, - [BNXT_ULP_CLASS_HID_213e7] = 620, - [BNXT_ULP_CLASS_HID_287a7] = 621, - [BNXT_ULP_CLASS_HID_2b137] = 622, - [BNXT_ULP_CLASS_HID_26e17] = 623, - [BNXT_ULP_CLASS_HID_26043] = 624, - [BNXT_ULP_CLASS_HID_2d403] = 625, - [BNXT_ULP_CLASS_HID_2c793] = 626, - [BNXT_ULP_CLASS_HID_20827] = 627, - [BNXT_ULP_CLASS_HID_23ba7] = 628, - [BNXT_ULP_CLASS_HID_2af67] = 629, - [BNXT_ULP_CLASS_HID_2dee7] = 630, - [BNXT_ULP_CLASS_HID_25e83] = 631, - [BNXT_ULP_CLASS_HID_24803] = 632, - [BNXT_ULP_CLASS_HID_2fdc3] = 633, - [BNXT_ULP_CLASS_HID_2ef43] = 634, - [BNXT_ULP_CLASS_HID_247bf] = 635, - [BNXT_ULP_CLASS_HID_219ff] = 636, - [BNXT_ULP_CLASS_HID_28dbf] = 637, - [BNXT_ULP_CLASS_HID_2bf07] = 638, - [BNXT_ULP_CLASS_HID_25467] = 639, - [BNXT_ULP_CLASS_HID_26e5f] = 640, - [BNXT_ULP_CLASS_HID_2d21f] = 641, - [BNXT_ULP_CLASS_HID_2cde7] = 642, - [BNXT_ULP_CLASS_HID_26f6f] = 643, - [BNXT_ULP_CLASS_HID_221af] = 644, - [BNXT_ULP_CLASS_HID_2956f] = 645, - [BNXT_ULP_CLASS_HID_2c4c7] = 646, - [BNXT_ULP_CLASS_HID_24487] = 647, - [BNXT_ULP_CLASS_HID_2760f] = 648, - [BNXT_ULP_CLASS_HID_2fbcf] = 649, - [BNXT_ULP_CLASS_HID_2d5a7] = 650, - [BNXT_ULP_CLASS_HID_25357] = 651, - [BNXT_ULP_CLASS_HID_21597] = 652, - [BNXT_ULP_CLASS_HID_29957] = 653, - [BNXT_ULP_CLASS_HID_2cb27] = 654, - [BNXT_ULP_CLASS_HID_248f7] = 655, - [BNXT_ULP_CLASS_HID_27a77] = 656, - [BNXT_ULP_CLASS_HID_2ee37] = 657, - [BNXT_ULP_CLASS_HID_2d987] = 658, - [BNXT_ULP_CLASS_HID_203c7] = 659, - [BNXT_ULP_CLASS_HID_23d47] = 660, - [BNXT_ULP_CLASS_HID_2a107] = 661, - [BNXT_ULP_CLASS_HID_2d0e7] = 662, - [BNXT_ULP_CLASS_HID_250a7] = 663, - [BNXT_ULP_CLASS_HID_24227] = 664, - [BNXT_ULP_CLASS_HID_2f7e7] = 665, - [BNXT_ULP_CLASS_HID_2c827] = 666, - [BNXT_ULP_CLASS_HID_25422] = 667, - [BNXT_ULP_CLASS_HID_21a66] = 668, - [BNXT_ULP_CLASS_HID_2f76a] = 669, - [BNXT_ULP_CLASS_HID_2bcae] = 670, - [BNXT_ULP_CLASS_HID_245ce] = 671, - [BNXT_ULP_CLASS_HID_24b02] = 672, - [BNXT_ULP_CLASS_HID_2dfc2] = 673, - [BNXT_ULP_CLASS_HID_2ee4a] = 674, - [BNXT_ULP_CLASS_HID_22cbe] = 675, - [BNXT_ULP_CLASS_HID_21232] = 676, - [BNXT_ULP_CLASS_HID_2cf26] = 677, - [BNXT_ULP_CLASS_HID_2b53a] = 678, - [BNXT_ULP_CLASS_HID_25d9a] = 679, - [BNXT_ULP_CLASS_HID_2439e] = 680, - [BNXT_ULP_CLASS_HID_2d79e] = 681, - [BNXT_ULP_CLASS_HID_2e606] = 682, - [BNXT_ULP_CLASS_HID_21c5e] = 683, - [BNXT_ULP_CLASS_HID_22ac6] = 684, - [BNXT_ULP_CLASS_HID_2be86] = 685, - [BNXT_ULP_CLASS_HID_2cd0e] = 686, - [BNXT_ULP_CLASS_HID_24d1a] = 687, - [BNXT_ULP_CLASS_HID_25b82] = 688, - [BNXT_ULP_CLASS_HID_2d042] = 689, - [BNXT_ULP_CLASS_HID_2d586] = 690, - [BNXT_ULP_CLASS_HID_2140a] = 691, - [BNXT_ULP_CLASS_HID_22292] = 692, - [BNXT_ULP_CLASS_HID_2b712] = 693, - [BNXT_ULP_CLASS_HID_2c59a] = 694, - [BNXT_ULP_CLASS_HID_24596] = 695, - [BNXT_ULP_CLASS_HID_2541e] = 696, - [BNXT_ULP_CLASS_HID_2e81e] = 697, - [BNXT_ULP_CLASS_HID_2f686] = 698, - [BNXT_ULP_CLASS_HID_24cf2] = 699, - [BNXT_ULP_CLASS_HID_23236] = 700, - [BNXT_ULP_CLASS_HID_286f6] = 701, - [BNXT_ULP_CLASS_HID_2d57e] = 702, - [BNXT_ULP_CLASS_HID_2555a] = 703, - [BNXT_ULP_CLASS_HID_263d2] = 704, - [BNXT_ULP_CLASS_HID_2f792] = 705, - [BNXT_ULP_CLASS_HID_2c61a] = 706, - [BNXT_ULP_CLASS_HID_244be] = 707, - [BNXT_ULP_CLASS_HID_20ab2] = 708, - [BNXT_ULP_CLASS_HID_29eb2] = 709, - [BNXT_ULP_CLASS_HID_2ad3a] = 710, - [BNXT_ULP_CLASS_HID_2761a] = 711, - [BNXT_ULP_CLASS_HID_27b9e] = 712, - [BNXT_ULP_CLASS_HID_2f01e] = 713, - [BNXT_ULP_CLASS_HID_2de96] = 714, - [BNXT_ULP_CLASS_HID_2341e] = 715, - [BNXT_ULP_CLASS_HID_24296] = 716, - [BNXT_ULP_CLASS_HID_2d756] = 717, - [BNXT_ULP_CLASS_HID_29c9a] = 718, - [BNXT_ULP_CLASS_HID_265da] = 719, - [BNXT_ULP_CLASS_HID_27452] = 720, - [BNXT_ULP_CLASS_HID_2c812] = 721, - [BNXT_ULP_CLASS_HID_2ce56] = 722, - [BNXT_ULP_CLASS_HID_20c9a] = 723, - [BNXT_ULP_CLASS_HID_25b12] = 724, - [BNXT_ULP_CLASS_HID_2af12] = 725, - [BNXT_ULP_CLASS_HID_29516] = 726, - [BNXT_ULP_CLASS_HID_27d96] = 727, - [BNXT_ULP_CLASS_HID_24c1e] = 728, - [BNXT_ULP_CLASS_HID_2c09e] = 729, - [BNXT_ULP_CLASS_HID_2c612] = 730, - [BNXT_ULP_CLASS_HID_24002] = 731, - [BNXT_ULP_CLASS_HID_20646] = 732, - [BNXT_ULP_CLASS_HID_29a06] = 733, - [BNXT_ULP_CLASS_HID_2a886] = 734, - [BNXT_ULP_CLASS_HID_271a6] = 735, - [BNXT_ULP_CLASS_HID_277e2] = 736, - [BNXT_ULP_CLASS_HID_2cba2] = 737, - [BNXT_ULP_CLASS_HID_2da22] = 738, - [BNXT_ULP_CLASS_HID_25896] = 739, - [BNXT_ULP_CLASS_HID_21e12] = 740, - [BNXT_ULP_CLASS_HID_29292] = 741, - [BNXT_ULP_CLASS_HID_2a112] = 742, - [BNXT_ULP_CLASS_HID_24a32] = 743, - [BNXT_ULP_CLASS_HID_24fb6] = 744, - [BNXT_ULP_CLASS_HID_2c436] = 745, - [BNXT_ULP_CLASS_HID_2d2a6] = 746, - [BNXT_ULP_CLASS_HID_20856] = 747, - [BNXT_ULP_CLASS_HID_256c6] = 748, - [BNXT_ULP_CLASS_HID_2aa86] = 749, - [BNXT_ULP_CLASS_HID_290d2] = 750, - [BNXT_ULP_CLASS_HID_279d2] = 751, - [BNXT_ULP_CLASS_HID_24842] = 752, - [BNXT_ULP_CLASS_HID_2dc02] = 753, - [BNXT_ULP_CLASS_HID_2c246] = 754, - [BNXT_ULP_CLASS_HID_20082] = 755, - [BNXT_ULP_CLASS_HID_22e92] = 756, - [BNXT_ULP_CLASS_HID_2a312] = 757, - [BNXT_ULP_CLASS_HID_2f192] = 758, - [BNXT_ULP_CLASS_HID_27196] = 759, - [BNXT_ULP_CLASS_HID_24016] = 760, - [BNXT_ULP_CLASS_HID_2d496] = 761, - [BNXT_ULP_CLASS_HID_2da12] = 762, - [BNXT_ULP_CLASS_HID_278d2] = 763, - [BNXT_ULP_CLASS_HID_23e16] = 764, - [BNXT_ULP_CLASS_HID_2b2d6] = 765, - [BNXT_ULP_CLASS_HID_2c156] = 766, - [BNXT_ULP_CLASS_HID_24132] = 767, - [BNXT_ULP_CLASS_HID_26fb2] = 768, - [BNXT_ULP_CLASS_HID_2e472] = 769, - [BNXT_ULP_CLASS_HID_2f2f2] = 770, - [BNXT_ULP_CLASS_HID_27096] = 771, - [BNXT_ULP_CLASS_HID_23692] = 772, - [BNXT_ULP_CLASS_HID_28a92] = 773, - [BNXT_ULP_CLASS_HID_2d912] = 774, - [BNXT_ULP_CLASS_HID_259b6] = 775, - [BNXT_ULP_CLASS_HID_26836] = 776, - [BNXT_ULP_CLASS_HID_2fc36] = 777, - [BNXT_ULP_CLASS_HID_2cab6] = 778, - [BNXT_ULP_CLASS_HID_22016] = 779, - [BNXT_ULP_CLASS_HID_24e96] = 780, - [BNXT_ULP_CLASS_HID_2c356] = 781, - [BNXT_ULP_CLASS_HID_28892] = 782, - [BNXT_ULP_CLASS_HID_25192] = 783, - [BNXT_ULP_CLASS_HID_257d6] = 784, - [BNXT_ULP_CLASS_HID_2f4d2] = 785, - [BNXT_ULP_CLASS_HID_2fa16] = 786, - [BNXT_ULP_CLASS_HID_23892] = 787, - [BNXT_ULP_CLASS_HID_24712] = 788, - [BNXT_ULP_CLASS_HID_2db12] = 789, - [BNXT_ULP_CLASS_HID_28116] = 790, - [BNXT_ULP_CLASS_HID_26a16] = 791, - [BNXT_ULP_CLASS_HID_27896] = 792, - [BNXT_ULP_CLASS_HID_2cc96] = 793, - [BNXT_ULP_CLASS_HID_2f292] = 794, - [BNXT_ULP_CLASS_HID_24b05] = 795, - [BNXT_ULP_CLASS_HID_20541] = 796, - [BNXT_ULP_CLASS_HID_2e84d] = 797, - [BNXT_ULP_CLASS_HID_2a389] = 798, - [BNXT_ULP_CLASS_HID_25ae9] = 799, - [BNXT_ULP_CLASS_HID_25425] = 800, - [BNXT_ULP_CLASS_HID_2c0e5] = 801, - [BNXT_ULP_CLASS_HID_2f16d] = 802, - [BNXT_ULP_CLASS_HID_253d5] = 803, - [BNXT_ULP_CLASS_HID_22d11] = 804, - [BNXT_ULP_CLASS_HID_299d1] = 805, - [BNXT_ULP_CLASS_HID_2ca59] = 806, - [BNXT_ULP_CLASS_HID_24a7d] = 807, - [BNXT_ULP_CLASS_HID_27cf5] = 808, - [BNXT_ULP_CLASS_HID_2e8b5] = 809, - [BNXT_ULP_CLASS_HID_2d93d] = 810, - [BNXT_ULP_CLASS_HID_25f25] = 811, - [BNXT_ULP_CLASS_HID_21961] = 812, - [BNXT_ULP_CLASS_HID_28521] = 813, - [BNXT_ULP_CLASS_HID_2b7a1] = 814, - [BNXT_ULP_CLASS_HID_26e81] = 815, - [BNXT_ULP_CLASS_HID_268c5] = 816, - [BNXT_ULP_CLASS_HID_2d485] = 817, - [BNXT_ULP_CLASS_HID_2c505] = 818, - [BNXT_ULP_CLASS_HID_267f5] = 819, - [BNXT_ULP_CLASS_HID_22131] = 820, - [BNXT_ULP_CLASS_HID_2adf1] = 821, - [BNXT_ULP_CLASS_HID_2de71] = 822, - [BNXT_ULP_CLASS_HID_25e15] = 823, - [BNXT_ULP_CLASS_HID_27095] = 824, - [BNXT_ULP_CLASS_HID_2fb55] = 825, - [BNXT_ULP_CLASS_HID_2edd5] = 826, - [BNXT_ULP_CLASS_HID_24511] = 827, - [BNXT_ULP_CLASS_HID_21f51] = 828, - [BNXT_ULP_CLASS_HID_28b11] = 829, - [BNXT_ULP_CLASS_HID_2bd99] = 830, - [BNXT_ULP_CLASS_HID_254f9] = 831, - [BNXT_ULP_CLASS_HID_26e31] = 832, - [BNXT_ULP_CLASS_HID_2daf1] = 833, - [BNXT_ULP_CLASS_HID_2cb79] = 834, - [BNXT_ULP_CLASS_HID_26dd1] = 835, - [BNXT_ULP_CLASS_HID_22711] = 836, - [BNXT_ULP_CLASS_HID_293d1] = 837, - [BNXT_ULP_CLASS_HID_2c459] = 838, - [BNXT_ULP_CLASS_HID_24419] = 839, - [BNXT_ULP_CLASS_HID_276f1] = 840, - [BNXT_ULP_CLASS_HID_2e2b1] = 841, - [BNXT_ULP_CLASS_HID_2d339] = 842, - [BNXT_ULP_CLASS_HID_25931] = 843, - [BNXT_ULP_CLASS_HID_21371] = 844, - [BNXT_ULP_CLASS_HID_29f31] = 845, - [BNXT_ULP_CLASS_HID_2b1b1] = 846, - [BNXT_ULP_CLASS_HID_26891] = 847, - [BNXT_ULP_CLASS_HID_262d1] = 848, - [BNXT_ULP_CLASS_HID_2ee91] = 849, - [BNXT_ULP_CLASS_HID_2df11] = 850, - [BNXT_ULP_CLASS_HID_20951] = 851, - [BNXT_ULP_CLASS_HID_23b31] = 852, - [BNXT_ULP_CLASS_HID_2a7f1] = 853, - [BNXT_ULP_CLASS_HID_2d871] = 854, - [BNXT_ULP_CLASS_HID_25831] = 855, - [BNXT_ULP_CLASS_HID_24a91] = 856, - [BNXT_ULP_CLASS_HID_2f551] = 857, - [BNXT_ULP_CLASS_HID_2e7d1] = 858, - [BNXT_ULP_CLASS_HID_2481f] = 859, - [BNXT_ULP_CLASS_HID_2025b] = 860, - [BNXT_ULP_CLASS_HID_28e1b] = 861, - [BNXT_ULP_CLASS_HID_2a083] = 862, - [BNXT_ULP_CLASS_HID_257e3] = 863, - [BNXT_ULP_CLASS_HID_2513f] = 864, - [BNXT_ULP_CLASS_HID_2ddff] = 865, - [BNXT_ULP_CLASS_HID_2ce67] = 866, - [BNXT_ULP_CLASS_HID_250df] = 867, - [BNXT_ULP_CLASS_HID_22a1b] = 868, - [BNXT_ULP_CLASS_HID_296db] = 869, - [BNXT_ULP_CLASS_HID_2c753] = 870, - [BNXT_ULP_CLASS_HID_24777] = 871, - [BNXT_ULP_CLASS_HID_279ff] = 872, - [BNXT_ULP_CLASS_HID_2e5bf] = 873, - [BNXT_ULP_CLASS_HID_2d637] = 874, - [BNXT_ULP_CLASS_HID_25c37] = 875, - [BNXT_ULP_CLASS_HID_21673] = 876, - [BNXT_ULP_CLASS_HID_28233] = 877, - [BNXT_ULP_CLASS_HID_2b4a3] = 878, - [BNXT_ULP_CLASS_HID_26b83] = 879, - [BNXT_ULP_CLASS_HID_265d7] = 880, - [BNXT_ULP_CLASS_HID_2d197] = 881, - [BNXT_ULP_CLASS_HID_2c207] = 882, - [BNXT_ULP_CLASS_HID_20db3] = 883, - [BNXT_ULP_CLASS_HID_23e33] = 884, - [BNXT_ULP_CLASS_HID_2aaf3] = 885, - [BNXT_ULP_CLASS_HID_2db73] = 886, - [BNXT_ULP_CLASS_HID_25b17] = 887, - [BNXT_ULP_CLASS_HID_24d97] = 888, - [BNXT_ULP_CLASS_HID_2f857] = 889, - [BNXT_ULP_CLASS_HID_2ead7] = 890, - [BNXT_ULP_CLASS_HID_2422b] = 891, - [BNXT_ULP_CLASS_HID_21c6b] = 892, - [BNXT_ULP_CLASS_HID_2882b] = 893, - [BNXT_ULP_CLASS_HID_2ba93] = 894, - [BNXT_ULP_CLASS_HID_251f3] = 895, - [BNXT_ULP_CLASS_HID_26bcb] = 896, - [BNXT_ULP_CLASS_HID_2d78b] = 897, - [BNXT_ULP_CLASS_HID_2c873] = 898, - [BNXT_ULP_CLASS_HID_26afb] = 899, - [BNXT_ULP_CLASS_HID_2243b] = 900, - [BNXT_ULP_CLASS_HID_290fb] = 901, - [BNXT_ULP_CLASS_HID_2c153] = 902, - [BNXT_ULP_CLASS_HID_24113] = 903, - [BNXT_ULP_CLASS_HID_2739b] = 904, - [BNXT_ULP_CLASS_HID_2fe5b] = 905, - [BNXT_ULP_CLASS_HID_2d033] = 906, - [BNXT_ULP_CLASS_HID_256c3] = 907, - [BNXT_ULP_CLASS_HID_21003] = 908, - [BNXT_ULP_CLASS_HID_29cc3] = 909, - [BNXT_ULP_CLASS_HID_2ceb3] = 910, - [BNXT_ULP_CLASS_HID_24d63] = 911, - [BNXT_ULP_CLASS_HID_27fe3] = 912, - [BNXT_ULP_CLASS_HID_2eba3] = 913, - [BNXT_ULP_CLASS_HID_2dc13] = 914, - [BNXT_ULP_CLASS_HID_20653] = 915, - [BNXT_ULP_CLASS_HID_238d3] = 916, - [BNXT_ULP_CLASS_HID_2a493] = 917, - [BNXT_ULP_CLASS_HID_2d573] = 918, - [BNXT_ULP_CLASS_HID_25533] = 919, - [BNXT_ULP_CLASS_HID_247b3] = 920, - [BNXT_ULP_CLASS_HID_2f273] = 921, - [BNXT_ULP_CLASS_HID_2cdb3] = 922, - [BNXT_ULP_CLASS_HID_25c7d] = 923, - [BNXT_ULP_CLASS_HID_21239] = 924, - [BNXT_ULP_CLASS_HID_2ff35] = 925, - [BNXT_ULP_CLASS_HID_2b4f1] = 926, - [BNXT_ULP_CLASS_HID_24d91] = 927, - [BNXT_ULP_CLASS_HID_2435d] = 928, - [BNXT_ULP_CLASS_HID_2d79d] = 929, - [BNXT_ULP_CLASS_HID_2e615] = 930, - [BNXT_ULP_CLASS_HID_244ad] = 931, - [BNXT_ULP_CLASS_HID_23a69] = 932, - [BNXT_ULP_CLASS_HID_28ea9] = 933, - [BNXT_ULP_CLASS_HID_2dd21] = 934, - [BNXT_ULP_CLASS_HID_25d05] = 935, - [BNXT_ULP_CLASS_HID_26b8d] = 936, - [BNXT_ULP_CLASS_HID_2ffcd] = 937, - [BNXT_ULP_CLASS_HID_2ce45] = 938, - [BNXT_ULP_CLASS_HID_2485d] = 939, - [BNXT_ULP_CLASS_HID_20e19] = 940, - [BNXT_ULP_CLASS_HID_29259] = 941, - [BNXT_ULP_CLASS_HID_2a0d9] = 942, - [BNXT_ULP_CLASS_HID_279f9] = 943, - [BNXT_ULP_CLASS_HID_27fbd] = 944, - [BNXT_ULP_CLASS_HID_2c3fd] = 945, - [BNXT_ULP_CLASS_HID_2d27d] = 946, - [BNXT_ULP_CLASS_HID_2708d] = 947, - [BNXT_ULP_CLASS_HID_23649] = 948, - [BNXT_ULP_CLASS_HID_2ba89] = 949, - [BNXT_ULP_CLASS_HID_2c909] = 950, - [BNXT_ULP_CLASS_HID_2496d] = 951, - [BNXT_ULP_CLASS_HID_267ed] = 952, - [BNXT_ULP_CLASS_HID_2ec2d] = 953, - [BNXT_ULP_CLASS_HID_2faad] = 954, - [BNXT_ULP_CLASS_HID_34c6] = 955, - [BNXT_ULP_CLASS_HID_0c22] = 956, - [BNXT_ULP_CLASS_HID_1cbe] = 957, - [BNXT_ULP_CLASS_HID_179a] = 958, - [BNXT_ULP_CLASS_HID_59be] = 959, - [BNXT_ULP_CLASS_HID_515a] = 960, - [BNXT_ULP_CLASS_HID_1c72] = 961, - [BNXT_ULP_CLASS_HID_171e] = 962, - [BNXT_ULP_CLASS_HID_19c8] = 963, - [BNXT_ULP_CLASS_HID_112c] = 964, - [BNXT_ULP_CLASS_HID_4d68] = 965, - [BNXT_ULP_CLASS_HID_444c] = 966, - [BNXT_ULP_CLASS_HID_0e8c] = 967, - [BNXT_ULP_CLASS_HID_09e0] = 968, - [BNXT_ULP_CLASS_HID_1af0] = 969, - [BNXT_ULP_CLASS_HID_15d4] = 970, - [BNXT_ULP_CLASS_HID_1dd0] = 971, - [BNXT_ULP_CLASS_HID_14f4] = 972, - [BNXT_ULP_CLASS_HID_70b0] = 973, - [BNXT_ULP_CLASS_HID_4854] = 974, - [BNXT_ULP_CLASS_HID_3dd4] = 975, - [BNXT_ULP_CLASS_HID_34f8] = 976, - [BNXT_ULP_CLASS_HID_09e8] = 977, - [BNXT_ULP_CLASS_HID_008c] = 978, - [BNXT_ULP_CLASS_HID_34e6] = 979, - [BNXT_ULP_CLASS_HID_0c02] = 980, - [BNXT_ULP_CLASS_HID_1c9e] = 981, - [BNXT_ULP_CLASS_HID_17ba] = 982, - [BNXT_ULP_CLASS_HID_429e] = 983, - [BNXT_ULP_CLASS_HID_5dba] = 984, - [BNXT_ULP_CLASS_HID_2a16] = 985, - [BNXT_ULP_CLASS_HID_2532] = 986, - [BNXT_ULP_CLASS_HID_2da2] = 987, - [BNXT_ULP_CLASS_HID_24fe] = 988, - [BNXT_ULP_CLASS_HID_355a] = 989, - [BNXT_ULP_CLASS_HID_0c76] = 990, - [BNXT_ULP_CLASS_HID_13e6] = 991, - [BNXT_ULP_CLASS_HID_7276] = 992, - [BNXT_ULP_CLASS_HID_42d2] = 993, - [BNXT_ULP_CLASS_HID_5dee] = 994, - [BNXT_ULP_CLASS_HID_59de] = 995, - [BNXT_ULP_CLASS_HID_513a] = 996, - [BNXT_ULP_CLASS_HID_1c12] = 997, - [BNXT_ULP_CLASS_HID_177e] = 998, - [BNXT_ULP_CLASS_HID_0e92] = 999, - [BNXT_ULP_CLASS_HID_09fe] = 1000, - [BNXT_ULP_CLASS_HID_5c1a] = 1001, - [BNXT_ULP_CLASS_HID_5746] = 1002, - [BNXT_ULP_CLASS_HID_79da] = 1003, - [BNXT_ULP_CLASS_HID_7106] = 1004, - [BNXT_ULP_CLASS_HID_3c1e] = 1005, - [BNXT_ULP_CLASS_HID_377a] = 1006, - [BNXT_ULP_CLASS_HID_2e9e] = 1007, - [BNXT_ULP_CLASS_HID_29fa] = 1008, - [BNXT_ULP_CLASS_HID_14d2] = 1009, - [BNXT_ULP_CLASS_HID_7742] = 1010, - [BNXT_ULP_CLASS_HID_3706] = 1011, - [BNXT_ULP_CLASS_HID_0fe2] = 1012, - [BNXT_ULP_CLASS_HID_1f7e] = 1013, - [BNXT_ULP_CLASS_HID_145a] = 1014, - [BNXT_ULP_CLASS_HID_417e] = 1015, - [BNXT_ULP_CLASS_HID_5e5a] = 1016, - [BNXT_ULP_CLASS_HID_29f6] = 1017, - [BNXT_ULP_CLASS_HID_26d2] = 1018, - [BNXT_ULP_CLASS_HID_2e42] = 1019, - [BNXT_ULP_CLASS_HID_271e] = 1020, - [BNXT_ULP_CLASS_HID_36ba] = 1021, - [BNXT_ULP_CLASS_HID_0f96] = 1022, - [BNXT_ULP_CLASS_HID_1006] = 1023, - [BNXT_ULP_CLASS_HID_7196] = 1024, - [BNXT_ULP_CLASS_HID_4132] = 1025, - [BNXT_ULP_CLASS_HID_5e0e] = 1026, - [BNXT_ULP_CLASS_HID_59fe] = 1027, - [BNXT_ULP_CLASS_HID_511a] = 1028, - [BNXT_ULP_CLASS_HID_1c32] = 1029, - [BNXT_ULP_CLASS_HID_175e] = 1030, - [BNXT_ULP_CLASS_HID_0eb2] = 1031, - [BNXT_ULP_CLASS_HID_09de] = 1032, - [BNXT_ULP_CLASS_HID_5c3a] = 1033, - [BNXT_ULP_CLASS_HID_5766] = 1034, - [BNXT_ULP_CLASS_HID_79fa] = 1035, - [BNXT_ULP_CLASS_HID_7126] = 1036, - [BNXT_ULP_CLASS_HID_3c3e] = 1037, - [BNXT_ULP_CLASS_HID_375a] = 1038, - [BNXT_ULP_CLASS_HID_2ebe] = 1039, - [BNXT_ULP_CLASS_HID_29da] = 1040, - [BNXT_ULP_CLASS_HID_14f2] = 1041, - [BNXT_ULP_CLASS_HID_7762] = 1042, - [BNXT_ULP_CLASS_HID_19e8] = 1043, - [BNXT_ULP_CLASS_HID_110c] = 1044, - [BNXT_ULP_CLASS_HID_4d48] = 1045, - [BNXT_ULP_CLASS_HID_446c] = 1046, - [BNXT_ULP_CLASS_HID_0eac] = 1047, - [BNXT_ULP_CLASS_HID_09c0] = 1048, - [BNXT_ULP_CLASS_HID_1ad0] = 1049, - [BNXT_ULP_CLASS_HID_15f4] = 1050, - [BNXT_ULP_CLASS_HID_39ec] = 1051, - [BNXT_ULP_CLASS_HID_3100] = 1052, - [BNXT_ULP_CLASS_HID_0210] = 1053, - [BNXT_ULP_CLASS_HID_1d34] = 1054, - [BNXT_ULP_CLASS_HID_2ea0] = 1055, - [BNXT_ULP_CLASS_HID_29c4] = 1056, - [BNXT_ULP_CLASS_HID_3ad4] = 1057, - [BNXT_ULP_CLASS_HID_35e8] = 1058, - [BNXT_ULP_CLASS_HID_5d80] = 1059, - [BNXT_ULP_CLASS_HID_54a4] = 1060, - [BNXT_ULP_CLASS_HID_29b4] = 1061, - [BNXT_ULP_CLASS_HID_20c8] = 1062, - [BNXT_ULP_CLASS_HID_7244] = 1063, - [BNXT_ULP_CLASS_HID_4d98] = 1064, - [BNXT_ULP_CLASS_HID_5e68] = 1065, - [BNXT_ULP_CLASS_HID_598c] = 1066, - [BNXT_ULP_CLASS_HID_1248] = 1067, - [BNXT_ULP_CLASS_HID_74d8] = 1068, - [BNXT_ULP_CLASS_HID_49a8] = 1069, - [BNXT_ULP_CLASS_HID_40cc] = 1070, - [BNXT_ULP_CLASS_HID_0b0c] = 1071, - [BNXT_ULP_CLASS_HID_0220] = 1072, - [BNXT_ULP_CLASS_HID_1730] = 1073, - [BNXT_ULP_CLASS_HID_7980] = 1074, - [BNXT_ULP_CLASS_HID_1db0] = 1075, - [BNXT_ULP_CLASS_HID_1494] = 1076, - [BNXT_ULP_CLASS_HID_70d0] = 1077, - [BNXT_ULP_CLASS_HID_4834] = 1078, - [BNXT_ULP_CLASS_HID_3db4] = 1079, - [BNXT_ULP_CLASS_HID_3498] = 1080, - [BNXT_ULP_CLASS_HID_0988] = 1081, - [BNXT_ULP_CLASS_HID_00ec] = 1082, - [BNXT_ULP_CLASS_HID_23f44] = 1083, - [BNXT_ULP_CLASS_HID_236a8] = 1084, - [BNXT_ULP_CLASS_HID_20b58] = 1085, - [BNXT_ULP_CLASS_HID_202bc] = 1086, - [BNXT_ULP_CLASS_HID_25f48] = 1087, - [BNXT_ULP_CLASS_HID_256ac] = 1088, - [BNXT_ULP_CLASS_HID_22b5c] = 1089, - [BNXT_ULP_CLASS_HID_22280] = 1090, - [BNXT_ULP_CLASS_HID_14000] = 1091, - [BNXT_ULP_CLASS_HID_15b64] = 1092, - [BNXT_ULP_CLASS_HID_12c14] = 1093, - [BNXT_ULP_CLASS_HID_12778] = 1094, - [BNXT_ULP_CLASS_HID_118f8] = 1095, - [BNXT_ULP_CLASS_HID_113dc] = 1096, - [BNXT_ULP_CLASS_HID_14c18] = 1097, - [BNXT_ULP_CLASS_HID_1477c] = 1098, - [BNXT_ULP_CLASS_HID_31a88] = 1099, - [BNXT_ULP_CLASS_HID_315ec] = 1100, - [BNXT_ULP_CLASS_HID_34e28] = 1101, - [BNXT_ULP_CLASS_HID_3490c] = 1102, - [BNXT_ULP_CLASS_HID_33a8c] = 1103, - [BNXT_ULP_CLASS_HID_335f0] = 1104, - [BNXT_ULP_CLASS_HID_306e0] = 1105, - [BNXT_ULP_CLASS_HID_301c4] = 1106, - [BNXT_ULP_CLASS_HID_1a08] = 1107, - [BNXT_ULP_CLASS_HID_12ec] = 1108, - [BNXT_ULP_CLASS_HID_4ea8] = 1109, - [BNXT_ULP_CLASS_HID_478c] = 1110, - [BNXT_ULP_CLASS_HID_0d4c] = 1111, - [BNXT_ULP_CLASS_HID_0a20] = 1112, - [BNXT_ULP_CLASS_HID_1930] = 1113, - [BNXT_ULP_CLASS_HID_1614] = 1114, - [BNXT_ULP_CLASS_HID_3a0c] = 1115, - [BNXT_ULP_CLASS_HID_32e0] = 1116, - [BNXT_ULP_CLASS_HID_01f0] = 1117, - [BNXT_ULP_CLASS_HID_1ed4] = 1118, - [BNXT_ULP_CLASS_HID_2d40] = 1119, - [BNXT_ULP_CLASS_HID_2a24] = 1120, - [BNXT_ULP_CLASS_HID_3934] = 1121, - [BNXT_ULP_CLASS_HID_3608] = 1122, - [BNXT_ULP_CLASS_HID_5e60] = 1123, - [BNXT_ULP_CLASS_HID_5744] = 1124, - [BNXT_ULP_CLASS_HID_2a54] = 1125, - [BNXT_ULP_CLASS_HID_2328] = 1126, - [BNXT_ULP_CLASS_HID_71a4] = 1127, - [BNXT_ULP_CLASS_HID_4e78] = 1128, - [BNXT_ULP_CLASS_HID_5d88] = 1129, - [BNXT_ULP_CLASS_HID_5a6c] = 1130, - [BNXT_ULP_CLASS_HID_11a8] = 1131, - [BNXT_ULP_CLASS_HID_7738] = 1132, - [BNXT_ULP_CLASS_HID_4a48] = 1133, - [BNXT_ULP_CLASS_HID_432c] = 1134, - [BNXT_ULP_CLASS_HID_08ec] = 1135, - [BNXT_ULP_CLASS_HID_01c0] = 1136, - [BNXT_ULP_CLASS_HID_14d0] = 1137, - [BNXT_ULP_CLASS_HID_7a60] = 1138, - [BNXT_ULP_CLASS_HID_1d90] = 1139, - [BNXT_ULP_CLASS_HID_14b4] = 1140, - [BNXT_ULP_CLASS_HID_70f0] = 1141, - [BNXT_ULP_CLASS_HID_4814] = 1142, - [BNXT_ULP_CLASS_HID_3d94] = 1143, - [BNXT_ULP_CLASS_HID_34b8] = 1144, - [BNXT_ULP_CLASS_HID_09a8] = 1145, - [BNXT_ULP_CLASS_HID_00cc] = 1146, - [BNXT_ULP_CLASS_HID_23f64] = 1147, - [BNXT_ULP_CLASS_HID_23688] = 1148, - [BNXT_ULP_CLASS_HID_20b78] = 1149, - [BNXT_ULP_CLASS_HID_2029c] = 1150, - [BNXT_ULP_CLASS_HID_25f68] = 1151, - [BNXT_ULP_CLASS_HID_2568c] = 1152, - [BNXT_ULP_CLASS_HID_22b7c] = 1153, - [BNXT_ULP_CLASS_HID_222a0] = 1154, - [BNXT_ULP_CLASS_HID_14020] = 1155, - [BNXT_ULP_CLASS_HID_15b44] = 1156, - [BNXT_ULP_CLASS_HID_12c34] = 1157, - [BNXT_ULP_CLASS_HID_12758] = 1158, - [BNXT_ULP_CLASS_HID_118d8] = 1159, - [BNXT_ULP_CLASS_HID_113fc] = 1160, - [BNXT_ULP_CLASS_HID_14c38] = 1161, - [BNXT_ULP_CLASS_HID_1475c] = 1162, - [BNXT_ULP_CLASS_HID_31aa8] = 1163, - [BNXT_ULP_CLASS_HID_315cc] = 1164, - [BNXT_ULP_CLASS_HID_34e08] = 1165, - [BNXT_ULP_CLASS_HID_3492c] = 1166, - [BNXT_ULP_CLASS_HID_33aac] = 1167, - [BNXT_ULP_CLASS_HID_335d0] = 1168, - [BNXT_ULP_CLASS_HID_306c0] = 1169, - [BNXT_ULP_CLASS_HID_301e4] = 1170, - [BNXT_ULP_CLASS_HID_4d32] = 1171, - [BNXT_ULP_CLASS_HID_54aa] = 1172, - [BNXT_ULP_CLASS_HID_0686] = 1173, - [BNXT_ULP_CLASS_HID_540e] = 1174, - [BNXT_ULP_CLASS_HID_2e3c] = 1175, - [BNXT_ULP_CLASS_HID_3a20] = 1176, - [BNXT_ULP_CLASS_HID_46f0] = 1177, - [BNXT_ULP_CLASS_HID_52e4] = 1178, - [BNXT_ULP_CLASS_HID_55e4] = 1179, - [BNXT_ULP_CLASS_HID_21f8] = 1180, - [BNXT_ULP_CLASS_HID_75e8] = 1181, - [BNXT_ULP_CLASS_HID_41fc] = 1182, - [BNXT_ULP_CLASS_HID_4d12] = 1183, - [BNXT_ULP_CLASS_HID_548a] = 1184, - [BNXT_ULP_CLASS_HID_3356] = 1185, - [BNXT_ULP_CLASS_HID_1ace] = 1186, - [BNXT_ULP_CLASS_HID_1a9a] = 1187, - [BNXT_ULP_CLASS_HID_4d46] = 1188, - [BNXT_ULP_CLASS_HID_2812] = 1189, - [BNXT_ULP_CLASS_HID_338a] = 1190, - [BNXT_ULP_CLASS_HID_06e6] = 1191, - [BNXT_ULP_CLASS_HID_546e] = 1192, - [BNXT_ULP_CLASS_HID_46ee] = 1193, - [BNXT_ULP_CLASS_HID_0d22] = 1194, - [BNXT_ULP_CLASS_HID_26e2] = 1195, - [BNXT_ULP_CLASS_HID_746a] = 1196, - [BNXT_ULP_CLASS_HID_1fa6] = 1197, - [BNXT_ULP_CLASS_HID_2d2e] = 1198, - [BNXT_ULP_CLASS_HID_4ef2] = 1199, - [BNXT_ULP_CLASS_HID_576a] = 1200, - [BNXT_ULP_CLASS_HID_30b6] = 1201, - [BNXT_ULP_CLASS_HID_192e] = 1202, - [BNXT_ULP_CLASS_HID_197a] = 1203, - [BNXT_ULP_CLASS_HID_4ea6] = 1204, - [BNXT_ULP_CLASS_HID_2bf2] = 1205, - [BNXT_ULP_CLASS_HID_306a] = 1206, - [BNXT_ULP_CLASS_HID_06c6] = 1207, - [BNXT_ULP_CLASS_HID_544e] = 1208, - [BNXT_ULP_CLASS_HID_46ce] = 1209, - [BNXT_ULP_CLASS_HID_0d02] = 1210, - [BNXT_ULP_CLASS_HID_26c2] = 1211, - [BNXT_ULP_CLASS_HID_744a] = 1212, - [BNXT_ULP_CLASS_HID_1f86] = 1213, - [BNXT_ULP_CLASS_HID_2d0e] = 1214, - [BNXT_ULP_CLASS_HID_2e1c] = 1215, - [BNXT_ULP_CLASS_HID_3a00] = 1216, - [BNXT_ULP_CLASS_HID_46d0] = 1217, - [BNXT_ULP_CLASS_HID_52c4] = 1218, - [BNXT_ULP_CLASS_HID_4e10] = 1219, - [BNXT_ULP_CLASS_HID_5a04] = 1220, - [BNXT_ULP_CLASS_HID_1f98] = 1221, - [BNXT_ULP_CLASS_HID_72f8] = 1222, - [BNXT_ULP_CLASS_HID_0a78] = 1223, - [BNXT_ULP_CLASS_HID_166c] = 1224, - [BNXT_ULP_CLASS_HID_233c] = 1225, - [BNXT_ULP_CLASS_HID_0f20] = 1226, - [BNXT_ULP_CLASS_HID_2a7c] = 1227, - [BNXT_ULP_CLASS_HID_3660] = 1228, - [BNXT_ULP_CLASS_HID_4330] = 1229, - [BNXT_ULP_CLASS_HID_2f24] = 1230, - [BNXT_ULP_CLASS_HID_5584] = 1231, - [BNXT_ULP_CLASS_HID_2198] = 1232, - [BNXT_ULP_CLASS_HID_7588] = 1233, - [BNXT_ULP_CLASS_HID_419c] = 1234, - [BNXT_ULP_CLASS_HID_27758] = 1235, - [BNXT_ULP_CLASS_HID_243ac] = 1236, - [BNXT_ULP_CLASS_HID_20c10] = 1237, - [BNXT_ULP_CLASS_HID_21864] = 1238, - [BNXT_ULP_CLASS_HID_130c8] = 1239, - [BNXT_ULP_CLASS_HID_11cdc] = 1240, - [BNXT_ULP_CLASS_HID_150cc] = 1241, - [BNXT_ULP_CLASS_HID_13d20] = 1242, - [BNXT_ULP_CLASS_HID_3529c] = 1243, - [BNXT_ULP_CLASS_HID_33ef0] = 1244, - [BNXT_ULP_CLASS_HID_372e0] = 1245, - [BNXT_ULP_CLASS_HID_35ef4] = 1246, - [BNXT_ULP_CLASS_HID_2dfc] = 1247, - [BNXT_ULP_CLASS_HID_39e0] = 1248, - [BNXT_ULP_CLASS_HID_4530] = 1249, - [BNXT_ULP_CLASS_HID_5124] = 1250, - [BNXT_ULP_CLASS_HID_4df0] = 1251, - [BNXT_ULP_CLASS_HID_59e4] = 1252, - [BNXT_ULP_CLASS_HID_1c78] = 1253, - [BNXT_ULP_CLASS_HID_7118] = 1254, - [BNXT_ULP_CLASS_HID_0998] = 1255, - [BNXT_ULP_CLASS_HID_158c] = 1256, - [BNXT_ULP_CLASS_HID_20dc] = 1257, - [BNXT_ULP_CLASS_HID_0cc0] = 1258, - [BNXT_ULP_CLASS_HID_299c] = 1259, - [BNXT_ULP_CLASS_HID_3580] = 1260, - [BNXT_ULP_CLASS_HID_40d0] = 1261, - [BNXT_ULP_CLASS_HID_2cc4] = 1262, - [BNXT_ULP_CLASS_HID_55a4] = 1263, - [BNXT_ULP_CLASS_HID_21b8] = 1264, - [BNXT_ULP_CLASS_HID_75a8] = 1265, - [BNXT_ULP_CLASS_HID_41bc] = 1266, - [BNXT_ULP_CLASS_HID_27778] = 1267, - [BNXT_ULP_CLASS_HID_2438c] = 1268, - [BNXT_ULP_CLASS_HID_20c30] = 1269, - [BNXT_ULP_CLASS_HID_21844] = 1270, - [BNXT_ULP_CLASS_HID_130e8] = 1271, - [BNXT_ULP_CLASS_HID_11cfc] = 1272, - [BNXT_ULP_CLASS_HID_150ec] = 1273, - [BNXT_ULP_CLASS_HID_13d00] = 1274, - [BNXT_ULP_CLASS_HID_352bc] = 1275, - [BNXT_ULP_CLASS_HID_33ed0] = 1276, - [BNXT_ULP_CLASS_HID_372c0] = 1277, - [BNXT_ULP_CLASS_HID_35ed4] = 1278, - [BNXT_ULP_CLASS_HID_3866] = 1279, - [BNXT_ULP_CLASS_HID_381e] = 1280, - [BNXT_ULP_CLASS_HID_3860] = 1281, - [BNXT_ULP_CLASS_HID_0454] = 1282, - [BNXT_ULP_CLASS_HID_3818] = 1283, - [BNXT_ULP_CLASS_HID_042c] = 1284, - [BNXT_ULP_CLASS_HID_3846] = 1285, - [BNXT_ULP_CLASS_HID_387e] = 1286, - [BNXT_ULP_CLASS_HID_3ba6] = 1287, - [BNXT_ULP_CLASS_HID_385e] = 1288, - [BNXT_ULP_CLASS_HID_3840] = 1289, - [BNXT_ULP_CLASS_HID_0474] = 1290, - [BNXT_ULP_CLASS_HID_3878] = 1291, - [BNXT_ULP_CLASS_HID_044c] = 1292, - [BNXT_ULP_CLASS_HID_3ba0] = 1293, - [BNXT_ULP_CLASS_HID_0794] = 1294, - [BNXT_ULP_CLASS_HID_3858] = 1295, - [BNXT_ULP_CLASS_HID_046c] = 1296 + [BNXT_ULP_CLASS_HID_00b8] = 1, + [BNXT_ULP_CLASS_HID_0cc2] = 2, + [BNXT_ULP_CLASS_HID_10e4] = 3, + [BNXT_ULP_CLASS_HID_1d0e] = 4, + [BNXT_ULP_CLASS_HID_0286] = 5, + [BNXT_ULP_CLASS_HID_0e98] = 6, + [BNXT_ULP_CLASS_HID_1666] = 7, + [BNXT_ULP_CLASS_HID_02de] = 8, + [BNXT_ULP_CLASS_HID_81d25] = 9, + [BNXT_ULP_CLASS_HID_809ad] = 10, + [BNXT_ULP_CLASS_HID_80ae3] = 11, + [BNXT_ULP_CLASS_HID_8170d] = 12, + [BNXT_ULP_CLASS_HID_80773] = 13, + [BNXT_ULP_CLASS_HID_8139d] = 14, + [BNXT_ULP_CLASS_HID_814d3] = 15, + [BNXT_ULP_CLASS_HID_8015b] = 16, + [BNXT_ULP_CLASS_HID_21977] = 17, + [BNXT_ULP_CLASS_HID_205ef] = 18, + [BNXT_ULP_CLASS_HID_20735] = 19, + [BNXT_ULP_CLASS_HID_2134f] = 20, + [BNXT_ULP_CLASS_HID_61beb] = 21, + [BNXT_ULP_CLASS_HID_60863] = 22, + [BNXT_ULP_CLASS_HID_609a9] = 23, + [BNXT_ULP_CLASS_HID_615c3] = 24, + [BNXT_ULP_CLASS_HID_00a8] = 25, + [BNXT_ULP_CLASS_HID_0cd2] = 26, + [BNXT_ULP_CLASS_HID_10f4] = 27, + [BNXT_ULP_CLASS_HID_1d1e] = 28, + [BNXT_ULP_CLASS_HID_1488] = 29, + [BNXT_ULP_CLASS_HID_0110] = 30, + [BNXT_ULP_CLASS_HID_0532] = 31, + [BNXT_ULP_CLASS_HID_115c] = 32, + [BNXT_ULP_CLASS_HID_0ab8] = 33, + [BNXT_ULP_CLASS_HID_16a2] = 34, + [BNXT_ULP_CLASS_HID_1ac4] = 35, + [BNXT_ULP_CLASS_HID_074c] = 36, + [BNXT_ULP_CLASS_HID_1e98] = 37, + [BNXT_ULP_CLASS_HID_0ae0] = 38, + [BNXT_ULP_CLASS_HID_0f02] = 39, + [BNXT_ULP_CLASS_HID_1b2c] = 40, + [BNXT_ULP_CLASS_HID_0296] = 41, + [BNXT_ULP_CLASS_HID_0e88] = 42, + [BNXT_ULP_CLASS_HID_1676] = 43, + [BNXT_ULP_CLASS_HID_02ce] = 44, + [BNXT_ULP_CLASS_HID_8076e] = 45, + [BNXT_ULP_CLASS_HID_81380] = 46, + [BNXT_ULP_CLASS_HID_81b4e] = 47, + [BNXT_ULP_CLASS_HID_807c6] = 48, + [BNXT_ULP_CLASS_HID_404ea] = 49, + [BNXT_ULP_CLASS_HID_4110c] = 50, + [BNXT_ULP_CLASS_HID_418ca] = 51, + [BNXT_ULP_CLASS_HID_40542] = 52, + [BNXT_ULP_CLASS_HID_c09e2] = 53, + [BNXT_ULP_CLASS_HID_c1604] = 54, + [BNXT_ULP_CLASS_HID_c1dc2] = 55, + [BNXT_ULP_CLASS_HID_c0a5a] = 56, + [BNXT_ULP_CLASS_HID_0098] = 57, + [BNXT_ULP_CLASS_HID_0ce2] = 58, + [BNXT_ULP_CLASS_HID_10c4] = 59, + [BNXT_ULP_CLASS_HID_1d2e] = 60, + [BNXT_ULP_CLASS_HID_14b8] = 61, + [BNXT_ULP_CLASS_HID_0120] = 62, + [BNXT_ULP_CLASS_HID_0502] = 63, + [BNXT_ULP_CLASS_HID_116c] = 64, + [BNXT_ULP_CLASS_HID_0a88] = 65, + [BNXT_ULP_CLASS_HID_1692] = 66, + [BNXT_ULP_CLASS_HID_1af4] = 67, + [BNXT_ULP_CLASS_HID_077c] = 68, + [BNXT_ULP_CLASS_HID_1ea8] = 69, + [BNXT_ULP_CLASS_HID_0ad0] = 70, + [BNXT_ULP_CLASS_HID_0f32] = 71, + [BNXT_ULP_CLASS_HID_1b1c] = 72, + [BNXT_ULP_CLASS_HID_02a6] = 73, + [BNXT_ULP_CLASS_HID_0eb8] = 74, + [BNXT_ULP_CLASS_HID_1646] = 75, + [BNXT_ULP_CLASS_HID_02fe] = 76, + [BNXT_ULP_CLASS_HID_8075e] = 77, + [BNXT_ULP_CLASS_HID_813b0] = 78, + [BNXT_ULP_CLASS_HID_81b7e] = 79, + [BNXT_ULP_CLASS_HID_807f6] = 80, + [BNXT_ULP_CLASS_HID_404da] = 81, + [BNXT_ULP_CLASS_HID_4113c] = 82, + [BNXT_ULP_CLASS_HID_418fa] = 83, + [BNXT_ULP_CLASS_HID_40572] = 84, + [BNXT_ULP_CLASS_HID_c09d2] = 85, + [BNXT_ULP_CLASS_HID_c1634] = 86, + [BNXT_ULP_CLASS_HID_c1df2] = 87, + [BNXT_ULP_CLASS_HID_c0a6a] = 88, + [BNXT_ULP_CLASS_HID_81d35] = 89, + [BNXT_ULP_CLASS_HID_809bd] = 90, + [BNXT_ULP_CLASS_HID_80af3] = 91, + [BNXT_ULP_CLASS_HID_8171d] = 92, + [BNXT_ULP_CLASS_HID_80763] = 93, + [BNXT_ULP_CLASS_HID_8138d] = 94, + [BNXT_ULP_CLASS_HID_814c3] = 95, + [BNXT_ULP_CLASS_HID_8014b] = 96, + [BNXT_ULP_CLASS_HID_c001f] = 97, + [BNXT_ULP_CLASS_HID_c0c39] = 98, + [BNXT_ULP_CLASS_HID_c0d7f] = 99, + [BNXT_ULP_CLASS_HID_c1999] = 100, + [BNXT_ULP_CLASS_HID_c09ef] = 101, + [BNXT_ULP_CLASS_HID_c1609] = 102, + [BNXT_ULP_CLASS_HID_c174f] = 103, + [BNXT_ULP_CLASS_HID_c03d7] = 104, + [BNXT_ULP_CLASS_HID_a1e73] = 105, + [BNXT_ULP_CLASS_HID_a0afb] = 106, + [BNXT_ULP_CLASS_HID_a0c31] = 107, + [BNXT_ULP_CLASS_HID_a185b] = 108, + [BNXT_ULP_CLASS_HID_a08a1] = 109, + [BNXT_ULP_CLASS_HID_a14cb] = 110, + [BNXT_ULP_CLASS_HID_a1601] = 111, + [BNXT_ULP_CLASS_HID_a0289] = 112, + [BNXT_ULP_CLASS_HID_e015d] = 113, + [BNXT_ULP_CLASS_HID_e0d47] = 114, + [BNXT_ULP_CLASS_HID_e0ebd] = 115, + [BNXT_ULP_CLASS_HID_e1aa7] = 116, + [BNXT_ULP_CLASS_HID_e0b2d] = 117, + [BNXT_ULP_CLASS_HID_e1757] = 118, + [BNXT_ULP_CLASS_HID_e188d] = 119, + [BNXT_ULP_CLASS_HID_e0515] = 120, + [BNXT_ULP_CLASS_HID_21967] = 121, + [BNXT_ULP_CLASS_HID_205ff] = 122, + [BNXT_ULP_CLASS_HID_20725] = 123, + [BNXT_ULP_CLASS_HID_2135f] = 124, + [BNXT_ULP_CLASS_HID_61bfb] = 125, + [BNXT_ULP_CLASS_HID_60873] = 126, + [BNXT_ULP_CLASS_HID_609b9] = 127, + [BNXT_ULP_CLASS_HID_615d3] = 128, + [BNXT_ULP_CLASS_HID_30a55] = 129, + [BNXT_ULP_CLASS_HID_3164f] = 130, + [BNXT_ULP_CLASS_HID_317b5] = 131, + [BNXT_ULP_CLASS_HID_3040d] = 132, + [BNXT_ULP_CLASS_HID_70ca9] = 133, + [BNXT_ULP_CLASS_HID_718c3] = 134, + [BNXT_ULP_CLASS_HID_71a09] = 135, + [BNXT_ULP_CLASS_HID_70681] = 136, + [BNXT_ULP_CLASS_HID_2821d] = 137, + [BNXT_ULP_CLASS_HID_28e37] = 138, + [BNXT_ULP_CLASS_HID_28f7d] = 139, + [BNXT_ULP_CLASS_HID_29b97] = 140, + [BNXT_ULP_CLASS_HID_68491] = 141, + [BNXT_ULP_CLASS_HID_6908b] = 142, + [BNXT_ULP_CLASS_HID_691f1] = 143, + [BNXT_ULP_CLASS_HID_69deb] = 144, + [BNXT_ULP_CLASS_HID_3926d] = 145, + [BNXT_ULP_CLASS_HID_39e87] = 146, + [BNXT_ULP_CLASS_HID_38023] = 147, + [BNXT_ULP_CLASS_HID_38c45] = 148, + [BNXT_ULP_CLASS_HID_794e1] = 149, + [BNXT_ULP_CLASS_HID_78179] = 150, + [BNXT_ULP_CLASS_HID_782a7] = 151, + [BNXT_ULP_CLASS_HID_78ed9] = 152, + [BNXT_ULP_CLASS_HID_81d05] = 153, + [BNXT_ULP_CLASS_HID_8098d] = 154, + [BNXT_ULP_CLASS_HID_80ac3] = 155, + [BNXT_ULP_CLASS_HID_8172d] = 156, + [BNXT_ULP_CLASS_HID_80753] = 157, + [BNXT_ULP_CLASS_HID_813bd] = 158, + [BNXT_ULP_CLASS_HID_814f3] = 159, + [BNXT_ULP_CLASS_HID_8017b] = 160, + [BNXT_ULP_CLASS_HID_c002f] = 161, + [BNXT_ULP_CLASS_HID_c0c09] = 162, + [BNXT_ULP_CLASS_HID_c0d4f] = 163, + [BNXT_ULP_CLASS_HID_c19a9] = 164, + [BNXT_ULP_CLASS_HID_c09df] = 165, + [BNXT_ULP_CLASS_HID_c1639] = 166, + [BNXT_ULP_CLASS_HID_c177f] = 167, + [BNXT_ULP_CLASS_HID_c03e7] = 168, + [BNXT_ULP_CLASS_HID_a1e43] = 169, + [BNXT_ULP_CLASS_HID_a0acb] = 170, + [BNXT_ULP_CLASS_HID_a0c01] = 171, + [BNXT_ULP_CLASS_HID_a186b] = 172, + [BNXT_ULP_CLASS_HID_a0891] = 173, + [BNXT_ULP_CLASS_HID_a14fb] = 174, + [BNXT_ULP_CLASS_HID_a1631] = 175, + [BNXT_ULP_CLASS_HID_a02b9] = 176, + [BNXT_ULP_CLASS_HID_e016d] = 177, + [BNXT_ULP_CLASS_HID_e0d77] = 178, + [BNXT_ULP_CLASS_HID_e0e8d] = 179, + [BNXT_ULP_CLASS_HID_e1a97] = 180, + [BNXT_ULP_CLASS_HID_e0b1d] = 181, + [BNXT_ULP_CLASS_HID_e1767] = 182, + [BNXT_ULP_CLASS_HID_e18bd] = 183, + [BNXT_ULP_CLASS_HID_e0525] = 184, + [BNXT_ULP_CLASS_HID_21957] = 185, + [BNXT_ULP_CLASS_HID_205cf] = 186, + [BNXT_ULP_CLASS_HID_20715] = 187, + [BNXT_ULP_CLASS_HID_2136f] = 188, + [BNXT_ULP_CLASS_HID_61bcb] = 189, + [BNXT_ULP_CLASS_HID_60843] = 190, + [BNXT_ULP_CLASS_HID_60989] = 191, + [BNXT_ULP_CLASS_HID_615e3] = 192, + [BNXT_ULP_CLASS_HID_30a65] = 193, + [BNXT_ULP_CLASS_HID_3167f] = 194, + [BNXT_ULP_CLASS_HID_31785] = 195, + [BNXT_ULP_CLASS_HID_3043d] = 196, + [BNXT_ULP_CLASS_HID_70c99] = 197, + [BNXT_ULP_CLASS_HID_718f3] = 198, + [BNXT_ULP_CLASS_HID_71a39] = 199, + [BNXT_ULP_CLASS_HID_706b1] = 200, + [BNXT_ULP_CLASS_HID_2822d] = 201, + [BNXT_ULP_CLASS_HID_28e07] = 202, + [BNXT_ULP_CLASS_HID_28f4d] = 203, + [BNXT_ULP_CLASS_HID_29ba7] = 204, + [BNXT_ULP_CLASS_HID_684a1] = 205, + [BNXT_ULP_CLASS_HID_690bb] = 206, + [BNXT_ULP_CLASS_HID_691c1] = 207, + [BNXT_ULP_CLASS_HID_69ddb] = 208, + [BNXT_ULP_CLASS_HID_3925d] = 209, + [BNXT_ULP_CLASS_HID_39eb7] = 210, + [BNXT_ULP_CLASS_HID_38013] = 211, + [BNXT_ULP_CLASS_HID_38c75] = 212, + [BNXT_ULP_CLASS_HID_794d1] = 213, + [BNXT_ULP_CLASS_HID_78149] = 214, + [BNXT_ULP_CLASS_HID_78297] = 215, + [BNXT_ULP_CLASS_HID_78ee9] = 216, + [BNXT_ULP_CLASS_HID_0816] = 217, + [BNXT_ULP_CLASS_HID_1852] = 218, + [BNXT_ULP_CLASS_HID_09f4] = 219, + [BNXT_ULP_CLASS_HID_1dd4] = 220, + [BNXT_ULP_CLASS_HID_804f1] = 221, + [BNXT_ULP_CLASS_HID_81251] = 222, + [BNXT_ULP_CLASS_HID_80ee1] = 223, + [BNXT_ULP_CLASS_HID_81c41] = 224, + [BNXT_ULP_CLASS_HID_2013b] = 225, + [BNXT_ULP_CLASS_HID_20e9b] = 226, + [BNXT_ULP_CLASS_HID_603bf] = 227, + [BNXT_ULP_CLASS_HID_6111f] = 228, + [BNXT_ULP_CLASS_HID_0806] = 229, + [BNXT_ULP_CLASS_HID_1842] = 230, + [BNXT_ULP_CLASS_HID_1be6] = 231, + [BNXT_ULP_CLASS_HID_0c80] = 232, + [BNXT_ULP_CLASS_HID_1216] = 233, + [BNXT_ULP_CLASS_HID_02b0] = 234, + [BNXT_ULP_CLASS_HID_0654] = 235, + [BNXT_ULP_CLASS_HID_1690] = 236, + [BNXT_ULP_CLASS_HID_09e4] = 237, + [BNXT_ULP_CLASS_HID_1dc4] = 238, + [BNXT_ULP_CLASS_HID_80efc] = 239, + [BNXT_ULP_CLASS_HID_80332] = 240, + [BNXT_ULP_CLASS_HID_40c78] = 241, + [BNXT_ULP_CLASS_HID_400be] = 242, + [BNXT_ULP_CLASS_HID_c1170] = 243, + [BNXT_ULP_CLASS_HID_c05b6] = 244, + [BNXT_ULP_CLASS_HID_0836] = 245, + [BNXT_ULP_CLASS_HID_1872] = 246, + [BNXT_ULP_CLASS_HID_1bd6] = 247, + [BNXT_ULP_CLASS_HID_0cb0] = 248, + [BNXT_ULP_CLASS_HID_1226] = 249, + [BNXT_ULP_CLASS_HID_0280] = 250, + [BNXT_ULP_CLASS_HID_0664] = 251, + [BNXT_ULP_CLASS_HID_16a0] = 252, + [BNXT_ULP_CLASS_HID_09d4] = 253, + [BNXT_ULP_CLASS_HID_1df4] = 254, + [BNXT_ULP_CLASS_HID_80ecc] = 255, + [BNXT_ULP_CLASS_HID_80302] = 256, + [BNXT_ULP_CLASS_HID_40c48] = 257, + [BNXT_ULP_CLASS_HID_4008e] = 258, + [BNXT_ULP_CLASS_HID_c1140] = 259, + [BNXT_ULP_CLASS_HID_c0586] = 260, + [BNXT_ULP_CLASS_HID_804e1] = 261, + [BNXT_ULP_CLASS_HID_81241] = 262, + [BNXT_ULP_CLASS_HID_80ef1] = 263, + [BNXT_ULP_CLASS_HID_81c51] = 264, + [BNXT_ULP_CLASS_HID_c076d] = 265, + [BNXT_ULP_CLASS_HID_c14cd] = 266, + [BNXT_ULP_CLASS_HID_c117d] = 267, + [BNXT_ULP_CLASS_HID_c1edd] = 268, + [BNXT_ULP_CLASS_HID_a062f] = 269, + [BNXT_ULP_CLASS_HID_a138f] = 270, + [BNXT_ULP_CLASS_HID_a103f] = 271, + [BNXT_ULP_CLASS_HID_a1d9f] = 272, + [BNXT_ULP_CLASS_HID_e08ab] = 273, + [BNXT_ULP_CLASS_HID_e160b] = 274, + [BNXT_ULP_CLASS_HID_e12bb] = 275, + [BNXT_ULP_CLASS_HID_e0079] = 276, + [BNXT_ULP_CLASS_HID_2012b] = 277, + [BNXT_ULP_CLASS_HID_20e8b] = 278, + [BNXT_ULP_CLASS_HID_603af] = 279, + [BNXT_ULP_CLASS_HID_6110f] = 280, + [BNXT_ULP_CLASS_HID_311bb] = 281, + [BNXT_ULP_CLASS_HID_31f1b] = 282, + [BNXT_ULP_CLASS_HID_7143f] = 283, + [BNXT_ULP_CLASS_HID_701fd] = 284, + [BNXT_ULP_CLASS_HID_28963] = 285, + [BNXT_ULP_CLASS_HID_296c3] = 286, + [BNXT_ULP_CLASS_HID_68be7] = 287, + [BNXT_ULP_CLASS_HID_69947] = 288, + [BNXT_ULP_CLASS_HID_399f3] = 289, + [BNXT_ULP_CLASS_HID_387b1] = 290, + [BNXT_ULP_CLASS_HID_79c77] = 291, + [BNXT_ULP_CLASS_HID_78a35] = 292, + [BNXT_ULP_CLASS_HID_804d1] = 293, + [BNXT_ULP_CLASS_HID_81271] = 294, + [BNXT_ULP_CLASS_HID_80ec1] = 295, + [BNXT_ULP_CLASS_HID_81c61] = 296, + [BNXT_ULP_CLASS_HID_c075d] = 297, + [BNXT_ULP_CLASS_HID_c14fd] = 298, + [BNXT_ULP_CLASS_HID_c114d] = 299, + [BNXT_ULP_CLASS_HID_c1eed] = 300, + [BNXT_ULP_CLASS_HID_a061f] = 301, + [BNXT_ULP_CLASS_HID_a13bf] = 302, + [BNXT_ULP_CLASS_HID_a100f] = 303, + [BNXT_ULP_CLASS_HID_a1daf] = 304, + [BNXT_ULP_CLASS_HID_e089b] = 305, + [BNXT_ULP_CLASS_HID_e163b] = 306, + [BNXT_ULP_CLASS_HID_e128b] = 307, + [BNXT_ULP_CLASS_HID_e0049] = 308, + [BNXT_ULP_CLASS_HID_2011b] = 309, + [BNXT_ULP_CLASS_HID_20ebb] = 310, + [BNXT_ULP_CLASS_HID_6039f] = 311, + [BNXT_ULP_CLASS_HID_6113f] = 312, + [BNXT_ULP_CLASS_HID_3118b] = 313, + [BNXT_ULP_CLASS_HID_31f2b] = 314, + [BNXT_ULP_CLASS_HID_7140f] = 315, + [BNXT_ULP_CLASS_HID_701cd] = 316, + [BNXT_ULP_CLASS_HID_28953] = 317, + [BNXT_ULP_CLASS_HID_296f3] = 318, + [BNXT_ULP_CLASS_HID_68bd7] = 319, + [BNXT_ULP_CLASS_HID_69977] = 320, + [BNXT_ULP_CLASS_HID_399c3] = 321, + [BNXT_ULP_CLASS_HID_38781] = 322, + [BNXT_ULP_CLASS_HID_79c47] = 323, + [BNXT_ULP_CLASS_HID_78a05] = 324, + [BNXT_ULP_CLASS_HID_04a4] = 325, + [BNXT_ULP_CLASS_HID_04a8] = 326, + [BNXT_ULP_CLASS_HID_04a5] = 327, + [BNXT_ULP_CLASS_HID_1205] = 328, + [BNXT_ULP_CLASS_HID_04a9] = 329, + [BNXT_ULP_CLASS_HID_1209] = 330, + [BNXT_ULP_CLASS_HID_04b4] = 331, + [BNXT_ULP_CLASS_HID_04b8] = 332, + [BNXT_ULP_CLASS_HID_0484] = 333, + [BNXT_ULP_CLASS_HID_0488] = 334, + [BNXT_ULP_CLASS_HID_04b5] = 335, + [BNXT_ULP_CLASS_HID_1215] = 336, + [BNXT_ULP_CLASS_HID_04b9] = 337, + [BNXT_ULP_CLASS_HID_1219] = 338, + [BNXT_ULP_CLASS_HID_0485] = 339, + [BNXT_ULP_CLASS_HID_1225] = 340, + [BNXT_ULP_CLASS_HID_0489] = 341, + [BNXT_ULP_CLASS_HID_1229] = 342, + [BNXT_ULP_CLASS_HID_0226] = 343, + [BNXT_ULP_CLASS_HID_4045a] = 344, + [BNXT_ULP_CLASS_HID_0daa] = 345, + [BNXT_ULP_CLASS_HID_11b0] = 346, + [BNXT_ULP_CLASS_HID_403f8] = 347, + [BNXT_ULP_CLASS_HID_4161e] = 348, + [BNXT_ULP_CLASS_HID_40439] = 349, + [BNXT_ULP_CLASS_HID_41405] = 350, + [BNXT_ULP_CLASS_HID_51449] = 351, + [BNXT_ULP_CLASS_HID_50b33] = 352, + [BNXT_ULP_CLASS_HID_48c01] = 353, + [BNXT_ULP_CLASS_HID_483eb] = 354, + [BNXT_ULP_CLASS_HID_5833f] = 355, + [BNXT_ULP_CLASS_HID_5937b] = 356, + [BNXT_ULP_CLASS_HID_41875] = 357, + [BNXT_ULP_CLASS_HID_40f5f] = 358, + [BNXT_ULP_CLASS_HID_50f23] = 359, + [BNXT_ULP_CLASS_HID_51f6f] = 360, + [BNXT_ULP_CLASS_HID_4875b] = 361, + [BNXT_ULP_CLASS_HID_49727] = 362, + [BNXT_ULP_CLASS_HID_5976b] = 363, + [BNXT_ULP_CLASS_HID_58655] = 364, + [BNXT_ULP_CLASS_HID_4125f] = 365, + [BNXT_ULP_CLASS_HID_401f9] = 366, + [BNXT_ULP_CLASS_HID_501cd] = 367, + [BNXT_ULP_CLASS_HID_51149] = 368, + [BNXT_ULP_CLASS_HID_49a67] = 369, + [BNXT_ULP_CLASS_HID_489c1] = 370, + [BNXT_ULP_CLASS_HID_58955] = 371, + [BNXT_ULP_CLASS_HID_59951] = 372, + [BNXT_ULP_CLASS_HID_40569] = 373, + [BNXT_ULP_CLASS_HID_41575] = 374, + [BNXT_ULP_CLASS_HID_51579] = 375, + [BNXT_ULP_CLASS_HID_50463] = 376, + [BNXT_ULP_CLASS_HID_48d71] = 377, + [BNXT_ULP_CLASS_HID_49d7d] = 378, + [BNXT_ULP_CLASS_HID_59d41] = 379, + [BNXT_ULP_CLASS_HID_58c6b] = 380, + [BNXT_ULP_CLASS_HID_10255] = 381, + [BNXT_ULP_CLASS_HID_11675] = 382, + [BNXT_ULP_CLASS_HID_14649] = 383, + [BNXT_ULP_CLASS_HID_15a69] = 384, + [BNXT_ULP_CLASS_HID_1205b] = 385, + [BNXT_ULP_CLASS_HID_1347b] = 386, + [BNXT_ULP_CLASS_HID_16bbf] = 387, + [BNXT_ULP_CLASS_HID_1785f] = 388, + [BNXT_ULP_CLASS_HID_11551] = 389, + [BNXT_ULP_CLASS_HID_10897] = 390, + [BNXT_ULP_CLASS_HID_15955] = 391, + [BNXT_ULP_CLASS_HID_14c8b] = 392, + [BNXT_ULP_CLASS_HID_13b47] = 393, + [BNXT_ULP_CLASS_HID_12e85] = 394, + [BNXT_ULP_CLASS_HID_17f5b] = 395, + [BNXT_ULP_CLASS_HID_17299] = 396, + [BNXT_ULP_CLASS_HID_10fe7] = 397, + [BNXT_ULP_CLASS_HID_10325] = 398, + [BNXT_ULP_CLASS_HID_153cb] = 399, + [BNXT_ULP_CLASS_HID_14709] = 400, + [BNXT_ULP_CLASS_HID_12dc5] = 401, + [BNXT_ULP_CLASS_HID_1212b] = 402, + [BNXT_ULP_CLASS_HID_171c9] = 403, + [BNXT_ULP_CLASS_HID_1650f] = 404, + [BNXT_ULP_CLASS_HID_10201] = 405, + [BNXT_ULP_CLASS_HID_116c1] = 406, + [BNXT_ULP_CLASS_HID_14605] = 407, + [BNXT_ULP_CLASS_HID_15a05] = 408, + [BNXT_ULP_CLASS_HID_12007] = 409, + [BNXT_ULP_CLASS_HID_13407] = 410, + [BNXT_ULP_CLASS_HID_1640b] = 411, + [BNXT_ULP_CLASS_HID_1780b] = 412, + [BNXT_ULP_CLASS_HID_404b0] = 413, + [BNXT_ULP_CLASS_HID_4148c] = 414, + [BNXT_ULP_CLASS_HID_514c0] = 415, + [BNXT_ULP_CLASS_HID_50bba] = 416, + [BNXT_ULP_CLASS_HID_48c88] = 417, + [BNXT_ULP_CLASS_HID_48362] = 418, + [BNXT_ULP_CLASS_HID_583b6] = 419, + [BNXT_ULP_CLASS_HID_593f2] = 420, + [BNXT_ULP_CLASS_HID_41f54] = 421, + [BNXT_ULP_CLASS_HID_40fce] = 422, + [BNXT_ULP_CLASS_HID_50e02] = 423, + [BNXT_ULP_CLASS_HID_51e5e] = 424, + [BNXT_ULP_CLASS_HID_487ca] = 425, + [BNXT_ULP_CLASS_HID_49606] = 426, + [BNXT_ULP_CLASS_HID_5965a] = 427, + [BNXT_ULP_CLASS_HID_58514] = 428, + [BNXT_ULP_CLASS_HID_412c2] = 429, + [BNXT_ULP_CLASS_HID_401ac] = 430, + [BNXT_ULP_CLASS_HID_501e0] = 431, + [BNXT_ULP_CLASS_HID_511cc] = 432, + [BNXT_ULP_CLASS_HID_4990a] = 433, + [BNXT_ULP_CLASS_HID_489e4] = 434, + [BNXT_ULP_CLASS_HID_589c8] = 435, + [BNXT_ULP_CLASS_HID_59804] = 436, + [BNXT_ULP_CLASS_HID_40404] = 437, + [BNXT_ULP_CLASS_HID_41440] = 438, + [BNXT_ULP_CLASS_HID_51484] = 439, + [BNXT_ULP_CLASS_HID_50b0e] = 440, + [BNXT_ULP_CLASS_HID_48c4c] = 441, + [BNXT_ULP_CLASS_HID_48306] = 442, + [BNXT_ULP_CLASS_HID_5830a] = 443, + [BNXT_ULP_CLASS_HID_59346] = 444, + [BNXT_ULP_CLASS_HID_102cc] = 445, + [BNXT_ULP_CLASS_HID_116ec] = 446, + [BNXT_ULP_CLASS_HID_146d0] = 447, + [BNXT_ULP_CLASS_HID_15af0] = 448, + [BNXT_ULP_CLASS_HID_120c2] = 449, + [BNXT_ULP_CLASS_HID_134e2] = 450, + [BNXT_ULP_CLASS_HID_16b26] = 451, + [BNXT_ULP_CLASS_HID_178c6] = 452, + [BNXT_ULP_CLASS_HID_115c6] = 453, + [BNXT_ULP_CLASS_HID_10804] = 454, + [BNXT_ULP_CLASS_HID_15822] = 455, + [BNXT_ULP_CLASS_HID_14c60] = 456, + [BNXT_ULP_CLASS_HID_13bd4] = 457, + [BNXT_ULP_CLASS_HID_12e12] = 458, + [BNXT_ULP_CLASS_HID_17e30] = 459, + [BNXT_ULP_CLASS_HID_17276] = 460, + [BNXT_ULP_CLASS_HID_11f1a] = 461, + [BNXT_ULP_CLASS_HID_11358] = 462, + [BNXT_ULP_CLASS_HID_14398] = 463, + [BNXT_ULP_CLASS_HID_157b8] = 464, + [BNXT_ULP_CLASS_HID_13d68] = 465, + [BNXT_ULP_CLASS_HID_131aa] = 466, + [BNXT_ULP_CLASS_HID_16192] = 467, + [BNXT_ULP_CLASS_HID_175b2] = 468, + [BNXT_ULP_CLASS_HID_112b2] = 469, + [BNXT_ULP_CLASS_HID_106f0] = 470, + [BNXT_ULP_CLASS_HID_15692] = 471, + [BNXT_ULP_CLASS_HID_14ad0] = 472, + [BNXT_ULP_CLASS_HID_13080] = 473, + [BNXT_ULP_CLASS_HID_124c2] = 474, + [BNXT_ULP_CLASS_HID_174e0] = 475, + [BNXT_ULP_CLASS_HID_16f22] = 476, + [BNXT_ULP_CLASS_HID_4025b] = 477, + [BNXT_ULP_CLASS_HID_41267] = 478, + [BNXT_ULP_CLASS_HID_5122b] = 479, + [BNXT_ULP_CLASS_HID_50d51] = 480, + [BNXT_ULP_CLASS_HID_48a63] = 481, + [BNXT_ULP_CLASS_HID_48589] = 482, + [BNXT_ULP_CLASS_HID_5855d] = 483, + [BNXT_ULP_CLASS_HID_59519] = 484, + [BNXT_ULP_CLASS_HID_41e17] = 485, + [BNXT_ULP_CLASS_HID_4093d] = 486, + [BNXT_ULP_CLASS_HID_50941] = 487, + [BNXT_ULP_CLASS_HID_5190d] = 488, + [BNXT_ULP_CLASS_HID_48139] = 489, + [BNXT_ULP_CLASS_HID_49145] = 490, + [BNXT_ULP_CLASS_HID_59109] = 491, + [BNXT_ULP_CLASS_HID_58037] = 492, + [BNXT_ULP_CLASS_HID_4143d] = 493, + [BNXT_ULP_CLASS_HID_4079b] = 494, + [BNXT_ULP_CLASS_HID_507af] = 495, + [BNXT_ULP_CLASS_HID_5172b] = 496, + [BNXT_ULP_CLASS_HID_49c05] = 497, + [BNXT_ULP_CLASS_HID_48fa3] = 498, + [BNXT_ULP_CLASS_HID_58f37] = 499, + [BNXT_ULP_CLASS_HID_59f33] = 500, + [BNXT_ULP_CLASS_HID_4030b] = 501, + [BNXT_ULP_CLASS_HID_41317] = 502, + [BNXT_ULP_CLASS_HID_5131b] = 503, + [BNXT_ULP_CLASS_HID_50201] = 504, + [BNXT_ULP_CLASS_HID_48b13] = 505, + [BNXT_ULP_CLASS_HID_49b1f] = 506, + [BNXT_ULP_CLASS_HID_59b23] = 507, + [BNXT_ULP_CLASS_HID_58a09] = 508, + [BNXT_ULP_CLASS_HID_419bf] = 509, + [BNXT_ULP_CLASS_HID_40925] = 510, + [BNXT_ULP_CLASS_HID_508e9] = 511, + [BNXT_ULP_CLASS_HID_518b5] = 512, + [BNXT_ULP_CLASS_HID_48121] = 513, + [BNXT_ULP_CLASS_HID_490ed] = 514, + [BNXT_ULP_CLASS_HID_590b1] = 515, + [BNXT_ULP_CLASS_HID_583ff] = 516, + [BNXT_ULP_CLASS_HID_41475] = 517, + [BNXT_ULP_CLASS_HID_40473] = 518, + [BNXT_ULP_CLASS_HID_50427] = 519, + [BNXT_ULP_CLASS_HID_51763] = 520, + [BNXT_ULP_CLASS_HID_49c3d] = 521, + [BNXT_ULP_CLASS_HID_48c3b] = 522, + [BNXT_ULP_CLASS_HID_58f6f] = 523, + [BNXT_ULP_CLASS_HID_59f2b] = 524, + [BNXT_ULP_CLASS_HID_40333] = 525, + [BNXT_ULP_CLASS_HID_412bf] = 526, + [BNXT_ULP_CLASS_HID_512a3] = 527, + [BNXT_ULP_CLASS_HID_50229] = 528, + [BNXT_ULP_CLASS_HID_48abb] = 529, + [BNXT_ULP_CLASS_HID_49aa7] = 530, + [BNXT_ULP_CLASS_HID_59a2b] = 531, + [BNXT_ULP_CLASS_HID_595b1] = 532, + [BNXT_ULP_CLASS_HID_41e2f] = 533, + [BNXT_ULP_CLASS_HID_40e35] = 534, + [BNXT_ULP_CLASS_HID_50939] = 535, + [BNXT_ULP_CLASS_HID_51925] = 536, + [BNXT_ULP_CLASS_HID_48631] = 537, + [BNXT_ULP_CLASS_HID_4913d] = 538, + [BNXT_ULP_CLASS_HID_59121] = 539, + [BNXT_ULP_CLASS_HID_5812f] = 540, + [BNXT_ULP_CLASS_HID_41429] = 541, + [BNXT_ULP_CLASS_HID_40747] = 542, + [BNXT_ULP_CLASS_HID_5070b] = 543, + [BNXT_ULP_CLASS_HID_51727] = 544, + [BNXT_ULP_CLASS_HID_49fe1] = 545, + [BNXT_ULP_CLASS_HID_48f0f] = 546, + [BNXT_ULP_CLASS_HID_58f23] = 547, + [BNXT_ULP_CLASS_HID_59eef] = 548, + [BNXT_ULP_CLASS_HID_40347] = 549, + [BNXT_ULP_CLASS_HID_41303] = 550, + [BNXT_ULP_CLASS_HID_51247] = 551, + [BNXT_ULP_CLASS_HID_5026d] = 552, + [BNXT_ULP_CLASS_HID_48b0f] = 553, + [BNXT_ULP_CLASS_HID_49a4b] = 554, + [BNXT_ULP_CLASS_HID_59a0f] = 555, + [BNXT_ULP_CLASS_HID_58a05] = 556, + [BNXT_ULP_CLASS_HID_41983] = 557, + [BNXT_ULP_CLASS_HID_40929] = 558, + [BNXT_ULP_CLASS_HID_5092d] = 559, + [BNXT_ULP_CLASS_HID_518a9] = 560, + [BNXT_ULP_CLASS_HID_48125] = 561, + [BNXT_ULP_CLASS_HID_49121] = 562, + [BNXT_ULP_CLASS_HID_59085] = 563, + [BNXT_ULP_CLASS_HID_58023] = 564, + [BNXT_ULP_CLASS_HID_41509] = 565, + [BNXT_ULP_CLASS_HID_40407] = 566, + [BNXT_ULP_CLASS_HID_5040b] = 567, + [BNXT_ULP_CLASS_HID_51407] = 568, + [BNXT_ULP_CLASS_HID_49d21] = 569, + [BNXT_ULP_CLASS_HID_48c0f] = 570, + [BNXT_ULP_CLASS_HID_58c03] = 571, + [BNXT_ULP_CLASS_HID_59f0f] = 572, + [BNXT_ULP_CLASS_HID_402ef] = 573, + [BNXT_ULP_CLASS_HID_412ab] = 574, + [BNXT_ULP_CLASS_HID_5126f] = 575, + [BNXT_ULP_CLASS_HID_50de5] = 576, + [BNXT_ULP_CLASS_HID_48aa7] = 577, + [BNXT_ULP_CLASS_HID_485ed] = 578, + [BNXT_ULP_CLASS_HID_585e1] = 579, + [BNXT_ULP_CLASS_HID_595ad] = 580, + [BNXT_ULP_CLASS_HID_41e6b] = 581, + [BNXT_ULP_CLASS_HID_40961] = 582, + [BNXT_ULP_CLASS_HID_50925] = 583, + [BNXT_ULP_CLASS_HID_51961] = 584, + [BNXT_ULP_CLASS_HID_4816d] = 585, + [BNXT_ULP_CLASS_HID_49129] = 586, + [BNXT_ULP_CLASS_HID_5916d] = 587, + [BNXT_ULP_CLASS_HID_5806b] = 588, + [BNXT_ULP_CLASS_HID_414a1] = 589, + [BNXT_ULP_CLASS_HID_4042f] = 590, + [BNXT_ULP_CLASS_HID_507a3] = 591, + [BNXT_ULP_CLASS_HID_517af] = 592, + [BNXT_ULP_CLASS_HID_49c29] = 593, + [BNXT_ULP_CLASS_HID_48fa7] = 594, + [BNXT_ULP_CLASS_HID_58fab] = 595, + [BNXT_ULP_CLASS_HID_59f27] = 596, + [BNXT_ULP_CLASS_HID_4032f] = 597, + [BNXT_ULP_CLASS_HID_4132b] = 598, + [BNXT_ULP_CLASS_HID_5132f] = 599, + [BNXT_ULP_CLASS_HID_50225] = 600, + [BNXT_ULP_CLASS_HID_48b27] = 601, + [BNXT_ULP_CLASS_HID_49b23] = 602, + [BNXT_ULP_CLASS_HID_59b27] = 603, + [BNXT_ULP_CLASS_HID_58a2d] = 604, + [BNXT_ULP_CLASS_HID_10437] = 605, + [BNXT_ULP_CLASS_HID_11017] = 606, + [BNXT_ULP_CLASS_HID_1402b] = 607, + [BNXT_ULP_CLASS_HID_15c0b] = 608, + [BNXT_ULP_CLASS_HID_12639] = 609, + [BNXT_ULP_CLASS_HID_13219] = 610, + [BNXT_ULP_CLASS_HID_16ddd] = 611, + [BNXT_ULP_CLASS_HID_17e3d] = 612, + [BNXT_ULP_CLASS_HID_11333] = 613, + [BNXT_ULP_CLASS_HID_10ef5] = 614, + [BNXT_ULP_CLASS_HID_15f37] = 615, + [BNXT_ULP_CLASS_HID_14ae9] = 616, + [BNXT_ULP_CLASS_HID_13d25] = 617, + [BNXT_ULP_CLASS_HID_128e7] = 618, + [BNXT_ULP_CLASS_HID_17939] = 619, + [BNXT_ULP_CLASS_HID_174fb] = 620, + [BNXT_ULP_CLASS_HID_10985] = 621, + [BNXT_ULP_CLASS_HID_10547] = 622, + [BNXT_ULP_CLASS_HID_155a9] = 623, + [BNXT_ULP_CLASS_HID_1416b] = 624, + [BNXT_ULP_CLASS_HID_12ba7] = 625, + [BNXT_ULP_CLASS_HID_12749] = 626, + [BNXT_ULP_CLASS_HID_177ab] = 627, + [BNXT_ULP_CLASS_HID_1636d] = 628, + [BNXT_ULP_CLASS_HID_10463] = 629, + [BNXT_ULP_CLASS_HID_110a3] = 630, + [BNXT_ULP_CLASS_HID_14067] = 631, + [BNXT_ULP_CLASS_HID_15c67] = 632, + [BNXT_ULP_CLASS_HID_12665] = 633, + [BNXT_ULP_CLASS_HID_13265] = 634, + [BNXT_ULP_CLASS_HID_16269] = 635, + [BNXT_ULP_CLASS_HID_17e69] = 636, + [BNXT_ULP_CLASS_HID_1133d] = 637, + [BNXT_ULP_CLASS_HID_10eff] = 638, + [BNXT_ULP_CLASS_HID_15ed9] = 639, + [BNXT_ULP_CLASS_HID_14a9b] = 640, + [BNXT_ULP_CLASS_HID_13d2f] = 641, + [BNXT_ULP_CLASS_HID_128e9] = 642, + [BNXT_ULP_CLASS_HID_178cb] = 643, + [BNXT_ULP_CLASS_HID_1748d] = 644, + [BNXT_ULP_CLASS_HID_109fb] = 645, + [BNXT_ULP_CLASS_HID_105bd] = 646, + [BNXT_ULP_CLASS_HID_155bf] = 647, + [BNXT_ULP_CLASS_HID_14179] = 648, + [BNXT_ULP_CLASS_HID_12bed] = 649, + [BNXT_ULP_CLASS_HID_127af] = 650, + [BNXT_ULP_CLASS_HID_177a9] = 651, + [BNXT_ULP_CLASS_HID_1636b] = 652, + [BNXT_ULP_CLASS_HID_1046d] = 653, + [BNXT_ULP_CLASS_HID_1104d] = 654, + [BNXT_ULP_CLASS_HID_14009] = 655, + [BNXT_ULP_CLASS_HID_15c69] = 656, + [BNXT_ULP_CLASS_HID_1260f] = 657, + [BNXT_ULP_CLASS_HID_1326f] = 658, + [BNXT_ULP_CLASS_HID_1622b] = 659, + [BNXT_ULP_CLASS_HID_17e0b] = 660, + [BNXT_ULP_CLASS_HID_11369] = 661, + [BNXT_ULP_CLASS_HID_10f2b] = 662, + [BNXT_ULP_CLASS_HID_15f6d] = 663, + [BNXT_ULP_CLASS_HID_14b2f] = 664, + [BNXT_ULP_CLASS_HID_13d6b] = 665, + [BNXT_ULP_CLASS_HID_1292d] = 666, + [BNXT_ULP_CLASS_HID_1792f] = 667, + [BNXT_ULP_CLASS_HID_174e9] = 668, + [BNXT_ULP_CLASS_HID_119e1] = 669, + [BNXT_ULP_CLASS_HID_115a3] = 670, + [BNXT_ULP_CLASS_HID_14563] = 671, + [BNXT_ULP_CLASS_HID_15143] = 672, + [BNXT_ULP_CLASS_HID_13b93] = 673, + [BNXT_ULP_CLASS_HID_13751] = 674, + [BNXT_ULP_CLASS_HID_16769] = 675, + [BNXT_ULP_CLASS_HID_17349] = 676, + [BNXT_ULP_CLASS_HID_114ab] = 677, + [BNXT_ULP_CLASS_HID_10061] = 678, + [BNXT_ULP_CLASS_HID_15063] = 679, + [BNXT_ULP_CLASS_HID_14c21] = 680, + [BNXT_ULP_CLASS_HID_13671] = 681, + [BNXT_ULP_CLASS_HID_12233] = 682, + [BNXT_ULP_CLASS_HID_17271] = 683, + [BNXT_ULP_CLASS_HID_16e33] = 684, + [BNXT_ULP_CLASS_HID_102c1] = 685, + [BNXT_ULP_CLASS_HID_11f21] = 686, + [BNXT_ULP_CLASS_HID_14ee1] = 687, + [BNXT_ULP_CLASS_HID_15ac1] = 688, + [BNXT_ULP_CLASS_HID_12cc3] = 689, + [BNXT_ULP_CLASS_HID_13923] = 690, + [BNXT_ULP_CLASS_HID_168e3] = 691, + [BNXT_ULP_CLASS_HID_164a9] = 692, + [BNXT_ULP_CLASS_HID_11e29] = 693, + [BNXT_ULP_CLASS_HID_115eb] = 694, + [BNXT_ULP_CLASS_HID_145a3] = 695, + [BNXT_ULP_CLASS_HID_151a3] = 696, + [BNXT_ULP_CLASS_HID_1382b] = 697, + [BNXT_ULP_CLASS_HID_137e1] = 698, + [BNXT_ULP_CLASS_HID_167a1] = 699, + [BNXT_ULP_CLASS_HID_173a1] = 700, + [BNXT_ULP_CLASS_HID_11449] = 701, + [BNXT_ULP_CLASS_HID_1000b] = 702, + [BNXT_ULP_CLASS_HID_15069] = 703, + [BNXT_ULP_CLASS_HID_14c2b] = 704, + [BNXT_ULP_CLASS_HID_1367b] = 705, + [BNXT_ULP_CLASS_HID_12239] = 706, + [BNXT_ULP_CLASS_HID_1721b] = 707, + [BNXT_ULP_CLASS_HID_169d9] = 708, + [BNXT_ULP_CLASS_HID_1033b] = 709, + [BNXT_ULP_CLASS_HID_11f3b] = 710, + [BNXT_ULP_CLASS_HID_14f2b] = 711, + [BNXT_ULP_CLASS_HID_15b2b] = 712, + [BNXT_ULP_CLASS_HID_12d39] = 713, + [BNXT_ULP_CLASS_HID_13939] = 714, + [BNXT_ULP_CLASS_HID_168f9] = 715, + [BNXT_ULP_CLASS_HID_164bb] = 716, + [BNXT_ULP_CLASS_HID_119cb] = 717, + [BNXT_ULP_CLASS_HID_11589] = 718, + [BNXT_ULP_CLASS_HID_14549] = 719, + [BNXT_ULP_CLASS_HID_151a9] = 720, + [BNXT_ULP_CLASS_HID_13bc9] = 721, + [BNXT_ULP_CLASS_HID_1378b] = 722, + [BNXT_ULP_CLASS_HID_1674b] = 723, + [BNXT_ULP_CLASS_HID_173ab] = 724, + [BNXT_ULP_CLASS_HID_114a9] = 725, + [BNXT_ULP_CLASS_HID_1006b] = 726, + [BNXT_ULP_CLASS_HID_150a9] = 727, + [BNXT_ULP_CLASS_HID_14c6b] = 728, + [BNXT_ULP_CLASS_HID_136ab] = 729, + [BNXT_ULP_CLASS_HID_12269] = 730, + [BNXT_ULP_CLASS_HID_172ab] = 731, + [BNXT_ULP_CLASS_HID_16e69] = 732, + [BNXT_ULP_CLASS_HID_402d2] = 733, + [BNXT_ULP_CLASS_HID_412ee] = 734, + [BNXT_ULP_CLASS_HID_512a2] = 735, + [BNXT_ULP_CLASS_HID_50dd8] = 736, + [BNXT_ULP_CLASS_HID_48aea] = 737, + [BNXT_ULP_CLASS_HID_48500] = 738, + [BNXT_ULP_CLASS_HID_585d4] = 739, + [BNXT_ULP_CLASS_HID_59590] = 740, + [BNXT_ULP_CLASS_HID_41936] = 741, + [BNXT_ULP_CLASS_HID_409ac] = 742, + [BNXT_ULP_CLASS_HID_50860] = 743, + [BNXT_ULP_CLASS_HID_5183c] = 744, + [BNXT_ULP_CLASS_HID_481a8] = 745, + [BNXT_ULP_CLASS_HID_49064] = 746, + [BNXT_ULP_CLASS_HID_59038] = 747, + [BNXT_ULP_CLASS_HID_58376] = 748, + [BNXT_ULP_CLASS_HID_414a0] = 749, + [BNXT_ULP_CLASS_HID_407ce] = 750, + [BNXT_ULP_CLASS_HID_50782] = 751, + [BNXT_ULP_CLASS_HID_517ae] = 752, + [BNXT_ULP_CLASS_HID_49f68] = 753, + [BNXT_ULP_CLASS_HID_48f86] = 754, + [BNXT_ULP_CLASS_HID_58faa] = 755, + [BNXT_ULP_CLASS_HID_59e66] = 756, + [BNXT_ULP_CLASS_HID_40266] = 757, + [BNXT_ULP_CLASS_HID_41222] = 758, + [BNXT_ULP_CLASS_HID_512e6] = 759, + [BNXT_ULP_CLASS_HID_50d6c] = 760, + [BNXT_ULP_CLASS_HID_48a2e] = 761, + [BNXT_ULP_CLASS_HID_48564] = 762, + [BNXT_ULP_CLASS_HID_58568] = 763, + [BNXT_ULP_CLASS_HID_59524] = 764, + [BNXT_ULP_CLASS_HID_419d8] = 765, + [BNXT_ULP_CLASS_HID_4087e] = 766, + [BNXT_ULP_CLASS_HID_5080a] = 767, + [BNXT_ULP_CLASS_HID_518ce] = 768, + [BNXT_ULP_CLASS_HID_4807a] = 769, + [BNXT_ULP_CLASS_HID_4900e] = 770, + [BNXT_ULP_CLASS_HID_590ca] = 771, + [BNXT_ULP_CLASS_HID_58378] = 772, + [BNXT_ULP_CLASS_HID_414be] = 773, + [BNXT_ULP_CLASS_HID_4073c] = 774, + [BNXT_ULP_CLASS_HID_507e8] = 775, + [BNXT_ULP_CLASS_HID_517ac] = 776, + [BNXT_ULP_CLASS_HID_49f7e] = 777, + [BNXT_ULP_CLASS_HID_48fec] = 778, + [BNXT_ULP_CLASS_HID_58fa8] = 779, + [BNXT_ULP_CLASS_HID_59e7c] = 780, + [BNXT_ULP_CLASS_HID_40208] = 781, + [BNXT_ULP_CLASS_HID_412cc] = 782, + [BNXT_ULP_CLASS_HID_51288] = 783, + [BNXT_ULP_CLASS_HID_50d2e] = 784, + [BNXT_ULP_CLASS_HID_48ac8] = 785, + [BNXT_ULP_CLASS_HID_4856e] = 786, + [BNXT_ULP_CLASS_HID_5852a] = 787, + [BNXT_ULP_CLASS_HID_595ce] = 788, + [BNXT_ULP_CLASS_HID_4196c] = 789, + [BNXT_ULP_CLASS_HID_409aa] = 790, + [BNXT_ULP_CLASS_HID_5086e] = 791, + [BNXT_ULP_CLASS_HID_5182a] = 792, + [BNXT_ULP_CLASS_HID_481ae] = 793, + [BNXT_ULP_CLASS_HID_4906a] = 794, + [BNXT_ULP_CLASS_HID_5902e] = 795, + [BNXT_ULP_CLASS_HID_580ac] = 796, + [BNXT_ULP_CLASS_HID_40766] = 797, + [BNXT_ULP_CLASS_HID_41726] = 798, + [BNXT_ULP_CLASS_HID_517f6] = 799, + [BNXT_ULP_CLASS_HID_5066c] = 800, + [BNXT_ULP_CLASS_HID_48f3e] = 801, + [BNXT_ULP_CLASS_HID_49ffe] = 802, + [BNXT_ULP_CLASS_HID_59f8e] = 803, + [BNXT_ULP_CLASS_HID_58e24] = 804, + [BNXT_ULP_CLASS_HID_4126e] = 805, + [BNXT_ULP_CLASS_HID_402e4] = 806, + [BNXT_ULP_CLASS_HID_502b4] = 807, + [BNXT_ULP_CLASS_HID_51d74] = 808, + [BNXT_ULP_CLASS_HID_49a26] = 809, + [BNXT_ULP_CLASS_HID_48abc] = 810, + [BNXT_ULP_CLASS_HID_5956c] = 811, + [BNXT_ULP_CLASS_HID_585ee] = 812, + [BNXT_ULP_CLASS_HID_409e4] = 813, + [BNXT_ULP_CLASS_HID_419a4] = 814, + [BNXT_ULP_CLASS_HID_51844] = 815, + [BNXT_ULP_CLASS_HID_508e6] = 816, + [BNXT_ULP_CLASS_HID_4918c] = 817, + [BNXT_ULP_CLASS_HID_4802e] = 818, + [BNXT_ULP_CLASS_HID_580ee] = 819, + [BNXT_ULP_CLASS_HID_590ae] = 820, + [BNXT_ULP_CLASS_HID_404ae] = 821, + [BNXT_ULP_CLASS_HID_41766] = 822, + [BNXT_ULP_CLASS_HID_5172e] = 823, + [BNXT_ULP_CLASS_HID_507a4] = 824, + [BNXT_ULP_CLASS_HID_48f66] = 825, + [BNXT_ULP_CLASS_HID_49f2e] = 826, + [BNXT_ULP_CLASS_HID_59fe6] = 827, + [BNXT_ULP_CLASS_HID_58e6c] = 828, + [BNXT_ULP_CLASS_HID_4126c] = 829, + [BNXT_ULP_CLASS_HID_4028e] = 830, + [BNXT_ULP_CLASS_HID_50d5e] = 831, + [BNXT_ULP_CLASS_HID_51d1e] = 832, + [BNXT_ULP_CLASS_HID_49a2c] = 833, + [BNXT_ULP_CLASS_HID_4954e] = 834, + [BNXT_ULP_CLASS_HID_5951e] = 835, + [BNXT_ULP_CLASS_HID_5858c] = 836, + [BNXT_ULP_CLASS_HID_409fe] = 837, + [BNXT_ULP_CLASS_HID_419ee] = 838, + [BNXT_ULP_CLASS_HID_519ae] = 839, + [BNXT_ULP_CLASS_HID_508fc] = 840, + [BNXT_ULP_CLASS_HID_491ee] = 841, + [BNXT_ULP_CLASS_HID_4802c] = 842, + [BNXT_ULP_CLASS_HID_580fc] = 843, + [BNXT_ULP_CLASS_HID_590bc] = 844, + [BNXT_ULP_CLASS_HID_4074c] = 845, + [BNXT_ULP_CLASS_HID_4170c] = 846, + [BNXT_ULP_CLASS_HID_5172c] = 847, + [BNXT_ULP_CLASS_HID_5064e] = 848, + [BNXT_ULP_CLASS_HID_48f0c] = 849, + [BNXT_ULP_CLASS_HID_49fcc] = 850, + [BNXT_ULP_CLASS_HID_59fec] = 851, + [BNXT_ULP_CLASS_HID_58e0e] = 852, + [BNXT_ULP_CLASS_HID_413ac] = 853, + [BNXT_ULP_CLASS_HID_402ee] = 854, + [BNXT_ULP_CLASS_HID_502ae] = 855, + [BNXT_ULP_CLASS_HID_512ae] = 856, + [BNXT_ULP_CLASS_HID_49a6c] = 857, + [BNXT_ULP_CLASS_HID_48aae] = 858, + [BNXT_ULP_CLASS_HID_58aae] = 859, + [BNXT_ULP_CLASS_HID_585ec] = 860, + [BNXT_ULP_CLASS_HID_104ae] = 861, + [BNXT_ULP_CLASS_HID_1108e] = 862, + [BNXT_ULP_CLASS_HID_140b2] = 863, + [BNXT_ULP_CLASS_HID_15c92] = 864, + [BNXT_ULP_CLASS_HID_126a0] = 865, + [BNXT_ULP_CLASS_HID_13280] = 866, + [BNXT_ULP_CLASS_HID_16d44] = 867, + [BNXT_ULP_CLASS_HID_17ea4] = 868, + [BNXT_ULP_CLASS_HID_113a4] = 869, + [BNXT_ULP_CLASS_HID_10e66] = 870, + [BNXT_ULP_CLASS_HID_15e40] = 871, + [BNXT_ULP_CLASS_HID_14a02] = 872, + [BNXT_ULP_CLASS_HID_13db6] = 873, + [BNXT_ULP_CLASS_HID_12870] = 874, + [BNXT_ULP_CLASS_HID_17852] = 875, + [BNXT_ULP_CLASS_HID_17414] = 876, + [BNXT_ULP_CLASS_HID_11978] = 877, + [BNXT_ULP_CLASS_HID_1153a] = 878, + [BNXT_ULP_CLASS_HID_145fa] = 879, + [BNXT_ULP_CLASS_HID_151da] = 880, + [BNXT_ULP_CLASS_HID_13b0a] = 881, + [BNXT_ULP_CLASS_HID_137c8] = 882, + [BNXT_ULP_CLASS_HID_167f0] = 883, + [BNXT_ULP_CLASS_HID_173d0] = 884, + [BNXT_ULP_CLASS_HID_114d0] = 885, + [BNXT_ULP_CLASS_HID_10092] = 886, + [BNXT_ULP_CLASS_HID_150f0] = 887, + [BNXT_ULP_CLASS_HID_14cb2] = 888, + [BNXT_ULP_CLASS_HID_136e2] = 889, + [BNXT_ULP_CLASS_HID_122a0] = 890, + [BNXT_ULP_CLASS_HID_17282] = 891, + [BNXT_ULP_CLASS_HID_16940] = 892, + [BNXT_ULP_CLASS_HID_11b90] = 893, + [BNXT_ULP_CLASS_HID_11654] = 894, + [BNXT_ULP_CLASS_HID_14618] = 895, + [BNXT_ULP_CLASS_HID_15278] = 896, + [BNXT_ULP_CLASS_HID_12404] = 897, + [BNXT_ULP_CLASS_HID_13064] = 898, + [BNXT_ULP_CLASS_HID_16028] = 899, + [BNXT_ULP_CLASS_HID_17c08] = 900, + [BNXT_ULP_CLASS_HID_11100] = 901, + [BNXT_ULP_CLASS_HID_10dc4] = 902, + [BNXT_ULP_CLASS_HID_15d24] = 903, + [BNXT_ULP_CLASS_HID_149d0] = 904, + [BNXT_ULP_CLASS_HID_13314] = 905, + [BNXT_ULP_CLASS_HID_12fd4] = 906, + [BNXT_ULP_CLASS_HID_17f20] = 907, + [BNXT_ULP_CLASS_HID_16be0] = 908, + [BNXT_ULP_CLASS_HID_11cd8] = 909, + [BNXT_ULP_CLASS_HID_10880] = 910, + [BNXT_ULP_CLASS_HID_158e0] = 911, + [BNXT_ULP_CLASS_HID_154a0] = 912, + [BNXT_ULP_CLASS_HID_13ed0] = 913, + [BNXT_ULP_CLASS_HID_12a90] = 914, + [BNXT_ULP_CLASS_HID_16550] = 915, + [BNXT_ULP_CLASS_HID_176b0] = 916, + [BNXT_ULP_CLASS_HID_10bb0] = 917, + [BNXT_ULP_CLASS_HID_10670] = 918, + [BNXT_ULP_CLASS_HID_15650] = 919, + [BNXT_ULP_CLASS_HID_14210] = 920, + [BNXT_ULP_CLASS_HID_13440] = 921, + [BNXT_ULP_CLASS_HID_12000] = 922, + [BNXT_ULP_CLASS_HID_17060] = 923, + [BNXT_ULP_CLASS_HID_16c20] = 924, + [BNXT_ULP_CLASS_HID_11511] = 925, + [BNXT_ULP_CLASS_HID_101d3] = 926, + [BNXT_ULP_CLASS_HID_15135] = 927, + [BNXT_ULP_CLASS_HID_14df7] = 928, + [BNXT_ULP_CLASS_HID_13723] = 929, + [BNXT_ULP_CLASS_HID_123e5] = 930, + [BNXT_ULP_CLASS_HID_173c7] = 931, + [BNXT_ULP_CLASS_HID_16f89] = 932, + [BNXT_ULP_CLASS_HID_10081] = 933, + [BNXT_ULP_CLASS_HID_11ce1] = 934, + [BNXT_ULP_CLASS_HID_14ca5] = 935, + [BNXT_ULP_CLASS_HID_15885] = 936, + [BNXT_ULP_CLASS_HID_12293] = 937, + [BNXT_ULP_CLASS_HID_13ef3] = 938, + [BNXT_ULP_CLASS_HID_16eb7] = 939, + [BNXT_ULP_CLASS_HID_16561] = 940, + [BNXT_ULP_CLASS_HID_10e59] = 941, + [BNXT_ULP_CLASS_HID_11bb9] = 942, + [BNXT_ULP_CLASS_HID_14a61] = 943, + [BNXT_ULP_CLASS_HID_14623] = 944, + [BNXT_ULP_CLASS_HID_1286b] = 945, + [BNXT_ULP_CLASS_HID_12411] = 946, + [BNXT_ULP_CLASS_HID_17473] = 947, + [BNXT_ULP_CLASS_HID_16031] = 948, + [BNXT_ULP_CLASS_HID_10531] = 949, + [BNXT_ULP_CLASS_HID_11111] = 950, + [BNXT_ULP_CLASS_HID_141d1] = 951, + [BNXT_ULP_CLASS_HID_15d31] = 952, + [BNXT_ULP_CLASS_HID_127c3] = 953, + [BNXT_ULP_CLASS_HID_13323] = 954, + [BNXT_ULP_CLASS_HID_163e3] = 955, + [BNXT_ULP_CLASS_HID_17fc3] = 956, + [BNXT_ULP_CLASS_HID_108f5] = 957, + [BNXT_ULP_CLASS_HID_104b9] = 958, + [BNXT_ULP_CLASS_HID_15499] = 959, + [BNXT_ULP_CLASS_HID_1435d] = 960, + [BNXT_ULP_CLASS_HID_12a89] = 961, + [BNXT_ULP_CLASS_HID_12149] = 962, + [BNXT_ULP_CLASS_HID_176ad] = 963, + [BNXT_ULP_CLASS_HID_16d6d] = 964, + [BNXT_ULP_CLASS_HID_10665] = 965, + [BNXT_ULP_CLASS_HID_11245] = 966, + [BNXT_ULP_CLASS_HID_14271] = 967, + [BNXT_ULP_CLASS_HID_15e51] = 968, + [BNXT_ULP_CLASS_HID_12061] = 969, + [BNXT_ULP_CLASS_HID_13c41] = 970, + [BNXT_ULP_CLASS_HID_16c05] = 971, + [BNXT_ULP_CLASS_HID_17865] = 972, + [BNXT_ULP_CLASS_HID_10d21] = 973, + [BNXT_ULP_CLASS_HID_11901] = 974, + [BNXT_ULP_CLASS_HID_149c1] = 975, + [BNXT_ULP_CLASS_HID_14589] = 976, + [BNXT_ULP_CLASS_HID_12f31] = 977, + [BNXT_ULP_CLASS_HID_13b11] = 978, + [BNXT_ULP_CLASS_HID_16bd9] = 979, + [BNXT_ULP_CLASS_HID_16799] = 980, + [BNXT_ULP_CLASS_HID_11831] = 981, + [BNXT_ULP_CLASS_HID_114f1] = 982, + [BNXT_ULP_CLASS_HID_144b1] = 983, + [BNXT_ULP_CLASS_HID_15091] = 984, + [BNXT_ULP_CLASS_HID_13ac1] = 985, + [BNXT_ULP_CLASS_HID_13681] = 986, + [BNXT_ULP_CLASS_HID_166b1] = 987, + [BNXT_ULP_CLASS_HID_17291] = 988, + [BNXT_ULP_CLASS_HID_4007d] = 989, + [BNXT_ULP_CLASS_HID_41041] = 990, + [BNXT_ULP_CLASS_HID_5100d] = 991, + [BNXT_ULP_CLASS_HID_50f77] = 992, + [BNXT_ULP_CLASS_HID_48845] = 993, + [BNXT_ULP_CLASS_HID_487af] = 994, + [BNXT_ULP_CLASS_HID_5877b] = 995, + [BNXT_ULP_CLASS_HID_5973f] = 996, + [BNXT_ULP_CLASS_HID_41c31] = 997, + [BNXT_ULP_CLASS_HID_40b1b] = 998, + [BNXT_ULP_CLASS_HID_50b67] = 999, + [BNXT_ULP_CLASS_HID_51b2b] = 1000, + [BNXT_ULP_CLASS_HID_4831f] = 1001, + [BNXT_ULP_CLASS_HID_49363] = 1002, + [BNXT_ULP_CLASS_HID_5932f] = 1003, + [BNXT_ULP_CLASS_HID_58211] = 1004, + [BNXT_ULP_CLASS_HID_4161b] = 1005, + [BNXT_ULP_CLASS_HID_405bd] = 1006, + [BNXT_ULP_CLASS_HID_50589] = 1007, + [BNXT_ULP_CLASS_HID_5150d] = 1008, + [BNXT_ULP_CLASS_HID_49e23] = 1009, + [BNXT_ULP_CLASS_HID_48d85] = 1010, + [BNXT_ULP_CLASS_HID_58d11] = 1011, + [BNXT_ULP_CLASS_HID_59d15] = 1012, + [BNXT_ULP_CLASS_HID_4012d] = 1013, + [BNXT_ULP_CLASS_HID_41131] = 1014, + [BNXT_ULP_CLASS_HID_5113d] = 1015, + [BNXT_ULP_CLASS_HID_50027] = 1016, + [BNXT_ULP_CLASS_HID_48935] = 1017, + [BNXT_ULP_CLASS_HID_49939] = 1018, + [BNXT_ULP_CLASS_HID_59905] = 1019, + [BNXT_ULP_CLASS_HID_5882f] = 1020, + [BNXT_ULP_CLASS_HID_41b99] = 1021, + [BNXT_ULP_CLASS_HID_40b03] = 1022, + [BNXT_ULP_CLASS_HID_50acf] = 1023, + [BNXT_ULP_CLASS_HID_51a93] = 1024, + [BNXT_ULP_CLASS_HID_48307] = 1025, + [BNXT_ULP_CLASS_HID_492cb] = 1026, + [BNXT_ULP_CLASS_HID_59297] = 1027, + [BNXT_ULP_CLASS_HID_581d9] = 1028, + [BNXT_ULP_CLASS_HID_41653] = 1029, + [BNXT_ULP_CLASS_HID_40655] = 1030, + [BNXT_ULP_CLASS_HID_50601] = 1031, + [BNXT_ULP_CLASS_HID_51545] = 1032, + [BNXT_ULP_CLASS_HID_49e1b] = 1033, + [BNXT_ULP_CLASS_HID_48e1d] = 1034, + [BNXT_ULP_CLASS_HID_58d49] = 1035, + [BNXT_ULP_CLASS_HID_59d0d] = 1036, + [BNXT_ULP_CLASS_HID_40115] = 1037, + [BNXT_ULP_CLASS_HID_41099] = 1038, + [BNXT_ULP_CLASS_HID_51085] = 1039, + [BNXT_ULP_CLASS_HID_5000f] = 1040, + [BNXT_ULP_CLASS_HID_4889d] = 1041, + [BNXT_ULP_CLASS_HID_49881] = 1042, + [BNXT_ULP_CLASS_HID_5980d] = 1043, + [BNXT_ULP_CLASS_HID_59797] = 1044, + [BNXT_ULP_CLASS_HID_41c09] = 1045, + [BNXT_ULP_CLASS_HID_40c13] = 1046, + [BNXT_ULP_CLASS_HID_50b1f] = 1047, + [BNXT_ULP_CLASS_HID_51b03] = 1048, + [BNXT_ULP_CLASS_HID_48417] = 1049, + [BNXT_ULP_CLASS_HID_4931b] = 1050, + [BNXT_ULP_CLASS_HID_59307] = 1051, + [BNXT_ULP_CLASS_HID_58309] = 1052, + [BNXT_ULP_CLASS_HID_4160f] = 1053, + [BNXT_ULP_CLASS_HID_40561] = 1054, + [BNXT_ULP_CLASS_HID_5052d] = 1055, + [BNXT_ULP_CLASS_HID_51501] = 1056, + [BNXT_ULP_CLASS_HID_49dc7] = 1057, + [BNXT_ULP_CLASS_HID_48d29] = 1058, + [BNXT_ULP_CLASS_HID_58d05] = 1059, + [BNXT_ULP_CLASS_HID_59cc9] = 1060, + [BNXT_ULP_CLASS_HID_4