From patchwork Thu Feb 16 00:29:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Mingxia" X-Patchwork-Id: 124005 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6BA6A41CA9; Thu, 16 Feb 2023 02:27:55 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 309E34161A; Thu, 16 Feb 2023 02:27:53 +0100 (CET) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id A93354113F for ; Thu, 16 Feb 2023 02:27:50 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676510870; x=1708046870; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=q+5r01iNR/xzSzhjABz8D4gtKt7y416gRXRWHYOQOjc=; b=dmqlFKLINaBVU68S8Yif5aH3HFvMsRE9aBz6yugA+VibSnYl8c7X5NHS aH/mJjCt2REOIoOWfA7xz6kqZiUJTv/hOccDQG9uhwHNyWgco9ssundne SzRjJPr8lZU52QCgGmCnfToeYAB94+RSQLzobr4Pp62DUhGwk/gX4mDeb yCc/iK2W50kFxaOj4ZtGNShi2s7UK/wsIcX7QLZENJRolZP0x9IKVQ7yi tn2vWdGtK0t85UgPXs6LhnwBkjCnburcVLYgOHCfQ0lgR2OyPIGT4MzM3 2Nw1Rs6FqLxAQXjRxyeXv4FS8k/Xu2StCsq6VzVh77YyWy52RJ16ar3gI A==; X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="329315344" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="329315344" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2023 17:27:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="779166177" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="779166177" Received: from dpdk-mingxial-01.sh.intel.com ([10.67.119.167]) by fmsmga002.fm.intel.com with ESMTP; 15 Feb 2023 17:27:48 -0800 From: Mingxia Liu To: dev@dpdk.org, beilei.xing@intel.com, yuying.zhang@intel.com Cc: Mingxia Liu Subject: [PATCH v7 01/21] net/cpfl: support device initialization Date: Thu, 16 Feb 2023 00:29:50 +0000 Message-Id: <20230216003010.3439881-2-mingxia.liu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230216003010.3439881-1-mingxia.liu@intel.com> References: <20230213021956.2953088-1-mingxia.liu@intel.com> <20230216003010.3439881-1-mingxia.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Support device init and add the following dev ops: - dev_configure - dev_close - dev_infos_get - link_update - dev_supported_ptypes_get Signed-off-by: Mingxia Liu --- MAINTAINERS | 8 + doc/guides/nics/cpfl.rst | 66 +++ doc/guides/nics/features/cpfl.ini | 12 + doc/guides/rel_notes/release_23_03.rst | 6 + drivers/net/cpfl/cpfl_ethdev.c | 768 +++++++++++++++++++++++++ drivers/net/cpfl/cpfl_ethdev.h | 78 +++ drivers/net/cpfl/cpfl_logs.h | 32 ++ drivers/net/cpfl/cpfl_rxtx.c | 244 ++++++++ drivers/net/cpfl/cpfl_rxtx.h | 25 + drivers/net/cpfl/meson.build | 14 + drivers/net/meson.build | 1 + 11 files changed, 1254 insertions(+) create mode 100644 doc/guides/nics/cpfl.rst create mode 100644 doc/guides/nics/features/cpfl.ini create mode 100644 drivers/net/cpfl/cpfl_ethdev.c create mode 100644 drivers/net/cpfl/cpfl_ethdev.h create mode 100644 drivers/net/cpfl/cpfl_logs.h create mode 100644 drivers/net/cpfl/cpfl_rxtx.c create mode 100644 drivers/net/cpfl/cpfl_rxtx.h create mode 100644 drivers/net/cpfl/meson.build diff --git a/MAINTAINERS b/MAINTAINERS index 9a0f416d2e..af80edaf6e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -783,6 +783,14 @@ F: drivers/common/idpf/ F: doc/guides/nics/idpf.rst F: doc/guides/nics/features/idpf.ini +Intel cpfl +M: Yuying Zhang +M: Beilei Xing +T: git://dpdk.org/next/dpdk-next-net-intel +F: drivers/net/cpfl/ +F: doc/guides/nics/cpfl.rst +F: doc/guides/nics/features/cpfl.ini + Intel igc M: Junfeng Guo M: Simei Su diff --git a/doc/guides/nics/cpfl.rst b/doc/guides/nics/cpfl.rst new file mode 100644 index 0000000000..7c5aff0789 --- /dev/null +++ b/doc/guides/nics/cpfl.rst @@ -0,0 +1,66 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(c) 2022 Intel Corporation. + +.. include:: + +CPFL Poll Mode Driver +===================== + +The [*EXPERIMENTAL*] cpfl PMD (**librte_net_cpfl**) provides poll mode driver support +for Intel\ |reg| Infrastructure Processing Unit (Intel\ |reg| IPU) E2100. + + +Linux Prerequisites +------------------- + +Follow the DPDK :doc:`../linux_gsg/index` to setup the basic DPDK environment. + +To get better performance on Intel platforms, +please follow the :doc:`../linux_gsg/nic_perf_intel_platform`. + + +Pre-Installation Configuration +------------------------------ + +Runtime Config Options +~~~~~~~~~~~~~~~~~~~~~~ + +- ``vport`` (default ``0``) + + The PMD supports creation of multiple vports for one PCI device, + each vport corresponds to a single ethdev. + The user can specify the vports with specific ID to be created, for example:: + + -a ca:00.0,vport=[0,2,3] + + Then the PMD will create 3 vports (ethdevs) for device ``ca:00.0``. + + If the parameter is not provided, the vport 0 will be created by default. + +- ``rx_single`` (default ``0``) + + There are two queue modes supported by Intel\ |reg| IPU Ethernet E2100 Series, + single queue mode and split queue mode for Rx queue. + User can choose Rx queue mode, example:: + + -a ca:00.0,rx_single=1 + + Then the PMD will configure Rx queue with single queue mode. + Otherwise, split queue mode is chosen by default. + +- ``tx_single`` (default ``0``) + + There are two queue modes supported by Intel\ |reg| IPU Ethernet E2100 Series, + single queue mode and split queue mode for Tx queue. + User can choose Tx queue mode, example:: + + -a ca:00.0,tx_single=1 + + Then the PMD will configure Tx queue with single queue mode. + Otherwise, split queue mode is chosen by default. + + +Driver compilation and testing +------------------------------ + +Refer to the document :doc:`build_and_test` for details. \ No newline at end of file diff --git a/doc/guides/nics/features/cpfl.ini b/doc/guides/nics/features/cpfl.ini new file mode 100644 index 0000000000..a2d1ca9e15 --- /dev/null +++ b/doc/guides/nics/features/cpfl.ini @@ -0,0 +1,12 @@ +; +; Supported features of the 'cpfl' network poll mode driver. +; +; Refer to default.ini for the full list of available PMD features. +; +; A feature with "P" indicates only be supported when non-vector path +; is selected. +; +[Features] +Linux = Y +x86-32 = Y +x86-64 = Y diff --git a/doc/guides/rel_notes/release_23_03.rst b/doc/guides/rel_notes/release_23_03.rst index 07914170a7..b0b23d1a44 100644 --- a/doc/guides/rel_notes/release_23_03.rst +++ b/doc/guides/rel_notes/release_23_03.rst @@ -88,6 +88,12 @@ New Features * Added timesync API support. * Added packet pacing(launch time offloading) support. +* **Added Intel cpfl driver.** + + Added the new ``cpfl`` net driver + for Intel\ |reg| Infrastructure Processing Unit (Intel\ |reg| IPU) E2100. + See the :doc:`../nics/cpfl` NIC guide for more details on this new driver. + Removed Items ------------- diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c new file mode 100644 index 0000000000..fe0061133c --- /dev/null +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -0,0 +1,768 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Intel Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cpfl_ethdev.h" + +#define CPFL_TX_SINGLE_Q "tx_single" +#define CPFL_RX_SINGLE_Q "rx_single" +#define CPFL_VPORT "vport" + +rte_spinlock_t cpfl_adapter_lock; +/* A list for all adapters, one adapter matches one PCI device */ +struct cpfl_adapter_list cpfl_adapter_list; +bool cpfl_adapter_list_init; + +static const char * const cpfl_valid_args[] = { + CPFL_TX_SINGLE_Q, + CPFL_RX_SINGLE_Q, + CPFL_VPORT, + NULL +}; + +static int +cpfl_dev_link_update(struct rte_eth_dev *dev, + __rte_unused int wait_to_complete) +{ + struct idpf_vport *vport = dev->data->dev_private; + struct rte_eth_link new_link; + + memset(&new_link, 0, sizeof(new_link)); + + switch (vport->link_speed) { + case RTE_ETH_SPEED_NUM_10M: + new_link.link_speed = RTE_ETH_SPEED_NUM_10M; + break; + case RTE_ETH_SPEED_NUM_100M: + new_link.link_speed = RTE_ETH_SPEED_NUM_100M; + break; + case RTE_ETH_SPEED_NUM_1G: + new_link.link_speed = RTE_ETH_SPEED_NUM_1G; + break; + case RTE_ETH_SPEED_NUM_10G: + new_link.link_speed = RTE_ETH_SPEED_NUM_10G; + break; + case RTE_ETH_SPEED_NUM_20G: + new_link.link_speed = RTE_ETH_SPEED_NUM_20G; + break; + case RTE_ETH_SPEED_NUM_25G: + new_link.link_speed = RTE_ETH_SPEED_NUM_25G; + break; + case RTE_ETH_SPEED_NUM_40G: + new_link.link_speed = RTE_ETH_SPEED_NUM_40G; + break; + case RTE_ETH_SPEED_NUM_50G: + new_link.link_speed = RTE_ETH_SPEED_NUM_50G; + break; + case RTE_ETH_SPEED_NUM_100G: + new_link.link_speed = RTE_ETH_SPEED_NUM_100G; + break; + case RTE_ETH_SPEED_NUM_200G: + new_link.link_speed = RTE_ETH_SPEED_NUM_200G; + break; + default: + new_link.link_speed = RTE_ETH_SPEED_NUM_NONE; + } + + new_link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; + new_link.link_status = vport->link_up ? RTE_ETH_LINK_UP : + RTE_ETH_LINK_DOWN; + new_link.link_autoneg = (dev->data->dev_conf.link_speeds & RTE_ETH_LINK_SPEED_FIXED) ? + RTE_ETH_LINK_FIXED : RTE_ETH_LINK_AUTONEG; + + return rte_eth_linkstatus_set(dev, &new_link); +} + +static int +cpfl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) +{ + struct idpf_vport *vport = dev->data->dev_private; + struct idpf_adapter *adapter = vport->adapter; + + dev_info->max_rx_queues = adapter->caps.max_rx_q; + dev_info->max_tx_queues = adapter->caps.max_tx_q; + dev_info->min_rx_bufsize = CPFL_MIN_BUF_SIZE; + dev_info->max_rx_pktlen = vport->max_mtu + CPFL_ETH_OVERHEAD; + + dev_info->max_mtu = vport->max_mtu; + dev_info->min_mtu = RTE_ETHER_MIN_MTU; + + return 0; +} + +static const uint32_t * +cpfl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused) +{ + static const uint32_t ptypes[] = { + RTE_PTYPE_L2_ETHER, + RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, + RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, + RTE_PTYPE_L4_FRAG, + RTE_PTYPE_L4_UDP, + RTE_PTYPE_L4_TCP, + RTE_PTYPE_L4_SCTP, + RTE_PTYPE_L4_ICMP, + RTE_PTYPE_UNKNOWN + }; + + return ptypes; +} + +static int +cpfl_dev_configure(struct rte_eth_dev *dev) +{ + struct rte_eth_conf *conf = &dev->data->dev_conf; + + if (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) { + PMD_INIT_LOG(ERR, "Setting link speed is not supported"); + return -ENOTSUP; + } + + if (conf->txmode.mq_mode != RTE_ETH_MQ_TX_NONE) { + PMD_INIT_LOG(ERR, "Multi-queue TX mode %d is not supported", + conf->txmode.mq_mode); + return -ENOTSUP; + } + + if (conf->lpbk_mode != 0) { + PMD_INIT_LOG(ERR, "Loopback operation mode %d is not supported", + conf->lpbk_mode); + return -ENOTSUP; + } + + if (conf->dcb_capability_en != 0) { + PMD_INIT_LOG(ERR, "Priority Flow Control(PFC) if not supported"); + return -ENOTSUP; + } + + if (conf->intr_conf.lsc != 0) { + PMD_INIT_LOG(ERR, "LSC interrupt is not supported"); + return -ENOTSUP; + } + + if (conf->intr_conf.rxq != 0) { + PMD_INIT_LOG(ERR, "RXQ interrupt is not supported"); + return -ENOTSUP; + } + + if (conf->intr_conf.rmv != 0) { + PMD_INIT_LOG(ERR, "RMV interrupt is not supported"); + return -ENOTSUP; + } + + return 0; +} + +static int +cpfl_dev_close(struct rte_eth_dev *dev) +{ + struct idpf_vport *vport = dev->data->dev_private; + struct cpfl_adapter_ext *adapter = CPFL_ADAPTER_TO_EXT(vport->adapter); + + idpf_vport_deinit(vport); + + adapter->cur_vports &= ~RTE_BIT32(vport->devarg_id); + adapter->cur_vport_nb--; + dev->data->dev_private = NULL; + adapter->vports[vport->sw_idx] = NULL; + rte_free(vport); + + return 0; +} + +static int +insert_value(struct cpfl_devargs *devargs, uint16_t id) +{ + uint16_t i; + + /* ignore duplicate */ + for (i = 0; i < devargs->req_vport_nb; i++) { + if (devargs->req_vports[i] == id) + return 0; + } + + if (devargs->req_vport_nb >= RTE_DIM(devargs->req_vports)) { + PMD_INIT_LOG(ERR, "Total vport number can't be > %d", + CPFL_MAX_VPORT_NUM); + return -EINVAL; + } + + devargs->req_vports[devargs->req_vport_nb] = id; + devargs->req_vport_nb++; + + return 0; +} + +static const char * +parse_range(const char *value, struct cpfl_devargs *devargs) +{ + uint16_t lo, hi, i; + int n = 0; + int result; + const char *pos = value; + + result = sscanf(value, "%hu%n-%hu%n", &lo, &n, &hi, &n); + if (result == 1) { + if (lo >= CPFL_MAX_VPORT_NUM) + return NULL; + if (insert_value(devargs, lo) != 0) + return NULL; + } else if (result == 2) { + if (lo > hi || hi >= CPFL_MAX_VPORT_NUM) + return NULL; + for (i = lo; i <= hi; i++) { + if (insert_value(devargs, i) != 0) + return NULL; + } + } else { + return NULL; + } + + return pos + n; +} + +static int +parse_vport(const char *key, const char *value, void *args) +{ + struct cpfl_devargs *devargs = args; + const char *pos = value; + + devargs->req_vport_nb = 0; + + if (*pos == '[') + pos++; + + while (1) { + pos = parse_range(pos, devargs); + if (pos == NULL) { + PMD_INIT_LOG(ERR, "invalid value:\"%s\" for key:\"%s\", ", + value, key); + return -EINVAL; + } + if (*pos != ',') + break; + pos++; + } + + if (*value == '[' && *pos != ']') { + PMD_INIT_LOG(ERR, "invalid value:\"%s\" for key:\"%s\", ", + value, key); + return -EINVAL; + } + + return 0; +} + +static int +parse_bool(const char *key, const char *value, void *args) +{ + int *i = args; + char *end; + int num; + + errno = 0; + + num = strtoul(value, &end, 10); + + if (errno == ERANGE || (num != 0 && num != 1)) { + PMD_INIT_LOG(ERR, "invalid value:\"%s\" for key:\"%s\", value must be 0 or 1", + value, key); + return -EINVAL; + } + + *i = num; + return 0; +} + +static int +cpfl_parse_devargs(struct rte_pci_device *pci_dev, struct cpfl_adapter_ext *adapter, + struct cpfl_devargs *cpfl_args) +{ + struct rte_devargs *devargs = pci_dev->device.devargs; + struct rte_kvargs *kvlist; + int i, ret; + + cpfl_args->req_vport_nb = 0; + + if (devargs == NULL) + return 0; + + kvlist = rte_kvargs_parse(devargs->args, cpfl_valid_args); + if (kvlist == NULL) { + PMD_INIT_LOG(ERR, "invalid kvargs key"); + return -EINVAL; + } + + /* check parsed devargs */ + if (adapter->cur_vport_nb + cpfl_args->req_vport_nb > + CPFL_MAX_VPORT_NUM) { + PMD_INIT_LOG(ERR, "Total vport number can't be > %d", + CPFL_MAX_VPORT_NUM); + ret = -EINVAL; + goto bail; + } + + for (i = 0; i < cpfl_args->req_vport_nb; i++) { + if (adapter->cur_vports & RTE_BIT32(cpfl_args->req_vports[i])) { + PMD_INIT_LOG(ERR, "Vport %d has been created", + cpfl_args->req_vports[i]); + ret = -EINVAL; + goto bail; + } + } + + ret = rte_kvargs_process(kvlist, CPFL_VPORT, &parse_vport, + cpfl_args); + if (ret != 0) + goto bail; + + ret = rte_kvargs_process(kvlist, CPFL_TX_SINGLE_Q, &parse_bool, + &adapter->base.txq_model); + if (ret != 0) + goto bail; + + ret = rte_kvargs_process(kvlist, CPFL_RX_SINGLE_Q, &parse_bool, + &adapter->base.rxq_model); + if (ret != 0) + goto bail; + +bail: + rte_kvargs_free(kvlist); + return ret; +} + +static struct idpf_vport * +cpfl_find_vport(struct cpfl_adapter_ext *adapter, uint32_t vport_id) +{ + struct idpf_vport *vport = NULL; + int i; + + for (i = 0; i < adapter->cur_vport_nb; i++) { + vport = adapter->vports[i]; + if (vport->vport_id != vport_id) + continue; + else + return vport; + } + + return vport; +} + +static void +cpfl_handle_event_msg(struct idpf_vport *vport, uint8_t *msg, uint16_t msglen) +{ + struct virtchnl2_event *vc_event = (struct virtchnl2_event *)msg; + struct rte_eth_dev *dev = (struct rte_eth_dev *)vport->dev; + + if (msglen < sizeof(struct virtchnl2_event)) { + PMD_DRV_LOG(ERR, "Error event"); + return; + } + + switch (vc_event->event) { + case VIRTCHNL2_EVENT_LINK_CHANGE: + PMD_DRV_LOG(DEBUG, "VIRTCHNL2_EVENT_LINK_CHANGE"); + vport->link_up = !!(vc_event->link_status); + vport->link_speed = vc_event->link_speed; + cpfl_dev_link_update(dev, 0); + break; + default: + PMD_DRV_LOG(ERR, " unknown event received %u", vc_event->event); + break; + } +} + +static void +cpfl_handle_virtchnl_msg(struct cpfl_adapter_ext *adapter_ex) +{ + struct idpf_adapter *adapter = &adapter_ex->base; + struct idpf_dma_mem *dma_mem = NULL; + struct idpf_hw *hw = &adapter->hw; + struct virtchnl2_event *vc_event; + struct idpf_ctlq_msg ctlq_msg; + enum idpf_mbx_opc mbx_op; + struct idpf_vport *vport; + enum virtchnl_ops vc_op; + uint16_t pending = 1; + int ret; + + while (pending) { + ret = idpf_vc_ctlq_recv(hw->arq, &pending, &ctlq_msg); + if (ret) { + PMD_DRV_LOG(INFO, "Failed to read msg from virtual channel, ret: %d", ret); + return; + } + + memcpy(adapter->mbx_resp, ctlq_msg.ctx.indirect.payload->va, + IDPF_DFLT_MBX_BUF_SIZE); + + mbx_op = rte_le_to_cpu_16(ctlq_msg.opcode); + vc_op = rte_le_to_cpu_32(ctlq_msg.cookie.mbx.chnl_opcode); + adapter->cmd_retval = rte_le_to_cpu_32(ctlq_msg.cookie.mbx.chnl_retval); + + switch (mbx_op) { + case idpf_mbq_opc_send_msg_to_peer_pf: + if (vc_op == VIRTCHNL2_OP_EVENT) { + if (ctlq_msg.data_len < sizeof(struct virtchnl2_event)) { + PMD_DRV_LOG(ERR, "Error event"); + return; + } + vc_event = (struct virtchnl2_event *)adapter->mbx_resp; + vport = cpfl_find_vport(adapter_ex, vc_event->vport_id); + if (!vport) { + PMD_DRV_LOG(ERR, "Can't find vport."); + return; + } + cpfl_handle_event_msg(vport, adapter->mbx_resp, + ctlq_msg.data_len); + } else { + if (vc_op == adapter->pend_cmd) + notify_cmd(adapter, adapter->cmd_retval); + else + PMD_DRV_LOG(ERR, "command mismatch, expect %u, get %u", + adapter->pend_cmd, vc_op); + + PMD_DRV_LOG(DEBUG, " Virtual channel response is received," + "opcode = %d", vc_op); + } + goto post_buf; + default: + PMD_DRV_LOG(DEBUG, "Request %u is not supported yet", mbx_op); + } + } + +post_buf: + if (ctlq_msg.data_len) + dma_mem = ctlq_msg.ctx.indirect.payload; + else + pending = 0; + + ret = idpf_vc_ctlq_post_rx_buffs(hw, hw->arq, &pending, &dma_mem); + if (ret && dma_mem) + idpf_free_dma_mem(hw, dma_mem); +} + +static void +cpfl_dev_alarm_handler(void *param) +{ + struct cpfl_adapter_ext *adapter = param; + + cpfl_handle_virtchnl_msg(adapter); + + rte_eal_alarm_set(CPFL_ALARM_INTERVAL, cpfl_dev_alarm_handler, adapter); +} + +static int +cpfl_adapter_ext_init(struct rte_pci_device *pci_dev, struct cpfl_adapter_ext *adapter) +{ + struct idpf_adapter *base = &adapter->base; + struct idpf_hw *hw = &base->hw; + int ret = 0; + + hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; + hw->hw_addr_len = pci_dev->mem_resource[0].len; + hw->back = base; + hw->vendor_id = pci_dev->id.vendor_id; + hw->device_id = pci_dev->id.device_id; + hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; + + strncpy(adapter->name, pci_dev->device.name, PCI_PRI_STR_SIZE); + + ret = idpf_adapter_init(base); + if (ret != 0) { + PMD_INIT_LOG(ERR, "Failed to init adapter"); + goto err_adapter_init; + } + + rte_eal_alarm_set(CPFL_ALARM_INTERVAL, cpfl_dev_alarm_handler, adapter); + + adapter->max_vport_nb = adapter->base.caps.max_vports; + + adapter->vports = rte_zmalloc("vports", + adapter->max_vport_nb * + sizeof(*adapter->vports), + 0); + if (adapter->vports == NULL) { + PMD_INIT_LOG(ERR, "Failed to allocate vports memory"); + ret = -ENOMEM; + goto err_get_ptype; + } + + adapter->cur_vports = 0; + adapter->cur_vport_nb = 0; + + adapter->used_vecs_num = 0; + + return ret; + +err_get_ptype: + idpf_adapter_deinit(base); +err_adapter_init: + return ret; +} + +static const struct eth_dev_ops cpfl_eth_dev_ops = { + .dev_configure = cpfl_dev_configure, + .dev_close = cpfl_dev_close, + .dev_infos_get = cpfl_dev_info_get, + .link_update = cpfl_dev_link_update, + .dev_supported_ptypes_get = cpfl_dev_supported_ptypes_get, +}; + +static uint16_t +cpfl_vport_idx_alloc(struct cpfl_adapter_ext *ad) +{ + uint16_t vport_idx; + uint16_t i; + + for (i = 0; i < ad->max_vport_nb; i++) { + if (ad->vports[i] == NULL) + break; + } + + if (i == ad->max_vport_nb) + vport_idx = CPFL_INVALID_VPORT_IDX; + else + vport_idx = i; + + return vport_idx; +} + +static int +cpfl_dev_vport_init(struct rte_eth_dev *dev, void *init_params) +{ + struct idpf_vport *vport = dev->data->dev_private; + struct cpfl_vport_param *param = init_params; + struct cpfl_adapter_ext *adapter = param->adapter; + /* for sending create vport virtchnl msg prepare */ + struct virtchnl2_create_vport create_vport_info; + int ret = 0; + + dev->dev_ops = &cpfl_eth_dev_ops; + vport->adapter = &adapter->base; + vport->sw_idx = param->idx; + vport->devarg_id = param->devarg_id; + vport->dev = dev; + + memset(&create_vport_info, 0, sizeof(create_vport_info)); + ret = idpf_vport_info_init(vport, &create_vport_info); + if (ret != 0) { + PMD_INIT_LOG(ERR, "Failed to init vport req_info."); + goto err; + } + + ret = idpf_vport_init(vport, &create_vport_info, dev->data); + if (ret != 0) { + PMD_INIT_LOG(ERR, "Failed to init vports."); + goto err; + } + + adapter->vports[param->idx] = vport; + adapter->cur_vports |= RTE_BIT32(param->devarg_id); + adapter->cur_vport_nb++; + + dev->data->mac_addrs = rte_zmalloc(NULL, RTE_ETHER_ADDR_LEN, 0); + if (dev->data->mac_addrs == NULL) { + PMD_INIT_LOG(ERR, "Cannot allocate mac_addr memory."); + ret = -ENOMEM; + goto err_mac_addrs; + } + + rte_ether_addr_copy((struct rte_ether_addr *)vport->default_mac_addr, + &dev->data->mac_addrs[0]); + + return 0; + +err_mac_addrs: + adapter->vports[param->idx] = NULL; /* reset */ + idpf_vport_deinit(vport); +err: + return ret; +} + +static const struct rte_pci_id pci_id_cpfl_map[] = { + { RTE_PCI_DEVICE(IDPF_INTEL_VENDOR_ID, IDPF_DEV_ID_CPF) }, + { .vendor_id = 0, /* sentinel */ }, +}; + +static struct cpfl_adapter_ext * +cpfl_find_adapter_ext(struct rte_pci_device *pci_dev) +{ + struct cpfl_adapter_ext *adapter; + int found = 0; + + if (pci_dev == NULL) + return NULL; + + rte_spinlock_lock(&cpfl_adapter_lock); + TAILQ_FOREACH(adapter, &cpfl_adapter_list, next) { + if (strncmp(adapter->name, pci_dev->device.name, PCI_PRI_STR_SIZE) == 0) { + found = 1; + break; + } + } + rte_spinlock_unlock(&cpfl_adapter_lock); + + if (found == 0) + return NULL; + + return adapter; +} + +static void +cpfl_adapter_ext_deinit(struct cpfl_adapter_ext *adapter) +{ + rte_eal_alarm_cancel(cpfl_dev_alarm_handler, adapter); + idpf_adapter_deinit(&adapter->base); + + rte_free(adapter->vports); + adapter->vports = NULL; +} + +static int +cpfl_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, + struct rte_pci_device *pci_dev) +{ + struct cpfl_vport_param vport_param; + struct cpfl_adapter_ext *adapter; + struct cpfl_devargs devargs; + char name[RTE_ETH_NAME_MAX_LEN]; + int i, retval; + bool first_probe = false; + + if (!cpfl_adapter_list_init) { + rte_spinlock_init(&cpfl_adapter_lock); + TAILQ_INIT(&cpfl_adapter_list); + cpfl_adapter_list_init = true; + } + + adapter = cpfl_find_adapter_ext(pci_dev); + if (adapter == NULL) { + first_probe = true; + adapter = rte_zmalloc("cpfl_adapter_ext", + sizeof(struct cpfl_adapter_ext), 0); + if (adapter == NULL) { + PMD_INIT_LOG(ERR, "Failed to allocate adapter."); + return -ENOMEM; + } + + retval = cpfl_adapter_ext_init(pci_dev, adapter); + if (retval != 0) { + PMD_INIT_LOG(ERR, "Failed to init adapter."); + return retval; + } + + rte_spinlock_lock(&cpfl_adapter_lock); + TAILQ_INSERT_TAIL(&cpfl_adapter_list, adapter, next); + rte_spinlock_unlock(&cpfl_adapter_lock); + } + + retval = cpfl_parse_devargs(pci_dev, adapter, &devargs); + if (retval != 0) { + PMD_INIT_LOG(ERR, "Failed to parse private devargs"); + goto err; + } + + if (devargs.req_vport_nb == 0) { + /* If no vport devarg, create vport 0 by default. */ + vport_param.adapter = adapter; + vport_param.devarg_id = 0; + vport_param.idx = cpfl_vport_idx_alloc(adapter); + if (vport_param.idx == CPFL_INVALID_VPORT_IDX) { + PMD_INIT_LOG(ERR, "No space for vport %u", vport_param.devarg_id); + return 0; + } + snprintf(name, sizeof(name), "cpfl_%s_vport_0", + pci_dev->device.name); + retval = rte_eth_dev_create(&pci_dev->device, name, + sizeof(struct idpf_vport), + NULL, NULL, cpfl_dev_vport_init, + &vport_param); + if (retval != 0) + PMD_DRV_LOG(ERR, "Failed to create default vport 0"); + } else { + for (i = 0; i < devargs.req_vport_nb; i++) { + vport_param.adapter = adapter; + vport_param.devarg_id = devargs.req_vports[i]; + vport_param.idx = cpfl_vport_idx_alloc(adapter); + if (vport_param.idx == CPFL_INVALID_VPORT_IDX) { + PMD_INIT_LOG(ERR, "No space for vport %u", vport_param.devarg_id); + break; + } + snprintf(name, sizeof(name), "cpfl_%s_vport_%d", + pci_dev->device.name, + devargs.req_vports[i]); + retval = rte_eth_dev_create(&pci_dev->device, name, + sizeof(struct idpf_vport), + NULL, NULL, cpfl_dev_vport_init, + &vport_param); + if (retval != 0) + PMD_DRV_LOG(ERR, "Failed to create vport %d", + vport_param.devarg_id); + } + } + + return 0; + +err: + if (first_probe) { + rte_spinlock_lock(&cpfl_adapter_lock); + TAILQ_REMOVE(&cpfl_adapter_list, adapter, next); + rte_spinlock_unlock(&cpfl_adapter_lock); + cpfl_adapter_ext_deinit(adapter); + rte_free(adapter); + } + return retval; +} + +static int +cpfl_pci_remove(struct rte_pci_device *pci_dev) +{ + struct cpfl_adapter_ext *adapter = cpfl_find_adapter_ext(pci_dev); + uint16_t port_id; + + /* Ethdev created can be found RTE_ETH_FOREACH_DEV_OF through rte_device */ + RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) { + rte_eth_dev_close(port_id); + } + + rte_spinlock_lock(&cpfl_adapter_lock); + TAILQ_REMOVE(&cpfl_adapter_list, adapter, next); + rte_spinlock_unlock(&cpfl_adapter_lock); + cpfl_adapter_ext_deinit(adapter); + rte_free(adapter); + + return 0; +} + +static struct rte_pci_driver rte_cpfl_pmd = { + .id_table = pci_id_cpfl_map, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING, + .probe = cpfl_pci_probe, + .remove = cpfl_pci_remove, +}; + +/** + * Driver initialization routine. + * Invoked once at EAL init time. + * Register itself as the [Poll Mode] Driver of PCI devices. + */ +RTE_PMD_REGISTER_PCI(net_cpfl, rte_cpfl_pmd); +RTE_PMD_REGISTER_PCI_TABLE(net_cpfl, pci_id_cpfl_map); +RTE_PMD_REGISTER_KMOD_DEP(net_cpfl, "* igb_uio | vfio-pci"); +RTE_PMD_REGISTER_PARAM_STRING(net_cpfl, + CPFL_TX_SINGLE_Q "=<0|1> " + CPFL_RX_SINGLE_Q "=<0|1> " + CPFL_VPORT "=[vport_set0,[vport_set1],...]"); + +RTE_LOG_REGISTER_SUFFIX(cpfl_logtype_init, init, NOTICE); +RTE_LOG_REGISTER_SUFFIX(cpfl_logtype_driver, driver, NOTICE); diff --git a/drivers/net/cpfl/cpfl_ethdev.h b/drivers/net/cpfl/cpfl_ethdev.h new file mode 100644 index 0000000000..9ca39b4558 --- /dev/null +++ b/drivers/net/cpfl/cpfl_ethdev.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Intel Corporation + */ + +#ifndef _CPFL_ETHDEV_H_ +#define _CPFL_ETHDEV_H_ + +#include +#include +#include +#include +#include +#include +#include + +#include "cpfl_logs.h" + +#include +#include +#include +#include + +#define CPFL_MAX_VPORT_NUM 8 + +#define CPFL_INVALID_VPORT_IDX 0xffff + +#define CPFL_MIN_BUF_SIZE 1024 +#define CPFL_MAX_FRAME_SIZE 9728 +#define CPFL_DEFAULT_MTU RTE_ETHER_MTU + +#define CPFL_NUM_MACADDR_MAX 64 + +#define CPFL_VLAN_TAG_SIZE 4 +#define CPFL_ETH_OVERHEAD \ + (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + CPFL_VLAN_TAG_SIZE * 2) + +#define CPFL_ADAPTER_NAME_LEN (PCI_PRI_STR_SIZE + 1) + +#define CPFL_ALARM_INTERVAL 50000 /* us */ + +/* Device IDs */ +#define IDPF_DEV_ID_CPF 0x1453 + +struct cpfl_vport_param { + struct cpfl_adapter_ext *adapter; + uint16_t devarg_id; /* arg id from user */ + uint16_t idx; /* index in adapter->vports[]*/ +}; + +/* Struct used when parse driver specific devargs */ +struct cpfl_devargs { + uint16_t req_vports[CPFL_MAX_VPORT_NUM]; + uint16_t req_vport_nb; +}; + +struct cpfl_adapter_ext { + TAILQ_ENTRY(cpfl_adapter_ext) next; + struct idpf_adapter base; + + char name[CPFL_ADAPTER_NAME_LEN]; + + struct idpf_vport **vports; + uint16_t max_vport_nb; + + uint16_t cur_vports; /* bit mask of created vport */ + uint16_t cur_vport_nb; + + uint16_t used_vecs_num; +}; + +TAILQ_HEAD(cpfl_adapter_list, cpfl_adapter_ext); + +#define CPFL_DEV_TO_PCI(eth_dev) \ + RTE_DEV_TO_PCI((eth_dev)->device) +#define CPFL_ADAPTER_TO_EXT(p) \ + container_of((p), struct cpfl_adapter_ext, base) + +#endif /* _CPFL_ETHDEV_H_ */ diff --git a/drivers/net/cpfl/cpfl_logs.h b/drivers/net/cpfl/cpfl_logs.h new file mode 100644 index 0000000000..365b53e8b3 --- /dev/null +++ b/drivers/net/cpfl/cpfl_logs.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Intel Corporation + */ + +#ifndef _CPFL_LOGS_H_ +#define _CPFL_LOGS_H_ + +#include + +extern int cpfl_logtype_init; +extern int cpfl_logtype_driver; + +#define PMD_INIT_LOG(level, ...) \ + rte_log(RTE_LOG_ ## level, \ + cpfl_logtype_init, \ + RTE_FMT("%s(): " \ + RTE_FMT_HEAD(__VA_ARGS__,) "\n", \ + __func__, \ + RTE_FMT_TAIL(__VA_ARGS__,))) + +#define PMD_DRV_LOG_RAW(level, ...) \ + rte_log(RTE_LOG_ ## level, \ + cpfl_logtype_driver, \ + RTE_FMT("%s(): " \ + RTE_FMT_HEAD(__VA_ARGS__,) "\n", \ + __func__, \ + RTE_FMT_TAIL(__VA_ARGS__,))) + +#define PMD_DRV_LOG(level, fmt, args...) \ + PMD_DRV_LOG_RAW(level, fmt "\n", ## args) + +#endif /* _CPFL_LOGS_H_ */ diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c new file mode 100644 index 0000000000..2b9c20928b --- /dev/null +++ b/drivers/net/cpfl/cpfl_rxtx.c @@ -0,0 +1,244 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Intel Corporation + */ + +#include +#include +#include + +#include "cpfl_ethdev.h" +#include "cpfl_rxtx.h" + +static uint64_t +cpfl_tx_offload_convert(uint64_t offload) +{ + uint64_t ol = 0; + + if ((offload & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM) != 0) + ol |= IDPF_TX_OFFLOAD_IPV4_CKSUM; + if ((offload & RTE_ETH_TX_OFFLOAD_UDP_CKSUM) != 0) + ol |= IDPF_TX_OFFLOAD_UDP_CKSUM; + if ((offload & RTE_ETH_TX_OFFLOAD_TCP_CKSUM) != 0) + ol |= IDPF_TX_OFFLOAD_TCP_CKSUM; + if ((offload & RTE_ETH_TX_OFFLOAD_SCTP_CKSUM) != 0) + ol |= IDPF_TX_OFFLOAD_SCTP_CKSUM; + if ((offload & RTE_ETH_TX_OFFLOAD_MULTI_SEGS) != 0) + ol |= IDPF_TX_OFFLOAD_MULTI_SEGS; + if ((offload & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) != 0) + ol |= IDPF_TX_OFFLOAD_MBUF_FAST_FREE; + + return ol; +} + +static const struct rte_memzone * +cpfl_dma_zone_reserve(struct rte_eth_dev *dev, uint16_t queue_idx, + uint16_t len, uint16_t queue_type, + unsigned int socket_id, bool splitq) +{ + char ring_name[RTE_MEMZONE_NAMESIZE]; + const struct rte_memzone *mz; + uint32_t ring_size; + + memset(ring_name, 0, RTE_MEMZONE_NAMESIZE); + switch (queue_type) { + case VIRTCHNL2_QUEUE_TYPE_TX: + if (splitq) + ring_size = RTE_ALIGN(len * sizeof(struct idpf_flex_tx_sched_desc), + CPFL_DMA_MEM_ALIGN); + else + ring_size = RTE_ALIGN(len * sizeof(struct idpf_flex_tx_desc), + CPFL_DMA_MEM_ALIGN); + memcpy(ring_name, "cpfl Tx ring", sizeof("cpfl Tx ring")); + break; + case VIRTCHNL2_QUEUE_TYPE_RX: + if (splitq) + ring_size = RTE_ALIGN(len * sizeof(struct virtchnl2_rx_flex_desc_adv_nic_3), + CPFL_DMA_MEM_ALIGN); + else + ring_size = RTE_ALIGN(len * sizeof(struct virtchnl2_singleq_rx_buf_desc), + CPFL_DMA_MEM_ALIGN); + memcpy(ring_name, "cpfl Rx ring", sizeof("cpfl Rx ring")); + break; + case VIRTCHNL2_QUEUE_TYPE_TX_COMPLETION: + ring_size = RTE_ALIGN(len * sizeof(struct idpf_splitq_tx_compl_desc), + CPFL_DMA_MEM_ALIGN); + memcpy(ring_name, "cpfl Tx compl ring", sizeof("cpfl Tx compl ring")); + break; + case VIRTCHNL2_QUEUE_TYPE_RX_BUFFER: + ring_size = RTE_ALIGN(len * sizeof(struct virtchnl2_splitq_rx_buf_desc), + CPFL_DMA_MEM_ALIGN); + memcpy(ring_name, "cpfl Rx buf ring", sizeof("cpfl Rx buf ring")); + break; + default: + PMD_INIT_LOG(ERR, "Invalid queue type"); + return NULL; + } + + mz = rte_eth_dma_zone_reserve(dev, ring_name, queue_idx, + ring_size, CPFL_RING_BASE_ALIGN, + socket_id); + if (mz == NULL) { + PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for ring"); + return NULL; + } + + /* Zero all the descriptors in the ring. */ + memset(mz->addr, 0, ring_size); + + return mz; +} + +static void +cpfl_dma_zone_release(const struct rte_memzone *mz) +{ + rte_memzone_free(mz); +} + +static int +cpfl_tx_complq_setup(struct rte_eth_dev *dev, struct idpf_tx_queue *txq, + uint16_t queue_idx, uint16_t nb_desc, + unsigned int socket_id) +{ + struct idpf_vport *vport = dev->data->dev_private; + const struct rte_memzone *mz; + struct idpf_tx_queue *cq; + int ret; + + cq = rte_zmalloc_socket("cpfl splitq cq", + sizeof(struct idpf_tx_queue), + RTE_CACHE_LINE_SIZE, + socket_id); + if (cq == NULL) { + PMD_INIT_LOG(ERR, "Failed to allocate memory for Tx compl queue"); + ret = -ENOMEM; + goto err_cq_alloc; + } + + cq->nb_tx_desc = nb_desc; + cq->queue_id = vport->chunks_info.tx_compl_start_qid + queue_idx; + cq->port_id = dev->data->port_id; + cq->txqs = dev->data->tx_queues; + cq->tx_start_qid = vport->chunks_info.tx_start_qid; + + mz = cpfl_dma_zone_reserve(dev, queue_idx, nb_desc, + VIRTCHNL2_QUEUE_TYPE_TX_COMPLETION, + socket_id, true); + if (mz == NULL) { + ret = -ENOMEM; + goto err_mz_reserve; + } + cq->tx_ring_phys_addr = mz->iova; + cq->compl_ring = mz->addr; + cq->mz = mz; + reset_split_tx_complq(cq); + + txq->complq = cq; + + return 0; + +err_mz_reserve: + rte_free(cq); +err_cq_alloc: + return ret; +} + +int +cpfl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, + uint16_t nb_desc, unsigned int socket_id, + const struct rte_eth_txconf *tx_conf) +{ + struct idpf_vport *vport = dev->data->dev_private; + struct idpf_adapter *adapter = vport->adapter; + uint16_t tx_rs_thresh, tx_free_thresh; + struct idpf_hw *hw = &adapter->hw; + const struct rte_memzone *mz; + struct idpf_tx_queue *txq; + uint64_t offloads; + uint16_t len; + bool is_splitq; + int ret; + + offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads; + + tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh > 0) ? + tx_conf->tx_rs_thresh : CPFL_DEFAULT_TX_RS_THRESH); + tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh > 0) ? + tx_conf->tx_free_thresh : CPFL_DEFAULT_TX_FREE_THRESH); + if (check_tx_thresh(nb_desc, tx_rs_thresh, tx_free_thresh) != 0) + return -EINVAL; + + /* Allocate the TX queue data structure. */ + txq = rte_zmalloc_socket("cpfl txq", + sizeof(struct idpf_tx_queue), + RTE_CACHE_LINE_SIZE, + socket_id); + if (txq == NULL) { + PMD_INIT_LOG(ERR, "Failed to allocate memory for tx queue structure"); + ret = -ENOMEM; + goto err_txq_alloc; + } + + is_splitq = !!(vport->txq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT); + + txq->nb_tx_desc = nb_desc; + txq->rs_thresh = tx_rs_thresh; + txq->free_thresh = tx_free_thresh; + txq->queue_id = vport->chunks_info.tx_start_qid + queue_idx; + txq->port_id = dev->data->port_id; + txq->offloads = cpfl_tx_offload_convert(offloads); + txq->tx_deferred_start = tx_conf->tx_deferred_start; + + if (is_splitq) + len = 2 * nb_desc; + else + len = nb_desc; + txq->sw_nb_desc = len; + + /* Allocate TX hardware ring descriptors. */ + mz = cpfl_dma_zone_reserve(dev, queue_idx, nb_desc, VIRTCHNL2_QUEUE_TYPE_TX, + socket_id, is_splitq); + if (mz == NULL) { + ret = -ENOMEM; + goto err_mz_reserve; + } + txq->tx_ring_phys_addr = mz->iova; + txq->mz = mz; + + txq->sw_ring = rte_zmalloc_socket("cpfl tx sw ring", + sizeof(struct idpf_tx_entry) * len, + RTE_CACHE_LINE_SIZE, socket_id); + if (txq->sw_ring == NULL) { + PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring"); + ret = -ENOMEM; + goto err_sw_ring_alloc; + } + + if (!is_splitq) { + txq->tx_ring = mz->addr; + reset_single_tx_queue(txq); + } else { + txq->desc_ring = mz->addr; + reset_split_tx_descq(txq); + + /* Setup tx completion queue if split model */ + ret = cpfl_tx_complq_setup(dev, txq, queue_idx, + 2 * nb_desc, socket_id); + if (ret != 0) + goto err_complq_setup; + } + + txq->qtx_tail = hw->hw_addr + (vport->chunks_info.tx_qtail_start + + queue_idx * vport->chunks_info.tx_qtail_spacing); + txq->q_set = true; + dev->data->tx_queues[queue_idx] = txq; + + return 0; + +err_complq_setup: +err_sw_ring_alloc: + cpfl_dma_zone_release(mz); +err_mz_reserve: + rte_free(txq); +err_txq_alloc: + return ret; +} diff --git a/drivers/net/cpfl/cpfl_rxtx.h b/drivers/net/cpfl/cpfl_rxtx.h new file mode 100644 index 0000000000..232630c5e9 --- /dev/null +++ b/drivers/net/cpfl/cpfl_rxtx.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Intel Corporation + */ + +#ifndef _CPFL_RXTX_H_ +#define _CPFL_RXTX_H_ + +#include +#include "cpfl_ethdev.h" + +/* In QLEN must be whole number of 32 descriptors. */ +#define CPFL_ALIGN_RING_DESC 32 +#define CPFL_MIN_RING_DESC 32 +#define CPFL_MAX_RING_DESC 4096 +#define CPFL_DMA_MEM_ALIGN 4096 +/* Base address of the HW descriptor ring should be 128B aligned. */ +#define CPFL_RING_BASE_ALIGN 128 + +#define CPFL_DEFAULT_TX_RS_THRESH 32 +#define CPFL_DEFAULT_TX_FREE_THRESH 32 + +int cpfl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, + uint16_t nb_desc, unsigned int socket_id, + const struct rte_eth_txconf *tx_conf); +#endif /* _CPFL_RXTX_H_ */ diff --git a/drivers/net/cpfl/meson.build b/drivers/net/cpfl/meson.build new file mode 100644 index 0000000000..c721732b50 --- /dev/null +++ b/drivers/net/cpfl/meson.build @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2023 Intel Corporation + +if is_windows + build = false + reason = 'not supported on Windows' + subdir_done() +endif + +deps += ['common_idpf'] + +sources = files( + 'cpfl_ethdev.c', +) \ No newline at end of file diff --git a/drivers/net/meson.build b/drivers/net/meson.build index 6470bf3636..a8ca338875 100644 --- a/drivers/net/meson.build +++ b/drivers/net/meson.build @@ -13,6 +13,7 @@ drivers = [ 'bnxt', 'bonding', 'cnxk', + 'cpfl', 'cxgbe', 'dpaa', 'dpaa2', From patchwork Thu Feb 16 00:29:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Mingxia" X-Patchwork-Id: 124006 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 110F241CA9; Thu, 16 Feb 2023 02:28:02 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4874B42BC9; Thu, 16 Feb 2023 02:27:54 +0100 (CET) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id 2D1EB4113F for ; Thu, 16 Feb 2023 02:27:52 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676510872; x=1708046872; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lpalN6E69cnv6dLfJLnmoggXdoSEHJdrQCXxAMIPFKg=; b=RUerNA7jBgyXh9VXFUw7RVHS6DEbUT4pPw6ac/732H/B/daQVIOh7Owq PgH/maH0D1m2y+mdSuxTqneoK78E2JHxa7Pf1pS8bdIZgDtdf1PMtWkEo vjyGvzCBtI1MvZGK1z7P3IrAemKANEbLGL3HWCV8Dauq2yDi9LMpKgRyD YG9Pq+ZZxGyiq3UlOwGrXavMgajvVcde0izvxz2brBs/hM6Ewj80txWqU WqwZcj6Zw1fpoWr3xLf+WC9gXQQWsgjaHrPs3tU0Td+lTV5vcmyRi+ayt hgOvtHche5n2a7mtiBxrD1hpVd49IenWVep0oI44i9gF5Mk6+PL4xXeDL Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="329315350" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="329315350" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2023 17:27:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="779166183" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="779166183" Received: from dpdk-mingxial-01.sh.intel.com ([10.67.119.167]) by fmsmga002.fm.intel.com with ESMTP; 15 Feb 2023 17:27:50 -0800 From: Mingxia Liu To: dev@dpdk.org, beilei.xing@intel.com, yuying.zhang@intel.com Cc: Mingxia Liu Subject: [PATCH v7 02/21] net/cpfl: add Tx queue setup Date: Thu, 16 Feb 2023 00:29:51 +0000 Message-Id: <20230216003010.3439881-3-mingxia.liu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230216003010.3439881-1-mingxia.liu@intel.com> References: <20230213021956.2953088-1-mingxia.liu@intel.com> <20230216003010.3439881-1-mingxia.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for tx_queue_setup ops. In the single queue model, the same descriptor queue is used by SW to post buffer descriptors to HW and by HW to post completed descriptors to SW. In the split queue model, "RX buffer queues" are used to pass descriptor buffers from SW to HW while Rx queues are used only to pass the descriptor completions, that is, descriptors that point to completed buffers, from HW to SW. This is contrary to the single queue model in which Rx queues are used for both purposes. Signed-off-by: Mingxia Liu --- drivers/net/cpfl/cpfl_ethdev.c | 13 +++++++++++++ drivers/net/cpfl/cpfl_rxtx.c | 8 ++++---- drivers/net/cpfl/meson.build | 1 + 3 files changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index fe0061133c..5ca21c9772 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -12,6 +12,7 @@ #include #include "cpfl_ethdev.h" +#include "cpfl_rxtx.h" #define CPFL_TX_SINGLE_Q "tx_single" #define CPFL_RX_SINGLE_Q "rx_single" @@ -96,6 +97,17 @@ cpfl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) dev_info->max_mtu = vport->max_mtu; dev_info->min_mtu = RTE_ETHER_MIN_MTU; + dev_info->default_txconf = (struct rte_eth_txconf) { + .tx_free_thresh = CPFL_DEFAULT_TX_FREE_THRESH, + .tx_rs_thresh = CPFL_DEFAULT_TX_RS_THRESH, + }; + + dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { + .nb_max = CPFL_MAX_RING_DESC, + .nb_min = CPFL_MIN_RING_DESC, + .nb_align = CPFL_ALIGN_RING_DESC, + }; + return 0; } @@ -513,6 +525,7 @@ cpfl_adapter_ext_init(struct rte_pci_device *pci_dev, struct cpfl_adapter_ext *a static const struct eth_dev_ops cpfl_eth_dev_ops = { .dev_configure = cpfl_dev_configure, .dev_close = cpfl_dev_close, + .tx_queue_setup = cpfl_tx_queue_setup, .dev_infos_get = cpfl_dev_info_get, .link_update = cpfl_dev_link_update, .dev_supported_ptypes_get = cpfl_dev_supported_ptypes_get, diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c index 2b9c20928b..5b69ac0009 100644 --- a/drivers/net/cpfl/cpfl_rxtx.c +++ b/drivers/net/cpfl/cpfl_rxtx.c @@ -130,7 +130,7 @@ cpfl_tx_complq_setup(struct rte_eth_dev *dev, struct idpf_tx_queue *txq, cq->tx_ring_phys_addr = mz->iova; cq->compl_ring = mz->addr; cq->mz = mz; - reset_split_tx_complq(cq); + idpf_qc_split_tx_complq_reset(cq); txq->complq = cq; @@ -164,7 +164,7 @@ cpfl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, tx_conf->tx_rs_thresh : CPFL_DEFAULT_TX_RS_THRESH); tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh > 0) ? tx_conf->tx_free_thresh : CPFL_DEFAULT_TX_FREE_THRESH); - if (check_tx_thresh(nb_desc, tx_rs_thresh, tx_free_thresh) != 0) + if (idpf_qc_tx_thresh_check(nb_desc, tx_rs_thresh, tx_free_thresh) != 0) return -EINVAL; /* Allocate the TX queue data structure. */ @@ -215,10 +215,10 @@ cpfl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, if (!is_splitq) { txq->tx_ring = mz->addr; - reset_single_tx_queue(txq); + idpf_qc_single_tx_queue_reset(txq); } else { txq->desc_ring = mz->addr; - reset_split_tx_descq(txq); + idpf_qc_split_tx_descq_reset(txq); /* Setup tx completion queue if split model */ ret = cpfl_tx_complq_setup(dev, txq, queue_idx, diff --git a/drivers/net/cpfl/meson.build b/drivers/net/cpfl/meson.build index c721732b50..1894423689 100644 --- a/drivers/net/cpfl/meson.build +++ b/drivers/net/cpfl/meson.build @@ -11,4 +11,5 @@ deps += ['common_idpf'] sources = files( 'cpfl_ethdev.c', + 'cpfl_rxtx.c', ) \ No newline at end of file From patchwork Thu Feb 16 00:29:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Mingxia" X-Patchwork-Id: 124007 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 41C5341CA9; Thu, 16 Feb 2023 02:28:11 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EC28F42D16; Thu, 16 Feb 2023 02:27:57 +0100 (CET) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id BB34A42C4D for ; Thu, 16 Feb 2023 02:27:54 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676510875; x=1708046875; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RuwyiMiB7hRjr1AAgdB+FerWTn49f1sT6G6p1G6vJ1c=; b=XmB1Spgn2SZ14yRY7FINGFxOp1EPKM+0tQeBaCZ5iMM3t4mBF/m21ojD 2YLz+VfkY9Zz0xbagC1mj/oBcFfgntVvCv4WvHsIO4izqE7SXTSSLfcoy 587ctrWI7Tv5xUZdwOcU1kPdpwKBKvTVYMH4h6AG2je48YOOnxtXbofbh dJsNjSGwbV1THU7NasIyedFWULaAmMHrQnGaL/GzitstwhO+wntukfjnL 2qgu/hP9mx4ecfM0cuKvHSg+7e3Rmdxp8MTyscNjL0rqAi1NiE39U/Rjn boekjFIn5yH4iG6jTbfdFCH4nesngu/H80m7mYNxPRivmTo7E39Da49i6 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="329315365" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="329315365" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2023 17:27:53 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="779166195" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="779166195" Received: from dpdk-mingxial-01.sh.intel.com ([10.67.119.167]) by fmsmga002.fm.intel.com with ESMTP; 15 Feb 2023 17:27:52 -0800 From: Mingxia Liu To: dev@dpdk.org, beilei.xing@intel.com, yuying.zhang@intel.com Cc: Mingxia Liu Subject: [PATCH v7 03/21] net/cpfl: add Rx queue setup Date: Thu, 16 Feb 2023 00:29:52 +0000 Message-Id: <20230216003010.3439881-4-mingxia.liu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230216003010.3439881-1-mingxia.liu@intel.com> References: <20230213021956.2953088-1-mingxia.liu@intel.com> <20230216003010.3439881-1-mingxia.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for rx_queue_setup ops. Signed-off-by: Mingxia Liu --- drivers/net/cpfl/cpfl_ethdev.c | 11 ++ drivers/net/cpfl/cpfl_rxtx.c | 232 +++++++++++++++++++++++++++++++++ drivers/net/cpfl/cpfl_rxtx.h | 6 + 3 files changed, 249 insertions(+) diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index 5ca21c9772..3029f03d02 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -102,12 +102,22 @@ cpfl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) .tx_rs_thresh = CPFL_DEFAULT_TX_RS_THRESH, }; + dev_info->default_rxconf = (struct rte_eth_rxconf) { + .rx_free_thresh = CPFL_DEFAULT_RX_FREE_THRESH, + }; + dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { .nb_max = CPFL_MAX_RING_DESC, .nb_min = CPFL_MIN_RING_DESC, .nb_align = CPFL_ALIGN_RING_DESC, }; + dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { + .nb_max = CPFL_MAX_RING_DESC, + .nb_min = CPFL_MIN_RING_DESC, + .nb_align = CPFL_ALIGN_RING_DESC, + }; + return 0; } @@ -525,6 +535,7 @@ cpfl_adapter_ext_init(struct rte_pci_device *pci_dev, struct cpfl_adapter_ext *a static const struct eth_dev_ops cpfl_eth_dev_ops = { .dev_configure = cpfl_dev_configure, .dev_close = cpfl_dev_close, + .rx_queue_setup = cpfl_rx_queue_setup, .tx_queue_setup = cpfl_tx_queue_setup, .dev_infos_get = cpfl_dev_info_get, .link_update = cpfl_dev_link_update, diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c index 5b69ac0009..042b848ce2 100644 --- a/drivers/net/cpfl/cpfl_rxtx.c +++ b/drivers/net/cpfl/cpfl_rxtx.c @@ -9,6 +9,25 @@ #include "cpfl_ethdev.h" #include "cpfl_rxtx.h" +static uint64_t +cpfl_rx_offload_convert(uint64_t offload) +{ + uint64_t ol = 0; + + if ((offload & RTE_ETH_RX_OFFLOAD_IPV4_CKSUM) != 0) + ol |= IDPF_RX_OFFLOAD_IPV4_CKSUM; + if ((offload & RTE_ETH_RX_OFFLOAD_UDP_CKSUM) != 0) + ol |= IDPF_RX_OFFLOAD_UDP_CKSUM; + if ((offload & RTE_ETH_RX_OFFLOAD_TCP_CKSUM) != 0) + ol |= IDPF_RX_OFFLOAD_TCP_CKSUM; + if ((offload & RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM) != 0) + ol |= IDPF_RX_OFFLOAD_OUTER_IPV4_CKSUM; + if ((offload & RTE_ETH_RX_OFFLOAD_TIMESTAMP) != 0) + ol |= IDPF_RX_OFFLOAD_TIMESTAMP; + + return ol; +} + static uint64_t cpfl_tx_offload_convert(uint64_t offload) { @@ -94,6 +113,219 @@ cpfl_dma_zone_release(const struct rte_memzone *mz) rte_memzone_free(mz); } +static int +cpfl_rx_split_bufq_setup(struct rte_eth_dev *dev, struct idpf_rx_queue *rxq, + uint16_t queue_idx, uint16_t rx_free_thresh, + uint16_t nb_desc, unsigned int socket_id, + struct rte_mempool *mp, uint8_t bufq_id) +{ + struct idpf_vport *vport = dev->data->dev_private; + struct idpf_adapter *adapter = vport->adapter; + struct idpf_hw *hw = &adapter->hw; + const struct rte_memzone *mz; + struct idpf_rx_queue *bufq; + uint16_t len; + int ret; + + bufq = rte_zmalloc_socket("cpfl bufq", + sizeof(struct idpf_rx_queue), + RTE_CACHE_LINE_SIZE, + socket_id); + if (bufq == NULL) { + PMD_INIT_LOG(ERR, "Failed to allocate memory for rx buffer queue."); + ret = -ENOMEM; + goto err_bufq1_alloc; + } + + bufq->mp = mp; + bufq->nb_rx_desc = nb_desc; + bufq->rx_free_thresh = rx_free_thresh; + bufq->queue_id = vport->chunks_info.rx_buf_start_qid + queue_idx; + bufq->port_id = dev->data->port_id; + bufq->rx_hdr_len = 0; + bufq->adapter = adapter; + + len = rte_pktmbuf_data_room_size(bufq->mp) - RTE_PKTMBUF_HEADROOM; + bufq->rx_buf_len = len; + + /* Allocate a little more to support bulk allocate. */ + len = nb_desc + IDPF_RX_MAX_BURST; + + mz = cpfl_dma_zone_reserve(dev, queue_idx, len, + VIRTCHNL2_QUEUE_TYPE_RX_BUFFER, + socket_id, true); + if (mz == NULL) { + ret = -ENOMEM; + goto err_mz_reserve; + } + + bufq->rx_ring_phys_addr = mz->iova; + bufq->rx_ring = mz->addr; + bufq->mz = mz; + + bufq->sw_ring = + rte_zmalloc_socket("cpfl rx bufq sw ring", + sizeof(struct rte_mbuf *) * len, + RTE_CACHE_LINE_SIZE, + socket_id); + if (bufq->sw_ring == NULL) { + PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring"); + ret = -ENOMEM; + goto err_sw_ring_alloc; + } + + idpf_qc_split_rx_bufq_reset(bufq); + bufq->qrx_tail = hw->hw_addr + (vport->chunks_info.rx_buf_qtail_start + + queue_idx * vport->chunks_info.rx_buf_qtail_spacing); + bufq->q_set = true; + + if (bufq_id == 1) { + rxq->bufq1 = bufq; + } else if (bufq_id == 2) { + rxq->bufq2 = bufq; + } else { + PMD_INIT_LOG(ERR, "Invalid buffer queue index."); + ret = -EINVAL; + goto err_bufq_id; + } + + return 0; + +err_bufq_id: + rte_free(bufq->sw_ring); +err_sw_ring_alloc: + cpfl_dma_zone_release(mz); +err_mz_reserve: + rte_free(bufq); +err_bufq1_alloc: + return ret; +} + +static void +cpfl_rx_split_bufq_release(struct idpf_rx_queue *bufq) +{ + rte_free(bufq->sw_ring); + cpfl_dma_zone_release(bufq->mz); + rte_free(bufq); +} + +int +cpfl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, + uint16_t nb_desc, unsigned int socket_id, + const struct rte_eth_rxconf *rx_conf, + struct rte_mempool *mp) +{ + struct idpf_vport *vport = dev->data->dev_private; + struct idpf_adapter *adapter = vport->adapter; + struct idpf_hw *hw = &adapter->hw; + const struct rte_memzone *mz; + struct idpf_rx_queue *rxq; + uint16_t rx_free_thresh; + uint64_t offloads; + bool is_splitq; + uint16_t len; + int ret; + + offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads; + + /* Check free threshold */ + rx_free_thresh = (rx_conf->rx_free_thresh == 0) ? + CPFL_DEFAULT_RX_FREE_THRESH : + rx_conf->rx_free_thresh; + if (idpf_qc_rx_thresh_check(nb_desc, rx_free_thresh) != 0) + return -EINVAL; + + /* Setup Rx queue */ + rxq = rte_zmalloc_socket("cpfl rxq", + sizeof(struct idpf_rx_queue), + RTE_CACHE_LINE_SIZE, + socket_id); + if (rxq == NULL) { + PMD_INIT_LOG(ERR, "Failed to allocate memory for rx queue data structure"); + ret = -ENOMEM; + goto err_rxq_alloc; + } + + is_splitq = !!(vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT); + + rxq->mp = mp; + rxq->nb_rx_desc = nb_desc; + rxq->rx_free_thresh = rx_free_thresh; + rxq->queue_id = vport->chunks_info.rx_start_qid + queue_idx; + rxq->port_id = dev->data->port_id; + rxq->rx_deferred_start = rx_conf->rx_deferred_start; + rxq->rx_hdr_len = 0; + rxq->adapter = adapter; + rxq->offloads = cpfl_rx_offload_convert(offloads); + + len = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM; + rxq->rx_buf_len = len; + + /* Allocate a little more to support bulk allocate. */ + len = nb_desc + IDPF_RX_MAX_BURST; + mz = cpfl_dma_zone_reserve(dev, queue_idx, len, VIRTCHNL2_QUEUE_TYPE_RX, + socket_id, is_splitq); + if (mz == NULL) { + ret = -ENOMEM; + goto err_mz_reserve; + } + rxq->rx_ring_phys_addr = mz->iova; + rxq->rx_ring = mz->addr; + rxq->mz = mz; + + if (!is_splitq) { + rxq->sw_ring = rte_zmalloc_socket("cpfl rxq sw ring", + sizeof(struct rte_mbuf *) * len, + RTE_CACHE_LINE_SIZE, + socket_id); + if (rxq->sw_ring == NULL) { + PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring"); + ret = -ENOMEM; + goto err_sw_ring_alloc; + } + + idpf_qc_single_rx_queue_reset(rxq); + rxq->qrx_tail = hw->hw_addr + (vport->chunks_info.rx_qtail_start + + queue_idx * vport->chunks_info.rx_qtail_spacing); + } else { + idpf_qc_split_rx_descq_reset(rxq); + + /* Setup Rx buffer queues */ + ret = cpfl_rx_split_bufq_setup(dev, rxq, 2 * queue_idx, + rx_free_thresh, nb_desc, + socket_id, mp, 1); + if (ret != 0) { + PMD_INIT_LOG(ERR, "Failed to setup buffer queue 1"); + ret = -EINVAL; + goto err_bufq1_setup; + } + + ret = cpfl_rx_split_bufq_setup(dev, rxq, 2 * queue_idx + 1, + rx_free_thresh, nb_desc, + socket_id, mp, 2); + if (ret != 0) { + PMD_INIT_LOG(ERR, "Failed to setup buffer queue 2"); + ret = -EINVAL; + goto err_bufq2_setup; + } + } + + rxq->q_set = true; + dev->data->rx_queues[queue_idx] = rxq; + + return 0; + +err_bufq2_setup: + cpfl_rx_split_bufq_release(rxq->bufq1); +err_bufq1_setup: +err_sw_ring_alloc: + cpfl_dma_zone_release(mz); +err_mz_reserve: + rte_free(rxq); +err_rxq_alloc: + return ret; +} + static int cpfl_tx_complq_setup(struct rte_eth_dev *dev, struct idpf_tx_queue *txq, uint16_t queue_idx, uint16_t nb_desc, diff --git a/drivers/net/cpfl/cpfl_rxtx.h b/drivers/net/cpfl/cpfl_rxtx.h index 232630c5e9..e0221abfa3 100644 --- a/drivers/net/cpfl/cpfl_rxtx.h +++ b/drivers/net/cpfl/cpfl_rxtx.h @@ -16,10 +16,16 @@ /* Base address of the HW descriptor ring should be 128B aligned. */ #define CPFL_RING_BASE_ALIGN 128 +#define CPFL_DEFAULT_RX_FREE_THRESH 32 + #define CPFL_DEFAULT_TX_RS_THRESH 32 #define CPFL_DEFAULT_TX_FREE_THRESH 32 int cpfl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, uint16_t nb_desc, unsigned int socket_id, const struct rte_eth_txconf *tx_conf); +int cpfl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, + uint16_t nb_desc, unsigned int socket_id, + const struct rte_eth_rxconf *rx_conf, + struct rte_mempool *mp); #endif /* _CPFL_RXTX_H_ */ From patchwork Thu Feb 16 00:29:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Mingxia" X-Patchwork-Id: 124008 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4E29B41CA9; Thu, 16 Feb 2023 02:28:18 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1858B42D2C; Thu, 16 Feb 2023 02:27:59 +0100 (CET) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id C23E442D10 for ; Thu, 16 Feb 2023 02:27:55 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676510876; x=1708046876; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=E0KQJecbykKQULX6yAvZFrbi/MkGI+Z3oSVBFnxmfEQ=; b=myVmAFu4L9nHgaLKtgDDD6brkXnNQahBbqoCAct7TiFa91xaNzfpWADP 1nr06WYb96qMFBx6QDQUwmE7DdQ55iTlLSmrP+aoAlt9QGswDds5PkxBR O1jCG+WM/SCQnzefv4eLXAsA5L+gpwgvRQn5w2GCJyRX8/JkNSgg/35uG yxN8babD6dA3wjP7XKycvBM2zei0ykty5oJgw82QsCnhN/jbhtHxfy2Rr SiZhNa8gFmHgqLL9zg6sADIw3PrTPqzrhP3eyzA22N83adPW8yFSLNBwS lB4RsWOCrCliFpaYo4bh+b+Rmi9ZcW6qeKP9tJHgecEkI6KkMcy09ZBdv g==; X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="329315377" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="329315377" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2023 17:27:54 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="779166200" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="779166200" Received: from dpdk-mingxial-01.sh.intel.com ([10.67.119.167]) by fmsmga002.fm.intel.com with ESMTP; 15 Feb 2023 17:27:53 -0800 From: Mingxia Liu To: dev@dpdk.org, beilei.xing@intel.com, yuying.zhang@intel.com Cc: Mingxia Liu Subject: [PATCH v7 04/21] net/cpfl: support device start and stop Date: Thu, 16 Feb 2023 00:29:53 +0000 Message-Id: <20230216003010.3439881-5-mingxia.liu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230216003010.3439881-1-mingxia.liu@intel.com> References: <20230213021956.2953088-1-mingxia.liu@intel.com> <20230216003010.3439881-1-mingxia.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add dev ops dev_start, dev_stop and link_update. Signed-off-by: Mingxia Liu --- drivers/net/cpfl/cpfl_ethdev.c | 35 ++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index 3029f03d02..d1dfcfff9b 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -184,12 +184,45 @@ cpfl_dev_configure(struct rte_eth_dev *dev) return 0; } +static int +cpfl_dev_start(struct rte_eth_dev *dev) +{ + struct idpf_vport *vport = dev->data->dev_private; + int ret; + + ret = idpf_vc_vport_ena_dis(vport, true); + if (ret != 0) { + PMD_DRV_LOG(ERR, "Failed to enable vport"); + return ret; + } + + vport->stopped = 0; + + return 0; +} + +static int +cpfl_dev_stop(struct rte_eth_dev *dev) +{ + struct idpf_vport *vport = dev->data->dev_private; + + if (vport->stopped == 1) + return 0; + + idpf_vc_vport_ena_dis(vport, false); + + vport->stopped = 1; + + return 0; +} + static int cpfl_dev_close(struct rte_eth_dev *dev) { struct idpf_vport *vport = dev->data->dev_private; struct cpfl_adapter_ext *adapter = CPFL_ADAPTER_TO_EXT(vport->adapter); + cpfl_dev_stop(dev); idpf_vport_deinit(vport); adapter->cur_vports &= ~RTE_BIT32(vport->devarg_id); @@ -538,6 +571,8 @@ static const struct eth_dev_ops cpfl_eth_dev_ops = { .rx_queue_setup = cpfl_rx_queue_setup, .tx_queue_setup = cpfl_tx_queue_setup, .dev_infos_get = cpfl_dev_info_get, + .dev_start = cpfl_dev_start, + .dev_stop = cpfl_dev_stop, .link_update = cpfl_dev_link_update, .dev_supported_ptypes_get = cpfl_dev_supported_ptypes_get, }; From patchwork Thu Feb 16 00:29:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Mingxia" X-Patchwork-Id: 124009 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E74F941CA9; Thu, 16 Feb 2023 02:28:25 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 34D6542D31; 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15 Feb 2023 17:27:56 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="779166219" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="779166219" Received: from dpdk-mingxial-01.sh.intel.com ([10.67.119.167]) by fmsmga002.fm.intel.com with ESMTP; 15 Feb 2023 17:27:55 -0800 From: Mingxia Liu To: dev@dpdk.org, beilei.xing@intel.com, yuying.zhang@intel.com Cc: Mingxia Liu Subject: [PATCH v7 05/21] net/cpfl: support queue start Date: Thu, 16 Feb 2023 00:29:54 +0000 Message-Id: <20230216003010.3439881-6-mingxia.liu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230216003010.3439881-1-mingxia.liu@intel.com> References: <20230213021956.2953088-1-mingxia.liu@intel.com> <20230216003010.3439881-1-mingxia.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for these device ops: - rx_queue_start - tx_queue_start Signed-off-by: Mingxia Liu --- drivers/net/cpfl/cpfl_ethdev.c | 41 ++++++++++ drivers/net/cpfl/cpfl_rxtx.c | 138 +++++++++++++++++++++++++++++++++ drivers/net/cpfl/cpfl_rxtx.h | 4 + 3 files changed, 183 insertions(+) diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index d1dfcfff9b..c4565e687b 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -184,12 +184,51 @@ cpfl_dev_configure(struct rte_eth_dev *dev) return 0; } +static int +cpfl_start_queues(struct rte_eth_dev *dev) +{ + struct idpf_rx_queue *rxq; + struct idpf_tx_queue *txq; + int err = 0; + int i; + + for (i = 0; i < dev->data->nb_tx_queues; i++) { + txq = dev->data->tx_queues[i]; + if (txq == NULL || txq->tx_deferred_start) + continue; + err = cpfl_tx_queue_start(dev, i); + if (err != 0) { + PMD_DRV_LOG(ERR, "Fail to start Tx queue %u", i); + return err; + } + } + + for (i = 0; i < dev->data->nb_rx_queues; i++) { + rxq = dev->data->rx_queues[i]; + if (rxq == NULL || rxq->rx_deferred_start) + continue; + err = cpfl_rx_queue_start(dev, i); + if (err != 0) { + PMD_DRV_LOG(ERR, "Fail to start Rx queue %u", i); + return err; + } + } + + return err; +} + static int cpfl_dev_start(struct rte_eth_dev *dev) { struct idpf_vport *vport = dev->data->dev_private; int ret; + ret = cpfl_start_queues(dev); + if (ret != 0) { + PMD_DRV_LOG(ERR, "Failed to start queues"); + return ret; + } + ret = idpf_vc_vport_ena_dis(vport, true); if (ret != 0) { PMD_DRV_LOG(ERR, "Failed to enable vport"); @@ -574,6 +613,8 @@ static const struct eth_dev_ops cpfl_eth_dev_ops = { .dev_start = cpfl_dev_start, .dev_stop = cpfl_dev_stop, .link_update = cpfl_dev_link_update, + .rx_queue_start = cpfl_rx_queue_start, + .tx_queue_start = cpfl_tx_queue_start, .dev_supported_ptypes_get = cpfl_dev_supported_ptypes_get, }; diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c index 042b848ce2..e306a52b31 100644 --- a/drivers/net/cpfl/cpfl_rxtx.c +++ b/drivers/net/cpfl/cpfl_rxtx.c @@ -474,3 +474,141 @@ cpfl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, err_txq_alloc: return ret; } + +int +cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id) +{ + struct idpf_rx_queue *rxq; + int err; + + if (rx_queue_id >= dev->data->nb_rx_queues) + return -EINVAL; + + rxq = dev->data->rx_queues[rx_queue_id]; + + if (rxq == NULL || !rxq->q_set) { + PMD_DRV_LOG(ERR, "RX queue %u not available or setup", + rx_queue_id); + return -EINVAL; + } + + if (rxq->bufq1 == NULL) { + /* Single queue */ + err = idpf_qc_single_rxq_mbufs_alloc(rxq); + if (err != 0) { + PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf"); + return err; + } + + rte_wmb(); + + /* Init the RX tail register. */ + IDPF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1); + } else { + /* Split queue */ + err = idpf_qc_split_rxq_mbufs_alloc(rxq->bufq1); + if (err != 0) { + PMD_DRV_LOG(ERR, "Failed to allocate RX buffer queue mbuf"); + return err; + } + err = idpf_qc_split_rxq_mbufs_alloc(rxq->bufq2); + if (err != 0) { + PMD_DRV_LOG(ERR, "Failed to allocate RX buffer queue mbuf"); + return err; + } + + rte_wmb(); + + /* Init the RX tail register. */ + IDPF_PCI_REG_WRITE(rxq->bufq1->qrx_tail, rxq->bufq1->rx_tail); + IDPF_PCI_REG_WRITE(rxq->bufq2->qrx_tail, rxq->bufq2->rx_tail); + } + + return err; +} + +int +cpfl_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id) +{ + struct idpf_vport *vport = dev->data->dev_private; + struct idpf_rx_queue *rxq = + dev->data->rx_queues[rx_queue_id]; + int err = 0; + + err = idpf_vc_rxq_config(vport, rxq); + if (err != 0) { + PMD_DRV_LOG(ERR, "Fail to configure Rx queue %u", rx_queue_id); + return err; + } + + err = cpfl_rx_queue_init(dev, rx_queue_id); + if (err != 0) { + PMD_DRV_LOG(ERR, "Failed to init RX queue %u", + rx_queue_id); + return err; + } + + /* Ready to switch the queue on */ + err = idpf_vc_queue_switch(vport, rx_queue_id, true, true); + if (err != 0) { + PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on", + rx_queue_id); + } else { + rxq->q_started = true; + dev->data->rx_queue_state[rx_queue_id] = + RTE_ETH_QUEUE_STATE_STARTED; + } + + return err; +} + +int +cpfl_tx_queue_init(struct rte_eth_dev *dev, uint16_t tx_queue_id) +{ + struct idpf_tx_queue *txq; + + if (tx_queue_id >= dev->data->nb_tx_queues) + return -EINVAL; + + txq = dev->data->tx_queues[tx_queue_id]; + + /* Init the RX tail register. */ + IDPF_PCI_REG_WRITE(txq->qtx_tail, 0); + + return 0; +} + +int +cpfl_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) +{ + struct idpf_vport *vport = dev->data->dev_private; + struct idpf_tx_queue *txq = + dev->data->tx_queues[tx_queue_id]; + int err = 0; + + err = idpf_vc_txq_config(vport, txq); + if (err != 0) { + PMD_DRV_LOG(ERR, "Fail to configure Tx queue %u", tx_queue_id); + return err; + } + + err = cpfl_tx_queue_init(dev, tx_queue_id); + if (err != 0) { + PMD_DRV_LOG(ERR, "Failed to init TX queue %u", + tx_queue_id); + return err; + } + + /* Ready to switch the queue on */ + err = idpf_vc_queue_switch(vport, tx_queue_id, false, true); + if (err != 0) { + PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on", + tx_queue_id); + } else { + txq->q_started = true; + dev->data->tx_queue_state[tx_queue_id] = + RTE_ETH_QUEUE_STATE_STARTED; + } + + return err; +} diff --git a/drivers/net/cpfl/cpfl_rxtx.h b/drivers/net/cpfl/cpfl_rxtx.h index e0221abfa3..716b2fefa4 100644 --- a/drivers/net/cpfl/cpfl_rxtx.h +++ b/drivers/net/cpfl/cpfl_rxtx.h @@ -28,4 +28,8 @@ int cpfl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, uint16_t nb_desc, unsigned int socket_id, const struct rte_eth_rxconf *rx_conf, struct rte_mempool *mp); +int cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id); +int cpfl_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id); +int cpfl_tx_queue_init(struct rte_eth_dev *dev, uint16_t tx_queue_id); +int cpfl_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id); #endif /* _CPFL_RXTX_H_ */ From patchwork Thu Feb 16 00:29:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Mingxia" X-Patchwork-Id: 124010 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 89E8541CA9; Thu, 16 Feb 2023 02:28:36 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C1CFB42D1A; Thu, 16 Feb 2023 02:28:03 +0100 (CET) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id 6519042D1A for ; Thu, 16 Feb 2023 02:27:59 +0100 (CET) DKIM-Signature: v=1; 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d="scan'208";a="779166224" Received: from dpdk-mingxial-01.sh.intel.com ([10.67.119.167]) by fmsmga002.fm.intel.com with ESMTP; 15 Feb 2023 17:27:56 -0800 From: Mingxia Liu To: dev@dpdk.org, beilei.xing@intel.com, yuying.zhang@intel.com Cc: Mingxia Liu Subject: [PATCH v7 06/21] net/cpfl: support queue stop Date: Thu, 16 Feb 2023 00:29:55 +0000 Message-Id: <20230216003010.3439881-7-mingxia.liu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230216003010.3439881-1-mingxia.liu@intel.com> References: <20230213021956.2953088-1-mingxia.liu@intel.com> <20230216003010.3439881-1-mingxia.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for these device ops: - rx_queue_stop - tx_queue_stop Signed-off-by: Mingxia Liu --- drivers/net/cpfl/cpfl_ethdev.c | 10 +++- drivers/net/cpfl/cpfl_rxtx.c | 87 ++++++++++++++++++++++++++++++++++ drivers/net/cpfl/cpfl_rxtx.h | 3 ++ 3 files changed, 99 insertions(+), 1 deletion(-) diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index c4565e687b..f757fea530 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -232,12 +232,16 @@ cpfl_dev_start(struct rte_eth_dev *dev) ret = idpf_vc_vport_ena_dis(vport, true); if (ret != 0) { PMD_DRV_LOG(ERR, "Failed to enable vport"); - return ret; + goto err_vport; } vport->stopped = 0; return 0; + +err_vport: + cpfl_stop_queues(dev); + return ret; } static int @@ -250,6 +254,8 @@ cpfl_dev_stop(struct rte_eth_dev *dev) idpf_vc_vport_ena_dis(vport, false); + cpfl_stop_queues(dev); + vport->stopped = 1; return 0; @@ -615,6 +621,8 @@ static const struct eth_dev_ops cpfl_eth_dev_ops = { .link_update = cpfl_dev_link_update, .rx_queue_start = cpfl_rx_queue_start, .tx_queue_start = cpfl_tx_queue_start, + .rx_queue_stop = cpfl_rx_queue_stop, + .tx_queue_stop = cpfl_tx_queue_stop, .dev_supported_ptypes_get = cpfl_dev_supported_ptypes_get, }; diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c index e306a52b31..de0f2a5723 100644 --- a/drivers/net/cpfl/cpfl_rxtx.c +++ b/drivers/net/cpfl/cpfl_rxtx.c @@ -612,3 +612,90 @@ cpfl_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) return err; } + +int +cpfl_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id) +{ + struct idpf_vport *vport = dev->data->dev_private; + struct idpf_rx_queue *rxq; + int err; + + if (rx_queue_id >= dev->data->nb_rx_queues) + return -EINVAL; + + err = idpf_vc_queue_switch(vport, rx_queue_id, true, false); + if (err != 0) { + PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off", + rx_queue_id); + return err; + } + + rxq = dev->data->rx_queues[rx_queue_id]; + if (vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SINGLE) { + rxq->ops->release_mbufs(rxq); + idpf_qc_single_rx_queue_reset(rxq); + } else { + rxq->bufq1->ops->release_mbufs(rxq->bufq1); + rxq->bufq2->ops->release_mbufs(rxq->bufq2); + idpf_qc_split_rx_queue_reset(rxq); + } + dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; + + return 0; +} + +int +cpfl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id) +{ + struct idpf_vport *vport = dev->data->dev_private; + struct idpf_tx_queue *txq; + int err; + + if (tx_queue_id >= dev->data->nb_tx_queues) + return -EINVAL; + + err = idpf_vc_queue_switch(vport, tx_queue_id, false, false); + if (err != 0) { + PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off", + tx_queue_id); + return err; + } + + txq = dev->data->tx_queues[tx_queue_id]; + txq->ops->release_mbufs(txq); + if (vport->txq_model == VIRTCHNL2_QUEUE_MODEL_SINGLE) { + idpf_qc_single_tx_queue_reset(txq); + } else { + idpf_qc_split_tx_descq_reset(txq); + idpf_qc_split_tx_complq_reset(txq->complq); + } + dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; + + return 0; +} + +void +cpfl_stop_queues(struct rte_eth_dev *dev) +{ + struct idpf_rx_queue *rxq; + struct idpf_tx_queue *txq; + int i; + + for (i = 0; i < dev->data->nb_rx_queues; i++) { + rxq = dev->data->rx_queues[i]; + if (rxq == NULL) + continue; + + if (cpfl_rx_queue_stop(dev, i) != 0) + PMD_DRV_LOG(WARNING, "Fail to stop Rx queue %d", i); + } + + for (i = 0; i < dev->data->nb_tx_queues; i++) { + txq = dev->data->tx_queues[i]; + if (txq == NULL) + continue; + + if (cpfl_tx_queue_stop(dev, i) != 0) + PMD_DRV_LOG(WARNING, "Fail to stop Tx queue %d", i); + } +} diff --git a/drivers/net/cpfl/cpfl_rxtx.h b/drivers/net/cpfl/cpfl_rxtx.h index 716b2fefa4..e9b810deaa 100644 --- a/drivers/net/cpfl/cpfl_rxtx.h +++ b/drivers/net/cpfl/cpfl_rxtx.h @@ -32,4 +32,7 @@ int cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id); int cpfl_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id); int cpfl_tx_queue_init(struct rte_eth_dev *dev, uint16_t tx_queue_id); int cpfl_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id); +void cpfl_stop_queues(struct rte_eth_dev *dev); +int cpfl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id); +int cpfl_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id); #endif /* _CPFL_RXTX_H_ */ From patchwork Thu Feb 16 00:29:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Mingxia" X-Patchwork-Id: 124011 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D28C341CA9; Thu, 16 Feb 2023 02:28:43 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E582B42D49; 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15 Feb 2023 17:27:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="779166235" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="779166235" Received: from dpdk-mingxial-01.sh.intel.com ([10.67.119.167]) by fmsmga002.fm.intel.com with ESMTP; 15 Feb 2023 17:27:57 -0800 From: Mingxia Liu To: dev@dpdk.org, beilei.xing@intel.com, yuying.zhang@intel.com Cc: Mingxia Liu Subject: [PATCH v7 07/21] net/cpfl: support queue release Date: Thu, 16 Feb 2023 00:29:56 +0000 Message-Id: <20230216003010.3439881-8-mingxia.liu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230216003010.3439881-1-mingxia.liu@intel.com> References: <20230213021956.2953088-1-mingxia.liu@intel.com> <20230216003010.3439881-1-mingxia.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for queue operations: - rx_queue_release - tx_queue_release Signed-off-by: Mingxia Liu --- drivers/net/cpfl/cpfl_ethdev.c | 2 ++ drivers/net/cpfl/cpfl_rxtx.c | 35 ++++++++++++++++++++++++++++++++++ drivers/net/cpfl/cpfl_rxtx.h | 2 ++ 3 files changed, 39 insertions(+) diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index f757fea530..2e5bfac1c0 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -623,6 +623,8 @@ static const struct eth_dev_ops cpfl_eth_dev_ops = { .tx_queue_start = cpfl_tx_queue_start, .rx_queue_stop = cpfl_rx_queue_stop, .tx_queue_stop = cpfl_tx_queue_stop, + .rx_queue_release = cpfl_dev_rx_queue_release, + .tx_queue_release = cpfl_dev_tx_queue_release, .dev_supported_ptypes_get = cpfl_dev_supported_ptypes_get, }; diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c index de0f2a5723..3edba70b16 100644 --- a/drivers/net/cpfl/cpfl_rxtx.c +++ b/drivers/net/cpfl/cpfl_rxtx.c @@ -49,6 +49,14 @@ cpfl_tx_offload_convert(uint64_t offload) return ol; } +static const struct idpf_rxq_ops def_rxq_ops = { + .release_mbufs = idpf_qc_rxq_mbufs_release, +}; + +static const struct idpf_txq_ops def_txq_ops = { + .release_mbufs = idpf_qc_txq_mbufs_release, +}; + static const struct rte_memzone * cpfl_dma_zone_reserve(struct rte_eth_dev *dev, uint16_t queue_idx, uint16_t len, uint16_t queue_type, @@ -177,6 +185,7 @@ cpfl_rx_split_bufq_setup(struct rte_eth_dev *dev, struct idpf_rx_queue *rxq, idpf_qc_split_rx_bufq_reset(bufq); bufq->qrx_tail = hw->hw_addr + (vport->chunks_info.rx_buf_qtail_start + queue_idx * vport->chunks_info.rx_buf_qtail_spacing); + bufq->ops = &def_rxq_ops; bufq->q_set = true; if (bufq_id == 1) { @@ -235,6 +244,12 @@ cpfl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, if (idpf_qc_rx_thresh_check(nb_desc, rx_free_thresh) != 0) return -EINVAL; + /* Free memory if needed */ + if (dev->data->rx_queues[queue_idx] != NULL) { + idpf_qc_rx_queue_release(dev->data->rx_queues[queue_idx]); + dev->data->rx_queues[queue_idx] = NULL; + } + /* Setup Rx queue */ rxq = rte_zmalloc_socket("cpfl rxq", sizeof(struct idpf_rx_queue), @@ -287,6 +302,7 @@ cpfl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, idpf_qc_single_rx_queue_reset(rxq); rxq->qrx_tail = hw->hw_addr + (vport->chunks_info.rx_qtail_start + queue_idx * vport->chunks_info.rx_qtail_spacing); + rxq->ops = &def_rxq_ops; } else { idpf_qc_split_rx_descq_reset(rxq); @@ -399,6 +415,12 @@ cpfl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, if (idpf_qc_tx_thresh_check(nb_desc, tx_rs_thresh, tx_free_thresh) != 0) return -EINVAL; + /* Free memory if needed. */ + if (dev->data->tx_queues[queue_idx] != NULL) { + idpf_qc_tx_queue_release(dev->data->tx_queues[queue_idx]); + dev->data->tx_queues[queue_idx] = NULL; + } + /* Allocate the TX queue data structure. */ txq = rte_zmalloc_socket("cpfl txq", sizeof(struct idpf_tx_queue), @@ -461,6 +483,7 @@ cpfl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, txq->qtx_tail = hw->hw_addr + (vport->chunks_info.tx_qtail_start + queue_idx * vport->chunks_info.tx_qtail_spacing); + txq->ops = &def_txq_ops; txq->q_set = true; dev->data->tx_queues[queue_idx] = txq; @@ -674,6 +697,18 @@ cpfl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id) return 0; } +void +cpfl_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid) +{ + idpf_qc_rx_queue_release(dev->data->rx_queues[qid]); +} + +void +cpfl_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid) +{ + idpf_qc_tx_queue_release(dev->data->tx_queues[qid]); +} + void cpfl_stop_queues(struct rte_eth_dev *dev) { diff --git a/drivers/net/cpfl/cpfl_rxtx.h b/drivers/net/cpfl/cpfl_rxtx.h index e9b810deaa..f5882401dc 100644 --- a/drivers/net/cpfl/cpfl_rxtx.h +++ b/drivers/net/cpfl/cpfl_rxtx.h @@ -35,4 +35,6 @@ int cpfl_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id); void cpfl_stop_queues(struct rte_eth_dev *dev); int cpfl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id); int cpfl_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id); +void cpfl_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid); +void cpfl_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid); #endif /* _CPFL_RXTX_H_ */ From patchwork Thu Feb 16 00:29:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Mingxia" X-Patchwork-Id: 124012 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 80A8F41CA9; Thu, 16 Feb 2023 02:28:51 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0C2AF42D4B; Thu, 16 Feb 2023 02:28:06 +0100 (CET) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id 0926942C4D for ; Thu, 16 Feb 2023 02:28:00 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676510881; 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15 Feb 2023 17:27:59 -0800 From: Mingxia Liu To: dev@dpdk.org, beilei.xing@intel.com, yuying.zhang@intel.com Cc: Mingxia Liu Subject: [PATCH v7 08/21] net/cpfl: support MTU configuration Date: Thu, 16 Feb 2023 00:29:57 +0000 Message-Id: <20230216003010.3439881-9-mingxia.liu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230216003010.3439881-1-mingxia.liu@intel.com> References: <20230213021956.2953088-1-mingxia.liu@intel.com> <20230216003010.3439881-1-mingxia.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add dev ops mtu_set. Signed-off-by: Mingxia Liu --- doc/guides/nics/features/cpfl.ini | 1 + drivers/net/cpfl/cpfl_ethdev.c | 27 +++++++++++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/doc/guides/nics/features/cpfl.ini b/doc/guides/nics/features/cpfl.ini index a2d1ca9e15..470ba81579 100644 --- a/doc/guides/nics/features/cpfl.ini +++ b/doc/guides/nics/features/cpfl.ini @@ -7,6 +7,7 @@ ; is selected. ; [Features] +MTU update = Y Linux = Y x86-32 = Y x86-64 = Y diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index 2e5bfac1c0..e2eb92c738 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -121,6 +121,27 @@ cpfl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) return 0; } +static int +cpfl_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) +{ + struct idpf_vport *vport = dev->data->dev_private; + + /* mtu setting is forbidden if port is start */ + if (dev->data->dev_started) { + PMD_DRV_LOG(ERR, "port must be stopped before configuration"); + return -EBUSY; + } + + if (mtu > vport->max_mtu) { + PMD_DRV_LOG(ERR, "MTU should be less than %d", vport->max_mtu); + return -EINVAL; + } + + vport->max_pkt_len = mtu + CPFL_ETH_OVERHEAD; + + return 0; +} + static const uint32_t * cpfl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused) { @@ -142,6 +163,7 @@ cpfl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused) static int cpfl_dev_configure(struct rte_eth_dev *dev) { + struct idpf_vport *vport = dev->data->dev_private; struct rte_eth_conf *conf = &dev->data->dev_conf; if (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) { @@ -181,6 +203,10 @@ cpfl_dev_configure(struct rte_eth_dev *dev) return -ENOTSUP; } + vport->max_pkt_len = + (dev->data->mtu == 0) ? CPFL_DEFAULT_MTU : dev->data->mtu + + CPFL_ETH_OVERHEAD; + return 0; } @@ -625,6 +651,7 @@ static const struct eth_dev_ops cpfl_eth_dev_ops = { .tx_queue_stop = cpfl_tx_queue_stop, .rx_queue_release = cpfl_dev_rx_queue_release, .tx_queue_release = cpfl_dev_tx_queue_release, + .mtu_set = cpfl_dev_mtu_set, .dev_supported_ptypes_get = cpfl_dev_supported_ptypes_get, }; From patchwork Thu Feb 16 00:29:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Mingxia" X-Patchwork-Id: 124013 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BFE0E41CA9; Thu, 16 Feb 2023 02:28:58 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4E2C942D3D; Thu, 16 Feb 2023 02:28:08 +0100 (CET) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id 58EEB42D2F for ; Thu, 16 Feb 2023 02:28:01 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676510883; x=1708046883; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TXxx10lBKM7k0klxnN7BYJB9HMnbMU26iUrDOhRV81k=; b=QVqa7hUZpnTZFOkfy5beBDCkytzLRUfy+yTAZy9OxhuMBPrpIMK+X5h2 G6wuJAa8yu6zneoZU0SE/XD6TJk5LzXw/G0MP679ugTYy0+uBq8nOYVmP CbeCk4RN3ObfhT8zIxO430+B/qSj3oLQ9+m+laXl2QZPhjvkdH4zRF1j8 P1YBciCZzgef0Hqp3ot/2PhFvDH6as6fc8sQe/cDuIaWuk+BPI3xcWmdZ Dx1V5vLVS1/zJ1gaAe8Pra5odXkrDdzFJUYBqhnoxb9jvr9NAT5UriOpb 2MmZ5aibmlvmiWASbR8s+aPr7uOIYO4OzoqH4EEVJu/7wMNFvy28VXXtJ g==; X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="329315420" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="329315420" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2023 17:28:01 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="779166249" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="779166249" Received: from dpdk-mingxial-01.sh.intel.com ([10.67.119.167]) by fmsmga002.fm.intel.com with ESMTP; 15 Feb 2023 17:28:00 -0800 From: Mingxia Liu To: dev@dpdk.org, beilei.xing@intel.com, yuying.zhang@intel.com Cc: Mingxia Liu Subject: [PATCH v7 09/21] net/cpfl: support basic Rx data path Date: Thu, 16 Feb 2023 00:29:58 +0000 Message-Id: <20230216003010.3439881-10-mingxia.liu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230216003010.3439881-1-mingxia.liu@intel.com> References: <20230213021956.2953088-1-mingxia.liu@intel.com> <20230216003010.3439881-1-mingxia.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add basic Rx support in split queue mode and single queue mode. Signed-off-by: Mingxia Liu --- drivers/net/cpfl/cpfl_ethdev.c | 2 ++ drivers/net/cpfl/cpfl_rxtx.c | 18 ++++++++++++++++++ drivers/net/cpfl/cpfl_rxtx.h | 1 + 3 files changed, 21 insertions(+) diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index e2eb92c738..ba66b284cc 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -255,6 +255,8 @@ cpfl_dev_start(struct rte_eth_dev *dev) return ret; } + cpfl_set_rx_function(dev); + ret = idpf_vc_vport_ena_dis(vport, true); if (ret != 0) { PMD_DRV_LOG(ERR, "Failed to enable vport"); diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c index 3edba70b16..568ae3ec68 100644 --- a/drivers/net/cpfl/cpfl_rxtx.c +++ b/drivers/net/cpfl/cpfl_rxtx.c @@ -734,3 +734,21 @@ cpfl_stop_queues(struct rte_eth_dev *dev) PMD_DRV_LOG(WARNING, "Fail to stop Tx queue %d", i); } } + +void +cpfl_set_rx_function(struct rte_eth_dev *dev) +{ + struct idpf_vport *vport = dev->data->dev_private; + + if (vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT) { + PMD_DRV_LOG(NOTICE, + "Using Split Scalar Rx (port %d).", + dev->data->port_id); + dev->rx_pkt_burst = idpf_dp_splitq_recv_pkts; + } else { + PMD_DRV_LOG(NOTICE, + "Using Single Scalar Rx (port %d).", + dev->data->port_id); + dev->rx_pkt_burst = idpf_dp_singleq_recv_pkts; + } +} diff --git a/drivers/net/cpfl/cpfl_rxtx.h b/drivers/net/cpfl/cpfl_rxtx.h index f5882401dc..a5dd388e1f 100644 --- a/drivers/net/cpfl/cpfl_rxtx.h +++ b/drivers/net/cpfl/cpfl_rxtx.h @@ -37,4 +37,5 @@ int cpfl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id); int cpfl_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id); void cpfl_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid); void cpfl_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid); +void cpfl_set_rx_function(struct rte_eth_dev *dev); #endif /* _CPFL_RXTX_H_ */ From patchwork Thu Feb 16 00:29:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Mingxia" X-Patchwork-Id: 124014 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BC4F741CA9; Thu, 16 Feb 2023 02:29:04 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6642742D55; Thu, 16 Feb 2023 02:28:09 +0100 (CET) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id 217E542D43 for ; Thu, 16 Feb 2023 02:28:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676510884; x=1708046884; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LvDyihD1fQCzW0eXlObQUBK0oeX2gCgJX7YE6s6Dem0=; b=mkkYkLjG89Uf96u2gfqFupLP5dNl2zrunAPZvpyNGTPE3/sXZO5RpNgB yiQrJ4a6dqiyNHiGrr596npodmWt76r1s9UXDZ2TiePKBKiRqCXhHi+e4 OCGruiNM2WDwRVPWMqTzQyHK2EUTU1RVLRivyLm9kwASqB1Mvx2bcI/oR K0Ek0EZC8+e9fPhoUnXuGJPCngH/hpNw8E9pJFonkVKrJMrUIwwll4hhS QvuOftHclCaVAg7h2F+GsBTI/pwQRHIp2bEtlwAw1PCYbJHnUhplnpbBL 5H06QR2xRYxR/FpW/D0GvtG51KADj31XtMEXPze6kxp024OSIdxmoOqio w==; X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="329315428" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="329315428" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2023 17:28:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="779166259" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="779166259" Received: from dpdk-mingxial-01.sh.intel.com ([10.67.119.167]) by fmsmga002.fm.intel.com with ESMTP; 15 Feb 2023 17:28:01 -0800 From: Mingxia Liu To: dev@dpdk.org, beilei.xing@intel.com, yuying.zhang@intel.com Cc: Mingxia Liu Subject: [PATCH v7 10/21] net/cpfl: support basic Tx data path Date: Thu, 16 Feb 2023 00:29:59 +0000 Message-Id: <20230216003010.3439881-11-mingxia.liu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230216003010.3439881-1-mingxia.liu@intel.com> References: <20230213021956.2953088-1-mingxia.liu@intel.com> <20230216003010.3439881-1-mingxia.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add basic Tx support in split queue mode and single queue mode. Signed-off-by: Mingxia Liu --- drivers/net/cpfl/cpfl_ethdev.c | 3 +++ drivers/net/cpfl/cpfl_rxtx.c | 20 ++++++++++++++++++++ drivers/net/cpfl/cpfl_rxtx.h | 1 + 3 files changed, 24 insertions(+) diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index ba66b284cc..f02cbd08d9 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -97,6 +97,8 @@ cpfl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) dev_info->max_mtu = vport->max_mtu; dev_info->min_mtu = RTE_ETHER_MIN_MTU; + dev_info->tx_offload_capa = RTE_ETH_TX_OFFLOAD_MULTI_SEGS; + dev_info->default_txconf = (struct rte_eth_txconf) { .tx_free_thresh = CPFL_DEFAULT_TX_FREE_THRESH, .tx_rs_thresh = CPFL_DEFAULT_TX_RS_THRESH, @@ -256,6 +258,7 @@ cpfl_dev_start(struct rte_eth_dev *dev) } cpfl_set_rx_function(dev); + cpfl_set_tx_function(dev); ret = idpf_vc_vport_ena_dis(vport, true); if (ret != 0) { diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c index 568ae3ec68..c250642719 100644 --- a/drivers/net/cpfl/cpfl_rxtx.c +++ b/drivers/net/cpfl/cpfl_rxtx.c @@ -752,3 +752,23 @@ cpfl_set_rx_function(struct rte_eth_dev *dev) dev->rx_pkt_burst = idpf_dp_singleq_recv_pkts; } } + +void +cpfl_set_tx_function(struct rte_eth_dev *dev) +{ + struct idpf_vport *vport = dev->data->dev_private; + + if (vport->txq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT) { + PMD_DRV_LOG(NOTICE, + "Using Split Scalar Tx (port %d).", + dev->data->port_id); + dev->tx_pkt_burst = idpf_dp_splitq_xmit_pkts; + dev->tx_pkt_prepare = idpf_dp_prep_pkts; + } else { + PMD_DRV_LOG(NOTICE, + "Using Single Scalar Tx (port %d).", + dev->data->port_id); + dev->tx_pkt_burst = idpf_dp_singleq_xmit_pkts; + dev->tx_pkt_prepare = idpf_dp_prep_pkts; + } +} diff --git a/drivers/net/cpfl/cpfl_rxtx.h b/drivers/net/cpfl/cpfl_rxtx.h index a5dd388e1f..5f8144e55f 100644 --- a/drivers/net/cpfl/cpfl_rxtx.h +++ b/drivers/net/cpfl/cpfl_rxtx.h @@ -38,4 +38,5 @@ int cpfl_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id); void cpfl_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid); void cpfl_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid); void cpfl_set_rx_function(struct rte_eth_dev *dev); +void cpfl_set_tx_function(struct rte_eth_dev *dev); #endif /* _CPFL_RXTX_H_ */ From patchwork Thu Feb 16 00:30:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Mingxia" X-Patchwork-Id: 124015 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 141AB41CA9; Thu, 16 Feb 2023 02:29:11 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8060F42D5A; Thu, 16 Feb 2023 02:28:10 +0100 (CET) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id 20F1E42D29 for ; Thu, 16 Feb 2023 02:28:04 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676510885; x=1708046885; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fTy7/5iMqDZICBWMy6qJQ6SYB1Cmrp+HpdJsx0eanO4=; b=ciDwxK9HGN9VWceXkU7BpAhUvj7UDY9g7l5ZP/6/LgwqNLKMDcNUOKHs EPOhvrKgmHvuyCdcjMHVrgC4HoJuOKi8BjyOLpHeFsqLOTum7NJzjDPCl jIgQh40VZOuN3GeiQRt6JSGflpUb04pPKXt3R9ZUZFzNcUevs6/fkO2wd lo6wy+9loFU6X5AkdgQel+l3hFQqJWgcQyqlxn6sL8QV4AMPKir0t2/6n P7xCLfQI/hmlSRiMbM5NQRpAXNGzYGv3Q6nTIFMc0wzEyyvNB+ExhxozV ji7Bg8z//A84YVP7k5usLT+TsLQ1VrNazcZNtKABYiD5uk+ZtpgGtfmVu A==; X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="329315434" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="329315434" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2023 17:28:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="779166268" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="779166268" Received: from dpdk-mingxial-01.sh.intel.com ([10.67.119.167]) by fmsmga002.fm.intel.com with ESMTP; 15 Feb 2023 17:28:03 -0800 From: Mingxia Liu To: dev@dpdk.org, beilei.xing@intel.com, yuying.zhang@intel.com Cc: Mingxia Liu Subject: [PATCH v7 11/21] net/cpfl: support write back based on ITR expire Date: Thu, 16 Feb 2023 00:30:00 +0000 Message-Id: <20230216003010.3439881-12-mingxia.liu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230216003010.3439881-1-mingxia.liu@intel.com> References: <20230213021956.2953088-1-mingxia.liu@intel.com> <20230216003010.3439881-1-mingxia.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enable write back on ITR expire, then packets can be received one by Signed-off-by: Mingxia Liu --- drivers/net/cpfl/cpfl_ethdev.c | 45 +++++++++++++++++++++++++++++++++- drivers/net/cpfl/cpfl_ethdev.h | 2 ++ 2 files changed, 46 insertions(+), 1 deletion(-) diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index f02cbd08d9..7e0630c605 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -212,6 +212,15 @@ cpfl_dev_configure(struct rte_eth_dev *dev) return 0; } +static int +cpfl_config_rx_queues_irqs(struct rte_eth_dev *dev) +{ + struct idpf_vport *vport = dev->data->dev_private; + uint16_t nb_rx_queues = dev->data->nb_rx_queues; + + return idpf_vport_irq_map_config(vport, nb_rx_queues); +} + static int cpfl_start_queues(struct rte_eth_dev *dev) { @@ -249,12 +258,37 @@ static int cpfl_dev_start(struct rte_eth_dev *dev) { struct idpf_vport *vport = dev->data->dev_private; + struct idpf_adapter *base = vport->adapter; + struct cpfl_adapter_ext *adapter = CPFL_ADAPTER_TO_EXT(base); + uint16_t num_allocated_vectors = base->caps.num_allocated_vectors; + uint16_t req_vecs_num; int ret; + req_vecs_num = CPFL_DFLT_Q_VEC_NUM; + if (req_vecs_num + adapter->used_vecs_num > num_allocated_vectors) { + PMD_DRV_LOG(ERR, "The accumulated request vectors' number should be less than %d", + num_allocated_vectors); + ret = -EINVAL; + goto err_vec; + } + + ret = idpf_vc_vectors_alloc(vport, req_vecs_num); + if (ret != 0) { + PMD_DRV_LOG(ERR, "Failed to allocate interrupt vectors"); + goto err_vec; + } + adapter->used_vecs_num += req_vecs_num; + + ret = cpfl_config_rx_queues_irqs(dev); + if (ret != 0) { + PMD_DRV_LOG(ERR, "Failed to configure irqs"); + goto err_irq; + } + ret = cpfl_start_queues(dev); if (ret != 0) { PMD_DRV_LOG(ERR, "Failed to start queues"); - return ret; + goto err_startq; } cpfl_set_rx_function(dev); @@ -272,6 +306,11 @@ cpfl_dev_start(struct rte_eth_dev *dev) err_vport: cpfl_stop_queues(dev); +err_startq: + idpf_vport_irq_unmap_config(vport, dev->data->nb_rx_queues); +err_irq: + idpf_vc_vectors_dealloc(vport); +err_vec: return ret; } @@ -287,6 +326,10 @@ cpfl_dev_stop(struct rte_eth_dev *dev) cpfl_stop_queues(dev); + idpf_vport_irq_unmap_config(vport, dev->data->nb_rx_queues); + + idpf_vc_vectors_dealloc(vport); + vport->stopped = 1; return 0; diff --git a/drivers/net/cpfl/cpfl_ethdev.h b/drivers/net/cpfl/cpfl_ethdev.h index 9ca39b4558..cd7f560d19 100644 --- a/drivers/net/cpfl/cpfl_ethdev.h +++ b/drivers/net/cpfl/cpfl_ethdev.h @@ -24,6 +24,8 @@ #define CPFL_INVALID_VPORT_IDX 0xffff +#define CPFL_DFLT_Q_VEC_NUM 1 + #define CPFL_MIN_BUF_SIZE 1024 #define CPFL_MAX_FRAME_SIZE 9728 #define CPFL_DEFAULT_MTU RTE_ETHER_MTU From patchwork Thu Feb 16 00:30:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Mingxia" X-Patchwork-Id: 124016 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7DB3441CA9; Thu, 16 Feb 2023 02:29:19 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 39EB742D65; Thu, 16 Feb 2023 02:28:12 +0100 (CET) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id 7D66142D29 for ; Thu, 16 Feb 2023 02:28:06 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676510887; x=1708046887; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HaatzXZEppmQYzuWskP6Pu9tSUOZWpEXzQ8ZcB/su+8=; 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Signed-off-by: Mingxia Liu --- drivers/net/cpfl/cpfl_ethdev.c | 51 ++++++++++++++++++++++++++++++++++ drivers/net/cpfl/cpfl_ethdev.h | 15 ++++++++++ 2 files changed, 66 insertions(+) diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index 7e0630c605..fb15004e48 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -97,6 +97,8 @@ cpfl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) dev_info->max_mtu = vport->max_mtu; dev_info->min_mtu = RTE_ETHER_MIN_MTU; + dev_info->flow_type_rss_offloads = CPFL_RSS_OFFLOAD_ALL; + dev_info->tx_offload_capa = RTE_ETH_TX_OFFLOAD_MULTI_SEGS; dev_info->default_txconf = (struct rte_eth_txconf) { @@ -162,11 +164,49 @@ cpfl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused) return ptypes; } +static int +cpfl_init_rss(struct idpf_vport *vport) +{ + struct rte_eth_rss_conf *rss_conf; + struct rte_eth_dev_data *dev_data; + uint16_t i, nb_q; + int ret = 0; + + dev_data = vport->dev_data; + rss_conf = &dev_data->dev_conf.rx_adv_conf.rss_conf; + nb_q = dev_data->nb_rx_queues; + + if (rss_conf->rss_key == NULL) { + for (i = 0; i < vport->rss_key_size; i++) + vport->rss_key[i] = (uint8_t)rte_rand(); + } else if (rss_conf->rss_key_len != vport->rss_key_size) { + PMD_INIT_LOG(ERR, "Invalid RSS key length in RSS configuration, should be %d", + vport->rss_key_size); + return -EINVAL; + } else { + rte_memcpy(vport->rss_key, rss_conf->rss_key, + vport->rss_key_size); + } + + for (i = 0; i < vport->rss_lut_size; i++) + vport->rss_lut[i] = i % nb_q; + + vport->rss_hf = IDPF_DEFAULT_RSS_HASH_EXPANDED; + + ret = idpf_vport_rss_config(vport); + if (ret != 0) + PMD_INIT_LOG(ERR, "Failed to configure RSS"); + + return ret; +} + static int cpfl_dev_configure(struct rte_eth_dev *dev) { struct idpf_vport *vport = dev->data->dev_private; struct rte_eth_conf *conf = &dev->data->dev_conf; + struct idpf_adapter *adapter = vport->adapter; + int ret; if (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) { PMD_INIT_LOG(ERR, "Setting link speed is not supported"); @@ -205,6 +245,17 @@ cpfl_dev_configure(struct rte_eth_dev *dev) return -ENOTSUP; } + if (adapter->caps.rss_caps != 0 && dev->data->nb_rx_queues != 0) { + ret = cpfl_init_rss(vport); + if (ret != 0) { + PMD_INIT_LOG(ERR, "Failed to init rss"); + return ret; + } + } else { + PMD_INIT_LOG(ERR, "RSS is not supported."); + return -1; + } + vport->max_pkt_len = (dev->data->mtu == 0) ? CPFL_DEFAULT_MTU : dev->data->mtu + CPFL_ETH_OVERHEAD; diff --git a/drivers/net/cpfl/cpfl_ethdev.h b/drivers/net/cpfl/cpfl_ethdev.h index cd7f560d19..e00dff4bf0 100644 --- a/drivers/net/cpfl/cpfl_ethdev.h +++ b/drivers/net/cpfl/cpfl_ethdev.h @@ -36,6 +36,21 @@ #define CPFL_ETH_OVERHEAD \ (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + CPFL_VLAN_TAG_SIZE * 2) +#define CPFL_RSS_OFFLOAD_ALL ( \ + RTE_ETH_RSS_IPV4 | \ + RTE_ETH_RSS_FRAG_IPV4 | \ + RTE_ETH_RSS_NONFRAG_IPV4_TCP | \ + RTE_ETH_RSS_NONFRAG_IPV4_UDP | \ + RTE_ETH_RSS_NONFRAG_IPV4_SCTP | \ + RTE_ETH_RSS_NONFRAG_IPV4_OTHER | \ + RTE_ETH_RSS_IPV6 | \ + RTE_ETH_RSS_FRAG_IPV6 | \ + RTE_ETH_RSS_NONFRAG_IPV6_TCP | \ + RTE_ETH_RSS_NONFRAG_IPV6_UDP | \ + RTE_ETH_RSS_NONFRAG_IPV6_SCTP | \ + RTE_ETH_RSS_NONFRAG_IPV6_OTHER | \ + RTE_ETH_RSS_L2_PAYLOAD) + #define CPFL_ADAPTER_NAME_LEN (PCI_PRI_STR_SIZE + 1) #define CPFL_ALARM_INTERVAL 50000 /* us */ From patchwork Thu Feb 16 00:30:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Mingxia" X-Patchwork-Id: 124017 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 50FF041CA9; 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a="329315439" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="329315439" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2023 17:28:07 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="779166282" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="779166282" Received: from dpdk-mingxial-01.sh.intel.com ([10.67.119.167]) by fmsmga002.fm.intel.com with ESMTP; 15 Feb 2023 17:28:06 -0800 From: Mingxia Liu To: dev@dpdk.org, beilei.xing@intel.com, yuying.zhang@intel.com Cc: Mingxia Liu Subject: [PATCH v7 13/21] net/cpfl: support Rx offloading Date: Thu, 16 Feb 2023 00:30:02 +0000 Message-Id: <20230216003010.3439881-14-mingxia.liu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230216003010.3439881-1-mingxia.liu@intel.com> References: <20230213021956.2953088-1-mingxia.liu@intel.com> <20230216003010.3439881-1-mingxia.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add Rx offloading support: - support CHKSUM and RSS offload for split queue model - support CHKSUM offload for single queue model Signed-off-by: Mingxia Liu --- doc/guides/nics/features/cpfl.ini | 2 ++ drivers/net/cpfl/cpfl_ethdev.c | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/doc/guides/nics/features/cpfl.ini b/doc/guides/nics/features/cpfl.ini index 470ba81579..ee5948f444 100644 --- a/doc/guides/nics/features/cpfl.ini +++ b/doc/guides/nics/features/cpfl.ini @@ -8,6 +8,8 @@ ; [Features] MTU update = Y +L3 checksum offload = P +L4 checksum offload = P Linux = Y x86-32 = Y x86-64 = Y diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index fb15004e48..d0f90b7d2c 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -99,6 +99,12 @@ cpfl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) dev_info->flow_type_rss_offloads = CPFL_RSS_OFFLOAD_ALL; + dev_info->rx_offload_capa = + RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | + RTE_ETH_RX_OFFLOAD_UDP_CKSUM | + RTE_ETH_RX_OFFLOAD_TCP_CKSUM | + RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM; + dev_info->tx_offload_capa = RTE_ETH_TX_OFFLOAD_MULTI_SEGS; dev_info->default_txconf = (struct rte_eth_txconf) { From patchwork Thu Feb 16 00:30:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Mingxia" X-Patchwork-Id: 124018 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7CA9241CA9; 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a="329315441" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="329315441" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2023 17:28:08 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="779166288" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="779166288" Received: from dpdk-mingxial-01.sh.intel.com ([10.67.119.167]) by fmsmga002.fm.intel.com with ESMTP; 15 Feb 2023 17:28:07 -0800 From: Mingxia Liu To: dev@dpdk.org, beilei.xing@intel.com, yuying.zhang@intel.com Cc: Mingxia Liu Subject: [PATCH v7 14/21] net/cpfl: support Tx offloading Date: Thu, 16 Feb 2023 00:30:03 +0000 Message-Id: <20230216003010.3439881-15-mingxia.liu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230216003010.3439881-1-mingxia.liu@intel.com> References: <20230213021956.2953088-1-mingxia.liu@intel.com> <20230216003010.3439881-1-mingxia.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add Tx offloading support: - support TSO for single queue model and split queue model. Signed-off-by: Mingxia Liu --- doc/guides/nics/features/cpfl.ini | 1 + drivers/net/cpfl/cpfl_ethdev.c | 8 +++++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/doc/guides/nics/features/cpfl.ini b/doc/guides/nics/features/cpfl.ini index ee5948f444..f4e45c7c68 100644 --- a/doc/guides/nics/features/cpfl.ini +++ b/doc/guides/nics/features/cpfl.ini @@ -8,6 +8,7 @@ ; [Features] MTU update = Y +TSO = P L3 checksum offload = P L4 checksum offload = P Linux = Y diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index d0f90b7d2c..fda945d34b 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -105,7 +105,13 @@ cpfl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) RTE_ETH_RX_OFFLOAD_TCP_CKSUM | RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM; - dev_info->tx_offload_capa = RTE_ETH_TX_OFFLOAD_MULTI_SEGS; + dev_info->tx_offload_capa = + RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | + RTE_ETH_TX_OFFLOAD_UDP_CKSUM | + RTE_ETH_TX_OFFLOAD_TCP_CKSUM | + RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | + RTE_ETH_TX_OFFLOAD_TCP_TSO | + RTE_ETH_TX_OFFLOAD_MULTI_SEGS; dev_info->default_txconf = (struct rte_eth_txconf) { .tx_free_thresh = CPFL_DEFAULT_TX_FREE_THRESH, From patchwork Thu Feb 16 00:30:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Mingxia" X-Patchwork-Id: 124019 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4447D41CA9; Thu, 16 Feb 2023 02:29:41 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A5EC742D6D; Thu, 16 Feb 2023 02:28:18 +0100 (CET) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id 2492842D59 for ; Thu, 16 Feb 2023 02:28:10 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676510891; x=1708046891; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8llNR9ixfVdN/C7K3ClnvR/2I1HxTQIcJiT+1e1xuXU=; b=PACGM2Xp8oNVZwNHJEGPe1BU+6LSaKVyLJcs6xYoPLAJklmE3gWGu7Xg HfdvS+ZArsmOEegE8FMnOBBnE++7SYsqhciH8luBESFmF7/+fzHffi1z8 OKOilpzX9/yjcCo0khqeBKp07lX6eh8BDYsO+dRmp7Syov3e7Gp3BiQaJ wn+lMsjnaP3pBYIYyKwHweimeQz5Nl+DtgkONLykQ0K1AVw+2F0yChFtr QndYY+Xtyt/ZWnDvPW34rifwZ12+n77DQq2lNlynH2POTM7LuwrMQ0o4v U0ldO6R2CXg0KAW+qU2PgSYNOacc0IcQPu5K/YzdPB/sBY1UOK49p3Psj A==; X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="329315469" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="329315469" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2023 17:28:10 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="779166292" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="779166292" Received: from dpdk-mingxial-01.sh.intel.com ([10.67.119.167]) by fmsmga002.fm.intel.com with ESMTP; 15 Feb 2023 17:28:08 -0800 From: Mingxia Liu To: dev@dpdk.org, beilei.xing@intel.com, yuying.zhang@intel.com Cc: Mingxia Liu , Wenjun Wu Subject: [PATCH v7 15/21] net/cpfl: add AVX512 data path for single queue model Date: Thu, 16 Feb 2023 00:30:04 +0000 Message-Id: <20230216003010.3439881-16-mingxia.liu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230216003010.3439881-1-mingxia.liu@intel.com> References: <20230213021956.2953088-1-mingxia.liu@intel.com> <20230216003010.3439881-1-mingxia.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support of AVX512 vector data path for single queue model. Signed-off-by: Wenjun Wu Signed-off-by: Mingxia Liu --- doc/guides/nics/cpfl.rst | 24 +++++- drivers/net/cpfl/cpfl_ethdev.c | 3 +- drivers/net/cpfl/cpfl_rxtx.c | 94 ++++++++++++++++++++++ drivers/net/cpfl/cpfl_rxtx_vec_common.h | 100 ++++++++++++++++++++++++ drivers/net/cpfl/meson.build | 25 +++++- 5 files changed, 243 insertions(+), 3 deletions(-) create mode 100644 drivers/net/cpfl/cpfl_rxtx_vec_common.h diff --git a/doc/guides/nics/cpfl.rst b/doc/guides/nics/cpfl.rst index 7c5aff0789..f0018b41df 100644 --- a/doc/guides/nics/cpfl.rst +++ b/doc/guides/nics/cpfl.rst @@ -63,4 +63,26 @@ Runtime Config Options Driver compilation and testing ------------------------------ -Refer to the document :doc:`build_and_test` for details. \ No newline at end of file +Refer to the document :doc:`build_and_test` for details. + +Features +-------- + +Vector PMD +~~~~~~~~~~ + +Vector path for Rx and Tx path are selected automatically. +The paths are chosen based on 2 conditions: + +- ``CPU`` + + On the x86 platform, the driver checks if the CPU supports AVX512. + If the CPU supports AVX512 and EAL argument ``--force-max-simd-bitwidth`` + is set to 512, AVX512 paths will be chosen. + +- ``Offload features`` + + The supported HW offload features are described in the document cpfl.ini, + A value "P" means the offload feature is not supported by vector path. + If any not supported features are used, cpfl vector PMD is disabled + and the scalar paths are chosen. diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index fda945d34b..346af055cf 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -111,7 +111,8 @@ cpfl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) RTE_ETH_TX_OFFLOAD_TCP_CKSUM | RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | RTE_ETH_TX_OFFLOAD_TCP_TSO | - RTE_ETH_TX_OFFLOAD_MULTI_SEGS; + RTE_ETH_TX_OFFLOAD_MULTI_SEGS | + RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; dev_info->default_txconf = (struct rte_eth_txconf) { .tx_free_thresh = CPFL_DEFAULT_TX_FREE_THRESH, diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c index c250642719..cb7bbddb16 100644 --- a/drivers/net/cpfl/cpfl_rxtx.c +++ b/drivers/net/cpfl/cpfl_rxtx.c @@ -8,6 +8,7 @@ #include "cpfl_ethdev.h" #include "cpfl_rxtx.h" +#include "cpfl_rxtx_vec_common.h" static uint64_t cpfl_rx_offload_convert(uint64_t offload) @@ -735,11 +736,61 @@ cpfl_stop_queues(struct rte_eth_dev *dev) } } + void cpfl_set_rx_function(struct rte_eth_dev *dev) { struct idpf_vport *vport = dev->data->dev_private; +#ifdef RTE_ARCH_X86 + struct idpf_rx_queue *rxq; + int i; + + if (cpfl_rx_vec_dev_check_default(dev) == CPFL_VECTOR_PATH && + rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { + vport->rx_vec_allowed = true; + if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512) +#ifdef CC_AVX512_SUPPORT + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 && + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1) + vport->rx_use_avx512 = true; +#else + PMD_DRV_LOG(NOTICE, + "AVX512 is not supported in build env"); +#endif /* CC_AVX512_SUPPORT */ + } else { + vport->rx_vec_allowed = false; + } +#endif /* RTE_ARCH_X86 */ + +#ifdef RTE_ARCH_X86 + if (vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT) { + PMD_DRV_LOG(NOTICE, + "Using Split Scalar Rx (port %d).", + dev->data->port_id); + dev->rx_pkt_burst = idpf_dp_splitq_recv_pkts; + } else { + if (vport->rx_vec_allowed) { + for (i = 0; i < dev->data->nb_rx_queues; i++) { + rxq = dev->data->rx_queues[i]; + (void)idpf_qc_singleq_rx_vec_setup(rxq); + } +#ifdef CC_AVX512_SUPPORT + if (vport->rx_use_avx512) { + PMD_DRV_LOG(NOTICE, + "Using Single AVX512 Vector Rx (port %d).", + dev->data->port_id); + dev->rx_pkt_burst = idpf_dp_singleq_recv_pkts_avx512; + return; + } +#endif /* CC_AVX512_SUPPORT */ + } + PMD_DRV_LOG(NOTICE, + "Using Single Scalar Rx (port %d).", + dev->data->port_id); + dev->rx_pkt_burst = idpf_dp_singleq_recv_pkts; + } +#else if (vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT) { PMD_DRV_LOG(NOTICE, "Using Split Scalar Rx (port %d).", @@ -751,12 +802,35 @@ cpfl_set_rx_function(struct rte_eth_dev *dev) dev->data->port_id); dev->rx_pkt_burst = idpf_dp_singleq_recv_pkts; } +#endif /* RTE_ARCH_X86 */ } void cpfl_set_tx_function(struct rte_eth_dev *dev) { struct idpf_vport *vport = dev->data->dev_private; +#ifdef RTE_ARCH_X86 +#ifdef CC_AVX512_SUPPORT + struct idpf_tx_queue *txq; + int i; +#endif /* CC_AVX512_SUPPORT */ + + if (cpfl_tx_vec_dev_check_default(dev) == CPFL_VECTOR_PATH && + rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { + vport->tx_vec_allowed = true; + if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512) +#ifdef CC_AVX512_SUPPORT + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 && + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1) + vport->tx_use_avx512 = true; +#else + PMD_DRV_LOG(NOTICE, + "AVX512 is not supported in build env"); +#endif /* CC_AVX512_SUPPORT */ + } else { + vport->tx_vec_allowed = false; + } +#endif /* RTE_ARCH_X86 */ if (vport->txq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT) { PMD_DRV_LOG(NOTICE, @@ -765,6 +839,26 @@ cpfl_set_tx_function(struct rte_eth_dev *dev) dev->tx_pkt_burst = idpf_dp_splitq_xmit_pkts; dev->tx_pkt_prepare = idpf_dp_prep_pkts; } else { +#ifdef RTE_ARCH_X86 + if (vport->tx_vec_allowed) { +#ifdef CC_AVX512_SUPPORT + if (vport->tx_use_avx512) { + for (i = 0; i < dev->data->nb_tx_queues; i++) { + txq = dev->data->tx_queues[i]; + if (txq == NULL) + continue; + idpf_qc_tx_vec_avx512_setup(txq); + } + PMD_DRV_LOG(NOTICE, + "Using Single AVX512 Vector Tx (port %d).", + dev->data->port_id); + dev->tx_pkt_burst = idpf_dp_singleq_xmit_pkts_avx512; + dev->tx_pkt_prepare = idpf_dp_prep_pkts; + return; + } +#endif /* CC_AVX512_SUPPORT */ + } +#endif /* RTE_ARCH_X86 */ PMD_DRV_LOG(NOTICE, "Using Single Scalar Tx (port %d).", dev->data->port_id); diff --git a/drivers/net/cpfl/cpfl_rxtx_vec_common.h b/drivers/net/cpfl/cpfl_rxtx_vec_common.h new file mode 100644 index 0000000000..2d4c6a0ef3 --- /dev/null +++ b/drivers/net/cpfl/cpfl_rxtx_vec_common.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Intel Corporation + */ + +#ifndef _CPFL_RXTX_VEC_COMMON_H_ +#define _CPFL_RXTX_VEC_COMMON_H_ +#include +#include +#include + +#include "cpfl_ethdev.h" +#include "cpfl_rxtx.h" + +#ifndef __INTEL_COMPILER +#pragma GCC diagnostic ignored "-Wcast-qual" +#endif + +#define CPFL_SCALAR_PATH 0 +#define CPFL_VECTOR_PATH 1 +#define CPFL_RX_NO_VECTOR_FLAGS ( \ + RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | \ + RTE_ETH_RX_OFFLOAD_UDP_CKSUM | \ + RTE_ETH_RX_OFFLOAD_TCP_CKSUM | \ + RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | \ + RTE_ETH_RX_OFFLOAD_TIMESTAMP) +#define CPFL_TX_NO_VECTOR_FLAGS ( \ + RTE_ETH_TX_OFFLOAD_TCP_TSO | \ + RTE_ETH_TX_OFFLOAD_MULTI_SEGS) + +static inline int +cpfl_rx_vec_queue_default(struct idpf_rx_queue *rxq) +{ + if (rxq == NULL) + return CPFL_SCALAR_PATH; + + if (rte_is_power_of_2(rxq->nb_rx_desc) == 0) + return CPFL_SCALAR_PATH; + + if (rxq->rx_free_thresh < IDPF_VPMD_RX_MAX_BURST) + return CPFL_SCALAR_PATH; + + if ((rxq->nb_rx_desc % rxq->rx_free_thresh) != 0) + return CPFL_SCALAR_PATH; + + if ((rxq->offloads & CPFL_RX_NO_VECTOR_FLAGS) != 0) + return CPFL_SCALAR_PATH; + + return CPFL_VECTOR_PATH; +} + +static inline int +cpfl_tx_vec_queue_default(struct idpf_tx_queue *txq) +{ + if (txq == NULL) + return CPFL_SCALAR_PATH; + + if (txq->rs_thresh < IDPF_VPMD_TX_MAX_BURST || + (txq->rs_thresh & 3) != 0) + return CPFL_SCALAR_PATH; + + if ((txq->offloads & CPFL_TX_NO_VECTOR_FLAGS) != 0) + return CPFL_SCALAR_PATH; + + return CPFL_VECTOR_PATH; +} + +static inline int +cpfl_rx_vec_dev_check_default(struct rte_eth_dev *dev) +{ + struct idpf_rx_queue *rxq; + int i, ret = 0; + + for (i = 0; i < dev->data->nb_rx_queues; i++) { + rxq = dev->data->rx_queues[i]; + ret = (cpfl_rx_vec_queue_default(rxq)); + if (ret == CPFL_SCALAR_PATH) + return CPFL_SCALAR_PATH; + } + + return CPFL_VECTOR_PATH; +} + +static inline int +cpfl_tx_vec_dev_check_default(struct rte_eth_dev *dev) +{ + int i; + struct idpf_tx_queue *txq; + int ret = 0; + + for (i = 0; i < dev->data->nb_tx_queues; i++) { + txq = dev->data->tx_queues[i]; + ret = cpfl_tx_vec_queue_default(txq); + if (ret == CPFL_SCALAR_PATH) + return CPFL_SCALAR_PATH; + } + + return CPFL_VECTOR_PATH; +} + +#endif /*_CPFL_RXTX_VEC_COMMON_H_*/ diff --git a/drivers/net/cpfl/meson.build b/drivers/net/cpfl/meson.build index 1894423689..fbe6500826 100644 --- a/drivers/net/cpfl/meson.build +++ b/drivers/net/cpfl/meson.build @@ -7,9 +7,32 @@ if is_windows subdir_done() endif +if dpdk_conf.get('RTE_IOVA_AS_PA') == 0 + build = false + reason = 'driver does not support disabling IOVA as PA mode' + subdir_done() +endif + deps += ['common_idpf'] sources = files( 'cpfl_ethdev.c', 'cpfl_rxtx.c', -) \ No newline at end of file +) + +if arch_subdir == 'x86' + cpfl_avx512_cpu_support = ( + cc.get_define('__AVX512F__', args: machine_args) != '' and + cc.get_define('__AVX512BW__', args: machine_args) != '' + ) + + cpfl_avx512_cc_support = ( + not machine_args.contains('-mno-avx512f') and + cc.has_argument('-mavx512f') and + cc.has_argument('-mavx512bw') + ) + + if cpfl_avx512_cpu_support == true or cpfl_avx512_cc_support == true + cflags += ['-DCC_AVX512_SUPPORT'] + endif +endif From patchwork Thu Feb 16 00:30:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Mingxia" X-Patchwork-Id: 124020 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 104B941CA9; Thu, 16 Feb 2023 02:29:47 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C815D42D94; Thu, 16 Feb 2023 02:28:19 +0100 (CET) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id 0CE7F42D74 for ; Thu, 16 Feb 2023 02:28:11 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676510892; x=1708046892; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RwdQWbbRoGrvbYLcEKzHkQhf4e4G53goNmWql99Ffgk=; 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Signed-off-by: Mingxia Liu --- doc/guides/nics/features/cpfl.ini | 1 + drivers/net/cpfl/cpfl_ethdev.c | 3 ++- drivers/net/cpfl/cpfl_rxtx.c | 7 +++++++ 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/doc/guides/nics/features/cpfl.ini b/doc/guides/nics/features/cpfl.ini index f4e45c7c68..c1209df3e5 100644 --- a/doc/guides/nics/features/cpfl.ini +++ b/doc/guides/nics/features/cpfl.ini @@ -11,6 +11,7 @@ MTU update = Y TSO = P L3 checksum offload = P L4 checksum offload = P +Timestamp offload = P Linux = Y x86-32 = Y x86-64 = Y diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index 346af055cf..1e40f3e55c 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -103,7 +103,8 @@ cpfl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | RTE_ETH_RX_OFFLOAD_UDP_CKSUM | RTE_ETH_RX_OFFLOAD_TCP_CKSUM | - RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM; + RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | + RTE_ETH_RX_OFFLOAD_TIMESTAMP; dev_info->tx_offload_capa = RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c index cb7bbddb16..7b12c80f1c 100644 --- a/drivers/net/cpfl/cpfl_rxtx.c +++ b/drivers/net/cpfl/cpfl_rxtx.c @@ -516,6 +516,13 @@ cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id) return -EINVAL; } + err = idpf_qc_ts_mbuf_register(rxq); + if (err != 0) { + PMD_DRV_LOG(ERR, "fail to register timestamp mbuf %u", + rx_queue_id); + return -EIO; + } + if (rxq->bufq1 == NULL) { /* Single queue */ err = idpf_qc_single_rxq_mbufs_alloc(rxq); From patchwork Thu Feb 16 00:30:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Mingxia" X-Patchwork-Id: 124021 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5C35B41CA9; Thu, 16 Feb 2023 02:29:52 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E884842DA2; Thu, 16 Feb 2023 02:28:20 +0100 (CET) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id A006942D81 for ; Thu, 16 Feb 2023 02:28:13 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676510893; x=1708046893; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=o+KpnxgopIKTXLcI36lPGGLILV9t8yfo3WcqhsQc0EU=; b=IwH4US+oeI00P4R5wU5sJzaQVVQutwU0SPoY9hTrJLPcsfR7VkH4c2Lo comUrqVOgtzCKDCehHa1u6V/FYlofz3gqgnr/YbBRiB0opgwFom+iwkqd wqSUxOJ84P1h9yt5HOljHW0Dd1+qQLmzpAnRfd5ivOxSEtk2qWj0qwCDs 6Rzut23ra17VbPGzOBvMTWj6DxiaD7feJ8wJBD7L+uIxIBGmCEaDV3/X3 LZu8B3cGRllB9MJG3q+CSKpM/XIEmnSayNKKZVnPajOJ5Z/yRTioJT7zQ N5l4gHfqdTfsRCggsIM3mGQzUdmP+2FbFCzTHEviVINTg6c32NxBFzCqN w==; X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="329315482" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="329315482" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2023 17:28:13 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="779166310" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="779166310" Received: from dpdk-mingxial-01.sh.intel.com ([10.67.119.167]) by fmsmga002.fm.intel.com with ESMTP; 15 Feb 2023 17:28:11 -0800 From: Mingxia Liu To: dev@dpdk.org, beilei.xing@intel.com, yuying.zhang@intel.com Cc: Mingxia Liu , Wenjun Wu Subject: [PATCH v7 17/21] net/cpfl: add AVX512 data path for split queue model Date: Thu, 16 Feb 2023 00:30:06 +0000 Message-Id: <20230216003010.3439881-18-mingxia.liu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230216003010.3439881-1-mingxia.liu@intel.com> References: <20230213021956.2953088-1-mingxia.liu@intel.com> <20230216003010.3439881-1-mingxia.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support of AVX512 data path for split queue model. Signed-off-by: Wenjun Wu Signed-off-by: Mingxia Liu --- drivers/net/cpfl/cpfl_rxtx.c | 56 +++++++++++++++++++++++-- drivers/net/cpfl/cpfl_rxtx_vec_common.h | 20 ++++++++- drivers/net/cpfl/meson.build | 6 ++- 3 files changed, 75 insertions(+), 7 deletions(-) diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c index 7b12c80f1c..0d5bfb901d 100644 --- a/drivers/net/cpfl/cpfl_rxtx.c +++ b/drivers/net/cpfl/cpfl_rxtx.c @@ -759,7 +759,8 @@ cpfl_set_rx_function(struct rte_eth_dev *dev) if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512) #ifdef CC_AVX512_SUPPORT if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 && - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1) + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 && + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512DQ)) vport->rx_use_avx512 = true; #else PMD_DRV_LOG(NOTICE, @@ -772,6 +773,21 @@ cpfl_set_rx_function(struct rte_eth_dev *dev) #ifdef RTE_ARCH_X86 if (vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT) { + if (vport->rx_vec_allowed) { + for (i = 0; i < dev->data->nb_rx_queues; i++) { + rxq = dev->data->rx_queues[i]; + (void)idpf_qc_splitq_rx_vec_setup(rxq); + } +#ifdef CC_AVX512_SUPPORT + if (vport->rx_use_avx512) { + PMD_DRV_LOG(NOTICE, + "Using Split AVX512 Vector Rx (port %d).", + dev->data->port_id); + dev->rx_pkt_burst = idpf_dp_splitq_recv_pkts_avx512; + return; + } +#endif /* CC_AVX512_SUPPORT */ + } PMD_DRV_LOG(NOTICE, "Using Split Scalar Rx (port %d).", dev->data->port_id); @@ -827,9 +843,17 @@ cpfl_set_tx_function(struct rte_eth_dev *dev) vport->tx_vec_allowed = true; if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512) #ifdef CC_AVX512_SUPPORT + { if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 && rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1) vport->tx_use_avx512 = true; + if (vport->tx_use_avx512) { + for (i = 0; i < dev->data->nb_tx_queues; i++) { + txq = dev->data->tx_queues[i]; + idpf_qc_tx_vec_avx512_setup(txq); + } + } + } #else PMD_DRV_LOG(NOTICE, "AVX512 is not supported in build env"); @@ -839,14 +863,26 @@ cpfl_set_tx_function(struct rte_eth_dev *dev) } #endif /* RTE_ARCH_X86 */ +#ifdef RTE_ARCH_X86 if (vport->txq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT) { + if (vport->tx_vec_allowed) { +#ifdef CC_AVX512_SUPPORT + if (vport->tx_use_avx512) { + PMD_DRV_LOG(NOTICE, + "Using Split AVX512 Vector Tx (port %d).", + dev->data->port_id); + dev->tx_pkt_burst = idpf_dp_splitq_xmit_pkts_avx512; + dev->tx_pkt_prepare = idpf_dp_prep_pkts; + return; + } +#endif /* CC_AVX512_SUPPORT */ + } PMD_DRV_LOG(NOTICE, "Using Split Scalar Tx (port %d).", dev->data->port_id); dev->tx_pkt_burst = idpf_dp_splitq_xmit_pkts; dev->tx_pkt_prepare = idpf_dp_prep_pkts; } else { -#ifdef RTE_ARCH_X86 if (vport->tx_vec_allowed) { #ifdef CC_AVX512_SUPPORT if (vport->tx_use_avx512) { @@ -865,11 +901,25 @@ cpfl_set_tx_function(struct rte_eth_dev *dev) } #endif /* CC_AVX512_SUPPORT */ } -#endif /* RTE_ARCH_X86 */ PMD_DRV_LOG(NOTICE, "Using Single Scalar Tx (port %d).", dev->data->port_id); dev->tx_pkt_burst = idpf_dp_singleq_xmit_pkts; dev->tx_pkt_prepare = idpf_dp_prep_pkts; } +#else + if (vport->txq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT) { + PMD_DRV_LOG(NOTICE, + "Using Split Scalar Tx (port %d).", + dev->data->port_id); + dev->tx_pkt_burst = idpf_dp_splitq_xmit_pkts; + dev->tx_pkt_prepare = idpf_dp_prep_pkts; + } else { + PMD_DRV_LOG(NOTICE, + "Using Single Scalar Tx (port %d).", + dev->data->port_id); + dev->tx_pkt_burst = idpf_dp_singleq_xmit_pkts; + dev->tx_pkt_prepare = idpf_dp_prep_pkts; + } +#endif /* RTE_ARCH_X86 */ } diff --git a/drivers/net/cpfl/cpfl_rxtx_vec_common.h b/drivers/net/cpfl/cpfl_rxtx_vec_common.h index 2d4c6a0ef3..665418d27d 100644 --- a/drivers/net/cpfl/cpfl_rxtx_vec_common.h +++ b/drivers/net/cpfl/cpfl_rxtx_vec_common.h @@ -64,15 +64,31 @@ cpfl_tx_vec_queue_default(struct idpf_tx_queue *txq) return CPFL_VECTOR_PATH; } +static inline int +cpfl_rx_splitq_vec_default(struct idpf_rx_queue *rxq) +{ + if (rxq->bufq2->rx_buf_len < rxq->max_pkt_len) + return CPFL_SCALAR_PATH; + + return CPFL_VECTOR_PATH; +} + static inline int cpfl_rx_vec_dev_check_default(struct rte_eth_dev *dev) { + struct idpf_vport *vport = dev->data->dev_private; struct idpf_rx_queue *rxq; - int i, ret = 0; + int i, default_ret, splitq_ret, ret = CPFL_SCALAR_PATH; for (i = 0; i < dev->data->nb_rx_queues; i++) { rxq = dev->data->rx_queues[i]; - ret = (cpfl_rx_vec_queue_default(rxq)); + default_ret = cpfl_rx_vec_queue_default(rxq); + if (vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT) { + splitq_ret = cpfl_rx_splitq_vec_default(rxq); + ret = splitq_ret && default_ret; + } else { + ret = default_ret; + } if (ret == CPFL_SCALAR_PATH) return CPFL_SCALAR_PATH; } diff --git a/drivers/net/cpfl/meson.build b/drivers/net/cpfl/meson.build index fbe6500826..2cf69258e2 100644 --- a/drivers/net/cpfl/meson.build +++ b/drivers/net/cpfl/meson.build @@ -23,13 +23,15 @@ sources = files( if arch_subdir == 'x86' cpfl_avx512_cpu_support = ( cc.get_define('__AVX512F__', args: machine_args) != '' and - cc.get_define('__AVX512BW__', args: machine_args) != '' + cc.get_define('__AVX512BW__', args: machine_args) != '' and + cc.get_define('__AVX512DQ__', args: machine_args) != '' ) cpfl_avx512_cc_support = ( not machine_args.contains('-mno-avx512f') and cc.has_argument('-mavx512f') and - cc.has_argument('-mavx512bw') + cc.has_argument('-mavx512bw') and + cc.has_argument('-mavx512dq') ) if cpfl_avx512_cpu_support == true or cpfl_avx512_cc_support == true From patchwork Thu Feb 16 00:30:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Mingxia" X-Patchwork-Id: 124022 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 16D8741CA9; Thu, 16 Feb 2023 02:29:58 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4199342DAB; Thu, 16 Feb 2023 02:28:22 +0100 (CET) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id 2686542D81 for ; Thu, 16 Feb 2023 02:28:15 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676510895; x=1708046895; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PdszsbDl3Wqo3ZqI7Fmp6wM+un3Tx6DWV5rcVYgXicU=; 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Signed-off-by: Mingxia Liu --- drivers/net/cpfl/cpfl_ethdev.c | 86 ++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index 1e40f3e55c..0fb9f0455b 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -178,6 +178,87 @@ cpfl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused) return ptypes; } +static uint64_t +cpfl_get_mbuf_alloc_failed_stats(struct rte_eth_dev *dev) +{ + uint64_t mbuf_alloc_failed = 0; + struct idpf_rx_queue *rxq; + int i = 0; + + for (i = 0; i < dev->data->nb_rx_queues; i++) { + rxq = dev->data->rx_queues[i]; + mbuf_alloc_failed += __atomic_load_n(&rxq->rx_stats.mbuf_alloc_failed, + __ATOMIC_RELAXED); + } + + return mbuf_alloc_failed; +} + +static int +cpfl_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) +{ + struct idpf_vport *vport = + (struct idpf_vport *)dev->data->dev_private; + struct virtchnl2_vport_stats *pstats = NULL; + int ret; + + ret = idpf_vc_stats_query(vport, &pstats); + if (ret == 0) { + uint8_t crc_stats_len = (dev->data->dev_conf.rxmode.offloads & + RTE_ETH_RX_OFFLOAD_KEEP_CRC) ? 0 : + RTE_ETHER_CRC_LEN; + + idpf_vport_stats_update(&vport->eth_stats_offset, pstats); + stats->ipackets = pstats->rx_unicast + pstats->rx_multicast + + pstats->rx_broadcast - pstats->rx_discards; + stats->opackets = pstats->tx_broadcast + pstats->tx_multicast + + pstats->tx_unicast; + stats->imissed = pstats->rx_discards; + stats->oerrors = pstats->tx_errors + pstats->tx_discards; + stats->ibytes = pstats->rx_bytes; + stats->ibytes -= stats->ipackets * crc_stats_len; + stats->obytes = pstats->tx_bytes; + + dev->data->rx_mbuf_alloc_failed = cpfl_get_mbuf_alloc_failed_stats(dev); + stats->rx_nombuf = dev->data->rx_mbuf_alloc_failed; + } else { + PMD_DRV_LOG(ERR, "Get statistics failed"); + } + return ret; +} + +static void +cpfl_reset_mbuf_alloc_failed_stats(struct rte_eth_dev *dev) +{ + struct idpf_rx_queue *rxq; + int i; + + for (i = 0; i < dev->data->nb_rx_queues; i++) { + rxq = dev->data->rx_queues[i]; + __atomic_store_n(&rxq->rx_stats.mbuf_alloc_failed, 0, __ATOMIC_RELAXED); + } +} + +static int +cpfl_dev_stats_reset(struct rte_eth_dev *dev) +{ + struct idpf_vport *vport = + (struct idpf_vport *)dev->data->dev_private; + struct virtchnl2_vport_stats *pstats = NULL; + int ret; + + ret = idpf_vc_stats_query(vport, &pstats); + if (ret != 0) + return ret; + + /* set stats offset base on current values */ + vport->eth_stats_offset = *pstats; + + cpfl_reset_mbuf_alloc_failed_stats(dev); + + return 0; +} + static int cpfl_init_rss(struct idpf_vport *vport) { @@ -365,6 +446,9 @@ cpfl_dev_start(struct rte_eth_dev *dev) goto err_vport; } + if (cpfl_dev_stats_reset(dev)) + PMD_DRV_LOG(ERR, "Failed to reset stats"); + vport->stopped = 0; return 0; @@ -766,6 +850,8 @@ static const struct eth_dev_ops cpfl_eth_dev_ops = { .tx_queue_release = cpfl_dev_tx_queue_release, .mtu_set = cpfl_dev_mtu_set, .dev_supported_ptypes_get = cpfl_dev_supported_ptypes_get, + .stats_get = cpfl_dev_stats_get, + .stats_reset = cpfl_dev_stats_reset, }; static uint16_t From patchwork Thu Feb 16 00:30:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Mingxia" X-Patchwork-Id: 124023 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EC06141CA9; Thu, 16 Feb 2023 02:30:03 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5459442D8F; Thu, 16 Feb 2023 02:28:23 +0100 (CET) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id 8AA7942BB1 for ; Thu, 16 Feb 2023 02:28:16 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676510896; x=1708046896; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fCg6yf4P2IVc8Q5DiLfUexRNVePCzGTjWfup520KXTM=; b=DBdQLcFsMYKKtQJ16IXL0y0CUI1p5U+OofO6tZsV5jB9sRZDmAFwaCAi QQC86QgRUXy6P1G2jhG2wSIeaxdc6/2YY3jbosRYwx3mR35tjUTgR8B1t +wcdb8jdJdih3VF1VthcgdF0VmNnJscM++j9ZelYtd9Q5Av/NVjxnpoG7 SS+2gpPhy0O5QDU+dCOPyvwI5n5pyqla0oB30cVbZNWAyM5itAB8nE1xq n5/0bGSrADnky86rx4AaxXIkTmq9cRmg9TuEHqz+4dyv47Ga3Ntx4MoFc ik2TP3nc6oy6PbFe2S1uOsw/kTWQnjL/aMqMZ3Bs1w0oea9zHRXapJNJ0 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="329315493" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="329315493" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2023 17:28:16 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="779166324" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="779166324" Received: from dpdk-mingxial-01.sh.intel.com ([10.67.119.167]) by fmsmga002.fm.intel.com with ESMTP; 15 Feb 2023 17:28:14 -0800 From: Mingxia Liu To: dev@dpdk.org, beilei.xing@intel.com, yuying.zhang@intel.com Cc: Mingxia Liu Subject: [PATCH v7 19/21] net/cpfl: add RSS set/get ops Date: Thu, 16 Feb 2023 00:30:08 +0000 Message-Id: <20230216003010.3439881-20-mingxia.liu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230216003010.3439881-1-mingxia.liu@intel.com> References: <20230213021956.2953088-1-mingxia.liu@intel.com> <20230216003010.3439881-1-mingxia.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for these device ops: - rss_reta_update - rss_reta_query - rss_hash_update - rss_hash_conf_get Signed-off-by: Mingxia Liu --- drivers/net/cpfl/cpfl_ethdev.c | 270 ++++++++++++++++++++++++++++++++- 1 file changed, 269 insertions(+), 1 deletion(-) diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index 0fb9f0455b..d2387b9a39 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -30,6 +30,56 @@ static const char * const cpfl_valid_args[] = { NULL }; +static const uint64_t cpfl_map_hena_rss[] = { + [IDPF_HASH_NONF_UNICAST_IPV4_UDP] = + RTE_ETH_RSS_NONFRAG_IPV4_UDP, + [IDPF_HASH_NONF_MULTICAST_IPV4_UDP] = + RTE_ETH_RSS_NONFRAG_IPV4_UDP, + [IDPF_HASH_NONF_IPV4_UDP] = + RTE_ETH_RSS_NONFRAG_IPV4_UDP, + [IDPF_HASH_NONF_IPV4_TCP_SYN_NO_ACK] = + RTE_ETH_RSS_NONFRAG_IPV4_TCP, + [IDPF_HASH_NONF_IPV4_TCP] = + RTE_ETH_RSS_NONFRAG_IPV4_TCP, + [IDPF_HASH_NONF_IPV4_SCTP] = + RTE_ETH_RSS_NONFRAG_IPV4_SCTP, + [IDPF_HASH_NONF_IPV4_OTHER] = + RTE_ETH_RSS_NONFRAG_IPV4_OTHER, + [IDPF_HASH_FRAG_IPV4] = RTE_ETH_RSS_FRAG_IPV4, + + /* IPv6 */ + [IDPF_HASH_NONF_UNICAST_IPV6_UDP] = + RTE_ETH_RSS_NONFRAG_IPV6_UDP, + [IDPF_HASH_NONF_MULTICAST_IPV6_UDP] = + RTE_ETH_RSS_NONFRAG_IPV6_UDP, + [IDPF_HASH_NONF_IPV6_UDP] = + RTE_ETH_RSS_NONFRAG_IPV6_UDP, + [IDPF_HASH_NONF_IPV6_TCP_SYN_NO_ACK] = + RTE_ETH_RSS_NONFRAG_IPV6_TCP, + [IDPF_HASH_NONF_IPV6_TCP] = + RTE_ETH_RSS_NONFRAG_IPV6_TCP, + [IDPF_HASH_NONF_IPV6_SCTP] = + RTE_ETH_RSS_NONFRAG_IPV6_SCTP, + [IDPF_HASH_NONF_IPV6_OTHER] = + RTE_ETH_RSS_NONFRAG_IPV6_OTHER, + [IDPF_HASH_FRAG_IPV6] = RTE_ETH_RSS_FRAG_IPV6, + + /* L2 Payload */ + [IDPF_HASH_L2_PAYLOAD] = RTE_ETH_RSS_L2_PAYLOAD +}; + +static const uint64_t cpfl_ipv4_rss = RTE_ETH_RSS_NONFRAG_IPV4_UDP | + RTE_ETH_RSS_NONFRAG_IPV4_TCP | + RTE_ETH_RSS_NONFRAG_IPV4_SCTP | + RTE_ETH_RSS_NONFRAG_IPV4_OTHER | + RTE_ETH_RSS_FRAG_IPV4; + +static const uint64_t cpfl_ipv6_rss = RTE_ETH_RSS_NONFRAG_IPV6_UDP | + RTE_ETH_RSS_NONFRAG_IPV6_TCP | + RTE_ETH_RSS_NONFRAG_IPV6_SCTP | + RTE_ETH_RSS_NONFRAG_IPV6_OTHER | + RTE_ETH_RSS_FRAG_IPV6; + static int cpfl_dev_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete) @@ -97,6 +147,9 @@ cpfl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) dev_info->max_mtu = vport->max_mtu; dev_info->min_mtu = RTE_ETHER_MIN_MTU; + dev_info->hash_key_size = vport->rss_key_size; + dev_info->reta_size = vport->rss_lut_size; + dev_info->flow_type_rss_offloads = CPFL_RSS_OFFLOAD_ALL; dev_info->rx_offload_capa = @@ -259,6 +312,36 @@ cpfl_dev_stats_reset(struct rte_eth_dev *dev) return 0; } +static int cpfl_config_rss_hf(struct idpf_vport *vport, uint64_t rss_hf) +{ + uint64_t hena = 0; + uint16_t i; + + /** + * RTE_ETH_RSS_IPV4 and RTE_ETH_RSS_IPV6 can be considered as 2 + * generalizations of all other IPv4 and IPv6 RSS types. + */ + if (rss_hf & RTE_ETH_RSS_IPV4) + rss_hf |= cpfl_ipv4_rss; + + if (rss_hf & RTE_ETH_RSS_IPV6) + rss_hf |= cpfl_ipv6_rss; + + for (i = 0; i < RTE_DIM(cpfl_map_hena_rss); i++) { + if (cpfl_map_hena_rss[i] & rss_hf) + hena |= BIT_ULL(i); + } + + /** + * At present, cp doesn't process the virtual channel msg of rss_hf configuration, + * tips are given below. + */ + if (hena != vport->rss_hf) + PMD_DRV_LOG(WARNING, "Updating RSS Hash Function is not supported at present."); + + return 0; +} + static int cpfl_init_rss(struct idpf_vport *vport) { @@ -279,7 +362,7 @@ cpfl_init_rss(struct idpf_vport *vport) vport->rss_key_size); return -EINVAL; } else { - rte_memcpy(vport->rss_key, rss_conf->rss_key, + memcpy(vport->rss_key, rss_conf->rss_key, vport->rss_key_size); } @@ -295,6 +378,187 @@ cpfl_init_rss(struct idpf_vport *vport) return ret; } +static int +cpfl_rss_reta_update(struct rte_eth_dev *dev, + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size) +{ + struct idpf_vport *vport = dev->data->dev_private; + struct idpf_adapter *adapter = vport->adapter; + uint16_t idx, shift; + int ret = 0; + uint16_t i; + + if (adapter->caps.rss_caps == 0 || dev->data->nb_rx_queues == 0) { + PMD_DRV_LOG(DEBUG, "RSS is not supported"); + return -ENOTSUP; + } + + if (reta_size != vport->rss_lut_size) { + PMD_DRV_LOG(ERR, "The size of hash lookup table configured " + "(%d) doesn't match the number of hardware can " + "support (%d)", + reta_size, vport->rss_lut_size); + return -EINVAL; + } + + for (i = 0; i < reta_size; i++) { + idx = i / RTE_ETH_RETA_GROUP_SIZE; + shift = i % RTE_ETH_RETA_GROUP_SIZE; + if (reta_conf[idx].mask & (1ULL << shift)) + vport->rss_lut[i] = reta_conf[idx].reta[shift]; + } + + /* send virtchnl ops to configure RSS */ + ret = idpf_vc_rss_lut_set(vport); + if (ret) + PMD_INIT_LOG(ERR, "Failed to configure RSS lut"); + + return ret; +} + +static int +cpfl_rss_reta_query(struct rte_eth_dev *dev, + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size) +{ + struct idpf_vport *vport = dev->data->dev_private; + struct idpf_adapter *adapter = vport->adapter; + uint16_t idx, shift; + int ret = 0; + uint16_t i; + + if (adapter->caps.rss_caps == 0 || dev->data->nb_rx_queues == 0) { + PMD_DRV_LOG(DEBUG, "RSS is not supported"); + return -ENOTSUP; + } + + if (reta_size != vport->rss_lut_size) { + PMD_DRV_LOG(ERR, "The size of hash lookup table configured " + "(%d) doesn't match the number of hardware can " + "support (%d)", reta_size, vport->rss_lut_size); + return -EINVAL; + } + + ret = idpf_vc_rss_lut_get(vport); + if (ret) { + PMD_DRV_LOG(ERR, "Failed to get RSS LUT"); + return ret; + } + + for (i = 0; i < reta_size; i++) { + idx = i / RTE_ETH_RETA_GROUP_SIZE; + shift = i % RTE_ETH_RETA_GROUP_SIZE; + if (reta_conf[idx].mask & (1ULL << shift)) + reta_conf[idx].reta[shift] = vport->rss_lut[i]; + } + + return 0; +} + +static int +cpfl_rss_hash_update(struct rte_eth_dev *dev, + struct rte_eth_rss_conf *rss_conf) +{ + struct idpf_vport *vport = dev->data->dev_private; + struct idpf_adapter *adapter = vport->adapter; + int ret = 0; + + if (adapter->caps.rss_caps == 0 || dev->data->nb_rx_queues == 0) { + PMD_DRV_LOG(DEBUG, "RSS is not supported"); + return -ENOTSUP; + } + + if (!rss_conf->rss_key || rss_conf->rss_key_len == 0) { + PMD_DRV_LOG(DEBUG, "No key to be configured"); + goto skip_rss_key; + } else if (rss_conf->rss_key_len != vport->rss_key_size) { + PMD_DRV_LOG(ERR, "The size of hash key configured " + "(%d) doesn't match the size of hardware can " + "support (%d)", + rss_conf->rss_key_len, + vport->rss_key_size); + return -EINVAL; + } + + memcpy(vport->rss_key, rss_conf->rss_key, + vport->rss_key_size); + ret = idpf_vc_rss_key_set(vport); + if (ret != 0) { + PMD_INIT_LOG(ERR, "Failed to configure RSS key"); + return ret; + } + +skip_rss_key: + ret = cpfl_config_rss_hf(vport, rss_conf->rss_hf); + if (ret != 0) { + PMD_INIT_LOG(ERR, "Failed to configure RSS hash"); + return ret; + } + + return 0; +} + +static uint64_t +cpfl_map_general_rss_hf(uint64_t config_rss_hf, uint64_t last_general_rss_hf) +{ + uint64_t valid_rss_hf = 0; + uint16_t i; + + for (i = 0; i < RTE_DIM(cpfl_map_hena_rss); i++) { + uint64_t bit = BIT_ULL(i); + + if (bit & config_rss_hf) + valid_rss_hf |= cpfl_map_hena_rss[i]; + } + + if (valid_rss_hf & cpfl_ipv4_rss) + valid_rss_hf |= last_general_rss_hf & RTE_ETH_RSS_IPV4; + + if (valid_rss_hf & cpfl_ipv6_rss) + valid_rss_hf |= last_general_rss_hf & RTE_ETH_RSS_IPV6; + + return valid_rss_hf; +} + +static int +cpfl_rss_hash_conf_get(struct rte_eth_dev *dev, + struct rte_eth_rss_conf *rss_conf) +{ + struct idpf_vport *vport = dev->data->dev_private; + struct idpf_adapter *adapter = vport->adapter; + int ret = 0; + + if (adapter->caps.rss_caps == 0 || dev->data->nb_rx_queues == 0) { + PMD_DRV_LOG(DEBUG, "RSS is not supported"); + return -ENOTSUP; + } + + ret = idpf_vc_rss_hash_get(vport); + if (ret) { + PMD_DRV_LOG(ERR, "Failed to get RSS hf"); + return ret; + } + + rss_conf->rss_hf = cpfl_map_general_rss_hf(vport->rss_hf, vport->last_general_rss_hf); + + if (!rss_conf->rss_key) + return 0; + + ret = idpf_vc_rss_key_get(vport); + if (ret) { + PMD_DRV_LOG(ERR, "Failed to get RSS key"); + return ret; + } + + if (rss_conf->rss_key_len > vport->rss_key_size) + rss_conf->rss_key_len = vport->rss_key_size; + + memcpy(rss_conf->rss_key, vport->rss_key, rss_conf->rss_key_len); + + return 0; +} + static int cpfl_dev_configure(struct rte_eth_dev *dev) { @@ -852,6 +1116,10 @@ static const struct eth_dev_ops cpfl_eth_dev_ops = { .dev_supported_ptypes_get = cpfl_dev_supported_ptypes_get, .stats_get = cpfl_dev_stats_get, .stats_reset = cpfl_dev_stats_reset, + .reta_update = cpfl_rss_reta_update, + .reta_query = cpfl_rss_reta_query, + .rss_hash_update = cpfl_rss_hash_update, + .rss_hash_conf_get = cpfl_rss_hash_conf_get, }; static uint16_t From patchwork Thu Feb 16 00:30:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Mingxia" X-Patchwork-Id: 124024 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B668741CA9; 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a="329315500" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="329315500" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2023 17:28:17 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="779166330" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="779166330" Received: from dpdk-mingxial-01.sh.intel.com ([10.67.119.167]) by fmsmga002.fm.intel.com with ESMTP; 15 Feb 2023 17:28:16 -0800 From: Mingxia Liu To: dev@dpdk.org, beilei.xing@intel.com, yuying.zhang@intel.com Cc: Mingxia Liu , Wenjun Wu Subject: [PATCH v7 20/21] net/cpfl: support scalar scatter Rx datapath for single queue model Date: Thu, 16 Feb 2023 00:30:09 +0000 Message-Id: <20230216003010.3439881-21-mingxia.liu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230216003010.3439881-1-mingxia.liu@intel.com> References: <20230213021956.2953088-1-mingxia.liu@intel.com> <20230216003010.3439881-1-mingxia.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch add single q recv scatter Rx function. Signed-off-by: Wenjun Wu Signed-off-by: Mingxia Liu --- drivers/net/cpfl/cpfl_ethdev.c | 3 ++- drivers/net/cpfl/cpfl_rxtx.c | 27 +++++++++++++++++++++++++++ drivers/net/cpfl/cpfl_rxtx.h | 2 ++ 3 files changed, 31 insertions(+), 1 deletion(-) diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index d2387b9a39..f959a2911d 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -157,7 +157,8 @@ cpfl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) RTE_ETH_RX_OFFLOAD_UDP_CKSUM | RTE_ETH_RX_OFFLOAD_TCP_CKSUM | RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | - RTE_ETH_RX_OFFLOAD_TIMESTAMP; + RTE_ETH_RX_OFFLOAD_TIMESTAMP | + RTE_ETH_RX_OFFLOAD_SCATTER; dev_info->tx_offload_capa = RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c index 0d5bfb901d..6226b02301 100644 --- a/drivers/net/cpfl/cpfl_rxtx.c +++ b/drivers/net/cpfl/cpfl_rxtx.c @@ -503,6 +503,8 @@ int cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id) { struct idpf_rx_queue *rxq; + uint16_t max_pkt_len; + uint32_t frame_size; int err; if (rx_queue_id >= dev->data->nb_rx_queues) @@ -516,6 +518,17 @@ cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id) return -EINVAL; } + frame_size = dev->data->mtu + CPFL_ETH_OVERHEAD; + + max_pkt_len = + RTE_MIN((uint32_t)CPFL_SUPPORT_CHAIN_NUM * rxq->rx_buf_len, + frame_size); + + rxq->max_pkt_len = max_pkt_len; + if ((dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_SCATTER) || + frame_size > rxq->rx_buf_len) + dev->data->scattered_rx = 1; + err = idpf_qc_ts_mbuf_register(rxq); if (err != 0) { PMD_DRV_LOG(ERR, "fail to register timestamp mbuf %u", @@ -808,6 +821,13 @@ cpfl_set_rx_function(struct rte_eth_dev *dev) } #endif /* CC_AVX512_SUPPORT */ } + if (dev->data->scattered_rx) { + PMD_DRV_LOG(NOTICE, + "Using Single Scalar Scatterd Rx (port %d).", + dev->data->port_id); + dev->rx_pkt_burst = idpf_dp_singleq_recv_scatter_pkts; + return; + } PMD_DRV_LOG(NOTICE, "Using Single Scalar Rx (port %d).", dev->data->port_id); @@ -820,6 +840,13 @@ cpfl_set_rx_function(struct rte_eth_dev *dev) dev->data->port_id); dev->rx_pkt_burst = idpf_dp_splitq_recv_pkts; } else { + if (dev->data->scattered_rx) { + PMD_DRV_LOG(NOTICE, + "Using Single Scalar Scatterd Rx (port %d).", + dev->data->port_id); + dev->rx_pkt_burst = idpf_dp_singleq_recv_scatter_pkts; + return; + } PMD_DRV_LOG(NOTICE, "Using Single Scalar Rx (port %d).", dev->data->port_id); diff --git a/drivers/net/cpfl/cpfl_rxtx.h b/drivers/net/cpfl/cpfl_rxtx.h index 5f8144e55f..fb267d38c8 100644 --- a/drivers/net/cpfl/cpfl_rxtx.h +++ b/drivers/net/cpfl/cpfl_rxtx.h @@ -21,6 +21,8 @@ #define CPFL_DEFAULT_TX_RS_THRESH 32 #define CPFL_DEFAULT_TX_FREE_THRESH 32 +#define CPFL_SUPPORT_CHAIN_NUM 5 + int cpfl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, uint16_t nb_desc, unsigned int socket_id, const struct rte_eth_txconf *tx_conf); From patchwork Thu Feb 16 00:30:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Mingxia" X-Patchwork-Id: 124025 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4DFB741CA9; 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a="329315506" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="329315506" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2023 17:28:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="779166333" X-IronPort-AV: E=Sophos;i="5.97,301,1669104000"; d="scan'208";a="779166333" Received: from dpdk-mingxial-01.sh.intel.com ([10.67.119.167]) by fmsmga002.fm.intel.com with ESMTP; 15 Feb 2023 17:28:17 -0800 From: Mingxia Liu To: dev@dpdk.org, beilei.xing@intel.com, yuying.zhang@intel.com Cc: Mingxia Liu Subject: [PATCH v7 21/21] net/cpfl: add xstats ops Date: Thu, 16 Feb 2023 00:30:10 +0000 Message-Id: <20230216003010.3439881-22-mingxia.liu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230216003010.3439881-1-mingxia.liu@intel.com> References: <20230213021956.2953088-1-mingxia.liu@intel.com> <20230216003010.3439881-1-mingxia.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for these device ops: - dev_xstats_get - dev_xstats_get_names - dev_xstats_reset Signed-off-by: Mingxia Liu --- drivers/net/cpfl/cpfl_ethdev.c | 80 ++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index f959a2911d..543dbd60f0 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -80,6 +80,30 @@ static const uint64_t cpfl_ipv6_rss = RTE_ETH_RSS_NONFRAG_IPV6_UDP | RTE_ETH_RSS_NONFRAG_IPV6_OTHER | RTE_ETH_RSS_FRAG_IPV6; +struct rte_cpfl_xstats_name_off { + char name[RTE_ETH_XSTATS_NAME_SIZE]; + unsigned int offset; +}; + +static const struct rte_cpfl_xstats_name_off rte_cpfl_stats_strings[] = { + {"rx_bytes", offsetof(struct virtchnl2_vport_stats, rx_bytes)}, + {"rx_unicast_packets", offsetof(struct virtchnl2_vport_stats, rx_unicast)}, + {"rx_multicast_packets", offsetof(struct virtchnl2_vport_stats, rx_multicast)}, + {"rx_broadcast_packets", offsetof(struct virtchnl2_vport_stats, rx_broadcast)}, + {"rx_dropped_packets", offsetof(struct virtchnl2_vport_stats, rx_discards)}, + {"rx_errors", offsetof(struct virtchnl2_vport_stats, rx_errors)}, + {"rx_unknown_protocol_packets", offsetof(struct virtchnl2_vport_stats, + rx_unknown_protocol)}, + {"tx_bytes", offsetof(struct virtchnl2_vport_stats, tx_bytes)}, + {"tx_unicast_packets", offsetof(struct virtchnl2_vport_stats, tx_unicast)}, + {"tx_multicast_packets", offsetof(struct virtchnl2_vport_stats, tx_multicast)}, + {"tx_broadcast_packets", offsetof(struct virtchnl2_vport_stats, tx_broadcast)}, + {"tx_dropped_packets", offsetof(struct virtchnl2_vport_stats, tx_discards)}, + {"tx_error_packets", offsetof(struct virtchnl2_vport_stats, tx_errors)}}; + +#define CPFL_NB_XSTATS (sizeof(rte_cpfl_stats_strings) / \ + sizeof(rte_cpfl_stats_strings[0])) + static int cpfl_dev_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete) @@ -313,6 +337,59 @@ cpfl_dev_stats_reset(struct rte_eth_dev *dev) return 0; } +static int cpfl_dev_xstats_reset(struct rte_eth_dev *dev) +{ + cpfl_dev_stats_reset(dev); + return 0; +} + +static int cpfl_dev_xstats_get(struct rte_eth_dev *dev, + struct rte_eth_xstat *xstats, unsigned int n) +{ + struct idpf_vport *vport = + (struct idpf_vport *)dev->data->dev_private; + struct virtchnl2_vport_stats *pstats = NULL; + unsigned int i; + int ret; + + if (n < CPFL_NB_XSTATS) + return CPFL_NB_XSTATS; + + if (!xstats) + return 0; + + ret = idpf_vc_stats_query(vport, &pstats); + if (ret) { + PMD_DRV_LOG(ERR, "Get statistics failed"); + return 0; + } + + idpf_vport_stats_update(&vport->eth_stats_offset, pstats); + + /* loop over xstats array and values from pstats */ + for (i = 0; i < CPFL_NB_XSTATS; i++) { + xstats[i].id = i; + xstats[i].value = *(uint64_t *)(((char *)pstats) + + rte_cpfl_stats_strings[i].offset); + } + return CPFL_NB_XSTATS; +} + +static int cpfl_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, + struct rte_eth_xstat_name *xstats_names, + __rte_unused unsigned int limit) +{ + unsigned int i; + + if (xstats_names) + for (i = 0; i < CPFL_NB_XSTATS; i++) { + snprintf(xstats_names[i].name, + sizeof(xstats_names[i].name), + "%s", rte_cpfl_stats_strings[i].name); + } + return CPFL_NB_XSTATS; +} + static int cpfl_config_rss_hf(struct idpf_vport *vport, uint64_t rss_hf) { uint64_t hena = 0; @@ -1121,6 +1198,9 @@ static const struct eth_dev_ops cpfl_eth_dev_ops = { .reta_query = cpfl_rss_reta_query, .rss_hash_update = cpfl_rss_hash_update, .rss_hash_conf_get = cpfl_rss_hash_conf_get, + .xstats_get = cpfl_dev_xstats_get, + .xstats_get_names = cpfl_dev_xstats_get_names, + .xstats_reset = cpfl_dev_xstats_reset, }; static uint16_t