From patchwork Thu Feb 2 10:11:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rongwei Liu X-Patchwork-Id: 122915 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 16B0941BAB; Thu, 2 Feb 2023 11:12:07 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A2C4E42D70; Thu, 2 Feb 2023 11:12:04 +0100 (CET) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2053.outbound.protection.outlook.com [40.107.244.53]) by mails.dpdk.org (Postfix) with ESMTP id 4597942D65 for ; Thu, 2 Feb 2023 11:12:03 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=hvhngHRdUf0XVny8uxc7LIDqTdC9c4grUIPzy/dpjaCq+YeNUsioLrphVo8ntBCOstKV9UzKWuFx01vu8fOygq1YMvv3QuTIWq6qpVI3cIQOo7CwuBfX9Co8MHalqwXeZQ5gvSYVZQKd1tUaPEWD5IKP/MClkhKouSsNl8d0g2zIuN0W0LhIgU8/ILIO9XSlhukceNR1c1aPW3yt17YQZxsym0xJo/3BN00ZIxr3GIhPFn1x6vd/mo+ROM6ZdzjxOcKFZoqjqkPT0bNJjyArtSnop8XYRbG+D1U22FYAUJ4cUrxqXP5G4Xq//3TYLhLwG+YeTgSPFpRnYmg0wJhOVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=U0dijBUFt4PPLLlYmEGorQd7KLo6RPo5CnZ9rwTca3k=; b=izop0Q49/Xwov6C8j7VRW0wVpnNuMT5ooYTg47qgcrFmghhtVz3j8QdrMHeGyh4Cr8UV1Sb4KOk13H8PVCgZ1HRvtSjNTQCW19SQgQ26hGozt4SVkcZ52bLi1I2PBjH52Hf+JUGzCMPvpfJOz86CdeFwpAyYNzmu5YHC9eJkmQnE5I72IaAq+KVD3r5rC57+ASW6qlGE0hC3D1mAyiGHeEmnypNrYol8zVx5TLbOOYS0EZm1dHlayVxV4t6qJP9q64RNlzifpic1cSMYEt41Ck8uWbWRCcTlLUmyGWonjcPyU/mt8gYOxzBVMenaaDs6CtyAe+OjJLaY/ZMUY1rYIg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=U0dijBUFt4PPLLlYmEGorQd7KLo6RPo5CnZ9rwTca3k=; b=MtoMtiF4kXDcyJKyTi5ctT1rUWZqxaRn8IwlnOdjwfTviD+kQ7zHh07L3DssZeQMDPyADmchwywAZROpqQdT18QE0besOScVjQjbx9fhG98sHTgZ7B+haOAprmc8JNMglnOukdforLvTi7ZDEgA8dLFaQZlqWqc9ksjot69gYF35v7nMyVbUPq9LwbuTkpAGK2/7uUR9jdcnzokuFv2fp7txSv5/Yr23J+ulH1G3qiAfx7HRwYtXrQCuLpQDNELAQyS8JFXuB4a5OqPbZ+O9FnPbwtq2IWS65wGUtpR4lMyQX1LKERMg0stuzugl7HNOuUKEHEJBXwNTRtagPIDUSg== Received: from BN1PR12CA0022.namprd12.prod.outlook.com (2603:10b6:408:e1::27) by DM4PR12MB5747.namprd12.prod.outlook.com (2603:10b6:8:5e::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6064.22; Thu, 2 Feb 2023 10:12:01 +0000 Received: from BN8NAM11FT106.eop-nam11.prod.protection.outlook.com (2603:10b6:408:e1:cafe::28) by BN1PR12CA0022.outlook.office365.com (2603:10b6:408:e1::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6064.27 via Frontend Transport; Thu, 2 Feb 2023 10:12:01 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BN8NAM11FT106.mail.protection.outlook.com (10.13.177.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6064.27 via Frontend Transport; Thu, 2 Feb 2023 10:12:00 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Thu, 2 Feb 2023 02:11:45 -0800 Received: from nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Thu, 2 Feb 2023 02:11:43 -0800 From: Rongwei Liu To: , , , , CC: Subject: [PATCH v1 1/5] net/mlx5: adopt IPv6 routing extension prm definition Date: Thu, 2 Feb 2023 12:11:24 +0200 Message-ID: <20230202101128.2446928-2-rongweil@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230202101128.2446928-1-rongweil@nvidia.com> References: <20230202101128.2446928-1-rongweil@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT106:EE_|DM4PR12MB5747:EE_ X-MS-Office365-Filtering-Correlation-Id: 9537b0d9-e6f8-4eeb-9ca9-08db0505ecf2 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: g7mlsJa4V4FiI3mSRuY6BJyIB8vWWPVmDQzr6ENku7+N7gGDcUy6TaW+lnrULAbuiF8JM0K1EGC5PsWRBjaW87SVjWReV4K6A874KW5/L4CCcHc1dT75EaLpthHDG4Q2PYprg+nfqHRfp3Alheipgxq8LSmRQF4nWxt9AmZ2diQaVYKeVZdPjDAmbdC3+ZMLNfntdLx1YfBKGp+PlnsJ05hCUpELp+igeTUPfHEjdLqmXxY4i1mc+Md9P/RMXU3Is1sWewp9FdxFOMJnB3xk2Hg41bhevAB+SrgANi6J/Y4fGleKzqLkjFNXiQEp2P2G+8fXNndSzfgl5pkV4HuGKwM5qlV5iH7NoTBJibG9BACfeCpwPS7SCk0ViSk4h4htzlm3roTjb4TJm61oem9o1Df/ojojGyuRvZtsvdruMa5UKARW0t9sO+uo/UAc6bhhTfkHZPgc1cX0NgfpVOVFBwz/s04gCbtXasagQbtPnYbI/qhU1U/1NGFKutB/nJiY59Iu3LeZPuKJcN7vvEoWUaXP+rYPNEdeRQ4DsAKcUcM3Jf9Zm1Ezd+Ik4dLH3bGnsoWckSIvMfNg4rnEPM3FzHxa8ksxxwrNscuXZFSUyK0bgu9mC46SPmviAzCIukV4AlHiID0H2MZa99v70F4DBD9qbVY6FBol8ICNtj1pb0OZuTqfA4HRclFSTFy6KDXnbhUGIMWqBY6ITvHOJuTwhA== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230025)(4636009)(136003)(376002)(396003)(39860400002)(346002)(451199018)(40470700004)(36840700001)(46966006)(40480700001)(55016003)(40460700003)(82310400005)(47076005)(16526019)(426003)(336012)(83380400001)(7696005)(107886003)(478600001)(6666004)(356005)(1076003)(2616005)(26005)(86362001)(186003)(36756003)(6286002)(36860700001)(41300700001)(82740400003)(70206006)(2906002)(8936002)(316002)(7636003)(5660300002)(110136005)(70586007)(8676002)(4326008); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2023 10:12:00.9324 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9537b0d9-e6f8-4eeb-9ca9-08db0505ecf2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT106.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5747 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Per newest PRM definition, sample_id stands for 3 parts of information instead of single uint32_t id: sample_id + modify_filed_id + format_select_dw. Also new FW capability bits have been introduces to identify the new capability. Signed-off-by: Rongwei Liu Acked-by: Viacheslav Ovsiienko --- drivers/common/mlx5/mlx5_devx_cmds.c | 14 +++++++++++--- drivers/common/mlx5/mlx5_devx_cmds.h | 7 ++++++- drivers/common/mlx5/mlx5_prm.h | 28 ++++++++++++++++++++++++++-- drivers/net/mlx5/mlx5.c | 15 +++++++++++---- drivers/net/mlx5/mlx5.h | 3 ++- drivers/net/mlx5/mlx5_flow_flex.c | 14 +++++++++++--- 6 files changed, 67 insertions(+), 14 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index e3a4927d0f..1f65ea7dcb 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -607,7 +607,8 @@ mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, - uint32_t ids[], uint32_t num) + struct mlx5_ext_sample_id ids[], + uint32_t num, uint8_t *anchor) { uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; @@ -636,6 +637,7 @@ mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, (void *)flex_obj); return -rte_errno; } + *anchor = MLX5_GET(parse_graph_flex, flex, head_anchor_id); for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { void *s_off = (void *)((char *)sample + i * MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); @@ -645,8 +647,8 @@ mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, flow_match_sample_en); if (!en) continue; - ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, - flow_match_sample_field_id); + ids[idx++].id = MLX5_GET(parse_graph_flow_match_sample, s_off, + flow_match_sample_field_id); } if (num != idx) { rte_errno = EINVAL; @@ -794,6 +796,12 @@ mlx5_devx_cmd_query_hca_parse_graph_node_cap max_num_arc_out); attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr, max_num_sample); + attr->anchor_en = MLX5_GET(parse_graph_node_cap, hcattr, anchor_en); + attr->ext_sample_id = MLX5_GET(parse_graph_node_cap, hcattr, ext_sample_id); + attr->sample_tunnel_inner2 = MLX5_GET(parse_graph_node_cap, hcattr, + sample_tunnel_inner2); + attr->zero_size_supported = MLX5_GET(parse_graph_node_cap, hcattr, + zero_size_supported); attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr, sample_id_in_out); attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr, diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index c94b9eac06..5b33010155 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -114,6 +114,10 @@ struct mlx5_hca_flex_attr { uint8_t max_num_arc_out; uint8_t max_num_sample; uint8_t max_num_prog_sample:5; /* From HCA CAP 2 */ + uint8_t anchor_en:1; + uint8_t ext_sample_id:1; + uint8_t sample_tunnel_inner2:1; + uint8_t zero_size_supported:1; uint8_t sample_id_in_out:1; uint16_t max_base_header_length; uint8_t max_sample_base_offset; @@ -706,7 +710,8 @@ int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, struct mlx5_devx_modify_tir_attr *tir_attr); __rte_internal int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, - uint32_t ids[], uint32_t num); + struct mlx5_ext_sample_id ids[], + uint32_t num, uint8_t *anchor); __rte_internal struct mlx5_devx_obj * diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 9294f65e24..b32dc735a1 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1894,7 +1894,11 @@ struct mlx5_ifc_parse_graph_node_cap_bits { u8 max_num_arc_in[0x08]; u8 max_num_arc_out[0x08]; u8 max_num_sample[0x08]; - u8 reserved_at_78[0x07]; + u8 reserved_at_78[0x03]; + u8 anchor_en[0x1]; + u8 ext_sample_id[0x1]; + u8 sample_tunnel_inner2[0x1]; + u8 zero_size_supported[0x1]; u8 sample_id_in_out[0x1]; u8 max_base_header_length[0x10]; u8 reserved_at_90[0x08]; @@ -1904,6 +1908,24 @@ struct mlx5_ifc_parse_graph_node_cap_bits { u8 header_length_mask_width[0x08]; }; +/* ext_sample_id structure, see PRM Table: Flow Match Sample ID Format. */ +struct mlx5_ext_sample_id { + union { + struct { +#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN + uint32_t format_select_dw:8; + uint32_t modify_field_id:12; + uint32_t sample_id:12; +#else + uint32_t sample_id:12; + uint32_t modify_field_id:12; + uint32_t format_select_dw:8; +#endif + }; + uint32_t id; + }; +}; + struct mlx5_ifc_flow_table_prop_layout_bits { u8 ft_support[0x1]; u8 flow_tag[0x1]; @@ -4542,7 +4564,9 @@ struct mlx5_ifc_parse_graph_flex_bits { u8 header_length_mode[0x4]; u8 header_length_field_offset[0x10]; u8 next_header_field_offset[0x10]; - u8 reserved_at_160[0x1b]; + u8 reserved_at_160[0x12]; + u8 head_anchor_id[0x6]; + u8 reserved_at_178[0x3]; u8 next_header_field_size[0x5]; u8 header_length_field_mask[0x20]; u8 reserved_at_224[0x20]; diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index b8643cebdd..0b97c4e78d 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -964,11 +964,13 @@ int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev) { struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_hca_flex_attr *attr = &priv->sh->cdev->config.hca_attr.flex; struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser; struct mlx5_devx_graph_node_attr node = { .modify_field_select = 0, }; - uint32_t ids[8]; + struct mlx5_ext_sample_id ids[8]; + uint8_t anchor_id; int ret; if (!priv->sh->cdev->config.hca_attr.parse_graph_flex_node) { @@ -1004,15 +1006,20 @@ mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev) return (rte_errno == 0) ? -ENODEV : -rte_errno; } prf->num = 2; - ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num); + ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num, &anchor_id); if (ret) { DRV_LOG(ERR, "Failed to query sample IDs."); return (rte_errno == 0) ? -ENODEV : -rte_errno; } prf->offset[0] = 0x0; prf->offset[1] = sizeof(uint32_t); - prf->ids[0] = ids[0]; - prf->ids[1] = ids[1]; + if (attr->ext_sample_id) { + prf->ids[0] = ids[0].sample_id; + prf->ids[1] = ids[1].sample_id; + } else { + prf->ids[0] = ids[0].id; + prf->ids[1] = ids[1].id; + } return 0; } diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 16b33e1548..83fb316ad8 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1307,9 +1307,10 @@ struct mlx5_lag { struct mlx5_flex_parser_devx { struct mlx5_list_entry entry; /* List element at the beginning. */ uint32_t num_samples; + uint8_t anchor_id; void *devx_obj; struct mlx5_devx_graph_node_attr devx_conf; - uint32_t sample_ids[MLX5_GRAPH_NODE_SAMPLE_NUM]; + struct mlx5_ext_sample_id sample_ids[MLX5_GRAPH_NODE_SAMPLE_NUM]; }; /* Pattern field descriptor - how to translate flex pattern into samples. */ diff --git a/drivers/net/mlx5/mlx5_flow_flex.c b/drivers/net/mlx5/mlx5_flow_flex.c index fb08910ddb..35f2a9923d 100644 --- a/drivers/net/mlx5/mlx5_flow_flex.c +++ b/drivers/net/mlx5/mlx5_flow_flex.c @@ -226,15 +226,18 @@ mlx5_flex_flow_translate_item(struct rte_eth_dev *dev, void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_4); void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4); + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_hca_flex_attr *attr = &priv->sh->cdev->config.hca_attr.flex; struct mlx5_flex_item *tp; uint32_t i, pos = 0; + uint32_t sample_id; RTE_SET_USED(dev); MLX5_ASSERT(item->spec && item->mask); spec = item->spec; mask = item->mask; tp = (struct mlx5_flex_item *)spec->handle; - MLX5_ASSERT(mlx5_flex_index(dev->data->dev_private, tp) >= 0); + MLX5_ASSERT(mlx5_flex_index(priv, tp) >= 0); for (i = 0; i < tp->mapnum; i++) { struct mlx5_flex_pattern_field *map = tp->map + i; uint32_t id = map->reg_id; @@ -257,9 +260,13 @@ mlx5_flex_flow_translate_item(struct rte_eth_dev *dev, MLX5_ASSERT(id < num_samples); id += num_samples; } + if (attr->ext_sample_id) + sample_id = tp->devx_fp->sample_ids[id].sample_id; + else + sample_id = tp->devx_fp->sample_ids[id].id; mlx5_flex_set_match_sample(misc4_m, misc4_v, def, msk & def, val & msk & def, - tp->devx_fp->sample_ids[id], id); + sample_id, id); pos += map->width; } } @@ -1298,7 +1305,8 @@ mlx5_flex_parser_create_cb(void *list_ctx, void *ctx) /* Query the firmware assigned sample ids. */ ret = mlx5_devx_cmd_query_parse_samples(fp->devx_obj, fp->sample_ids, - fp->num_samples); + fp->num_samples, + &fp->anchor_id); if (ret) goto error; DRV_LOG(DEBUG, "DEVx flex parser %p created, samples num: %u", From patchwork Thu Feb 2 10:11:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rongwei Liu X-Patchwork-Id: 122916 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7D7CC41BAB; Thu, 2 Feb 2023 11:12:13 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CE4C042D65; Thu, 2 Feb 2023 11:12:07 +0100 (CET) Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2040.outbound.protection.outlook.com [40.107.236.40]) by mails.dpdk.org (Postfix) with ESMTP id 0325C42D7E for ; Thu, 2 Feb 2023 11:12:06 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Xuu033VuRitPHyUiqzWnYGCAnDvaAKnYno0JXJPgkWH1MOBGbJ+I32QYKs9yFH/JpiDwSVon/Rz/vN5Qqw6kwwOrR8mk1HC5rN4fEMXfeA+Peewt5bIpsQP67c43A124AL658am6FdxeWj7ZuFCSRAPEPxQsllcld5IYI8dsEPxL9f0d+GjGV5e0Lg5jCd7cz5Thg/3x3QPlBX6pEF5BWtuOyFYxUeJOXh6+lhPsWGPdBrNk+PKIVmD1bz0FOcBIR97aNFlcvBHGi8q13IS4UqPf9gskS7f1ctt2gkXpCXdwuPNxbYsvvcqRFWH/zVJTSDlJhDCSOJSwextSjACIKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=R1X6dDsqH+9LW7PaVUHxAX3FmCQXcyEv8Q82zCepYRk=; b=XaGM8fgkzMjTLOH11kueDmckFEJoxRPy6NL7gngVRjeRtjOVkXegEKUAQD2y2bifzbQIwuuPyrad+UYW+70s0AZXMFYpbFV/+7f42OrpHYsN2BgTsCmBJ2WQ+O56apK9luqve5K3ueaDsFJqFi31CQSLDVkcZlgk/oekp+XtMgQMwfI6jLccLFDzFQxQjDqUu+1k2nbUnEdt/GTGowdI/QaU4Zj4CQbJ1sPZZWtkrn05uk4q1jTkiTFSCAnqGLx75enN0H/yV9JvV8uJ69gEEC3psPV+5Ih/T/FUbfdeNBEYSIyVqdso8VYXWCth7fsnfx+7WpX+PtElTnMoqPA7Qg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=R1X6dDsqH+9LW7PaVUHxAX3FmCQXcyEv8Q82zCepYRk=; b=FNwocBcWz0MlKz+29lPTlwieMiBXWS/FiKBsTB5oaQU3mz+AU4fszC0YeZQwzU+IugvCfIoXnEZZphC1k6unmrsp4s0whZO/gFdmrH+93307yIucbf5GJ+uETsSQ1UHncaXNCaKhO2CIIQhirVCuSaB6gTqSuHna2PdJcBMHWEAfumcBkuU2ujZixLlWJeVcS9CbAqgIcicZwljclBpca6ateTWeW9cO0Za3wMO8B202s0fd1El1ohVnxMdGAS74CRiia0bxh+Pcyv9nXyKmzpRBBm0Ql1GKvwtjhBw1CkiGlH2rAVkQHpwbPV7kTGJa3g4VEDx7pmsCnc2qTFKDOg== Received: from BN1PR12CA0001.namprd12.prod.outlook.com (2603:10b6:408:e1::6) by DS0PR12MB8020.namprd12.prod.outlook.com (2603:10b6:8:14f::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6043.36; Thu, 2 Feb 2023 10:12:04 +0000 Received: from BN8NAM11FT106.eop-nam11.prod.protection.outlook.com (2603:10b6:408:e1:cafe::3e) by BN1PR12CA0001.outlook.office365.com (2603:10b6:408:e1::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6064.27 via Frontend Transport; Thu, 2 Feb 2023 10:12:04 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BN8NAM11FT106.mail.protection.outlook.com (10.13.177.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6064.27 via Frontend Transport; Thu, 2 Feb 2023 10:12:04 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Thu, 2 Feb 2023 02:11:48 -0800 Received: from nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Thu, 2 Feb 2023 02:11:45 -0800 From: Rongwei Liu To: , , , , CC: , Gregory Etelson , Alex Vesker Subject: [PATCH v1 2/5] net/mlx5/hws: Definer, add mlx5dr context to definer_conv_data Date: Thu, 2 Feb 2023 12:11:25 +0200 Message-ID: <20230202101128.2446928-3-rongweil@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230202101128.2446928-1-rongweil@nvidia.com> References: <20230202101128.2446928-1-rongweil@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT106:EE_|DS0PR12MB8020:EE_ X-MS-Office365-Filtering-Correlation-Id: c6fabd29-ad08-4064-0b3b-08db0505eed9 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: v8XgBRL73IwwGjErCwMoDODxmv0Xf/hqbGt7xsEuBjOX54so8exQA/2HoVXTXfvKUMNJ0g0yeuuTbo8DP5QndF/b/5yarEoovXtL6MQc9B61tyoBFXq4tksWD3jGqWNpsqRhW3Oku0Kk/BzQuX3BTZvWkPxz1Ilrn55Uz3siLUf4oud6Tt+Fsd4ef9/015IHHAOhkdutAzsD1sefHDmiRpLSLDtT/hCuBDxDSYySgzfGdu4YCm2eF4qyJRPsD+JnxtlggFYW8kp/uU44pD46CWJzYbXpxh/RmKlWrGht/UlJ4vmAvYpS6mEPUMd3uly7B040u5MrpI+UT3IhkSP3HVVeTqnkMV27rbYrywjaQYHOh2exG7yX/u/xBzjwgAGFLxYjr5EV5xD3J23o7ejFCgIRnMPb6x7efWaLndTaWeUiYO0SJQ1yPQx6AFcSJfP1OhBIxeT7VFj/fXXbDo9kwJg9VtQkg2NSZSAPHkoazuewDOFknX87/wRfT+cQU7WWTIaTqleRXLmO5PHevAwOKhz/wH9UgJzVFk8Zm4Vrl2PX9K3Q576mTeWrjX0dJcWr9evUkCgsBa7ktilx/D8VKUfF58fa/HGmxok7toJ0qFZR3mbGcGBq5SmxdSSwBc9VFrgadEnKM3B7MbI6UnkTYQxzdXkbxo5I5vybuip0tirCzkxWJs8YHofZFCsiwWHYmL+DA/IFW1SAPtoWsKpPyG1fzSg4POcjhgqn0E+fseqIiXySWakNthkDPUeN094f X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230025)(4636009)(136003)(376002)(39860400002)(396003)(346002)(451199018)(36840700001)(46966006)(40470700004)(110136005)(36756003)(54906003)(4326008)(70586007)(36860700001)(8676002)(70206006)(8936002)(5660300002)(316002)(86362001)(7636003)(356005)(82740400003)(6666004)(1076003)(6286002)(16526019)(186003)(26005)(107886003)(55016003)(82310400005)(478600001)(336012)(2906002)(40460700003)(83380400001)(40480700001)(7696005)(2616005)(47076005)(426003)(41300700001)(42413004)(32563001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2023 10:12:04.1202 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c6fabd29-ad08-4064-0b3b-08db0505eed9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT106.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8020 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Gregory Etelson New mlx5dr_context member replaces mlx5dr_cmd_query_caps. Capabilities structure is a member of mlx5dr_context. Signed-off-by: Gregory Etelson Signed-off-by: Rongwei Liu Reviewed-by: Alex Vesker Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/hws/mlx5dr_definer.c | 42 ++++++++++++++------------- 1 file changed, 22 insertions(+), 20 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index 6b98eb8c96..0f1cab7e07 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -100,7 +100,7 @@ struct mlx5dr_definer_sel_ctrl { }; struct mlx5dr_definer_conv_data { - struct mlx5dr_cmd_query_caps *caps; + struct mlx5dr_context *ctx; struct mlx5dr_definer_fc *fc; uint8_t relaxed; uint8_t tunnel; @@ -815,6 +815,7 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, struct rte_flow_item *item, int item_idx) { + struct mlx5dr_cmd_query_caps *caps = cd->ctx->caps; const struct rte_flow_item_gtp *m = item->mask; struct mlx5dr_definer_fc *fc; @@ -836,7 +837,7 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, } if (m->teid) { - if (!(cd->caps->flex_protocols & MLX5_HCA_FLEX_GTPU_TEID_ENABLED)) { + if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_TEID_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; } @@ -844,11 +845,11 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, fc->item_idx = item_idx; fc->tag_set = &mlx5dr_definer_gtp_teid_set; fc->bit_mask = __mlx5_mask(header_gtp, teid); - fc->byte_off = cd->caps->format_select_gtpu_dw_1 * DW_SIZE; + fc->byte_off = caps->format_select_gtpu_dw_1 * DW_SIZE; } if (m->v_pt_rsv_flags) { - if (!(cd->caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_0_ENABLED)) { + if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_0_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; } @@ -857,12 +858,12 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, fc->tag_set = &mlx5dr_definer_gtp_ext_flag_set; fc->bit_mask = __mlx5_mask(header_gtp, ext_hdr_flag); fc->bit_off = __mlx5_dw_bit_off(header_gtp, ext_hdr_flag); - fc->byte_off = cd->caps->format_select_gtpu_dw_0 * DW_SIZE; + fc->byte_off = caps->format_select_gtpu_dw_0 * DW_SIZE; } if (m->msg_type) { - if (!(cd->caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_0_ENABLED)) { + if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_0_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; } @@ -871,7 +872,7 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, fc->tag_set = &mlx5dr_definer_gtp_msg_type_set; fc->bit_mask = __mlx5_mask(header_gtp, msg_type); fc->bit_off = __mlx5_dw_bit_off(header_gtp, msg_type); - fc->byte_off = cd->caps->format_select_gtpu_dw_0 * DW_SIZE; + fc->byte_off = caps->format_select_gtpu_dw_0 * DW_SIZE; } return 0; @@ -882,12 +883,13 @@ mlx5dr_definer_conv_item_gtp_psc(struct mlx5dr_definer_conv_data *cd, struct rte_flow_item *item, int item_idx) { + struct mlx5dr_cmd_query_caps *caps = cd->ctx->caps; const struct rte_flow_item_gtp_psc *m = item->mask; struct mlx5dr_definer_fc *fc; /* Overwrite GTP extension flag to be 1 */ if (!cd->relaxed) { - if (!(cd->caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_0_ENABLED)) { + if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_0_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; } @@ -896,12 +898,12 @@ mlx5dr_definer_conv_item_gtp_psc(struct mlx5dr_definer_conv_data *cd, fc->tag_set = &mlx5dr_definer_ones_set; fc->bit_mask = __mlx5_mask(header_gtp, ext_hdr_flag); fc->bit_off = __mlx5_dw_bit_off(header_gtp, ext_hdr_flag); - fc->byte_off = cd->caps->format_select_gtpu_dw_0 * DW_SIZE; + fc->byte_off = caps->format_select_gtpu_dw_0 * DW_SIZE; } /* Overwrite next extension header type */ if (!cd->relaxed) { - if (!(cd->caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_2_ENABLED)) { + if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_2_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; } @@ -911,14 +913,14 @@ mlx5dr_definer_conv_item_gtp_psc(struct mlx5dr_definer_conv_data *cd, fc->tag_mask_set = &mlx5dr_definer_ones_set; fc->bit_mask = __mlx5_mask(header_opt_gtp, next_ext_hdr_type); fc->bit_off = __mlx5_dw_bit_off(header_opt_gtp, next_ext_hdr_type); - fc->byte_off = cd->caps->format_select_gtpu_dw_2 * DW_SIZE; + fc->byte_off = caps->format_select_gtpu_dw_2 * DW_SIZE; } if (!m) return 0; if (m->hdr.type) { - if (!(cd->caps->flex_protocols & MLX5_HCA_FLEX_GTPU_FIRST_EXT_DW_0_ENABLED)) { + if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_FIRST_EXT_DW_0_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; } @@ -927,11 +929,11 @@ mlx5dr_definer_conv_item_gtp_psc(struct mlx5dr_definer_conv_data *cd, fc->tag_set = &mlx5dr_definer_gtp_ext_hdr_pdu_set; fc->bit_mask = __mlx5_mask(header_gtp_psc, pdu_type); fc->bit_off = __mlx5_dw_bit_off(header_gtp_psc, pdu_type); - fc->byte_off = cd->caps->format_select_gtpu_ext_dw_0 * DW_SIZE; + fc->byte_off = caps->format_select_gtpu_ext_dw_0 * DW_SIZE; } if (m->hdr.qfi) { - if (!(cd->caps->flex_protocols & MLX5_HCA_FLEX_GTPU_FIRST_EXT_DW_0_ENABLED)) { + if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_FIRST_EXT_DW_0_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; } @@ -940,7 +942,7 @@ mlx5dr_definer_conv_item_gtp_psc(struct mlx5dr_definer_conv_data *cd, fc->tag_set = &mlx5dr_definer_gtp_ext_hdr_qfi_set; fc->bit_mask = __mlx5_mask(header_gtp_psc, qfi); fc->bit_off = __mlx5_dw_bit_off(header_gtp_psc, qfi); - fc->byte_off = cd->caps->format_select_gtpu_ext_dw_0 * DW_SIZE; + fc->byte_off = caps->format_select_gtpu_ext_dw_0 * DW_SIZE; } return 0; @@ -951,18 +953,19 @@ mlx5dr_definer_conv_item_port(struct mlx5dr_definer_conv_data *cd, struct rte_flow_item *item, int item_idx) { + struct mlx5dr_cmd_query_caps *caps = cd->ctx->caps; const struct rte_flow_item_ethdev *m = item->mask; struct mlx5dr_definer_fc *fc; uint8_t bit_offset = 0; if (m->port_id) { - if (!cd->caps->wire_regc_mask) { + if (!caps->wire_regc_mask) { DR_LOG(ERR, "Port ID item not supported, missing wire REGC mask"); rte_errno = ENOTSUP; return rte_errno; } - while (!(cd->caps->wire_regc_mask & (1 << bit_offset))) + while (!(caps->wire_regc_mask & (1 << bit_offset))) bit_offset++; fc = &cd->fc[MLX5DR_DEFINER_FNAME_VPORT_REG_C_0]; @@ -971,7 +974,7 @@ mlx5dr_definer_conv_item_port(struct mlx5dr_definer_conv_data *cd, fc->tag_mask_set = &mlx5dr_definer_ones_set; DR_CALC_SET_HDR(fc, registers, register_c_0); fc->bit_off = bit_offset; - fc->bit_mask = cd->caps->wire_regc_mask >> bit_offset; + fc->bit_mask = caps->wire_regc_mask >> bit_offset; } else { DR_LOG(ERR, "Pord ID item mask must specify ID mask"); rte_errno = EINVAL; @@ -1479,8 +1482,7 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, int ret; cd.fc = fc; - cd.hl = hl; - cd.caps = ctx->caps; + cd.ctx = ctx; cd.relaxed = mt->flags & MLX5DR_MATCH_TEMPLATE_FLAG_RELAXED_MATCH; /* Collect all RTE fields to the field array and set header layout */ From patchwork Thu Feb 2 10:11:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rongwei Liu X-Patchwork-Id: 122917 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 016FE41BAB; Thu, 2 Feb 2023 11:12:23 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6E98642DA0; Thu, 2 Feb 2023 11:12:09 +0100 (CET) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2070.outbound.protection.outlook.com [40.107.94.70]) by mails.dpdk.org (Postfix) with ESMTP id 24B5642D65 for ; Thu, 2 Feb 2023 11:12:07 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=JgLDYJicvcx7vU/PCZxWoXzClqqxwJYhOL4c4hi1XY8KYt365RO/p4FWYtwBLP8NJL8h6wSl3mahb2JfhHucwQs7R/7wAq31yZhNzQSYsbh8MxYlluHt/mWLPdQyKUaC1AmKxcUbF1r9KOvq2WxjT1ySIROVEzrEIRS9RB5ampFF3tLbr18gIKiQIKvvGaYjPOPAkvNbSkqgqgtuo8/Ps1OJgbgGi5wnUi+vFlNSHIegFm0RL4OH4z4Xc/4mEvjG8aGSn47Yo/02iTVS3FIVHqq6FmcYA7RhyMoBKR/k6DtNG4xb+SFmII6cLZJZPAXwFLEbZWvhXtsJRMBcDvt7Vg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=6WxSHurTYpqgKKdb3Z6VrRfl0MerqxEHifLlsPK2lN4=; b=oR8qb1ihnmfiRkp1S/Z7xf9iMWe5fMo2VeE1OWqqOLJ6YQUc6jiRDHi32EP6VgCimK1fy5gBiQAxI9BETh4qwXngBsN5Hz0pZMaTFpcF/bs1Neuik8I6I7Il72X2GxOruH+86TH2ry3bmLoOfLhi6x3FCHwfqhSk9vsLNnOdMC+v6GdEGE+S49NRZFqOtnhdGSNVQkynXTeYrnzMvgh/lFjgKSm8TIx17/Hw39pXE4BoPFfyfHaM4z6VDpf9gd9hK857vVB93n57bVQct3zozZQyF13Ad22AI9Sp1KKqa83rI6NaKiun11wT9GjG6lV+Kkc2CyyPE6xFupcyARTtvQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6WxSHurTYpqgKKdb3Z6VrRfl0MerqxEHifLlsPK2lN4=; b=Gtk5g3BrbPSHj00uxSTmRuqKPE15iYRuh213B1YrY6h5IWAFCsPuI+4Shnt7iuU/NcgNEzmudiedi/Wa+1h3dIKSq6dFohcMJsUnQ/wzl261WuEBOneJtWBFyk6EI8xUMpWvGyfF4HFYImijcb3pA9y3UujcCnD7VjN5YHqU6urE1W1bJ2RjV3rm5LpzLpqJ5yID7gKpB55I57jKqbhLYkbwBd8L8v3pK4Q+5o/atVOWxiOeL/aSjnphNVqLTF6iDpXQ2u9A4b0lua+VcpJDFyH/E6Zbl2OAREd0+EVNcb6CzS9Lpp+Pg4k8vnmYpJOkaJHHp2ztdQYk3IVQf1a4EA== Received: from BN9PR03CA0465.namprd03.prod.outlook.com (2603:10b6:408:139::20) by DM4PR12MB6471.namprd12.prod.outlook.com (2603:10b6:8:ba::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6043.30; Thu, 2 Feb 2023 10:12:04 +0000 Received: from BN8NAM11FT087.eop-nam11.prod.protection.outlook.com (2603:10b6:408:139:cafe::d7) by BN9PR03CA0465.outlook.office365.com (2603:10b6:408:139::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6064.23 via Frontend Transport; Thu, 2 Feb 2023 10:12:04 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BN8NAM11FT087.mail.protection.outlook.com (10.13.177.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6064.27 via Frontend Transport; Thu, 2 Feb 2023 10:12:04 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Thu, 2 Feb 2023 02:11:51 -0800 Received: from nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Thu, 2 Feb 2023 02:11:48 -0800 From: Rongwei Liu To: , , , , CC: , Alex Vesker Subject: [PATCH v1 3/5] net/mlx5/hws: add IPv6 routing extension matching support Date: Thu, 2 Feb 2023 12:11:26 +0200 Message-ID: <20230202101128.2446928-4-rongweil@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230202101128.2446928-1-rongweil@nvidia.com> References: <20230202101128.2446928-1-rongweil@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT087:EE_|DM4PR12MB6471:EE_ X-MS-Office365-Filtering-Correlation-Id: 84c2b507-d5e2-4467-0638-08db0505ef0e X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: YJ9W7iwWhwpGZCHJMfMLE0wQp25vJOsAMEaqWVCl79LiJNDkiUOC9s+vCeEVCyTOvv9UwTDjhszpkzkcrjSEh8kmJqf8f9XE1xd0Oc+P4phFfmmRL/zqSsdrQ6lIJ6W5xV6YmjKe6xJIAeKfegqlt+obgjOZfIUFEFPHnr2dTirtu9iQYATulhVNCfK1N0CV6xDh5fASRWvGXsFcqplRWj56fgqqoqL68gIJuUx2Hql7r1H4a69Nh9fE/OInfDKDwEKbiVKbuWUTysf0latAk9Yj++NkSukA+FJ6Tb4amsTn+s3tN6q5MTbdKZ8lCaAvuN38RojLoxD/k2RNOgti3QEcddSyZ07p1aaAVDyRDUGFGWmJ9luzDDSNGhtgZ+4yrNThSBDvJaUS2Pm5uBwMxIpHPw19T+HD1mqLCtZMsZL/cgJRykziBvuxAVqpGoLMJ+pDgKR7q9P8E/NGEEn2B6tJtzSsDJsMPx7CjVaZlgqBh/M0QYYhPKlrwp/3vO0pbW5ie2/Rgnxsf1jwxmFMHg+JlYcapgaFrjCka868id3AYBWKjF2m1s/Mgxg9mRT9zt2nj4ddSonWnRzUo+B6Eg2e23Iyl4XTUsdDtD8ZljsoJFq3uF2QkIA2GGbjFIxxST223z3KTjT059V9MDK/OPd7kBr0CRsj6hloDh2LSJ/P7HfWLv8+htHeYlJMsgBz7DjPWi6n2im03Gwg+bfwTA== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230025)(4636009)(376002)(396003)(136003)(346002)(39860400002)(451199018)(36840700001)(40470700004)(46966006)(86362001)(356005)(2906002)(478600001)(7696005)(82310400005)(107886003)(41300700001)(6666004)(110136005)(8936002)(5660300002)(36860700001)(30864003)(54906003)(8676002)(316002)(40480700001)(55016003)(70586007)(186003)(40460700003)(82740400003)(70206006)(7636003)(6286002)(4326008)(83380400001)(16526019)(26005)(1076003)(47076005)(336012)(426003)(2616005)(36756003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2023 10:12:04.4675 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 84c2b507-d5e2-4467-0638-08db0505ef0e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT087.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6471 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add mlx5 HWS logic to match IPv6 routing extension header. Once detecting IPv6 matching extension items in pattern template create callback, PMD allocates a flex parser to sample the first dword of srv6 header. Only support next_hdr/segments_left/type for now. Signed-off-by: Rongwei Liu Reviewed-by: Alex Vesker Acked-by: Viacheslav Ovsiienko --- drivers/common/mlx5/mlx5_devx_cmds.c | 7 +- drivers/net/mlx5/hws/mlx5dr_definer.c | 91 ++++++++++++++++++++++++++ drivers/net/mlx5/hws/mlx5dr_definer.h | 15 +++++ drivers/net/mlx5/mlx5.c | 92 ++++++++++++++++++++++++++- drivers/net/mlx5/mlx5.h | 16 +++++ drivers/net/mlx5/mlx5_flow.h | 28 ++++++++ drivers/net/mlx5/mlx5_flow_hw.c | 29 +++++++-- 7 files changed, 268 insertions(+), 10 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 1f65ea7dcb..22a94c1e1a 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -607,7 +607,7 @@ mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, - struct mlx5_ext_sample_id ids[], + struct mlx5_ext_sample_id *ids, uint32_t num, uint8_t *anchor) { uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; @@ -637,8 +637,9 @@ mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, (void *)flex_obj); return -rte_errno; } - *anchor = MLX5_GET(parse_graph_flex, flex, head_anchor_id); - for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { + if (anchor) + *anchor = MLX5_GET(parse_graph_flex, flex, head_anchor_id); + for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM && idx <= num; i++) { void *s_off = (void *)((char *)sample + i * MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); uint32_t en; diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index 0f1cab7e07..142fc545eb 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -125,6 +125,7 @@ struct mlx5dr_definer_conv_data { X(SET_BE16, ipv4_frag, v->fragment_offset, rte_ipv4_hdr) \ X(SET_BE16, ipv6_payload_len, v->hdr.payload_len, rte_flow_item_ipv6) \ X(SET, ipv6_proto, v->hdr.proto, rte_flow_item_ipv6) \ + X(SET, ipv6_routing_hdr, IPPROTO_ROUTING, rte_flow_item_ipv6) \ X(SET, ipv6_hop_limits, v->hdr.hop_limits, rte_flow_item_ipv6) \ X(SET_BE32P, ipv6_src_addr_127_96, &v->hdr.src_addr[0], rte_flow_item_ipv6) \ X(SET_BE32P, ipv6_src_addr_95_64, &v->hdr.src_addr[4], rte_flow_item_ipv6) \ @@ -293,6 +294,21 @@ mlx5dr_definer_integrity_set(struct mlx5dr_definer_fc *fc, DR_SET(tag, ok1_bits, fc->byte_off, fc->bit_off, fc->bit_mask); } +static void +mlx5dr_definer_ipv6_routing_ext_set(struct mlx5dr_definer_fc *fc, + const void *item, + uint8_t *tag) +{ + const struct rte_flow_item_ipv6_routing_ext *v = item; + uint32_t val; + + val = v->hdr.next_hdr << __mlx5_dw_bit_off(header_ipv6_routing_ext, next_hdr); + val |= v->hdr.type << __mlx5_dw_bit_off(header_ipv6_routing_ext, type); + val |= v->hdr.segments_left << + __mlx5_dw_bit_off(header_ipv6_routing_ext, segments_left); + DR_SET(tag, val, fc->byte_off, 0, fc->bit_mask); +} + static void mlx5dr_definer_gre_key_set(struct mlx5dr_definer_fc *fc, const void *item_spec, @@ -1468,6 +1484,76 @@ mlx5dr_definer_conv_item_meter_color(struct mlx5dr_definer_conv_data *cd, return 0; } +static struct mlx5dr_definer_fc * +mlx5dr_definer_get_flex_parser_fc(struct mlx5dr_definer_conv_data *cd, uint32_t byte_off) +{ + uint32_t byte_off_fp7 = MLX5_BYTE_OFF(definer_hl, flex_parser.flex_parser_7); + uint32_t byte_off_fp0 = MLX5_BYTE_OFF(definer_hl, flex_parser.flex_parser_0); + enum mlx5dr_definer_fname fname = MLX5DR_DEFINER_FNAME_FLEX_PARSER_0; + struct mlx5dr_definer_fc *fc; + uint32_t idx; + + if (byte_off < byte_off_fp7 || byte_off > byte_off_fp0) { + rte_errno = EINVAL; + return NULL; + } + idx = (byte_off_fp0 - byte_off) / (sizeof(uint32_t)); + fname += (enum mlx5dr_definer_fname)idx; + fc = &cd->fc[fname]; + fc->byte_off = byte_off; + fc->bit_mask = UINT32_MAX; + return fc; +} + +static int +mlx5dr_definer_conv_item_ipv6_routing_ext(struct mlx5dr_definer_conv_data *cd, + struct rte_flow_item *item, + int item_idx) +{ + const struct rte_flow_item_ipv6_routing_ext *m = item->mask; + struct mlx5dr_definer_fc *fc; + bool inner = cd->tunnel; + uint32_t byte_off; + + if (!cd->relaxed) { + fc = &cd->fc[DR_CALC_FNAME(IP_VERSION, inner)]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_ipv6_version_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + DR_CALC_SET(fc, eth_l2, l3_type, inner); + + /* Overwrite - Unset ethertype if present */ + memset(&cd->fc[DR_CALC_FNAME(ETH_TYPE, inner)], 0, sizeof(*fc)); + + fc = &cd->fc[DR_CALC_FNAME(IP_PROTOCOL, inner)]; + if (!fc->tag_set) { + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_ipv6_routing_hdr_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + DR_CALC_SET(fc, eth_l3, protocol_next_header, inner); + } + } + + if (!m) + return 0; + + if (m->hdr.hdr_len || m->hdr.flags) { + rte_errno = ENOTSUP; + return rte_errno; + } + + if (m->hdr.next_hdr || m->hdr.type || m->hdr.segments_left) { + byte_off = flow_hw_get_srh_flex_parser_byte_off_from_ctx(cd->ctx); + fc = mlx5dr_definer_get_flex_parser_fc(cd, byte_off); + if (!fc) + return rte_errno; + + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_ipv6_routing_ext_set; + } + return 0; +} + static int mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, struct mlx5dr_match_template *mt, @@ -1583,6 +1669,11 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, ret = mlx5dr_definer_conv_item_meter_color(&cd, items, i); item_flags |= MLX5_FLOW_ITEM_METER_COLOR; break; + case RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT: + ret = mlx5dr_definer_conv_item_ipv6_routing_ext(&cd, items, i); + item_flags |= cd.tunnel ? MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT : + MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT; + break; default: DR_LOG(ERR, "Unsupported item type %d", items->type); rte_errno = ENOTSUP; diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h index d52c6b0627..c857848a28 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.h +++ b/drivers/net/mlx5/hws/mlx5dr_definer.h @@ -511,6 +511,21 @@ struct mlx5_ifc_header_ipv6_vtc_bits { u8 flow_label[0x14]; }; +struct mlx5_ifc_header_ipv6_routing_ext_bits { + u8 next_hdr[0x8]; + u8 hdr_len[0x8]; + u8 type[0x8]; + u8 segments_left[0x8]; + union { + u8 flags[0x20]; + struct { + u8 last_entry[0x8]; + u8 flag[0x8]; + u8 tag[0x10]; + }; + }; +}; + struct mlx5_ifc_header_vxlan_bits { u8 flags[0x8]; u8 reserved1[0x18]; diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index 0b97c4e78d..94fd5a91e3 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -970,7 +970,6 @@ mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev) .modify_field_select = 0, }; struct mlx5_ext_sample_id ids[8]; - uint8_t anchor_id; int ret; if (!priv->sh->cdev->config.hca_attr.parse_graph_flex_node) { @@ -1006,7 +1005,7 @@ mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev) return (rte_errno == 0) ? -ENODEV : -rte_errno; } prf->num = 2; - ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num, &anchor_id); + ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num, NULL); if (ret) { DRV_LOG(ERR, "Failed to query sample IDs."); return (rte_errno == 0) ? -ENODEV : -rte_errno; @@ -1041,6 +1040,95 @@ mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev) prf->obj = NULL; } +/* + * Allocation of a flex parser for srh. Once refcnt is zero, the resources held + * by this parser will be freed. + * @param dev + * Pointer to Ethernet device structure. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_alloc_srh_flex_parser(struct rte_eth_dev *dev) +{ + struct mlx5_devx_graph_node_attr node = { + .modify_field_select = 0, + }; + struct mlx5_ext_sample_id ids[MLX5_GRAPH_NODE_SAMPLE_NUM]; + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_common_dev_config *config = &priv->sh->cdev->config; + void *ibv_ctx = priv->sh->cdev->ctx; + int ret; + + memset(ids, 0xff, sizeof(ids)); + if (!config->hca_attr.parse_graph_flex_node) { + DRV_LOG(ERR, "Dynamic flex parser is not supported"); + return -ENOTSUP; + } + if (__atomic_add_fetch(&priv->sh->srh_flex_parser.refcnt, 1, __ATOMIC_RELAXED) > 1) + return 0; + + node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIELD; + /* Srv6 first two DW are not counted in. */ + node.header_length_base_value = 0x8; + /* The unit is uint64_t. */ + node.header_length_field_shift = 0x3; + /* Header length is the 2nd byte. */ + node.header_length_field_offset = 0x8; + node.header_length_field_mask = 0xF; + /* One byte next header protocol. */ + node.next_header_field_size = 0x8; + node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_IP; + node.in[0].compare_condition_value = IPPROTO_ROUTING; + node.sample[0].flow_match_sample_en = 1; + /* First come first serve no matter inner or outer. */ + node.sample[0].flow_match_sample_tunnel_mode = MLX5_GRAPH_SAMPLE_TUNNEL_FIRST; + node.out[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_TCP; + node.out[0].compare_condition_value = IPPROTO_TCP; + node.out[1].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_UDP; + node.out[1].compare_condition_value = IPPROTO_UDP; + node.out[2].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_IPV6; + node.out[2].compare_condition_value = IPPROTO_IPV6; + priv->sh->srh_flex_parser.fp = mlx5_devx_cmd_create_flex_parser(ibv_ctx, &node); + if (!priv->sh->srh_flex_parser.fp) { + DRV_LOG(ERR, "Failed to create flex parser node object."); + return (rte_errno == 0) ? -ENODEV : -rte_errno; + } + priv->sh->srh_flex_parser.num = 1; + ret = mlx5_devx_cmd_query_parse_samples(priv->sh->srh_flex_parser.fp, ids, + priv->sh->srh_flex_parser.num, + &priv->sh->srh_flex_parser.anchor_id); + if (ret) { + DRV_LOG(ERR, "Failed to query sample IDs."); + return (rte_errno == 0) ? -ENODEV : -rte_errno; + } + priv->sh->srh_flex_parser.offset[0] = 0x0; + priv->sh->srh_flex_parser.ids[0].id = ids[0].id; + return 0; +} + +/* + * Destroy the flex parser node, including the parser itself, input / output + * arcs and DW samples. Resources could be reused then. + * + * @param dev + * Pointer to Ethernet device structure + */ +void +mlx5_free_srh_flex_parser(struct rte_eth_dev *dev) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_internal_flex_parser_profile *fp = &priv->sh->srh_flex_parser; + + if (__atomic_sub_fetch(&fp->refcnt, 1, __ATOMIC_RELAXED)) + return; + if (fp->fp) + mlx5_devx_cmd_destroy(fp->fp); + fp->fp = NULL; + fp->num = 0; +} + uint32_t mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr) { diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 83fb316ad8..bea1f62ea8 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -543,6 +543,17 @@ struct mlx5_counter_stats_raw { volatile struct flow_counter_stats *data; }; +/* Mlx5 internal flex parser profile structure. */ +struct mlx5_internal_flex_parser_profile { + uint32_t num;/* Actual number of samples. */ + /* Sample IDs for this profile. */ + struct mlx5_ext_sample_id ids[MLX5_FLEX_ITEM_MAPPING_NUM]; + uint32_t offset[MLX5_FLEX_ITEM_MAPPING_NUM]; /* Each ID sample offset. */ + uint8_t anchor_id; + uint32_t refcnt; + void *fp; /* DevX flex parser object. */ +}; + TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool); /* Counter global management structure. */ @@ -1436,6 +1447,7 @@ struct mlx5_dev_ctx_shared { struct mlx5_uar rx_uar; /* DevX UAR for Rx. */ struct mlx5_proc_priv *pppriv; /* Pointer to primary private process. */ struct mlx5_ecpri_parser_profile ecpri_parser; + struct mlx5_internal_flex_parser_profile srh_flex_parser; /* srh flex parser structure. */ /* Flex parser profiles information. */ LIST_HEAD(shared_rxqs, mlx5_rxq_ctrl) shared_rxqs; /* Shared RXQs. */ struct mlx5_aso_age_mng *aso_age_mng; @@ -2258,4 +2270,8 @@ struct mlx5_list_entry *mlx5_flex_parser_clone_cb(void *list_ctx, void *ctx); void mlx5_flex_parser_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry); + +int mlx5_alloc_srh_flex_parser(struct rte_eth_dev *dev); + +void mlx5_free_srh_flex_parser(struct rte_eth_dev *dev); #endif /* RTE_PMD_MLX5_H_ */ diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index e376dcae93..1f359cfb12 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -219,6 +219,10 @@ enum mlx5_feature_name { /* Meter color item */ #define MLX5_FLOW_ITEM_METER_COLOR (UINT64_C(1) << 44) +/* IPv6 routing extension item */ +#define MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT (UINT64_C(1) << 45) +#define MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT (UINT64_C(1) << 46) + /* Outer Masks. */ #define MLX5_FLOW_LAYER_OUTER_L3 \ (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) @@ -2611,4 +2615,28 @@ int mlx5_flow_item_field_width(struct rte_eth_dev *dev, enum rte_flow_field_id field, int inherit, const struct rte_flow_attr *attr, struct rte_flow_error *error); + +static __rte_always_inline int +flow_hw_get_srh_flex_parser_byte_off_from_ctx(void *dr_ctx __rte_unused) +{ +#ifdef HAVE_IBV_FLOW_DV_SUPPORT + uint16_t port; + + MLX5_ETH_FOREACH_DEV(port, NULL) { + struct mlx5_priv *priv; + struct mlx5_hca_flex_attr *attr; + + priv = rte_eth_devices[port].data->dev_private; + attr = &priv->sh->cdev->config.hca_attr.flex; + if (priv->dr_ctx == dr_ctx && attr->ext_sample_id) { + if (priv->sh->srh_flex_parser.num) + return priv->sh->srh_flex_parser.ids[0].format_select_dw * + sizeof(uint32_t); + else + return UINT32_MAX; + } + } +#endif + return UINT32_MAX; +} #endif /* RTE_PMD_MLX5_FLOW_H_ */ diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 952247d3cf..d0e07acc4e 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -213,17 +213,17 @@ flow_hw_hashfields_set(struct mlx5_flow_rss_desc *rss_desc, } /** - * Generate the pattern item flags. - * Will be used for shared RSS action. + * Generate the matching pattern item flags. * * @param[in] items * Pointer to the list of items. * * @return - * Item flags. + * Matching item flags. RSS hash field function + * silently ignores the flags which are unsupported. */ static uint64_t -flow_hw_rss_item_flags_get(const struct rte_flow_item items[]) +flow_hw_matching_item_flags_get(const struct rte_flow_item items[]) { uint64_t item_flags = 0; uint64_t last_item = 0; @@ -249,6 +249,10 @@ flow_hw_rss_item_flags_get(const struct rte_flow_item items[]) last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP : MLX5_FLOW_LAYER_OUTER_L4_UDP; break; + case RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT: + last_item = tunnel ? MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT : + MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT; + break; case RTE_FLOW_ITEM_TYPE_GRE: last_item = MLX5_FLOW_LAYER_GRE; break; @@ -4736,6 +4740,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev, case RTE_FLOW_ITEM_TYPE_ICMP: case RTE_FLOW_ITEM_TYPE_ICMP6: case RTE_FLOW_ITEM_TYPE_CONNTRACK: + case RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT: break; case RTE_FLOW_ITEM_TYPE_INTEGRITY: /* @@ -4864,7 +4869,7 @@ flow_hw_pattern_template_create(struct rte_eth_dev *dev, "cannot create match template"); return NULL; } - it->item_flags = flow_hw_rss_item_flags_get(tmpl_items); + it->item_flags = flow_hw_matching_item_flags_get(tmpl_items); if (copied_items) { if (attr->ingress) it->implicit_port = true; @@ -4872,6 +4877,17 @@ flow_hw_pattern_template_create(struct rte_eth_dev *dev, it->implicit_tag = true; mlx5_free(copied_items); } + /* Either inner or outer, can't both. */ + if (it->item_flags & (MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT | + MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT)) { + if (((it->item_flags & MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT) && + (it->item_flags & MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT)) || + (mlx5_alloc_srh_flex_parser(dev))) { + claim_zero(mlx5dr_match_template_destroy(it->mt)); + mlx5_free(it); + return NULL; + } + } __atomic_fetch_add(&it->refcnt, 1, __ATOMIC_RELAXED); LIST_INSERT_HEAD(&priv->flow_hw_itt, it, next); return it; @@ -4903,6 +4919,9 @@ flow_hw_pattern_template_destroy(struct rte_eth_dev *dev __rte_unused, NULL, "item template in using"); } + if (template->item_flags & (MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT | + MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT)) + mlx5_free_srh_flex_parser(dev); LIST_REMOVE(template, next); claim_zero(mlx5dr_match_template_destroy(template->mt)); mlx5_free(template); From patchwork Thu Feb 2 10:11:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rongwei Liu X-Patchwork-Id: 122918 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9780541BAB; Thu, 2 Feb 2023 11:12:30 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9B44742D88; Thu, 2 Feb 2023 11:12:10 +0100 (CET) Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2066.outbound.protection.outlook.com [40.107.100.66]) by mails.dpdk.org (Postfix) with ESMTP id 8AD2642D88 for ; Thu, 2 Feb 2023 11:12:08 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=HggSjdLMZ1iTufnLscuveKs6dDqJaI1Q2SCe1fwH1aYnf4Eue56MmgU3UqoLDlR+37X9dlD66ZK3YTLCBKwhV5ELHk9E/VkncF21HGzVluz42A1igSQOl849nLzD32JYV2YAReVoyF/gpfyfaDZXiYSCUlfzd1gaeCmMpn2phML92l9nFmfFg10Gy0eSvbu2r6No6+/rVECuvGZRTAgF79iN81vsa+5LwbxRnZLf1I6l2kzodKmAKJKAIi80wo1kN5gKopsM1KMnZ2RKCN1+6M6lz+8r8JCqJ1+iknDeOJdC9QbZP5O4nISE50qa5CfSSx8c552I8mtWsn98fY/gRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=r5/O4INVBlyP2seB/MAgUA6VMEqRZWCGww/EmBCK1Lo=; b=lvGR7yM/FQoTIz3AQXM09+DtD7/npfSQa/i6I/DWiU7g+Kb+U0zEcPwfTzm2H4wc+3NzfcPfhk/W0P2LjkjPA78JYZlUv06Z+5jT9r9uOsKQ7hPGPa0eVdc+5ZHLIDqUO5NMl9GYhHHGbwGDtW2nP0EMHKevabQOetmo4Fv5C7AUzKOGIVlIppME5bZDniPz9b+hki4z0Bijbi5ubG+0JBTLYmsUZ3GKcOll8JbVR+iC4V1zcxIFpmJaj4QgW2Ch2DVWIxwtWtNOpEON/bMOa7Uu6+0c2ryz7ARxMfwSRkOOyBdWwx3Vr6le0IkN7wNdGqgGralPxJzlXrY7RH/GGw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=r5/O4INVBlyP2seB/MAgUA6VMEqRZWCGww/EmBCK1Lo=; b=bCLZmUo6Ky7I+dOLRYfraiTEbsenbJyLNA+RPg2IOP/39ublPq7r5jWmkndkoUkgdOZkB2g/MWmWpgPXvmEkucbhiqGLWBe2oI8MpRSZuPYGayMWWgmMVfXQe+3kwEny8T5O/LzCVCxxYe2iVXOJSArTRA98tuQn/ybda5x9IN4wBGVenI2OKHRlHDyieMw117xqOkQEUmdsa663YxVvbXloUOWfX9u0+2mQ0iwZsjSUmJ2849RWyDFm+2ZBVdLYBXmwwjSLACHcQ6TcMwk8/Wl7AtfUcz41LafDGSdn/Wjl1v7t3IKJWXrskSvAHoaZMMAjhfX7bfn2YvxR0KbkRw== Received: from BN8PR16CA0021.namprd16.prod.outlook.com (2603:10b6:408:4c::34) by DM6PR12MB4340.namprd12.prod.outlook.com (2603:10b6:5:2a8::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6064.24; Thu, 2 Feb 2023 10:12:07 +0000 Received: from BN8NAM11FT052.eop-nam11.prod.protection.outlook.com (2603:10b6:408:4c:cafe::62) by BN8PR16CA0021.outlook.office365.com (2603:10b6:408:4c::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6064.27 via Frontend Transport; Thu, 2 Feb 2023 10:12:06 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BN8NAM11FT052.mail.protection.outlook.com (10.13.177.210) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6064.27 via Frontend Transport; Thu, 2 Feb 2023 10:12:06 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Thu, 2 Feb 2023 02:11:53 -0800 Received: from nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Thu, 2 Feb 2023 02:11:51 -0800 From: Rongwei Liu To: , , , , CC: Subject: [PATCH v1 4/5] net/mlx5: add modify IPv6 protocol implementation Date: Thu, 2 Feb 2023 12:11:27 +0200 Message-ID: <20230202101128.2446928-5-rongweil@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230202101128.2446928-1-rongweil@nvidia.com> References: <20230202101128.2446928-1-rongweil@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT052:EE_|DM6PR12MB4340:EE_ X-MS-Office365-Filtering-Correlation-Id: 37e4f1e9-f1d9-491b-0734-08db0505f058 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LLHCcnRbcaWBWWUHeSFBp8lMxu5mVgWW+b1yXdFb+lLEtva/rTi49UMtMnG8jq1WOyIpF7V91ck8n9Vf4vXO8PlEo2qJWcqhUijPb8nXvaQMrIiq5KEUpYydFefOveWkeGX/TAy7XdQf2tUqw1aCFIFVjAsjywNlrCupZc/kU8sBlecCsU8oK1hYGC2pQTl5paCFEjrkIDhNYOE8SHB8rQIDiJy1y5O3q+eDTIk6OK8PJmQz0BjZYnpg8UinDF2P/oja93oKsKRcYnzmNoOyjFeVtjwL0qDiCcCD8i/DprUBWyAiUOSt72mkxSgQx5TlXZq6eMbzRLMuiUngsSlupbI28lRRZDcBXw3VwRfQyhXyzZE7rnJ/wkK+jhX7l6SK/TBycTIT9j8xXJb8FpkFf30H0pQ0GhT5lIrFG3340FK2H6BITmF8gnoIYB8m6tfIDDjn3vzG64G7QlPnQhKCQkCCUnMPBJvjPkzk7MM498KM8FXPsxIiFjB0zQ4iRs/b2Xig0S7/RLTJMdmWGqIhELJ+wuq0GfEJ2lusZkWZcCn8I73g9WgSuYIDydmdevy+mKVV4QFoDRSb98CbBzxaW/kfSimGHy+ZOTo+Dek+Js/99qun0iBtP46ph7JIKrUm0V/3UBbC4pVIEoQZL72bRhBRI1eQDWU3ajLJZz8nhDVL1K36FQFcEjYHtYBIKJSvdCSuz6QaEKienhn0jbpBgQ== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230025)(4636009)(396003)(346002)(376002)(39860400002)(136003)(451199018)(36840700001)(46966006)(40470700004)(41300700001)(8936002)(8676002)(70206006)(478600001)(86362001)(70586007)(4326008)(7696005)(316002)(7636003)(36756003)(110136005)(55016003)(40460700003)(36860700001)(1076003)(40480700001)(107886003)(6666004)(5660300002)(2906002)(82310400005)(26005)(16526019)(82740400003)(2616005)(186003)(426003)(83380400001)(336012)(6286002)(47076005)(356005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2023 10:12:06.6302 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 37e4f1e9-f1d9-491b-0734-08db0505f058 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT052.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4340 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add HWS modify IPv6 protocol implementation. Signed-off-by: Rongwei Liu Acked-by: Viacheslav Ovsiienko --- drivers/common/mlx5/mlx5_prm.h | 1 + drivers/net/mlx5/mlx5_flow_dv.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index b32dc735a1..7667874152 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -760,6 +760,7 @@ enum mlx5_modification_field { MLX5_MODI_TUNNEL_HDR_DW_1 = 0x75, MLX5_MODI_GTPU_FIRST_EXT_DW_0 = 0x76, MLX5_MODI_HASH_RESULT = 0x81, + MLX5_MODI_OUT_IPV6_NEXT_HDR = 0x4A, }; /* Total number of metadata reg_c's. */ diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 7ca909999b..e972a2dc5a 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -1357,6 +1357,7 @@ mlx5_flow_item_field_width(struct rte_eth_dev *dev, case RTE_FLOW_FIELD_IPV6_DSCP: return 6; case RTE_FLOW_FIELD_IPV6_HOPLIMIT: + case RTE_FLOW_FIELD_IPV6_PROTO: return 8; case RTE_FLOW_FIELD_IPV6_SRC: case RTE_FLOW_FIELD_IPV6_DST: @@ -1883,6 +1884,15 @@ mlx5_flow_field_id_to_modify_info info[idx].offset = data->offset; } break; + case RTE_FLOW_FIELD_IPV6_PROTO: + MLX5_ASSERT(data->offset + width <= 8); + off_be = 8 - (data->offset + width); + info[idx] = (struct field_modify_info){1, 0, MLX5_MODI_OUT_IPV6_NEXT_HDR}; + if (mask) + mask[idx] = flow_modify_info_mask_8(width, off_be); + else + info[idx].offset = off_be; + break; case RTE_FLOW_FIELD_POINTER: case RTE_FLOW_FIELD_VALUE: default: From patchwork Thu Feb 2 10:11:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rongwei Liu X-Patchwork-Id: 122919 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 42BC041BAB; Thu, 2 Feb 2023 11:12:40 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 95DC042D9E; Thu, 2 Feb 2023 11:12:16 +0100 (CET) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2067.outbound.protection.outlook.com [40.107.94.67]) by mails.dpdk.org (Postfix) with ESMTP id 1688142D9E for ; Thu, 2 Feb 2023 11:12:15 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=WaNdZW4He0CKFV9W5iboLNLX9NJu27B6nHCX9QjRyBJ5JurkedxHXF5vyKFP+RPTLxk5oIZKF58knkNHFdD+7wku0fL3YUlMPSEcsbolg4baalzZNMB3pi+HIj2x2eDz51vkjSk8l6Rigze+wgoCKdsCG+G/ST8EYw0xK8KJvLmAbIMZRlfZhgXIk2U1iAfEAYmjgUmTprT1cQvXSRjiNLSaLeDOeMTSYNvftTF7x3SUUfXs61M6tbqNI0AmSZbl+FSg4c+GKEQdLTEaxOGo6ZF+Z2z/J1Iq7p0VfpFWJGARnhkw4naZA8yiUA21GXDyKB1K3peAAfVjBzuUdyqPUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=yPaZzzjFEggM2c9sg94zrPQ94wlwCwUKa35ZIiRH/hs=; b=bDOdEDoD61rwswwv4XI2vuR2FAO4ap/ETYe9weGAjCFhm7Efcp29qkxVotcTUVuP+pIgCajNqV08JRPX74YOMLbVyHi2ArldFDCVCvB1BBZ2y/b+usKQxeCdZ7R+QA1itSEvSQcmHnLTpLz1kaDU8p08D+Z5mUzA2wypnOrYZt5AdN7ki++z/6NgIBJ3zwstN0C3hdT0r7vO4HgFaWfdb0f+NwyyPdW7V/BDhEdMZf9PKQbEPdEWvdXAOT+VNb/exJXiAtp4A7JbstDYgKVHrZdO+ACDSFjIqRunPJ2l3pscGY/npPIV3uGRfAA+YJt9JWflcREGMr0HOsU/swZz1A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=yPaZzzjFEggM2c9sg94zrPQ94wlwCwUKa35ZIiRH/hs=; b=tEX9DA9fAbR209xv2Wmjcfx3Z8eQD2KbIpCWfgoF5tJyaceKWREXlCxUrxMzhV4wIdDDweL0mIg4NytGCySMwQNx4ewAi3bRaH9Q5pdlz6+ZWQjeKHv1dAxTGfiJZ0TqydUzB0ktfdNn7GEswQIAvbHrcJHlrWxOPBEIm6iVt0GR1L40SslCajD6doDV1LtzMMqp8KvnTCNCHmV1v3yMa51lJkYZwcVY+6D4LdWxMaUx2G1d6xMLHJOE9NNuMrEtmfTMZoxiJoxBX97sqA5H94Lc2DvAWc4AX1+cD3Ia5g9fgjXVCKre3NezpvVCTYmqTjnyg0/zFID4RftwMSBBTw== Received: from DM6PR02CA0143.namprd02.prod.outlook.com (2603:10b6:5:332::10) by CY5PR12MB6251.namprd12.prod.outlook.com (2603:10b6:930:21::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6064.27; Thu, 2 Feb 2023 10:12:13 +0000 Received: from DM6NAM11FT108.eop-nam11.prod.protection.outlook.com (2603:10b6:5:332:cafe::1f) by DM6PR02CA0143.outlook.office365.com (2603:10b6:5:332::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6064.25 via Frontend Transport; Thu, 2 Feb 2023 10:12:13 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DM6NAM11FT108.mail.protection.outlook.com (10.13.172.95) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6064.27 via Frontend Transport; Thu, 2 Feb 2023 10:12:13 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Thu, 2 Feb 2023 02:11:55 -0800 Received: from nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Thu, 2 Feb 2023 02:11:53 -0800 From: Rongwei Liu To: , , , , CC: , Ferruh Yigit Subject: [PATCH v1 5/5] doc/mlx5: add IPv6 routing extension matching docs Date: Thu, 2 Feb 2023 12:11:28 +0200 Message-ID: <20230202101128.2446928-6-rongweil@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230202101128.2446928-1-rongweil@nvidia.com> References: <20230202101128.2446928-1-rongweil@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT108:EE_|CY5PR12MB6251:EE_ X-MS-Office365-Filtering-Correlation-Id: 66abdbca-342e-4b31-37aa-08db0505f42c X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: F2MdUEtzZIuHz4L4nX3IcfOy5FioXVj7twdg6mC3Z6rygvbbLoz41luxmZpHJ8jsXnIBdqsofo+x8BtENi5QI3gqv/RR5Ofnl6QZQdQpRlLT0iJoAkMKM94dHpWZpTt71vaCYaIA1protf143QCFFfKB9uUN50c7lRuNN0D4m67AdxA+0uHtFQjXF0GOppeuZBCG7rCxNOaMTokOEI7MJhf7LGtB7V39ojAQrm+++as1/fzqife0YkMvEmQ7xcYgpN/ZbnKxKujiMs6aQ1NHEW4kWfxhJ+RiPsd0T6Zer6a1ZgBcVChpo0jukp4/fXzf6ToU6xDY9MulhO0UpZrx7vxbRYl64VjqyOFmDQbeK8n7gjW2BsUkuz8537N/HnJlYFH+Evo3v7BGge3NANMGTiJtuHfxoQv2cHru60VpKcqPIyQBmvUEr2iwNtSAkmM7HOHLctYywV/KRgdNirnVP2selIo6TJOx6yVDi/qAfEmDfr8zEgaXXQOO5tdDg345tzqPG0yFShzIZmzVgvgl5Db2Eyj9JPPQx0si4k2G2Dc6rqp371XgJHSPnwOpjQEWknXIGTZDTyaf6m8ZrIl06MJggaISG4Mun5lhrL6jPGleOR4deBRIFFWU9SsGVJGSs5B1Sj4wADLPyxp56sJNCoiE3k4565zxebLY/YrZ0X8/ke9rsAbiYAAFQOAyrU9SNK37QHlcHnJNZvbWa0ASrw== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230025)(4636009)(39860400002)(346002)(396003)(376002)(136003)(451199018)(46966006)(36840700001)(40470700004)(356005)(55016003)(40480700001)(40460700003)(186003)(16526019)(6286002)(2616005)(1076003)(26005)(36756003)(47076005)(336012)(83380400001)(426003)(6666004)(70586007)(70206006)(8676002)(4326008)(54906003)(2906002)(110136005)(5660300002)(316002)(41300700001)(8936002)(7696005)(478600001)(82740400003)(82310400005)(7636003)(36860700001)(86362001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2023 10:12:13.1164 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 66abdbca-342e-4b31-37aa-08db0505f42c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT108.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6251 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Update mlx5 related document on IPv6 routing extension header matching. Signed-off-by: Rongwei Liu Acked-by: Viacheslav Ovsiienko --- doc/guides/nics/features/default.ini | 1 + doc/guides/nics/features/mlx5.ini | 1 + doc/guides/nics/mlx5.rst | 2 ++ 3 files changed, 4 insertions(+) diff --git a/doc/guides/nics/features/default.ini b/doc/guides/nics/features/default.ini index 510cc6679d..3d0744a243 100644 --- a/doc/guides/nics/features/default.ini +++ b/doc/guides/nics/features/default.ini @@ -141,6 +141,7 @@ udp = vlan = vxlan = vxlan_gpe = +ipv6_routing_ext = [rte_flow actions] age = diff --git a/doc/guides/nics/features/mlx5.ini b/doc/guides/nics/features/mlx5.ini index 62fd330e2b..bd911a467b 100644 --- a/doc/guides/nics/features/mlx5.ini +++ b/doc/guides/nics/features/mlx5.ini @@ -87,6 +87,7 @@ vlan = Y vxlan = Y vxlan_gpe = Y represented_port = Y +ipv6_routing_ext = Y [rte_flow actions] age = I diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index f137f156f9..966f1bd83f 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -106,6 +106,7 @@ Features - Sub-Function representors. - Sub-Function. - Matching on represented port. +- Matching on IPv6 routing extension header. Limitations @@ -174,6 +175,7 @@ Limitations - ``-EAGAIN`` for ``rte_eth_dev_start()``. - ``-EBUSY`` for ``rte_eth_dev_stop()``. + - Matching on ICMP6 following IPv6 routing extension header, should match ipv6_routing_ext_next_hdr instead of ICMP6. - When using Verbs flow engine (``dv_flow_en`` = 0), flow pattern without any specific VLAN will match for VLAN packets as well: