From patchwork Thu Feb 2 09:21:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 122894 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CF4A641BAB; Thu, 2 Feb 2023 10:25:45 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 37F3A42D5A; Thu, 2 Feb 2023 10:25:45 +0100 (CET) Received: from smtpbgau2.qq.com (smtpbgau2.qq.com [54.206.34.216]) by mails.dpdk.org (Postfix) with ESMTP id E64A542D53; Thu, 2 Feb 2023 10:25:41 +0100 (CET) X-QQ-mid: bizesmtp85t1675329938tqc1pwi2 Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 02 Feb 2023 17:25:36 +0800 (CST) X-QQ-SSF: 01400000002000H0Y000B00A0000000 X-QQ-FEAT: PCNBVolVbio1Y+o2b1ynF1owbThVMrDF4dNi5HmlX0FpCuJyVo3a7Lp8MQsr9 /08GX6eOCymvmRCCpt5DtcLgQvp4sMxVuSpbAoZoVsn0mZYpZ1iT1hwTzTxXN7Ccyl4iQ7K 3exYj95it6z9I+gzWSmMyEKAFriWwRcp/Wm9etpC+r0ueXDo/ZXRFs8m4Cc/P5xtsE59JZC D0c73cQ5gtw1PZDzt1tY81v6EssuFBqF3topvxUEZiqzoNjKcjERroFB8ddhRT4vGHpzA9q eu/gQY13LjZUMEYM+foYnKSd+Q8/Ahg9Zn0ciUHZcCCM0NhA5kfOlTul3XGAs0osOQtnR+B cN0RKuzRF63X+O+/A1zHNEdHEhS3DVUH4xW8SMMcbUegnbS6zqlAqtzzKHnTxwUN0eDgh7b aYsWePzaXZA= X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Subject: [PATCH v2 01/10] net/ngbe: fix Rx buffer size in configure register Date: Thu, 2 Feb 2023 17:21:23 +0800 Message-Id: <20230202092132.3271910-2-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230202092132.3271910-1-jiawenwu@trustnetic.com> References: <20230118060039.3074016-1-jiawenwu@trustnetic.com> <20230202092132.3271910-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybglogicsvr:qybglogicsvr5 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When buffer size is less than 1K, round down makes it 0, which is an error value. Fixes: 62fc35e63d0e ("net/ngbe: support Rx queue start/stop") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/ngbe/ngbe_rxtx.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/ngbe/ngbe_rxtx.c b/drivers/net/ngbe/ngbe_rxtx.c index 9fd24fa444..9a646cb6a7 100644 --- a/drivers/net/ngbe/ngbe_rxtx.c +++ b/drivers/net/ngbe/ngbe_rxtx.c @@ -2944,7 +2944,10 @@ ngbe_dev_rx_init(struct rte_eth_dev *dev) */ buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) - RTE_PKTMBUF_HEADROOM); - buf_size = ROUND_DOWN(buf_size, 0x1 << 10); + if (buf_size < 1024) + buf_size = ROUND_UP(buf_size, 0x1 << 10); + else + buf_size = ROUND_DOWN(buf_size, 0x1 << 10); srrctl |= NGBE_RXCFG_PKTLEN(buf_size); wr32(hw, NGBE_RXCFG(rxq->reg_idx), srrctl); From patchwork Thu Feb 2 09:21:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 122895 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9938C41BAB; Thu, 2 Feb 2023 10:25:51 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 708DD42D67; Thu, 2 Feb 2023 10:25:49 +0100 (CET) Received: from smtpbgbr2.qq.com (smtpbgbr2.qq.com [54.207.22.56]) by mails.dpdk.org (Postfix) with ESMTP id D26C242D5E; Thu, 2 Feb 2023 10:25:45 +0100 (CET) X-QQ-mid: bizesmtp85t1675329941t0a3m7ha Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 02 Feb 2023 17:25:39 +0800 (CST) X-QQ-SSF: 01400000002000H0Y000B00A0000000 X-QQ-FEAT: V0qnkXF7A2hkAVXTunqMkYyGxxyCu7C2go5c92fw2/4+2xdw2osIeNyeX6rCC YTvmhh4NuKBO834o3GPthPvSGRG7EHb4QDbu6MtT4Y/26YQvhcx2yVBxaCkaMjSR4fokg3K D+qZ54m42hkEPVpXXWT6Se5V4/TLEAWCA6O5bN5NIXFr9NsbThbzgv/eOrAswMHbfDylXZS b5ChdKQT3LMJ4Tp0qrHA0uDuXU8AwCEHwSq7kJdIWyaBk/6rT2icssc1f2mhXyxP2n//27o X5F4aK8tX8ufArZJ4pKyV03trK2gZdJ1jBLpStVJr7/qc/hu7z2QCm+AxOVhLqXtmaLOrN3 4x2UAXigNNWMGkuuFrmS/0eBBW4d5kpvp4cQGI8PVBrIR+ISF/0GJahaOSgT45S+rQQ98Za OFqBItpF7udY/VBSmnkVIA== X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Subject: [PATCH v2 02/10] net/txgbe: fix Rx buffer size in configure register Date: Thu, 2 Feb 2023 17:21:24 +0800 Message-Id: <20230202092132.3271910-3-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230202092132.3271910-1-jiawenwu@trustnetic.com> References: <20230118060039.3074016-1-jiawenwu@trustnetic.com> <20230202092132.3271910-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybglogicsvr:qybglogicsvr5 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When round up buffer size to 1K, to configure the register, hardware will receive packets exceeding the buffer size in LRO mode. It will cause a segment fault in the receive function. Fixes: be797cbf4582 ("net/txgbe: add Rx and Tx init") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/txgbe/txgbe_rxtx.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/txgbe/txgbe_rxtx.c b/drivers/net/txgbe/txgbe_rxtx.c index ac1bba08a3..328406908d 100644 --- a/drivers/net/txgbe/txgbe_rxtx.c +++ b/drivers/net/txgbe/txgbe_rxtx.c @@ -4382,7 +4382,10 @@ txgbe_dev_rx_init(struct rte_eth_dev *dev) */ buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) - RTE_PKTMBUF_HEADROOM); - buf_size = ROUND_UP(buf_size, 0x1 << 10); + if (buf_size < 1024) + buf_size = ROUND_UP(buf_size, 0x1 << 10); + else + buf_size = ROUND_DOWN(buf_size, 0x1 << 10); srrctl |= TXGBE_RXCFG_PKTLEN(buf_size); wr32(hw, TXGBE_RXCFG(rxq->reg_idx), srrctl); From patchwork Thu Feb 2 09:21:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 122897 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E3F1141BAB; Thu, 2 Feb 2023 10:26:03 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C397842D7E; Thu, 2 Feb 2023 10:25:53 +0100 (CET) Received: from smtpbgbr1.qq.com (smtpbgbr1.qq.com [54.207.19.206]) by mails.dpdk.org (Postfix) with ESMTP id A68E242D40; Thu, 2 Feb 2023 10:25:48 +0100 (CET) X-QQ-mid: bizesmtp85t1675329944t602ml4e Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 02 Feb 2023 17:25:42 +0800 (CST) X-QQ-SSF: 01400000002000H0Y000B00A0000000 X-QQ-FEAT: cBa71F6Ap8QKFQG6nmuJE2Jfdd7B5Lko+6EXdV4z1EZKz40h0ARP46nmzAOUI J4b6DdACAnFknpH5vOdc0CHz7DVrH3FHRtTG+Mk5divU3GqUp1nqbwC9gUABX0PB8QoAslV ek0Chck1uYNyt21wy4fxs7isOm5FiKwLdMwpqwxolULtvpeCJnjNrhioe9RvuELMSjchdgD 3p8mPhoCeMF+EMv1BJ3sMEJk+4bxZieb22PB0sG+O6pop81x1IqS7puah3C1F4jOwgpPloy ZqzBEzUUQA0VKvT4/Oiq7hUeGc4DgnvmSVVwRLGd9529grBveWLuAIHIplt5gV3+k+XokrC 4WRXaxFog+2aNdw7tqNoz/4jYcHelQCpiat7LQxXvmEQy5bBgvUZY4cfYjb+983cP3Sljyr 9zrvvBzsTVwGNnDmjYhyHg== X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Subject: [PATCH v2 03/10] net/txgbe: fix default signal quality value for KX/KX4 Date: Thu, 2 Feb 2023 17:21:25 +0800 Message-Id: <20230202092132.3271910-4-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230202092132.3271910-1-jiawenwu@trustnetic.com> References: <20230118060039.3074016-1-jiawenwu@trustnetic.com> <20230202092132.3271910-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybglogicsvr:qybglogicsvr5 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On old firmware versions, the default value of signal quality(TX_EQ) is configured by the driver. Fix it for KX/KX4 mode. Fixes: 01c3cf5c85a7 ("net/txgbe: add autoneg control read and write") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/txgbe/base/txgbe_phy.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c index 9f46d5bdb0..87935abdaa 100644 --- a/drivers/net/txgbe/base/txgbe_phy.c +++ b/drivers/net/txgbe/base/txgbe_phy.c @@ -1693,9 +1693,10 @@ txgbe_set_link_to_kx4(struct txgbe_hw *hw, bool autoneg) wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); } else if (hw->fw_version <= TXGBE_FW_N_TXEQ) { value = (0x1804 & ~0x3F3F); + value |= 40 << 8; wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); - value = (0x50 & ~0x7F) | 40 | (1 << 6); + value = (0x50 & ~0x7F) | (1 << 6); wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); } out: @@ -1907,10 +1908,10 @@ txgbe_set_link_to_kx(struct txgbe_hw *hw, value |= hw->phy.ffe_post | (1 << 6); wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); } else if (hw->fw_version <= TXGBE_FW_N_TXEQ) { - value = (0x1804 & ~0x3F3F) | (24 << 8) | 4; + value = (0x1804 & ~0x3F3F) | (40 << 8); wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); - value = (0x50 & ~0x7F) | 16 | (1 << 6); + value = (0x50 & ~0x7F) | (1 << 6); wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); } out: From patchwork Thu Feb 2 09:21:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 122896 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 74F3C41BAB; Thu, 2 Feb 2023 10:25:57 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8498A42D56; Thu, 2 Feb 2023 10:25:52 +0100 (CET) Received: from smtpbg151.qq.com (smtpbg151.qq.com [18.169.211.239]) by mails.dpdk.org (Postfix) with ESMTP id B255D42D59; Thu, 2 Feb 2023 10:25:49 +0100 (CET) X-QQ-mid: bizesmtp85t1675329946txmn6fua Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 02 Feb 2023 17:25:45 +0800 (CST) X-QQ-SSF: 01400000002000H0Y000B00A0000000 X-QQ-FEAT: +oIWmpEafD9keW1LoSZX9BYloMI7NuLPscTz5aHzVmub5/rKvGeLV4vl9uCFn jigv48R5M5Z53kJnbaqkQwMjZRCBEPWOsqC7/5cLencfsuEm4QyJXY20bWVAH9acx7/eRle GVXwL13inyQJTg/0TE8oqWqGPukjzuzP1oU6UQt5Y53QOs91cutZkL7P2MZot/dpL+wZOlg m2L1aneSKHuBkMdIV4hAZQ1J9NvKJvIwcFJOgSyfoM2ghl/3dsXeYZpR82N09mIV9/so12d 7j0qi761LxZAIYF/WftFpl4jgyinmjLHwGcfCZW3zwYzafRwUgbckjx3XdgfsSE4S/O9tv2 3tbfKutxbDbHEDiaS80N7GkBoH45KK5zed7USu0MT2JTjTo5GRPWMDX/60TYQE64XGTTyx7 x/KU1f/SqlnZ9eri7Wflgw== X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Subject: [PATCH v2 04/10] net/txgbe: fix packet type to parse from offload flags Date: Thu, 2 Feb 2023 17:21:26 +0800 Message-Id: <20230202092132.3271910-5-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230202092132.3271910-1-jiawenwu@trustnetic.com> References: <20230118060039.3074016-1-jiawenwu@trustnetic.com> <20230202092132.3271910-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybglogicsvr:qybglogicsvr5 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Context descriptors which contains the length of each packet layer and the packet type are needed when Tx checksum offload or TSO is on. If the packet type and length do not strictly match, it will cause Tx ring hang. In some external applications, developers may fill in wrong packet_type in rte_mbuf for Tx path. For example, they encap/decap the packets but did not refill the packet_type. To prevent this, change it to parse from ol_flags. Fixes: ca46fcd753b1 ("net/txgbe: support Tx with hardware offload") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/txgbe/txgbe_rxtx.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/net/txgbe/txgbe_rxtx.c b/drivers/net/txgbe/txgbe_rxtx.c index 328406908d..f7e3159dc9 100644 --- a/drivers/net/txgbe/txgbe_rxtx.c +++ b/drivers/net/txgbe/txgbe_rxtx.c @@ -516,20 +516,21 @@ tx_desc_ol_flags_to_cmdtype(uint64_t ol_flags) return cmdtype; } -static inline uint8_t -tx_desc_ol_flags_to_ptid(uint64_t oflags, uint32_t ptype) +static inline uint32_t +tx_desc_ol_flags_to_ptype(uint64_t oflags) { + uint32_t ptype; bool tun; - if (ptype) - return txgbe_encode_ptype(ptype); - /* Only support flags in TXGBE_TX_OFFLOAD_MASK */ tun = !!(oflags & RTE_MBUF_F_TX_TUNNEL_MASK); /* L2 level */ ptype = RTE_PTYPE_L2_ETHER; if (oflags & RTE_MBUF_F_TX_VLAN) + ptype |= (tun ? RTE_PTYPE_INNER_L2_ETHER_VLAN : RTE_PTYPE_L2_ETHER_VLAN); + + if (oflags & RTE_MBUF_F_TX_QINQ) /* tunnel + QINQ is not supported */ ptype |= RTE_PTYPE_L2_ETHER_VLAN; /* L3 level */ @@ -587,6 +588,16 @@ tx_desc_ol_flags_to_ptid(uint64_t oflags, uint32_t ptype) break; } + return ptype; +} + +static inline uint8_t +tx_desc_ol_flags_to_ptid(uint64_t oflags) +{ + uint32_t ptype; + + ptype = tx_desc_ol_flags_to_ptype(oflags); + return txgbe_encode_ptype(ptype); } @@ -776,8 +787,7 @@ txgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, /* If hardware offload required */ tx_ol_req = ol_flags & TXGBE_TX_OFFLOAD_MASK; if (tx_ol_req) { - tx_offload.ptid = tx_desc_ol_flags_to_ptid(tx_ol_req, - tx_pkt->packet_type); + tx_offload.ptid = tx_desc_ol_flags_to_ptid(tx_ol_req); if (tx_offload.ptid & TXGBE_PTID_PKT_TUN) tx_offload.ptid |= txgbe_parse_tun_ptid(tx_pkt); tx_offload.l2_len = tx_pkt->l2_len; From patchwork Thu Feb 2 09:21:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 122898 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C996041BAB; Thu, 2 Feb 2023 10:26:10 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3CE1142D8E; Thu, 2 Feb 2023 10:25:55 +0100 (CET) Received: from smtpbgjp3.qq.com (smtpbgjp3.qq.com [54.92.39.34]) by mails.dpdk.org (Postfix) with ESMTP id E564842D63; Thu, 2 Feb 2023 10:25:52 +0100 (CET) X-QQ-mid: bizesmtp85t1675329949ta6k6u4a Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 02 Feb 2023 17:25:48 +0800 (CST) X-QQ-SSF: 01400000002000H0Y000B00A0000000 X-QQ-FEAT: GWo/kaWjaZk4X/3jEvXdQsvzLVSweC9QSJm31xh/UgpG6JxP7xOquJA8HqQgp LRjDkuIPcUuxzT2nad+rbMfLp4EG519f42NcIQSKFq7BVFOEYiXLikRUhbx45yrYW8AXSFS 1Qiwd1LfDbLY12toJEjjjbLyUhqQmUlsAj3jwHy+T5b+UlIq9x66siMjfHfIq75miorIx0b 4XAJqI/zUGVauCT2+7XUXbjlxrEl93gwtm2fMDTLqilWnFXge5yyMX1C/vv8BM/myj8eK/0 xT/SbmGruf3p2ff4O50GCZuXs5X8+Fw5fmwv/Fti8nS/WbJuGskzKEPOGnIYGwXSHUc+u1L /RQLgXb+mcUEIoo7Od61RxUJUzP4Jgw1obxrt5fo2NWEvx3yu2FTio8z6+5YMjssFK7eLRv QEMHeQjUlMzaJzHmfj6CGg== X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Subject: [PATCH v2 05/10] net/ngbe: fix packet type to parse from offload flags Date: Thu, 2 Feb 2023 17:21:27 +0800 Message-Id: <20230202092132.3271910-6-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230202092132.3271910-1-jiawenwu@trustnetic.com> References: <20230118060039.3074016-1-jiawenwu@trustnetic.com> <20230202092132.3271910-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybglogicsvr:qybglogicsvr5 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Context descriptors which contains the length of each packet layer and the packet type are needed when Tx checksum offload or TSO is on. If the packet type and length do not strictly match, it will cause Tx ring hang. In some external applications, developers may fill in wrong packet_type in rte_mbuf for Tx path. For example, they encap/decap the packets but did not refill the packet_type. To prevent this, change it to parse from ol_flags. And remove redundant tunnel type since the NIC does not support it. Fixes: 9f3206140274 ("net/ngbe: support TSO") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/ngbe/ngbe_rxtx.c | 92 +++++++++--------------------------- 1 file changed, 23 insertions(+), 69 deletions(-) diff --git a/drivers/net/ngbe/ngbe_rxtx.c b/drivers/net/ngbe/ngbe_rxtx.c index 9a646cb6a7..0dce4079b5 100644 --- a/drivers/net/ngbe/ngbe_rxtx.c +++ b/drivers/net/ngbe/ngbe_rxtx.c @@ -24,15 +24,11 @@ /* Bit Mask to indicate what bits required for building Tx context */ static const u64 NGBE_TX_OFFLOAD_MASK = (RTE_MBUF_F_TX_IP_CKSUM | - RTE_MBUF_F_TX_OUTER_IPV6 | - RTE_MBUF_F_TX_OUTER_IPV4 | RTE_MBUF_F_TX_IPV6 | RTE_MBUF_F_TX_IPV4 | RTE_MBUF_F_TX_VLAN | RTE_MBUF_F_TX_L4_MASK | RTE_MBUF_F_TX_TCP_SEG | - RTE_MBUF_F_TX_TUNNEL_MASK | - RTE_MBUF_F_TX_OUTER_IP_CKSUM | NGBE_TX_IEEE1588_TMST); #define NGBE_TX_OFFLOAD_NOTSUP_MASK \ @@ -333,34 +329,15 @@ ngbe_set_xmit_ctx(struct ngbe_tx_queue *txq, } vlan_macip_lens = NGBE_TXD_IPLEN(tx_offload.l3_len >> 1); - - if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) { - tx_offload_mask.outer_tun_len |= ~0; - tx_offload_mask.outer_l2_len |= ~0; - tx_offload_mask.outer_l3_len |= ~0; - tx_offload_mask.l2_len |= ~0; - tunnel_seed = NGBE_TXD_ETUNLEN(tx_offload.outer_tun_len >> 1); - tunnel_seed |= NGBE_TXD_EIPLEN(tx_offload.outer_l3_len >> 2); - - switch (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) { - case RTE_MBUF_F_TX_TUNNEL_IPIP: - /* for non UDP / GRE tunneling, set to 0b */ - break; - default: - PMD_TX_LOG(ERR, "Tunnel type not supported"); - return; - } - vlan_macip_lens |= NGBE_TXD_MACLEN(tx_offload.outer_l2_len); - } else { - tunnel_seed = 0; - vlan_macip_lens |= NGBE_TXD_MACLEN(tx_offload.l2_len); - } + vlan_macip_lens |= NGBE_TXD_MACLEN(tx_offload.l2_len); if (ol_flags & RTE_MBUF_F_TX_VLAN) { tx_offload_mask.vlan_tci |= ~0; vlan_macip_lens |= NGBE_TXD_VLAN(tx_offload.vlan_tci); } + tunnel_seed = 0; + txq->ctx_cache[ctx_idx].flags = ol_flags; txq->ctx_cache[ctx_idx].tx_offload.data[0] = tx_offload_mask.data[0] & tx_offload.data[0]; @@ -449,16 +426,10 @@ tx_desc_ol_flags_to_cmdtype(uint64_t ol_flags) return cmdtype; } -static inline uint8_t -tx_desc_ol_flags_to_ptid(uint64_t oflags, uint32_t ptype) +static inline uint32_t +tx_desc_ol_flags_to_ptype(uint64_t oflags) { - bool tun; - - if (ptype) - return ngbe_encode_ptype(ptype); - - /* Only support flags in NGBE_TX_OFFLOAD_MASK */ - tun = !!(oflags & RTE_MBUF_F_TX_TUNNEL_MASK); + uint32_t ptype; /* L2 level */ ptype = RTE_PTYPE_L2_ETHER; @@ -466,41 +437,36 @@ tx_desc_ol_flags_to_ptid(uint64_t oflags, uint32_t ptype) ptype |= RTE_PTYPE_L2_ETHER_VLAN; /* L3 level */ - if (oflags & (RTE_MBUF_F_TX_OUTER_IPV4 | RTE_MBUF_F_TX_OUTER_IP_CKSUM)) - ptype |= RTE_PTYPE_L3_IPV4; - else if (oflags & (RTE_MBUF_F_TX_OUTER_IPV6)) - ptype |= RTE_PTYPE_L3_IPV6; - if (oflags & (RTE_MBUF_F_TX_IPV4 | RTE_MBUF_F_TX_IP_CKSUM)) - ptype |= (tun ? RTE_PTYPE_INNER_L3_IPV4 : RTE_PTYPE_L3_IPV4); + ptype |= RTE_PTYPE_L3_IPV4; else if (oflags & (RTE_MBUF_F_TX_IPV6)) - ptype |= (tun ? RTE_PTYPE_INNER_L3_IPV6 : RTE_PTYPE_L3_IPV6); + ptype |= RTE_PTYPE_L3_IPV6; /* L4 level */ switch (oflags & (RTE_MBUF_F_TX_L4_MASK)) { case RTE_MBUF_F_TX_TCP_CKSUM: - ptype |= (tun ? RTE_PTYPE_INNER_L4_TCP : RTE_PTYPE_L4_TCP); + ptype |= RTE_PTYPE_L4_TCP; break; case RTE_MBUF_F_TX_UDP_CKSUM: - ptype |= (tun ? RTE_PTYPE_INNER_L4_UDP : RTE_PTYPE_L4_UDP); + ptype |= RTE_PTYPE_L4_UDP; break; case RTE_MBUF_F_TX_SCTP_CKSUM: - ptype |= (tun ? RTE_PTYPE_INNER_L4_SCTP : RTE_PTYPE_L4_SCTP); + ptype |= RTE_PTYPE_L4_SCTP; break; } if (oflags & RTE_MBUF_F_TX_TCP_SEG) - ptype |= (tun ? RTE_PTYPE_INNER_L4_TCP : RTE_PTYPE_L4_TCP); - - /* Tunnel */ - switch (oflags & RTE_MBUF_F_TX_TUNNEL_MASK) { - case RTE_MBUF_F_TX_TUNNEL_IPIP: - case RTE_MBUF_F_TX_TUNNEL_IP: - ptype |= RTE_PTYPE_L2_ETHER | - RTE_PTYPE_L3_IPV4 | - RTE_PTYPE_TUNNEL_IP; - break; - } + ptype |= RTE_PTYPE_L4_TCP; + + return ptype; +} + +static inline uint8_t +tx_desc_ol_flags_to_ptid(uint64_t oflags) +{ + uint32_t ptype; + + ptype = tx_desc_ol_flags_to_ptype(oflags); return ngbe_encode_ptype(ptype); } @@ -622,16 +588,12 @@ ngbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, /* If hardware offload required */ tx_ol_req = ol_flags & NGBE_TX_OFFLOAD_MASK; if (tx_ol_req) { - tx_offload.ptid = tx_desc_ol_flags_to_ptid(tx_ol_req, - tx_pkt->packet_type); + tx_offload.ptid = tx_desc_ol_flags_to_ptid(tx_ol_req); tx_offload.l2_len = tx_pkt->l2_len; tx_offload.l3_len = tx_pkt->l3_len; tx_offload.l4_len = tx_pkt->l4_len; tx_offload.vlan_tci = tx_pkt->vlan_tci; tx_offload.tso_segsz = tx_pkt->tso_segsz; - tx_offload.outer_l2_len = tx_pkt->outer_l2_len; - tx_offload.outer_l3_len = tx_pkt->outer_l3_len; - tx_offload.outer_tun_len = 0; /* If new context need be built or reuse the exist ctx*/ ctx = what_ctx_update(txq, tx_ol_req, tx_offload); @@ -752,10 +714,6 @@ ngbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, */ pkt_len -= (tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len); - pkt_len -= - (tx_pkt->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) - ? tx_offload.outer_l2_len + - tx_offload.outer_l3_len : 0; } /* @@ -1939,12 +1897,8 @@ ngbe_get_tx_port_offloads(struct rte_eth_dev *dev) RTE_ETH_TX_OFFLOAD_UDP_CKSUM | RTE_ETH_TX_OFFLOAD_TCP_CKSUM | RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | - RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | RTE_ETH_TX_OFFLOAD_TCP_TSO | RTE_ETH_TX_OFFLOAD_UDP_TSO | - RTE_ETH_TX_OFFLOAD_UDP_TNL_TSO | - RTE_ETH_TX_OFFLOAD_IP_TNL_TSO | - RTE_ETH_TX_OFFLOAD_IPIP_TNL_TSO | RTE_ETH_TX_OFFLOAD_MULTI_SEGS; if (hw->is_pf) From patchwork Thu Feb 2 09:21:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 122899 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F3CC441BAB; Thu, 2 Feb 2023 10:26:16 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 72CDD42DA0; Thu, 2 Feb 2023 10:25:57 +0100 (CET) Received: from smtpbgsg1.qq.com (smtpbgsg1.qq.com [54.254.200.92]) by mails.dpdk.org (Postfix) with ESMTP id 915AE42D65; Thu, 2 Feb 2023 10:25:55 +0100 (CET) X-QQ-mid: bizesmtp85t1675329952tjbdswig Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 02 Feb 2023 17:25:51 +0800 (CST) X-QQ-SSF: 01400000002000H0Y000B00A0000000 X-QQ-FEAT: hoArX50alxEdFUrc3iWK3lc+56p6n8j9eWEDZM1jWobtBc4d4GYYyfmL4C5dc +HBLanWqtNHjYgsA29CfLGzrVn8gNR4uD4Kxl/6d7vN1YERC4uEHJ+9y4lkrO0dr/P7ha0w Ud7/62LmMBva6EhgmZqEuixNhWGBWVrexGGs3Z1cAU+uRdsCNvm7g65or1Ab9C7/MiJNwgG P64qGg+z7LNRsZos4x1BnE8FzRp7ZegeBbINu6AZQ7veRvS2VRYhQxDMMQ5xF78tXf/P57n WUo7bhR1RsP+SxaSqRXPqRgx4pHEiOUaGmIS4He+RvP4FId/IVO7Tjrxh42bs6gPn8dY2xG BsbA7Ecxh6yRlOhx1AuwiMf8A+58wFDy5QFQeIw7RpymQQR0MSIg+HaKm3Ox0PhfhAntvW5 BKkKfbyGJqGH7oXW2/i6tA== X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Subject: [PATCH v2 06/10] net/ngbe: add spinlock protection on YT PHY Date: Thu, 2 Feb 2023 17:21:28 +0800 Message-Id: <20230202092132.3271910-7-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230202092132.3271910-1-jiawenwu@trustnetic.com> References: <20230118060039.3074016-1-jiawenwu@trustnetic.com> <20230202092132.3271910-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybglogicsvr:qybglogicsvr5 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org For yt8521s/yt8531s PHY, if other registers are accessing between reads/writes of ext field registers, the value of ext filed registers will get weird for unknown reasons. So it's protected when all of ext field registers accessing. Fixes: 44e97550ca68 ("net/ngbe: identify and reset PHY") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/ngbe/base/ngbe_phy_yt.c | 36 +++++++++++++++++++++++++++++ drivers/net/ngbe/base/ngbe_type.h | 1 + 2 files changed, 37 insertions(+) diff --git a/drivers/net/ngbe/base/ngbe_phy_yt.c b/drivers/net/ngbe/base/ngbe_phy_yt.c index c88946f7c3..726d6c8ef5 100644 --- a/drivers/net/ngbe/base/ngbe_phy_yt.c +++ b/drivers/net/ngbe/base/ngbe_phy_yt.c @@ -100,11 +100,15 @@ s32 ngbe_write_phy_reg_sds_ext_yt(struct ngbe_hw *hw, s32 ngbe_init_phy_yt(struct ngbe_hw *hw) { + rte_spinlock_init(&hw->phy_lock); + + rte_spinlock_lock(&hw->phy_lock); /* close sds area register */ ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, 0, 0); /* enable interrupts */ ngbe_write_phy_reg_mdi(hw, YT_INTR, 0, YT_INTR_ENA_MASK | YT_SDS_INTR_ENA_MASK); + rte_spinlock_unlock(&hw->phy_lock); hw->phy.set_phy_power(hw, false); @@ -123,7 +127,9 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, hw->phy.autoneg_advertised = 0; /* check chip_mode first */ + rte_spinlock_lock(&hw->phy_lock); ngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &value); + rte_spinlock_unlock(&hw->phy_lock); if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(0)) { /* UTP to rgmii */ if (!hw->mac.autoneg) { @@ -146,11 +152,14 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, } /* duplex full */ value |= YT_BCR_DUPLEX | YT_BCR_RESET; + rte_spinlock_lock(&hw->phy_lock); ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value); + rte_spinlock_unlock(&hw->phy_lock); goto skip_an; } + rte_spinlock_lock(&hw->phy_lock); /*disable 100/10base-T Self-negotiation ability*/ ngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value); value &= ~(YT_ANA_100BASET_FULL | YT_ANA_100BASET_HALF | @@ -189,6 +198,7 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value); value |= YT_BCR_RESET | YT_BCR_ANE | YT_BCR_RESTART_AN; ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value); + rte_spinlock_unlock(&hw->phy_lock); skip_an: hw->phy.set_phy_power(hw, true); } else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(1)) { @@ -199,6 +209,7 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, value = YT_RGMII_CONF1_RXDELAY | YT_RGMII_CONF1_TXDELAY_FE | YT_RGMII_CONF1_TXDELAY; + rte_spinlock_lock(&hw->phy_lock); ngbe_write_phy_reg_ext_yt(hw, YT_RGMII_CONF1, 0, value); value = YT_CHIP_MODE_SEL(1) | YT_CHIP_SW_LDO_EN | @@ -225,17 +236,21 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, value = YT_BCR_RESET | YT_BCR_DUPLEX | YT_BCR_SPEED_SELECT1; hw->phy.write_reg(hw, YT_BCR, 0, value); + rte_spinlock_unlock(&hw->phy_lock); hw->phy.set_phy_power(hw, true); } else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(2)) { hw->phy.set_phy_power(hw, true); + rte_spinlock_lock(&hw->phy_lock); hw->phy.read_reg(hw, YT_SPST, 0, &value); + rte_spinlock_unlock(&hw->phy_lock); if (value & YT_SPST_LINK) { /* fiber up */ hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL; } else { /* utp up */ + rte_spinlock_lock(&hw->phy_lock); /*disable 100/10base-T Self-negotiation ability*/ ngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value); value &= ~(YT_ANA_100BASET_FULL | YT_ANA_100BASET_HALF | @@ -279,10 +294,12 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value); value |= YT_BCR_RESET; ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value); + rte_spinlock_unlock(&hw->phy_lock); } } else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(4)) { hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL; + rte_spinlock_lock(&hw->phy_lock); ngbe_read_phy_reg_ext_yt(hw, YT_RGMII_CONF1, 0, &value); value |= YT_RGMII_CONF1_MODE; ngbe_write_phy_reg_ext_yt(hw, YT_RGMII_CONF1, 0, value); @@ -297,6 +314,7 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, ngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &value); value &= ~YT_SMI_PHY_SW_RST; ngbe_write_phy_reg_ext_yt(hw, YT_CHIP, 0, value); + rte_spinlock_unlock(&hw->phy_lock); hw->phy.set_phy_power(hw, true); } else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(5)) { @@ -320,7 +338,9 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, } /* duplex full */ value |= YT_BCR_DUPLEX | YT_BCR_RESET; + rte_spinlock_lock(&hw->phy_lock); hw->phy.write_reg(hw, YT_BCR, 0, value); + rte_spinlock_unlock(&hw->phy_lock); goto skip_an_sr; } @@ -339,19 +359,23 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, /* duplex full */ value |= YT_BCR_DUPLEX | YT_BCR_RESET; + rte_spinlock_lock(&hw->phy_lock); hw->phy.write_reg(hw, YT_BCR, 0, value); /* software reset to make the above configuration take effect */ hw->phy.read_reg(hw, YT_BCR, 0, &value); value |= YT_BCR_RESET | YT_BCR_ANE | YT_BCR_RESTART_AN; hw->phy.write_reg(hw, 0x0, 0, value); + rte_spinlock_unlock(&hw->phy_lock); skip_an_sr: hw->phy.set_phy_power(hw, true); } + rte_spinlock_lock(&hw->phy_lock); ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, 0, 0); ngbe_read_phy_reg_mdi(hw, YT_INTR_STATUS, 0, &value); + rte_spinlock_unlock(&hw->phy_lock); return 0; } @@ -366,6 +390,7 @@ s32 ngbe_reset_phy_yt(struct ngbe_hw *hw) hw->phy.type != ngbe_phy_yt8521s_sfi) return NGBE_ERR_PHY_TYPE; + rte_spinlock_lock(&hw->phy_lock); /* check chip_mode first */ ngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &ctrl); if (ctrl & YT_CHIP_MODE_MASK) { @@ -395,6 +420,7 @@ s32 ngbe_reset_phy_yt(struct ngbe_hw *hw) msleep(1); } } + rte_spinlock_unlock(&hw->phy_lock); if (i == YT_PHY_RST_WAIT_PERIOD) { DEBUGOUT("PHY reset polling failed to complete."); @@ -409,7 +435,9 @@ s32 ngbe_get_phy_advertised_pause_yt(struct ngbe_hw *hw, u8 *pause_bit) u16 value; s32 status = 0; + rte_spinlock_lock(&hw->phy_lock); status = hw->phy.read_reg(hw, YT_ANA, 0, &value); + rte_spinlock_unlock(&hw->phy_lock); value &= YT_FANA_PAUSE_MASK; *pause_bit = (u8)(value >> 7); @@ -421,7 +449,9 @@ s32 ngbe_get_phy_lp_advertised_pause_yt(struct ngbe_hw *hw, u8 *pause_bit) u16 value; s32 status = 0; + rte_spinlock_lock(&hw->phy_lock); status = hw->phy.read_reg(hw, YT_LPAR, 0, &value); + rte_spinlock_unlock(&hw->phy_lock); value &= YT_FLPAR_PAUSE_MASK; *pause_bit = (u8)(value >> 7); @@ -433,10 +463,12 @@ s32 ngbe_set_phy_pause_adv_yt(struct ngbe_hw *hw, u16 pause_bit) u16 value; s32 status = 0; + rte_spinlock_lock(&hw->phy_lock); status = hw->phy.read_reg(hw, YT_ANA, 0, &value); value &= ~YT_FANA_PAUSE_MASK; value |= pause_bit; status = hw->phy.write_reg(hw, YT_ANA, 0, value); + rte_spinlock_unlock(&hw->phy_lock); return status; } @@ -453,6 +485,7 @@ s32 ngbe_check_phy_link_yt(struct ngbe_hw *hw, /* Initialize speed and link to default case */ *link_up = false; *speed = NGBE_LINK_SPEED_UNKNOWN; + rte_spinlock_lock(&hw->phy_lock); ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, 0, 0); ngbe_read_phy_reg_mdi(hw, YT_INTR_STATUS, 0, &insr); @@ -472,6 +505,7 @@ s32 ngbe_check_phy_link_yt(struct ngbe_hw *hw, *link_up = true; } + rte_spinlock_unlock(&hw->phy_lock); if (*link_up) { if (phy_speed == YT_SPST_SPEED_1000M) *speed = NGBE_LINK_SPEED_1GB_FULL; @@ -488,6 +522,7 @@ s32 ngbe_set_phy_power_yt(struct ngbe_hw *hw, bool on) { u16 value = 0; + rte_spinlock_lock(&hw->phy_lock); /* power down/up in fiber mode */ hw->phy.read_reg(hw, YT_BCR, 0, &value); if (on) @@ -504,6 +539,7 @@ s32 ngbe_set_phy_power_yt(struct ngbe_hw *hw, bool on) else value |= YT_BCR_PWDN; ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value); + rte_spinlock_unlock(&hw->phy_lock); return 0; } diff --git a/drivers/net/ngbe/base/ngbe_type.h b/drivers/net/ngbe/base/ngbe_type.h index aa5c41146c..05804eeab7 100644 --- a/drivers/net/ngbe/base/ngbe_type.h +++ b/drivers/net/ngbe/base/ngbe_type.h @@ -433,6 +433,7 @@ struct ngbe_hw { bool gpio_ctl; u32 led_conf; bool init_phy; + rte_spinlock_t phy_lock; struct { u64 rx_qp_packets; u64 tx_qp_packets; From patchwork Thu Feb 2 09:21:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 122900 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 862B441BAB; Thu, 2 Feb 2023 10:26:24 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 60F9242D8D; Thu, 2 Feb 2023 10:26:01 +0100 (CET) Received: from smtpbg150.qq.com (smtpbg150.qq.com [18.132.163.193]) by mails.dpdk.org (Postfix) with ESMTP id 5B58A42DAA for ; Thu, 2 Feb 2023 10:25:59 +0100 (CET) X-QQ-mid: bizesmtp85t1675329955thk3yobm Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 02 Feb 2023 17:25:54 +0800 (CST) X-QQ-SSF: 01400000002000H0Y000B00A0000000 X-QQ-FEAT: qcKkmz/zJhxd6HG7gtwztGt/owKjp+c4mfu4kvJlLrAY9h9mFBzN9f2+cGhSl /64LVzwUy5IV4jP4zyeZJdPIcBiCvg6eeVLcfMT0AfIPnZNWO7w+949EFC7rywqQyRf3TJh 8a1mr4lA93Z849jQw7TSKqiVIu8+pdPSoCXaaZ297QcN0tF867Se/czwi2rDg3J98MdIE/r PhDYxvfkda8aXoZ6+VPWzbpaRYrXKHqdUfWPz3a0EGLCBzJkzDtCet61rV/DuFS1rC2RIPZ ZWculAYinJmf90k70+W8YiRofDO4QE6AFEjk5nAg4nB7aGKA0pTEZgb6rwv5LWPpkfGp0TU 9mtRaCbJE3XziCCBH1ffaT8QdR+lNSjELAx9X/Z5bGgWw3KXPmfAXeDDDcpyMMHf2/6fPG1 QLQYdqtCR4I= X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu Subject: [PATCH v2 07/10] net/ngbe: add chip overheat support Date: Thu, 2 Feb 2023 17:21:29 +0800 Message-Id: <20230202092132.3271910-8-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230202092132.3271910-1-jiawenwu@trustnetic.com> References: <20230118060039.3074016-1-jiawenwu@trustnetic.com> <20230202092132.3271910-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybglogicsvr:qybglogicsvr5 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Support to handle overheat interrupt. Signed-off-by: Jiawen Wu --- doc/guides/rel_notes/release_23_03.rst | 4 ++++ drivers/net/ngbe/ngbe_ethdev.c | 32 +++++++++++++++++++++++++- drivers/net/ngbe/ngbe_ethdev.h | 1 + 3 files changed, 36 insertions(+), 1 deletion(-) diff --git a/doc/guides/rel_notes/release_23_03.rst b/doc/guides/rel_notes/release_23_03.rst index b8c5b68d6c..9c61bdbdcb 100644 --- a/doc/guides/rel_notes/release_23_03.rst +++ b/doc/guides/rel_notes/release_23_03.rst @@ -55,6 +55,10 @@ New Features Also, make sure to start the actual text at the margin. ======================================================= +* **Updated Wangxun ngbe driver.** + + * Added chip overheat detection support. + Removed Items ------------- diff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c index afdb3ad41f..c32d954769 100644 --- a/drivers/net/ngbe/ngbe_ethdev.c +++ b/drivers/net/ngbe/ngbe_ethdev.c @@ -947,7 +947,7 @@ ngbe_dev_phy_intr_setup(struct rte_eth_dev *dev) else wr32(hw, NGBE_GPIOINTPOL, NGBE_GPIOINTPOL_ACT(3)); - intr->mask_misc |= NGBE_ICRMISC_GPIO; + intr->mask_misc |= NGBE_ICRMISC_GPIO | NGBE_ICRMISC_HEAT; } /* @@ -1869,6 +1869,28 @@ ngbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) return NULL; } +static void +ngbe_dev_overheat(struct rte_eth_dev *dev) +{ + struct ngbe_hw *hw = ngbe_dev_hw(dev); + s32 temp_state; + + temp_state = hw->mac.check_overtemp(hw); + if (!temp_state) + return; + + if (temp_state == NGBE_ERR_UNDERTEMP) { + PMD_DRV_LOG(CRIT, "Network adapter has been started again, " + "since the temperature has been back to normal state."); + wr32m(hw, NGBE_PBRXCTL, NGBE_PBRXCTL_ENA, NGBE_PBRXCTL_ENA); + ngbe_dev_set_link_up(dev); + } else if (temp_state == NGBE_ERR_OVERTEMP) { + PMD_DRV_LOG(CRIT, "Network adapter has been stopped because it has over heated."); + wr32m(hw, NGBE_PBRXCTL, NGBE_PBRXCTL_ENA, 0); + ngbe_dev_set_link_down(dev); + } +} + void ngbe_dev_setup_link_alarm_handler(void *param) { @@ -2167,6 +2189,9 @@ ngbe_dev_interrupt_get_status(struct rte_eth_dev *dev) if (eicr & NGBE_ICRMISC_GPIO) intr->flags |= NGBE_FLAG_NEED_LINK_UPDATE; + if (eicr & NGBE_ICRMISC_HEAT) + intr->flags |= NGBE_FLAG_OVERHEAT; + ((u32 *)hw->isb_mem)[NGBE_ISB_MISC] = 0; return 0; @@ -2243,6 +2268,11 @@ ngbe_dev_interrupt_action(struct rte_eth_dev *dev) RTE_ETH_EVENT_INTR_LSC, NULL); } + if (intr->flags & NGBE_FLAG_OVERHEAT) { + ngbe_dev_overheat(dev); + intr->flags &= ~NGBE_FLAG_OVERHEAT; + } + PMD_DRV_LOG(DEBUG, "enable intr immediately"); ngbe_enable_intr(dev); diff --git a/drivers/net/ngbe/ngbe_ethdev.h b/drivers/net/ngbe/ngbe_ethdev.h index 8d500fd38c..330f476f6f 100644 --- a/drivers/net/ngbe/ngbe_ethdev.h +++ b/drivers/net/ngbe/ngbe_ethdev.h @@ -17,6 +17,7 @@ #define NGBE_FLAG_PHY_INTERRUPT ((uint32_t)(1 << 2)) #define NGBE_FLAG_MACSEC ((uint32_t)(1 << 3)) #define NGBE_FLAG_NEED_LINK_CONFIG ((uint32_t)(1 << 4)) +#define NGBE_FLAG_OVERHEAT ((uint32_t)(1 << 5)) #define NGBE_VFTA_SIZE 128 #define NGBE_HKEY_MAX_INDEX 10 From patchwork Thu Feb 2 09:21:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 122901 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1773841BAB; Thu, 2 Feb 2023 10:26:30 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8318C42DAD; Thu, 2 Feb 2023 10:26:03 +0100 (CET) Received: from smtpbg154.qq.com (smtpbg154.qq.com [15.184.224.54]) by mails.dpdk.org (Postfix) with ESMTP id 3A32C42D8A for ; Thu, 2 Feb 2023 10:26:00 +0100 (CET) X-QQ-mid: bizesmtp85t1675329957tc1if03f Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 02 Feb 2023 17:25:56 +0800 (CST) X-QQ-SSF: 01400000002000H0Y000B00A0000000 X-QQ-FEAT: CR3LFp2JE4nJ2ULr/3gHnScwWTD6dFAtQpgyR4UWmCla18yf+qHrCM0epa8+r YP43ti5KNgSxnxbM+bNIiURjdEiYPBVIFODNYc9zy9mwVH3Gq1tmcKVY9in/bJ1CY1tYAkP OQZRn3HXmnuEOm0Oy4KbpWsj4qvLSu2ENu1x6ic3/0NL+u+01zxzr1DD01xwnnbzpdSE5N7 O4Su1H0Y1lJEc2pHJlyIIciqImVKobmld7PWjglKtBJA/Tp5dOUYxC+CnsjyhPubzPcM5qV Z7xRize9q9tcUwtmlBhDXHWZKs+sxj+Ld3C/dDW7dD2T2y1ud6acz06S92VN5zENdsET7NP ctWvPseyXsKzdp1bQ4d4mi3Auqs3d/2N98z8aPG/NoAPegA+y0LfAVpZEhcBvrSAxTQvFrj CJQBZSdcuRTEhj45BbDoog== X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu Subject: [PATCH v2 08/10] net/txgbe: add chip overheat support Date: Thu, 2 Feb 2023 17:21:30 +0800 Message-Id: <20230202092132.3271910-9-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230202092132.3271910-1-jiawenwu@trustnetic.com> References: <20230118060039.3074016-1-jiawenwu@trustnetic.com> <20230202092132.3271910-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybglogicsvr:qybglogicsvr5 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Support to handle overheat interrupt. Signed-off-by: Jiawen Wu --- doc/guides/rel_notes/release_23_03.rst | 4 ++++ drivers/net/txgbe/base/txgbe_hw.c | 1 + drivers/net/txgbe/base/txgbe_phy.c | 22 ++++++++++++++++++ drivers/net/txgbe/base/txgbe_phy.h | 1 + drivers/net/txgbe/txgbe_ethdev.c | 31 ++++++++++++++++++++++++++ drivers/net/txgbe/txgbe_ethdev.h | 1 + 6 files changed, 60 insertions(+) diff --git a/doc/guides/rel_notes/release_23_03.rst b/doc/guides/rel_notes/release_23_03.rst index 9c61bdbdcb..e64cb2d974 100644 --- a/doc/guides/rel_notes/release_23_03.rst +++ b/doc/guides/rel_notes/release_23_03.rst @@ -59,6 +59,10 @@ New Features * Added chip overheat detection support. +* **Updated Wangxun txgbe driver.** + + * Added chip overheat detection support. + Removed Items ------------- diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c index 8966453a03..e7c9754d26 100644 --- a/drivers/net/txgbe/base/txgbe_hw.c +++ b/drivers/net/txgbe/base/txgbe_hw.c @@ -2684,6 +2684,7 @@ s32 txgbe_init_ops_pf(struct txgbe_hw *hw) phy->identify_sfp = txgbe_identify_module; phy->read_i2c_byte_unlocked = txgbe_read_i2c_byte_unlocked; phy->write_i2c_byte_unlocked = txgbe_write_i2c_byte_unlocked; + phy->check_overtemp = txgbe_check_overtemp; phy->reset = txgbe_reset_phy; /* MAC */ diff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c index 87935abdaa..f4cadcc510 100644 --- a/drivers/net/txgbe/base/txgbe_phy.c +++ b/drivers/net/txgbe/base/txgbe_phy.c @@ -1363,6 +1363,28 @@ static void txgbe_i2c_stop(struct txgbe_hw *hw) wr32(hw, TXGBE_I2CENA, 0); } +/** + * txgbe_check_overtemp - Checks if an overtemp occurred. + * @hw: pointer to hardware structure + * + * Checks if the temp alarm status was triggered due to overtemp + **/ +s32 txgbe_check_overtemp(struct txgbe_hw *hw) +{ + s32 status = 0; + u32 ts_state; + + /* Check that the temp alarm status was triggered */ + ts_state = rd32(hw, TXGBE_TS_ALARM_ST); + + if (ts_state & TXGBE_TS_ALARM_ST_DALARM) + status = TXGBE_ERR_UNDERTEMP; + else if (ts_state & TXGBE_TS_ALARM_ST_ALARM) + status = TXGBE_ERR_OVERTEMP; + + return status; +} + static void txgbe_set_sgmii_an37_ability(struct txgbe_hw *hw) { diff --git a/drivers/net/txgbe/base/txgbe_phy.h b/drivers/net/txgbe/base/txgbe_phy.h index 5093d83b97..4dfe18930c 100644 --- a/drivers/net/txgbe/base/txgbe_phy.h +++ b/drivers/net/txgbe/base/txgbe_phy.h @@ -447,6 +447,7 @@ s32 txgbe_identify_module(struct txgbe_hw *hw); s32 txgbe_identify_sfp_module(struct txgbe_hw *hw); s32 txgbe_identify_qsfp_module(struct txgbe_hw *hw); +s32 txgbe_check_overtemp(struct txgbe_hw *hw); s32 txgbe_read_i2c_byte(struct txgbe_hw *hw, u8 byte_offset, u8 dev_addr, u8 *data); s32 txgbe_read_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset, diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c index 86ef979b29..ce7cf2506d 100644 --- a/drivers/net/txgbe/txgbe_ethdev.c +++ b/drivers/net/txgbe/txgbe_ethdev.c @@ -1542,6 +1542,7 @@ txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev) wr32(hw, TXGBE_GPIOINTEN, gpie); intr->mask_misc |= TXGBE_ICRMISC_GPIO; intr->mask_misc |= TXGBE_ICRMISC_ANDONE; + intr->mask_misc |= TXGBE_ICRMISC_HEAT; } int @@ -2672,6 +2673,28 @@ txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) return NULL; } +static void +txgbe_dev_overheat(struct rte_eth_dev *dev) +{ + struct txgbe_hw *hw = TXGBE_DEV_HW(dev); + s32 temp_state; + + temp_state = hw->phy.check_overtemp(hw); + if (!temp_state) + return; + + if (temp_state == TXGBE_ERR_UNDERTEMP) { + PMD_DRV_LOG(CRIT, "Network adapter has been started again, " + "since the temperature has been back to normal state."); + wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, TXGBE_PBRXCTL_ENA); + txgbe_dev_set_link_up(dev); + } else if (temp_state == TXGBE_ERR_OVERTEMP) { + PMD_DRV_LOG(CRIT, "Network adapter has been stopped because it has over heated."); + wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, 0); + txgbe_dev_set_link_down(dev); + } +} + void txgbe_dev_setup_link_alarm_handler(void *param) { @@ -2974,6 +2997,9 @@ txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev, if (eicr & TXGBE_ICRMISC_GPIO) intr->flags |= TXGBE_FLAG_PHY_INTERRUPT; + if (eicr & TXGBE_ICRMISC_HEAT) + intr->flags |= TXGBE_FLAG_OVERHEAT; + return 0; } @@ -3086,6 +3112,11 @@ txgbe_dev_interrupt_action(struct rte_eth_dev *dev, } } + if (intr->flags & TXGBE_FLAG_OVERHEAT) { + txgbe_dev_overheat(dev); + intr->flags &= ~TXGBE_FLAG_OVERHEAT; + } + PMD_DRV_LOG(DEBUG, "enable intr immediately"); txgbe_enable_intr(dev); rte_intr_enable(intr_handle); diff --git a/drivers/net/txgbe/txgbe_ethdev.h b/drivers/net/txgbe/txgbe_ethdev.h index 6a18865e23..c59b6370bb 100644 --- a/drivers/net/txgbe/txgbe_ethdev.h +++ b/drivers/net/txgbe/txgbe_ethdev.h @@ -30,6 +30,7 @@ #define TXGBE_FLAG_MACSEC (uint32_t)(1 << 3) #define TXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4) #define TXGBE_FLAG_NEED_AN_CONFIG (uint32_t)(1 << 5) +#define TXGBE_FLAG_OVERHEAT (uint32_t)(1 << 6) /* * Defines that were not part of txgbe_type.h as they are not used by the From patchwork Thu Feb 2 09:21:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 122902 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 84B5241BAB; Thu, 2 Feb 2023 10:26:35 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E03CD42D7C; Thu, 2 Feb 2023 10:26:06 +0100 (CET) Received: from smtpbg154.qq.com (smtpbg154.qq.com [15.184.224.54]) by mails.dpdk.org (Postfix) with ESMTP id BABCD42D86; Thu, 2 Feb 2023 10:26:03 +0100 (CET) X-QQ-mid: bizesmtp85t1675329960thk8soaq Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 02 Feb 2023 17:25:59 +0800 (CST) X-QQ-SSF: 01400000002000H0Y000B00A0000000 X-QQ-FEAT: 7aHzntQn+UCy+DW3M1R5OKSiVluPHb3RaSxeMEZULzopMDlPBytZI224uZXED fWy2HTlSRPbM2ym0vduvZQWtIlELCLpMY8msoWg4USKY6FGCvDpPHnhBJOjlydniGnpkNLL 9f3u9/XPRdwpWctPpy2xedC5b8UBRsz/Aw7zKPCyTkDzUiY7JW9GOb8VI6tIzZS47EvjxP5 ef/c94D369ON+GvrUcfnEBPSJuGCuLeANZ/2jHMdzHPimKKrtUXaPFuLCYS/a5+IH7/QYIG 0ReFV32GpSLQsu5F6BpVsB+gb9RIdu4xQuQ7vJrvVsKfm3qWwKjwAiq6+IV1j4CslNFyhpq Zwvisi9J3+bIa80AN2guadim23B7P8QNA76pwgMqpqsGwk/TVafNX4XWj+M7Ua5hzHqqwTC jO21oHD9C8M= X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Subject: [PATCH v2 09/10] net/txgbe: fix interrupt loss Date: Thu, 2 Feb 2023 17:21:31 +0800 Message-Id: <20230202092132.3271910-10-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230202092132.3271910-1-jiawenwu@trustnetic.com> References: <20230118060039.3074016-1-jiawenwu@trustnetic.com> <20230202092132.3271910-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybglogicsvr:qybglogicsvr5 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Disable interrupt in the interrupt handling process will sometimes cause interrupts to be lost. Fixes: 2fc745e6b606 ("net/txgbe: add interrupt operation") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/txgbe/txgbe_ethdev.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c index ce7cf2506d..6e939b8ce3 100644 --- a/drivers/net/txgbe/txgbe_ethdev.c +++ b/drivers/net/txgbe/txgbe_ethdev.c @@ -2972,9 +2972,6 @@ txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev, rte_intr_type_get(intr_handle) != RTE_INTR_HANDLE_VFIO_MSIX) wr32(hw, TXGBE_PX_INTA, 1); - /* clear all cause mask */ - txgbe_disable_intr(hw); - /* read-on-clear nic registers here */ eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC]; PMD_DRV_LOG(DEBUG, "eicr %x", eicr); @@ -3000,6 +2997,8 @@ txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev, if (eicr & TXGBE_ICRMISC_HEAT) intr->flags |= TXGBE_FLAG_OVERHEAT; + ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC] = 0; + return 0; } From patchwork Thu Feb 2 09:21:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 122903 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2465141BAB; Thu, 2 Feb 2023 10:26:42 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7BE7242D77; Thu, 2 Feb 2023 10:26:11 +0100 (CET) Received: from smtpbgbr1.qq.com (smtpbgbr1.qq.com [54.207.19.206]) by mails.dpdk.org (Postfix) with ESMTP id B9CF642D84 for ; Thu, 2 Feb 2023 10:26:07 +0100 (CET) X-QQ-mid: bizesmtp85t1675329962t8rl9kz7 Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 02 Feb 2023 17:26:01 +0800 (CST) X-QQ-SSF: 01400000002000H0Y000B00A0000000 X-QQ-FEAT: J5JfekO1WsjKbgmvluh3i3j+iUtczQLf0RA76ftuZZlKn3wpJw+d2ruQ/6MOT e5cRkB7WKY4LAB+aLC8amkbiV3KD2XWwua2oAL6B+hcnZ4cSwnrkHXrWvg0iFjwdGQXFobZ mWCVtojIg1sQh3gLevbeLe9u9n4qiWqxyN5yqRg6XZANoGS5/7/AOeKA2eipiPCiLtSC4cP 0zzvuiNv82LILRQF/deiqL5zgri82vOqdGuJf+A27zWKfNeoaTelLgSLp7jlg4tOA748aFO AK5G+tc9wXeJnCJs5+HJY8qnga4D38lrxCzxvXc4WB86ijFDbGGPE9bVPWUmdchTEy3+DL8 gAbS7zH/8ccCGNj3VyODtcF8XJoE1ck3bycHOAnK6kAuGok2jtdGxicyVU2Tknzj/jfzDmh 06YiY0RcXNP4dyHMVn9u/A== X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu Subject: [PATCH v2 10/10] net/txgbe: add SFP hot-plug identification support Date: Thu, 2 Feb 2023 17:21:32 +0800 Message-Id: <20230202092132.3271910-11-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230202092132.3271910-1-jiawenwu@trustnetic.com> References: <20230118060039.3074016-1-jiawenwu@trustnetic.com> <20230202092132.3271910-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybglogicsvr:qybglogicsvr5 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Support to identify the new SFP/SFP+ module when the device is started. Signed-off-by: Jiawen Wu --- doc/guides/rel_notes/release_23_03.rst | 1 + drivers/net/txgbe/base/txgbe_regs.h | 1 + drivers/net/txgbe/txgbe_ethdev.c | 65 ++++++++++++++++++++++++-- 3 files changed, 63 insertions(+), 4 deletions(-) diff --git a/doc/guides/rel_notes/release_23_03.rst b/doc/guides/rel_notes/release_23_03.rst index e64cb2d974..3c43b75ac0 100644 --- a/doc/guides/rel_notes/release_23_03.rst +++ b/doc/guides/rel_notes/release_23_03.rst @@ -62,6 +62,7 @@ New Features * **Updated Wangxun txgbe driver.** * Added chip overheat detection support. + * Added SFP hot-plug identification support. Removed Items diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h index 911bb6e04e..bc2854b01a 100644 --- a/drivers/net/txgbe/base/txgbe_regs.h +++ b/drivers/net/txgbe/base/txgbe_regs.h @@ -1579,6 +1579,7 @@ enum txgbe_5tuple_protocol { #define TXGBE_GPIOINTMASK 0x014834 #define TXGBE_GPIOINTTYPE 0x014838 #define TXGBE_GPIOINTSTAT 0x014840 +#define TXGBE_GPIORAWINTSTAT 0x014844 #define TXGBE_GPIOEOI 0x01484C diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c index 6e939b8ce3..a502618bc5 100644 --- a/drivers/net/txgbe/txgbe_ethdev.c +++ b/drivers/net/txgbe/txgbe_ethdev.c @@ -114,6 +114,7 @@ static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev, static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *handle); static void txgbe_dev_interrupt_handler(void *param); +static void txgbe_dev_detect_sfp(void *param); static void txgbe_dev_interrupt_delayed_handler(void *param); static void txgbe_configure_msix(struct rte_eth_dev *dev); @@ -1535,11 +1536,20 @@ txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev) { struct txgbe_hw *hw = TXGBE_DEV_HW(dev); struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); + u8 device_type = hw->subsystem_device_id & 0xF0; uint32_t gpie; - gpie = rd32(hw, TXGBE_GPIOINTEN); - gpie |= TXGBE_GPIOBIT_6; - wr32(hw, TXGBE_GPIOINTEN, gpie); + if (device_type != TXGBE_DEV_ID_MAC_XAUI && + device_type != TXGBE_DEV_ID_MAC_SGMII) { + gpie = rd32(hw, TXGBE_GPIOINTEN); + gpie |= TXGBE_GPIOBIT_2 | TXGBE_GPIOBIT_3 | TXGBE_GPIOBIT_6; + wr32(hw, TXGBE_GPIOINTEN, gpie); + + gpie = rd32(hw, TXGBE_GPIOINTTYPE); + gpie |= TXGBE_GPIOBIT_2 | TXGBE_GPIOBIT_3 | TXGBE_GPIOBIT_6; + wr32(hw, TXGBE_GPIOINTTYPE, gpie); + } + intr->mask_misc |= TXGBE_ICRMISC_GPIO; intr->mask_misc |= TXGBE_ICRMISC_ANDONE; intr->mask_misc |= TXGBE_ICRMISC_HEAT; @@ -1648,6 +1658,7 @@ txgbe_dev_start(struct rte_eth_dev *dev) PMD_INIT_FUNC_TRACE(); /* Stop the link setup handler before resetting the HW. */ + rte_eal_alarm_cancel(txgbe_dev_detect_sfp, dev); rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev); /* disable uio/vfio intr/eventfd mapping */ @@ -1880,6 +1891,7 @@ txgbe_dev_stop(struct rte_eth_dev *dev) PMD_INIT_FUNC_TRACE(); + rte_eal_alarm_cancel(txgbe_dev_detect_sfp, dev); rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev); /* disable interrupts */ @@ -2673,6 +2685,51 @@ txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) return NULL; } +static void +txgbe_dev_detect_sfp(void *param) +{ + struct rte_eth_dev *dev = (struct rte_eth_dev *)param; + struct txgbe_hw *hw = TXGBE_DEV_HW(dev); + s32 err; + + err = hw->phy.identify_sfp(hw); + if (err == TXGBE_ERR_SFP_NOT_SUPPORTED) { + PMD_DRV_LOG(ERR, "Unsupported SFP+ module type was detected."); + } else if (err == TXGBE_ERR_SFP_NOT_PRESENT) { + PMD_DRV_LOG(INFO, "SFP not present."); + } else if (err == 0) { + hw->mac.setup_sfp(hw); + PMD_DRV_LOG(INFO, "detected SFP+: %d\n", hw->phy.sfp_type); + txgbe_dev_setup_link_alarm_handler(dev); + txgbe_dev_link_update(dev, 0); + } +} + +static void +txgbe_dev_sfp_event(struct rte_eth_dev *dev) +{ + struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); + struct txgbe_hw *hw = TXGBE_DEV_HW(dev); + u32 reg; + + wr32(hw, TXGBE_GPIOINTMASK, 0xFF); + reg = rd32(hw, TXGBE_GPIORAWINTSTAT); + if (reg & TXGBE_GPIOBIT_2) { + wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_2); + rte_eal_alarm_set(1000 * 100, txgbe_dev_detect_sfp, dev); + } + if (reg & TXGBE_GPIOBIT_3) { + wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_3); + intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE; + } + if (reg & TXGBE_GPIOBIT_6) { + wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_6); + intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE; + } + + wr32(hw, TXGBE_GPIOINTMASK, 0); +} + static void txgbe_dev_overheat(struct rte_eth_dev *dev) { @@ -3063,7 +3120,7 @@ txgbe_dev_interrupt_action(struct rte_eth_dev *dev, } if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) { - hw->phy.handle_lasi(hw); + txgbe_dev_sfp_event(dev); intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT; }