From patchwork Mon Nov 7 09:23:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arkadiusz Kusztal X-Patchwork-Id: 119524 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 06CB2A0093; Mon, 7 Nov 2022 11:32:35 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A580C40156; Mon, 7 Nov 2022 11:32:34 +0100 (CET) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id 5162440151 for ; Mon, 7 Nov 2022 11:32:33 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667817153; x=1699353153; h=from:to:cc:subject:date:message-id; bh=RATdYU2YNG0uODAk1SepyMkNfP0rqdbi6WerLFFiuiM=; b=SgytxwqBV5epOFRKCVoaD4DCFVbxNF0dt2nx24nK7aBX6M0PnxS80nK8 tkO7HZmH3avyHJ4s49yssg3+xSz7g7Vzgg521qKqUUOQYgt7pWof3bNp6 eKR67e4VV8HE7HLqA3rq8AV7V6vdsO+9u3jNrn1G/kZlPj0qnLmiJjiTE ybWXoHJwA7rePdxZet1jq6ZM6f1yZmUpaVEXyWltjq2jqndJA2CJ5XBjn ToTogRDCbP4vayn5jv2hFF17+4AIBycRrwcZwWOKQ35Ck6QCHVvYIgCd0 7zHwvzuXAUBGojPhmboNectyJ28cjA3kR4Pe7JRyJwCi3UFixR0WG0rF7 g==; X-IronPort-AV: E=McAfee;i="6500,9779,10523"; a="396677558" X-IronPort-AV: E=Sophos;i="5.96,143,1665471600"; d="scan'208";a="396677558" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2022 02:32:24 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10523"; a="725092032" X-IronPort-AV: E=Sophos;i="5.96,143,1665471600"; d="scan'208";a="725092032" Received: from silpixa00399302.ir.intel.com ([10.237.214.136]) by FMSMGA003.fm.intel.com with ESMTP; 07 Nov 2022 02:32:23 -0800 From: Arek Kusztal To: dev@dpdk.org Cc: gakhil@marvell.com, kai.ji@intel.com, Arek Kusztal Subject: [PATCH] common/qat: fix undefined initial slice Date: Mon, 7 Nov 2022 09:23:36 +0000 Message-Id: <20221107092336.45559-1-arkadiuszx.kusztal@intel.com> X-Mailer: git-send-email 2.13.6 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This commit fixes undefined initial value of slice capability. When unset it could lead to undefined read of capability due to stack frame picked values, is should therefore be set to 0. Fixes: b3cbbcdffa4f ("common/qat: read HW slice configuration") Signed-off-by: Arek Kusztal Acked-by: Kai Ji --- drivers/common/qat/qat_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c index 057ba60931..8bce2ac073 100644 --- a/drivers/common/qat/qat_device.c +++ b/drivers/common/qat/qat_device.c @@ -361,7 +361,7 @@ static int qat_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, { int sym_ret = 0, asym_ret = 0, comp_ret = 0; int num_pmds_created = 0; - uint16_t capa; + uint16_t capa = 0; struct qat_pci_device *qat_pci_dev; struct qat_dev_hw_spec_funcs *ops_hw; struct qat_dev_cmd_param qat_dev_cmd_param[] = {