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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DM6NAM11FT028.mail.protection.outlook.com (10.13.173.140) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5791.20 via Frontend Transport; Fri, 4 Nov 2022 11:50:35 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Fri, 4 Nov 2022 04:50:23 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 4 Nov 2022 04:50:21 -0700 From: Suanming Mou To: Matan Azrad , Viacheslav Ovsiienko CC: , Subject: [PATCH] net/mlx5: fix Windows flow table and queue routine Date: Fri, 4 Nov 2022 13:50:07 +0200 Message-ID: <20221104115007.14391-1-suanmingm@nvidia.com> X-Mailer: git-send-email 2.18.1 MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT028:EE_|SA0PR12MB4557:EE_ X-MS-Office365-Filtering-Correlation-Id: de68d238-b368-4be2-ba55-08dabe5ac8db X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2022 11:50:35.0961 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: de68d238-b368-4be2-ba55-08dabe5ac8db X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4557 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The macro HAVE_MLX5_HWS_SUPPORT was introduced for HWS only. And HWS was not supported on Windows. So macro HAVE_MLX5_HWS_SUPPORT should only around the code which HWS uses, but avoid including the code block shared by Linux and Windows. Fixes: 22681deead3e ("net/mlx5/hws: enable hardware steering") Signed-off-by: Suanming Mou diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index 78234b116c..3f87f83ff0 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -1813,12 +1813,14 @@ mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused) int err = 0; /* Tables are only used in DV and DR modes. */ -#ifdef HAVE_MLX5_HWS_SUPPORT +#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) struct mlx5_dev_ctx_shared *sh = priv->sh; char s[MLX5_NAME_SIZE]; +#ifdef HAVE_MLX5_HWS_SUPPORT if (priv->sh->config.dv_flow_en == 2) return mlx5_alloc_hw_group_hash_list(priv); +#endif MLX5_ASSERT(sh); snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name); sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE, diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c index 137e7dd4ac..c1305836cf 100644 --- a/drivers/net/mlx5/mlx5_devx.c +++ b/drivers/net/mlx5/mlx5_devx.c @@ -907,6 +907,7 @@ mlx5_devx_hrxq_new(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, rte_errno = errno; goto error; } +#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) #ifdef HAVE_MLX5_HWS_SUPPORT if (hrxq->hws_flags) { hrxq->action = mlx5dr_action_create_dest_tir @@ -916,6 +917,7 @@ mlx5_devx_hrxq_new(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, goto error; return 0; } +#endif if (mlx5_flow_os_create_flow_action_dest_devx_tir(hrxq->tir, &hrxq->action)) { rte_errno = errno;