From patchwork Fri Oct 7 08:04:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gerry Gribbon X-Patchwork-Id: 117547 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B45B1A0093; Fri, 7 Oct 2022 10:05:13 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5168640687; Fri, 7 Oct 2022 10:05:13 +0200 (CEST) Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2041.outbound.protection.outlook.com [40.107.100.41]) by mails.dpdk.org (Postfix) with ESMTP id 5D32940042 for ; Fri, 7 Oct 2022 10:05:12 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=VxcZwz5YPtQvzNbxZ7JTbo8Iqw5TKUkqZGYNEyCB7saEnPhmfoVSxPagS0KGMSDgzg5AkN6xGt20jF2iLk51Zj2AylkxM+Fhy0ycbdEbKARN8dblXIfBimyIwCoM/qj/Rqq7W+x0/F+nTRRyjgO32u5/jTSJhKQt7td5Vc4x6YKS25aY0mzHjJiDPFp1rjKVImRr+2E3Bmr9zZ4b5F2zjTDDCLXFH3jYcC1VJcqsBPQLrOnIf7q+mWnZAC1H033yCpUWDnYcs26kylOPXWytFd9A/WZhEd91P2MO4L/K5YhT9SqM3U1fcZIyFgEqhAHdvD7tQECdgGVdIy5lAFDWbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=hfrBLjImopPVX0qawF+jONqW82gm+6EThP3gqiEXGeI=; b=TJWyVpfPWzIL2wv2ZEFIRaoVg29jIBro8BbZJI7ASnR6qxyvU3MGFWQV/vDyAH8dAwPetERircF6xhW6pw+Rl/jw3znVQhERnc+/JdIO6DLKvoGvGDq9UqETM0wfTtFCdAN1Z5lI4vCNGKNkoFQliTMX8EmcXfpRSPiJQl35WUuwlTi4TPJ6eBFY45KdnLDxyTbpb9IcVut/r0l7F/qZwG9j/PqiadU4PR26TC6ucInJjWxOems0jAIURrvmpt/Rbj/yMCgL3+2i0YLp3bOdpIyao0pOQgu4CjFssHUzz7naB4ria+UPfkgV5H/vB0vb1J3Ygu2Tlgxax1D6GPCJ/g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hfrBLjImopPVX0qawF+jONqW82gm+6EThP3gqiEXGeI=; b=ly1a4uyrp4wOHy9XcRQ6yRACqN50Km8iYsj5AqQ3WM5Z257oFotIM9rZgDJdzl9lv5uQlVvxz+3WonMLaIkZGbwVDauZ2oGmREscyAcHppenvEAkEQBgAbXA/KTVHJ6vLzE74prCplAiLfkl4yZVnYiKFgfue/Ak6FbHf0rjz2BA89chIq0JKaPCQlgcf2bkBghd6WlLWOLy9jKdMQ8vA+4i3Kcqnm2gUxMWSFZZbJ7c1GBEeaLgh0Tl0+ec+IFSSz686v05iJJHqySvHhcT51M7SRaxrrt5U5atE4893UhQ17NE85+YocaXsZysCQfIVjUSheCY33Ecx/b+JGkQZg== Received: from BN9PR03CA0195.namprd03.prod.outlook.com (2603:10b6:408:f9::20) by DM4PR12MB5199.namprd12.prod.outlook.com (2603:10b6:5:396::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.24; Fri, 7 Oct 2022 08:05:10 +0000 Received: from BN8NAM11FT085.eop-nam11.prod.protection.outlook.com (2603:10b6:408:f9:cafe::44) by BN9PR03CA0195.outlook.office365.com (2603:10b6:408:f9::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.26 via Frontend Transport; Fri, 7 Oct 2022 08:05:10 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BN8NAM11FT085.mail.protection.outlook.com (10.13.176.100) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5709.10 via Frontend Transport; Fri, 7 Oct 2022 08:05:10 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Fri, 7 Oct 2022 01:05:01 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 7 Oct 2022 01:04:59 -0700 From: Gerry Gribbon To: CC: , , , Subject: [PATCH v2] regexdev: add maximum number of mbuf segments field Date: Fri, 7 Oct 2022 08:04:22 +0000 Message-ID: <20221007080422.280482-1-ggribbon@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220901081655.2434317-2-ggribbon@nvidia.com> References: <20220901081655.2434317-2-ggribbon@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT085:EE_|DM4PR12MB5199:EE_ X-MS-Office365-Filtering-Correlation-Id: 6837fecc-8ea4-443b-3e11-08daa83aa810 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: TWVgYJxVyWUIb+LQecgF7VlFYGVH7z7T0ZxYh0YA5a7s4VrCsWNdVhB4IrgegEE5nksgkcGDg00pnGG+0I0stz89UlEngsHRUbYO4C9ASdKKFxiz2I3KHP4AnR86jzhVp53nYJ3BS5UxwF9eabIAbSPik8VtWk29TwkFnpsrpzUW+BNzaj5VUhqmXmqt98isqQ0FOgTVsMIunl7ceLIEk0peQoPZ3b5phrKWBUoqU/YkIaK/vSZXAIzjgjW3Efg1lQB3VPGnYv870jJTS+5VHW2oPpsYblJns5UYiyY2c0scUnrRM102XqmrtxZokGUBWpkVGpolsTT7wZz4c65V7pY4Ez1NbO9ubagcO2qoBdhBx+dMRec1NE1/rsGiX6GjqQpib/fQQCCrLIOoXp4YssNnDPdKauaxXsCWHSCR0Vb3BOw7nuAFbsY+m/kop/K1wAE9Jb1b/YrruFLrFK2QnMWfHUSBS6472zw605OY7vcqrnBhcgXrcq7NqEcdEN0+OW4aZ6bVUCFNe6exkZxL0B9cDJFjp09Hj9UQpZ3T1sJaKZOo1eSGLapcrNjYtEsDPLmCiptj/P7ITn8Jp7Uc7XGE+jMx816xaJMIa246W9p0sVrXUQKNKv38VwTJY4Hfi7tD/vLVy9tvP+LxzO6/wRagyKhrvchmcLFhEdDzvsVOBHyigpCAesvbaZo/7qY3TncEZZvNf7wVNan0gRt4sg3g9Qjs/KK1aQJN0Os1txeJae8hqkM5/NCzzcNDDn+OGztUl7jGbrNhhFghSD8vvw== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(396003)(39860400002)(376002)(136003)(346002)(451199015)(36840700001)(40470700004)(46966006)(2906002)(36756003)(82310400005)(5660300002)(6862004)(41300700001)(36860700001)(86362001)(26005)(426003)(70206006)(70586007)(478600001)(47076005)(83380400001)(186003)(8936002)(8676002)(7049001)(6200100001)(82740400003)(7696005)(40460700003)(16526019)(37006003)(2616005)(1076003)(4326008)(336012)(55016003)(40480700001)(6666004)(54906003)(356005)(316002)(6286002)(7636003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2022 08:05:10.5209 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6837fecc-8ea4-443b-3e11-08daa83aa810 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT085.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5199 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Allows application to query maximum number of mbuf segments that can be chained together. Signed-off-by: Gerry Gribbon Acked-by: Ori Kam --- v2: * Moved max_num_mbuf_segs field in the sparse rte_regexdev_info struct to reuse an existing hole. * Renamed max_num_mbuf_segs to max_segs. drivers/regex/mlx5/mlx5_regex.h | 1 + drivers/regex/mlx5/mlx5_regex_fastpath.c | 43 ++++++++++++++++++++++++ drivers/regex/mlx5/mlx5_rxp.c | 1 + lib/regexdev/rte_regexdev.h | 2 ++ 4 files changed, 47 insertions(+) diff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h index 89495301ac..98fe95b781 100644 --- a/drivers/regex/mlx5/mlx5_regex.h +++ b/drivers/regex/mlx5/mlx5_regex.h @@ -94,4 +94,5 @@ uint16_t mlx5_regexdev_dequeue(struct rte_regexdev *dev, uint16_t qp_id, struct rte_regex_ops **ops, uint16_t nb_ops); uint16_t mlx5_regexdev_enqueue_gga(struct rte_regexdev *dev, uint16_t qp_id, struct rte_regex_ops **ops, uint16_t nb_ops); +uint16_t mlx5_regexdev_max_segs_get(void); #endif /* MLX5_REGEX_H */ diff --git a/drivers/regex/mlx5/mlx5_regex_fastpath.c b/drivers/regex/mlx5/mlx5_regex_fastpath.c index 0a8c83fe14..d6c747aeae 100644 --- a/drivers/regex/mlx5/mlx5_regex_fastpath.c +++ b/drivers/regex/mlx5/mlx5_regex_fastpath.c @@ -41,6 +41,39 @@ /* In WQE set mode, the pi should be quarter of the MLX5_REGEX_MAX_WQE_INDEX. */ #define MLX5_REGEX_UMR_QP_PI_IDX(pi, ops) \ (((pi) + (ops)) & (MLX5_REGEX_MAX_WQE_INDEX >> 2)) +#ifdef RTE_LIBRTE_MLX5_DEBUG +#define MLX5_REGEX_DEBUG 0 +#endif +#ifdef HAVE_MLX5_UMR_IMKEY +static uint16_t max_nb_segs = MLX5_REGEX_MAX_KLM_NUM; +#else +static uint16_t max_nb_segs = 1; +#endif + +uint16_t +mlx5_regexdev_max_segs_get(void) +{ + return max_nb_segs; +} + +#ifdef MLX5_REGEX_DEBUG +static inline uint16_t +validate_ops(struct rte_regex_ops **ops, uint16_t nb_ops) +{ + uint16_t nb_left = nb_ops; + struct rte_mbuf *mbuf; + + while (nb_left--) { + mbuf = ops[nb_left]->mbuf; + if ((mbuf->pkt_len > MLX5_RXP_MAX_JOB_LENGTH) || + (mbuf->nb_segs > max_nb_segs)) { + DRV_LOG(ERR, "Failed to validate regex ops"); + return 1; + } + } + return 0; +} +#endif static inline uint32_t qp_size_get(struct mlx5_regex_hw_qp *qp) @@ -375,6 +408,11 @@ mlx5_regexdev_enqueue_gga(struct rte_regexdev *dev, uint16_t qp_id, struct mlx5_regex_hw_qp *qp_obj; size_t hw_qpid, nb_left = nb_ops, nb_desc; +#ifdef MLX5_REGEX_DEBUG + if (validate_ops(ops, nb_ops)) + return 0; +#endif + while ((hw_qpid = ffs(queue->free_qps))) { hw_qpid--; /* ffs returns 1 for bit 0 */ qp_obj = &queue->qps[hw_qpid]; @@ -409,6 +447,11 @@ mlx5_regexdev_enqueue(struct rte_regexdev *dev, uint16_t qp_id, struct mlx5_regex_hw_qp *qp_obj; size_t hw_qpid, job_id, i = 0; +#ifdef MLX5_REGEX_DEBUG + if (validate_ops(ops, nb_ops)) + return 0; +#endif + while ((hw_qpid = ffs(queue->free_qps))) { hw_qpid--; /* ffs returns 1 for bit 0 */ qp_obj = &queue->qps[hw_qpid]; diff --git a/drivers/regex/mlx5/mlx5_rxp.c b/drivers/regex/mlx5/mlx5_rxp.c index ed3af15e40..eadc7fe603 100644 --- a/drivers/regex/mlx5/mlx5_rxp.c +++ b/drivers/regex/mlx5/mlx5_rxp.c @@ -45,6 +45,7 @@ mlx5_regex_info_get(struct rte_regexdev *dev __rte_unused, RTE_REGEXDEV_CAPA_QUEUE_PAIR_OOS_F; info->rule_flags = 0; info->max_queue_pairs = UINT16_MAX; + info->max_segs = mlx5_regexdev_max_segs_get(); return 0; } diff --git a/lib/regexdev/rte_regexdev.h b/lib/regexdev/rte_regexdev.h index 6061e648b1..9473c6bb4c 100644 --- a/lib/regexdev/rte_regexdev.h +++ b/lib/regexdev/rte_regexdev.h @@ -612,6 +612,8 @@ struct rte_regexdev_info { /**< Maximum payload size for a pattern match request or scan. * @see RTE_REGEXDEV_CFG_CROSS_BUFFER_SCAN_F */ + uint16_t max_segs; + /**< Maximum number of mbuf segments that can be chained together. */ uint32_t max_rules_per_group; /**< Maximum rules supported per group by this device. */ uint16_t max_groups;