From patchwork Mon Sep 26 23:07:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sevincer, Abdullah" X-Patchwork-Id: 116915 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 14879A00C2; Tue, 27 Sep 2022 01:07:08 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EBC2440A8A; Tue, 27 Sep 2022 01:07:07 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id 1EF7540146 for ; Tue, 27 Sep 2022 01:07:06 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1664233627; x=1695769627; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=s2nYoYZj7s5ce1RUEOB2PoIyayvgspflQT1KhjRyjqY=; b=ahbSaU12w3ULgvTGRhqHHw9qsfaGlk65ReKl4FHGGUN7lX+NwC/pEdqC SSekLMjSAangDtKDPHxAohFJtzrbhSyOjVt+MSQViu5k1JRrwDvwZoxX9 RojX1aIbI/LzmseN/96/A1v2T20F3MXsW1OqTx/KlEsRaAPQrwAZX8bl8 r0HePTQO0SyZtyXSO+fph0+sYuMbQf0EKHES5jx2sMdFej+PvAgrMzQEF x7xCJLgPRISSiLcNtmGy7d0l4JFJBNYnqAH0zXodx94qrJedxZFH/ZEfU gyP0Hdc50KUdXlklUAWc3MzlxyEk/zLOwSMaYTlngs+DOPLoTaRach+Na A==; X-IronPort-AV: E=McAfee;i="6500,9779,10482"; a="284283576" X-IronPort-AV: E=Sophos;i="5.93,347,1654585200"; d="scan'208";a="284283576" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Sep 2022 16:07:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10482"; a="710319664" X-IronPort-AV: E=Sophos;i="5.93,347,1654585200"; d="scan'208";a="710319664" Received: from txanpdk02.an.intel.com ([10.123.117.76]) by FMSMGA003.fm.intel.com with ESMTP; 26 Sep 2022 16:07:05 -0700 From: Abdullah Sevincer To: dev@dpdk.org Cc: jerinj@marvell.com, rashmi.shetty@intel.com, pravin.pathak@intel.com, mike.ximing.chen@intel.com, timothy.mcdaniel@intel.com, shivani.doneria@intel.com, tirthendu.sarkar@intel.com, Abdullah Sevincer Subject: [PATCH v1] doc: update DLB2 documentation Date: Mon, 26 Sep 2022 18:07:03 -0500 Message-Id: <20220926230703.1388093-1-abdullah.sevincer@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This commit updates the dlb2.rst eventdev guide to document a new devarg. A new devarg: "default_port_allocation" added to allow default ldb port allocation scheme. Signed-off-by: Abdullah Sevincer --- doc/guides/eventdevs/dlb2.rst | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/doc/guides/eventdevs/dlb2.rst b/doc/guides/eventdevs/dlb2.rst index 5b21f13b68..7b01d5c070 100644 --- a/doc/guides/eventdevs/dlb2.rst +++ b/doc/guides/eventdevs/dlb2.rst @@ -414,3 +414,22 @@ Note that the weight may not exceed the maximum CQ depth. --allow ea:00.0,cq_weight=all: --allow ea:00.0,cq_weight=qidA-qidB: --allow ea:00.0,cq_weight=qid: + +Default LDB Port Allocation +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +For optimal load balancing ports that map to one or more QIDs in common +should not be in numerical sequence. The port->QID mapping is application +dependent, but the driver interleaves port IDs as much as possible to +reduce the likelihood of sequential ports mapping to the same QID(s). + +Hence, DLB uses an initial allocation of Port IDs to maximize the +average distance between an ID and its immediate neighbors. (i.e.the +distance from 1 to 0 and to 2, the distance from 2 to 1 and to 3, etc.). +Initial port allocation option can be passed through devarg. If y (or Y) +inial port allocation will be used, otherwise initial port allocation +won't be used. + + .. code-block:: console + + --allow ea:00.0,default_port_allocation=