From patchwork Tue Aug 9 18:48:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 114766 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 45550A04FD; Tue, 9 Aug 2022 20:49:51 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2094C4113F; Tue, 9 Aug 2022 20:49:50 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 5547E40143 for ; Tue, 9 Aug 2022 20:49:48 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 279D5wJI016176 for ; Tue, 9 Aug 2022 11:49:47 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=pfpt0220; bh=8oOskMpE1tROBMBp0bp4r1vhrAPY39+BZen9cwUDyHw=; b=Ei3nZgTWAq5Ngqo8lO2C2y1yK++x8x1iLSi0QIgNf5B8AKTbonSV+rVRLFeV+Mg9gGhh FrqdJ3rxLi42cq7LueBZrG/PmKgU9AdNprTEEjTf30giqV/RcC7rA56cN4cQNjd7VD7r rIWHyV/VWSop/jcH0vZKh5fnlCIYerJA/nWrbTAOjxdkuZcwWbvN93wWtWRoExTsXlqJ JC0G03cv0Ter2zZj0s+sBVzW1yuqtuRSTO/VcxOltaSu3KCNzvni2pEKjZ9TbUSXpk24 V6eUwoBxkN+IcJfWVDglv5sRFGu0W/1ZRRjlYEKyPwdwMo5X+yazkK1jHRlo9yoiKPgO kg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3huds2ukpm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 09 Aug 2022 11:49:47 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 9 Aug 2022 11:49:45 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 9 Aug 2022 11:49:45 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 675493F7085; Tue, 9 Aug 2022 11:49:43 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Harman Kalra Subject: [PATCH 01/23] common/cnxk: fix part value for cn10k Date: Wed, 10 Aug 2022 00:18:45 +0530 Message-ID: <20220809184908.24030-1-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: ddld4RLa8QJJLvIVdgdGXZN7_NHIPM5N X-Proofpoint-GUID: ddld4RLa8QJJLvIVdgdGXZN7_NHIPM5N X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Harman Kalra Updating the logic for getting part and pass value for cn10k family, as device tree compatible logic does not work in VMs. Scanning all the PCI device and detect first RVU device, subsystem device file gives part no and revision file provide pass information. Fixes: 014a9e222bac ("common/cnxk: add model init and IO handling API") Signed-off-by: Harman Kalra --- Depends-on: series-23650("[v2] event/cnxk: add eth port specific PTP enable") Depends-on: series-24029("[1/4] cnxk/net: add fc check in vector event Tx path") drivers/common/cnxk/roc_model.c | 152 +++++++++++++++++++++++++++---------- drivers/common/cnxk/roc_platform.h | 3 + 2 files changed, 113 insertions(+), 42 deletions(-) diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c index a68baa6..791ffa6 100644 --- a/drivers/common/cnxk/roc_model.c +++ b/drivers/common/cnxk/roc_model.c @@ -2,6 +2,7 @@ * Copyright(C) 2021 Marvell. */ +#include #include #include @@ -40,6 +41,16 @@ struct roc_model *roc_model; #define MODEL_MINOR_SHIFT 0 #define MODEL_MINOR_MASK ((1 << MODEL_MINOR_BITS) - 1) +#define MODEL_CN10K_PART_SHIFT 8 +#define MODEL_CN10K_PASS_BITS 4 +#define MODEL_CN10K_PASS_MASK ((1 << MODEL_CN10K_PASS_BITS) - 1) +#define MODEL_CN10K_MAJOR_BITS 2 +#define MODEL_CN10K_MAJOR_SHIFT 2 +#define MODEL_CN10K_MAJOR_MASK ((1 << MODEL_CN10K_MAJOR_BITS) - 1) +#define MODEL_CN10K_MINOR_BITS 2 +#define MODEL_CN10K_MINOR_SHIFT 0 +#define MODEL_CN10K_MINOR_MASK ((1 << MODEL_CN10K_MINOR_BITS) - 1) + static const struct model_db { uint32_t impl; uint32_t part; @@ -66,55 +77,101 @@ static const struct model_db { {VENDOR_CAVIUM, PART_95xxMM, 0, 0, ROC_MODEL_CNF95xxMM_A0, "cnf95xxmm_a0"}}; -static uint32_t -cn10k_part_get(void) +/* Detect if RVU device */ +static bool +is_rvu_device(unsigned long val) { - uint32_t soc = 0x0; - char buf[BUFSIZ]; - char *ptr; - FILE *fd; - - /* Read the CPU compatible variant */ - fd = fopen("/proc/device-tree/compatible", "r"); - if (!fd) { - plt_err("Failed to open /proc/device-tree/compatible"); - goto err; - } + return (val == PCI_DEVID_CNXK_RVU_PF || val == PCI_DEVID_CNXK_RVU_VF || + val == PCI_DEVID_CNXK_RVU_AF || + val == PCI_DEVID_CNXK_RVU_AF_VF || + val == PCI_DEVID_CNXK_RVU_NPA_PF || + val == PCI_DEVID_CNXK_RVU_NPA_VF || + val == PCI_DEVID_CNXK_RVU_SSO_TIM_PF || + val == PCI_DEVID_CNXK_RVU_SSO_TIM_VF || + val == PCI_DEVID_CN10K_RVU_CPT_PF || + val == PCI_DEVID_CN10K_RVU_CPT_VF); +} - if (fgets(buf, sizeof(buf), fd) == NULL) { - plt_err("Failed to read from /proc/device-tree/compatible"); - goto fclose; - } - ptr = strchr(buf, ','); - if (!ptr) { - plt_err("Malformed 'CPU compatible': <%s>", buf); - goto fclose; - } - ptr++; - if (strcmp("cn10ka", ptr) == 0) { - soc = PART_106xx; - } else if (strcmp("cnf10ka", ptr) == 0) { - soc = PART_105xx; - } else if (strcmp("cnf10kb", ptr) == 0) { - soc = PART_105xxN; - } else if (strcmp("cn10kb", ptr) == 0) { - soc = PART_103xx; - } else { - plt_err("Unidentified 'CPU compatible': <%s>", ptr); - goto fclose; +static int +rvu_device_lookup(const char *dirname, uint32_t *part, uint32_t *pass) +{ + char filename[PATH_MAX]; + unsigned long val; + + /* Check if vendor id is cavium */ + snprintf(filename, sizeof(filename), "%s/vendor", dirname); + if (plt_sysfs_value_parse(filename, &val) < 0) + goto error; + + if (val != PCI_VENDOR_ID_CAVIUM) + goto error; + + /* Get device id */ + snprintf(filename, sizeof(filename), "%s/device", dirname); + if (plt_sysfs_value_parse(filename, &val) < 0) + goto error; + + /* Check if device ID belongs to any RVU device */ + if (!is_rvu_device(val)) + goto error; + + /* Get subsystem_device id */ + snprintf(filename, sizeof(filename), "%s/subsystem_device", dirname); + if (plt_sysfs_value_parse(filename, &val) < 0) + goto error; + + *part = val >> MODEL_CN10K_PART_SHIFT; + + /* Get revision for pass value*/ + snprintf(filename, sizeof(filename), "%s/revision", dirname); + if (plt_sysfs_value_parse(filename, &val) < 0) + goto error; + + *pass = val & MODEL_CN10K_PASS_MASK; + + return 0; +error: + return -EINVAL; +} + +/* Scans through all PCI devices, detects RVU device and returns + * subsystem_device + */ +static int +cn10k_part_pass_get(uint32_t *part, uint32_t *pass) +{ +#define SYSFS_PCI_DEVICES "/sys/bus/pci/devices" + char dirname[PATH_MAX]; + struct dirent *e; + DIR *dir; + + dir = opendir(SYSFS_PCI_DEVICES); + if (dir == NULL) { + plt_err("%s(): opendir failed: %s\n", __func__, + strerror(errno)); + return -errno; } -fclose: - fclose(fd); + while ((e = readdir(dir)) != NULL) { + if (e->d_name[0] == '.') + continue; + + snprintf(dirname, sizeof(dirname), "%s/%s", SYSFS_PCI_DEVICES, + e->d_name); + + /* Lookup for rvu device and get part pass information */ + if (!rvu_device_lookup(dirname, part, pass)) + break; + } -err: - return soc; + closedir(dir); + return 0; } static bool populate_model(struct roc_model *model, uint32_t midr) { - uint32_t impl, major, part, minor; + uint32_t impl, major, part, minor, pass; bool found = false; size_t i; @@ -124,8 +181,19 @@ populate_model(struct roc_model *model, uint32_t midr) minor = (midr >> MODEL_MINOR_SHIFT) & MODEL_MINOR_MASK; /* Update part number for cn10k from device-tree */ - if (part == SOC_PART_CN10K) - part = cn10k_part_get(); + if (part == SOC_PART_CN10K) { + if (cn10k_part_pass_get(&part, &pass)) + goto not_found; + /* + * Pass value format: + * Bits 0..1: minor pass + * Bits 3..2: major pass + */ + minor = (pass >> MODEL_CN10K_MINOR_SHIFT) & + MODEL_CN10K_MINOR_MASK; + major = (pass >> MODEL_CN10K_MAJOR_SHIFT) & + MODEL_CN10K_MAJOR_MASK; + } for (i = 0; i < PLT_DIM(model_db); i++) if (model_db[i].impl == impl && model_db[i].part == part && @@ -136,7 +204,7 @@ populate_model(struct roc_model *model, uint32_t midr) found = true; break; } - +not_found: if (!found) { model->flag = 0; strncpy(model->name, "unknown", ROC_MODEL_STR_LEN_MAX - 1); diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h index 502f243..3e7adfc 100644 --- a/drivers/common/cnxk/roc_platform.h +++ b/drivers/common/cnxk/roc_platform.h @@ -24,6 +24,8 @@ #include #include +#include "eal_filesystem.h" + #include "roc_bits.h" #if defined(__ARM_FEATURE_SVE) @@ -94,6 +96,7 @@ #define plt_pci_device rte_pci_device #define plt_pci_read_config rte_pci_read_config #define plt_pci_find_ext_capability rte_pci_find_ext_capability +#define plt_sysfs_value_parse eal_parse_sysfs_value #define plt_log2_u32 rte_log2_u32 #define plt_cpu_to_be_16 rte_cpu_to_be_16 From patchwork Tue Aug 9 18:48:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 114767 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2EFECA04FD; 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Tue, 09 Aug 2022 11:49:49 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 9 Aug 2022 11:49:48 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 9 Aug 2022 11:49:48 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 42CE63F7086; Tue, 9 Aug 2022 11:49:46 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Harman Kalra Subject: [PATCH 02/23] common/cnxk: add cn10ka A1 platform Date: Wed, 10 Aug 2022 00:18:46 +0530 Message-ID: <20220809184908.24030-2-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220809184908.24030-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: pvKghoWMXyBOWxZal3ZEkL6xF1E9QscW X-Proofpoint-GUID: pvKghoWMXyBOWxZal3ZEkL6xF1E9QscW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Harman Kalra Adding support for cn10ka A1 pass Signed-off-by: Harman Kalra --- drivers/common/cnxk/roc_model.c | 1 + drivers/common/cnxk/roc_model.h | 9 ++++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c index 791ffa6..b040bc0 100644 --- a/drivers/common/cnxk/roc_model.c +++ b/drivers/common/cnxk/roc_model.c @@ -60,6 +60,7 @@ static const struct model_db { char name[ROC_MODEL_STR_LEN_MAX]; } model_db[] = { {VENDOR_ARM, PART_106xx, 0, 0, ROC_MODEL_CN106xx_A0, "cn10ka_a0"}, + {VENDOR_ARM, PART_106xx, 0, 1, ROC_MODEL_CN106xx_A1, "cn10ka_a1"}, {VENDOR_ARM, PART_105xx, 0, 0, ROC_MODEL_CNF105xx_A0, "cnf10ka_a0"}, {VENDOR_ARM, PART_103xx, 0, 0, ROC_MODEL_CN103xx_A0, "cn10kb_a0"}, {VENDOR_ARM, PART_105xxN, 0, 0, ROC_MODEL_CNF105xxN_A0, "cnf10kb_a0"}, diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h index 37c8a47..d231d44 100644 --- a/drivers/common/cnxk/roc_model.h +++ b/drivers/common/cnxk/roc_model.h @@ -25,6 +25,7 @@ struct roc_model { #define ROC_MODEL_CNF105xx_A0 BIT_ULL(21) #define ROC_MODEL_CNF105xxN_A0 BIT_ULL(22) #define ROC_MODEL_CN103xx_A0 BIT_ULL(23) +#define ROC_MODEL_CN106xx_A1 BIT_ULL(24) /* Following flags describe platform code is running on */ #define ROC_ENV_HW BIT_ULL(61) #define ROC_ENV_EMUL BIT_ULL(62) @@ -48,7 +49,7 @@ struct roc_model { ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CNF95xxN_A1 | \ ROC_MODEL_CNF95xxN_B0) -#define ROC_MODEL_CN106xx (ROC_MODEL_CN106xx_A0) +#define ROC_MODEL_CN106xx (ROC_MODEL_CN106xx_A0 | ROC_MODEL_CN106xx_A1) #define ROC_MODEL_CNF105xx (ROC_MODEL_CNF105xx_A0) #define ROC_MODEL_CNF105xxN (ROC_MODEL_CNF105xxN_A0) #define ROC_MODEL_CN103xx (ROC_MODEL_CN103xx_A0) @@ -192,6 +193,12 @@ roc_model_is_cn10ka_a0(void) } static inline uint64_t +roc_model_is_cn10ka_a1(void) +{ + return roc_model->flag & ROC_MODEL_CN106xx_A1; +} + +static inline uint64_t roc_model_is_cnf10ka_a0(void) { return roc_model->flag & ROC_MODEL_CNF105xx_A0; From patchwork Tue Aug 9 18:48:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 114784 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 57A2AA04FD; Tue, 9 Aug 2022 20:52:00 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 42F3242BCB; Tue, 9 Aug 2022 20:52:00 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id B98D04113F for ; Tue, 9 Aug 2022 20:51:58 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 279D8BCo017014; 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Tue, 9 Aug 2022 11:49:51 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 160FE3F7085; Tue, 9 Aug 2022 11:49:48 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: , , Srujana Challa Subject: [PATCH 03/23] common/cnxk: update inbound inline IPsec config mailbox Date: Wed, 10 Aug 2022 00:18:47 +0530 Message-ID: <20220809184908.24030-3-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220809184908.24030-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: ZphHo3-QxAHnv12jzs-nV-h45Y3Wa0nj X-Proofpoint-ORIG-GUID: ZphHo3-QxAHnv12jzs-nV-h45Y3Wa0nj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Srujana Challa Updates CPT inbound inline IPsec configuration mailbox to provide opcode and CPT credit from VF. This patch also adds mailbox for reading inbound IPsec configuration. Signed-off-by: Srujana Challa --- drivers/common/cnxk/roc_cpt.c | 15 +++++++++++++++ drivers/common/cnxk/roc_cpt.h | 2 ++ drivers/common/cnxk/roc_mbox.h | 12 +++++++++--- drivers/common/cnxk/version.map | 1 + 4 files changed, 27 insertions(+), 3 deletions(-) diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index f1be6a3..d607bde 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -261,6 +261,21 @@ roc_cpt_inline_ipsec_cfg(struct dev *cpt_dev, uint8_t lf_id, } int +roc_cpt_inline_ipsec_inb_cfg_read(struct roc_cpt *roc_cpt, + struct nix_inline_ipsec_cfg *inb_cfg) +{ + struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt); + struct dev *dev = &cpt->dev; + struct msg_req *req; + + req = mbox_alloc_msg_nix_read_inline_ipsec_cfg(dev->mbox); + if (req == NULL) + return -EIO; + + return mbox_process_msg(dev->mbox, (void *)&inb_cfg); +} + +int roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt, uint16_t param1, uint16_t param2) { diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index a3a65f1..4e3a078 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -158,6 +158,8 @@ int __roc_api roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, void *cptr, int __roc_api roc_cpt_lf_ctx_reload(struct roc_cpt_lf *lf, void *cptr); int __roc_api roc_cpt_inline_ipsec_cfg(struct dev *dev, uint8_t slot, struct roc_nix *nix); +int __roc_api roc_cpt_inline_ipsec_inb_cfg_read( + struct roc_cpt *roc_cpt, struct nix_inline_ipsec_cfg *inb_cfg); int __roc_api roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt, uint16_t param1, uint16_t param2); int __roc_api roc_cpt_afs_print(struct roc_cpt *roc_cpt); diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 965c704..912de11 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -263,7 +263,9 @@ struct mbox_msghdr { nix_bp_cfg_rsp) \ M(NIX_CPT_BP_DISABLE, 0x8021, nix_cpt_bp_disable, nix_bp_cfg_req, \ msg_rsp) \ - M(NIX_RX_SW_SYNC, 0x8022, nix_rx_sw_sync, msg_req, msg_rsp) + M(NIX_RX_SW_SYNC, 0x8022, nix_rx_sw_sync, msg_req, msg_rsp) \ + M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \ + msg_req, nix_inline_ipsec_cfg) /* Messages initiated by AF (range 0xC00 - 0xDFF) */ #define MBOX_UP_CGX_MESSAGES \ @@ -1161,7 +1163,9 @@ struct nix_inline_ipsec_cfg { uint32_t __io cpt_credit; struct { uint8_t __io egrp; - uint8_t __io opcode; + uint16_t __io opcode; + uint16_t __io param1; + uint16_t __io param2; } gen_cfg; struct { uint16_t __io cpt_pf_func; @@ -1465,7 +1469,9 @@ struct cpt_rx_inline_lf_cfg_msg { uint16_t __io sso_pf_func; uint16_t __io param1; uint16_t __io param2; - uint16_t __io reserved; + uint16_t __io opcode; + uint32_t __io credit; + uint32_t __io reserved; }; enum cpt_eng_type { diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 019f531..a2d99e1 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -65,6 +65,7 @@ INTERNAL { roc_cpt_dev_init; roc_cpt_eng_grp_add; roc_cpt_inline_ipsec_cfg; + roc_cpt_inline_ipsec_inb_cfg_read; roc_cpt_inline_ipsec_inb_cfg; roc_cpt_iq_disable; roc_cpt_iq_enable; From patchwork Tue Aug 9 18:48:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 114768 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C3D42A04FD; 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Tue, 09 Aug 2022 11:49:55 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 9 Aug 2022 11:49:54 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 9 Aug 2022 11:49:53 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 198663F7086; Tue, 9 Aug 2022 11:49:51 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 04/23] net/cnxk: fix missing fc wait for outbound path in vec mode Date: Wed, 10 Aug 2022 00:18:48 +0530 Message-ID: <20220809184908.24030-4-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220809184908.24030-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: x0KwGZEgjR4F4JNMKEU4G9O3u7WsNFr3 X-Proofpoint-GUID: x0KwGZEgjR4F4JNMKEU4G9O3u7WsNFr3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fix missing fc wait for outbound path in vector mode. Currently only poll mode has it. Fixes: 358d02d20a2f ("net/cnxk: support flow control for outbound inline") Cc: ndabilpuram@marvell.com Signed-off-by: Nithin Dabilpuram --- drivers/net/cnxk/cn10k_tx.h | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h index 8056510..07c88a9 100644 --- a/drivers/net/cnxk/cn10k_tx.h +++ b/drivers/net/cnxk/cn10k_tx.h @@ -1049,9 +1049,13 @@ cn10k_nix_xmit_pkts(void *tx_queue, uint64_t *ws, struct rte_mbuf **tx_pkts, /* Submit CPT instructions if any */ if (flags & NIX_TX_OFFLOAD_SECURITY_F) { + uint16_t sec_pkts = ((c_lnum << 1) + c_loff); + /* Reduce pkts to be sent to CPT */ - burst -= ((c_lnum << 1) + c_loff); - cn10k_nix_sec_fc_wait(txq, (c_lnum << 1) + c_loff); + burst -= sec_pkts; + if (flags & NIX_TX_VWQE_F) + cn10k_nix_vwqe_wait_fc(txq, sec_pkts); + cn10k_nix_sec_fc_wait(txq, sec_pkts); cn10k_nix_sec_steorl(c_io_addr, c_lmt_id, c_lnum, c_loff, c_shft); } @@ -1199,9 +1203,13 @@ cn10k_nix_xmit_pkts_mseg(void *tx_queue, uint64_t *ws, /* Submit CPT instructions if any */ if (flags & NIX_TX_OFFLOAD_SECURITY_F) { + uint16_t sec_pkts = ((c_lnum << 1) + c_loff); + /* Reduce pkts to be sent to CPT */ - burst -= ((c_lnum << 1) + c_loff); - cn10k_nix_sec_fc_wait(txq, (c_lnum << 1) + c_loff); + burst -= sec_pkts; + if (flags & NIX_TX_VWQE_F) + cn10k_nix_vwqe_wait_fc(txq, sec_pkts); + cn10k_nix_sec_fc_wait(txq, sec_pkts); cn10k_nix_sec_steorl(c_io_addr, c_lmt_id, c_lnum, c_loff, c_shft); } @@ -2753,7 +2761,11 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, uint64_t *ws, /* Submit CPT instructions if any */ if (flags & NIX_TX_OFFLOAD_SECURITY_F) { - cn10k_nix_sec_fc_wait(txq, (c_lnum << 1) + c_loff); + uint16_t sec_pkts = (c_lnum << 1) + c_loff; + + if (flags & NIX_TX_VWQE_F) + cn10k_nix_vwqe_wait_fc(txq, sec_pkts); + cn10k_nix_sec_fc_wait(txq, sec_pkts); cn10k_nix_sec_steorl(c_io_addr, c_lmt_id, c_lnum, c_loff, c_shft); } From patchwork Tue Aug 9 18:48:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 114769 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4819CA04FD; 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Tue, 09 Aug 2022 11:49:58 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 9 Aug 2022 11:49:56 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 9 Aug 2022 11:49:56 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id A04433F7085; Tue, 9 Aug 2022 11:49:54 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 05/23] common/cnxk: limit meta aura workaround to CN10K A0 Date: Wed, 10 Aug 2022 00:18:49 +0530 Message-ID: <20220809184908.24030-5-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220809184908.24030-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: HY4KHJ-8jIzCbpNc1pjLp-2p2Z51QywO X-Proofpoint-GUID: HY4KHJ-8jIzCbpNc1pjLp-2p2Z51QywO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Limit meta aura workaround to CN10K A0. Also other NIX and Inline related Erratas applicable for CN10K A1. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_errata.h | 7 +++++++ drivers/common/cnxk/roc_nix_inl.c | 10 ++++++---- drivers/net/cnxk/cnxk_ethdev.c | 3 ++- 3 files changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/common/cnxk/roc_errata.h b/drivers/common/cnxk/roc_errata.h index f048297..8dc372f 100644 --- a/drivers/common/cnxk/roc_errata.h +++ b/drivers/common/cnxk/roc_errata.h @@ -81,6 +81,13 @@ roc_errata_nix_has_perf_issue_on_stats_update(void) static inline bool roc_errata_cpt_hang_on_x2p_bp(void) { + return roc_model_is_cn10ka_a0() || roc_model_is_cn10ka_a1(); +} + +/* IPBUNIXRX-40400 */ +static inline bool +roc_errata_nix_no_meta_aura(void) +{ return roc_model_is_cn10ka_a0(); } diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index 7da8938..603551b 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -627,18 +627,18 @@ roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq) inl_rq->first_skip = rq->first_skip; inl_rq->later_skip = rq->later_skip; inl_rq->lpb_size = rq->lpb_size; - inl_rq->lpb_drop_ena = true; inl_rq->spb_ena = rq->spb_ena; inl_rq->spb_aura_handle = rq->spb_aura_handle; inl_rq->spb_size = rq->spb_size; - inl_rq->spb_drop_ena = !!rq->spb_ena; - if (!roc_model_is_cn9k()) { + if (roc_errata_nix_no_meta_aura()) { uint64_t aura_limit = roc_npa_aura_op_limit_get(inl_rq->aura_handle); uint64_t aura_shift = plt_log2_u32(aura_limit); uint64_t aura_drop, drop_pc; + inl_rq->lpb_drop_ena = true; + if (aura_shift < 8) aura_shift = 0; else @@ -653,12 +653,14 @@ roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq) roc_npa_aura_drop_set(inl_rq->aura_handle, aura_drop, true); } - if (inl_rq->spb_ena) { + if (roc_errata_nix_no_meta_aura() && inl_rq->spb_ena) { uint64_t aura_limit = roc_npa_aura_op_limit_get(inl_rq->spb_aura_handle); uint64_t aura_shift = plt_log2_u32(aura_limit); uint64_t aura_drop, drop_pc; + inl_rq->spb_drop_ena = true; + if (aura_shift < 8) aura_shift = 0; else diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 2418290..df20f27 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -617,7 +617,8 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, rq->first_skip = first_skip; rq->later_skip = sizeof(struct rte_mbuf); rq->lpb_size = mp->elt_size; - rq->lpb_drop_ena = !(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY); + if (roc_errata_nix_no_meta_aura()) + rq->lpb_drop_ena = !(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY); /* Enable Inline IPSec on RQ, will not be used for Poll mode */ if (roc_nix_inl_inb_is_enabled(nix)) From patchwork Tue Aug 9 18:48:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 114785 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 756E3A04FD; Tue, 9 Aug 2022 20:52:10 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6198C42BD6; Tue, 9 Aug 2022 20:52:10 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 174EF42BDA for ; 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Tue, 9 Aug 2022 11:49:59 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 9 Aug 2022 11:49:59 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 3A40E3F7086; Tue, 9 Aug 2022 11:49:56 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: , Subject: [PATCH 06/23] common/cnxk: delay inline device RQ enable to dev start Date: Wed, 10 Aug 2022 00:18:50 +0530 Message-ID: <20220809184908.24030-6-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220809184908.24030-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: -spcDmKxLEXNLLRIGNhi0dBAj2fm5rEn X-Proofpoint-ORIG-GUID: -spcDmKxLEXNLLRIGNhi0dBAj2fm5rEn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Similar to other RQ's, delay inline device rq until dev is started to avoid traffic reception when device is stopped. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_idev.h | 2 -- drivers/common/cnxk/roc_nix_inl.c | 34 +++++++++++++++++++++++++++++++--- drivers/common/cnxk/roc_nix_inl.h | 5 ++++- drivers/common/cnxk/version.map | 7 ++++--- drivers/net/cnxk/cnxk_ethdev.c | 14 +++++++++++++- 5 files changed, 52 insertions(+), 10 deletions(-) diff --git a/drivers/common/cnxk/roc_idev.h b/drivers/common/cnxk/roc_idev.h index 7e0beed..16793c2 100644 --- a/drivers/common/cnxk/roc_idev.h +++ b/drivers/common/cnxk/roc_idev.h @@ -17,6 +17,4 @@ void __roc_api roc_idev_cpt_set(struct roc_cpt *cpt); struct roc_nix *__roc_api roc_idev_npa_nix_get(void); -uint64_t *__roc_api roc_nix_inl_outb_ring_base_get(struct roc_nix *roc_nix); - #endif /* _ROC_IDEV_H_ */ diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index 603551b..c621867 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -245,6 +245,9 @@ roc_nix_reassembly_configure(uint32_t max_wait_time, uint16_t max_frags) struct roc_cpt *roc_cpt; struct roc_cpt_rxc_time_cfg cfg; + if (!idev) + return -EFAULT; + PLT_SET_USED(max_frags); if (idev == NULL) return -ENOTSUP; @@ -587,7 +590,7 @@ roc_nix_inl_outb_is_enabled(struct roc_nix *roc_nix) } int -roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq) +roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq, bool enable) { struct idev_cfg *idev = idev_get_cfg(); int port_id = rq->roc_nix->port_id; @@ -688,9 +691,9 @@ roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq) /* Prepare and send RQ init mbox */ if (roc_model_is_cn9k()) - rc = nix_rq_cn9k_cfg(dev, inl_rq, inl_dev->qints, false, true); + rc = nix_rq_cn9k_cfg(dev, inl_rq, inl_dev->qints, false, enable); else - rc = nix_rq_cfg(dev, inl_rq, inl_dev->qints, false, true); + rc = nix_rq_cfg(dev, inl_rq, inl_dev->qints, false, enable); if (rc) { plt_err("Failed to prepare aq_enq msg, rc=%d", rc); return rc; @@ -755,6 +758,31 @@ roc_nix_inl_dev_rq_put(struct roc_nix_rq *rq) return rc; } +int +roc_nix_inl_rq_ena_dis(struct roc_nix *roc_nix, bool enable) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct roc_nix_rq *inl_rq = roc_nix_inl_dev_rq(roc_nix); + struct idev_cfg *idev = idev_get_cfg(); + struct nix_inl_dev *inl_dev; + int rc; + + if (!idev) + return -EFAULT; + + if (nix->inb_inl_dev) { + if (!inl_rq || !idev->nix_inl_dev) + return -EFAULT; + + inl_dev = idev->nix_inl_dev; + + rc = nix_rq_ena_dis(&inl_dev->dev, inl_rq, enable); + if (rc) + return rc; + } + return 0; +} + void roc_nix_inb_mode_set(struct roc_nix *roc_nix, bool use_inl_dev) { diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h index c7b1817..702ec01 100644 --- a/drivers/common/cnxk/roc_nix_inl.h +++ b/drivers/common/cnxk/roc_nix_inl.h @@ -165,7 +165,7 @@ uint32_t __roc_api roc_nix_inl_inb_sa_sz(struct roc_nix *roc_nix, uintptr_t __roc_api roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, bool inl_dev_sa, uint32_t spi); void __roc_api roc_nix_inb_mode_set(struct roc_nix *roc_nix, bool use_inl_dev); -int __roc_api roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq); +int __roc_api roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq, bool ena); int __roc_api roc_nix_inl_dev_rq_put(struct roc_nix_rq *rq); bool __roc_api roc_nix_inb_is_with_inl_dev(struct roc_nix *roc_nix); struct roc_nix_rq *__roc_api roc_nix_inl_dev_rq(struct roc_nix *roc_nix); @@ -175,6 +175,7 @@ int __roc_api roc_nix_reassembly_configure(uint32_t max_wait_time, uint16_t max_frags); int __roc_api roc_nix_inl_ts_pkind_set(struct roc_nix *roc_nix, bool ts_ena, bool inb_inl_dev); +int __roc_api roc_nix_inl_rq_ena_dis(struct roc_nix *roc_nix, bool ena); /* NIX Inline Outbound API */ int __roc_api roc_nix_inl_outb_init(struct roc_nix *roc_nix); @@ -189,6 +190,8 @@ int __roc_api roc_nix_inl_cb_unregister(roc_nix_inl_sso_work_cb_t cb, void *args); int __roc_api roc_nix_inl_outb_soft_exp_poll_switch(struct roc_nix *roc_nix, bool poll); +uint64_t *__roc_api roc_nix_inl_outb_ring_base_get(struct roc_nix *roc_nix); + /* NIX Inline/Outbound API */ enum roc_nix_inl_sa_sync_op { ROC_NIX_INL_SA_OP_FLUSH, diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index a2d99e1..6d43e37 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -90,7 +90,6 @@ INTERNAL { roc_hash_sha512_gen; roc_idev_cpt_get; roc_idev_cpt_set; - roc_nix_inl_outb_ring_base_get; roc_idev_lmt_base_addr_get; roc_idev_npa_maxpools_get; roc_idev_npa_maxpools_set; @@ -137,11 +136,13 @@ INTERNAL { roc_nix_get_vwqe_interval; roc_nix_inl_cb_register; roc_nix_inl_cb_unregister; + roc_nix_inl_ctx_write; roc_nix_inl_dev_dump; roc_nix_inl_dev_fini; roc_nix_inl_dev_init; roc_nix_inl_dev_is_probed; roc_nix_inl_dev_lock; + roc_nix_inl_dev_pffunc_get; roc_nix_inl_dev_rq; roc_nix_inl_dev_rq_get; roc_nix_inl_dev_rq_put; @@ -163,11 +164,11 @@ INTERNAL { roc_nix_inl_outb_sa_base_get; roc_nix_inl_outb_sso_pffunc_get; roc_nix_inl_outb_is_enabled; + roc_nix_inl_outb_ring_base_get; roc_nix_inl_outb_soft_exp_poll_switch; + roc_nix_inl_rq_ena_dis; roc_nix_inl_sa_sync; roc_nix_inl_ts_pkind_set; - roc_nix_inl_ctx_write; - roc_nix_inl_dev_pffunc_get; roc_nix_inl_outb_cpt_lfs_dump; roc_nix_cpt_ctx_cache_sync; roc_nix_is_lbk; diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index df20f27..b3af2f8 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -660,7 +660,7 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, 0x0FF00000 | ((uint32_t)RTE_EVENT_TYPE_ETHDEV << 28); /* Setup rq reference for inline dev if present */ - rc = roc_nix_inl_dev_rq_get(rq); + rc = roc_nix_inl_dev_rq_get(rq, !!eth_dev->data->dev_started); if (rc) goto free_mem; } @@ -1482,6 +1482,10 @@ cnxk_nix_dev_stop(struct rte_eth_dev *eth_dev) roc_nix_inl_outb_soft_exp_poll_switch(&dev->nix, false); + /* Stop inline device RQ first */ + if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) + roc_nix_inl_rq_ena_dis(&dev->nix, false); + /* Stop rx queues and free up pkts pending */ for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { rc = dev_ops->rx_queue_stop(eth_dev, i); @@ -1527,6 +1531,14 @@ cnxk_nix_dev_start(struct rte_eth_dev *eth_dev) return rc; } + if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) { + rc = roc_nix_inl_rq_ena_dis(&dev->nix, true); + if (rc) { + plt_err("Failed to enable Inline device RQ, rc=%d", rc); + return rc; + } + } + /* Start tx queues */ for (i = 0; i < eth_dev->data->nb_tx_queues; i++) { rc = cnxk_nix_tx_queue_start(eth_dev, i); From patchwork Tue Aug 9 18:48:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 114786 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7C033A04FD; Tue, 9 Aug 2022 20:52:16 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6F88F42BE6; Tue, 9 Aug 2022 20:52:16 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 7075542BD4 for ; Tue, 9 Aug 2022 20:52:14 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 279D65aj015667; Tue, 9 Aug 2022 11:50:07 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; 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Tue, 9 Aug 2022 11:49:59 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella , Ashwin Sekhar T K , Pavan Nikhilesh CC: , Subject: [PATCH 07/23] common/cnxk: reserve aura zero on cn10ka NPA Date: Wed, 10 Aug 2022 00:18:51 +0530 Message-ID: <20220809184908.24030-7-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220809184908.24030-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: GmyNGDgli5GzteTXP-z2mgLuhffdFMfy X-Proofpoint-GUID: GmyNGDgli5GzteTXP-z2mgLuhffdFMfy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Reserve aura id 0 on cn10k and provide mechanism to specifically allocate it and free it via roc_npa_* API's. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_dpi.c | 2 +- drivers/common/cnxk/roc_nix_queue.c | 2 +- drivers/common/cnxk/roc_npa.c | 100 ++++++++++++++++++++++++++------ drivers/common/cnxk/roc_npa.h | 6 +- drivers/common/cnxk/roc_npa_priv.h | 1 + drivers/common/cnxk/roc_sso.c | 2 +- drivers/common/cnxk/version.map | 1 + drivers/mempool/cnxk/cnxk_mempool_ops.c | 7 ++- 8 files changed, 97 insertions(+), 24 deletions(-) diff --git a/drivers/common/cnxk/roc_dpi.c b/drivers/common/cnxk/roc_dpi.c index 23b2cc4..93c8318 100644 --- a/drivers/common/cnxk/roc_dpi.c +++ b/drivers/common/cnxk/roc_dpi.c @@ -75,7 +75,7 @@ roc_dpi_configure(struct roc_dpi *roc_dpi) memset(&aura, 0, sizeof(aura)); rc = roc_npa_pool_create(&aura_handle, DPI_CMD_QUEUE_SIZE, - DPI_CMD_QUEUE_BUFS, &aura, &pool); + DPI_CMD_QUEUE_BUFS, &aura, &pool, 0); if (rc) { plt_err("Failed to create NPA pool, err %d\n", rc); return rc; diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index 692b134..70b4516 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -713,7 +713,7 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq) aura.fc_addr = (uint64_t)sq->fc; aura.fc_hyst_bits = 0; /* Store count on all updates */ rc = roc_npa_pool_create(&sq->aura_handle, blk_sz, nb_sqb_bufs, &aura, - &pool); + &pool, 0); if (rc) goto fail; diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c index 1e60f44..760a231 100644 --- a/drivers/common/cnxk/roc_npa.c +++ b/drivers/common/cnxk/roc_npa.c @@ -261,15 +261,59 @@ bitmap_ctzll(uint64_t slab) } static int +find_free_aura(struct npa_lf *lf, uint32_t flags) +{ + struct plt_bitmap *bmp = lf->npa_bmp; + uint64_t aura0_state = 0; + uint64_t slab; + uint32_t pos; + int idx = -1; + int rc; + + if (flags & ROC_NPA_ZERO_AURA_F) { + /* Only look for zero aura */ + if (plt_bitmap_get(bmp, 0)) + return 0; + plt_err("Zero aura already in use"); + return -1; + } + + if (lf->zero_aura_rsvd) { + /* Save and clear zero aura bit if needed */ + aura0_state = plt_bitmap_get(bmp, 0); + if (aura0_state) + plt_bitmap_clear(bmp, 0); + } + + pos = 0; + slab = 0; + /* Scan from the beginning */ + plt_bitmap_scan_init(bmp); + /* Scan bitmap to get the free pool */ + rc = plt_bitmap_scan(bmp, &pos, &slab); + /* Empty bitmap */ + if (rc == 0) { + plt_err("Aura's exhausted"); + goto empty; + } + + idx = pos + bitmap_ctzll(slab); +empty: + if (lf->zero_aura_rsvd && aura0_state) + plt_bitmap_set(bmp, 0); + + return idx; +} + +static int npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size, const uint32_t block_count, struct npa_aura_s *aura, - struct npa_pool_s *pool, uint64_t *aura_handle) + struct npa_pool_s *pool, uint64_t *aura_handle, + uint32_t flags) { int rc, aura_id, pool_id, stack_size, alloc_size; char name[PLT_MEMZONE_NAMESIZE]; const struct plt_memzone *mz; - uint64_t slab; - uint32_t pos; /* Sanity check */ if (!lf || !block_size || !block_count || !pool || !aura || @@ -281,20 +325,11 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size, block_size > ROC_NPA_MAX_BLOCK_SZ) return NPA_ERR_INVALID_BLOCK_SZ; - pos = 0; - slab = 0; - /* Scan from the beginning */ - plt_bitmap_scan_init(lf->npa_bmp); - /* Scan bitmap to get the free pool */ - rc = plt_bitmap_scan(lf->npa_bmp, &pos, &slab); - /* Empty bitmap */ - if (rc == 0) { - plt_err("Mempools exhausted"); - return NPA_ERR_AURA_ID_ALLOC; - } - /* Get aura_id from resource bitmap */ - aura_id = pos + bitmap_ctzll(slab); + aura_id = find_free_aura(lf, flags); + if (aura_id < 0) + return NPA_ERR_AURA_ID_ALLOC; + /* Mark pool as reserved */ plt_bitmap_clear(lf->npa_bmp, aura_id); @@ -374,7 +409,7 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size, int roc_npa_pool_create(uint64_t *aura_handle, uint32_t block_size, uint32_t block_count, struct npa_aura_s *aura, - struct npa_pool_s *pool) + struct npa_pool_s *pool, uint32_t flags) { struct npa_aura_s defaura; struct npa_pool_s defpool; @@ -394,6 +429,11 @@ roc_npa_pool_create(uint64_t *aura_handle, uint32_t block_size, goto error; } + if (flags & ROC_NPA_ZERO_AURA_F && !lf->zero_aura_rsvd) { + rc = NPA_ERR_ALLOC; + goto error; + } + if (aura == NULL) { memset(&defaura, 0, sizeof(struct npa_aura_s)); aura = &defaura; @@ -406,7 +446,7 @@ roc_npa_pool_create(uint64_t *aura_handle, uint32_t block_size, } rc = npa_aura_pool_pair_alloc(lf, block_size, block_count, aura, pool, - aura_handle); + aura_handle, flags); if (rc) { plt_err("Failed to alloc pool or aura rc=%d", rc); goto error; @@ -522,6 +562,26 @@ roc_npa_pool_range_update_check(uint64_t aura_handle) return 0; } +uint64_t +roc_npa_zero_aura_handle(void) +{ + struct idev_cfg *idev; + struct npa_lf *lf; + + lf = idev_npa_obj_get(); + if (lf == NULL) + return NPA_ERR_DEVICE_NOT_BOUNDED; + + idev = idev_get_cfg(); + if (idev == NULL) + return NPA_ERR_ALLOC; + + /* Return aura handle only if reserved */ + if (lf->zero_aura_rsvd) + return roc_npa_aura_handle_gen(0, lf->base); + return 0; +} + static inline int npa_attach(struct mbox *mbox) { @@ -672,6 +732,10 @@ npa_dev_init(struct npa_lf *lf, uintptr_t base, struct mbox *mbox) for (i = 0; i < nr_pools; i++) plt_bitmap_set(lf->npa_bmp, i); + /* Reserve zero aura for all models other than CN9K */ + if (!roc_model_is_cn9k()) + lf->zero_aura_rsvd = true; + /* Allocate memory for qint context */ lf->npa_qint_mem = plt_zmalloc(sizeof(struct npa_qint) * nr_pools, 0); if (lf->npa_qint_mem == NULL) { diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h index 59d13d8..69129cb 100644 --- a/drivers/common/cnxk/roc_npa.h +++ b/drivers/common/cnxk/roc_npa.h @@ -711,10 +711,13 @@ struct roc_npa { int __roc_api roc_npa_dev_init(struct roc_npa *roc_npa); int __roc_api roc_npa_dev_fini(struct roc_npa *roc_npa); +/* Flags to pool create */ +#define ROC_NPA_ZERO_AURA_F BIT(0) + /* NPA pool */ int __roc_api roc_npa_pool_create(uint64_t *aura_handle, uint32_t block_size, uint32_t block_count, struct npa_aura_s *aura, - struct npa_pool_s *pool); + struct npa_pool_s *pool, uint32_t flags); int __roc_api roc_npa_aura_limit_modify(uint64_t aura_handle, uint16_t aura_limit); int __roc_api roc_npa_pool_destroy(uint64_t aura_handle); @@ -722,6 +725,7 @@ int __roc_api roc_npa_pool_range_update_check(uint64_t aura_handle); void __roc_api roc_npa_aura_op_range_set(uint64_t aura_handle, uint64_t start_iova, uint64_t end_iova); +uint64_t __roc_api roc_npa_zero_aura_handle(void); /* Init callbacks */ typedef int (*roc_npa_lf_init_cb_t)(struct plt_pci_device *pci_dev); diff --git a/drivers/common/cnxk/roc_npa_priv.h b/drivers/common/cnxk/roc_npa_priv.h index 5a02a61..de3d544 100644 --- a/drivers/common/cnxk/roc_npa_priv.h +++ b/drivers/common/cnxk/roc_npa_priv.h @@ -32,6 +32,7 @@ struct npa_lf { uint8_t aura_sz; uint32_t qints; uintptr_t base; + bool zero_aura_rsvd; }; struct npa_qint { diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c index 126a9cb..4bee5a9 100644 --- a/drivers/common/cnxk/roc_sso.c +++ b/drivers/common/cnxk/roc_sso.c @@ -473,7 +473,7 @@ sso_hwgrp_init_xaq_aura(struct dev *dev, struct roc_sso_xaq_data *xaq, aura.fc_addr = (uint64_t)xaq->fc; aura.fc_hyst_bits = 0; /* Store count on all updates */ rc = roc_npa_pool_create(&xaq->aura_handle, xaq_buf_size, xaq->nb_xaq, - &aura, &pool); + &aura, &pool, 0); if (rc) { plt_err("Failed to create XAQ pool"); goto npa_fail; diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 6d43e37..6c05e89 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -318,6 +318,7 @@ INTERNAL { roc_npa_pool_destroy; roc_npa_pool_op_pc_reset; roc_npa_pool_range_update_check; + roc_npa_zero_aura_handle; roc_npc_fini; roc_npc_flow_create; roc_npc_flow_destroy; diff --git a/drivers/mempool/cnxk/cnxk_mempool_ops.c b/drivers/mempool/cnxk/cnxk_mempool_ops.c index c7b75f0..a0b94bb 100644 --- a/drivers/mempool/cnxk/cnxk_mempool_ops.c +++ b/drivers/mempool/cnxk/cnxk_mempool_ops.c @@ -72,10 +72,10 @@ cnxk_mempool_calc_mem_size(const struct rte_mempool *mp, uint32_t obj_num, int cnxk_mempool_alloc(struct rte_mempool *mp) { + uint32_t block_count, flags = 0; uint64_t aura_handle = 0; struct npa_aura_s aura; struct npa_pool_s pool; - uint32_t block_count; size_t block_size; int rc = -ERANGE; @@ -100,8 +100,11 @@ cnxk_mempool_alloc(struct rte_mempool *mp) if (mp->pool_config != NULL) memcpy(&aura, mp->pool_config, sizeof(struct npa_aura_s)); + if (aura.ena && aura.pool_addr == 0) + flags = ROC_NPA_ZERO_AURA_F; + rc = roc_npa_pool_create(&aura_handle, block_size, block_count, &aura, - &pool); + &pool, flags); if (rc) { plt_err("Failed to alloc pool or aura rc=%d", rc); goto error; From patchwork Tue Aug 9 18:48:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 114787 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CB14CA04FD; Tue, 9 Aug 2022 20:52:22 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B45DD42BEB; Tue, 9 Aug 2022 20:52:19 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 142F142BD8 for ; Tue, 9 Aug 2022 20:52:18 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 279D5wJO016176; Tue, 9 Aug 2022 11:50:13 -0700 DKIM-Signature: v=1; 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Tue, 9 Aug 2022 11:50:11 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 721F03F7085; Tue, 9 Aug 2022 11:50:03 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: , Subject: [PATCH 08/23] common/cnxk: add support to set NPA buf type Date: Wed, 10 Aug 2022 00:18:52 +0530 Message-ID: <20220809184908.24030-8-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220809184908.24030-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: syZv8Glc8t_U3qbDzu7k8o6EbYu5yJXK X-Proofpoint-GUID: syZv8Glc8t_U3qbDzu7k8o6EbYu5yJXK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support to set/get per-aura buf type with refs and get sum of all aura limits matching given buf type mask and val. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/meson.build | 1 + drivers/common/cnxk/roc_npa.c | 11 +++++ drivers/common/cnxk/roc_npa.h | 22 +++++++++ drivers/common/cnxk/roc_npa_priv.h | 8 ++- drivers/common/cnxk/roc_npa_type.c | 99 ++++++++++++++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 3 ++ 6 files changed, 143 insertions(+), 1 deletion(-) create mode 100644 drivers/common/cnxk/roc_npa_type.c diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build index 6f80827..127fcbc 100644 --- a/drivers/common/cnxk/meson.build +++ b/drivers/common/cnxk/meson.build @@ -51,6 +51,7 @@ sources = files( 'roc_npa.c', 'roc_npa_debug.c', 'roc_npa_irq.c', + 'roc_npa_type.c', 'roc_npc.c', 'roc_npc_mcam.c', 'roc_npc_mcam_dump.c', diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c index 760a231..ee42434 100644 --- a/drivers/common/cnxk/roc_npa.c +++ b/drivers/common/cnxk/roc_npa.c @@ -499,6 +499,7 @@ npa_aura_pool_pair_free(struct npa_lf *lf, uint64_t aura_handle) pool_id = aura_id; rc = npa_aura_pool_fini(lf->mbox, aura_id, aura_handle); rc |= npa_stack_dma_free(lf, name, pool_id); + memset(&lf->aura_attr[aura_id], 0, sizeof(struct npa_aura_attr)); plt_bitmap_set(lf->npa_bmp, aura_id); @@ -750,6 +751,13 @@ npa_dev_init(struct npa_lf *lf, uintptr_t base, struct mbox *mbox) goto qint_free; } + /* Allocate per-aura attribute */ + lf->aura_attr = plt_zmalloc(sizeof(struct npa_aura_attr) * nr_pools, 0); + if (lf->aura_attr == NULL) { + rc = NPA_ERR_PARAM; + goto lim_free; + } + /* Init aura start & end limits */ for (i = 0; i < nr_pools; i++) { lf->aura_lim[i].ptr_start = UINT64_MAX; @@ -758,6 +766,8 @@ npa_dev_init(struct npa_lf *lf, uintptr_t base, struct mbox *mbox) return 0; +lim_free: + plt_free(lf->aura_lim); qint_free: plt_free(lf->npa_qint_mem); bmap_free: @@ -780,6 +790,7 @@ npa_dev_fini(struct npa_lf *lf) plt_free(lf->npa_qint_mem); plt_bitmap_free(lf->npa_bmp); plt_free(lf->npa_bmp_mem); + plt_free(lf->aura_attr); return npa_lf_free(lf->mbox); } diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h index 69129cb..fed1942 100644 --- a/drivers/common/cnxk/roc_npa.h +++ b/drivers/common/cnxk/roc_npa.h @@ -714,6 +714,25 @@ int __roc_api roc_npa_dev_fini(struct roc_npa *roc_npa); /* Flags to pool create */ #define ROC_NPA_ZERO_AURA_F BIT(0) +/* Enumerations */ +enum roc_npa_buf_type { + /* Aura used for normal pkts */ + ROC_NPA_BUF_TYPE_PACKET = 0, + /* Aura used for ipsec pkts */ + ROC_NPA_BUF_TYPE_PACKET_IPSEC, + /* Aura used as vwqe for normal pkts */ + ROC_NPA_BUF_TYPE_VWQE, + /* Aura used as vwqe for ipsec pkts */ + ROC_NPA_BUF_TYPE_VWQE_IPSEC, + /* Aura used as SQB for SQ */ + ROC_NPA_BUF_TYPE_SQB, + /* Aura used for general buffer */ + ROC_NPA_BUF_TYPE_BUF, + /* Aura used for timeout pool */ + ROC_NPA_BUF_TYPE_TIMEOUT, + ROC_NPA_BUF_TYPE_END, +}; + /* NPA pool */ int __roc_api roc_npa_pool_create(uint64_t *aura_handle, uint32_t block_size, uint32_t block_count, struct npa_aura_s *aura, @@ -726,6 +745,9 @@ void __roc_api roc_npa_aura_op_range_set(uint64_t aura_handle, uint64_t start_iova, uint64_t end_iova); uint64_t __roc_api roc_npa_zero_aura_handle(void); +int __roc_api roc_npa_buf_type_update(uint64_t aura_handle, enum roc_npa_buf_type type, int cnt); +uint64_t __roc_api roc_npa_buf_type_mask(uint64_t aura_handle); +uint64_t __roc_api roc_npa_buf_type_limit_get(uint64_t type_mask); /* Init callbacks */ typedef int (*roc_npa_lf_init_cb_t)(struct plt_pci_device *pci_dev); diff --git a/drivers/common/cnxk/roc_npa_priv.h b/drivers/common/cnxk/roc_npa_priv.h index de3d544..d2118cc 100644 --- a/drivers/common/cnxk/roc_npa_priv.h +++ b/drivers/common/cnxk/roc_npa_priv.h @@ -18,6 +18,7 @@ enum npa_error_status { struct npa_lf { struct plt_intr_handle *intr_handle; + struct npa_aura_attr *aura_attr; struct npa_aura_lim *aura_lim; struct plt_pci_device *pci_dev; struct plt_bitmap *npa_bmp; @@ -25,6 +26,7 @@ struct npa_lf { uint32_t stack_pg_ptrs; uint32_t stack_pg_bytes; uint16_t npa_msixoff; + bool zero_aura_rsvd; void *npa_qint_mem; void *npa_bmp_mem; uint32_t nr_pools; @@ -32,7 +34,7 @@ struct npa_lf { uint8_t aura_sz; uint32_t qints; uintptr_t base; - bool zero_aura_rsvd; + }; struct npa_qint { @@ -45,6 +47,10 @@ struct npa_aura_lim { uint64_t ptr_end; }; +struct npa_aura_attr { + int buf_type[ROC_NPA_BUF_TYPE_END]; +}; + struct dev; static inline struct npa * diff --git a/drivers/common/cnxk/roc_npa_type.c b/drivers/common/cnxk/roc_npa_type.c new file mode 100644 index 0000000..ed90138 --- /dev/null +++ b/drivers/common/cnxk/roc_npa_type.c @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2022 Marvell. + */ + +#include "roc_api.h" +#include "roc_priv.h" + +int +roc_npa_buf_type_update(uint64_t aura_handle, enum roc_npa_buf_type type, int count) +{ + uint64_t aura_id = roc_npa_aura_handle_to_aura(aura_handle); + struct npa_lf *lf; + + lf = idev_npa_obj_get(); + if (lf == NULL || aura_id >= lf->nr_pools) + return NPA_ERR_PARAM; + + if (plt_bitmap_get(lf->npa_bmp, aura_id)) { + plt_err("Cannot set buf type on unused aura"); + return NPA_ERR_PARAM; + } + + if (type >= ROC_NPA_BUF_TYPE_END || (lf->aura_attr[aura_id].buf_type[type] + count < 0)) { + plt_err("Pool buf type invalid"); + return NPA_ERR_PARAM; + } + + lf->aura_attr[aura_id].buf_type[type] += count; + plt_wmb(); + return 0; +} + +uint64_t +roc_npa_buf_type_mask(uint64_t aura_handle) +{ + uint64_t aura_id = roc_npa_aura_handle_to_aura(aura_handle); + uint64_t type_mask = 0; + struct npa_lf *lf; + int type; + + lf = idev_npa_obj_get(); + if (lf == NULL || aura_id >= lf->nr_pools) { + plt_err("Invalid aura id or lf"); + return 0; + } + + if (plt_bitmap_get(lf->npa_bmp, aura_id)) { + plt_err("Cannot get buf_type on unused aura"); + return 0; + } + + for (type = 0; type < ROC_NPA_BUF_TYPE_END; type++) { + if (lf->aura_attr[aura_id].buf_type[type]) + type_mask |= BIT_ULL(type); + } + + return type_mask; +} + +uint64_t +roc_npa_buf_type_limit_get(uint64_t type_mask) +{ + uint64_t wdata, reg; + uint64_t limit = 0; + struct npa_lf *lf; + uint64_t aura_id; + int64_t *addr; + uint64_t val; + int type; + + lf = idev_npa_obj_get(); + if (lf == NULL) + return NPA_ERR_PARAM; + + for (aura_id = 0; aura_id < lf->nr_pools; aura_id++) { + if (plt_bitmap_get(lf->npa_bmp, aura_id)) + continue; + + /* Find aura's matching the buf_types requested */ + if (type_mask != 0) { + val = 0; + for (type = 0; type < ROC_NPA_BUF_TYPE_END; type++) { + if (lf->aura_attr[aura_id].buf_type[type] != 0) + val |= BIT_ULL(type); + } + if ((val & type_mask) == 0) + continue; + } + + wdata = aura_id << 44; + addr = (int64_t *)(lf->base + NPA_LF_AURA_OP_LIMIT); + reg = roc_atomic64_add_nosync(wdata, addr); + + if (!(reg & BIT_ULL(42))) + limit += (reg & ROC_AURA_OP_LIMIT_MASK); + } + + return limit; +} diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 6c05e89..6f3de2a 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -306,6 +306,9 @@ INTERNAL { roc_nix_vlan_mcam_entry_write; roc_nix_vlan_strip_vtag_ena_dis; roc_nix_vlan_tpid_set; + roc_npa_buf_type_mask; + roc_npa_buf_type_limit_get; + roc_npa_buf_type_update; roc_npa_aura_drop_set; roc_npa_aura_limit_modify; roc_npa_aura_op_range_set; From patchwork Tue Aug 9 18:48:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 114770 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4604AA04FD; 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Tue, 09 Aug 2022 11:50:18 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 9 Aug 2022 11:50:16 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 9 Aug 2022 11:50:16 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 4488D3F7122; Tue, 9 Aug 2022 11:50:06 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 09/23] common/cnxk: update attributes to pools used by NIX Date: Wed, 10 Aug 2022 00:18:53 +0530 Message-ID: <20220809184908.24030-9-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220809184908.24030-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 2JxENP7ZGXUZJQuH4r9suE4ntU38wl9r X-Proofpoint-GUID: 2JxENP7ZGXUZJQuH4r9suE4ntU38wl9r X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Update attributes to pools used by NIX. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_nix_queue.c | 112 +++++++++++++++++++++++++++++++++++- 1 file changed, 110 insertions(+), 2 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index 70b4516..98b9fb4 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -140,6 +140,96 @@ roc_nix_rq_is_sso_enable(struct roc_nix *roc_nix, uint32_t qid) return sso_enable ? true : false; } +static int +nix_rq_aura_buf_type_update(struct roc_nix_rq *rq, bool set) +{ + struct roc_nix *roc_nix = rq->roc_nix; + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + bool inl_inb_ena = roc_nix_inl_inb_is_enabled(roc_nix); + uint64_t lpb_aura = 0, vwqe_aura = 0, spb_aura = 0; + struct mbox *mbox = nix->dev.mbox; + uint64_t aura_base; + int rc, count; + + count = set ? 1 : -1; + /* For buf type set, use info from RQ context */ + if (set) { + lpb_aura = rq->aura_handle; + spb_aura = rq->spb_ena ? rq->spb_aura_handle : 0; + vwqe_aura = rq->vwqe_ena ? rq->vwqe_aura_handle : 0; + goto skip_ctx_read; + } + + aura_base = roc_npa_aura_handle_to_base(rq->aura_handle); + if (roc_model_is_cn9k()) { + struct nix_aq_enq_rsp *rsp; + struct nix_aq_enq_req *aq; + + aq = mbox_alloc_msg_nix_aq_enq(mbox); + if (!aq) + return -ENOSPC; + + aq->qidx = rq->qid; + aq->ctype = NIX_AQ_CTYPE_RQ; + aq->op = NIX_AQ_INSTOP_READ; + rc = mbox_process_msg(mbox, (void *)&rsp); + if (rc) + return rc; + + /* Get aura handle from aura */ + lpb_aura = roc_npa_aura_handle_gen(rsp->rq.lpb_aura, aura_base); + if (rsp->rq.spb_ena) + spb_aura = roc_npa_aura_handle_gen(rsp->rq.spb_aura, aura_base); + } else { + struct nix_cn10k_aq_enq_rsp *rsp; + struct nix_cn10k_aq_enq_req *aq; + + aq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox); + if (!aq) + return -ENOSPC; + + aq->qidx = rq->qid; + aq->ctype = NIX_AQ_CTYPE_RQ; + aq->op = NIX_AQ_INSTOP_READ; + + rc = mbox_process_msg(mbox, (void *)&rsp); + if (rc) + return rc; + + /* Get aura handle from aura */ + lpb_aura = roc_npa_aura_handle_gen(rsp->rq.lpb_aura, aura_base); + if (rsp->rq.spb_ena) + spb_aura = roc_npa_aura_handle_gen(rsp->rq.spb_aura, aura_base); + if (rsp->rq.vwqe_ena) + vwqe_aura = roc_npa_aura_handle_gen(rsp->rq.wqe_aura, aura_base); + } + +skip_ctx_read: + /* Update attributes for LPB aura */ + if (inl_inb_ena) + roc_npa_buf_type_update(lpb_aura, ROC_NPA_BUF_TYPE_PACKET_IPSEC, count); + else + roc_npa_buf_type_update(lpb_aura, ROC_NPA_BUF_TYPE_PACKET, count); + + /* Update attributes for SPB aura */ + if (spb_aura) { + if (inl_inb_ena) + roc_npa_buf_type_update(spb_aura, ROC_NPA_BUF_TYPE_PACKET_IPSEC, count); + else + roc_npa_buf_type_update(spb_aura, ROC_NPA_BUF_TYPE_PACKET, count); + } + + /* Update attributes for VWQE aura */ + if (vwqe_aura) { + if (inl_inb_ena) + roc_npa_buf_type_update(vwqe_aura, ROC_NPA_BUF_TYPE_VWQE_IPSEC, count); + else + roc_npa_buf_type_update(vwqe_aura, ROC_NPA_BUF_TYPE_VWQE, count); + } + + return 0; +} + int nix_rq_cn9k_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg, bool ena) @@ -292,7 +382,7 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg, /* Maximal Vector size is (2^(MAX_VSIZE_EXP+2)) */ aq->rq.max_vsize_exp = rq->vwqe_max_sz_exp - 2; aq->rq.vtime_wait = rq->vwqe_wait_tmo; - aq->rq.wqe_aura = rq->vwqe_aura_handle; + aq->rq.wqe_aura = roc_npa_aura_handle_to_aura(rq->vwqe_aura_handle); } } else { /* CQ mode */ @@ -463,6 +553,9 @@ roc_nix_rq_init(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena) if (rc) return rc; + /* Update aura buf type to indicate its use */ + nix_rq_aura_buf_type_update(rq, true); + return nix_tel_node_add_rq(rq); } @@ -481,6 +574,9 @@ roc_nix_rq_modify(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena) if (rq->qid >= nix->nb_rx_queues) return NIX_ERR_QUEUE_INVALID_RANGE; + /* Clear attributes for existing aura's */ + nix_rq_aura_buf_type_update(rq, false); + rq->roc_nix = roc_nix; if (is_cn9k) @@ -495,14 +591,25 @@ roc_nix_rq_modify(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena) if (rc) return rc; + /* Update aura attribute to indicate its use */ + nix_rq_aura_buf_type_update(rq, true); + return nix_tel_node_add_rq(rq); } int roc_nix_rq_fini(struct roc_nix_rq *rq) { + int rc; + /* Disabling RQ is sufficient */ - return roc_nix_rq_ena_dis(rq, false); + rc = roc_nix_rq_ena_dis(rq, false); + if (rc) + return rc; + + /* Update aura attribute to indicate its use for */ + nix_rq_aura_buf_type_update(rq, false); + return 0; } int @@ -717,6 +824,7 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq) if (rc) goto fail; + roc_npa_buf_type_update(sq->aura_handle, ROC_NPA_BUF_TYPE_SQB, 1); sq->sqe_mem = plt_zmalloc(blk_sz * nb_sqb_bufs, blk_sz); if (sq->sqe_mem == NULL) { rc = NIX_ERR_NO_MEM; From patchwork Tue Aug 9 18:48:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 114788 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 02422A04FD; Tue, 9 Aug 2022 20:52:30 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E9F6942C02; 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Tue, 09 Aug 2022 11:50:22 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 9 Aug 2022 11:50:20 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 9 Aug 2022 11:50:20 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id D864B3F7149; Tue, 9 Aug 2022 11:50:08 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: , Subject: [PATCH 10/23] common/cnxk: support zero aura for inline inbound meta Date: Wed, 10 Aug 2022 00:18:54 +0530 Message-ID: <20220809184908.24030-10-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220809184908.24030-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 1g9cZlJ3MWzO3M0-wjI7PvtqDR7OvRmx X-Proofpoint-ORIG-GUID: 1g9cZlJ3MWzO3M0-wjI7PvtqDR7OvRmx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support to create zero aura for inline inbound meta pkts when platform supports it. Aura zero will hold as many buffers as all the available pkt pool with a data to accommodate 384B in best case to store meta packets coming from Inline IPsec. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_idev.c | 10 ++ drivers/common/cnxk/roc_idev.h | 1 + drivers/common/cnxk/roc_idev_priv.h | 9 ++ drivers/common/cnxk/roc_nix.h | 1 + drivers/common/cnxk/roc_nix_inl.c | 211 +++++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_nix_inl.h | 8 ++ drivers/common/cnxk/roc_nix_inl_dev.c | 2 + drivers/common/cnxk/roc_nix_inl_priv.h | 4 + drivers/common/cnxk/roc_nix_priv.h | 1 + drivers/common/cnxk/roc_nix_queue.c | 19 +++ drivers/common/cnxk/version.map | 4 + 11 files changed, 270 insertions(+) diff --git a/drivers/common/cnxk/roc_idev.c b/drivers/common/cnxk/roc_idev.c index a08c7ce..4d2eff9 100644 --- a/drivers/common/cnxk/roc_idev.c +++ b/drivers/common/cnxk/roc_idev.c @@ -241,3 +241,13 @@ idev_sso_set(struct roc_sso *sso) if (idev != NULL) __atomic_store_n(&idev->sso, sso, __ATOMIC_RELEASE); } + +uint64_t +roc_idev_nix_inl_meta_aura_get(void) +{ + struct idev_cfg *idev = idev_get_cfg(); + + if (idev != NULL) + return idev->inl_cfg.meta_aura; + return 0; +} diff --git a/drivers/common/cnxk/roc_idev.h b/drivers/common/cnxk/roc_idev.h index 16793c2..926aac0 100644 --- a/drivers/common/cnxk/roc_idev.h +++ b/drivers/common/cnxk/roc_idev.h @@ -16,5 +16,6 @@ struct roc_cpt *__roc_api roc_idev_cpt_get(void); void __roc_api roc_idev_cpt_set(struct roc_cpt *cpt); struct roc_nix *__roc_api roc_idev_npa_nix_get(void); +uint64_t __roc_api roc_idev_nix_inl_meta_aura_get(void); #endif /* _ROC_IDEV_H_ */ diff --git a/drivers/common/cnxk/roc_idev_priv.h b/drivers/common/cnxk/roc_idev_priv.h index 46eebff..315cc6f 100644 --- a/drivers/common/cnxk/roc_idev_priv.h +++ b/drivers/common/cnxk/roc_idev_priv.h @@ -10,6 +10,14 @@ struct npa_lf; struct roc_bphy; struct roc_cpt; struct nix_inl_dev; + +struct idev_nix_inl_cfg { + uint64_t meta_aura; + uint32_t nb_bufs; + uint32_t buf_sz; + uint32_t refs; +}; + struct idev_cfg { uint16_t sso_pf_func; uint16_t npa_pf_func; @@ -23,6 +31,7 @@ struct idev_cfg { struct roc_cpt *cpt; struct roc_sso *sso; struct nix_inl_dev *nix_inl_dev; + struct idev_nix_inl_cfg inl_cfg; plt_spinlock_t nix_inl_dev_lock; }; diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 3ad3a7e..5f5f5f9 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -315,6 +315,7 @@ struct roc_nix_rq { bool spb_drop_ena; /* End of Input parameters */ struct roc_nix *roc_nix; + uint64_t meta_aura_handle; uint16_t inl_dev_refs; }; diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index c621867..507a153 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -6,6 +6,7 @@ #include "roc_priv.h" uint32_t soft_exp_consumer_cnt; +roc_nix_inl_meta_pool_cb_t meta_pool_cb; PLT_STATIC_ASSERT(ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ == 1UL << ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ_LOG2); @@ -19,6 +20,155 @@ PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ == 1UL << ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ_LOG2); static int +nix_inl_meta_aura_destroy(void) +{ + struct idev_cfg *idev = idev_get_cfg(); + struct idev_nix_inl_cfg *inl_cfg; + int rc; + + if (!idev) + return -EINVAL; + + inl_cfg = &idev->inl_cfg; + /* Destroy existing Meta aura */ + if (inl_cfg->meta_aura) { + uint64_t avail, limit; + + /* Check if all buffers are back to pool */ + avail = roc_npa_aura_op_available(inl_cfg->meta_aura); + limit = roc_npa_aura_op_limit_get(inl_cfg->meta_aura); + if (avail != limit) + plt_warn("Not all buffers are back to meta pool," + " %" PRIu64 " != %" PRIu64, avail, limit); + + rc = meta_pool_cb(&inl_cfg->meta_aura, 0, 0, true); + if (rc) { + plt_err("Failed to destroy meta aura, rc=%d", rc); + return rc; + } + inl_cfg->meta_aura = 0; + inl_cfg->buf_sz = 0; + inl_cfg->nb_bufs = 0; + inl_cfg->refs = 0; + } + + return 0; +} + +static int +nix_inl_meta_aura_create(struct idev_cfg *idev, uint16_t first_skip) +{ + uint64_t mask = BIT_ULL(ROC_NPA_BUF_TYPE_PACKET_IPSEC); + struct idev_nix_inl_cfg *inl_cfg; + struct nix_inl_dev *nix_inl_dev; + uint32_t nb_bufs, buf_sz; + int rc; + + inl_cfg = &idev->inl_cfg; + nix_inl_dev = idev->nix_inl_dev; + + /* Override meta buf count from devargs if present */ + if (nix_inl_dev && nix_inl_dev->nb_meta_bufs) + nb_bufs = nix_inl_dev->nb_meta_bufs; + else + nb_bufs = roc_npa_buf_type_limit_get(mask); + + /* Override meta buf size from devargs if present */ + if (nix_inl_dev && nix_inl_dev->meta_buf_sz) + buf_sz = nix_inl_dev->meta_buf_sz; + else + buf_sz = first_skip + NIX_INL_META_SIZE; + + /* Allocate meta aura */ + rc = meta_pool_cb(&inl_cfg->meta_aura, buf_sz, nb_bufs, false); + if (rc) { + plt_err("Failed to allocate meta aura, rc=%d", rc); + return rc; + } + + inl_cfg->buf_sz = buf_sz; + inl_cfg->nb_bufs = nb_bufs; + return 0; +} + +int +roc_nix_inl_meta_aura_check(struct roc_nix_rq *rq) +{ + struct idev_cfg *idev = idev_get_cfg(); + struct idev_nix_inl_cfg *inl_cfg; + uint32_t actual, expected; + uint64_t mask, type_mask; + int rc; + + if (!idev || !meta_pool_cb) + return -EFAULT; + inl_cfg = &idev->inl_cfg; + + /* Create meta aura if not present */ + if (!inl_cfg->meta_aura) { + rc = nix_inl_meta_aura_create(idev, rq->first_skip); + if (rc) + return rc; + } + + /* Validate if we have enough meta buffers */ + mask = BIT_ULL(ROC_NPA_BUF_TYPE_PACKET_IPSEC); + expected = roc_npa_buf_type_limit_get(mask); + actual = inl_cfg->nb_bufs; + + if (actual < expected) { + plt_err("Insufficient buffers in meta aura %u < %u (expected)", + actual, expected); + return -EIO; + } + + /* Validate if we have enough space for meta buffer */ + if (rq->first_skip + NIX_INL_META_SIZE > inl_cfg->buf_sz) { + plt_err("Meta buffer size %u not sufficient to meet RQ first skip %u", + inl_cfg->buf_sz, rq->first_skip); + return -EIO; + } + + /* Validate if we have enough VWQE buffers */ + if (rq->vwqe_ena) { + actual = roc_npa_aura_op_limit_get(rq->vwqe_aura_handle); + + type_mask = roc_npa_buf_type_mask(rq->vwqe_aura_handle); + if (type_mask & BIT_ULL(ROC_NPA_BUF_TYPE_VWQE_IPSEC) && + type_mask & BIT_ULL(ROC_NPA_BUF_TYPE_VWQE)) { + /* VWQE aura shared b/w Inline enabled and non Inline + * enabled ports needs enough buffers to store all the + * packet buffers, one per vwqe. + */ + mask = (BIT_ULL(ROC_NPA_BUF_TYPE_PACKET_IPSEC) | + BIT_ULL(ROC_NPA_BUF_TYPE_PACKET)); + expected = roc_npa_buf_type_limit_get(mask); + + if (actual < expected) { + plt_err("VWQE aura shared b/w Inline inbound and non-Inline inbound " + "ports needs vwqe bufs(%u) minimum of all pkt bufs (%u)", + actual, expected); + return -EIO; + } + } else { + /* VWQE aura not shared b/w Inline and non Inline ports have relaxed + * requirement of match all the meta buffers. + */ + expected = inl_cfg->nb_bufs; + + if (actual < expected) { + plt_err("VWQE aura not shared b/w Inline inbound and non-Inline " + "ports needs vwqe bufs(%u) minimum of all meta bufs (%u)", + actual, expected); + return -EIO; + } + } + } + + return 0; +} + +static int nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix) { uint32_t ipsec_in_min_spi = roc_nix->ipsec_in_min_spi; @@ -310,6 +460,10 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix) if (rc) return rc; + if (!roc_model_is_cn9k() && !roc_errata_nix_no_meta_aura()) { + nix->need_meta_aura = true; + idev->inl_cfg.refs++; + } nix->inl_inb_ena = true; return 0; } @@ -317,12 +471,22 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix) int roc_nix_inl_inb_fini(struct roc_nix *roc_nix) { + struct idev_cfg *idev = idev_get_cfg(); struct nix *nix = roc_nix_to_nix_priv(roc_nix); if (!nix->inl_inb_ena) return 0; + if (!idev) + return -EFAULT; + nix->inl_inb_ena = false; + if (nix->need_meta_aura) { + nix->need_meta_aura = false; + idev->inl_cfg.refs--; + if (!idev->inl_cfg.refs) + nix_inl_meta_aura_destroy(); + } /* Flush Inbound CTX cache entries */ roc_nix_cpt_ctx_cache_sync(roc_nix); @@ -592,6 +756,7 @@ roc_nix_inl_outb_is_enabled(struct roc_nix *roc_nix) int roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq, bool enable) { + struct nix *nix = roc_nix_to_nix_priv(rq->roc_nix); struct idev_cfg *idev = idev_get_cfg(); int port_id = rq->roc_nix->port_id; struct nix_inl_dev *inl_dev; @@ -603,6 +768,10 @@ roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq, bool enable) if (idev == NULL) return 0; + /* Update meta aura handle in RQ */ + if (nix->need_meta_aura) + rq->meta_aura_handle = roc_npa_zero_aura_handle(); + inl_dev = idev->nix_inl_dev; /* Nothing to do if no inline device */ if (!inl_dev) @@ -705,6 +874,13 @@ roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq, bool enable) return rc; } + /* Check meta aura */ + if (enable && nix->need_meta_aura) { + rc = roc_nix_inl_meta_aura_check(rq); + if (rc) + return rc; + } + inl_rq->inl_dev_refs++; rq->inl_dev_refs = 1; return 0; @@ -724,6 +900,7 @@ roc_nix_inl_dev_rq_put(struct roc_nix_rq *rq) if (idev == NULL) return 0; + rq->meta_aura_handle = 0; if (!rq->inl_dev_refs) return 0; @@ -779,6 +956,9 @@ roc_nix_inl_rq_ena_dis(struct roc_nix *roc_nix, bool enable) rc = nix_rq_ena_dis(&inl_dev->dev, inl_rq, enable); if (rc) return rc; + + if (enable && nix->need_meta_aura) + return roc_nix_inl_meta_aura_check(inl_rq); } return 0; } @@ -792,6 +972,31 @@ roc_nix_inb_mode_set(struct roc_nix *roc_nix, bool use_inl_dev) nix->inb_inl_dev = use_inl_dev; } +void +roc_nix_inl_inb_set(struct roc_nix *roc_nix, bool ena) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct idev_cfg *idev = idev_get_cfg(); + + if (!idev) + return; + /* Need to set here for cases when inbound SA table is + * managed outside RoC. + */ + nix->inl_inb_ena = ena; + if (!roc_model_is_cn9k() && !roc_errata_nix_no_meta_aura()) { + if (ena) { + nix->need_meta_aura = true; + idev->inl_cfg.refs++; + } else if (nix->need_meta_aura) { + nix->need_meta_aura = false; + idev->inl_cfg.refs--; + if (!idev->inl_cfg.refs) + nix_inl_meta_aura_destroy(); + } + } +} + int roc_nix_inl_outb_soft_exp_poll_switch(struct roc_nix *roc_nix, bool poll) { @@ -1128,3 +1333,9 @@ roc_nix_inl_dev_unlock(void) if (idev != NULL) plt_spinlock_unlock(&idev->nix_inl_dev_lock); } + +void +roc_nix_inl_meta_pool_cb_register(roc_nix_inl_meta_pool_cb_t cb) +{ + meta_pool_cb = cb; +} diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h index 702ec01..9911a48 100644 --- a/drivers/common/cnxk/roc_nix_inl.h +++ b/drivers/common/cnxk/roc_nix_inl.h @@ -121,6 +121,9 @@ roc_nix_inl_ot_ipsec_outb_sa_sw_rsvd(void *sa) typedef void (*roc_nix_inl_sso_work_cb_t)(uint64_t *gw, void *args, uint32_t soft_exp_event); +typedef int (*roc_nix_inl_meta_pool_cb_t)(uint64_t *aura_handle, uint32_t blk_sz, uint32_t nb_bufs, + bool destroy); + struct roc_nix_inl_dev { /* Input parameters */ struct plt_pci_device *pci_dev; @@ -135,6 +138,8 @@ struct roc_nix_inl_dev { uint8_t spb_drop_pc; uint8_t lpb_drop_pc; bool set_soft_exp_poll; + uint32_t nb_meta_bufs; + uint32_t meta_buf_sz; /* End of input parameters */ #define ROC_NIX_INL_MEM_SZ (1280) @@ -165,6 +170,7 @@ uint32_t __roc_api roc_nix_inl_inb_sa_sz(struct roc_nix *roc_nix, uintptr_t __roc_api roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, bool inl_dev_sa, uint32_t spi); void __roc_api roc_nix_inb_mode_set(struct roc_nix *roc_nix, bool use_inl_dev); +void __roc_api roc_nix_inl_inb_set(struct roc_nix *roc_nix, bool ena); int __roc_api roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq, bool ena); int __roc_api roc_nix_inl_dev_rq_put(struct roc_nix_rq *rq); bool __roc_api roc_nix_inb_is_with_inl_dev(struct roc_nix *roc_nix); @@ -176,6 +182,7 @@ int __roc_api roc_nix_reassembly_configure(uint32_t max_wait_time, int __roc_api roc_nix_inl_ts_pkind_set(struct roc_nix *roc_nix, bool ts_ena, bool inb_inl_dev); int __roc_api roc_nix_inl_rq_ena_dis(struct roc_nix *roc_nix, bool ena); +int __roc_api roc_nix_inl_meta_aura_check(struct roc_nix_rq *rq); /* NIX Inline Outbound API */ int __roc_api roc_nix_inl_outb_init(struct roc_nix *roc_nix); @@ -191,6 +198,7 @@ int __roc_api roc_nix_inl_cb_unregister(roc_nix_inl_sso_work_cb_t cb, int __roc_api roc_nix_inl_outb_soft_exp_poll_switch(struct roc_nix *roc_nix, bool poll); uint64_t *__roc_api roc_nix_inl_outb_ring_base_get(struct roc_nix *roc_nix); +void __roc_api roc_nix_inl_meta_pool_cb_register(roc_nix_inl_meta_pool_cb_t cb); /* NIX Inline/Outbound API */ enum roc_nix_inl_sa_sync_op { diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c index 3a96498..1e9b2b9 100644 --- a/drivers/common/cnxk/roc_nix_inl_dev.c +++ b/drivers/common/cnxk/roc_nix_inl_dev.c @@ -841,6 +841,8 @@ roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev) inl_dev->lpb_drop_pc = NIX_AURA_DROP_PC_DFLT; inl_dev->set_soft_exp_poll = roc_inl_dev->set_soft_exp_poll; inl_dev->nb_rqs = inl_dev->is_multi_channel ? 1 : PLT_MAX_ETHPORTS; + inl_dev->nb_meta_bufs = roc_inl_dev->nb_meta_bufs; + inl_dev->meta_buf_sz = roc_inl_dev->meta_buf_sz; if (roc_inl_dev->spb_drop_pc) inl_dev->spb_drop_pc = roc_inl_dev->spb_drop_pc; diff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h index a775efc..ccd2adf 100644 --- a/drivers/common/cnxk/roc_nix_inl_priv.h +++ b/drivers/common/cnxk/roc_nix_inl_priv.h @@ -6,6 +6,8 @@ #include #include +#define NIX_INL_META_SIZE 384u + struct nix_inl_dev; struct nix_inl_qint { struct nix_inl_dev *inl_dev; @@ -86,6 +88,8 @@ struct nix_inl_dev { bool attach_cptlf; uint16_t wqe_skip; bool ts_ena; + uint32_t nb_meta_bufs; + uint32_t meta_buf_sz; }; int nix_inl_sso_register_irqs(struct nix_inl_dev *inl_dev); diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h index a3d4ddf..a253f41 100644 --- a/drivers/common/cnxk/roc_nix_priv.h +++ b/drivers/common/cnxk/roc_nix_priv.h @@ -202,6 +202,7 @@ struct nix { uint16_t nb_cpt_lf; uint16_t outb_se_ring_cnt; uint16_t outb_se_ring_base; + bool need_meta_aura; /* Mode provided by driver */ bool inb_inl_dev; diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index 98b9fb4..b197de0 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -89,7 +89,12 @@ roc_nix_rq_ena_dis(struct roc_nix_rq *rq, bool enable) rc = nix_rq_ena_dis(&nix->dev, rq, enable); nix_rq_vwqe_flush(rq, nix->vwqe_interval); + if (rc) + return rc; + /* Check for meta aura if RQ is enabled */ + if (enable && nix->need_meta_aura) + rc = roc_nix_inl_meta_aura_check(rq); return rc; } @@ -556,6 +561,13 @@ roc_nix_rq_init(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena) /* Update aura buf type to indicate its use */ nix_rq_aura_buf_type_update(rq, true); + /* Check for meta aura if RQ is enabled */ + if (ena && nix->need_meta_aura) { + rc = roc_nix_inl_meta_aura_check(rq); + if (rc) + return rc; + } + return nix_tel_node_add_rq(rq); } @@ -594,6 +606,13 @@ roc_nix_rq_modify(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena) /* Update aura attribute to indicate its use */ nix_rq_aura_buf_type_update(rq, true); + /* Check for meta aura if RQ is enabled */ + if (ena && nix->need_meta_aura) { + rc = roc_nix_inl_meta_aura_check(rq); + if (rc) + return rc; + } + return nix_tel_node_add_rq(rq); } diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 6f3de2a..276fec3 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -95,6 +95,7 @@ INTERNAL { roc_idev_npa_maxpools_set; roc_idev_npa_nix_get; roc_idev_num_lmtlines_get; + roc_idev_nix_inl_meta_aura_get; roc_model; roc_se_auth_key_set; roc_se_ciph_key_set; @@ -156,7 +157,10 @@ INTERNAL { roc_nix_inl_inb_sa_sz; roc_nix_inl_inb_tag_update; roc_nix_inl_inb_fini; + roc_nix_inl_inb_set; roc_nix_inb_is_with_inl_dev; + roc_nix_inl_meta_aura_check; + roc_nix_inl_meta_pool_cb_register; roc_nix_inb_mode_set; roc_nix_inl_outb_fini; roc_nix_inl_outb_init; From patchwork Tue Aug 9 18:48:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 114771 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AA0CAA04FD; Tue, 9 Aug 2022 20:50:28 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 95A2042BF0; Tue, 9 Aug 2022 20:50:28 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id EC94A42BE6 for ; Tue, 9 Aug 2022 20:50:26 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 279D65ar015667 for ; Tue, 9 Aug 2022 11:50:26 -0700 DKIM-Signature: v=1; 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Tue, 9 Aug 2022 11:50:24 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id B3C543F710A; Tue, 9 Aug 2022 11:50:11 -0700 (PDT) From: Nithin Dabilpuram To: Pavan Nikhilesh , Shijith Thotton , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 11/23] net/cnxk: support for zero aura for inline meta Date: Wed, 10 Aug 2022 00:18:55 +0530 Message-ID: <20220809184908.24030-11-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220809184908.24030-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: LugDM89iE3ddNJ7pkX4AJo7mT2IQ7S9H X-Proofpoint-GUID: LugDM89iE3ddNJ7pkX4AJo7mT2IQ7S9H X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for zero aura for inline meta pkts and register callback to ROC to create meta pool via mempool. Also add devargs to override meta buffer count and size. Signed-off-by: Nithin Dabilpuram --- drivers/event/cnxk/cn10k_eventdev.c | 8 ++- drivers/event/cnxk/cn10k_worker.h | 32 ++++++----- drivers/event/cnxk/cnxk_eventdev.h | 1 + drivers/event/cnxk/cnxk_eventdev_adptr.c | 2 +- drivers/net/cnxk/cn10k_ethdev.c | 8 ++- drivers/net/cnxk/cn10k_ethdev.h | 2 +- drivers/net/cnxk/cn10k_rx.h | 35 +++++++----- drivers/net/cnxk/cnxk_ethdev.c | 3 + drivers/net/cnxk/cnxk_ethdev.h | 2 + drivers/net/cnxk/cnxk_ethdev_sec.c | 97 +++++++++++++++++++++++++++++++- 10 files changed, 154 insertions(+), 36 deletions(-) diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index db61606..0651b2d 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -694,7 +694,7 @@ cn10k_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev, } static void -cn10k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem) +cn10k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem, uint64_t meta_aura) { struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); int i; @@ -703,6 +703,8 @@ cn10k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem) struct cn10k_sso_hws *ws = event_dev->data->ports[i]; ws->lookup_mem = lookup_mem; ws->tstamp = dev->tstamp; + if (meta_aura) + ws->meta_aura = meta_aura; } } @@ -713,6 +715,7 @@ cn10k_sso_rx_adapter_queue_add( const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) { struct cn10k_eth_rxq *rxq; + uint64_t meta_aura; void *lookup_mem; int rc; @@ -726,7 +729,8 @@ cn10k_sso_rx_adapter_queue_add( return -EINVAL; rxq = eth_dev->data->rx_queues[0]; lookup_mem = rxq->lookup_mem; - cn10k_sso_set_priv_mem(event_dev, lookup_mem); + meta_aura = rxq->meta_aura; + cn10k_sso_set_priv_mem(event_dev, lookup_mem, meta_aura); cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev); return 0; diff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h index db56d96..47ce423 100644 --- a/drivers/event/cnxk/cn10k_worker.h +++ b/drivers/event/cnxk/cn10k_worker.h @@ -127,12 +127,14 @@ cn10k_sso_process_tstamp(uint64_t u64, uint64_t mbuf, } static __rte_always_inline void -cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags, - void *lookup_mem, void *tstamp, uintptr_t lbase) +cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags, struct cn10k_sso_hws *ws) { uint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM; + struct cnxk_timesync_info *tstamp = ws->tstamp[port_id]; + void *lookup_mem = ws->lookup_mem; + uintptr_t lbase = ws->lmt_base; struct rte_event_vector *vec; - uint64_t aura_handle, laddr; + uint64_t meta_aura, laddr; uint16_t nb_mbufs, non_vec; uint16_t lmt_id, d_off; struct rte_mbuf **wqe; @@ -153,25 +155,31 @@ cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags, if (flags & NIX_RX_OFFLOAD_TSTAMP_F && tstamp) mbuf_init |= 8; + meta_aura = ws->meta_aura; nb_mbufs = RTE_ALIGN_FLOOR(vec->nb_elem, NIX_DESCS_PER_LOOP); nb_mbufs = cn10k_nix_recv_pkts_vector(&mbuf_init, wqe, nb_mbufs, - flags | NIX_RX_VWQE_F, lookup_mem, - tstamp, lbase); + flags | NIX_RX_VWQE_F, + lookup_mem, tstamp, + lbase, meta_aura); wqe += nb_mbufs; non_vec = vec->nb_elem - nb_mbufs; if (flags & NIX_RX_OFFLOAD_SECURITY_F && non_vec) { + uint64_t sg_w1; + mbuf = (struct rte_mbuf *)((uintptr_t)wqe[0] - sizeof(struct rte_mbuf)); /* Pick first mbuf's aura handle assuming all * mbufs are from a vec and are from same RQ. */ - aura_handle = mbuf->pool->pool_id; + meta_aura = ws->meta_aura; + if (!meta_aura) + meta_aura = mbuf->pool->pool_id; ROC_LMT_BASE_ID_GET(lbase, lmt_id); laddr = lbase; laddr += 8; - d_off = ((uintptr_t)mbuf->buf_addr - (uintptr_t)mbuf); - d_off += (mbuf_init & 0xFFFF); + sg_w1 = *(uint64_t *)(((uintptr_t)wqe[0]) + 72); + d_off = sg_w1 - (uintptr_t)mbuf; sa_base = cnxk_nix_sa_base_get(mbuf_init >> 48, lookup_mem); sa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1); } @@ -208,7 +216,7 @@ cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags, /* Free remaining meta buffers if any */ if (flags & NIX_RX_OFFLOAD_SECURITY_F && loff) { - nix_sec_flush_meta(laddr, lmt_id, loff, aura_handle); + nix_sec_flush_meta(laddr, lmt_id, loff, meta_aura); plt_io_wmb(); } } @@ -241,8 +249,7 @@ cn10k_sso_hws_post_process(struct cn10k_sso_hws *ws, uint64_t *u64, uint64_t cq_w5; m = (struct rte_mbuf *)mbuf; - d_off = (uintptr_t)(m->buf_addr) - (uintptr_t)m; - d_off += RTE_PKTMBUF_HEADROOM; + d_off = (*(uint64_t *)(u64[1] + 72)) - (uintptr_t)m; cq_w1 = *(uint64_t *)(u64[1] + 8); cq_w5 = *(uint64_t *)(u64[1] + 40); @@ -273,8 +280,7 @@ cn10k_sso_hws_post_process(struct cn10k_sso_hws *ws, uint64_t *u64, vwqe_hdr = ((vwqe_hdr >> 64) & 0xFFF) | BIT_ULL(31) | ((vwqe_hdr & 0xFFFF) << 48) | ((uint64_t)port << 32); *(uint64_t *)u64[1] = (uint64_t)vwqe_hdr; - cn10k_process_vwqe(u64[1], port, flags, ws->lookup_mem, - ws->tstamp[port], ws->lmt_base); + cn10k_process_vwqe(u64[1], port, flags, ws); /* Mark vector mempool object as get */ RTE_MEMPOOL_CHECK_COOKIES(rte_mempool_from_obj((void *)u64[1]), (void **)&u64[1], 1, 1); diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index fae4484..d61e60d 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -148,6 +148,7 @@ struct cn10k_sso_hws { uint8_t hws_id; /* PTP timestamp */ struct cnxk_timesync_info **tstamp; + uint64_t meta_aura; /* Add Work Fastpath data */ uint64_t xaq_lmt __rte_cache_aligned; uint64_t *fc_mem; diff --git a/drivers/event/cnxk/cnxk_eventdev_adptr.c b/drivers/event/cnxk/cnxk_eventdev_adptr.c index 7937cad..5f51c50 100644 --- a/drivers/event/cnxk/cnxk_eventdev_adptr.c +++ b/drivers/event/cnxk/cnxk_eventdev_adptr.c @@ -194,7 +194,7 @@ cnxk_sso_rx_adapter_vwqe_enable(struct cnxk_eth_dev *cnxk_eth_dev, rq->vwqe_ena = 1; rq->vwqe_first_skip = 0; - rq->vwqe_aura_handle = roc_npa_aura_handle_to_aura(vmp->pool_id); + rq->vwqe_aura_handle = vmp->pool_id; rq->vwqe_max_sz_exp = rte_log2_u32(sz); rq->vwqe_wait_tmo = tmo_ns / diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c index 80c5c0e..e8faeeb 100644 --- a/drivers/net/cnxk/cn10k_ethdev.c +++ b/drivers/net/cnxk/cn10k_ethdev.c @@ -282,9 +282,13 @@ cn10k_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, rxq->lmt_base = dev->nix.lmt_base; rxq->sa_base = roc_nix_inl_inb_sa_base_get(&dev->nix, dev->inb.inl_dev); + rxq->meta_aura = rq->meta_aura_handle; + rxq_sp = cnxk_eth_rxq_to_sp(rxq); + /* Assume meta packet from normal aura if meta aura is not setup + */ + if (!rxq->meta_aura) + rxq->meta_aura = rxq_sp->qconf.mp->pool_id; } - rxq_sp = cnxk_eth_rxq_to_sp(rxq); - rxq->aura_handle = rxq_sp->qconf.mp->pool_id; /* Lookup mem */ rxq->lookup_mem = cnxk_nix_fastpath_lookup_mem_get(); diff --git a/drivers/net/cnxk/cn10k_ethdev.h b/drivers/net/cnxk/cn10k_ethdev.h index acfdbb6..d0a5b13 100644 --- a/drivers/net/cnxk/cn10k_ethdev.h +++ b/drivers/net/cnxk/cn10k_ethdev.h @@ -39,7 +39,7 @@ struct cn10k_eth_rxq { uint16_t data_off; uint64_t sa_base; uint64_t lmt_base; - uint64_t aura_handle; + uint64_t meta_aura; uint16_t rq; struct cnxk_timesync_info *tstamp; } __plt_cache_aligned; diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h index 0f8790b..2cd297e 100644 --- a/drivers/net/cnxk/cn10k_rx.h +++ b/drivers/net/cnxk/cn10k_rx.h @@ -877,7 +877,7 @@ cn10k_nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts, nb_pkts = nix_rx_nb_pkts(rxq, wdata, pkts, qmask); if (flags & NIX_RX_OFFLOAD_SECURITY_F) { - aura_handle = rxq->aura_handle; + aura_handle = rxq->meta_aura; sa_base = rxq->sa_base; sa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1); ROC_LMT_BASE_ID_GET(lbase, lmt_id); @@ -984,7 +984,7 @@ static __rte_always_inline uint16_t cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, const uint16_t flags, void *lookup_mem, struct cnxk_timesync_info *tstamp, - uintptr_t lmt_base) + uintptr_t lmt_base, uint64_t meta_aura) { struct cn10k_eth_rxq *rxq = args; const uint64_t mbuf_initializer = (flags & NIX_RX_VWQE_F) ? @@ -1003,10 +1003,10 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, uint64x2_t rearm2 = vdupq_n_u64(mbuf_initializer); uint64x2_t rearm3 = vdupq_n_u64(mbuf_initializer); struct rte_mbuf *mbuf0, *mbuf1, *mbuf2, *mbuf3; - uint64_t aura_handle, lbase, laddr; uint8_t loff = 0, lnum = 0, shft = 0; uint8x16_t f0, f1, f2, f3; uint16_t lmt_id, d_off; + uint64_t lbase, laddr; uint16_t packets = 0; uint16_t pkts_left; uintptr_t sa_base; @@ -1035,6 +1035,7 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, if (flags & NIX_RX_OFFLOAD_SECURITY_F) { if (flags & NIX_RX_VWQE_F) { + uint64_t sg_w1; uint16_t port; mbuf0 = (struct rte_mbuf *)((uintptr_t)mbufs[0] - @@ -1042,10 +1043,15 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, /* Pick first mbuf's aura handle assuming all * mbufs are from a vec and are from same RQ. */ - aura_handle = mbuf0->pool->pool_id; + if (!meta_aura) + meta_aura = mbuf0->pool->pool_id; /* Calculate offset from mbuf to actual data area */ - d_off = ((uintptr_t)mbuf0->buf_addr - (uintptr_t)mbuf0); - d_off += (mbuf_initializer & 0xFFFF); + /* Zero aura's first skip i.e mbuf setup might not match the actual + * offset as first skip is taken from second pass RQ. So compute + * using diff b/w first SG pointer and mbuf addr. + */ + sg_w1 = *(uint64_t *)((uintptr_t)mbufs[0] + 72); + d_off = (sg_w1 - (uint64_t)mbuf0); /* Get SA Base from lookup tbl using port_id */ port = mbuf_initializer >> 48; @@ -1053,7 +1059,7 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, lbase = lmt_base; } else { - aura_handle = rxq->aura_handle; + meta_aura = rxq->meta_aura; d_off = rxq->data_off; sa_base = rxq->sa_base; lbase = rxq->lmt_base; @@ -1721,7 +1727,7 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, /* Update aura handle */ *(uint64_t *)(laddr - 8) = (((uint64_t)(15 & 0x1) << 32) | - roc_npa_aura_handle_to_aura(aura_handle)); + roc_npa_aura_handle_to_aura(meta_aura)); loff = loff - 15; shft += 3; @@ -1744,14 +1750,14 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, /* Update aura handle */ *(uint64_t *)(laddr - 8) = (((uint64_t)(loff & 0x1) << 32) | - roc_npa_aura_handle_to_aura(aura_handle)); + roc_npa_aura_handle_to_aura(meta_aura)); data = (data & ~(0x7UL << shft)) | (((uint64_t)loff >> 1) << shft); /* Send up to 16 lmt lines of pointers */ nix_sec_flush_meta_burst(lmt_id, data, lnum + 1, - aura_handle); + meta_aura); rte_io_wmb(); lnum = 0; loff = 0; @@ -1769,13 +1775,13 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, /* Update aura handle */ *(uint64_t *)(laddr - 8) = (((uint64_t)(loff & 0x1) << 32) | - roc_npa_aura_handle_to_aura(aura_handle)); + roc_npa_aura_handle_to_aura(meta_aura)); data = (data & ~(0x7UL << shft)) | (((uint64_t)loff >> 1) << shft); /* Send up to 16 lmt lines of pointers */ - nix_sec_flush_meta_burst(lmt_id, data, lnum + 1, aura_handle); + nix_sec_flush_meta_burst(lmt_id, data, lnum + 1, meta_aura); if (flags & NIX_RX_VWQE_F) plt_io_wmb(); } @@ -1803,7 +1809,7 @@ static inline uint16_t cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, const uint16_t flags, void *lookup_mem, struct cnxk_timesync_info *tstamp, - uintptr_t lmt_base) + uintptr_t lmt_base, uint64_t meta_aura) { RTE_SET_USED(args); RTE_SET_USED(mbufs); @@ -1812,6 +1818,7 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, RTE_SET_USED(lookup_mem); RTE_SET_USED(tstamp); RTE_SET_USED(lmt_base); + RTE_SET_USED(meta_aura); return 0; } @@ -2038,7 +2045,7 @@ NIX_RX_FASTPATH_MODES void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts) \ { \ return cn10k_nix_recv_pkts_vector(rx_queue, rx_pkts, pkts, \ - (flags), NULL, NULL, 0); \ + (flags), NULL, NULL, 0, 0); \ } #define NIX_RX_RECV_VEC_MSEG(fn, flags) \ diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index b3af2f8..02416ad 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -1732,6 +1732,9 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev) roc_nix_mac_link_info_get_cb_register(nix, cnxk_eth_dev_link_status_get_cb); + /* Register callback for inline meta pool create */ + roc_nix_inl_meta_pool_cb_register(cnxk_nix_inl_meta_pool_cb); + dev->eth_dev = eth_dev; dev->configured = 0; dev->ptype_disable = 0; diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index 4cb7c9e..be5cecd 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -641,6 +641,8 @@ struct cnxk_eth_sec_sess *cnxk_eth_sec_sess_get_by_spi(struct cnxk_eth_dev *dev, struct cnxk_eth_sec_sess * cnxk_eth_sec_sess_get_by_sess(struct cnxk_eth_dev *dev, struct rte_security_session *sess); +int cnxk_nix_inl_meta_pool_cb(uint64_t *aura_handle, uint32_t buf_sz, uint32_t nb_bufs, + bool destroy); /* Other private functions */ int nix_recalc_mtu(struct rte_eth_dev *eth_dev); diff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c b/drivers/net/cnxk/cnxk_ethdev_sec.c index 1de3454..9304b14 100644 --- a/drivers/net/cnxk/cnxk_ethdev_sec.c +++ b/drivers/net/cnxk/cnxk_ethdev_sec.c @@ -4,10 +4,14 @@ #include +#define CNXK_NIX_INL_META_POOL_NAME "NIX_INL_META_POOL" + #define CNXK_NIX_INL_SELFTEST "selftest" #define CNXK_NIX_INL_IPSEC_IN_MIN_SPI "ipsec_in_min_spi" #define CNXK_NIX_INL_IPSEC_IN_MAX_SPI "ipsec_in_max_spi" #define CNXK_INL_CPT_CHANNEL "inl_cpt_channel" +#define CNXK_NIX_INL_NB_META_BUFS "nb_meta_bufs" +#define CNXK_NIX_INL_META_BUF_SZ "meta_buf_sz" struct inl_cpt_channel { bool is_multi_channel; @@ -29,6 +33,85 @@ bitmap_ctzll(uint64_t slab) } int +cnxk_nix_inl_meta_pool_cb(uint64_t *aura_handle, uint32_t buf_sz, uint32_t nb_bufs, bool destroy) +{ + const char *mp_name = CNXK_NIX_INL_META_POOL_NAME; + struct rte_pktmbuf_pool_private mbp_priv; + struct npa_aura_s *aura; + struct rte_mempool *mp; + uint16_t first_skip; + int rc; + + /* Destroy the mempool if requested */ + if (destroy) { + mp = rte_mempool_lookup(mp_name); + if (!mp) + return -ENOENT; + + if (mp->pool_id != *aura_handle) { + plt_err("Meta pool aura mismatch"); + return -EINVAL; + } + + plt_free(mp->pool_config); + rte_mempool_free(mp); + + *aura_handle = 0; + return 0; + } + + /* Need to make it similar to rte_pktmbuf_pool() for sake of OOP + * support. + */ + mp = rte_mempool_create_empty(mp_name, nb_bufs, buf_sz, 0, + sizeof(struct rte_pktmbuf_pool_private), + SOCKET_ID_ANY, 0); + if (!mp) { + plt_err("Failed to create inline meta pool"); + return -EIO; + } + + /* Indicate to allocate zero aura */ + aura = plt_zmalloc(sizeof(struct npa_aura_s), 0); + if (!aura) { + rc = -ENOMEM; + goto free_mp; + } + aura->ena = 1; + aura->pool_addr = 0x0; + + rc = rte_mempool_set_ops_byname(mp, rte_mbuf_platform_mempool_ops(), + aura); + if (rc) { + plt_err("Failed to setup mempool ops for meta, rc=%d", rc); + goto free_aura; + } + + /* Init mempool private area */ + first_skip = sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM; + memset(&mbp_priv, 0, sizeof(mbp_priv)); + mbp_priv.mbuf_data_room_size = (buf_sz - first_skip + + RTE_PKTMBUF_HEADROOM); + rte_pktmbuf_pool_init(mp, &mbp_priv); + + /* Populate buffer */ + rc = rte_mempool_populate_default(mp); + if (rc < 0) { + plt_err("Failed to create inline meta pool, rc=%d", rc); + goto free_aura; + } + + rte_mempool_obj_iter(mp, rte_pktmbuf_init, NULL); + *aura_handle = mp->pool_id; + return 0; +free_aura: + plt_free(aura); +free_mp: + rte_mempool_free(mp); + return rc; +} + +int cnxk_eth_outb_sa_idx_get(struct cnxk_eth_dev *dev, uint32_t *idx_p, uint32_t spi) { @@ -128,7 +211,7 @@ struct rte_security_ops cnxk_eth_sec_ops = { }; static int -parse_ipsec_in_spi_range(const char *key, const char *value, void *extra_args) +parse_val_u32(const char *key, const char *value, void *extra_args) { RTE_SET_USED(key); uint32_t val; @@ -184,6 +267,8 @@ nix_inl_parse_devargs(struct rte_devargs *devargs, uint32_t ipsec_in_min_spi = 0; struct inl_cpt_channel cpt_channel; struct rte_kvargs *kvlist; + uint32_t nb_meta_bufs = 0; + uint32_t meta_buf_sz = 0; uint8_t selftest = 0; memset(&cpt_channel, 0, sizeof(cpt_channel)); @@ -198,11 +283,15 @@ nix_inl_parse_devargs(struct rte_devargs *devargs, rte_kvargs_process(kvlist, CNXK_NIX_INL_SELFTEST, &parse_selftest, &selftest); rte_kvargs_process(kvlist, CNXK_NIX_INL_IPSEC_IN_MIN_SPI, - &parse_ipsec_in_spi_range, &ipsec_in_min_spi); + &parse_val_u32, &ipsec_in_min_spi); rte_kvargs_process(kvlist, CNXK_NIX_INL_IPSEC_IN_MAX_SPI, - &parse_ipsec_in_spi_range, &ipsec_in_max_spi); + &parse_val_u32, &ipsec_in_max_spi); rte_kvargs_process(kvlist, CNXK_INL_CPT_CHANNEL, &parse_inl_cpt_channel, &cpt_channel); + rte_kvargs_process(kvlist, CNXK_NIX_INL_NB_META_BUFS, &parse_val_u32, + &nb_meta_bufs); + rte_kvargs_process(kvlist, CNXK_NIX_INL_META_BUF_SZ, &parse_val_u32, + &meta_buf_sz); rte_kvargs_free(kvlist); null_devargs: @@ -212,6 +301,8 @@ nix_inl_parse_devargs(struct rte_devargs *devargs, inl_dev->channel = cpt_channel.channel; inl_dev->chan_mask = cpt_channel.mask; inl_dev->is_multi_channel = cpt_channel.is_multi_channel; + inl_dev->nb_meta_bufs = nb_meta_bufs; + inl_dev->meta_buf_sz = meta_buf_sz; return 0; exit: return -EINVAL; From patchwork Tue Aug 9 18:48:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 114772 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D7C8CA04FD; Tue, 9 Aug 2022 20:50:35 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EA24D42BDC; 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Tue, 09 Aug 2022 11:50:32 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 9 Aug 2022 11:50:30 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 9 Aug 2022 11:50:31 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id C70BD3F7125; Tue, 9 Aug 2022 11:50:14 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ankur Dwivedi , Anoob Joseph , Tejasree Kondoj CC: , , Vidya Sagar Velumuri Subject: [PATCH 12/23] common/cnxk: avoid the use of platform specific APIs Date: Wed, 10 Aug 2022 00:18:56 +0530 Message-ID: <20220809184908.24030-12-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220809184908.24030-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: yABMMoVyV_Y9T4686me31rlnmSU3-jt_ X-Proofpoint-GUID: yABMMoVyV_Y9T4686me31rlnmSU3-jt_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Vidya Sagar Velumuri Replace the use of platform specific APIs with platform independent APIs. Signed-off-by: Vidya Sagar Velumuri --- drivers/common/cnxk/roc_cpt.c | 8 ++++---- drivers/common/cnxk/roc_cpt.h | 2 +- drivers/crypto/cnxk/cn9k_ipsec.c | 8 ++++---- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index d607bde..6f0ee44 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -998,7 +998,7 @@ roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr, void *sa_cptr, } int -roc_on_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa, uint8_t opcode, +roc_on_cpt_ctx_write(struct roc_cpt_lf *lf, uint64_t sa, uint8_t opcode, uint16_t ctx_len, uint8_t egrp) { union cpt_res_s res, *hw_res; @@ -1019,9 +1019,9 @@ roc_on_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa, uint8_t opcode, inst.w4.s.param1 = 0; inst.w4.s.param2 = 0; inst.w4.s.dlen = ctx_len; - inst.dptr = rte_mempool_virt2iova(sa); + inst.dptr = sa; inst.rptr = 0; - inst.w7.s.cptr = rte_mempool_virt2iova(sa); + inst.w7.s.cptr = sa; inst.w7.s.egrp = egrp; inst.w0.u64 = 0; @@ -1029,7 +1029,7 @@ roc_on_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa, uint8_t opcode, inst.w3.u64 = 0; inst.res_addr = (uintptr_t)hw_res; - rte_io_wmb(); + plt_io_wmb(); do { /* Copy CPT command to LMTLINE */ diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index 4e3a078..6953f2b 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -173,7 +173,7 @@ void __roc_api roc_cpt_parse_hdr_dump(const struct cpt_parse_hdr_s *cpth); int __roc_api roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr, void *sa_cptr, uint16_t sa_len); -int __roc_api roc_on_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa, +int __roc_api roc_on_cpt_ctx_write(struct roc_cpt_lf *lf, uint64_t sa, uint8_t opcode, uint16_t ctx_len, uint8_t egrp); #endif /* _ROC_CPT_H_ */ diff --git a/drivers/crypto/cnxk/cn9k_ipsec.c b/drivers/crypto/cnxk/cn9k_ipsec.c index 6d26b0c..78c181b 100644 --- a/drivers/crypto/cnxk/cn9k_ipsec.c +++ b/drivers/crypto/cnxk/cn9k_ipsec.c @@ -82,8 +82,8 @@ cn9k_ipsec_outb_sa_create(struct cnxk_cpt_qp *qp, ctx_len = ret; opcode = ROC_IE_ON_MAJOR_OP_WRITE_IPSEC_OUTBOUND; egrp = roc_cpt->eng_grp[CPT_ENG_TYPE_IE]; - ret = roc_on_cpt_ctx_write(&qp->lf, (void *)&sa->out_sa, opcode, - ctx_len, egrp); + ret = roc_on_cpt_ctx_write(&qp->lf, rte_mempool_virt2iova(&sa->out_sa), + opcode, ctx_len, egrp); if (ret) return ret; @@ -174,8 +174,8 @@ cn9k_ipsec_inb_sa_create(struct cnxk_cpt_qp *qp, ctx_len = ret; opcode = ROC_IE_ON_MAJOR_OP_WRITE_IPSEC_INBOUND; egrp = roc_cpt->eng_grp[CPT_ENG_TYPE_IE]; - ret = roc_on_cpt_ctx_write(&qp->lf, (void *)&sa->in_sa, opcode, ctx_len, - egrp); + ret = roc_on_cpt_ctx_write(&qp->lf, rte_mempool_virt2iova(&sa->in_sa), + opcode, ctx_len, egrp); if (ret) return ret; From patchwork Tue Aug 9 18:48:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 114775 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E281FA04FD; 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Tue, 09 Aug 2022 11:50:34 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 9 Aug 2022 11:50:32 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 9 Aug 2022 11:50:32 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id E285A5B699B; Tue, 9 Aug 2022 11:50:18 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ankur Dwivedi , Anoob Joseph , Tejasree Kondoj , "Pavan Nikhilesh" , Shijith Thotton CC: , , Vidya Sagar Velumuri Subject: [PATCH 13/23] net/cnxk: use full context IPsec structures in fp Date: Wed, 10 Aug 2022 00:18:57 +0530 Message-ID: <20220809184908.24030-13-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220809184908.24030-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: IfVGbvpQcFI4iFo_FeRtLChhp25pbNWt X-Proofpoint-ORIG-GUID: IfVGbvpQcFI4iFo_FeRtLChhp25pbNWt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Vidya Sagar Velumuri Use the Full context SA structures and command in IPsec fast path. For inline outbound, populate CPT instruction as per Full context. Add new macros and functions with respect to Full context. Populate wqe ptr in CPT instruction with proper offset from mbuf. Add option to override outbound inline sa iv for debug Update mbuf len based on IP version in rx post process purposes via environment variable. User can set env variable as: export ETH_SEC_IV_OVR="0x0, 0x0,..." Signed-off-by: Vidya Sagar Velumuri Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/cnxk_security.c | 8 +- drivers/common/cnxk/roc_cpt.c | 9 ++- drivers/common/cnxk/roc_cpt.h | 8 +- drivers/common/cnxk/roc_ie_on.h | 6 ++ drivers/common/cnxk/roc_nix_inl.c | 33 +++++--- drivers/common/cnxk/roc_nix_inl.h | 46 +++++++++++ drivers/common/cnxk/roc_nix_inl_dev.c | 2 +- drivers/crypto/cnxk/cn9k_ipsec.c | 8 +- drivers/event/cnxk/cn9k_worker.h | 48 +++++++----- drivers/net/cnxk/cn9k_ethdev.h | 3 + drivers/net/cnxk/cn9k_ethdev_sec.c | 111 ++++++++++++++++++++++----- drivers/net/cnxk/cn9k_rx.h | 43 +++++++---- drivers/net/cnxk/cnxk_ethdev_sec_telemetry.c | 32 +++----- 13 files changed, 255 insertions(+), 102 deletions(-) diff --git a/drivers/common/cnxk/cnxk_security.c b/drivers/common/cnxk/cnxk_security.c index dca8742..89ac900 100644 --- a/drivers/common/cnxk/cnxk_security.c +++ b/drivers/common/cnxk/cnxk_security.c @@ -1242,7 +1242,9 @@ cnxk_on_ipsec_outb_sa_create(struct rte_security_ipsec_xform *ipsec, ctx_len += sizeof(template->ip4); ip4->version_ihl = RTE_IPV4_VHL_DEF; - ip4->time_to_live = ipsec->tunnel.ipv4.ttl; + ip4->time_to_live = ipsec->tunnel.ipv4.ttl ? + ipsec->tunnel.ipv4.ttl : + 0x40; ip4->type_of_service |= (ipsec->tunnel.ipv4.dscp << 2); if (ipsec->tunnel.ipv4.df) frag_off |= RTE_IPV4_HDR_DF_FLAG; @@ -1275,7 +1277,9 @@ cnxk_on_ipsec_outb_sa_create(struct rte_security_ipsec_xform *ipsec, ((ipsec->tunnel.ipv6.flabel << RTE_IPV6_HDR_FL_SHIFT) & RTE_IPV6_HDR_FL_MASK)); - ip6->hop_limits = ipsec->tunnel.ipv6.hlimit; + ip6->hop_limits = ipsec->tunnel.ipv6.hlimit ? + ipsec->tunnel.ipv6.hlimit : + 0x40; memcpy(&ip6->src_addr, &ipsec->tunnel.ipv6.src_addr, sizeof(struct in6_addr)); memcpy(&ip6->dst_addr, &ipsec->tunnel.ipv6.dst_addr, diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index 6f0ee44..8fc072b 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -277,7 +277,7 @@ roc_cpt_inline_ipsec_inb_cfg_read(struct roc_cpt *roc_cpt, int roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt, uint16_t param1, - uint16_t param2) + uint16_t param2, uint16_t opcode) { struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt); struct cpt_rx_inline_lf_cfg_msg *req; @@ -292,6 +292,7 @@ roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt, uint16_t param1, req->sso_pf_func = idev_sso_pffunc_get(); req->param1 = param1; req->param2 = param2; + req->opcode = opcode; return mbox_process(mbox); } @@ -998,7 +999,7 @@ roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr, void *sa_cptr, } int -roc_on_cpt_ctx_write(struct roc_cpt_lf *lf, uint64_t sa, uint8_t opcode, +roc_on_cpt_ctx_write(struct roc_cpt_lf *lf, uint64_t sa, bool inb, uint16_t ctx_len, uint8_t egrp) { union cpt_res_s res, *hw_res; @@ -1014,7 +1015,9 @@ roc_on_cpt_ctx_write(struct roc_cpt_lf *lf, uint64_t sa, uint8_t opcode, hw_res->cn9k.compcode = CPT_COMP_NOT_DONE; - inst.w4.s.opcode_major = opcode; + inst.w4.s.opcode_major = ROC_IE_ON_MAJOR_OP_WRITE_IPSEC_OUTBOUND; + if (inb) + inst.w4.s.opcode_major = ROC_IE_ON_MAJOR_OP_WRITE_IPSEC_INBOUND; inst.w4.s.opcode_minor = ctx_len >> 3; inst.w4.s.param1 = 0; inst.w4.s.param2 = 0; diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index 6953f2b..9a79998 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -161,7 +161,8 @@ int __roc_api roc_cpt_inline_ipsec_cfg(struct dev *dev, uint8_t slot, int __roc_api roc_cpt_inline_ipsec_inb_cfg_read( struct roc_cpt *roc_cpt, struct nix_inline_ipsec_cfg *inb_cfg); int __roc_api roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt, - uint16_t param1, uint16_t param2); + uint16_t param1, uint16_t param2, + uint16_t opcode); int __roc_api roc_cpt_afs_print(struct roc_cpt *roc_cpt); int __roc_api roc_cpt_lfs_print(struct roc_cpt *roc_cpt); void __roc_api roc_cpt_iq_disable(struct roc_cpt_lf *lf); @@ -173,7 +174,6 @@ void __roc_api roc_cpt_parse_hdr_dump(const struct cpt_parse_hdr_s *cpth); int __roc_api roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr, void *sa_cptr, uint16_t sa_len); -int __roc_api roc_on_cpt_ctx_write(struct roc_cpt_lf *lf, uint64_t sa, - uint8_t opcode, uint16_t ctx_len, - uint8_t egrp); +int __roc_api roc_on_cpt_ctx_write(struct roc_cpt_lf *lf, uint64_t sa, bool inb, + uint16_t ctx_len, uint8_t egrp); #endif /* _ROC_CPT_H_ */ diff --git a/drivers/common/cnxk/roc_ie_on.h b/drivers/common/cnxk/roc_ie_on.h index 2d93cb6..961d5fc 100644 --- a/drivers/common/cnxk/roc_ie_on.h +++ b/drivers/common/cnxk/roc_ie_on.h @@ -13,6 +13,12 @@ #define ROC_IE_ON_MAJOR_OP_PROCESS_OUTBOUND_IPSEC 0x23 #define ROC_IE_ON_MAJOR_OP_PROCESS_INBOUND_IPSEC 0x24 +#define ROC_IE_ON_INB_MAX_CTX_LEN 34UL +#define ROC_IE_ON_INB_IKEV2_SINGLE_SA_SUPPORT (1 << 12) +#define ROC_IE_ON_OUTB_MAX_CTX_LEN 31UL +#define ROC_IE_ON_OUTB_IKEV2_SINGLE_SA_SUPPORT (1 << 9) +#define ROC_IE_ON_OUTB_PER_PKT_IV (1 << 11) + /* Ucode completion codes */ enum roc_ie_on_ucc_ipsec { ROC_IE_ON_UCC_SUCCESS = 0, diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index 507a153..be0b806 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -8,11 +8,11 @@ uint32_t soft_exp_consumer_cnt; roc_nix_inl_meta_pool_cb_t meta_pool_cb; -PLT_STATIC_ASSERT(ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ == - 1UL << ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ_LOG2); -PLT_STATIC_ASSERT(ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ == 512); -PLT_STATIC_ASSERT(ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ == - 1UL << ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ_LOG2); +PLT_STATIC_ASSERT(ROC_NIX_INL_ON_IPSEC_INB_SA_SZ == + 1UL << ROC_NIX_INL_ON_IPSEC_INB_SA_SZ_LOG2); +PLT_STATIC_ASSERT(ROC_NIX_INL_ON_IPSEC_INB_SA_SZ == 1024); +PLT_STATIC_ASSERT(ROC_NIX_INL_ON_IPSEC_OUTB_SA_SZ == + 1UL << ROC_NIX_INL_ON_IPSEC_OUTB_SA_SZ_LOG2); PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ == 1UL << ROC_NIX_INL_OT_IPSEC_INB_SA_SZ_LOG2); PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ == 1024); @@ -184,7 +184,7 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix) /* CN9K SA size is different */ if (roc_model_is_cn9k()) - inb_sa_sz = ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ; + inb_sa_sz = ROC_NIX_INL_ON_IPSEC_INB_SA_SZ; else inb_sa_sz = ROC_NIX_INL_OT_IPSEC_INB_SA_SZ; @@ -422,7 +422,9 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix) struct nix *nix = roc_nix_to_nix_priv(roc_nix); struct idev_cfg *idev = idev_get_cfg(); struct roc_cpt *roc_cpt; + uint16_t opcode; uint16_t param1; + uint16_t param2; int rc; if (idev == NULL) @@ -439,17 +441,23 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix) } if (roc_model_is_cn9k()) { - param1 = ROC_ONF_IPSEC_INB_MAX_L2_SZ; + param1 = (ROC_ONF_IPSEC_INB_MAX_L2_SZ >> 3) & 0xf; + param2 = ROC_IE_ON_INB_IKEV2_SINGLE_SA_SUPPORT; + opcode = + ((ROC_IE_ON_INB_MAX_CTX_LEN << 8) | + (ROC_IE_ON_MAJOR_OP_PROCESS_INBOUND_IPSEC | (1 << 6))); } else { union roc_ot_ipsec_inb_param1 u; u.u16 = 0; u.s.esp_trailer_disable = 1; param1 = u.u16; + param2 = 0; + opcode = (ROC_IE_OT_MAJOR_OP_PROCESS_INBOUND_IPSEC | (1 << 6)); } /* Do onetime Inbound Inline config in CPTPF */ - rc = roc_cpt_inline_ipsec_inb_cfg(roc_cpt, param1, 0); + rc = roc_cpt_inline_ipsec_inb_cfg(roc_cpt, param1, param2, opcode); if (rc && rc != -EEXIST) { plt_err("Failed to setup inbound lf, rc=%d", rc); return rc; @@ -605,7 +613,7 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix) /* CN9K SA size is different */ if (roc_model_is_cn9k()) - sa_sz = ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ; + sa_sz = ROC_NIX_INL_ON_IPSEC_OUTB_SA_SZ; else sa_sz = ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ; /* Alloc contiguous memory of outbound SA */ @@ -1212,7 +1220,12 @@ roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr, void *sa_cptr, /* Nothing much to do on cn9k */ if (roc_model_is_cn9k()) { - plt_atomic_thread_fence(__ATOMIC_ACQ_REL); + nix = roc_nix_to_nix_priv(roc_nix); + outb_lf = nix->cpt_lf_base; + rc = roc_on_cpt_ctx_write(outb_lf, (uint64_t)sa_dptr, inb, + sa_len, ROC_CPT_DFLT_ENG_GRP_SE_IE); + if (rc) + return rc; return 0; } diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h index 9911a48..555cb28 100644 --- a/drivers/common/cnxk/roc_nix_inl.h +++ b/drivers/common/cnxk/roc_nix_inl.h @@ -22,6 +22,24 @@ (ROC_NIX_INL_ONF_IPSEC_OUTB_HW_SZ + ROC_NIX_INL_ONF_IPSEC_OUTB_SW_RSVD) #define ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ_LOG2 8 +/* ON INB HW area */ +#define ROC_NIX_INL_ON_IPSEC_INB_HW_SZ \ + PLT_ALIGN(sizeof(struct roc_ie_on_inb_sa), ROC_ALIGN) +/* ON INB SW reserved area */ +#define ROC_NIX_INL_ON_IPSEC_INB_SW_RSVD 640 +#define ROC_NIX_INL_ON_IPSEC_INB_SA_SZ \ + (ROC_NIX_INL_ON_IPSEC_INB_HW_SZ + ROC_NIX_INL_ON_IPSEC_INB_SW_RSVD) +#define ROC_NIX_INL_ON_IPSEC_INB_SA_SZ_LOG2 10 + +/* ONF OUTB HW area */ +#define ROC_NIX_INL_ON_IPSEC_OUTB_HW_SZ \ + PLT_ALIGN(sizeof(struct roc_ie_on_outb_sa), ROC_ALIGN) +/* ONF OUTB SW reserved area */ +#define ROC_NIX_INL_ON_IPSEC_OUTB_SW_RSVD 256 +#define ROC_NIX_INL_ON_IPSEC_OUTB_SA_SZ \ + (ROC_NIX_INL_ON_IPSEC_OUTB_HW_SZ + ROC_NIX_INL_ON_IPSEC_OUTB_SW_RSVD) +#define ROC_NIX_INL_ON_IPSEC_OUTB_SA_SZ_LOG2 9 + /* OT INB HW area */ #define ROC_NIX_INL_OT_IPSEC_INB_HW_SZ \ PLT_ALIGN(sizeof(struct roc_ot_ipsec_inb_sa), ROC_ALIGN) @@ -61,6 +79,34 @@ #define ROC_NIX_INL_REAS_ZOMBIE_LIMIT 0xFFF #define ROC_NIX_INL_REAS_ZOMBIE_THRESHOLD 10 +static inline struct roc_ie_on_inb_sa * +roc_nix_inl_on_ipsec_inb_sa(uintptr_t base, uint64_t idx) +{ + uint64_t off = idx << ROC_NIX_INL_ON_IPSEC_INB_SA_SZ_LOG2; + + return PLT_PTR_ADD(base, off); +} + +static inline struct roc_ie_on_outb_sa * +roc_nix_inl_on_ipsec_outb_sa(uintptr_t base, uint64_t idx) +{ + uint64_t off = idx << ROC_NIX_INL_ON_IPSEC_OUTB_SA_SZ_LOG2; + + return PLT_PTR_ADD(base, off); +} + +static inline void * +roc_nix_inl_on_ipsec_inb_sa_sw_rsvd(void *sa) +{ + return PLT_PTR_ADD(sa, ROC_NIX_INL_ON_IPSEC_INB_HW_SZ); +} + +static inline void * +roc_nix_inl_on_ipsec_outb_sa_sw_rsvd(void *sa) +{ + return PLT_PTR_ADD(sa, ROC_NIX_INL_ON_IPSEC_OUTB_HW_SZ); +} + static inline struct roc_onf_ipsec_inb_sa * roc_nix_inl_onf_ipsec_inb_sa(uintptr_t base, uint64_t idx) { diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c index 1e9b2b9..4fe7b51 100644 --- a/drivers/common/cnxk/roc_nix_inl_dev.c +++ b/drivers/common/cnxk/roc_nix_inl_dev.c @@ -394,7 +394,7 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev) /* CN9K SA is different */ if (roc_model_is_cn9k()) - inb_sa_sz = ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ; + inb_sa_sz = ROC_NIX_INL_ON_IPSEC_INB_SA_SZ; else inb_sa_sz = ROC_NIX_INL_OT_IPSEC_INB_SA_SZ; diff --git a/drivers/crypto/cnxk/cn9k_ipsec.c b/drivers/crypto/cnxk/cn9k_ipsec.c index 78c181b..8491558 100644 --- a/drivers/crypto/cnxk/cn9k_ipsec.c +++ b/drivers/crypto/cnxk/cn9k_ipsec.c @@ -29,7 +29,6 @@ cn9k_ipsec_outb_sa_create(struct cnxk_cpt_qp *qp, union cpt_inst_w4 w4; union cpt_inst_w7 w7; size_t ctx_len; - uint8_t opcode; uint8_t egrp; int ret; @@ -80,10 +79,9 @@ cn9k_ipsec_outb_sa_create(struct cnxk_cpt_qp *qp, return ret; ctx_len = ret; - opcode = ROC_IE_ON_MAJOR_OP_WRITE_IPSEC_OUTBOUND; egrp = roc_cpt->eng_grp[CPT_ENG_TYPE_IE]; ret = roc_on_cpt_ctx_write(&qp->lf, rte_mempool_virt2iova(&sa->out_sa), - opcode, ctx_len, egrp); + false, ctx_len, egrp); if (ret) return ret; @@ -133,7 +131,6 @@ cn9k_ipsec_inb_sa_create(struct cnxk_cpt_qp *qp, union cpt_inst_w4 w4; union cpt_inst_w7 w7; size_t ctx_len = 0; - uint8_t opcode; uint8_t egrp; int ret = 0; @@ -172,10 +169,9 @@ cn9k_ipsec_inb_sa_create(struct cnxk_cpt_qp *qp, sa->esn_en = 1; ctx_len = ret; - opcode = ROC_IE_ON_MAJOR_OP_WRITE_IPSEC_INBOUND; egrp = roc_cpt->eng_grp[CPT_ENG_TYPE_IE]; ret = roc_on_cpt_ctx_write(&qp->lf, rte_mempool_virt2iova(&sa->in_sa), - opcode, ctx_len, egrp); + true, ctx_len, egrp); if (ret) return ret; diff --git a/drivers/event/cnxk/cn9k_worker.h b/drivers/event/cnxk/cn9k_worker.h index b087255..881861f 100644 --- a/drivers/event/cnxk/cn9k_worker.h +++ b/drivers/event/cnxk/cn9k_worker.h @@ -626,12 +626,14 @@ cn9k_sso_hws_xmit_sec_one(const struct cn9k_eth_txq *txq, uint64_t base, struct nix_send_hdr_s *send_hdr; uint64_t sa_base = txq->sa_base; uint32_t pkt_len, dlen_adj, rlen; + struct roc_ie_on_outb_hdr *hdr; uint64x2_t cmd01, cmd23; uint64_t lmt_status, sa; union nix_send_sg_s *sg; + uint32_t esn_lo, esn_hi; uintptr_t dptr, nixtx; uint64_t ucode_cmd[4]; - uint64_t esn, *iv; + uint64_t esn; uint8_t l2_len; mdata.u64 = *rte_security_dynfield(m); @@ -670,14 +672,19 @@ cn9k_sso_hws_xmit_sec_one(const struct cn9k_eth_txq *txq, uint64_t base, /* Load opcode and cptr already prepared at pkt metadata set */ pkt_len -= l2_len; - pkt_len += sizeof(struct roc_onf_ipsec_outb_hdr) + - ROC_ONF_IPSEC_OUTB_MAX_L2_INFO_SZ; + pkt_len += (sizeof(struct roc_ie_on_outb_hdr) - ROC_IE_ON_MAX_IV_LEN) + + ROC_ONF_IPSEC_OUTB_MAX_L2_INFO_SZ; sa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1); - sa = (uintptr_t)roc_nix_inl_onf_ipsec_outb_sa(sa_base, mdata.sa_idx); + sa = (uintptr_t)roc_nix_inl_on_ipsec_outb_sa(sa_base, mdata.sa_idx); ucode_cmd[3] = (ROC_CPT_DFLT_ENG_GRP_SE_IE << 61 | sa); - ucode_cmd[0] = (ROC_IE_ONF_MAJOR_OP_PROCESS_OUTBOUND_IPSEC << 48 | - 0x40UL << 48 | pkt_len); + ucode_cmd[0] = (((ROC_IE_ON_OUTB_MAX_CTX_LEN << 8) | + ROC_IE_ON_MAJOR_OP_PROCESS_OUTBOUND_IPSEC) + << 48 | + (ROC_IE_ON_OUTB_IKEV2_SINGLE_SA_SUPPORT | + (ROC_ONF_IPSEC_OUTB_MAX_L2_INFO_SZ >> + 3)) << 32 | + pkt_len); /* CPT Word 0 and Word 1 */ cmd01 = vdupq_n_u64((nixtx + 16) | (cn9k_nix_tx_ext_subs(flags) + 1)); @@ -687,35 +694,40 @@ cn9k_sso_hws_xmit_sec_one(const struct cn9k_eth_txq *txq, uint64_t base, /* CPT word 2 and 3 */ cmd23 = vdupq_n_u64(0); cmd23 = vsetq_lane_u64((((uint64_t)RTE_EVENT_TYPE_CPU << 28) | - CNXK_ETHDEV_SEC_OUTB_EV_SUB << 20), cmd23, 0); - cmd23 = vsetq_lane_u64((uintptr_t)m | 1, cmd23, 1); + CNXK_ETHDEV_SEC_OUTB_EV_SUB << 20), + cmd23, 0); + cmd23 = vsetq_lane_u64(((uintptr_t)m + sizeof(struct rte_mbuf)) | 1, + cmd23, 1); dptr += l2_len - ROC_ONF_IPSEC_OUTB_MAX_L2_INFO_SZ - - sizeof(struct roc_onf_ipsec_outb_hdr); + (sizeof(struct roc_ie_on_outb_hdr) - ROC_IE_ON_MAX_IV_LEN); ucode_cmd[1] = dptr; ucode_cmd[2] = dptr; - /* Update IV to zero and l2 sz */ - *(uint16_t *)(dptr + sizeof(struct roc_onf_ipsec_outb_hdr)) = + /* Update l2 sz */ + *(uint16_t *)(dptr + (sizeof(struct roc_ie_on_outb_hdr) - + ROC_IE_ON_MAX_IV_LEN)) = rte_cpu_to_be_16(ROC_ONF_IPSEC_OUTB_MAX_L2_INFO_SZ); - iv = (uint64_t *)(dptr + 8); - iv[0] = 0; - iv[1] = 0; /* Head wait if needed */ if (base) roc_sso_hws_head_wait(base); /* ESN */ - outb_priv = roc_nix_inl_onf_ipsec_outb_sa_sw_rsvd((void *)sa); + outb_priv = roc_nix_inl_on_ipsec_outb_sa_sw_rsvd((void *)sa); esn = outb_priv->esn; outb_priv->esn = esn + 1; ucode_cmd[0] |= (esn >> 32) << 16; - esn = rte_cpu_to_be_32(esn & (BIT_ULL(32) - 1)); + esn_lo = rte_cpu_to_be_32(esn & (BIT_ULL(32) - 1)); + esn_hi = rte_cpu_to_be_32(esn >> 32); - /* Update ESN and IPID and IV */ - *(uint64_t *)dptr = esn << 32 | esn; + /* Update ESN, IPID and IV */ + hdr = (struct roc_ie_on_outb_hdr *)dptr; + hdr->ip_id = esn_lo; + hdr->seq = esn_lo; + hdr->esn = esn_hi; + hdr->df_tos = 0; rte_io_wmb(); cn9k_sso_txq_fc_wait(txq); diff --git a/drivers/net/cnxk/cn9k_ethdev.h b/drivers/net/cnxk/cn9k_ethdev.h index 449729f..472a4b0 100644 --- a/drivers/net/cnxk/cn9k_ethdev.h +++ b/drivers/net/cnxk/cn9k_ethdev.h @@ -79,6 +79,9 @@ struct cn9k_outb_priv_data { /* Back pointer to eth sec session */ struct cnxk_eth_sec_sess *eth_sec; + + /* IV in DBG mode */ + uint8_t iv_dbg[ROC_IE_ON_MAX_IV_LEN]; }; struct cn9k_sec_sess_priv { diff --git a/drivers/net/cnxk/cn9k_ethdev_sec.c b/drivers/net/cnxk/cn9k_ethdev_sec.c index 4dd0b61..88b95fb 100644 --- a/drivers/net/cnxk/cn9k_ethdev_sec.c +++ b/drivers/net/cnxk/cn9k_ethdev_sec.c @@ -134,6 +134,37 @@ ar_window_init(struct cn9k_inb_priv_data *inb_priv) return 0; } +static void +outb_dbg_iv_update(struct roc_ie_on_common_sa *common_sa, const char *__iv_str) +{ + uint8_t *iv_dbg = common_sa->iv.aes_iv; + char *iv_str = strdup(__iv_str); + char *iv_b = NULL; + char *save; + int i, iv_len = ROC_IE_ON_MAX_IV_LEN; + + if (!iv_str) + return; + + if (common_sa->ctl.enc_type == ROC_IE_OT_SA_ENC_AES_GCM || + common_sa->ctl.enc_type == ROC_IE_OT_SA_ENC_AES_CTR || + common_sa->ctl.enc_type == ROC_IE_OT_SA_ENC_AES_CCM || + common_sa->ctl.auth_type == ROC_IE_OT_SA_AUTH_AES_GMAC) { + iv_dbg = common_sa->iv.gcm.iv; + iv_len = 8; + } + + memset(iv_dbg, 0, iv_len); + for (i = 0; i < iv_len; i++) { + iv_b = strtok_r(i ? NULL : iv_str, ",", &save); + if (!iv_b) + break; + iv_dbg[i] = strtoul(iv_b, NULL, 0); + } + + free(iv_str); +} + static int cn9k_eth_sec_session_create(void *device, struct rte_security_session_conf *conf, @@ -150,6 +181,7 @@ cn9k_eth_sec_session_create(void *device, rte_spinlock_t *lock; char tbuf[128] = {0}; bool inbound; + int ctx_len; int rc = 0; if (conf->action_type != RTE_SECURITY_ACTION_TYPE_INLINE_PROTOCOL) @@ -183,21 +215,26 @@ cn9k_eth_sec_session_create(void *device, memset(eth_sec, 0, sizeof(struct cnxk_eth_sec_sess)); sess_priv.u64 = 0; + if (!dev->outb.lf_base) { + plt_err("Could not allocate security session private data"); + return -ENOMEM; + } + if (inbound) { struct cn9k_inb_priv_data *inb_priv; - struct roc_onf_ipsec_inb_sa *inb_sa; + struct roc_ie_on_inb_sa *inb_sa; uint32_t spi_mask; PLT_STATIC_ASSERT(sizeof(struct cn9k_inb_priv_data) < - ROC_NIX_INL_ONF_IPSEC_INB_SW_RSVD); + ROC_NIX_INL_ON_IPSEC_INB_SW_RSVD); spi_mask = roc_nix_inl_inb_spi_range(nix, false, NULL, NULL); /* Get Inbound SA from NIX_RX_IPSEC_SA_BASE. Assume no inline * device always for CN9K. */ - inb_sa = (struct roc_onf_ipsec_inb_sa *) - roc_nix_inl_inb_sa_get(nix, false, ipsec->spi); + inb_sa = (struct roc_ie_on_inb_sa *)roc_nix_inl_inb_sa_get( + nix, false, ipsec->spi); if (!inb_sa) { snprintf(tbuf, sizeof(tbuf), "Failed to create ingress sa"); @@ -206,7 +243,7 @@ cn9k_eth_sec_session_create(void *device, } /* Check if SA is already in use */ - if (inb_sa->ctl.valid) { + if (inb_sa->common_sa.ctl.valid) { snprintf(tbuf, sizeof(tbuf), "Inbound SA with SPI %u already in use", ipsec->spi); @@ -214,17 +251,26 @@ cn9k_eth_sec_session_create(void *device, goto mempool_put; } - memset(inb_sa, 0, sizeof(struct roc_onf_ipsec_inb_sa)); + memset(inb_sa, 0, sizeof(struct roc_ie_on_inb_sa)); /* Fill inbound sa params */ - rc = cnxk_onf_ipsec_inb_sa_fill(inb_sa, ipsec, crypto); - if (rc) { + rc = cnxk_on_ipsec_inb_sa_create(ipsec, crypto, inb_sa); + if (rc < 0) { snprintf(tbuf, sizeof(tbuf), "Failed to init inbound sa, rc=%d", rc); goto mempool_put; } - inb_priv = roc_nix_inl_onf_ipsec_inb_sa_sw_rsvd(inb_sa); + ctx_len = rc; + rc = roc_nix_inl_ctx_write(&dev->nix, inb_sa, inb_sa, inbound, + ctx_len); + if (rc) { + snprintf(tbuf, sizeof(tbuf), + "Failed to create inbound sa, rc=%d", rc); + goto mempool_put; + } + + inb_priv = roc_nix_inl_on_ipsec_inb_sa_sw_rsvd(inb_sa); /* Back pointer to get eth_sec */ inb_priv->eth_sec = eth_sec; @@ -253,27 +299,38 @@ cn9k_eth_sec_session_create(void *device, dev->inb.nb_sess++; } else { struct cn9k_outb_priv_data *outb_priv; - struct roc_onf_ipsec_outb_sa *outb_sa; uintptr_t sa_base = dev->outb.sa_base; struct cnxk_ipsec_outb_rlens *rlens; + struct roc_ie_on_outb_sa *outb_sa; + const char *iv_str; uint32_t sa_idx; PLT_STATIC_ASSERT(sizeof(struct cn9k_outb_priv_data) < - ROC_NIX_INL_ONF_IPSEC_OUTB_SW_RSVD); + ROC_NIX_INL_ON_IPSEC_OUTB_SW_RSVD); /* Alloc an sa index */ rc = cnxk_eth_outb_sa_idx_get(dev, &sa_idx, 0); if (rc) goto mempool_put; - outb_sa = roc_nix_inl_onf_ipsec_outb_sa(sa_base, sa_idx); - outb_priv = roc_nix_inl_onf_ipsec_outb_sa_sw_rsvd(outb_sa); + outb_sa = roc_nix_inl_on_ipsec_outb_sa(sa_base, sa_idx); + outb_priv = roc_nix_inl_on_ipsec_outb_sa_sw_rsvd(outb_sa); rlens = &outb_priv->rlens; - memset(outb_sa, 0, sizeof(struct roc_onf_ipsec_outb_sa)); + memset(outb_sa, 0, sizeof(struct roc_ie_on_outb_sa)); /* Fill outbound sa params */ - rc = cnxk_onf_ipsec_outb_sa_fill(outb_sa, ipsec, crypto); + rc = cnxk_on_ipsec_outb_sa_create(ipsec, crypto, outb_sa); + if (rc < 0) { + snprintf(tbuf, sizeof(tbuf), + "Failed to init outbound sa, rc=%d", rc); + rc |= cnxk_eth_outb_sa_idx_put(dev, sa_idx); + goto mempool_put; + } + + ctx_len = rc; + rc = roc_nix_inl_ctx_write(&dev->nix, outb_sa, outb_sa, inbound, + ctx_len); if (rc) { snprintf(tbuf, sizeof(tbuf), "Failed to init outbound sa, rc=%d", rc); @@ -281,6 +338,18 @@ cn9k_eth_sec_session_create(void *device, goto mempool_put; } + /* Always enable explicit IV. + * Copy the IV from application only when iv_gen_disable flag is + * set + */ + outb_sa->common_sa.ctl.explicit_iv_en = 1; + + if (conf->ipsec.options.iv_gen_disable == 1) { + iv_str = getenv("ETH_SEC_IV_OVR"); + if (iv_str) + outb_dbg_iv_update(&outb_sa->common_sa, iv_str); + } + /* Save userdata */ outb_priv->userdata = conf->userdata; outb_priv->sa_idx = sa_idx; @@ -288,8 +357,8 @@ cn9k_eth_sec_session_create(void *device, /* Start sequence number with 1 */ outb_priv->seq = 1; - memcpy(&outb_priv->nonce, outb_sa->nonce, 4); - if (outb_sa->ctl.enc_type == ROC_IE_ON_SA_ENC_AES_GCM) + memcpy(&outb_priv->nonce, outb_sa->common_sa.iv.gcm.nonce, 4); + if (outb_sa->common_sa.ctl.enc_type == ROC_IE_ON_SA_ENC_AES_GCM) outb_priv->copy_salt = 1; /* Save rlen info */ @@ -337,9 +406,9 @@ cn9k_eth_sec_session_destroy(void *device, struct rte_security_session *sess) { struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)device; struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); - struct roc_onf_ipsec_outb_sa *outb_sa; - struct roc_onf_ipsec_inb_sa *inb_sa; struct cnxk_eth_sec_sess *eth_sec; + struct roc_ie_on_outb_sa *outb_sa; + struct roc_ie_on_inb_sa *inb_sa; struct rte_mempool *mp; rte_spinlock_t *lock; @@ -353,14 +422,14 @@ cn9k_eth_sec_session_destroy(void *device, struct rte_security_session *sess) if (eth_sec->inb) { inb_sa = eth_sec->sa; /* Disable SA */ - inb_sa->ctl.valid = 0; + inb_sa->common_sa.ctl.valid = 0; TAILQ_REMOVE(&dev->inb.list, eth_sec, entry); dev->inb.nb_sess--; } else { outb_sa = eth_sec->sa; /* Disable SA */ - outb_sa->ctl.valid = 0; + outb_sa->common_sa.ctl.valid = 0; /* Release Outbound SA index */ cnxk_eth_outb_sa_idx_put(dev, eth_sec->sa_idx); diff --git a/drivers/net/cnxk/cn9k_rx.h b/drivers/net/cnxk/cn9k_rx.h index 25a4927..1a9f920 100644 --- a/drivers/net/cnxk/cn9k_rx.h +++ b/drivers/net/cnxk/cn9k_rx.h @@ -171,7 +171,7 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, } static inline int -ipsec_antireplay_check(struct roc_onf_ipsec_inb_sa *sa, +ipsec_antireplay_check(struct roc_ie_on_inb_sa *sa, struct cn9k_inb_priv_data *priv, uintptr_t data, uint32_t win_sz) { @@ -183,7 +183,7 @@ ipsec_antireplay_check(struct roc_onf_ipsec_inb_sa *sa, uint8_t esn; int rc; - esn = sa->ctl.esn_en; + esn = sa->common_sa.ctl.esn_en; seql = rte_be_to_cpu_32(*((uint32_t *)(data + IPSEC_SQ_LO_IDX))); if (!esn) { @@ -200,11 +200,12 @@ ipsec_antireplay_check(struct roc_onf_ipsec_inb_sa *sa, rte_spinlock_lock(&ar->lock); rc = cnxk_on_anti_replay_check(seq, ar, win_sz); if (esn && !rc) { - seq_in_sa = ((uint64_t)rte_be_to_cpu_32(sa->esn_hi) << 32) | - rte_be_to_cpu_32(sa->esn_low); + seq_in_sa = ((uint64_t)rte_be_to_cpu_32(sa->common_sa.seq_t.th) + << 32) | + rte_be_to_cpu_32(sa->common_sa.seq_t.tl); if (seq > seq_in_sa) { - sa->esn_low = rte_cpu_to_be_32(seql); - sa->esn_hi = rte_cpu_to_be_32(seqh); + sa->common_sa.seq_t.tl = rte_cpu_to_be_32(seql); + sa->common_sa.seq_t.th = rte_cpu_to_be_32(seqh); } } rte_spinlock_unlock(&ar->lock); @@ -266,9 +267,10 @@ nix_rx_sec_mbuf_update(const struct nix_cqe_hdr_s *cq, struct rte_mbuf *m, const union nix_rx_parse_u *rx = (const union nix_rx_parse_u *)((const uint64_t *)cq + 1); struct cn9k_inb_priv_data *sa_priv; - struct roc_onf_ipsec_inb_sa *sa; + struct roc_ie_on_inb_sa *sa; uint8_t lcptr = rx->lcptr; - struct rte_ipv4_hdr *ipv4; + struct rte_ipv4_hdr *ip; + struct rte_ipv6_hdr *ip6; uint16_t data_off, res; uint32_t spi, win_sz; uint32_t spi_mask; @@ -279,6 +281,7 @@ nix_rx_sec_mbuf_update(const struct nix_cqe_hdr_s *cq, struct rte_mbuf *m, res = *(uint64_t *)(res_sg0 + 8); data_off = *rearm_val & (BIT_ULL(16) - 1); data = (uintptr_t)m->buf_addr; + data += data_off; rte_prefetch0((void *)data); @@ -294,10 +297,10 @@ nix_rx_sec_mbuf_update(const struct nix_cqe_hdr_s *cq, struct rte_mbuf *m, sa_w = sa_base & (ROC_NIX_INL_SA_BASE_ALIGN - 1); sa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1); spi_mask = (1ULL << sa_w) - 1; - sa = roc_nix_inl_onf_ipsec_inb_sa(sa_base, spi & spi_mask); + sa = roc_nix_inl_on_ipsec_inb_sa(sa_base, spi & spi_mask); /* Update dynamic field with userdata */ - sa_priv = roc_nix_inl_onf_ipsec_inb_sa_sw_rsvd(sa); + sa_priv = roc_nix_inl_on_ipsec_inb_sa_sw_rsvd(sa); dw = *(__uint128_t *)sa_priv; *rte_security_dynfield(m) = (uint64_t)dw; @@ -309,16 +312,26 @@ nix_rx_sec_mbuf_update(const struct nix_cqe_hdr_s *cq, struct rte_mbuf *m, } /* Get total length from IPv4 header. We can assume only IPv4 */ - ipv4 = (struct rte_ipv4_hdr *)(data + ROC_ONF_IPSEC_INB_SPI_SEQ_SZ + - ROC_ONF_IPSEC_INB_MAX_L2_SZ); + ip = (struct rte_ipv4_hdr *)(data + ROC_ONF_IPSEC_INB_SPI_SEQ_SZ + + ROC_ONF_IPSEC_INB_MAX_L2_SZ); + + if (((ip->version_ihl & 0xf0) >> RTE_IPV4_IHL_MULTIPLIER) == + IPVERSION) { + *len = rte_be_to_cpu_16(ip->total_length) + lcptr; + } else { + PLT_ASSERT(((ip->version_ihl & 0xf0) >> + RTE_IPV4_IHL_MULTIPLIER) == 6); + ip6 = (struct rte_ipv6_hdr *)ip; + *len = rte_be_to_cpu_16(ip6->payload_len) + + sizeof(struct rte_ipv6_hdr) + lcptr; + } /* Update data offset */ - data_off += (ROC_ONF_IPSEC_INB_SPI_SEQ_SZ + - ROC_ONF_IPSEC_INB_MAX_L2_SZ); + data_off += + (ROC_ONF_IPSEC_INB_SPI_SEQ_SZ + ROC_ONF_IPSEC_INB_MAX_L2_SZ); *rearm_val = *rearm_val & ~(BIT_ULL(16) - 1); *rearm_val |= data_off; - *len = rte_be_to_cpu_16(ipv4->total_length) + lcptr; return RTE_MBUF_F_RX_SEC_OFFLOAD; } diff --git a/drivers/net/cnxk/cnxk_ethdev_sec_telemetry.c b/drivers/net/cnxk/cnxk_ethdev_sec_telemetry.c index bfdbd1e..dd8b7a5 100644 --- a/drivers/net/cnxk/cnxk_ethdev_sec_telemetry.c +++ b/drivers/net/cnxk/cnxk_ethdev_sec_telemetry.c @@ -14,59 +14,47 @@ static int copy_outb_sa_9k(struct rte_tel_data *d, uint32_t i, void *sa) { - struct roc_onf_ipsec_outb_sa *out_sa; union { - struct roc_ie_onf_sa_ctl ctl; + struct roc_ie_on_sa_ctl ctl; uint64_t u64; } w0; + struct roc_ie_on_outb_sa *out_sa; char strw0[W0_MAXLEN]; char str[STR_MAXLEN]; - out_sa = (struct roc_onf_ipsec_outb_sa *)sa; - w0.ctl = out_sa->ctl; + out_sa = (struct roc_ie_on_outb_sa *)sa; + w0.ctl = out_sa->common_sa.ctl; snprintf(str, sizeof(str), "outsa_w0_%u", i); snprintf(strw0, sizeof(strw0), "%" PRIu64, w0.u64); rte_tel_data_add_dict_string(d, str, strw0); - snprintf(str, sizeof(str), "outsa_src_%u", i); - rte_tel_data_add_dict_u64(d, str, out_sa->udp_src); - - snprintf(str, sizeof(str), "outsa_dst_%u", i); - rte_tel_data_add_dict_u64(d, str, out_sa->udp_dst); - - snprintf(str, sizeof(str), "outsa_isrc_%u", i); - rte_tel_data_add_dict_u64(d, str, out_sa->ip_src); - - snprintf(str, sizeof(str), "outsa_idst_%u", i); - rte_tel_data_add_dict_u64(d, str, out_sa->ip_dst); - return 0; } static int copy_inb_sa_9k(struct rte_tel_data *d, uint32_t i, void *sa) { - struct roc_onf_ipsec_inb_sa *in_sa; union { - struct roc_ie_onf_sa_ctl ctl; + struct roc_ie_on_sa_ctl ctl; uint64_t u64; } w0; + struct roc_ie_on_inb_sa *in_sa; char strw0[W0_MAXLEN]; char str[STR_MAXLEN]; - in_sa = (struct roc_onf_ipsec_inb_sa *)sa; - w0.ctl = in_sa->ctl; + in_sa = (struct roc_ie_on_inb_sa *)sa; + w0.ctl = in_sa->common_sa.ctl; snprintf(str, sizeof(str), "insa_w0_%u", i); snprintf(strw0, sizeof(strw0), "%" PRIu64, w0.u64); rte_tel_data_add_dict_string(d, str, strw0); snprintf(str, sizeof(str), "insa_esnh_%u", i); - rte_tel_data_add_dict_u64(d, str, in_sa->esn_hi); + rte_tel_data_add_dict_u64(d, str, in_sa->common_sa.seq_t.th); snprintf(str, sizeof(str), "insa_esnl_%u", i); - rte_tel_data_add_dict_u64(d, str, in_sa->esn_low); + rte_tel_data_add_dict_u64(d, str, in_sa->common_sa.seq_t.tl); return 0; } From patchwork Tue Aug 9 18:48:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 114774 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5DDD1A04FD; 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Tue, 09 Aug 2022 11:50:34 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 9 Aug 2022 11:50:32 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 9 Aug 2022 11:50:32 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 11EEB5B69B1; Tue, 9 Aug 2022 11:50:22 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Vidya Sagar Velumuri Subject: [PATCH 14/23] net/cnxk: add crypto capabilities for HMAC-SHA2 Date: Wed, 10 Aug 2022 00:18:58 +0530 Message-ID: <20220809184908.24030-14-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220809184908.24030-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: JglIsmtfDe07j1OZeTeZX8N8awzfs5nD X-Proofpoint-GUID: JglIsmtfDe07j1OZeTeZX8N8awzfs5nD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Vidya Sagar Velumuri Add capabilities for HMAC_SHA2 and udp encap for 9k security offload in inline mode. Set explicit IV mode in IPsec context when IV is provided by the application Signed-off-by: Vidya Sagar Velumuri --- drivers/net/cnxk/cn9k_ethdev_sec.c | 79 ++++++++++++++++++++++++++++++++++---- 1 file changed, 71 insertions(+), 8 deletions(-) diff --git a/drivers/net/cnxk/cn9k_ethdev_sec.c b/drivers/net/cnxk/cn9k_ethdev_sec.c index 88b95fb..42ba04a 100644 --- a/drivers/net/cnxk/cn9k_ethdev_sec.c +++ b/drivers/net/cnxk/cn9k_ethdev_sec.c @@ -80,6 +80,66 @@ static struct rte_cryptodev_capabilities cn9k_eth_sec_crypto_caps[] = { }, } }, } }, + { /* SHA256 HMAC */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_SHA256_HMAC, + .block_size = 64, + .key_size = { + .min = 1, + .max = 1024, + .increment = 1 + }, + .digest_size = { + .min = 16, + .max = 32, + .increment = 16 + }, + }, } + }, } + }, + { /* SHA384 HMAC */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_SHA384_HMAC, + .block_size = 64, + .key_size = { + .min = 1, + .max = 1024, + .increment = 1 + }, + .digest_size = { + .min = 24, + .max = 48, + .increment = 24 + }, + }, } + }, } + }, + { /* SHA512 HMAC */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_SHA512_HMAC, + .block_size = 128, + .key_size = { + .min = 1, + .max = 1024, + .increment = 1 + }, + .digest_size = { + .min = 32, + .max = 64, + .increment = 32 + }, + }, } + }, } + }, RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST() }; @@ -91,7 +151,9 @@ static const struct rte_security_capability cn9k_eth_sec_capabilities[] = { .proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP, .mode = RTE_SECURITY_IPSEC_SA_MODE_TUNNEL, .direction = RTE_SECURITY_IPSEC_SA_DIR_INGRESS, - .options = { 0 } + .options = { + .udp_encap = 1 + } }, .crypto_capabilities = cn9k_eth_sec_crypto_caps, .ol_flags = RTE_SECURITY_TX_OLOAD_NEED_MDATA @@ -103,7 +165,10 @@ static const struct rte_security_capability cn9k_eth_sec_capabilities[] = { .proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP, .mode = RTE_SECURITY_IPSEC_SA_MODE_TUNNEL, .direction = RTE_SECURITY_IPSEC_SA_DIR_EGRESS, - .options = { 0 } + .options = { + .udp_encap = 1, + .iv_gen_disable = 1 + } }, .crypto_capabilities = cn9k_eth_sec_crypto_caps, .ol_flags = RTE_SECURITY_TX_OLOAD_NEED_MDATA @@ -338,13 +403,11 @@ cn9k_eth_sec_session_create(void *device, goto mempool_put; } - /* Always enable explicit IV. - * Copy the IV from application only when iv_gen_disable flag is - * set + /* When IV is provided by the application, + * copy the IV to context and enable explicit IV flag in context. */ - outb_sa->common_sa.ctl.explicit_iv_en = 1; - - if (conf->ipsec.options.iv_gen_disable == 1) { + if (ipsec->options.iv_gen_disable == 1) { + outb_sa->common_sa.ctl.explicit_iv_en = 1; iv_str = getenv("ETH_SEC_IV_OVR"); if (iv_str) outb_dbg_iv_update(&outb_sa->common_sa, iv_str); From patchwork Tue Aug 9 18:48:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 114773 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9EE67A04FD; Tue, 9 Aug 2022 20:50:41 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CF6FA42BF7; Tue, 9 Aug 2022 20:50:36 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 3DAA542BE7 for ; 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Tue, 9 Aug 2022 11:50:32 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 9 Aug 2022 11:50:32 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id D89705B69B2; Tue, 9 Aug 2022 11:50:25 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 15/23] common/cnxk: enable aging on CN10K platform Date: Wed, 10 Aug 2022 00:18:59 +0530 Message-ID: <20220809184908.24030-15-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220809184908.24030-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: DQYCiN8WVNzykjJL2Gg0V_dmn4axhPDW X-Proofpoint-GUID: DQYCiN8WVNzykjJL2Gg0V_dmn4axhPDW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Satha Rao This patch set enables aging on CNF105 variant of CN10K platform. Enables aging statistics while dumping/reset SQ statistics. Signed-off-by: Satha Rao --- drivers/common/cnxk/roc_errata.h | 3 +-- drivers/common/cnxk/roc_nix_debug.c | 19 +++++++++---------- drivers/common/cnxk/roc_nix_stats.c | 2 ++ 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/common/cnxk/roc_errata.h b/drivers/common/cnxk/roc_errata.h index 8dc372f..d3b32f1 100644 --- a/drivers/common/cnxk/roc_errata.h +++ b/drivers/common/cnxk/roc_errata.h @@ -30,8 +30,7 @@ roc_errata_npa_has_no_fc_stype_ststp(void) static inline bool roc_errata_nix_has_no_drop_aging(void) { - return (roc_model_is_cn10ka_a0() || roc_model_is_cnf10ka_a0() || - roc_model_is_cnf10kb_a0()); + return (roc_model_is_cn10ka_a0() || roc_model_is_cnf10ka_a0()); } /* Errata IPBUNIXRX-40130 */ diff --git a/drivers/common/cnxk/roc_nix_debug.c b/drivers/common/cnxk/roc_nix_debug.c index efac7e5..bd7a5d3 100644 --- a/drivers/common/cnxk/roc_nix_debug.c +++ b/drivers/common/cnxk/roc_nix_debug.c @@ -472,22 +472,21 @@ nix_lf_sq_dump(__io struct nix_cn10k_sq_ctx_s *ctx, uint32_t *sqb_aura_p) nix_dump("W7: smenq_next_sqb \t\t0x%" PRIx64 "", ctx->smenq_next_sqb); nix_dump("W8: head_sqb \t\t\t0x%" PRIx64 "", ctx->head_sqb); - nix_dump("W9: vfi_lso_vld \t\t%d\nW9: vfi_lso_vlan1_ins_ena\t%d", - ctx->vfi_lso_vld, ctx->vfi_lso_vlan1_ins_ena); + nix_dump("W9: vfi_lso_vld \t\t%d\nW9: vfi_lso_vlan1_ins_ena\t%d", ctx->vfi_lso_vld, + ctx->vfi_lso_vlan1_ins_ena); nix_dump("W9: vfi_lso_vlan0_ins_ena\t%d\nW9: vfi_lso_mps\t\t\t%d", ctx->vfi_lso_vlan0_ins_ena, ctx->vfi_lso_mps); - nix_dump("W9: vfi_lso_sb \t\t\t%d\nW9: vfi_lso_sizem1\t\t%d", - ctx->vfi_lso_sb, ctx->vfi_lso_sizem1); + nix_dump("W9: vfi_lso_sb \t\t\t%d\nW9: vfi_lso_sizem1\t\t%d", ctx->vfi_lso_sb, + ctx->vfi_lso_sizem1); nix_dump("W9: vfi_lso_total\t\t%d", ctx->vfi_lso_total); - nix_dump("W10: scm_lso_rem \t\t0x%" PRIx64 "", - (uint64_t)ctx->scm_lso_rem); + nix_dump("W10: scm_lso_rem \t\t0x%" PRIx64 "", (uint64_t)ctx->scm_lso_rem); nix_dump("W11: octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->octs); nix_dump("W12: pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->pkts); - nix_dump("W14: dropped_octs \t\t0x%" PRIx64 "", - (uint64_t)ctx->drop_octs); - nix_dump("W15: dropped_pkts \t\t0x%" PRIx64 "", - (uint64_t)ctx->drop_pkts); + nix_dump("W13: aged_drop_pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->aged_drop_pkts); + nix_dump("W13: aged_drop_octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->aged_drop_octs); + nix_dump("W14: dropped_octs \t\t0x%" PRIx64 "", (uint64_t)ctx->drop_octs); + nix_dump("W15: dropped_pkts \t\t0x%" PRIx64 "", (uint64_t)ctx->drop_pkts); *sqb_aura_p = ctx->sqb_aura; } diff --git a/drivers/common/cnxk/roc_nix_stats.c b/drivers/common/cnxk/roc_nix_stats.c index 8fd5c71..2e5071e 100644 --- a/drivers/common/cnxk/roc_nix_stats.c +++ b/drivers/common/cnxk/roc_nix_stats.c @@ -238,6 +238,8 @@ nix_stat_tx_queue_reset(struct nix *nix, uint16_t qid) aq->sq_mask.pkts = ~(aq->sq_mask.pkts); aq->sq_mask.drop_octs = ~(aq->sq_mask.drop_octs); aq->sq_mask.drop_pkts = ~(aq->sq_mask.drop_pkts); + aq->sq_mask.aged_drop_octs = ~(aq->sq_mask.aged_drop_octs); + aq->sq_mask.aged_drop_pkts = ~(aq->sq_mask.aged_drop_pkts); } rc = mbox_process(mbox); From patchwork Tue Aug 9 18:49:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 114776 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D73FAA04FD; Tue, 9 Aug 2022 20:51:02 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9EA9B42C29; Tue, 9 Aug 2022 20:50:39 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 39B3642BD6 for ; Tue, 9 Aug 2022 20:50:36 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 279CZ8Yi017274 for ; Tue, 9 Aug 2022 11:50:35 -0700 DKIM-Signature: v=1; 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Tue, 9 Aug 2022 11:50:32 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 73AEE5B69B3; Tue, 9 Aug 2022 11:50:28 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 16/23] common/cnxk: updated shaper profile with red algorithm Date: Wed, 10 Aug 2022 00:19:00 +0530 Message-ID: <20220809184908.24030-16-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220809184908.24030-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: VKM93d4mQGgQWLDsyWYG6a6BbPLRW4AJ X-Proofpoint-ORIG-GUID: VKM93d4mQGgQWLDsyWYG6a6BbPLRW4AJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Satha Rao Updated shaper profile with user configurable RED algorithm. Signed-off-by: Satha Rao --- drivers/common/cnxk/roc_nix.h | 1 + drivers/common/cnxk/roc_nix_tm_utils.c | 7 +++++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 5f5f5f9..8fd5990 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -566,6 +566,7 @@ struct roc_nix_tm_shaper_profile { int32_t pkt_len_adj; bool pkt_mode; int8_t accuracy; + uint8_t red_algo; /* Function to free this memory */ void (*free_fn)(void *profile); }; diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c index b9b605f..193f9df 100644 --- a/drivers/common/cnxk/roc_nix_tm_utils.c +++ b/drivers/common/cnxk/roc_nix_tm_utils.c @@ -1236,11 +1236,14 @@ roc_nix_tm_shaper_default_red_algo(struct roc_nix_tm_node *node, struct nix_tm_shaper_profile *profile; struct nix_tm_shaper_data cir, pir; + if (!roc_prof) + return; + profile = (struct nix_tm_shaper_profile *)roc_prof->reserved; - tm_node->red_algo = NIX_REDALG_STD; + tm_node->red_algo = roc_prof->red_algo; /* C0 doesn't support STALL when both PIR & CIR are enabled */ - if (profile && roc_model_is_cn96_cx()) { + if (roc_model_is_cn96_cx()) { nix_tm_shaper_conf_get(profile, &cir, &pir); if (pir.rate && cir.rate) From patchwork Tue Aug 9 18:49:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 114777 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 61C8FA04FD; Tue, 9 Aug 2022 20:51:08 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 69C0C42C2F; Tue, 9 Aug 2022 20:50:40 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id A48C042BD6 for ; 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Tue, 9 Aug 2022 11:50:33 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 9 Aug 2022 11:50:33 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 068423F7085; Tue, 9 Aug 2022 11:50:30 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Harman Kalra Subject: [PATCH 17/23] common/cnxk: add 98xx A1 platform Date: Wed, 10 Aug 2022 00:19:01 +0530 Message-ID: <20220809184908.24030-17-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220809184908.24030-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: oseueHkShOXlth-RFJZnIJ9oqIjGkiHf X-Proofpoint-ORIG-GUID: oseueHkShOXlth-RFJZnIJ9oqIjGkiHf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Harman Kalra Adding support for 98xx A1 pass Signed-off-by: Harman Kalra --- drivers/common/cnxk/roc_model.c | 1 + drivers/common/cnxk/roc_model.h | 16 +++++++++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c index b040bc0..326b85e 100644 --- a/drivers/common/cnxk/roc_model.c +++ b/drivers/common/cnxk/roc_model.c @@ -65,6 +65,7 @@ static const struct model_db { {VENDOR_ARM, PART_103xx, 0, 0, ROC_MODEL_CN103xx_A0, "cn10kb_a0"}, {VENDOR_ARM, PART_105xxN, 0, 0, ROC_MODEL_CNF105xxN_A0, "cnf10kb_a0"}, {VENDOR_CAVIUM, PART_98xx, 0, 0, ROC_MODEL_CN98xx_A0, "cn98xx_a0"}, + {VENDOR_CAVIUM, PART_98xx, 0, 1, ROC_MODEL_CN98xx_A1, "cn98xx_a1"}, {VENDOR_CAVIUM, PART_96xx, 0, 0, ROC_MODEL_CN96xx_A0, "cn96xx_a0"}, {VENDOR_CAVIUM, PART_96xx, 0, 1, ROC_MODEL_CN96xx_B0, "cn96xx_b0"}, {VENDOR_CAVIUM, PART_96xx, 2, 0, ROC_MODEL_CN96xx_C0, "cn96xx_c0"}, diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h index d231d44..57a8af0 100644 --- a/drivers/common/cnxk/roc_model.h +++ b/drivers/common/cnxk/roc_model.h @@ -21,6 +21,7 @@ struct roc_model { #define ROC_MODEL_CNF95xxN_A1 BIT_ULL(14) #define ROC_MODEL_CNF95xxN_B0 BIT_ULL(15) #define ROC_MODEL_CN98xx_A0 BIT_ULL(16) +#define ROC_MODEL_CN98xx_A1 BIT_ULL(17) #define ROC_MODEL_CN106xx_A0 BIT_ULL(20) #define ROC_MODEL_CNF105xx_A0 BIT_ULL(21) #define ROC_MODEL_CNF105xxN_A0 BIT_ULL(22) @@ -38,10 +39,11 @@ struct roc_model { } __plt_cache_aligned; #define ROC_MODEL_CN96xx_Ax (ROC_MODEL_CN96xx_A0 | ROC_MODEL_CN96xx_B0) +#define ROC_MODEL_CN98xx_Ax (ROC_MODEL_CN98xx_A0 | ROC_MODEL_CN98xx_A1) #define ROC_MODEL_CN9K \ (ROC_MODEL_CN96xx_Ax | ROC_MODEL_CN96xx_C0 | ROC_MODEL_CNF95xx_A0 | \ ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95xxMM_A0 | \ - ROC_MODEL_CNF95xxO_A0 | ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CN98xx_A0 | \ + ROC_MODEL_CNF95xxO_A0 | ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CN98xx_Ax | \ ROC_MODEL_CNF95xxN_A1 | ROC_MODEL_CNF95xxN_B0) #define ROC_MODEL_CNF9K \ (ROC_MODEL_CNF95xx_A0 | ROC_MODEL_CNF95xx_B0 | \ @@ -111,10 +113,22 @@ roc_model_is_cn10k(void) static inline uint64_t roc_model_is_cn98xx(void) { + return (roc_model->flag & ROC_MODEL_CN98xx_Ax); +} + +static inline uint64_t +roc_model_is_cn98xx_a0(void) +{ return (roc_model->flag & ROC_MODEL_CN98xx_A0); } static inline uint64_t +roc_model_is_cn98xx_a1(void) +{ + return (roc_model->flag & ROC_MODEL_CN98xx_A1); +} + +static inline uint64_t roc_model_is_cn96_a0(void) { return roc_model->flag & ROC_MODEL_CN96xx_A0; From patchwork Tue Aug 9 18:49:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 114778 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 192D8A04FD; Tue, 9 Aug 2022 20:51:14 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2BA0642C36; Tue, 9 Aug 2022 20:50:41 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 9D6BC42BDA for ; Tue, 9 Aug 2022 20:50:38 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 279D8wci015744 for ; Tue, 9 Aug 2022 11:50:37 -0700 DKIM-Signature: v=1; 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Tue, 9 Aug 2022 11:50:35 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id C3AAB3F7087; Tue, 9 Aug 2022 11:50:33 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Vidya Sagar Velumuri Subject: [PATCH 18/23] net/cnxk: enable additional ciphers for inline Date: Wed, 10 Aug 2022 00:19:02 +0530 Message-ID: <20220809184908.24030-18-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220809184908.24030-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: mv0Xu0R__PCcNYouKijI_UCh3rfbnSfK X-Proofpoint-GUID: mv0Xu0R__PCcNYouKijI_UCh3rfbnSfK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Vidya Sagar Velumuri Enable below ciphers and auths as part of capabilities for inline IPsec AES_CTR AES_XCBC_MAC AES_GMAC Signed-off-by: Vidya Sagar Velumuri --- drivers/net/cnxk/cn9k_ethdev_sec.c | 86 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/drivers/net/cnxk/cn9k_ethdev_sec.c b/drivers/net/cnxk/cn9k_ethdev_sec.c index 42ba04a..2dc9fe1 100644 --- a/drivers/net/cnxk/cn9k_ethdev_sec.c +++ b/drivers/net/cnxk/cn9k_ethdev_sec.c @@ -10,6 +10,27 @@ #include static struct rte_cryptodev_capabilities cn9k_eth_sec_crypto_caps[] = { + { /* NULL (CIPHER) */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, + {.cipher = { + .algo = RTE_CRYPTO_CIPHER_NULL, + .block_size = 1, + .key_size = { + .min = 0, + .max = 0, + .increment = 0 + }, + .iv_size = { + .min = 0, + .max = 0, + .increment = 0 + } + }, }, + }, } + }, + { /* AES GCM */ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, {.sym = { @@ -60,6 +81,71 @@ static struct rte_cryptodev_capabilities cn9k_eth_sec_crypto_caps[] = { }, } }, } }, + { /* AES CTR */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, + {.cipher = { + .algo = RTE_CRYPTO_CIPHER_AES_CTR, + .block_size = 16, + .key_size = { + .min = 16, + .max = 32, + .increment = 8 + }, + .iv_size = { + .min = 12, + .max = 16, + .increment = 4 + } + }, } + }, } + }, + { /* AES-XCBC */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + { .sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_AES_XCBC_MAC, + .block_size = 16, + .key_size = { + .min = 16, + .max = 16, + .increment = 0 + }, + .digest_size = { + .min = 12, + .max = 12, + .increment = 0, + }, + }, } + }, } + }, + { /* AES GMAC (AUTH) */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_AES_GMAC, + .block_size = 16, + .key_size = { + .min = 16, + .max = 32, + .increment = 8 + }, + .digest_size = { + .min = 8, + .max = 16, + .increment = 4 + }, + .iv_size = { + .min = 12, + .max = 12, + .increment = 0 + } + }, } + }, } + }, { /* SHA1 HMAC */ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, {.sym = { From patchwork Tue Aug 9 18:49:03 2022 Content-Type: text/plain; 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Tue, 9 Aug 2022 11:50:36 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ankur Dwivedi , Anoob Joseph , Tejasree Kondoj CC: , , Vidya Sagar Velumuri Subject: [PATCH 19/23] net/cnxk: enable 3des-cbc cipher capability Date: Wed, 10 Aug 2022 00:19:03 +0530 Message-ID: <20220809184908.24030-19-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220809184908.24030-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: jhty6YIyJKv-L7NRHJAeq0DnHJ-U-8Mi X-Proofpoint-GUID: jhty6YIyJKv-L7NRHJAeq0DnHJ-U-8Mi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Vidya Sagar Velumuri Enable 3DES-CBC cipher capability for inline IPsec Signed-off-by: Vidya Sagar Velumuri --- drivers/common/cnxk/cnxk_security.c | 3 +++ drivers/crypto/cnxk/cn9k_ipsec.c | 6 ++++++ drivers/net/cnxk/cn9k_ethdev_sec.c | 21 ++++++++++++++++++++- 3 files changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/cnxk_security.c b/drivers/common/cnxk/cnxk_security.c index 89ac900..a442549 100644 --- a/drivers/common/cnxk/cnxk_security.c +++ b/drivers/common/cnxk/cnxk_security.c @@ -1033,6 +1033,9 @@ on_ipsec_sa_ctl_set(struct rte_security_ipsec_xform *ipsec, case RTE_CRYPTO_CIPHER_NULL: ctl->enc_type = ROC_IE_ON_SA_ENC_NULL; break; + case RTE_CRYPTO_CIPHER_3DES_CBC: + ctl->enc_type = ROC_IE_ON_SA_ENC_3DES_CBC; + break; case RTE_CRYPTO_CIPHER_AES_CBC: ctl->enc_type = ROC_IE_ON_SA_ENC_AES_CBC; aes_key_len = cipher_xform->cipher.key.length; diff --git a/drivers/crypto/cnxk/cn9k_ipsec.c b/drivers/crypto/cnxk/cn9k_ipsec.c index 8491558..3d37449 100644 --- a/drivers/crypto/cnxk/cn9k_ipsec.c +++ b/drivers/crypto/cnxk/cn9k_ipsec.c @@ -248,6 +248,12 @@ cn9k_ipsec_xform_verify(struct rte_security_ipsec_xform *ipsec, plt_err("Transport mode AES-CBC AES-XCBC is not supported"); return -ENOTSUP; } + + if ((cipher->algo == RTE_CRYPTO_CIPHER_3DES_CBC) && + (auth->algo == RTE_CRYPTO_AUTH_AES_XCBC_MAC)) { + plt_err("Transport mode 3DES-CBC AES-XCBC is not supported"); + return -ENOTSUP; + } } } diff --git a/drivers/net/cnxk/cn9k_ethdev_sec.c b/drivers/net/cnxk/cn9k_ethdev_sec.c index 2dc9fe1..9536a99 100644 --- a/drivers/net/cnxk/cn9k_ethdev_sec.c +++ b/drivers/net/cnxk/cn9k_ethdev_sec.c @@ -30,7 +30,26 @@ static struct rte_cryptodev_capabilities cn9k_eth_sec_crypto_caps[] = { }, }, }, } }, - + { /* 3DES CBC */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, + {.cipher = { + .algo = RTE_CRYPTO_CIPHER_3DES_CBC, + .block_size = 8, + .key_size = { + .min = 24, + .max = 24, + .increment = 0 + }, + .iv_size = { + .min = 8, + .max = 16, + .increment = 8 + } + }, }, + }, } + }, { /* AES GCM */ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, {.sym = { From patchwork Tue Aug 9 18:49:04 2022 Content-Type: text/plain; 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Tue, 9 Aug 2022 11:50:39 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 20/23] net/cnxk: skip PFC configuration on LBK Date: Wed, 10 Aug 2022 00:19:04 +0530 Message-ID: <20220809184908.24030-20-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220809184908.24030-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: M2J8e8-Y7Upp35_NIXVE1kiHtMugvUOG X-Proofpoint-ORIG-GUID: M2J8e8-Y7Upp35_NIXVE1kiHtMugvUOG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Satha Rao CNXK platforms do not support PFC on LBK so skipping configuration on LBK interfaces. Signed-off-by: Satha Rao --- drivers/net/cnxk/cnxk_ethdev.c | 2 +- drivers/net/cnxk/cnxk_ethdev_ops.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 02416ad..f08a20f 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -1859,7 +1859,7 @@ cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool reset) pfc_conf.tx_pause.rx_qid = i; rc = cnxk_nix_priority_flow_ctrl_queue_config(eth_dev, &pfc_conf); - if (rc) + if (rc && rc != -ENOTSUP) plt_err("Failed to reset PFC. error code(%d)", rc); } diff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_ethdev_ops.c index 1592971..64beabd 100644 --- a/drivers/net/cnxk/cnxk_ethdev_ops.c +++ b/drivers/net/cnxk/cnxk_ethdev_ops.c @@ -356,8 +356,8 @@ cnxk_nix_priority_flow_ctrl_queue_config(struct rte_eth_dev *eth_dev, return -ENOTSUP; } - if (roc_nix_is_sdp(nix)) { - plt_err("Prio flow ctrl config is not allowed on SDP"); + if (roc_nix_is_sdp(nix) || roc_nix_is_lbk(nix)) { + plt_nix_dbg("Prio flow ctrl config is not allowed on SDP/LBK"); return -ENOTSUP; } From patchwork Tue Aug 9 18:49:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 114781 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 336D7A04FD; Tue, 9 Aug 2022 20:51:30 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2371542C4E; Tue, 9 Aug 2022 20:50:50 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 7E0AA42BEB for ; Tue, 9 Aug 2022 20:50:47 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 279D8wcl015744 for ; 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Tue, 9 Aug 2022 11:50:44 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id B9FAC3F7085; Tue, 9 Aug 2022 11:50:42 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Rakesh Kudurumalla Subject: [PATCH 21/23] common/cnxk: add support for CPT second pass Date: Wed, 10 Aug 2022 00:19:05 +0530 Message-ID: <20220809184908.24030-21-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220809184908.24030-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: jmqMGyNd4APkzgj7WY0H0impayvLoVun X-Proofpoint-GUID: jmqMGyNd4APkzgj7WY0H0impayvLoVun X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Rakesh Kudurumalla Added mailbox for masking and setting nix_rq_ctx parameters and enabling rq masking in ipsec_cfg1 so second pass is applied to all rq's Signed-off-by: Rakesh Kudurumalla --- drivers/common/cnxk/hw/nix.h | 4 +- drivers/common/cnxk/roc_mbox.h | 23 ++++++++++- drivers/common/cnxk/roc_nix_inl.c | 81 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 106 insertions(+), 2 deletions(-) diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h index 5863e35..a535264 100644 --- a/drivers/common/cnxk/hw/nix.h +++ b/drivers/common/cnxk/hw/nix.h @@ -1242,7 +1242,9 @@ struct nix_cn10k_rq_ctx_s { uint64_t ipsech_ena : 1; uint64_t ena_wqwd : 1; uint64_t cq : 20; - uint64_t rsvd_36_24 : 13; + uint64_t rsvd_34_24 : 11; + uint64_t port_ol4_dis : 1; + uint64_t port_il4_dis : 1; uint64_t lenerr_dis : 1; uint64_t csum_il4_dis : 1; uint64_t csum_ol4_dis : 1; diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 912de11..688c70b 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -265,7 +265,9 @@ struct mbox_msghdr { msg_rsp) \ M(NIX_RX_SW_SYNC, 0x8022, nix_rx_sw_sync, msg_req, msg_rsp) \ M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \ - msg_req, nix_inline_ipsec_cfg) + msg_req, nix_inline_ipsec_cfg) \ + M(NIX_LF_INLINE_RQ_CFG, 0x8024, nix_lf_inline_rq_cfg, \ + nix_rq_cpt_field_mask_cfg_req, msg_rsp) /* Messages initiated by AF (range 0xC00 - 0xDFF) */ #define MBOX_UP_CGX_MESSAGES \ @@ -1088,6 +1090,25 @@ struct nix_mark_format_cfg_rsp { uint8_t __io mark_format_idx; }; +struct nix_rq_cpt_field_mask_cfg_req { + struct mbox_msghdr hdr; +#define RQ_CTX_MASK_MAX 6 + union { + uint64_t __io rq_ctx_word_set[RQ_CTX_MASK_MAX]; + struct nix_cn10k_rq_ctx_s rq_set; + }; + union { + uint64_t __io rq_ctx_word_mask[RQ_CTX_MASK_MAX]; + struct nix_cn10k_rq_ctx_s rq_mask; + }; + struct nix_lf_rx_ipec_cfg1_req { + uint32_t __io spb_cpt_aura; + uint8_t __io rq_mask_enable; + uint8_t __io spb_cpt_sizem1; + uint8_t __io spb_cpt_enable; + } ipsec_cfg1; +}; + struct nix_lso_format_cfg { struct mbox_msghdr hdr; uint64_t __io field_mask; diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index be0b806..cdf31b1 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -416,6 +416,70 @@ roc_nix_reassembly_configure(uint32_t max_wait_time, uint16_t max_frags) return roc_cpt_rxc_time_cfg(roc_cpt, &cfg); } +static int +nix_inl_rq_mask_cfg(struct roc_nix *roc_nix, bool enable) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct nix_rq_cpt_field_mask_cfg_req *msk_req; + struct idev_cfg *idev = idev_get_cfg(); + struct mbox *mbox = (&nix->dev)->mbox; + struct idev_nix_inl_cfg *inl_cfg; + uint64_t aura_handle; + int rc = -ENOSPC; + int i; + + if (!idev) + return rc; + + inl_cfg = &idev->inl_cfg; + msk_req = mbox_alloc_msg_nix_lf_inline_rq_cfg(mbox); + if (msk_req == NULL) + return rc; + + for (i = 0; i < RQ_CTX_MASK_MAX; i++) + msk_req->rq_ctx_word_mask[i] = 0xFFFFFFFFFFFFFFFF; + + msk_req->rq_set.len_ol3_dis = 1; + msk_req->rq_set.len_ol4_dis = 1; + msk_req->rq_set.len_il3_dis = 1; + + msk_req->rq_set.len_il4_dis = 1; + msk_req->rq_set.csum_ol4_dis = 1; + msk_req->rq_set.csum_il4_dis = 1; + + msk_req->rq_set.lenerr_dis = 1; + msk_req->rq_set.port_ol4_dis = 1; + msk_req->rq_set.port_il4_dis = 1; + + msk_req->rq_set.lpb_drop_ena = 0; + msk_req->rq_set.spb_drop_ena = 0; + msk_req->rq_set.xqe_drop_ena = 0; + + msk_req->rq_mask.len_ol3_dis = ~(msk_req->rq_set.len_ol3_dis); + msk_req->rq_mask.len_ol4_dis = ~(msk_req->rq_set.len_ol4_dis); + msk_req->rq_mask.len_il3_dis = ~(msk_req->rq_set.len_il3_dis); + + msk_req->rq_mask.len_il4_dis = ~(msk_req->rq_set.len_il4_dis); + msk_req->rq_mask.csum_ol4_dis = ~(msk_req->rq_set.csum_ol4_dis); + msk_req->rq_mask.csum_il4_dis = ~(msk_req->rq_set.csum_il4_dis); + + msk_req->rq_mask.lenerr_dis = ~(msk_req->rq_set.lenerr_dis); + msk_req->rq_mask.port_ol4_dis = ~(msk_req->rq_set.port_ol4_dis); + msk_req->rq_mask.port_il4_dis = ~(msk_req->rq_set.port_il4_dis); + + msk_req->rq_mask.lpb_drop_ena = ~(msk_req->rq_set.lpb_drop_ena); + msk_req->rq_mask.spb_drop_ena = ~(msk_req->rq_set.spb_drop_ena); + msk_req->rq_mask.xqe_drop_ena = ~(msk_req->rq_set.xqe_drop_ena); + + aura_handle = roc_npa_zero_aura_handle(); + msk_req->ipsec_cfg1.spb_cpt_aura = roc_npa_aura_handle_to_aura(aura_handle); + msk_req->ipsec_cfg1.rq_mask_enable = enable; + msk_req->ipsec_cfg1.spb_cpt_sizem1 = inl_cfg->buf_sz; + msk_req->ipsec_cfg1.spb_cpt_enable = enable; + + return mbox_process(mbox); +} + int roc_nix_inl_inb_init(struct roc_nix *roc_nix) { @@ -472,6 +536,14 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix) nix->need_meta_aura = true; idev->inl_cfg.refs++; } + + if (roc_model_is_cn10kb_a0()) { + rc = nix_inl_rq_mask_cfg(roc_nix, true); + if (rc) { + plt_err("Failed to get rq mask rc=%d", rc); + return rc; + } + } nix->inl_inb_ena = true; return 0; } @@ -481,6 +553,7 @@ roc_nix_inl_inb_fini(struct roc_nix *roc_nix) { struct idev_cfg *idev = idev_get_cfg(); struct nix *nix = roc_nix_to_nix_priv(roc_nix); + int rc; if (!nix->inl_inb_ena) return 0; @@ -496,6 +569,14 @@ roc_nix_inl_inb_fini(struct roc_nix *roc_nix) nix_inl_meta_aura_destroy(); } + if (roc_model_is_cn10kb_a0()) { + rc = nix_inl_rq_mask_cfg(roc_nix, false); + if (rc) { + plt_err("Failed to get rq mask rc=%d", rc); + return rc; + } + } + /* Flush Inbound CTX cache entries */ roc_nix_cpt_ctx_cache_sync(roc_nix); From patchwork Tue Aug 9 18:49:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 114782 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6A720A04FD; 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Tue, 09 Aug 2022 11:50:49 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 9 Aug 2022 11:50:47 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 9 Aug 2022 11:50:47 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 8B4073F7086; Tue, 9 Aug 2022 11:50:45 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Kommula Shiva Shankar Subject: [PATCH 22/23] common/cnxk: add CQ limit associated with SQ Date: Wed, 10 Aug 2022 00:19:06 +0530 Message-ID: <20220809184908.24030-22-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220809184908.24030-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: i2s3d9iqh_-PEcs_uekfOZo6xMY2ylri X-Proofpoint-GUID: i2s3d9iqh_-PEcs_uekfOZo6xMY2ylri X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Kommula Shiva Shankar Update cq threshold limit associated with sq Signed-off-by: Kommula Shiva Shankar --- drivers/common/cnxk/roc_nix.h | 1 + drivers/common/cnxk/roc_nix_queue.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 8fd5990..2fddb20 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -340,6 +340,7 @@ struct roc_nix_sq { uint32_t nb_desc; uint16_t qid; uint16_t cqid; + uint16_t cq_drop_thresh; bool sso_ena; bool cq_ena; /* End of Input parameters */ diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index b197de0..6030332 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -907,6 +907,7 @@ sq_cn9k_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum, aq->sq.sso_ena = !!sq->sso_ena; aq->sq.cq_ena = !!sq->cq_ena; aq->sq.cq = sq->cqid; + aq->sq.cq_limit = sq->cq_drop_thresh; if (aq->sq.max_sqe_size == NIX_MAXSQESZ_W8) aq->sq.sqe_stype = NIX_STYPE_STP; aq->sq.sqb_aura = roc_npa_aura_handle_to_aura(sq->aura_handle); @@ -1024,6 +1025,7 @@ sq_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum, aq->sq.sso_ena = !!sq->sso_ena; aq->sq.cq_ena = !!sq->cq_ena; aq->sq.cq = sq->cqid; + aq->sq.cq_limit = sq->cq_drop_thresh; if (aq->sq.max_sqe_size == NIX_MAXSQESZ_W8) aq->sq.sqe_stype = NIX_STYPE_STP; aq->sq.sqb_aura = roc_npa_aura_handle_to_aura(sq->aura_handle); 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Tue, 9 Aug 2022 11:50:50 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 6559E3F7085; Tue, 9 Aug 2022 11:50:48 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Kommula Shiva Shankar Subject: [PATCH 23/23] common/cnxk: support Tx compl event via RQ to CQ mapping Date: Wed, 10 Aug 2022 00:19:07 +0530 Message-ID: <20220809184908.24030-23-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220809184908.24030-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 31dY_f6U8EgZR3_GsgiF97zPMRdqAHDT X-Proofpoint-GUID: 31dY_f6U8EgZR3_GsgiF97zPMRdqAHDT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Kommula Shiva Shankar This patch adds RoC support for Tx completion events via RQ to CQ mapping. Signed-off-by: Kommula Shiva Shankar --- drivers/common/cnxk/roc_nix.c | 5 ++++- drivers/common/cnxk/roc_nix.h | 2 ++ drivers/common/cnxk/roc_nix_queue.c | 7 ++----- drivers/net/cnxk/cnxk_ethdev.c | 3 +++ 4 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c index 151d8c3..4bb306b 100644 --- a/drivers/common/cnxk/roc_nix.c +++ b/drivers/common/cnxk/roc_nix.c @@ -154,7 +154,10 @@ roc_nix_lf_alloc(struct roc_nix *roc_nix, uint32_t nb_rxq, uint32_t nb_txq, return rc; req->rq_cnt = nb_rxq; req->sq_cnt = nb_txq; - req->cq_cnt = nb_rxq; + if (roc_nix->tx_compl_ena) + req->cq_cnt = nb_rxq + nb_txq; + else + req->cq_cnt = nb_rxq; /* XQESZ can be W64 or W16 */ req->xqe_sz = NIX_XQESZ_W16; req->rss_sz = nix->reta_sz; diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 2fddb20..3366080 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -281,6 +281,7 @@ struct roc_nix_stats_queue { struct roc_nix_rq { /* Input parameters */ uint16_t qid; + uint16_t cqid; /* Not valid when SSO is enabled */ uint16_t bpf_id; uint64_t aura_handle; bool ipsech_ena; @@ -406,6 +407,7 @@ struct roc_nix { uint16_t max_sqb_count; enum roc_nix_rss_reta_sz reta_sz; bool enable_loop; + bool tx_compl_ena; bool hw_vlan_ins; uint8_t lock_rx_ctx; uint16_t sqb_slack; diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index 6030332..405d9a8 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -268,7 +268,7 @@ nix_rq_cn9k_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, aq->rq.good_utag = rq->tag_mask >> 24; aq->rq.bad_utag = rq->tag_mask >> 24; aq->rq.ltag = rq->tag_mask & BITMASK_ULL(24, 0); - aq->rq.cq = rq->qid; + aq->rq.cq = rq->cqid; } if (rq->ipsech_ena) @@ -395,7 +395,7 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg, aq->rq.good_utag = rq->tag_mask >> 24; aq->rq.bad_utag = rq->tag_mask >> 24; aq->rq.ltag = rq->tag_mask & BITMASK_ULL(24, 0); - aq->rq.cq = rq->qid; + aq->rq.cq = rq->cqid; } if (rq->ipsech_ena) { @@ -644,9 +644,6 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq) if (cq == NULL) return NIX_ERR_PARAM; - if (cq->qid >= nix->nb_rx_queues) - return NIX_ERR_QUEUE_INVALID_RANGE; - qsize = nix_qsize_clampup(cq->nb_desc); cq->nb_desc = nix_qsize_to_val(qsize); cq->qmask = cq->nb_desc - 1; diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index f08a20f..eb562ec 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -606,6 +606,7 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, /* Setup ROC RQ */ rq = &dev->rqs[qid]; rq->qid = qid; + rq->cqid = cq->qid; rq->aura_handle = mp->pool_id; rq->flow_tag_width = 32; rq->sso_ena = false; @@ -1168,6 +1169,8 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev) if (roc_nix_is_lbk(nix)) nix->enable_loop = eth_dev->data->dev_conf.lpbk_mode; + nix->tx_compl_ena = 0; + /* Alloc a nix lf */ rc = roc_nix_lf_alloc(nix, nb_rxq, nb_txq, rx_cfg); if (rc) {