From patchwork Sat Jun 4 16:26:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 112315 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 00A73A034C; Sat, 4 Jun 2022 18:27:21 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D7E5041155; Sat, 4 Jun 2022 18:27:16 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 1A072410D5 for ; Sat, 4 Jun 2022 18:27:16 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 254GRF5u032547; Sat, 4 Jun 2022 09:27:15 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=/0gmQBGeSSIBtiTkbYSHlXBh8hh+1AMWC5JbKIx3qP0=; b=JQMjXbZjERLd9g/n9HSIWsxkBL9RqYq3jgs1/seGPL8EoAgQAJ3SrOYNphAkkYvelbmo lX6ZHLYml0vo6NeZnbkizMNhLQ+asIFiZE1jg0B5ETNn/nk+zCnxjpmszMtVsZVl6RJZ q18R62P2QmLhXyTIVUzANbp+cIAf9vyB1hoMSGy6+MZTwtSG9Un2vajo5zgaZlOnPIeA 4ozLY6AFPmbblezsjdSi7NCDsoDABRV5fIegCGnxfobbSy+BNb91JG3zGGlHm48/MYaX qzMyDzrZQc125MraBuXlTy2L3daMiMiHnxm+F5lfx3I/Bluz0ZzZ/Y9m39SYDn7Awu6t Jw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3gg6wq0dgt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sat, 04 Jun 2022 09:27:15 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sat, 4 Jun 2022 09:27:13 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 4 Jun 2022 09:27:13 -0700 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id E4BC53F70AB; Sat, 4 Jun 2022 09:27:10 -0700 (PDT) From: Tomasz Duszynski To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Tomasz Duszynski , Jakub Palider Subject: [PATCH 01/10] common/cnxk: update register access for CNF10xxN Date: Sat, 4 Jun 2022 18:26:42 +0200 Message-ID: <20220604162651.3503338-2-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220604162651.3503338-1-tduszynski@marvell.com> References: <20220604162651.3503338-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: OH569jmjlkaBeG1N0VhHsAaF7B5mx9IR X-Proofpoint-GUID: OH569jmjlkaBeG1N0VhHsAaF7B5mx9IR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-04_05,2022-06-03_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Due to HW changes some fields which were used to enable xmit were moved elsewhere. This patch takes care of this. Signed-off-by: Tomasz Duszynski Reviewed-by: Jakub Palider Reviewed-by: Jerin Jacob Kollanukkaran Tested-by: Jerin Jacob Kollanukkaran --- drivers/common/cnxk/roc_bphy_cgx.c | 33 ++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 11 deletions(-) diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c index c3be3c9041..19baaa6757 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.c +++ b/drivers/common/cnxk/roc_bphy_cgx.c @@ -21,10 +21,13 @@ * * Hence common longer mask may be used. */ -#define CGX_CMRX_RX_LMACS 0x128 -#define CGX_CMRX_RX_LMACS_LMACS GENMASK_ULL(3, 0) -#define CGX_CMRX_SCRATCH0 0x1050 -#define CGX_CMRX_SCRATCH1 0x1058 +#define CGX_CMRX_RX_LMACS 0x128 +#define CGX_CMRX_RX_LMACS_LMACS GENMASK_ULL(3, 0) +#define CGX_CMRX_SCRATCH0 0x1050 +#define CGX_CMRX_SCRATCH1 0x1058 +#define CGX_MTI_MAC100X_COMMAND_CONFIG 0x8010 +#define CGX_MTI_MAC100X_COMMAND_CONFIG_RX_ENA BIT_ULL(1) +#define CGX_MTI_MAC100X_COMMAND_CONFIG_TX_ENA BIT_ULL(0) static uint64_t roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset) @@ -221,7 +224,7 @@ static int roc_bphy_cgx_start_stop_rxtx(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, bool start) { - uint64_t val; + uint64_t val, reg, rx_field, tx_field; if (!roc_cgx) return -EINVAL; @@ -229,16 +232,24 @@ roc_bphy_cgx_start_stop_rxtx(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac)) return -ENODEV; + if (roc_model_is_cnf10kb()) { + reg = CGX_MTI_MAC100X_COMMAND_CONFIG; + rx_field = CGX_MTI_MAC100X_COMMAND_CONFIG_RX_ENA; + tx_field = CGX_MTI_MAC100X_COMMAND_CONFIG_TX_ENA; + } else { + reg = CGX_CMRX_CONFIG; + rx_field = CGX_CMRX_CONFIG_DATA_PKT_RX_EN; + tx_field = CGX_CMRX_CONFIG_DATA_PKT_TX_EN; + } + pthread_mutex_lock(&roc_cgx->lock); - val = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_CONFIG); - val &= ~(CGX_CMRX_CONFIG_DATA_PKT_RX_EN | - CGX_CMRX_CONFIG_DATA_PKT_TX_EN); + val = roc_bphy_cgx_read(roc_cgx, lmac, reg); + val &= ~(rx_field | tx_field); if (start) - val |= FIELD_PREP(CGX_CMRX_CONFIG_DATA_PKT_RX_EN, 1) | - FIELD_PREP(CGX_CMRX_CONFIG_DATA_PKT_TX_EN, 1); + val |= FIELD_PREP(rx_field, 1) | FIELD_PREP(tx_field, 1); - roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_CONFIG, val); + roc_bphy_cgx_write(roc_cgx, lmac, reg, val); pthread_mutex_unlock(&roc_cgx->lock); return 0; From patchwork Sat Jun 4 16:26:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 112316 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 30C34A034C; Sat, 4 Jun 2022 18:27:27 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C8F89427F0; Sat, 4 Jun 2022 18:27:22 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id A6E9640041 for ; Sat, 4 Jun 2022 18:27:20 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 254GRJMw012868; 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Sat, 4 Jun 2022 09:27:18 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 4 Jun 2022 09:27:18 -0700 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id 0BBC33F70AC; Sat, 4 Jun 2022 09:27:13 -0700 (PDT) From: Tomasz Duszynski To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Tomasz Duszynski , Jakub Palider Subject: [PATCH 02/10] common/cnxk: use wider mask to extract RPM ID Date: Sat, 4 Jun 2022 18:26:43 +0200 Message-ID: <20220604162651.3503338-3-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220604162651.3503338-1-tduszynski@marvell.com> References: <20220604162651.3503338-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: QYZBM0PIt8LeWDhOzTzcOOj_ElMfKHBP X-Proofpoint-GUID: QYZBM0PIt8LeWDhOzTzcOOj_ElMfKHBP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-04_05,2022-06-03_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Some platforms have more RPMs available than the others. Take than into account when retrieving id of a particular RPM. Signed-off-by: Tomasz Duszynski Reviewed-by: Jakub Palider Reviewed-by: Jerin Jacob Kollanukkaran Tested-by: Jerin Jacob Kollanukkaran --- drivers/common/cnxk/roc_bphy_cgx.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c index 19baaa6757..a0a0d22f85 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.c +++ b/drivers/common/cnxk/roc_bphy_cgx.c @@ -173,8 +173,14 @@ roc_bphy_cgx_intf_req(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, static unsigned int roc_bphy_cgx_dev_id(struct roc_bphy_cgx *roc_cgx) { - uint64_t cgx_id = roc_model_is_cn10k() ? GENMASK_ULL(26, 24) : - GENMASK_ULL(25, 24); + uint64_t cgx_id; + + if (roc_model_is_cnf10kb()) + cgx_id = GENMASK_ULL(27, 24); + else if (roc_model_is_cn10k()) + cgx_id = GENMASK_ULL(26, 24); + else + cgx_id = GENMASK_ULL(25, 24); return FIELD_GET(cgx_id, roc_cgx->bar0_pa); } From patchwork Sat Jun 4 16:26:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 112317 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 465E2A034C; Sat, 4 Jun 2022 18:27:33 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AD8D64280D; Sat, 4 Jun 2022 18:27:24 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 844E140041 for ; Sat, 4 Jun 2022 18:27:22 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 254GRF5v032547; Sat, 4 Jun 2022 09:27:22 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=/A3Kk9+5f56kPV5q/KpwtcuwnBSm71MCYPTCk4aAmyE=; b=EnMBLbKqpMEMec9vNvOAd83Ty02j/lbWpVtJMGaDqkmmQGDcIEP8TAByIG17f9G9vmrO z0xU+F5pMQV2TJL4gdFpJ2UAQ1xqr5z8cnGn4WBp5UOT8tXRARVWMtigepEMawl+/r3L JI1x9OlbTC+S9s6TbTseiiKN/2uPDtU3StSQuudykwkQhAgOuVR+3t7vd440vqENdwKQ gIlrnZ+lX2VozbZl5YwlPAzj2qLrb/4weGjxZyArV+8yZmvcOZKA3OjYPCQqK2wuyzvq 1n0CFFh359mK94toA/z5F20YpKCRq9pi0zgSg7+Jk/G1L6Shk3lyaPe/9KS426hN6KRb QQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3gg6wq0dgy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sat, 04 Jun 2022 09:27:21 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 4 Jun 2022 09:27:19 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 4 Jun 2022 09:27:19 -0700 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id 2E7DF5E6885; Sat, 4 Jun 2022 09:27:16 -0700 (PDT) From: Tomasz Duszynski To: , Jakub Palider , Tomasz Duszynski CC: , Subject: [PATCH 03/10] raw/cnxk_bphy: add doxygen comments Date: Sat, 4 Jun 2022 18:26:44 +0200 Message-ID: <20220604162651.3503338-4-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220604162651.3503338-1-tduszynski@marvell.com> References: <20220604162651.3503338-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: dVJbrXD6TCtd553vpCMsR3wupG1hZp1E X-Proofpoint-GUID: dVJbrXD6TCtd553vpCMsR3wupG1hZp1E X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-04_05,2022-06-03_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Jakub Palider Documentation in doxygen format is important for API headers used by end user. This patch fills BPHY and CGX interface with missing bits. Signed-off-by: Jakub Palider Reviewed-by: Jerin Jacob Kollanukkaran --- drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 339 +++++++++++++++++++++++++-- 1 file changed, 318 insertions(+), 21 deletions(-) diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h index cc2372f719..db8a13a4f8 100644 --- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h +++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h @@ -13,103 +13,169 @@ #include #include +/** + * @file rte_pmd_bphy.h + * + * Marvell CGX and BPHY PMD specific structures and interface + * + * This API allows applications to manage BPHY memory in user space along with + * installing interrupt handlers for low latency signal processing. + */ + #ifdef __cplusplus extern "C" { #endif +/** Available message types */ enum cnxk_bphy_cgx_msg_type { + /** Type used to obtain link information */ CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO, + /** Type used to disable internal loopback */ CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE, + /** Type used to enable loopback */ CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE, + /** Type used to disable PTP on RX */ CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE, + /** Type used to enable PTP on RX */ CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE, + /** Type used to set link mode */ CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE, + /** Type used to set link state */ CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE, + /** Type used to start transmission and packet reception */ CNXK_BPHY_CGX_MSG_TYPE_START_RXTX, + /** Type used to stop transmission and packet reception */ CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX, + /** Type used to obtain supported FEC */ CNXK_BPHY_CGX_MSG_TYPE_GET_SUPPORTED_FEC, + /** Type used to set FEC */ CNXK_BPHY_CGX_MSG_TYPE_SET_FEC, }; +/** Available link speeds */ enum cnxk_bphy_cgx_eth_link_speed { - CNXK_BPHY_CGX_ETH_LINK_SPEED_NONE, - CNXK_BPHY_CGX_ETH_LINK_SPEED_10M, - CNXK_BPHY_CGX_ETH_LINK_SPEED_100M, - CNXK_BPHY_CGX_ETH_LINK_SPEED_1G, - CNXK_BPHY_CGX_ETH_LINK_SPEED_2HG, - CNXK_BPHY_CGX_ETH_LINK_SPEED_5G, - CNXK_BPHY_CGX_ETH_LINK_SPEED_10G, - CNXK_BPHY_CGX_ETH_LINK_SPEED_20G, - CNXK_BPHY_CGX_ETH_LINK_SPEED_25G, - CNXK_BPHY_CGX_ETH_LINK_SPEED_40G, - CNXK_BPHY_CGX_ETH_LINK_SPEED_50G, - CNXK_BPHY_CGX_ETH_LINK_SPEED_80G, - CNXK_BPHY_CGX_ETH_LINK_SPEED_100G, + CNXK_BPHY_CGX_ETH_LINK_SPEED_NONE, /**< None */ + CNXK_BPHY_CGX_ETH_LINK_SPEED_10M, /**< 10 Mbps */ + CNXK_BPHY_CGX_ETH_LINK_SPEED_100M, /**< 100 Mbps */ + CNXK_BPHY_CGX_ETH_LINK_SPEED_1G, /**< 1 Gbps */ + CNXK_BPHY_CGX_ETH_LINK_SPEED_2HG, /**< 2.5 Gbps */ + CNXK_BPHY_CGX_ETH_LINK_SPEED_5G, /**< 5 Gbps */ + CNXK_BPHY_CGX_ETH_LINK_SPEED_10G, /**< 10 Gbps */ + CNXK_BPHY_CGX_ETH_LINK_SPEED_20G, /**< 20 Gbps */ + CNXK_BPHY_CGX_ETH_LINK_SPEED_25G, /**< 25 Gbps */ + CNXK_BPHY_CGX_ETH_LINK_SPEED_40G, /**< 40 Gbps */ + CNXK_BPHY_CGX_ETH_LINK_SPEED_50G, /**< 50 Gbps */ + CNXK_BPHY_CGX_ETH_LINK_SPEED_80G, /**< 80 Gbps */ + CNXK_BPHY_CGX_ETH_LINK_SPEED_100G, /**< 100 Gbps */ __CNXK_BPHY_CGX_ETH_LINK_SPEED_MAX }; +/** Available FEC modes */ enum cnxk_bphy_cgx_eth_link_fec { + /** Disable FEC */ CNXK_BPHY_CGX_ETH_LINK_FEC_NONE, + /** Base FEC (IEEE 802.3 CLause 74) */ CNXK_BPHY_CGX_ETH_LINK_FEC_BASE_R, + /** Reed-Solomon FEC */ CNXK_BPHY_CGX_ETH_LINK_FEC_RS, __CNXK_BPHY_CGX_ETH_LINK_FEC_MAX }; +/** Available link modes */ enum cnxk_bphy_cgx_eth_link_mode { + /** SGMII */ CNXK_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT, + /** 1000BASE-X */ CNXK_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT, + /** QSGMII */ CNXK_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT, + /** 10GBASE-C2C */ CNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT, + /** 10GBASE-C2M */ CNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT, + /** 10GBASE-KR */ CNXK_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT, + /** 20GBASE-C2C */ CNXK_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT, + /** 25GBASE-C2C */ CNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT, + /** 25GBASE-C2M */ CNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT, + /** 25GBASE-2-C2M */ CNXK_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT, + /** 25GBASE-CR */ CNXK_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT, + /** 25GBASE-KR */ CNXK_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT, + /** 40GBASE-C2C */ CNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT, + /** 40GBASE-C2M */ CNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT, + /** 40GBASE-CR4 */ CNXK_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT, + /** 40GBASE-KR4 */ CNXK_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT, + /** 40GAUI-C2C */ CNXK_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT, + /** 50GBASE-C2C */ CNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT, + /** 50GBASE-C2M */ CNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT, + /** 50GBASE-4-C2C */ CNXK_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT, + /** 50GBASE-CR */ CNXK_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT, + /** 50GBASE-KR */ CNXK_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT, + /** 80GAUI-C2C */ CNXK_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT, + /** 100GBASE-C2C */ CNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT, + /** 100GBASE-C2M */ CNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT, + /** 100GBASE-CR4 */ CNXK_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT, + /** 100GBASE-KR4 */ CNXK_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT, __CNXK_BPHY_CGX_ETH_LINK_MODE_MAX }; struct cnxk_bphy_cgx_msg_link_mode { + /** Setting for full-duplex */ bool full_duplex; + /** Setting for automatic link negotiation */ bool autoneg; + /** Link speed */ enum cnxk_bphy_cgx_eth_link_speed speed; + /** Link mode */ enum cnxk_bphy_cgx_eth_link_mode mode; }; struct cnxk_bphy_cgx_msg_link_info { + /** Link state information */ bool link_up; + /** Link full duplex state */ bool full_duplex; + /** Link speed */ enum cnxk_bphy_cgx_eth_link_speed speed; + /** Link auto-negotiation setting */ bool autoneg; + /** FEC mode */ enum cnxk_bphy_cgx_eth_link_fec fec; + /** Link configuration */ enum cnxk_bphy_cgx_eth_link_mode mode; }; struct cnxk_bphy_cgx_msg_set_link_state { + /** Defines link state result */ bool state; /* up or down */ }; struct cnxk_bphy_cgx_msg { + /** Message type */ enum cnxk_bphy_cgx_msg_type type; - /* - * data depends on message type and whether + /** + * Data depends on message type and whether * it's a request or a response */ void *data; @@ -117,42 +183,63 @@ struct cnxk_bphy_cgx_msg { #define CNXK_BPHY_DEF_QUEUE 0 +/** + * BPHY interrupt handler + * + * @param irq_num + * Zero-based interrupt number + * @param isr_data + * Cookie passed to interrupt handler + */ typedef void (*cnxk_bphy_intr_handler_t)(int irq_num, void *isr_data); struct cnxk_bphy_mem { + /** Memory for BAR0 */ struct rte_mem_resource res0; + /** Memory for BAR2 */ struct rte_mem_resource res2; }; +/** Available IRQ configuration commands */ enum cnxk_bphy_irq_msg_type { + /** Type used to initialize interrupts */ CNXK_BPHY_IRQ_MSG_TYPE_INIT, + /** Type used to deinitialize interrupts */ CNXK_BPHY_IRQ_MSG_TYPE_FINI, + /** Type used to register interrupt */ CNXK_BPHY_IRQ_MSG_TYPE_REGISTER, + /** Type used to unregister interrupt */ CNXK_BPHY_IRQ_MSG_TYPE_UNREGISTER, + /** Type used to retrieve BPHY memory */ CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET, + /** Type used to retrieve NPA PF function */ CNXK_BPHY_MSG_TYPE_NPA_PF_FUNC, + /** Type used to retrieve NPA SSO function */ CNXK_BPHY_MSG_TYPE_SSO_PF_FUNC, }; struct cnxk_bphy_irq_msg { + /** Message command type */ enum cnxk_bphy_irq_msg_type type; - /* - * The data field, depending on message type, may point to - * - (enq) full struct cnxk_bphy_irq_info for registration request - * - (enq) struct cnxk_bphy_irq_info with irq_num set for unregistration - * - (deq) struct cnxk_bphy_mem for memory range request response - * - (xxx) NULL + /** + * Data depends on message type and whether + * it is a request or a response */ void *data; }; struct cnxk_bphy_irq_info { + /** Interrupt number */ int irq_num; + /** Interrupt handler */ cnxk_bphy_intr_handler_t handler; + /** Interrupt handler cookie */ void *data; + /** CPU zero-based number for interrupt execution */ int cpu; }; +/** @internal helper routine for enqueuing/dequeuing messages */ static __rte_always_inline int __rte_pmd_bphy_enq_deq(uint16_t dev_id, unsigned int queue, void *req, void *rsp, size_t rsp_size) @@ -187,6 +274,15 @@ __rte_pmd_bphy_enq_deq(uint16_t dev_id, unsigned int queue, void *req, return 0; } +/** + * Initialize BPHY subsystem + * + * @param dev_id + * The identifier of the device + * + * @return + * Returns 0 on success, negative error code otherwise + */ static __rte_always_inline int rte_pmd_bphy_intr_init(uint16_t dev_id) { @@ -198,6 +294,15 @@ rte_pmd_bphy_intr_init(uint16_t dev_id) NULL, 0); } +/** + * Deinitialize BPHY subsystem + * + * @param dev_id + * The identifier of the device + * + * @return + * Returns 0 on success, negative error code otherwise + */ static __rte_always_inline int rte_pmd_bphy_intr_fini(uint16_t dev_id) { @@ -209,6 +314,23 @@ rte_pmd_bphy_intr_fini(uint16_t dev_id) NULL, 0); } +/** + * Register BPHY interrupt handler + * + * @param dev_id + * The identifier of the device + * @param irq_num + * Zero-based interrupt number + * @param handler + * Interrupt handler to be executed + * @param data + * Data to be passed to interrupt handler + * @param cpu + * CPU number which will be handling interrupt + * + * @return + * Returns 0 on success, negative error code otherwise + */ static __rte_always_inline int rte_pmd_bphy_intr_register(uint16_t dev_id, int irq_num, cnxk_bphy_intr_handler_t handler, void *data, @@ -229,6 +351,17 @@ rte_pmd_bphy_intr_register(uint16_t dev_id, int irq_num, NULL, 0); } +/** + * Unregister BPHY interrupt handler + * + * @param dev_id + * The identifier of the device + * @param irq_num + * Zero-based interrupt number used during registration + * + * @return + * Returns 0 on success, negative error code otherwise + */ static __rte_always_inline int rte_pmd_bphy_intr_unregister(uint16_t dev_id, int irq_num) { @@ -244,6 +377,17 @@ rte_pmd_bphy_intr_unregister(uint16_t dev_id, int irq_num) NULL, 0); } +/** + * Obtain BPHY memory + * + * @param dev_id + * The identifier of the device + * @param mem + * Memory structure which will be filled for memory access + * + * @return + * Returns 0 on success, negative error code otherwise + */ static __rte_always_inline int rte_pmd_bphy_intr_mem_get(uint16_t dev_id, struct cnxk_bphy_mem *mem) { @@ -255,6 +399,17 @@ rte_pmd_bphy_intr_mem_get(uint16_t dev_id, struct cnxk_bphy_mem *mem) mem, sizeof(*mem)); } +/** + * Obtain NPA PF func + * + * @param dev_id + * The identifier of the device + * @param pf_func + * NPA PF function to obtain + * + * @return + * Returns 0 on success, negative error code otherwise + */ static __rte_always_inline int rte_pmd_bphy_npa_pf_func_get(uint16_t dev_id, uint16_t *pf_func) { @@ -266,6 +421,17 @@ rte_pmd_bphy_npa_pf_func_get(uint16_t dev_id, uint16_t *pf_func) pf_func, sizeof(*pf_func)); } +/** + * Obtain SSO PF func + * + * @param dev_id + * The identifier of the device + * @param pf_func + * SSO PF function to obtain + * + * @return + * Returns 0 on success, negative error code otherwise + */ static __rte_always_inline int rte_pmd_bphy_sso_pf_func_get(uint16_t dev_id, uint16_t *pf_func) { @@ -277,6 +443,19 @@ rte_pmd_bphy_sso_pf_func_get(uint16_t dev_id, uint16_t *pf_func) pf_func, sizeof(*pf_func)); } +/** + * Obtain link information + * + * @param dev_id + * The identifier of the device + * @param lmac + * LMAC number for operation + * @param info + * Link information structure + * + * @return + * Returns 0 on success, negative error code otherwise + */ static __rte_always_inline int rte_pmd_bphy_cgx_get_link_info(uint16_t dev_id, uint16_t lmac, struct cnxk_bphy_cgx_msg_link_info *info) @@ -288,6 +467,17 @@ rte_pmd_bphy_cgx_get_link_info(uint16_t dev_id, uint16_t lmac, return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, info, sizeof(*info)); } +/** + * Disable loopback mode for an interface + * + * @param dev_id + * The identifier of the device + * @param lmac + * LMAC number for operation + * + * @return + * Returns 0 on success, negative error code otherwise + */ static __rte_always_inline int rte_pmd_bphy_cgx_intlbk_disable(uint16_t dev_id, uint16_t lmac) { @@ -298,6 +488,17 @@ rte_pmd_bphy_cgx_intlbk_disable(uint16_t dev_id, uint16_t lmac) return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); } +/** + * Enable loopback mode for an interface + * + * @param dev_id + * The identifier of the device + * @param lmac + * LMAC number for operation + * + * @return + * Returns 0 on success, negative error code otherwise + */ static __rte_always_inline int rte_pmd_bphy_cgx_intlbk_enable(uint16_t dev_id, uint16_t lmac) { @@ -308,6 +509,17 @@ rte_pmd_bphy_cgx_intlbk_enable(uint16_t dev_id, uint16_t lmac) return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); } +/** + * Disable PTP on RX path + * + * @param dev_id + * The identifier of the device + * @param lmac + * LMAC number for operation + * + * @return + * Returns 0 on success, negative error code otherwise + */ static __rte_always_inline int rte_pmd_bphy_cgx_ptp_rx_disable(uint16_t dev_id, uint16_t lmac) { @@ -318,6 +530,17 @@ rte_pmd_bphy_cgx_ptp_rx_disable(uint16_t dev_id, uint16_t lmac) return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); } +/** + * Enable PTP on RX path + * + * @param dev_id + * The identifier of the device + * @param lmac + * LMAC number for operation + * + * @return + * Returns 0 on success, negative error code otherwise + */ static __rte_always_inline int rte_pmd_bphy_cgx_ptp_rx_enable(uint16_t dev_id, uint16_t lmac) { @@ -328,6 +551,19 @@ rte_pmd_bphy_cgx_ptp_rx_enable(uint16_t dev_id, uint16_t lmac) return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); } +/** + * Set link mode for a CGX + * + * @param dev_id + * The identifier of the device + * @param lmac + * LMAC number for operation + * @param mode + * Link mode to set + * + * @return + * Returns 0 on success, negative error code otherwise + */ static __rte_always_inline int rte_pmd_bphy_cgx_set_link_mode(uint16_t dev_id, uint16_t lmac, struct cnxk_bphy_cgx_msg_link_mode *mode) @@ -340,6 +576,19 @@ rte_pmd_bphy_cgx_set_link_mode(uint16_t dev_id, uint16_t lmac, return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); } +/** + * Set link state for a CGX + * + * @param dev_id + * The identifier of the device + * @param lmac + * LMAC number for operation + * @param up + * Link state to set + * + * @return + * Returns 0 on success, negative error code otherwise + */ static __rte_always_inline int rte_pmd_bphy_cgx_set_link_state(uint16_t dev_id, uint16_t lmac, bool up) { @@ -354,6 +603,17 @@ rte_pmd_bphy_cgx_set_link_state(uint16_t dev_id, uint16_t lmac, bool up) return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); } +/** + * Start CGX + * + * @param dev_id + * The identifier of the device + * @param lmac + * LMAC number for operation + * + * @return + * Returns 0 on success, negative error code otherwise + */ static __rte_always_inline int rte_pmd_bphy_cgx_start_rxtx(uint16_t dev_id, uint16_t lmac) { @@ -364,6 +624,17 @@ rte_pmd_bphy_cgx_start_rxtx(uint16_t dev_id, uint16_t lmac) return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); } +/** + * Stop CGX + * + * @param dev_id + * The identifier of the device + * @param lmac + * LMAC number for operation + * + * @return + * Returns 0 on success, negative error code otherwise + */ static __rte_always_inline int rte_pmd_bphy_cgx_stop_rxtx(uint16_t dev_id, uint16_t lmac) { @@ -374,6 +645,19 @@ rte_pmd_bphy_cgx_stop_rxtx(uint16_t dev_id, uint16_t lmac) return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); } +/** + * Get supported list FEC mode + * + * @param dev_id + * The identifier of the device + * @param lmac + * LMAC number for operation + * @param fec + * FEC structure which holds information + * + * @return + * Returns 0 on success, negative error code otherwise + */ static __rte_always_inline int rte_pmd_bphy_cgx_get_supported_fec(uint16_t dev_id, uint16_t lmac, enum cnxk_bphy_cgx_eth_link_fec *fec) @@ -385,6 +669,19 @@ rte_pmd_bphy_cgx_get_supported_fec(uint16_t dev_id, uint16_t lmac, return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, fec, sizeof(*fec)); } +/** + * Set FEC mode for a device + * + * @param dev_id + * The identifier of the device + * @param lmac + * LMAC number for operation + * @param fec + * FEC structure which holds information to set + * + * @return + * Returns 0 on success, negative error code otherwise + */ static __rte_always_inline int rte_pmd_bphy_cgx_set_fec(uint16_t dev_id, uint16_t lmac, enum cnxk_bphy_cgx_eth_link_fec fec) From patchwork Sat Jun 4 16:26:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 112318 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B3A10A034C; Sat, 4 Jun 2022 18:27:41 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CFC9542B6C; Sat, 4 Jun 2022 18:27:26 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 7860742802 for ; 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Sat, 04 Jun 2022 09:27:23 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 4 Jun 2022 09:27:22 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 4 Jun 2022 09:27:22 -0700 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id 615623F7097; Sat, 4 Jun 2022 09:27:19 -0700 (PDT) From: Tomasz Duszynski To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Tomasz Duszynski , Jakub Palider Subject: [PATCH 04/10] common/cnxk: don't switch affinity back and forth Date: Sat, 4 Jun 2022 18:26:45 +0200 Message-ID: <20220604162651.3503338-5-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220604162651.3503338-1-tduszynski@marvell.com> References: <20220604162651.3503338-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: uB29Bo8-6_OEmh1UQrmrgB79MLvoXGXT X-Proofpoint-GUID: uB29Bo8-6_OEmh1UQrmrgB79MLvoXGXT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-04_05,2022-06-03_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Switching affinity back and forth was used as a mean to pass cpu number to irq registration routine which is an overkill. Simplify current logic by extending irq registration routine parameter list with a cpu which should run irq handler. Signed-off-by: Tomasz Duszynski Reviewed-by: Jakub Palider Reviewed-by: Jerin Jacob Kollanukkaran --- drivers/common/cnxk/roc_bphy_irq.c | 103 +++-------------------------- 1 file changed, 9 insertions(+), 94 deletions(-) diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c index f4954d2a28..7b39b61537 100644 --- a/drivers/common/cnxk/roc_bphy_irq.c +++ b/drivers/common/cnxk/roc_bphy_irq.c @@ -11,8 +11,6 @@ #include "roc_api.h" #include "roc_bphy_irq.h" -#define roc_cpuset_t cpu_set_t - struct roc_bphy_irq_usr_data { uint64_t isr_base; uint64_t sp; @@ -222,14 +220,13 @@ roc_bphy_intr_handler(unsigned int irq_num) } static int -roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int irq_num, +roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int cpu, int irq_num, void (*isr)(int irq_num, void *isr_data), void *isr_data) { - roc_cpuset_t orig_cpuset, intr_cpuset; struct roc_bphy_irq_usr_data irq_usr; const struct plt_memzone *mz; - int i, retval, curr_cpu, rc; + int retval, rc; char *env; mz = plt_memzone_lookup(chip->mz_name); @@ -244,38 +241,11 @@ roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int irq_num, if (chip->irq_vecs[irq_num].handler != NULL) return -EINVAL; - rc = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset), - &orig_cpuset); - if (rc < 0) { - plt_err("Failed to get affinity mask"); - return rc; - } - - for (curr_cpu = -1, i = 0; i < CPU_SETSIZE; i++) - if (CPU_ISSET(i, &orig_cpuset)) - curr_cpu = i; - if (curr_cpu < 0) - return -ENOENT; - - CPU_ZERO(&intr_cpuset); - CPU_SET(curr_cpu, &intr_cpuset); - rc = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset), - &intr_cpuset); - if (rc < 0) { - plt_err("Failed to set affinity mask"); - return rc; - } - irq_usr.isr_base = (uint64_t)roc_bphy_intr_handler; - irq_usr.sp = (uint64_t)roc_bphy_irq_stack_get(curr_cpu); - irq_usr.cpu = curr_cpu; - if (irq_usr.sp == 0) { - rc = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset), - &orig_cpuset); - if (rc < 0) - plt_err("Failed to restore affinity mask"); - return rc; - } + irq_usr.sp = (uint64_t)roc_bphy_irq_stack_get(cpu); + irq_usr.cpu = cpu; + if (irq_usr.sp == 0) + return -ENOMEM; /* On simulator memory locking operation takes much time. We want * to skip this when running in such an environment. @@ -289,23 +259,18 @@ roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int irq_num, *((struct roc_bphy_irq_chip **)(mz->addr)) = chip; irq_usr.irq_num = irq_num; - chip->irq_vecs[irq_num].handler_cpu = curr_cpu; + chip->irq_vecs[irq_num].handler_cpu = cpu; chip->irq_vecs[irq_num].handler = isr; chip->irq_vecs[irq_num].isr_data = isr_data; retval = ioctl(chip->intfd, ROC_BPHY_IOC_SET_BPHY_HANDLER, &irq_usr); if (retval != 0) { - roc_bphy_irq_stack_remove(curr_cpu); + roc_bphy_irq_stack_remove(cpu); chip->irq_vecs[irq_num].handler = NULL; chip->irq_vecs[irq_num].handler_cpu = -1; } else { chip->n_handlers++; } - rc = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset), - &orig_cpuset); - if (rc < 0) - plt_warn("Failed to restore affinity mask"); - return retval; } @@ -327,7 +292,6 @@ roc_bphy_intr_max_get(struct roc_bphy_irq_chip *irq_chip) int roc_bphy_intr_clear(struct roc_bphy_irq_chip *chip, int irq_num) { - roc_cpuset_t orig_cpuset, intr_cpuset; const struct plt_memzone *mz; int retval; @@ -343,24 +307,6 @@ roc_bphy_intr_clear(struct roc_bphy_irq_chip *chip, int irq_num) if (mz == NULL) return -ENXIO; - retval = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset), - &orig_cpuset); - if (retval < 0) { - plt_warn("Failed to get affinity mask"); - CPU_ZERO(&orig_cpuset); - CPU_SET(0, &orig_cpuset); - } - - CPU_ZERO(&intr_cpuset); - CPU_SET(chip->irq_vecs[irq_num].handler_cpu, &intr_cpuset); - retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset), - &intr_cpuset); - if (retval < 0) { - plt_warn("Failed to set affinity mask"); - CPU_ZERO(&orig_cpuset); - CPU_SET(0, &orig_cpuset); - } - retval = ioctl(chip->intfd, ROC_BPHY_IOC_CLR_BPHY_HANDLER, irq_num); if (retval == 0) { roc_bphy_irq_stack_remove(chip->irq_vecs[irq_num].handler_cpu); @@ -378,14 +324,6 @@ roc_bphy_intr_clear(struct roc_bphy_irq_chip *chip, int irq_num) plt_err("Failed to clear bphy interrupt handler"); } - retval = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset), - &orig_cpuset); - if (retval < 0) { - plt_warn("Failed to restore affinity mask"); - CPU_ZERO(&orig_cpuset); - CPU_SET(0, &orig_cpuset); - } - return retval; } @@ -393,36 +331,13 @@ int roc_bphy_intr_register(struct roc_bphy_irq_chip *irq_chip, struct roc_bphy_intr *intr) { - roc_cpuset_t orig_cpuset, intr_cpuset; - int retval; int ret; if (!roc_bphy_intr_available(irq_chip, intr->irq_num)) return -ENOTSUP; - retval = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset), - &orig_cpuset); - if (retval < 0) { - plt_err("Failed to get affinity mask"); - return retval; - } - - CPU_ZERO(&intr_cpuset); - CPU_SET(intr->cpu, &intr_cpuset); - retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset), - &intr_cpuset); - if (retval < 0) { - plt_err("Failed to set affinity mask"); - return retval; - } - - ret = roc_bphy_irq_handler_set(irq_chip, intr->irq_num, + ret = roc_bphy_irq_handler_set(irq_chip, intr->cpu, intr->irq_num, intr->intr_handler, intr->isr_data); - retval = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset), - &orig_cpuset); - if (retval < 0) - plt_warn("Failed to restore affinity mask"); - return ret; } From patchwork Sat Jun 4 16:26:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 112322 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8E954A034C; Sat, 4 Jun 2022 18:29:31 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 820504021E; Sat, 4 Jun 2022 18:29:31 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id AB76640041 for ; Sat, 4 Jun 2022 18:29:30 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 254GMkhk022062; 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Sat, 4 Jun 2022 09:27:25 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 4 Jun 2022 09:27:25 -0700 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id 8146C3F70AB; Sat, 4 Jun 2022 09:27:22 -0700 (PDT) From: Tomasz Duszynski To: , Jakub Palider , Tomasz Duszynski , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: , Subject: [PATCH 05/10] raw/cnxk_bphy: support switching from eCPRI to CPRI Date: Sat, 4 Jun 2022 18:26:46 +0200 Message-ID: <20220604162651.3503338-6-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220604162651.3503338-1-tduszynski@marvell.com> References: <20220604162651.3503338-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: vq1neueeXiOWwo7mV7Fp2QLn_66a_Q5S X-Proofpoint-GUID: vq1neueeXiOWwo7mV7Fp2QLn_66a_Q5S X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-04_05,2022-06-03_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for switching from ethernet (eCPRI) to CPRI mode. Signed-off-by: Tomasz Duszynski Reviewed-by: Jakub Palider Reviewed-by: Jerin Jacob Kollanukkaran Acked-by: Ray Kinsella --- doc/guides/rawdevs/cnxk_bphy.rst | 11 +++++++ drivers/common/cnxk/roc_bphy_cgx.c | 33 ++++++++++++++++++++ drivers/common/cnxk/roc_bphy_cgx.h | 14 +++++++-- drivers/common/cnxk/roc_bphy_cgx_priv.h | 8 +++++ drivers/common/cnxk/roc_model.h | 24 +++++++++++++++ drivers/common/cnxk/version.map | 1 + drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 13 ++++++++ drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 40 +++++++++++++++++++++++++ 8 files changed, 141 insertions(+), 3 deletions(-) diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst index 522390bf1b..7f55e9eac6 100644 --- a/doc/guides/rawdevs/cnxk_bphy.rst +++ b/doc/guides/rawdevs/cnxk_bphy.rst @@ -100,6 +100,17 @@ Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_START_RXTX`` or ``CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX``. Former will enable traffic while the latter will do the opposite. +Change mode from eCPRI to CPRI +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Message is used to change operating mode from eCPRI to CPRI along with other +settings. + +Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_CHANGE``. +Prior to sending actual message payload i.e +``struct cnxk_bphy_cgx_msg_cpri_mode_change`` needs to be filled with relevant +information. + BPHY PMD -------- diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c index a0a0d22f85..223bd313fa 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.c +++ b/drivers/common/cnxk/roc_bphy_cgx.c @@ -455,3 +455,36 @@ roc_bphy_cgx_fec_supported_get(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, return 0; } + +int +roc_bphy_cgx_cpri_mode_change(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, + struct roc_bphy_cgx_cpri_mode_change *mode) +{ + uint64_t scr1, scr0; + + if (!(roc_model_is_cnf95xxn_a0() || + roc_model_is_cnf95xxn_a1() || + roc_model_is_cnf95xxn_b0())) + return -ENOTSUP; + + if (!roc_cgx) + return -EINVAL; + + if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac)) + return -ENODEV; + + if (!mode) + return -EINVAL; + + scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_CPRI_MODE_CHANGE) | + FIELD_PREP(SCR1_CPRI_MODE_CHANGE_ARGS_GSERC_IDX, + mode->gserc_idx) | + FIELD_PREP(SCR1_CPRI_MODE_CHANGE_ARGS_LANE_IDX, mode->lane_idx) | + FIELD_PREP(SCR1_CPRI_MODE_CHANGE_ARGS_RATE, mode->rate) | + FIELD_PREP(SCR1_CPRI_MODE_CHANGE_ARGS_DISABLE_LEQ, + mode->disable_leq) | + FIELD_PREP(SCR1_CPRI_MODE_CHANGE_ARGS_DISABLE_DFE, + mode->disable_dfe); + + return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0); +} diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h index d522d4e202..59adddd420 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.h +++ b/drivers/common/cnxk/roc_bphy_cgx.h @@ -92,6 +92,14 @@ struct roc_bphy_cgx_link_info { enum roc_bphy_cgx_eth_link_mode mode; }; +struct roc_bphy_cgx_cpri_mode_change { + int gserc_idx; + int lane_idx; + int rate; + bool disable_leq; + bool disable_dfe; +}; + __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx); __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx); @@ -118,9 +126,9 @@ __roc_api int roc_bphy_cgx_ptp_rx_disable(struct roc_bphy_cgx *roc_cgx, __roc_api int roc_bphy_cgx_fec_set(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, enum roc_bphy_cgx_eth_link_fec fec); -__roc_api int roc_bphy_cgx_fec_supported_get(struct roc_bphy_cgx *roc_cgx, - unsigned int lmac, +__roc_api int roc_bphy_cgx_fec_supported_get(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, enum roc_bphy_cgx_eth_link_fec *fec); - +__roc_api int roc_bphy_cgx_cpri_mode_change(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, + struct roc_bphy_cgx_cpri_mode_change *mode); #endif /* _ROC_BPHY_CGX_H_ */ diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h index 6a6b5a7b08..cdd94989c8 100644 --- a/drivers/common/cnxk/roc_bphy_cgx_priv.h +++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h @@ -69,6 +69,7 @@ enum eth_cmd_id { ETH_CMD_GET_SUPPORTED_FEC = 18, ETH_CMD_SET_FEC = 19, ETH_CMD_SET_PTP_MODE = 34, + ETH_CMD_CPRI_MODE_CHANGE = 35, }; /* event types - cause of interrupt */ @@ -133,6 +134,13 @@ enum eth_cmd_own { /* struct eth_set_fec_args */ #define SCR1_ETH_SET_FEC_ARGS GENMASK_ULL(9, 8) +/* struct eth_cpri_mode_change_args */ +#define SCR1_CPRI_MODE_CHANGE_ARGS_GSERC_IDX GENMASK_ULL(11, 8) +#define SCR1_CPRI_MODE_CHANGE_ARGS_LANE_IDX GENMASK_ULL(15, 12) +#define SCR1_CPRI_MODE_CHANGE_ARGS_RATE GENMASK_ULL(31, 16) +#define SCR1_CPRI_MODE_CHANGE_ARGS_DISABLE_LEQ BIT_ULL(32) +#define SCR1_CPRI_MODE_CHANGE_ARGS_DISABLE_DFE BIT_ULL(33) + #define SCR1_OWN_STATUS GENMASK_ULL(1, 0) #endif /* _ROC_BPHY_CGX_PRIV_H_ */ diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h index 4567566169..e28965d896 100644 --- a/drivers/common/cnxk/roc_model.h +++ b/drivers/common/cnxk/roc_model.h @@ -134,6 +134,30 @@ roc_model_is_cn95_a0(void) return roc_model->flag & ROC_MODEL_CNF95xx_A0; } +static inline uint64_t +roc_model_is_cnf95xxn_a0(void) +{ + return roc_model->flag & ROC_MODEL_CNF95xxN_A0; +} + +static inline uint64_t +roc_model_is_cnf95xxn_a1(void) +{ + return roc_model->flag & ROC_MODEL_CNF95xxN_A1; +} + +static inline uint64_t +roc_model_is_cnf95xxn_b0(void) +{ + return roc_model->flag & ROC_MODEL_CNF95xxN_B0; +} + +static inline uint16_t +roc_model_is_cn95xxn_a0(void) +{ + return roc_model->flag & ROC_MODEL_CNF95xxN_A0; +} + static inline uint64_t roc_model_is_cn10ka(void) { diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index a77f3f6e3c..720cad61ea 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -28,6 +28,7 @@ INTERNAL { roc_ae_fpm_get; roc_ae_fpm_put; roc_aes_xcbc_key_derive; + roc_bphy_cgx_cpri_mode_change; roc_bphy_cgx_dev_fini; roc_bphy_cgx_dev_init; roc_bphy_cgx_fec_set; diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c index 169cbc7855..803b245c78 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c @@ -56,10 +56,12 @@ cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue, struct rte_rawdev_buf *buf) { struct cnxk_bphy_cgx_queue *qp = &cgx->queues[queue]; + struct cnxk_bphy_cgx_msg_cpri_mode_change *cpri_mode; struct cnxk_bphy_cgx_msg_set_link_state *link_state; struct cnxk_bphy_cgx_msg *msg = buf->buf_addr; struct cnxk_bphy_cgx_msg_link_mode *link_mode; struct cnxk_bphy_cgx_msg_link_info *link_info; + struct roc_bphy_cgx_cpri_mode_change rcpri_mode; struct roc_bphy_cgx_link_info rlink_info; struct roc_bphy_cgx_link_mode rlink_mode; enum roc_bphy_cgx_eth_link_fec *fec; @@ -135,6 +137,17 @@ cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue, fec = msg->data; ret = roc_bphy_cgx_fec_set(cgx->rcgx, lmac, *fec); break; + case CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_CHANGE: + cpri_mode = msg->data; + memset(&rcpri_mode, 0, sizeof(rcpri_mode)); + rcpri_mode.gserc_idx = cpri_mode->gserc_idx; + rcpri_mode.lane_idx = cpri_mode->lane_idx; + rcpri_mode.rate = cpri_mode->rate; + rcpri_mode.disable_leq = cpri_mode->disable_leq; + rcpri_mode.disable_dfe = cpri_mode->disable_dfe; + ret = roc_bphy_cgx_cpri_mode_change(cgx->rcgx, lmac, + &rcpri_mode); + break; default: return -EINVAL; } diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h index db8a13a4f8..36b75aa385 100644 --- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h +++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h @@ -50,6 +50,8 @@ enum cnxk_bphy_cgx_msg_type { CNXK_BPHY_CGX_MSG_TYPE_GET_SUPPORTED_FEC, /** Type used to set FEC */ CNXK_BPHY_CGX_MSG_TYPE_SET_FEC, + /** Type used to switch from eCPRI to CPRI */ + CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_CHANGE, }; /** Available link speeds */ @@ -171,6 +173,19 @@ struct cnxk_bphy_cgx_msg_set_link_state { bool state; /* up or down */ }; +struct cnxk_bphy_cgx_msg_cpri_mode_change { + /** SERDES index (0 - 4) */ + int gserc_idx; + /** Lane index (0 - 1) */ + int lane_idx; + /** Baud rate (9830/4915/2458/6144/3072) */ + int rate; + /** Disable LEQ */ + bool disable_leq; + /** Disable DFE */ + bool disable_dfe; +}; + struct cnxk_bphy_cgx_msg { /** Message type */ enum cnxk_bphy_cgx_msg_type type; @@ -694,6 +709,31 @@ rte_pmd_bphy_cgx_set_fec(uint16_t dev_id, uint16_t lmac, return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); } +/** + * Switch from eCPRI to CPRI and change + * + * @param dev_id + * The identifier of the device + * @param lmac + * LMAC number for operation + * @param mode + * CPRI structure which holds configuration data + * + * @return + * Returns 0 on success, negative error code otherwise + */ +static __rte_always_inline int +rte_pmd_bphy_cgx_cpri_mode_change(uint16_t dev_id, uint16_t lmac, + struct cnxk_bphy_cgx_msg_cpri_mode_change *mode) +{ + struct cnxk_bphy_cgx_msg msg = { + .type = CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_CHANGE, + .data = mode, + }; + + return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); +} + #ifdef __cplusplus } #endif From patchwork Sat Jun 4 16:26:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 112323 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C06E9A034C; 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Sat, 04 Jun 2022 09:27:30 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sat, 4 Jun 2022 09:27:28 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Sat, 4 Jun 2022 09:27:28 -0700 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id D909C3F7097; Sat, 4 Jun 2022 09:27:25 -0700 (PDT) From: Tomasz Duszynski To: , Jakub Palider , Tomasz Duszynski , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: , Subject: [PATCH 06/10] raw/cnxk_bphy: support enabling TX for CPRI SERDES Date: Sat, 4 Jun 2022 18:26:47 +0200 Message-ID: <20220604162651.3503338-7-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220604162651.3503338-1-tduszynski@marvell.com> References: <20220604162651.3503338-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: YRjzlJR8n7RwumgCkiF52kWToToe1Q5n X-Proofpoint-GUID: YRjzlJR8n7RwumgCkiF52kWToToe1Q5n X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-04_05,2022-06-03_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for enabling or disablig TX for SERDES configured in CPRI mode. Signed-off-by: Tomasz Duszynski Reviewed-by: Jakub Palider Reviewed-by: Jerin Jacob Kollanukkaran Acked-by: Ray Kinsella --- doc/guides/rawdevs/cnxk_bphy.rst | 10 +++++++ drivers/common/cnxk/roc_bphy_cgx.c | 31 +++++++++++++++++++++ drivers/common/cnxk/roc_bphy_cgx.h | 8 ++++++ drivers/common/cnxk/roc_bphy_cgx_priv.h | 6 +++++ drivers/common/cnxk/version.map | 1 + drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 11 ++++++++ drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 36 +++++++++++++++++++++++++ 7 files changed, 103 insertions(+) diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst index 7f55e9eac6..50ee9bdaa6 100644 --- a/doc/guides/rawdevs/cnxk_bphy.rst +++ b/doc/guides/rawdevs/cnxk_bphy.rst @@ -111,6 +111,16 @@ Prior to sending actual message payload i.e ``struct cnxk_bphy_cgx_msg_cpri_mode_change`` needs to be filled with relevant information. +Enable TX for CPRI SERDES +~~~~~~~~~~~~~~~~~~~~~~~~~ + +Message is used to enable TX for SERDES configured in CPRI mode. + +Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_CPRI_TX_CONTROL``. +Prior to sending actual message payload i.e +``struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl`` needs to be filled with relevant +information. + BPHY PMD -------- diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c index 223bd313fa..ee0198924e 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.c +++ b/drivers/common/cnxk/roc_bphy_cgx.c @@ -488,3 +488,34 @@ roc_bphy_cgx_cpri_mode_change(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0); } + +int +roc_bphy_cgx_cpri_mode_tx_control(struct roc_bphy_cgx *roc_cgx, + unsigned int lmac, + struct roc_bphy_cgx_cpri_mode_tx_ctrl *mode) +{ + uint64_t scr1, scr0; + + if (!(roc_model_is_cnf95xxn_a0() || + roc_model_is_cnf95xxn_a1() || + roc_model_is_cnf95xxn_b0())) + return -ENOTSUP; + + if (!roc_cgx) + return -EINVAL; + + if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac)) + return -ENODEV; + + if (!mode) + return -EINVAL; + + scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_CPRI_TX_CONTROL) | + FIELD_PREP(SCR1_CPRI_MODE_TX_CTRL_ARGS_GSERC_IDX, + mode->gserc_idx) | + FIELD_PREP(SCR1_CPRI_MODE_TX_CTRL_ARGS_LANE_IDX, + mode->lane_idx) | + FIELD_PREP(SCR1_CPRI_MODE_TX_CTRL_ARGS_ENABLE, mode->enable); + + return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0); +} diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h index 59adddd420..b8023cce88 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.h +++ b/drivers/common/cnxk/roc_bphy_cgx.h @@ -100,6 +100,12 @@ struct roc_bphy_cgx_cpri_mode_change { bool disable_dfe; }; +struct roc_bphy_cgx_cpri_mode_tx_ctrl { + int gserc_idx; + int lane_idx; + bool enable; +}; + __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx); __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx); @@ -130,5 +136,7 @@ __roc_api int roc_bphy_cgx_fec_supported_get(struct roc_bphy_cgx *roc_cgx, unsig enum roc_bphy_cgx_eth_link_fec *fec); __roc_api int roc_bphy_cgx_cpri_mode_change(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, struct roc_bphy_cgx_cpri_mode_change *mode); +__roc_api int roc_bphy_cgx_cpri_mode_tx_control(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, + struct roc_bphy_cgx_cpri_mode_tx_ctrl *mode); #endif /* _ROC_BPHY_CGX_H_ */ diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h index cdd94989c8..96db34f6a1 100644 --- a/drivers/common/cnxk/roc_bphy_cgx_priv.h +++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h @@ -70,6 +70,7 @@ enum eth_cmd_id { ETH_CMD_SET_FEC = 19, ETH_CMD_SET_PTP_MODE = 34, ETH_CMD_CPRI_MODE_CHANGE = 35, + ETH_CMD_CPRI_TX_CONTROL = 36, }; /* event types - cause of interrupt */ @@ -141,6 +142,11 @@ enum eth_cmd_own { #define SCR1_CPRI_MODE_CHANGE_ARGS_DISABLE_LEQ BIT_ULL(32) #define SCR1_CPRI_MODE_CHANGE_ARGS_DISABLE_DFE BIT_ULL(33) +/* struct cpri_mode_tx_ctrl_args */ +#define SCR1_CPRI_MODE_TX_CTRL_ARGS_GSERC_IDX GENMASK_ULL(11, 8) +#define SCR1_CPRI_MODE_TX_CTRL_ARGS_LANE_IDX GENMASK_ULL(15, 12) +#define SCR1_CPRI_MODE_TX_CTRL_ARGS_ENABLE BIT_ULL(16) + #define SCR1_OWN_STATUS GENMASK_ULL(1, 0) #endif /* _ROC_BPHY_CGX_PRIV_H_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 720cad61ea..a6183799a9 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -29,6 +29,7 @@ INTERNAL { roc_ae_fpm_put; roc_aes_xcbc_key_derive; roc_bphy_cgx_cpri_mode_change; + roc_bphy_cgx_cpri_mode_tx_control; roc_bphy_cgx_dev_fini; roc_bphy_cgx_dev_init; roc_bphy_cgx_fec_set; diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c index 803b245c78..bdc65a7f2a 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c @@ -58,10 +58,12 @@ cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue, struct cnxk_bphy_cgx_queue *qp = &cgx->queues[queue]; struct cnxk_bphy_cgx_msg_cpri_mode_change *cpri_mode; struct cnxk_bphy_cgx_msg_set_link_state *link_state; + struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl *tx_ctrl; struct cnxk_bphy_cgx_msg *msg = buf->buf_addr; struct cnxk_bphy_cgx_msg_link_mode *link_mode; struct cnxk_bphy_cgx_msg_link_info *link_info; struct roc_bphy_cgx_cpri_mode_change rcpri_mode; + struct roc_bphy_cgx_cpri_mode_tx_ctrl rtx_ctrl; struct roc_bphy_cgx_link_info rlink_info; struct roc_bphy_cgx_link_mode rlink_mode; enum roc_bphy_cgx_eth_link_fec *fec; @@ -148,6 +150,15 @@ cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue, ret = roc_bphy_cgx_cpri_mode_change(cgx->rcgx, lmac, &rcpri_mode); break; + case CNXK_BPHY_CGX_MSG_TYPE_CPRI_TX_CONTROL: + tx_ctrl = msg->data; + memset(&rtx_ctrl, 0, sizeof(rtx_ctrl)); + rtx_ctrl.gserc_idx = tx_ctrl->gserc_idx; + rtx_ctrl.lane_idx = tx_ctrl->lane_idx; + rtx_ctrl.enable = tx_ctrl->enable; + ret = roc_bphy_cgx_cpri_mode_tx_control(cgx->rcgx, lmac, + &rtx_ctrl); + break; default: return -EINVAL; } diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h index 36b75aa385..79bb2233bc 100644 --- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h +++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h @@ -52,6 +52,8 @@ enum cnxk_bphy_cgx_msg_type { CNXK_BPHY_CGX_MSG_TYPE_SET_FEC, /** Type used to switch from eCPRI to CPRI */ CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_CHANGE, + /** Type used to enable TX for CPRI SERDES */ + CNXK_BPHY_CGX_MSG_TYPE_CPRI_TX_CONTROL, }; /** Available link speeds */ @@ -186,6 +188,15 @@ struct cnxk_bphy_cgx_msg_cpri_mode_change { bool disable_dfe; }; +struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl { + /** SERDES index (0 - 4) */ + int gserc_idx; + /** Lane index (0 - 1) */ + int lane_idx; + /** Disable or enable SERDES */ + bool enable; +}; + struct cnxk_bphy_cgx_msg { /** Message type */ enum cnxk_bphy_cgx_msg_type type; @@ -734,6 +745,31 @@ rte_pmd_bphy_cgx_cpri_mode_change(uint16_t dev_id, uint16_t lmac, return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); } +/** + * Enable TX for SERDES configured in CPRI mode + * + * @param dev_id + * The identifier of the device + * @param lmac + * LMAC number for operation + * @param mode + * CPRI TX control structure holding control data + * + * @return + * Returns 0 on success, negative error code otherwise + */ +static __rte_always_inline int +rte_pmd_bphy_cgx_cpri_tx_control(uint16_t dev_id, uint16_t lmac, + struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl *mode) +{ + struct cnxk_bphy_cgx_msg msg = { + .type = CNXK_BPHY_CGX_MSG_TYPE_CPRI_TX_CONTROL, + .data = mode, + }; + + return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); +} + #ifdef __cplusplus } #endif From patchwork Sat Jun 4 16:26:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 112324 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 03040A034C; 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Sat, 04 Jun 2022 09:27:34 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 4 Jun 2022 09:27:32 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 4 Jun 2022 09:27:32 -0700 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id 3DE793F70AB; Sat, 4 Jun 2022 09:27:29 -0700 (PDT) From: Tomasz Duszynski To: , Jakub Palider , Tomasz Duszynski , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: , Subject: [PATCH 07/10] raw/cnxk_bphy: support changing CPRI misc settings Date: Sat, 4 Jun 2022 18:26:48 +0200 Message-ID: <20220604162651.3503338-8-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220604162651.3503338-1-tduszynski@marvell.com> References: <20220604162651.3503338-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: gS2DYty29RYNYpyn-GvrkU78JGzcjwI2 X-Proofpoint-GUID: gS2DYty29RYNYpyn-GvrkU78JGzcjwI2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-04_05,2022-06-03_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for changing miscellaneous CPRI settings. Signed-off-by: Tomasz Duszynski Reviewed-by: Jerin Jacob Kollanukkaran Acked-by: Ray Kinsella --- doc/guides/rawdevs/cnxk_bphy.rst | 11 ++++++++ drivers/common/cnxk/roc_bphy_cgx.c | 30 +++++++++++++++++++++ drivers/common/cnxk/roc_bphy_cgx.h | 8 ++++++ drivers/common/cnxk/roc_bphy_cgx_priv.h | 6 +++++ drivers/common/cnxk/version.map | 1 + drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 10 +++++++ drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 36 +++++++++++++++++++++++++ 7 files changed, 102 insertions(+) diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst index 50ee9bdaa6..2490912534 100644 --- a/doc/guides/rawdevs/cnxk_bphy.rst +++ b/doc/guides/rawdevs/cnxk_bphy.rst @@ -121,6 +121,17 @@ Prior to sending actual message payload i.e ``struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl`` needs to be filled with relevant information. +Change CPRI misc settings +~~~~~~~~~~~~~~~~~~~~~~~~~ + +Message is used to change misc CPRI settings, for example to reset RX state +machine on CPRI SERDES. + +Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_MISC``. +Prior to sending actual message payload i.e +``struct cnxk_bphy_cgx_msg_cpri_mode_misc`` needs to be filled with relevant +information. + BPHY PMD -------- diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c index ee0198924e..4b62905164 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.c +++ b/drivers/common/cnxk/roc_bphy_cgx.c @@ -519,3 +519,33 @@ roc_bphy_cgx_cpri_mode_tx_control(struct roc_bphy_cgx *roc_cgx, return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0); } + +int +roc_bphy_cgx_cpri_mode_misc(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, + struct roc_bphy_cgx_cpri_mode_misc *mode) +{ + uint64_t scr1, scr0; + + if (!(roc_model_is_cnf95xxn_a0() || + roc_model_is_cnf95xxn_a1() || + roc_model_is_cnf95xxn_b0())) + return -ENOTSUP; + + if (!roc_cgx) + return -EINVAL; + + if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac)) + return -ENODEV; + + if (!mode) + return -EINVAL; + + scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_CPRI_MISC) | + FIELD_PREP(SCR1_CPRI_MODE_MISC_ARGS_GSERC_IDX, + mode->gserc_idx) | + FIELD_PREP(SCR1_CPRI_MODE_MISC_ARGS_LANE_IDX, + mode->lane_idx) | + FIELD_PREP(SCR1_CPRI_MODE_MISC_ARGS_FLAGS, mode->flags); + + return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0); +} diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h index b8023cce88..3b645eb130 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.h +++ b/drivers/common/cnxk/roc_bphy_cgx.h @@ -106,6 +106,12 @@ struct roc_bphy_cgx_cpri_mode_tx_ctrl { bool enable; }; +struct roc_bphy_cgx_cpri_mode_misc { + int gserc_idx; + int lane_idx; + int flags; +}; + __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx); __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx); @@ -138,5 +144,7 @@ __roc_api int roc_bphy_cgx_cpri_mode_change(struct roc_bphy_cgx *roc_cgx, unsign struct roc_bphy_cgx_cpri_mode_change *mode); __roc_api int roc_bphy_cgx_cpri_mode_tx_control(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, struct roc_bphy_cgx_cpri_mode_tx_ctrl *mode); +__roc_api int roc_bphy_cgx_cpri_mode_misc(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, + struct roc_bphy_cgx_cpri_mode_misc *mode); #endif /* _ROC_BPHY_CGX_H_ */ diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h index 96db34f6a1..a1a4239cbe 100644 --- a/drivers/common/cnxk/roc_bphy_cgx_priv.h +++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h @@ -71,6 +71,7 @@ enum eth_cmd_id { ETH_CMD_SET_PTP_MODE = 34, ETH_CMD_CPRI_MODE_CHANGE = 35, ETH_CMD_CPRI_TX_CONTROL = 36, + ETH_CMD_CPRI_MISC = 42, }; /* event types - cause of interrupt */ @@ -147,6 +148,11 @@ enum eth_cmd_own { #define SCR1_CPRI_MODE_TX_CTRL_ARGS_LANE_IDX GENMASK_ULL(15, 12) #define SCR1_CPRI_MODE_TX_CTRL_ARGS_ENABLE BIT_ULL(16) +/* struct cpri_mode_misc_args */ +#define SCR1_CPRI_MODE_MISC_ARGS_GSERC_IDX GENMASK_ULL(11, 8) +#define SCR1_CPRI_MODE_MISC_ARGS_LANE_IDX GENMASK_ULL(15, 12) +#define SCR1_CPRI_MODE_MISC_ARGS_FLAGS GENMASK_ULL(17, 16) + #define SCR1_OWN_STATUS GENMASK_ULL(1, 0) #endif /* _ROC_BPHY_CGX_PRIV_H_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index a6183799a9..d5fd1f41c2 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -29,6 +29,7 @@ INTERNAL { roc_ae_fpm_put; roc_aes_xcbc_key_derive; roc_bphy_cgx_cpri_mode_change; + roc_bphy_cgx_cpri_mode_misc; roc_bphy_cgx_cpri_mode_tx_control; roc_bphy_cgx_dev_fini; roc_bphy_cgx_dev_init; diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c index bdc65a7f2a..de1c372334 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c @@ -59,10 +59,12 @@ cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue, struct cnxk_bphy_cgx_msg_cpri_mode_change *cpri_mode; struct cnxk_bphy_cgx_msg_set_link_state *link_state; struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl *tx_ctrl; + struct cnxk_bphy_cgx_msg_cpri_mode_misc *mode_misc; struct cnxk_bphy_cgx_msg *msg = buf->buf_addr; struct cnxk_bphy_cgx_msg_link_mode *link_mode; struct cnxk_bphy_cgx_msg_link_info *link_info; struct roc_bphy_cgx_cpri_mode_change rcpri_mode; + struct roc_bphy_cgx_cpri_mode_misc rmode_misc; struct roc_bphy_cgx_cpri_mode_tx_ctrl rtx_ctrl; struct roc_bphy_cgx_link_info rlink_info; struct roc_bphy_cgx_link_mode rlink_mode; @@ -159,6 +161,14 @@ cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue, ret = roc_bphy_cgx_cpri_mode_tx_control(cgx->rcgx, lmac, &rtx_ctrl); break; + case CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_MISC: + mode_misc = msg->data; + memset(&rmode_misc, 0, sizeof(rmode_misc)); + rmode_misc.gserc_idx = mode_misc->gserc_idx; + rmode_misc.lane_idx = mode_misc->lane_idx; + rmode_misc.flags = mode_misc->flags; + ret = roc_bphy_cgx_cpri_mode_misc(cgx->rcgx, lmac, &rmode_misc); + break; default: return -EINVAL; } diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h index 79bb2233bc..86e58e4756 100644 --- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h +++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h @@ -54,6 +54,8 @@ enum cnxk_bphy_cgx_msg_type { CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_CHANGE, /** Type used to enable TX for CPRI SERDES */ CNXK_BPHY_CGX_MSG_TYPE_CPRI_TX_CONTROL, + /** Type use to change misc CPRI SERDES settings */ + CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_MISC, }; /** Available link speeds */ @@ -197,6 +199,15 @@ struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl { bool enable; }; +struct cnxk_bphy_cgx_msg_cpri_mode_misc { + /** SERDES index (0 - 4) */ + int gserc_idx; + /** Lane index (0 - 1) */ + int lane_idx; + /** Misc flags (0 - RX Eq, 1 - RX state machine reset) */ + int flags; +}; + struct cnxk_bphy_cgx_msg { /** Message type */ enum cnxk_bphy_cgx_msg_type type; @@ -770,6 +781,31 @@ rte_pmd_bphy_cgx_cpri_tx_control(uint16_t dev_id, uint16_t lmac, return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); } +/** + * CPRI misc settings + * + * @param dev_id + * The identifier of the device + * @param lmac + * LMAC number for operation + * @param mode + * CPRI settings holding misc control data + * + * @return + * Returns 0 on success, negative error code otherwise + */ +static __rte_always_inline int +rte_pmd_bphy_cgx_cpri_mode_misc(uint16_t dev_id, uint16_t lmac, + struct cnxk_bphy_cgx_msg_cpri_mode_misc *mode) +{ + struct cnxk_bphy_cgx_msg msg = { + .type = CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_MISC, + .data = mode, + }; + + return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); +} + #ifdef __cplusplus } #endif From patchwork Sat Jun 4 16:26:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 112319 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 58F09A034C; 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Sat, 04 Jun 2022 09:27:37 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sat, 4 Jun 2022 09:27:35 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Sat, 4 Jun 2022 09:27:35 -0700 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id 915753F7097; Sat, 4 Jun 2022 09:27:32 -0700 (PDT) From: Tomasz Duszynski To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Tomasz Duszynski , Jakub Palider Subject: [PATCH 08/10] common/cnxk: remove unused constants Date: Sat, 4 Jun 2022 18:26:49 +0200 Message-ID: <20220604162651.3503338-9-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220604162651.3503338-1-tduszynski@marvell.com> References: <20220604162651.3503338-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: H5LGJol5kozn-NFtLufvjxZidz5bqA6n X-Proofpoint-GUID: H5LGJol5kozn-NFtLufvjxZidz5bqA6n X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-04_05,2022-06-03_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Some constants are redundant hence remove them. Signed-off-by: Tomasz Duszynski Reviewed-by: Jakub Palider Reviewed-by: Jerin Jacob Kollanukkaran --- drivers/common/cnxk/roc_bphy_cgx_priv.h | 53 ------------------------- 1 file changed, 53 deletions(-) diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h index a1a4239cbe..c8c406439c 100644 --- a/drivers/common/cnxk/roc_bphy_cgx_priv.h +++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h @@ -5,59 +5,6 @@ #ifndef _ROC_BPHY_CGX_PRIV_H_ #define _ROC_BPHY_CGX_PRIV_H_ -/* LINK speed types */ -enum eth_link_speed { - ETH_LINK_NONE, - ETH_LINK_10M, - ETH_LINK_100M, - ETH_LINK_1G, - ETH_LINK_2HG, /* 2.5 Gbps */ - ETH_LINK_5G, - ETH_LINK_10G, - ETH_LINK_20G, - ETH_LINK_25G, - ETH_LINK_40G, - ETH_LINK_50G, - ETH_LINK_80G, - ETH_LINK_100G, - ETH_LINK_MAX, -}; - -/* Supported LINK MODE enums - * Each link mode is a bit mask of these - * enums which are represented as bits - */ -enum eth_mode { - ETH_MODE_SGMII_BIT = 0, - ETH_MODE_1000_BASEX_BIT, - ETH_MODE_QSGMII_BIT, - ETH_MODE_10G_C2C_BIT, - ETH_MODE_10G_C2M_BIT, - ETH_MODE_10G_KR_BIT, /* = 5 */ - ETH_MODE_20G_C2C_BIT, - ETH_MODE_25G_C2C_BIT, - ETH_MODE_25G_C2M_BIT, - ETH_MODE_25G_2_C2C_BIT, - ETH_MODE_25G_CR_BIT, /* = 10 */ - ETH_MODE_25G_KR_BIT, - ETH_MODE_40G_C2C_BIT, - ETH_MODE_40G_C2M_BIT, - ETH_MODE_40G_CR4_BIT, - ETH_MODE_40G_KR4_BIT, /* = 15 */ - ETH_MODE_40GAUI_C2C_BIT, - ETH_MODE_50G_C2C_BIT, - ETH_MODE_50G_C2M_BIT, - ETH_MODE_50G_4_C2C_BIT, - ETH_MODE_50G_CR_BIT, /* = 20 */ - ETH_MODE_50G_KR_BIT, - ETH_MODE_80GAUI_C2C_BIT, - ETH_MODE_100G_C2C_BIT, - ETH_MODE_100G_C2M_BIT, - ETH_MODE_100G_CR4_BIT, /* = 25 */ - ETH_MODE_100G_KR4_BIT, - ETH_MODE_MAX_BIT /* = 27 */ -}; - /* REQUEST ID types. Input to firmware */ enum eth_cmd_id { ETH_CMD_GET_LINK_STS = 4, From patchwork Sat Jun 4 16:26:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 112320 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 45E0CA034C; Sat, 4 Jun 2022 18:27:54 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 282DD42B79; Sat, 4 Jun 2022 18:27:42 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id B868842B76 for ; Sat, 4 Jun 2022 18:27:40 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 254FrqRj032131; Sat, 4 Jun 2022 09:27:40 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=VUtZ4VxKZVQoAK4fpZRoQc0ITnRteO8IkPr9jnMqwbU=; b=HbuXiKrd1nuXWIPzJkc9npz3Nq5PqYxvDSZa5SciAu5xpPGn/Tn2a8nxTVAxHbko2Urj AMvPgkID6C4ch4R8UouOC3Hnb1tCRMPmvkUrFPdzjMCl0/82S2Sfbx7KKpxcmK5ggWMB BjL20qOVU5lQU+e8iT9teqrecYMa5cmKAeqx4ITtklKcF2h8iECEXSKc/Fe1kNWB4Sua R8CoZKdw7c3Sdh9SXYo0syRVcM2h9XUf2/L6TqAYuXQOXSzRtZive22vpxeh4pn96DOy V0kVgeKLQvHdYDE66j1r9ploFWnzlxHBnWBADRywSDrtgWH73A/OnU7jowDCE7WTnH4X kg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3gg9ndg4hc-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sat, 04 Jun 2022 09:27:39 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 4 Jun 2022 09:27:38 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Sat, 4 Jun 2022 09:27:38 -0700 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id AE2E33F70AB; Sat, 4 Jun 2022 09:27:35 -0700 (PDT) From: Tomasz Duszynski To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Jakub Palider , "Tomasz Duszynski" CC: , Subject: [PATCH 09/10] common/cnxk: sync eth mode change command with firmware Date: Sat, 4 Jun 2022 18:26:50 +0200 Message-ID: <20220604162651.3503338-10-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220604162651.3503338-1-tduszynski@marvell.com> References: <20220604162651.3503338-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: inFZzCT0MH2QUQzKnT_INerRlCIhsQxw X-Proofpoint-GUID: inFZzCT0MH2QUQzKnT_INerRlCIhsQxw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-04_05,2022-06-03_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Layout of eth mode change command defined by firmware has been changed recently. So in order to retain compatibility between ROC and firmware update existing codebase. Signed-off-by: Tomasz Duszynski Reviewed-by: Jakub Palider Reviewed-by: Jerin Jacob Kollanukkaran --- drivers/common/cnxk/roc_bphy_cgx.c | 11 +++++++-- drivers/common/cnxk/roc_bphy_cgx.h | 19 +++++++++++++- drivers/common/cnxk/roc_bphy_cgx_priv.h | 12 +++++---- drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 4 +++ drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 33 +++++++++++++++++++++++++ 5 files changed, 71 insertions(+), 8 deletions(-) diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c index 4b62905164..a5df104088 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.c +++ b/drivers/common/cnxk/roc_bphy_cgx.c @@ -367,8 +367,10 @@ roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, { uint64_t scr1, scr0; - if (roc_model_is_cn10k()) + if (roc_model_is_cn9k() && + (mode->use_portm_idx || mode->portm_idx || mode->mode_group_idx)) { return -ENOTSUP; + } if (!roc_cgx) return -EINVAL; @@ -383,7 +385,12 @@ roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_SPEED, mode->speed) | FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX, mode->full_duplex) | FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_AN, mode->an) | - FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_PORT, mode->port) | + FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_USE_PORTM_IDX, + mode->use_portm_idx) | + FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_PORTM_IDX, + mode->portm_idx) | + FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_MODE_GROUP_IDX, + mode->mode_group_idx) | FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_MODE, BIT_ULL(mode->mode)); return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0); diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h index 3b645eb130..4ce1316513 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.h +++ b/drivers/common/cnxk/roc_bphy_cgx.h @@ -72,13 +72,30 @@ enum roc_bphy_cgx_eth_link_mode { ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT, ROC_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT, ROC_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_50GAUI_2_C2C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_50GAUI_2_C2M_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_50GBASE_CR2_C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_50GBASE_KR2_C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_100GAUI_2_C2C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_100GAUI_2_C2M_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_100GBASE_CR2_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_100GBASE_KR2_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_SFI_1G_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_25GBASE_CR_C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_25GBASE_KR_C_BIT, __ROC_BPHY_CGX_ETH_LINK_MODE_MAX }; +enum roc_bphy_cgx_mode_group { + ROC_BPHY_CGX_MODE_GROUP_ETH, +}; + struct roc_bphy_cgx_link_mode { bool full_duplex; bool an; - unsigned int port; + bool use_portm_idx; + unsigned int portm_idx; + enum roc_bphy_cgx_mode_group mode_group_idx; enum roc_bphy_cgx_eth_link_speed speed; enum roc_bphy_cgx_eth_link_mode mode; }; diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h index c8c406439c..78fa1eaa6b 100644 --- a/drivers/common/cnxk/roc_bphy_cgx_priv.h +++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h @@ -74,11 +74,13 @@ enum eth_cmd_own { #define SCR1_ETH_CTL_ARGS_ENABLE BIT_ULL(8) /* struct eth_mode_change_args */ -#define SCR1_ETH_MODE_CHANGE_ARGS_SPEED GENMASK_ULL(11, 8) -#define SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX BIT_ULL(12) -#define SCR1_ETH_MODE_CHANGE_ARGS_AN BIT_ULL(13) -#define SCR1_ETH_MODE_CHANGE_ARGS_PORT GENMASK_ULL(21, 14) -#define SCR1_ETH_MODE_CHANGE_ARGS_MODE GENMASK_ULL(63, 22) +#define SCR1_ETH_MODE_CHANGE_ARGS_SPEED GENMASK_ULL(11, 8) +#define SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX BIT_ULL(12) +#define SCR1_ETH_MODE_CHANGE_ARGS_AN BIT_ULL(13) +#define SCR1_ETH_MODE_CHANGE_ARGS_USE_PORTM_IDX BIT_ULL(14) +#define SCR1_ETH_MODE_CHANGE_ARGS_PORTM_IDX GENMASK_ULL(19, 15) +#define SCR1_ETH_MODE_CHANGE_ARGS_MODE_GROUP_IDX GENMASK_ULL(21, 20) +#define SCR1_ETH_MODE_CHANGE_ARGS_MODE GENMASK_ULL(63, 22) /* struct eth_set_fec_args */ #define SCR1_ETH_SET_FEC_ARGS GENMASK_ULL(9, 8) diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c index de1c372334..f839a70f04 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c @@ -112,6 +112,10 @@ cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue, memset(&rlink_mode, 0, sizeof(rlink_mode)); rlink_mode.full_duplex = link_mode->full_duplex; rlink_mode.an = link_mode->autoneg; + rlink_mode.use_portm_idx = link_mode->use_portm_idx; + rlink_mode.portm_idx = link_mode->portm_idx; + rlink_mode.mode_group_idx = + (enum roc_bphy_cgx_mode_group)link_mode->mode_group_idx; rlink_mode.speed = (enum roc_bphy_cgx_eth_link_speed)link_mode->speed; rlink_mode.mode = diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h index 86e58e4756..7f326e3643 100644 --- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h +++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h @@ -143,14 +143,47 @@ enum cnxk_bphy_cgx_eth_link_mode { CNXK_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT, /** 100GBASE-KR4 */ CNXK_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT, + /** 50GAUI-2-C2C */ + CNXK_BPHY_CGX_ETH_LINK_MODE_50GAUI_2_C2C_BIT, + /** 50GAUI-2-C2M */ + CNXK_BPHY_CGX_ETH_LINK_MODE_50GAUI_2_C2M_BIT, + /** 50GBASE-CR2-C */ + CNXK_BPHY_CGX_ETH_LINK_MODE_50GBASE_CR2_C_BIT, + /** 50GBASE-KR2-C */ + CNXK_BPHY_CGX_ETH_LINK_MODE_50GBASE_KR2_C_BIT, + /** 100GAUI-2-C2C */ + CNXK_BPHY_CGX_ETH_LINK_MODE_100GAUI_2_C2C_BIT, + /** 100GAUI-2-C2M */ + CNXK_BPHY_CGX_ETH_LINK_MODE_100GAUI_2_C2M_BIT, + /** 100GBASE-CR2 */ + CNXK_BPHY_CGX_ETH_LINK_MODE_100GBASE_CR2_BIT, + /** 100GBASE-KR2 */ + CNXK_BPHY_CGX_ETH_LINK_MODE_100GBASE_KR2_BIT, + /** SFI-1G */ + CNXK_BPHY_CGX_ETH_LINK_MODE_SFI_1G_BIT, + /** 25GBASE-CR-C */ + CNXK_BPHY_CGX_ETH_LINK_MODE_25GBASE_CR_C_BIT, + /** 25GBASE-KR-C */ + CNXK_BPHY_CGX_ETH_LINK_MODE_25GBASE_KR_C_BIT, __CNXK_BPHY_CGX_ETH_LINK_MODE_MAX }; +enum cnxk_bphy_cgx_mode_group { + /** ETH group */ + CNXK_BPHY_CGX_MODE_GROUP_ETH, +}; + struct cnxk_bphy_cgx_msg_link_mode { /** Setting for full-duplex */ bool full_duplex; /** Setting for automatic link negotiation */ bool autoneg; + /** Set to true to use port index */ + bool use_portm_idx; + /** Port index */ + unsigned int portm_idx; + /** Mode group */ + enum cnxk_bphy_cgx_mode_group mode_group_idx; /** Link speed */ enum cnxk_bphy_cgx_eth_link_speed speed; /** Link mode */ From patchwork Sat Jun 4 16:26:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 112321 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 799A0A034C; Sat, 4 Jun 2022 18:28:00 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 05BCD427F6; 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Sat, 04 Jun 2022 09:27:43 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sat, 4 Jun 2022 09:27:41 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Sat, 4 Jun 2022 09:27:41 -0700 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id C9DB13F7097; Sat, 4 Jun 2022 09:27:38 -0700 (PDT) From: Tomasz Duszynski To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Jakub Palider , "Tomasz Duszynski" CC: , Subject: [PATCH 10/10] common/cnxk: support switching CPRI/ETH back and forth Date: Sat, 4 Jun 2022 18:26:51 +0200 Message-ID: <20220604162651.3503338-11-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220604162651.3503338-1-tduszynski@marvell.com> References: <20220604162651.3503338-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: rHifoJjZBoOWYgTxIjPT2cAqihU_RoA7 X-Proofpoint-GUID: rHifoJjZBoOWYgTxIjPT2cAqihU_RoA7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-04_05,2022-06-03_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for toggling modes between ETH and CPRI on newer MACs (RPM). Signed-off-by: Tomasz Duszynski Reviewed-by: Jakub Palider Reviewed-by: Jerin Jacob Kollanukkaran --- drivers/common/cnxk/roc_bphy_cgx.h | 17 ++++++++++++++++- drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 14 ++++++++++++-- drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 27 +++++++++++++++++++++++++-- 3 files changed, 53 insertions(+), 5 deletions(-) diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h index 4ce1316513..2b9a23f5b1 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.h +++ b/drivers/common/cnxk/roc_bphy_cgx.h @@ -86,8 +86,20 @@ enum roc_bphy_cgx_eth_link_mode { __ROC_BPHY_CGX_ETH_LINK_MODE_MAX }; +/* Supported CPRI modes */ +enum roc_bphy_cgx_eth_mode_cpri { + ROC_BPHY_CGX_ETH_MODE_CPRI_2_4G_BIT, + ROC_BPHY_CGX_ETH_MODE_CPRI_3_1G_BIT, + ROC_BPHY_CGX_ETH_MODE_CPRI_4_9G_BIT, + ROC_BPHY_CGX_ETH_MODE_CPRI_6_1G_BIT, + ROC_BPHY_CGX_ETH_MODE_CPRI_9_8G_BIT, + ROC_BPHY_CGX_ETH_MODE_CPRI_10_1_BIT, + ROC_BPHY_CGX_ETH_MODE_CPRI_24_3G_BIT, +}; + enum roc_bphy_cgx_mode_group { ROC_BPHY_CGX_MODE_GROUP_ETH, + ROC_BPHY_CGX_MODE_GROUP_CPRI = 2, }; struct roc_bphy_cgx_link_mode { @@ -97,7 +109,10 @@ struct roc_bphy_cgx_link_mode { unsigned int portm_idx; enum roc_bphy_cgx_mode_group mode_group_idx; enum roc_bphy_cgx_eth_link_speed speed; - enum roc_bphy_cgx_eth_link_mode mode; + union { + enum roc_bphy_cgx_eth_link_mode mode; + enum roc_bphy_cgx_eth_mode_cpri mode_cpri; + }; }; struct roc_bphy_cgx_link_info { diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c index f839a70f04..26def43564 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c @@ -118,8 +118,18 @@ cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue, (enum roc_bphy_cgx_mode_group)link_mode->mode_group_idx; rlink_mode.speed = (enum roc_bphy_cgx_eth_link_speed)link_mode->speed; - rlink_mode.mode = - (enum roc_bphy_cgx_eth_link_mode)link_mode->mode; + switch (link_mode->mode_group_idx) { + case CNXK_BPHY_CGX_MODE_GROUP_ETH: + rlink_mode.mode = + (enum roc_bphy_cgx_eth_link_mode) + link_mode->mode; + break; + case CNXK_BPHY_CGX_MODE_GROUP_CPRI: + rlink_mode.mode_cpri = + (enum roc_bphy_cgx_eth_mode_cpri) + link_mode->mode_cpri; + break; + } ret = roc_bphy_cgx_set_link_mode(cgx->rcgx, lmac, &rlink_mode); break; case CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE: diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h index 7f326e3643..f9949fa313 100644 --- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h +++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h @@ -168,9 +168,28 @@ enum cnxk_bphy_cgx_eth_link_mode { __CNXK_BPHY_CGX_ETH_LINK_MODE_MAX }; +enum cnxk_bphy_cgx_eth_mode_cpri { + /** 2.4G Lane Rate */ + CNXK_BPHY_CGX_ETH_MODE_CPRI_2_4G_BIT, + /** 3.1G Lane Rate */ + CNXK_BPHY_CGX_ETH_MODE_CPRI_3_1G_BIT, + /** 4.9G Lane Rate */ + CNXK_BPHY_CGX_ETH_MODE_CPRI_4_9G_BIT, + /** 6.1G Lane Rate */ + CNXK_BPHY_CGX_ETH_MODE_CPRI_6_1G_BIT, + /** 9.8G Lane Rate */ + CNXK_BPHY_CGX_ETH_MODE_CPRI_9_8G_BIT, + /** 10.1G Lane Rate */ + CNXK_BPHY_CGX_ETH_MODE_CPRI_10_1_BIT, + /** 24.3G Lane Rate */ + CNXK_BPHY_CGX_ETH_MODE_CPRI_24_3G_BIT, +}; + enum cnxk_bphy_cgx_mode_group { /** ETH group */ CNXK_BPHY_CGX_MODE_GROUP_ETH, + /** CPRI group */ + CNXK_BPHY_CGX_MODE_GROUP_CPRI = 2, }; struct cnxk_bphy_cgx_msg_link_mode { @@ -186,8 +205,12 @@ struct cnxk_bphy_cgx_msg_link_mode { enum cnxk_bphy_cgx_mode_group mode_group_idx; /** Link speed */ enum cnxk_bphy_cgx_eth_link_speed speed; - /** Link mode */ - enum cnxk_bphy_cgx_eth_link_mode mode; + union { + /** Link mode */ + enum cnxk_bphy_cgx_eth_link_mode mode; + /** CPRI mode */ + enum cnxk_bphy_cgx_eth_mode_cpri mode_cpri; + }; }; struct cnxk_bphy_cgx_msg_link_info {