From patchwork Sat Apr 2 06:40:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Zhang X-Patchwork-Id: 109095 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5C5EBA0501; Sat, 2 Apr 2022 08:40:25 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EB2EE4067E; Sat, 2 Apr 2022 08:40:24 +0200 (CEST) Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2069.outbound.protection.outlook.com [40.107.220.69]) by mails.dpdk.org (Postfix) with ESMTP id 88DBA40143 for ; Sat, 2 Apr 2022 08:40:23 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=XAshlEUFtP+Q4/XuGlfImMGDyXurqPdlV6CPOUkl+TtxBYpY/fn6aw+OKkeLDb7RQW3VrzTf/g4Y899KN6dP6IWbYShC1wU2c1ovj9SRK5xHmtu/DByli9OsMJhxLiddjEi2J4sVhjK858z0fynh3XbJeLH3GDBtdXQ0LIwP9nItneN/yRUnWPP68VPdqS99TfGtn0YG2BM3M82WxBpfOUyUPmJpvHZGxe4Io2FBuvCmFcNOtA+WO/0AolsGpHPc/UTEBcat2sw8M1HWSUiLqOWxLhEqYSuniPm8Xjev98WXji4vRvnb9rV6vIkcJ2nuxNzzMYhqPndKRuEo9b04vQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=1aXMOfnvq+Xxvj2fat4n3+IYiAbFYYMLslKqpLLXudQ=; b=Owk+AJd+8u8SlFFUiCvB6vEzuPEN+L0gfPobbMJw+C+k+qfleNYE4uTvuyw8bQBgcHiik2dWjl//oRwGGlXyA/tIBd7eeK0mQm1f55osYR8pVV6qNAyW4vpJB64dV9aXl9kD9g4AOrKIEekcgWCFYzaYXVVZBQqthwHkYb0ya3bBanowoRZJiRz6URFHPdHMir4bEkDXqrbAZthRWQa6M61qZs924qA/Tt7jt7GKk5XDfrpO0xSGgIgotM8luojHryyAZQXDCaUvrtSAwvfXKghRuCrplIccyqsr4NPLzsqnEmUJy2KficneuV/2LHw+vIqvMbxtqkNn5QFkRz7wJg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.234) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=1aXMOfnvq+Xxvj2fat4n3+IYiAbFYYMLslKqpLLXudQ=; b=nZ9wdv8J61ou3JC+2e/tizp5fkxzuhPKZ6NzVQR2rrMgcJlKWqAnKW0nK+sDweRQUEEV0mUVJ/z7OGTs5407ubNv0fialbbm4i4aV/YE+V+DKE1BRrlLay5O251hM7YN86fDOmU5ieL7wYbCWlIN+y4g4q+S4tdUoItIvp+Vd3zWKD58oCjDWafjfobowHkP24t8g/2B5D2GRVypftM9O1rqkwtsC1NiT+rOptNxd60s85hLQ7l3jITqHML4n3CfH5KvH/ltVsv3tnNkPGjWytqKd6xFq3Rs0b7N0NZ5xliV4aHGy+Lm/eb3Sm6/QxecOlrHuDRgzC+19Z18OjeRIw== Received: from BN9PR03CA0887.namprd03.prod.outlook.com (2603:10b6:408:13c::22) by BYAPR12MB2741.namprd12.prod.outlook.com (2603:10b6:a03:62::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5123.30; Sat, 2 Apr 2022 06:40:19 +0000 Received: from BN8NAM11FT065.eop-nam11.prod.protection.outlook.com (2603:10b6:408:13c:cafe::a5) by BN9PR03CA0887.outlook.office365.com (2603:10b6:408:13c::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5123.30 via Frontend Transport; Sat, 2 Apr 2022 06:40:19 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.234) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.234 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.234; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.234) by BN8NAM11FT065.mail.protection.outlook.com (10.13.177.63) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5123.19 via Frontend Transport; Sat, 2 Apr 2022 06:40:18 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL101.nvidia.com (10.27.9.10) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Sat, 2 Apr 2022 06:40:18 +0000 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 1 Apr 2022 23:40:16 -0700 From: Sean Zhang To: Matan Azrad , Viacheslav Ovsiienko CC: Subject: [v1] net/mlx5: support represented port item Date: Sat, 2 Apr 2022 09:40:00 +0300 Message-ID: <20220402064000.8772-1-xiazhang@nvidia.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e84a3ad0-6524-4ba0-f7a6-08da1473a795 X-MS-TrafficTypeDiagnostic: BYAPR12MB2741:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 9OkBAzjF1rGlm1GfeGod0Xp9Cgm8MLNJSBSs+QBRnD+sjPjoSU2kvzUMRy+OB4UwaE/DvUKR6CvbwbkgYeqE+lEXC75e1QwBF9sChT083EQsb285tpN4VEjYoSSoxkjhIVb+nGwx7MMV1Nr9Kcn83ShHbjOuj0y2p3OdhpuK7eM2ar1kDhmHHgN7CkZwCKqqi6ChTNdKT7j86XlPVoOK/ccl3uJtqKvA4oVijOQca7iXF4b2oGZghlQQEZYz+QDVAKLFrzP6NgmEFoEV2ga1TUW2WfJDyIkt91qu3ZqqdAkh9iR2QdDCe3RhX4kNr0Xhi+m8jMP0w2QYfKgsE2eyrx+gBP0ClTBTtNWV1SlzWK4VGOtra+p14rbuuSK8L32vayia0dLNawGxYUchjoFKuTX1zN5Jof1fTrLGrUtTGwO2ORmtmgn5QjOqaW4V8PQaoCvEzPfTatf0xsMLk94HVh/GWOyDKxoSWkxcc4LC2P43nlqLOxF5VTTpt+J5A5eymBYbtzNDBeAU4OBH63qWn9VfxpaDFtg9OertElNdNSjnuAxTe6z2uSE0xIKDbdSSvLv1fxK+Jz4JLjeQFbS6AM/OePEQ86IoXp9mNFXV1Fff+E9nk0hbrteEJOC94cgaiPvFFmOILWh9bd0rvDmDe59Q7EvkexjlDuSrEQ5nxMr4m7uJV63TuOELmvELbhvACqoSCPu4uQhRIusRpd/bFw== X-Forefront-Antispam-Report: CIP:12.22.5.234; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(36840700001)(46966006)(40470700004)(4326008)(8676002)(70206006)(70586007)(110136005)(86362001)(40460700003)(36860700001)(55016003)(5660300002)(508600001)(6636002)(316002)(8936002)(36756003)(2906002)(356005)(186003)(26005)(16526019)(1076003)(6666004)(47076005)(7696005)(6286002)(2616005)(336012)(83380400001)(82310400004)(426003)(81166007)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Apr 2022 06:40:18.9733 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e84a3ad0-6524-4ba0-f7a6-08da1473a795 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB2741 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for represented_port item in pattern. And if the spec and mask both are NULL, translate function will not add source vport to matcher. For example, testpmd starts with PF, VF-rep0 and VF-rep1, below command will redirect packets from VF0 and VF1 to wire: testpmd> flow create 0 ingress transfer group 0 pattern eth / represented_port / end actions represented_port ethdev_id is 0 / end Signed-off-by: Sean Zhang Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow.h | 4 + drivers/net/mlx5/mlx5_flow_dv.c | 160 +++++++++++++++++++++++++++++++- 2 files changed, 163 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index f56115dd11..0740b01de5 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -186,6 +186,10 @@ enum mlx5_feature_name { #define MLX5_FLOW_ITEM_INNER_FLEX (UINT64_C(1) << 38) #define MLX5_FLOW_ITEM_FLEX_TUNNEL (UINT64_C(1) << 39) +/* Port Representor/Represented Port item */ +#define MLX5_FLOW_ITEM_PORT_REPRESENTOR (UINT64_C(1) << 40) +#define MLX5_FLOW_ITEM_REPRESENTED_PORT (UINT64_C(1) << 41) + /* Outer Masks. */ #define MLX5_FLOW_LAYER_OUTER_L3 \ (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 1e9bd63635..f20a64e8e4 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -2209,6 +2209,80 @@ flow_dv_validate_item_port_id(struct rte_eth_dev *dev, return 0; } +/** + * Validate represented port item. + * + * @param[in] dev + * Pointer to the rte_eth_dev structure. + * @param[in] item + * Item specification. + * @param[in] attr + * Attributes of flow that includes this item. + * @param[in] item_flags + * Bit-fields that holds the items detected until now. + * @param[out] error + * Pointer to error structure. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +static int +flow_dv_validate_item_represented_port(struct rte_eth_dev *dev, + const struct rte_flow_item *item, + const struct rte_flow_attr *attr, + uint64_t item_flags, + struct rte_flow_error *error) +{ + const struct rte_flow_item_ethdev *spec = item->spec; + const struct rte_flow_item_ethdev *mask = item->mask; + const struct rte_flow_item_ethdev switch_mask = { + .port_id = UINT16_MAX, + }; + struct mlx5_priv *esw_priv; + struct mlx5_priv *dev_priv; + int ret; + + if (!attr->transfer) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, NULL, + "match on port id is valid only when transfer flag is enabled"); + if (item_flags & MLX5_FLOW_ITEM_REPRESENTED_PORT) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ITEM, item, + "multiple source ports are not supported"); + if (!mask) + mask = &switch_mask; + if (mask->port_id != UINT16_MAX) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, + "no support for partial mask on \"id\" field"); + ret = mlx5_flow_item_acceptable + (item, (const uint8_t *)mask, + (const uint8_t *)&rte_flow_item_ethdev_mask, + sizeof(struct rte_flow_item_ethdev), + MLX5_ITEM_RANGE_NOT_ACCEPTED, error); + if (ret) + return ret; + if (!spec || spec->port_id == UINT16_MAX) + return 0; + esw_priv = mlx5_port_to_eswitch_info(spec->port_id, false); + if (!esw_priv) + return rte_flow_error_set(error, rte_errno, + RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec, + "failed to obtain E-Switch info for port"); + dev_priv = mlx5_dev_to_eswitch_info(dev); + if (!dev_priv) + return rte_flow_error_set(error, rte_errno, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "failed to obtain E-Switch info"); + if (esw_priv->domain_id != dev_priv->domain_id) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec, + "cannot match on a port from a different E-Switch"); + return 0; +} + /** * Validate VLAN item. * @@ -6963,6 +7037,13 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, last_item = MLX5_FLOW_ITEM_PORT_ID; port_id_item = items; break; + case RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT: + ret = flow_dv_validate_item_represented_port + (dev, items, attr, item_flags, error); + if (ret < 0) + return ret; + last_item = MLX5_FLOW_ITEM_REPRESENTED_PORT; + break; case RTE_FLOW_ITEM_TYPE_ETH: ret = mlx5_flow_validate_item_eth(items, item_flags, true, error); @@ -9918,6 +9999,77 @@ flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher, return 0; } +/** + * Translate represented port item to eswitch match on port id. + * + * @param[in] dev + * The devich to configure through. + * @param[in, out] matcher + * Flow matcher. + * @param[in, out] key + * Flow matcher value. + * @param[in] item + * Flow pattern to translate. + * @param[in] + * Flow attributes. + * + * @return + * 0 on success, a negative errno value otherwise. + */ +static int +flow_dv_translate_item_represented_port(struct rte_eth_dev *dev, void *matcher, + void *key, + const struct rte_flow_item *item, + const struct rte_flow_attr *attr) +{ + const struct rte_flow_item_ethdev *pid_m = item ? item->mask : NULL; + const struct rte_flow_item_ethdev *pid_v = item ? item->spec : NULL; + struct mlx5_priv *priv; + uint16_t mask, id; + + if (!pid_m && !pid_v) + return 0; + if (pid_v && pid_v->port_id == UINT16_MAX) { + flow_dv_translate_item_source_vport(matcher, key, + flow_dv_get_esw_manager_vport_id(dev), UINT16_MAX); + return 0; + } + mask = pid_m ? pid_m->port_id : UINT16_MAX; + id = pid_v ? pid_v->port_id : dev->data->port_id; + priv = mlx5_port_to_eswitch_info(id, item == NULL); + if (!priv) + return -rte_errno; + /* + * Translate to vport field or to metadata, depending on mode. + * Kernel can use either misc.source_port or half of C0 metadata + * register. + */ + if (priv->vport_meta_mask) { + /* + * Provide the hint for SW steering library + * to insert the flow into ingress domain and + * save the extra vport match. + */ + if (mask == UINT16_MAX && priv->vport_id == UINT16_MAX && + priv->pf_bond < 0 && attr->transfer) + flow_dv_translate_item_source_vport + (matcher, key, priv->vport_id, mask); + /* + * We should always set the vport metadata register, + * otherwise the SW steering library can drop + * the rule if wire vport metadata value is not zero, + * it depends on kernel configuration. + */ + flow_dv_translate_item_meta_vport(matcher, key, + priv->vport_meta_tag, + priv->vport_meta_mask); + } else { + flow_dv_translate_item_source_vport(matcher, key, + priv->vport_id, mask); + } + return 0; +} + /** * Add ICMP6 item to matcher and to the value. * @@ -13543,6 +13695,11 @@ flow_dv_translate(struct rte_eth_dev *dev, (dev, match_mask, match_value, items, attr); last_item = MLX5_FLOW_ITEM_PORT_ID; break; + case RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT: + flow_dv_translate_item_represented_port + (dev, match_mask, match_value, items, attr); + last_item = MLX5_FLOW_ITEM_REPRESENTED_PORT; + break; case RTE_FLOW_ITEM_TYPE_ETH: flow_dv_translate_item_eth(match_mask, match_value, items, tunnel, @@ -13801,7 +13958,8 @@ flow_dv_translate(struct rte_eth_dev *dev, * In both cases the source port is set according the current port * in use. */ - if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) && priv->sh->esw_mode && + if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) && + !(item_flags & MLX5_FLOW_ITEM_REPRESENTED_PORT) && priv->sh->esw_mode && !(attr->egress && !attr->transfer)) { if (flow_dv_translate_item_port_id(dev, match_mask, match_value, NULL, attr))