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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.234 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.234; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.234) by CO1NAM11FT053.mail.protection.outlook.com (10.13.175.63) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5038.14 via Frontend Transport; Thu, 10 Mar 2022 04:00:28 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL101.nvidia.com (10.27.9.10) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 10 Mar 2022 04:00:27 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.9; Wed, 9 Mar 2022 20:00:24 -0800 From: Jiawei Wang To: , , CC: , , Subject: [PATCH] net/mlx5: fix the implicit tag insertion in sample flow Date: Thu, 10 Mar 2022 06:00:10 +0200 Message-ID: <20220310040010.12454-1-jiaweiw@nvidia.com> X-Mailer: git-send-email 2.18.1 MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 51da8dd3-ad0f-4a04-8afa-08da024a83cc X-MS-TrafficTypeDiagnostic: BN7PR12MB2705:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Mar 2022 04:00:28.7308 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 51da8dd3-ad0f-4a04-8afa-08da024a83cc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT053.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR12MB2705 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The flow with sample action was split into two sub-flows, and the implicit tag action with unique id was added in the prefix sub-flow, the suffix sub-flow used the tag item to match with that unique id, and the implicit set tag action was inserted next to the sample action. While there's either PUSH VLAN action or ENCAP action preceding the sample action, implicit set tag action was added after PUSH VLAN or ENCAP actions, causing flow creation failure due to rdma-core does not support this action order. This patch ensures the implicit set tag action is inserted before either PUSH VLAN or encap action (if any) in the prefix sub-flow. Fixes: 6a951567c159 ("net/mlx5: support E-Switch mirroring and jump in one flow") Cc: stable@dpdk.org Signed-off-by: Jiawei Wang Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow.c | 63 ++++++++++++++++++++++++++++++++++-- 1 file changed, 61 insertions(+), 2 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index a690e2d337..d26454a1b1 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -5831,8 +5831,9 @@ flow_sample_split_prep(struct rte_eth_dev *dev, struct mlx5_rte_flow_item_tag *tag_mask; struct rte_flow_action_jump *jump_action; uint32_t tag_id = 0; - int index; int append_index = 0; + int set_tag_idx = -1; + int index; int ret; if (sample_action_pos < 0) @@ -5841,6 +5842,52 @@ flow_sample_split_prep(struct rte_eth_dev *dev, NULL, "invalid position of sample " "action in list"); /* Prepare the actions for prefix and suffix flow. */ + if (add_tag) { + /* Update the new added tag action index preceding + * the PUSH_VLAN or ENCAP action. + */ + const struct rte_flow_action_raw_encap *raw_encap; + const struct rte_flow_action *action = actions; + int encap_idx; + int action_idx = 0; + int raw_decap_idx = -1; + int push_vlan_idx = -1; + for (; action->type != RTE_FLOW_ACTION_TYPE_END; action++) { + switch (action->type) { + case RTE_FLOW_ACTION_TYPE_RAW_DECAP: + raw_decap_idx = action_idx; + break; + case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: + raw_encap = action->conf; + if (raw_encap->size > + MLX5_ENCAPSULATION_DECISION_SIZE) { + encap_idx = raw_decap_idx != -1 ? + raw_decap_idx : action_idx; + if (encap_idx < sample_action_pos && + push_vlan_idx == -1) + set_tag_idx = encap_idx; + } + break; + case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: + case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: + encap_idx = action_idx; + if (encap_idx < sample_action_pos && + push_vlan_idx == -1) + set_tag_idx = encap_idx; + break; + case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: + case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: + push_vlan_idx = action_idx; + if (push_vlan_idx < sample_action_pos) + set_tag_idx = action_idx; + break; + default: + break; + } + action_idx++; + } + } + /* Prepare the actions for prefix and suffix flow. */ if (qrss_action_pos >= 0 && qrss_action_pos < sample_action_pos) { index = qrss_action_pos; /* Put the preceding the Queue/RSS action into prefix flow. */ @@ -5857,6 +5904,14 @@ flow_sample_split_prep(struct rte_eth_dev *dev, memcpy(actions_sfx, actions + qrss_action_pos, sizeof(struct rte_flow_action)); actions_sfx++; + } else if (add_tag && set_tag_idx >= 0) { + if (set_tag_idx > 0) + memcpy(actions_pre, actions, + sizeof(struct rte_flow_action) * set_tag_idx); + memcpy(actions_pre + set_tag_idx + 1, actions + set_tag_idx, + sizeof(struct rte_flow_action) * + (sample_action_pos - set_tag_idx)); + index = sample_action_pos; } else { index = sample_action_pos; if (index != 0) @@ -5898,13 +5953,17 @@ flow_sample_split_prep(struct rte_eth_dev *dev, RTE_FLOW_ITEM_TYPE_END, }; /* Prepare the tag action in prefix subflow. */ - actions_pre[index++] = + set_tag_idx = (set_tag_idx == -1) ? index : set_tag_idx; + actions_pre[set_tag_idx] = (struct rte_flow_action){ .type = (enum rte_flow_action_type) MLX5_RTE_FLOW_ACTION_TYPE_TAG, .conf = set_tag, }; + /* Update next sample position due to add one tag action */ + index += 1; } + /* Copy the sample action into prefix flow. */ memcpy(actions_pre + index, actions + sample_action_pos, sizeof(struct rte_flow_action)); index += 1;