From patchwork Wed Feb 9 10:42:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 107111 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 56789A04A6; Wed, 9 Feb 2022 11:35:55 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D96F941184; Wed, 9 Feb 2022 11:35:47 +0100 (CET) Received: from smtpbg516.qq.com (smtpbg516.qq.com [203.205.250.54]) by mails.dpdk.org (Postfix) with ESMTP id 63EE341143 for ; Wed, 9 Feb 2022 11:35:44 +0100 (CET) X-QQ-mid: bizesmtp37t1644402935tsua25pq Received: from wxdbg.localdomain.com (unknown [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 09 Feb 2022 18:35:34 +0800 (CST) X-QQ-SSF: 01400000002000F0L000B00A0000000 X-QQ-FEAT: b174WCRqV1hY+KIxd3MeKXnjVdrI0fNonyHVXh2c2icza9+19BoO1gvk+cmEp 9E1G6MRy+Czn1w7WEbf5qsLP7vXajvmab+1u/gFF67P1Pagq/aeOfILlNNXmFozaONy9khY Jj/NWoJiJZ6NYn6bAOAZ0yU21mjJAFSopGyqgzzEOs4e98iDuQjuM//W7+y5lF211btcneb 7GMQdJPRS4ZG1oLoBF8G8DettZD2xs6m1UR/WVFF+X12goOGMdnvLtlSIYD5Ns6ZkHJCZhI dPkzmBd0mKQj54NwI0w+02DdAOKQAkjUiJEnn8FSoPA6KvimTBU4t2Hpzye08kPFqWQQa4W 5dj272LxoqXT3dNCjGw4NCAOaq4zmdn0Z/n2fP7hK7IO+6QVqA= X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Subject: [PATCH v2 01/12] net/ngbe: fix failed to receive packets Date: Wed, 9 Feb 2022 18:42:02 +0800 Message-Id: <20220209104213.602728-2-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220209104213.602728-1-jiawenwu@trustnetic.com> References: <20220209104213.602728-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign2 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Initialize Rx packet buffer before starting RxTx, ensure to receive packets. Fixes: 62fc35e63d0e ("net/ngbe: support Rx queue start/stop") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/ngbe/base/ngbe_dummy.h | 4 ++++ drivers/net/ngbe/base/ngbe_hw.c | 27 +++++++++++++++++++++++++++ drivers/net/ngbe/base/ngbe_hw.h | 2 ++ drivers/net/ngbe/base/ngbe_type.h | 7 +++++++ drivers/net/ngbe/ngbe_ethdev.c | 1 + 5 files changed, 41 insertions(+) diff --git a/drivers/net/ngbe/base/ngbe_dummy.h b/drivers/net/ngbe/base/ngbe_dummy.h index 61b0d82bfb..d74c9f7b54 100644 --- a/drivers/net/ngbe/base/ngbe_dummy.h +++ b/drivers/net/ngbe/base/ngbe_dummy.h @@ -114,6 +114,9 @@ static inline s32 ngbe_mac_get_link_capabilities_dummy(struct ngbe_hw *TUP0, { return NGBE_ERR_OPS_DUMMY; } +static inline void ngbe_setup_pba_dummy(struct ngbe_hw *TUP0) +{ +} static inline s32 ngbe_mac_led_on_dummy(struct ngbe_hw *TUP0, u32 TUP1) { return NGBE_ERR_OPS_DUMMY; @@ -298,6 +301,7 @@ static inline void ngbe_init_ops_dummy(struct ngbe_hw *hw) hw->mac.setup_link = ngbe_mac_setup_link_dummy; hw->mac.check_link = ngbe_mac_check_link_dummy; hw->mac.get_link_capabilities = ngbe_mac_get_link_capabilities_dummy; + hw->mac.setup_pba = ngbe_setup_pba_dummy; hw->mac.led_on = ngbe_mac_led_on_dummy; hw->mac.led_off = ngbe_mac_led_off_dummy; hw->mac.set_rar = ngbe_mac_set_rar_dummy; diff --git a/drivers/net/ngbe/base/ngbe_hw.c b/drivers/net/ngbe/base/ngbe_hw.c index 0716357725..0b22ea0fb3 100644 --- a/drivers/net/ngbe/base/ngbe_hw.c +++ b/drivers/net/ngbe/base/ngbe_hw.c @@ -1609,6 +1609,30 @@ void ngbe_set_mac_anti_spoofing(struct ngbe_hw *hw, bool enable, int vf) wr32(hw, NGBE_POOLTXASMAC, pfvfspoof); } +/** + * ngbe_set_pba - Initialize Rx packet buffer + * @hw: pointer to hardware structure + * @headroom: reserve n KB of headroom + **/ +void ngbe_set_pba(struct ngbe_hw *hw) +{ + u32 rxpktsize = hw->mac.rx_pb_size; + u32 txpktsize, txpbthresh; + + /* Reserve 256 KB of headroom */ + rxpktsize -= 256; + + rxpktsize <<= 10; + wr32(hw, NGBE_PBRXSIZE, rxpktsize); + + /* Only support an equally distributed Tx packet buffer strategy. */ + txpktsize = NGBE_PBTXSIZE_MAX; + txpbthresh = (txpktsize / 1024) - NGBE_TXPKT_SIZE_MAX; + + wr32(hw, NGBE_PBTXSIZE, txpktsize); + wr32(hw, NGBE_PBTXDMATH, txpbthresh); +} + /** * ngbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing * @hw: pointer to hardware structure @@ -1907,6 +1931,8 @@ s32 ngbe_init_ops_pf(struct ngbe_hw *hw) mac->check_link = ngbe_check_mac_link_em; mac->setup_link = ngbe_setup_mac_link_em; + mac->setup_pba = ngbe_set_pba; + /* Manageability interface */ mac->init_thermal_sensor_thresh = ngbe_init_thermal_sensor_thresh; mac->check_overtemp = ngbe_mac_check_overtemp; @@ -1928,6 +1954,7 @@ s32 ngbe_init_ops_pf(struct ngbe_hw *hw) mac->mcft_size = NGBE_EM_MC_TBL_SIZE; mac->vft_size = NGBE_EM_VFT_TBL_SIZE; mac->num_rar_entries = NGBE_EM_RAR_ENTRIES; + mac->rx_pb_size = NGBE_EM_RX_PB_SIZE; mac->max_rx_queues = NGBE_EM_MAX_RX_QUEUES; mac->max_tx_queues = NGBE_EM_MAX_TX_QUEUES; diff --git a/drivers/net/ngbe/base/ngbe_hw.h b/drivers/net/ngbe/base/ngbe_hw.h index ad7e8fc2d9..b32cf87ff4 100644 --- a/drivers/net/ngbe/base/ngbe_hw.h +++ b/drivers/net/ngbe/base/ngbe_hw.h @@ -13,6 +13,7 @@ #define NGBE_EM_RAR_ENTRIES 32 #define NGBE_EM_MC_TBL_SIZE 32 #define NGBE_EM_VFT_TBL_SIZE 128 +#define NGBE_EM_RX_PB_SIZE 42 /*KB*/ s32 ngbe_init_hw(struct ngbe_hw *hw); s32 ngbe_start_hw(struct ngbe_hw *hw); @@ -44,6 +45,7 @@ s32 ngbe_update_mc_addr_list(struct ngbe_hw *hw, u8 *mc_addr_list, ngbe_mc_addr_itr func, bool clear); s32 ngbe_disable_sec_rx_path(struct ngbe_hw *hw); s32 ngbe_enable_sec_rx_path(struct ngbe_hw *hw); +void ngbe_set_pba(struct ngbe_hw *hw); s32 ngbe_setup_fc_em(struct ngbe_hw *hw); s32 ngbe_fc_enable(struct ngbe_hw *hw); diff --git a/drivers/net/ngbe/base/ngbe_type.h b/drivers/net/ngbe/base/ngbe_type.h index 12847b7272..269e087d50 100644 --- a/drivers/net/ngbe/base/ngbe_type.h +++ b/drivers/net/ngbe/base/ngbe_type.h @@ -11,6 +11,9 @@ #define NGBE_FRAME_SIZE_MAX (9728) /* Maximum frame size, +FCS */ #define NGBE_FRAME_SIZE_DFT (1522) /* Default frame size, +FCS */ #define NGBE_NUM_POOL (32) +#define NGBE_PBRXSIZE_MAX 0x00080000 /* 512KB Packet Buffer */ +#define NGBE_PBTXSIZE_MAX 0x00005000 /* 20KB Packet Buffer */ +#define NGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */ #define NGBE_MAX_QP (8) #define NGBE_MAX_UTA 128 @@ -269,6 +272,9 @@ struct ngbe_mac_info { s32 (*get_link_capabilities)(struct ngbe_hw *hw, u32 *speed, bool *autoneg); + /* Packet Buffer manipulation */ + void (*setup_pba)(struct ngbe_hw *hw); + /* LED */ s32 (*led_on)(struct ngbe_hw *hw, u32 index); s32 (*led_off)(struct ngbe_hw *hw, u32 index); @@ -311,6 +317,7 @@ struct ngbe_mac_info { u32 mcft_size; u32 vft_size; u32 num_rar_entries; + u32 rx_pb_size; u32 max_tx_queues; u32 max_rx_queues; bool get_link_status; diff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c index 0d66c32551..180489ce38 100644 --- a/drivers/net/ngbe/ngbe_ethdev.c +++ b/drivers/net/ngbe/ngbe_ethdev.c @@ -1004,6 +1004,7 @@ ngbe_dev_start(struct rte_eth_dev *dev) goto error; } + hw->mac.setup_pba(hw); ngbe_configure_port(dev); err = ngbe_dev_rxtx_start(dev); From patchwork Wed Feb 9 10:42:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 107110 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F11CBA04A6; Wed, 9 Feb 2022 11:35:48 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DB95141144; Wed, 9 Feb 2022 11:35:45 +0100 (CET) Received: from smtpbgeu2.qq.com (smtpbgeu2.qq.com [18.194.254.142]) by mails.dpdk.org (Postfix) with ESMTP id CE70E4115B for ; Wed, 9 Feb 2022 11:35:42 +0100 (CET) X-QQ-mid: bizesmtp37t1644402937tny8hlc2 Received: from wxdbg.localdomain.com (unknown [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 09 Feb 2022 18:35:36 +0800 (CST) X-QQ-SSF: 01400000002000F0L000B00A0000000 X-QQ-FEAT: XjLdFDjXUO3vbIII7KArOthq6eGt8UHoXsMJpo7HzoOxf3BmP7VKlvTlyekLS Z0xxC7mZtQyvv354huo/fbmmvp73Gb69lXExFjPf2W4RgFpqCcUeIGei2t/kOM3wSW70fcG FpUwcWK1/0B44zTPVKcRyd1GiWjshZmCz8l4i2anqbNYpoK2Pqd+yxbpBQDKaBXcZBvTf0k xCydqptwNUL0j2U2mrNkSY6ziISBuOg0eTcH8hA+hd5GaKbuwz8sP5XuMhzwyoGYwHy6ogX e4YC9swHyPdF5IlXLXTQE5TfRk26s21GZl5/jyXAqFGtVNsNo57notO+ZRbnmnf8qKcLlJL Fe9OA4/VPoWt+9dabFSUw4S25j7fnawHpvx/iEeU85BEs/EE5U= X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Subject: [PATCH v2 02/12] net/ngbe: fix link interrupt sometimes lost Date: Wed, 9 Feb 2022 18:42:03 +0800 Message-Id: <20220209104213.602728-3-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220209104213.602728-1-jiawenwu@trustnetic.com> References: <20220209104213.602728-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign6 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When the port is started and stopped continuously and quickly, one interrupt cannot be handled in time, which will cause subsequent interrupts to be lost, so that link status will cannot be updated. Fixes: b9246b8fa280 ("net/ngbe: support link update") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/ngbe/ngbe_ethdev.c | 115 +++++++++++---------------------- drivers/net/ngbe/ngbe_ethdev.h | 1 + 2 files changed, 39 insertions(+), 77 deletions(-) diff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c index 180489ce38..8e31234442 100644 --- a/drivers/net/ngbe/ngbe_ethdev.c +++ b/drivers/net/ngbe/ngbe_ethdev.c @@ -89,7 +89,6 @@ static int ngbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev); static int ngbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev); static int ngbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev); static void ngbe_dev_interrupt_handler(void *param); -static void ngbe_dev_interrupt_delayed_handler(void *param); static void ngbe_configure_msix(struct rte_eth_dev *dev); #define NGBE_SET_HWSTRIP(h, q) do {\ @@ -943,6 +942,9 @@ ngbe_dev_start(struct rte_eth_dev *dev) PMD_INIT_FUNC_TRACE(); + /* Stop the link setup handler before resetting the HW. */ + rte_eal_alarm_cancel(ngbe_dev_setup_link_alarm_handler, dev); + /* disable uio/vfio intr/eventfd mapping */ rte_intr_disable(intr_handle); @@ -1132,6 +1134,8 @@ ngbe_dev_stop(struct rte_eth_dev *dev) PMD_INIT_FUNC_TRACE(); + rte_eal_alarm_cancel(ngbe_dev_setup_link_alarm_handler, dev); + if ((hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_M88E1512_SFP || (hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_YT8521S_SFP) { /* gpio0 is used to power on/off control*/ @@ -1801,6 +1805,24 @@ ngbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) return NULL; } +void +ngbe_dev_setup_link_alarm_handler(void *param) +{ + struct rte_eth_dev *dev = (struct rte_eth_dev *)param; + struct ngbe_hw *hw = ngbe_dev_hw(dev); + struct ngbe_interrupt *intr = ngbe_dev_intr(dev); + u32 speed; + bool autoneg = false; + + speed = hw->phy.autoneg_advertised; + if (!speed) + hw->mac.get_link_capabilities(hw, &speed, &autoneg); + + hw->mac.setup_link(hw, speed, true); + + intr->flags &= ~NGBE_FLAG_NEED_LINK_CONFIG; +} + /* return 0 means link status changed, -1 means not changed */ int ngbe_dev_link_update_share(struct rte_eth_dev *dev, @@ -1838,8 +1860,16 @@ ngbe_dev_link_update_share(struct rte_eth_dev *dev, return rte_eth_linkstatus_set(dev, &link); } - if (!link_up) + if (!link_up) { + if (hw->phy.media_type == ngbe_media_type_fiber && + hw->phy.type != ngbe_phy_mvl_sfi) { + intr->flags |= NGBE_FLAG_NEED_LINK_CONFIG; + rte_eal_alarm_set(10, + ngbe_dev_setup_link_alarm_handler, dev); + } + return rte_eth_linkstatus_set(dev, &link); + } intr->flags &= ~NGBE_FLAG_NEED_LINK_CONFIG; link.link_status = RTE_ETH_LINK_UP; @@ -2062,9 +2092,6 @@ ngbe_dev_interrupt_get_status(struct rte_eth_dev *dev) struct ngbe_hw *hw = ngbe_dev_hw(dev); struct ngbe_interrupt *intr = ngbe_dev_intr(dev); - /* clear all cause mask */ - ngbe_disable_intr(hw); - /* read-on-clear nic registers here */ eicr = ((u32 *)hw->isb_mem)[NGBE_ISB_MISC]; PMD_DRV_LOG(DEBUG, "eicr %x", eicr); @@ -2084,6 +2111,8 @@ ngbe_dev_interrupt_get_status(struct rte_eth_dev *dev) if (eicr & NGBE_ICRMISC_GPIO) intr->flags |= NGBE_FLAG_NEED_LINK_UPDATE; + ((u32 *)hw->isb_mem)[NGBE_ISB_MISC] = 0; + return 0; } @@ -2136,7 +2165,6 @@ static int ngbe_dev_interrupt_action(struct rte_eth_dev *dev) { struct ngbe_interrupt *intr = ngbe_dev_intr(dev); - int64_t timeout; PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags); @@ -2152,31 +2180,11 @@ ngbe_dev_interrupt_action(struct rte_eth_dev *dev) rte_eth_linkstatus_get(dev, &link); ngbe_dev_link_update(dev, 0); - - /* likely to up */ - if (link.link_status != RTE_ETH_LINK_UP) - /* handle it 1 sec later, wait it being stable */ - timeout = NGBE_LINK_UP_CHECK_TIMEOUT; - /* likely to down */ - else - /* handle it 4 sec later, wait it being stable */ - timeout = NGBE_LINK_DOWN_CHECK_TIMEOUT; - + intr->flags &= ~NGBE_FLAG_NEED_LINK_UPDATE; ngbe_dev_link_status_print(dev); - if (rte_eal_alarm_set(timeout * 1000, - ngbe_dev_interrupt_delayed_handler, - (void *)dev) < 0) { - PMD_DRV_LOG(ERR, "Error setting alarm"); - } else { - /* remember original mask */ - intr->mask_misc_orig = intr->mask_misc; - /* only disable lsc interrupt */ - intr->mask_misc &= ~NGBE_ICRMISC_PHY; - - intr->mask_orig = intr->mask; - /* only disable all misc interrupts */ - intr->mask &= ~(1ULL << NGBE_MISC_VEC_ID); - } + if (dev->data->dev_link.link_speed != link.link_speed) + rte_eth_dev_callback_process(dev, + RTE_ETH_EVENT_INTR_LSC, NULL); } PMD_DRV_LOG(DEBUG, "enable intr immediately"); @@ -2185,53 +2193,6 @@ ngbe_dev_interrupt_action(struct rte_eth_dev *dev) return 0; } -/** - * Interrupt handler which shall be registered for alarm callback for delayed - * handling specific interrupt to wait for the stable nic state. As the - * NIC interrupt state is not stable for ngbe after link is just down, - * it needs to wait 4 seconds to get the stable status. - * - * @param param - * The address of parameter (struct rte_eth_dev *) registered before. - */ -static void -ngbe_dev_interrupt_delayed_handler(void *param) -{ - struct rte_eth_dev *dev = (struct rte_eth_dev *)param; - struct ngbe_interrupt *intr = ngbe_dev_intr(dev); - struct ngbe_hw *hw = ngbe_dev_hw(dev); - uint32_t eicr; - - ngbe_disable_intr(hw); - - eicr = ((u32 *)hw->isb_mem)[NGBE_ISB_MISC]; - if (eicr & NGBE_ICRMISC_VFMBX) - ngbe_pf_mbx_process(dev); - - if (intr->flags & NGBE_FLAG_NEED_LINK_UPDATE) { - ngbe_dev_link_update(dev, 0); - intr->flags &= ~NGBE_FLAG_NEED_LINK_UPDATE; - ngbe_dev_link_status_print(dev); - rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, - NULL); - } - - if (intr->flags & NGBE_FLAG_MACSEC) { - rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, - NULL); - intr->flags &= ~NGBE_FLAG_MACSEC; - } - - /* restore original mask */ - intr->mask_misc = intr->mask_misc_orig; - intr->mask_misc_orig = 0; - intr->mask = intr->mask_orig; - intr->mask_orig = 0; - - PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr); - ngbe_enable_intr(dev); -} - /** * Interrupt handler triggered by NIC for handling * specific interrupt. diff --git a/drivers/net/ngbe/ngbe_ethdev.h b/drivers/net/ngbe/ngbe_ethdev.h index bb96f6a5e7..8d500fd38c 100644 --- a/drivers/net/ngbe/ngbe_ethdev.h +++ b/drivers/net/ngbe/ngbe_ethdev.h @@ -341,6 +341,7 @@ void ngbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on); void ngbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask); +void ngbe_dev_setup_link_alarm_handler(void *param); void ngbe_read_stats_registers(struct ngbe_hw *hw, struct ngbe_hw_stats *hw_stats); From patchwork Wed Feb 9 10:42:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 107112 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2AA4FA04A6; Wed, 9 Feb 2022 11:36:03 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 32B0C41182; Wed, 9 Feb 2022 11:35:51 +0100 (CET) Received: from smtpbg501.qq.com (smtpbg501.qq.com [203.205.250.101]) by mails.dpdk.org (Postfix) with ESMTP id 79B9041157 for ; Wed, 9 Feb 2022 11:35:48 +0100 (CET) X-QQ-mid: bizesmtp37t1644402939tlcbruix Received: from wxdbg.localdomain.com (unknown [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 09 Feb 2022 18:35:38 +0800 (CST) X-QQ-SSF: 01400000002000F0L000B00A0000000 X-QQ-FEAT: 3u0oYPVhaePxerLIIsyB4dNPv8bPlC/Fw+G1rbfN9knz90xcatp7h0et+uB8b JbASdu/z5VaEN1wJox0+tCA6K22N9dMCasyMRfMteJqGeDIzybTMS0LxYBMquX9GMWscs5S ix6EdeAz/MRxGxfexfb7L4w1tKvyVh1AsKGL+II7XCUeZU7SkctLZ2RSefAO+MwTpRV7VJv 3q2nfiJLhhg4ePGc6AMeKM1g7dj8kaW36TtIinNCB3FlUBoYjcP7K4chx2IGYQdoyagj/6i n3a7VtHYij4TjHJ0KNJtxrWdM5Bp6PqJ2kCcIYR+Cz4+LNXN+pG4SFd6c+4r7qjMF15gmpS miatjV5mhZYKb4K2MMs+cqPdZJyUh+xAe9gshbibWfBk0K9KeWaDqT1SuAllg== X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Subject: [PATCH v2 03/12] net/ngbe: fix Tx pending Date: Wed, 9 Feb 2022 18:42:04 +0800 Message-Id: <20220209104213.602728-4-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220209104213.602728-1-jiawenwu@trustnetic.com> References: <20220209104213.602728-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign6 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add commands requesting firmware to enable or disable PCIe bus master. Disable PCIe master access to clear BME when stop hardware, and verify there are no pending requests. Move disabling Tx queue after disabling PCIe bus master, to ensure that there are no packets left to cause Tx hang. Fixes: 78710873c2f3 ("net/ngbe: add HW initialization") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/ngbe/base/ngbe_hw.c | 76 +++++++++++++++++++++++++++---- drivers/net/ngbe/base/ngbe_hw.h | 1 + drivers/net/ngbe/base/ngbe_mng.c | 57 +++++++++++++++++++++++ drivers/net/ngbe/base/ngbe_mng.h | 21 +++++++++ drivers/net/ngbe/base/ngbe_regs.h | 3 ++ drivers/net/ngbe/base/ngbe_type.h | 3 ++ drivers/net/ngbe/ngbe_ethdev.c | 7 ++- 7 files changed, 158 insertions(+), 10 deletions(-) diff --git a/drivers/net/ngbe/base/ngbe_hw.c b/drivers/net/ngbe/base/ngbe_hw.c index 0b22ea0fb3..782fd71d29 100644 --- a/drivers/net/ngbe/base/ngbe_hw.c +++ b/drivers/net/ngbe/base/ngbe_hw.c @@ -350,8 +350,8 @@ void ngbe_set_lan_id_multi_port(struct ngbe_hw *hw) **/ s32 ngbe_stop_hw(struct ngbe_hw *hw) { - u32 reg_val; u16 i; + s32 status = 0; DEBUGFUNC("ngbe_stop_hw"); @@ -372,16 +372,27 @@ s32 ngbe_stop_hw(struct ngbe_hw *hw) wr32(hw, NGBE_ICRMISC, NGBE_ICRMISC_MASK); wr32(hw, NGBE_ICR(0), NGBE_ICR_MASK); - /* Disable the transmit unit. Each queue must be disabled. */ - for (i = 0; i < hw->mac.max_tx_queues; i++) - wr32(hw, NGBE_TXCFG(i), NGBE_TXCFG_FLUSH); + wr32(hw, NGBE_BMECTL, 0x3); /* Disable the receive unit by stopping each queue */ - for (i = 0; i < hw->mac.max_rx_queues; i++) { - reg_val = rd32(hw, NGBE_RXCFG(i)); - reg_val &= ~NGBE_RXCFG_ENA; - wr32(hw, NGBE_RXCFG(i), reg_val); - } + for (i = 0; i < hw->mac.max_rx_queues; i++) + wr32(hw, NGBE_RXCFG(i), 0); + + /* flush all queues disables */ + ngbe_flush(hw); + msec_delay(2); + + /* + * Prevent the PCI-E bus from hanging by disabling PCI-E master + * access and verify no pending requests + */ + status = ngbe_set_pcie_master(hw, false); + if (status) + return status; + + /* Disable the transmit unit. Each queue must be disabled. */ + for (i = 0; i < hw->mac.max_tx_queues; i++) + wr32(hw, NGBE_TXCFG(i), 0); /* flush all queues disables */ ngbe_flush(hw); @@ -1076,6 +1087,53 @@ void ngbe_fc_autoneg(struct ngbe_hw *hw) } } +/** + * ngbe_set_pcie_master - Disable or Enable PCI-express master access + * @hw: pointer to hardware structure + * + * Disables PCI-Express master access and verifies there are no pending + * requests. NGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable + * bit hasn't caused the master requests to be disabled, else 0 + * is returned signifying master requests disabled. + **/ +s32 ngbe_set_pcie_master(struct ngbe_hw *hw, bool enable) +{ + s32 status = 0; + u16 addr = 0x04; + u32 data, i; + + DEBUGFUNC("ngbe_set_pcie_master"); + + ngbe_hic_pcie_read(hw, addr, &data, 4); + if (enable) + data |= 0x04; + else + data &= ~0x04; + + ngbe_hic_pcie_write(hw, addr, &data, 4); + + if (enable) + goto out; + + /* Exit if master requests are blocked */ + if (!(rd32(hw, NGBE_BMEPEND)) || + NGBE_REMOVED(hw->hw_addr)) + goto out; + + /* Poll for master request bit to clear */ + for (i = 0; i < NGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { + usec_delay(100); + if (!(rd32(hw, NGBE_BMEPEND))) + goto out; + } + + DEBUGOUT("PCIe transaction pending bit also did not clear.\n"); + status = NGBE_ERR_MASTER_REQUESTS_PENDING; + +out: + return status; +} + /** * ngbe_acquire_swfw_sync - Acquire SWFW semaphore * @hw: pointer to hardware structure diff --git a/drivers/net/ngbe/base/ngbe_hw.h b/drivers/net/ngbe/base/ngbe_hw.h index b32cf87ff4..7e0e23b195 100644 --- a/drivers/net/ngbe/base/ngbe_hw.h +++ b/drivers/net/ngbe/base/ngbe_hw.h @@ -54,6 +54,7 @@ void ngbe_fc_autoneg(struct ngbe_hw *hw); s32 ngbe_validate_mac_addr(u8 *mac_addr); s32 ngbe_acquire_swfw_sync(struct ngbe_hw *hw, u32 mask); void ngbe_release_swfw_sync(struct ngbe_hw *hw, u32 mask); +s32 ngbe_set_pcie_master(struct ngbe_hw *hw, bool enable); s32 ngbe_set_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq); s32 ngbe_clear_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq); diff --git a/drivers/net/ngbe/base/ngbe_mng.c b/drivers/net/ngbe/base/ngbe_mng.c index a3dd8093ce..68e06e2c24 100644 --- a/drivers/net/ngbe/base/ngbe_mng.c +++ b/drivers/net/ngbe/base/ngbe_mng.c @@ -243,6 +243,63 @@ s32 ngbe_hic_sr_write(struct ngbe_hw *hw, u32 addr, u8 *buf, int len) return err; } +s32 ngbe_hic_pcie_read(struct ngbe_hw *hw, u16 addr, u32 *buf, int len) +{ + struct ngbe_hic_read_pcie command; + u32 value = 0; + int err, i = 0; + + if (len > NGBE_PMMBX_DATA_SIZE) + return NGBE_ERR_HOST_INTERFACE_COMMAND; + + memset(&command, 0, sizeof(command)); + command.hdr.cmd = FW_PCIE_READ_CMD; + command.hdr.buf_len = sizeof(command) - sizeof(command.hdr); + command.hdr.checksum = FW_DEFAULT_CHECKSUM; + command.lan_id = hw->bus.lan_id; + command.addr = addr; + + err = ngbe_host_interface_command(hw, (u32 *)&command, + sizeof(command), NGBE_HI_COMMAND_TIMEOUT, false); + if (err) + return err; + + while (i < (len >> 2)) { + value = rd32a(hw, NGBE_MNGMBX, FW_PCIE_BUSMASTER_OFFSET + i); + ((u32 *)buf)[i] = value; + i++; + } + + return 0; +} + +s32 ngbe_hic_pcie_write(struct ngbe_hw *hw, u16 addr, u32 *buf, int len) +{ + struct ngbe_hic_write_pcie command; + u32 value = 0; + int err, i = 0; + + while (i < (len >> 2)) { + value = ((u32 *)buf)[i]; + i++; + } + + memset(&command, 0, sizeof(command)); + command.hdr.cmd = FW_PCIE_WRITE_CMD; + command.hdr.buf_len = sizeof(command) - sizeof(command.hdr); + command.hdr.checksum = FW_DEFAULT_CHECKSUM; + command.lan_id = hw->bus.lan_id; + command.addr = addr; + command.data = value; + + err = ngbe_host_interface_command(hw, (u32 *)&command, + sizeof(command), NGBE_HI_COMMAND_TIMEOUT, false); + if (err) + return err; + + return 0; +} + s32 ngbe_hic_check_cap(struct ngbe_hw *hw) { struct ngbe_hic_read_shadow_ram command; diff --git a/drivers/net/ngbe/base/ngbe_mng.h b/drivers/net/ngbe/base/ngbe_mng.h index e3d0309cbc..321338a051 100644 --- a/drivers/net/ngbe/base/ngbe_mng.h +++ b/drivers/net/ngbe/base/ngbe_mng.h @@ -20,6 +20,9 @@ #define FW_READ_SHADOW_RAM_LEN 0x6 #define FW_WRITE_SHADOW_RAM_CMD 0x33 #define FW_WRITE_SHADOW_RAM_LEN 0xA /* 8 plus 1 WORD to write */ +#define FW_PCIE_READ_CMD 0xEC +#define FW_PCIE_WRITE_CMD 0xED +#define FW_PCIE_BUSMASTER_OFFSET 2 #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */ #define FW_NVM_DATA_OFFSET 3 #define FW_EEPROM_CHECK_STATUS 0xE9 @@ -76,8 +79,26 @@ struct ngbe_hic_write_shadow_ram { u16 pad3; }; +struct ngbe_hic_read_pcie { + struct ngbe_hic_hdr hdr; + u8 lan_id; + u8 rsvd; + u16 addr; + u32 data; +}; + +struct ngbe_hic_write_pcie { + struct ngbe_hic_hdr hdr; + u8 lan_id; + u8 rsvd; + u16 addr; + u32 data; +}; + s32 ngbe_hic_sr_read(struct ngbe_hw *hw, u32 addr, u8 *buf, int len); s32 ngbe_hic_sr_write(struct ngbe_hw *hw, u32 addr, u8 *buf, int len); +s32 ngbe_hic_pcie_read(struct ngbe_hw *hw, u16 addr, u32 *buf, int len); +s32 ngbe_hic_pcie_write(struct ngbe_hw *hw, u16 addr, u32 *buf, int len); s32 ngbe_hic_check_cap(struct ngbe_hw *hw); #endif /* _NGBE_MNG_H_ */ diff --git a/drivers/net/ngbe/base/ngbe_regs.h b/drivers/net/ngbe/base/ngbe_regs.h index 872b008c46..e84bfdf88a 100644 --- a/drivers/net/ngbe/base/ngbe_regs.h +++ b/drivers/net/ngbe/base/ngbe_regs.h @@ -866,6 +866,9 @@ enum ngbe_5tuple_protocol { * PF(Physical Function) Registers ******************************************************************************/ /* Interrupt */ +#define NGBE_BMECTL 0x012020 +#define NGBE_BMECTL_VFDRP MS(1, 0x1) +#define NGBE_BMECTL_PFDRP MS(0, 0x1) #define NGBE_ICRMISC 0x000100 #define NGBE_ICRMISC_MASK MS(8, 0xFFFFFF) #define NGBE_ICRMISC_RST MS(10, 0x1) /* device reset event */ diff --git a/drivers/net/ngbe/base/ngbe_type.h b/drivers/net/ngbe/base/ngbe_type.h index 269e087d50..4c995e7397 100644 --- a/drivers/net/ngbe/base/ngbe_type.h +++ b/drivers/net/ngbe/base/ngbe_type.h @@ -17,6 +17,9 @@ #define NGBE_MAX_QP (8) #define NGBE_MAX_UTA 128 +#define NGBE_PCI_MASTER_DISABLE_TIMEOUT 800 + + #define NGBE_ALIGN 128 /* as intel did */ #define NGBE_ISB_SIZE 16 diff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c index 8e31234442..30c9e68579 100644 --- a/drivers/net/ngbe/ngbe_ethdev.c +++ b/drivers/net/ngbe/ngbe_ethdev.c @@ -950,7 +950,6 @@ ngbe_dev_start(struct rte_eth_dev *dev) /* stop adapter */ hw->adapter_stopped = 0; - ngbe_stop_hw(hw); /* reinitialize adapter, this calls reset and start */ hw->nb_rx_queues = dev->data->nb_rx_queues; @@ -961,6 +960,8 @@ ngbe_dev_start(struct rte_eth_dev *dev) hw->mac.start_hw(hw); hw->mac.get_link_status = true; + ngbe_set_pcie_master(hw, true); + /* configure PF module if SRIOV enabled */ ngbe_pf_host_configure(dev); @@ -1174,6 +1175,8 @@ ngbe_dev_stop(struct rte_eth_dev *dev) rte_intr_efd_disable(intr_handle); rte_intr_vec_list_free(intr_handle); + ngbe_set_pcie_master(hw, true); + adapter->rss_reta_updated = 0; hw->adapter_stopped = true; @@ -1202,6 +1205,8 @@ ngbe_dev_close(struct rte_eth_dev *dev) ngbe_dev_free_queues(dev); + ngbe_set_pcie_master(hw, false); + /* reprogram the RAR[0] in case user changed it. */ ngbe_set_rar(hw, 0, hw->mac.addr, 0, true); From patchwork Wed Feb 9 10:42:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 107115 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8B350A04A6; Wed, 9 Feb 2022 11:36:23 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5264641199; Wed, 9 Feb 2022 11:35:55 +0100 (CET) Received: from smtpbgsg2.qq.com (smtpbgsg2.qq.com [54.254.200.128]) by mails.dpdk.org (Postfix) with ESMTP id 8E39E41199 for ; Wed, 9 Feb 2022 11:35:53 +0100 (CET) X-QQ-mid: bizesmtp37t1644402941tfp89w07 Received: from wxdbg.localdomain.com (unknown [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 09 Feb 2022 18:35:40 +0800 (CST) X-QQ-SSF: 01400000002000F0L000B00A0000000 X-QQ-FEAT: TskX/GkkryDC37zX4bS7/ZEir6CJs2YZvbfb1y/hTopYn5kMcRlTtJZCp908q PjaRousA4Wq0OKK1CGwhCu0OIla9FVFSGMvuPRiWciBkxhdThFNBF4gRkZ0TpsI9zSlSyvh bEVLqQHyc9TMSzoQHUDenZ13NYfoL/qt8NjWHCxvfkLAS878IUbvsbKVraq9m6zjRm1lPgn j9F27BmubGRVZrFqq7pjJ0/qgCgm2H3gmmJHUGPW/eg8oxjjWsRC3cbQMz8XmWk2eEMAP2j CBghrR0g9KIXhYtav39uwujJO4Stm9mE0i9866dq6EIZAa2ce89YGqXcSqI2jVDp1fcBl6b FC/kvf3eEG55TNGFCeMGpZVeXpBM/7TRbl2XyI+oCKFK9LYgGY= X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Subject: [PATCH v2 04/12] net/ngbe: fix RxTx packet statistics Date: Wed, 9 Feb 2022 18:42:05 +0800 Message-Id: <20220209104213.602728-5-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220209104213.602728-1-jiawenwu@trustnetic.com> References: <20220209104213.602728-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign6 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fix specific length packet statistics caused by wrong register addresses. Fixes: ed5f3bd3373e ("net/ngbe: define registers") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/ngbe/base/ngbe_regs.h | 48 +++++++++++++++---------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/drivers/net/ngbe/base/ngbe_regs.h b/drivers/net/ngbe/base/ngbe_regs.h index e84bfdf88a..6432ad8736 100644 --- a/drivers/net/ngbe/base/ngbe_regs.h +++ b/drivers/net/ngbe/base/ngbe_regs.h @@ -785,30 +785,30 @@ enum ngbe_5tuple_protocol { #define NGBE_MACRXERRCRCH 0x01192C #define NGBE_MACRXERRLENL 0x011978 #define NGBE_MACRXERRLENH 0x01197C -#define NGBE_MACRX1TO64L 0x001940 -#define NGBE_MACRX1TO64H 0x001944 -#define NGBE_MACRX65TO127L 0x001948 -#define NGBE_MACRX65TO127H 0x00194C -#define NGBE_MACRX128TO255L 0x001950 -#define NGBE_MACRX128TO255H 0x001954 -#define NGBE_MACRX256TO511L 0x001958 -#define NGBE_MACRX256TO511H 0x00195C -#define NGBE_MACRX512TO1023L 0x001960 -#define NGBE_MACRX512TO1023H 0x001964 -#define NGBE_MACRX1024TOMAXL 0x001968 -#define NGBE_MACRX1024TOMAXH 0x00196C -#define NGBE_MACTX1TO64L 0x001834 -#define NGBE_MACTX1TO64H 0x001838 -#define NGBE_MACTX65TO127L 0x00183C -#define NGBE_MACTX65TO127H 0x001840 -#define NGBE_MACTX128TO255L 0x001844 -#define NGBE_MACTX128TO255H 0x001848 -#define NGBE_MACTX256TO511L 0x00184C -#define NGBE_MACTX256TO511H 0x001850 -#define NGBE_MACTX512TO1023L 0x001854 -#define NGBE_MACTX512TO1023H 0x001858 -#define NGBE_MACTX1024TOMAXL 0x00185C -#define NGBE_MACTX1024TOMAXH 0x001860 +#define NGBE_MACRX1TO64L 0x011940 +#define NGBE_MACRX1TO64H 0x011944 +#define NGBE_MACRX65TO127L 0x011948 +#define NGBE_MACRX65TO127H 0x01194C +#define NGBE_MACRX128TO255L 0x011950 +#define NGBE_MACRX128TO255H 0x011954 +#define NGBE_MACRX256TO511L 0x011958 +#define NGBE_MACRX256TO511H 0x01195C +#define NGBE_MACRX512TO1023L 0x011960 +#define NGBE_MACRX512TO1023H 0x011964 +#define NGBE_MACRX1024TOMAXL 0x011968 +#define NGBE_MACRX1024TOMAXH 0x01196C +#define NGBE_MACTX1TO64L 0x011834 +#define NGBE_MACTX1TO64H 0x011838 +#define NGBE_MACTX65TO127L 0x01183C +#define NGBE_MACTX65TO127H 0x011840 +#define NGBE_MACTX128TO255L 0x011844 +#define NGBE_MACTX128TO255H 0x011848 +#define NGBE_MACTX256TO511L 0x01184C +#define NGBE_MACTX256TO511H 0x011850 +#define NGBE_MACTX512TO1023L 0x011854 +#define NGBE_MACTX512TO1023H 0x011858 +#define NGBE_MACTX1024TOMAXL 0x01185C +#define NGBE_MACTX1024TOMAXH 0x011860 #define NGBE_MACRXUNDERSIZE 0x011938 #define NGBE_MACRXOVERSIZE 0x01193C From patchwork Wed Feb 9 10:42:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 107114 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9D471A04A6; Wed, 9 Feb 2022 11:36:17 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4B75C411E1; Wed, 9 Feb 2022 11:35:53 +0100 (CET) Received: from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166]) by mails.dpdk.org (Postfix) with ESMTP id 860BF411B2 for ; Wed, 9 Feb 2022 11:35:51 +0100 (CET) X-QQ-mid: bizesmtp37t1644402943tcx5ws31 Received: from wxdbg.localdomain.com (unknown [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 09 Feb 2022 18:35:42 +0800 (CST) X-QQ-SSF: 01400000002000F0L000B00A0000000 X-QQ-FEAT: jfdGVjI73+RkmG2ygSEvPskmtH364P1KcwvGy6RlQm1cW9Qf9CR9g+hO4gIQa 73PAZUww5uxhH7+X5ACh6TDCVpfO9MUU120n1pUPYjSf7t5IBHhOTMgDfX5eoeNACb5aIjT vxHVTKXp/LtrBWfRktn12O7OY5nFaevJrQQB8Rfj58yeW4P3XUN9+7BUcLK0IKfJxIohrZA ly2khjfKsT8G7jtwzHuWkNVSPKQz1z4RrgN0QIe7Q/AEK4EqP4gKAgQfp5p46+yYRKSKuaU FsFLfyHyNP1UQThmrtsRCRMHi0LCvXpy3FZmA1R6EEL6kz0VPV20uEh1ty9Qmka+hLquYnh xMuiD1RFwVgPE3UMUXmKgM2YB38gOll0VxvJZaoCbhQFnsn/XkEh/H1gW1p/g== X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu Subject: [PATCH v2 05/12] net/ngbe: optimize the PHY initialization process Date: Wed, 9 Feb 2022 18:42:06 +0800 Message-Id: <20220209104213.602728-6-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220209104213.602728-1-jiawenwu@trustnetic.com> References: <20220209104213.602728-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign7 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Reduce the probability of PHY init failure, And add its error return. Signed-off-by: Jiawen Wu --- drivers/net/ngbe/base/ngbe_hw.c | 7 ++--- drivers/net/ngbe/base/ngbe_phy_rtl.c | 40 +++++++++++++--------------- drivers/net/ngbe/ngbe_ethdev.c | 6 ++++- 3 files changed, 28 insertions(+), 25 deletions(-) diff --git a/drivers/net/ngbe/base/ngbe_hw.c b/drivers/net/ngbe/base/ngbe_hw.c index 782fd71d29..72d475ccf9 100644 --- a/drivers/net/ngbe/base/ngbe_hw.c +++ b/drivers/net/ngbe/base/ngbe_hw.c @@ -1145,6 +1145,7 @@ s32 ngbe_set_pcie_master(struct ngbe_hw *hw, bool enable) s32 ngbe_acquire_swfw_sync(struct ngbe_hw *hw, u32 mask) { u32 mngsem = 0; + u32 fwsm = 0; u32 swmask = NGBE_MNGSEM_SW(mask); u32 fwmask = NGBE_MNGSEM_FW(mask); u32 timeout = 200; @@ -1173,9 +1174,9 @@ s32 ngbe_acquire_swfw_sync(struct ngbe_hw *hw, u32 mask) } } - /* If time expired clear the bits holding the lock and retry */ - if (mngsem & (fwmask | swmask)) - ngbe_release_swfw_sync(hw, mngsem & (fwmask | swmask)); + fwsm = rd32(hw, NGBE_MNGFWSYNC); + DEBUGOUT("SWFW semaphore not granted: MNG_SWFW_SYNC = 0x%x, MNG_FW_SM = 0x%x\n", + mngsem, fwsm); msec_delay(5); return NGBE_ERR_SWFW_SYNC; diff --git a/drivers/net/ngbe/base/ngbe_phy_rtl.c b/drivers/net/ngbe/base/ngbe_phy_rtl.c index 7b08b7a46c..c59efe3153 100644 --- a/drivers/net/ngbe/base/ngbe_phy_rtl.c +++ b/drivers/net/ngbe/base/ngbe_phy_rtl.c @@ -4,8 +4,6 @@ #include "ngbe_phy_rtl.h" -#define RTL_PHY_RST_WAIT_PERIOD 5 - s32 ngbe_read_phy_reg_rtl(struct ngbe_hw *hw, u32 reg_addr, u32 device_type, u16 *phy_data) { @@ -61,34 +59,44 @@ s32 ngbe_init_phy_rtl(struct ngbe_hw *hw) return NGBE_ERR_PHY_TIMEOUT; } - for (i = 0; i < 1000; i++) { - hw->phy.read_reg(hw, RTL_INSR, 0xa43, &value); - if (value & RTL_INSR_ACCESS) - break; + hw->phy.write_reg(hw, RTL_SCR, 0xa46, RTL_SCR_EFUSE); + hw->phy.read_reg(hw, RTL_SCR, 0xa46, &value); + if (!(value & RTL_SCR_EFUSE)) { + DEBUGOUT("Write EFUSE failed.\n"); + return NGBE_ERR_PHY_TIMEOUT; } - hw->phy.write_reg(hw, RTL_SCR, 0xa46, RTL_SCR_EFUSE); for (i = 0; i < 1000; i++) { hw->phy.read_reg(hw, RTL_INSR, 0xa43, &value); if (value & RTL_INSR_ACCESS) break; + msec_delay(1); } if (i == 1000) - return NGBE_ERR_PHY_TIMEOUT; + DEBUGOUT("PHY wait mdio 1 access timeout.\n"); + hw->phy.write_reg(hw, RTL_SCR, 0xa46, RTL_SCR_EXTINI); + hw->phy.read_reg(hw, RTL_SCR, 0xa46, &value); + if (!(value & RTL_SCR_EXTINI)) { + DEBUGOUT("Write EXIINI failed.\n"); + return NGBE_ERR_PHY_TIMEOUT; + } + for (i = 0; i < 1000; i++) { hw->phy.read_reg(hw, RTL_INSR, 0xa43, &value); if (value & RTL_INSR_ACCESS) break; + msec_delay(1); } if (i == 1000) - return NGBE_ERR_PHY_TIMEOUT; + DEBUGOUT("PHY wait mdio 2 access timeout.\n"); for (i = 0; i < 1000; i++) { hw->phy.read_reg(hw, RTL_GSR, 0xa42, &value); if ((value & RTL_GSR_ST) == RTL_GSR_ST_LANON) break; + msec_delay(1); } if (i == 1000) return NGBE_ERR_PHY_TIMEOUT; @@ -226,7 +234,7 @@ s32 ngbe_setup_phy_link_rtl(struct ngbe_hw *hw, s32 ngbe_reset_phy_rtl(struct ngbe_hw *hw) { - u16 value = 0, i; + u16 value = 0; s32 status = 0; DEBUGFUNC("ngbe_reset_phy_rtl"); @@ -234,17 +242,7 @@ s32 ngbe_reset_phy_rtl(struct ngbe_hw *hw) value |= RTL_BMCR_RESET; status = hw->phy.write_reg(hw, RTL_BMCR, RTL_DEV_ZERO, value); - for (i = 0; i < RTL_PHY_RST_WAIT_PERIOD; i++) { - status = hw->phy.read_reg(hw, RTL_BMCR, RTL_DEV_ZERO, &value); - if (!(value & RTL_BMCR_RESET)) - break; - msleep(1); - } - - if (i == RTL_PHY_RST_WAIT_PERIOD) { - DEBUGOUT("PHY reset polling failed to complete.\n"); - return NGBE_ERR_RESET_FAILED; - } + msec_delay(5); return status; } diff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c index 30c9e68579..cc530fdced 100644 --- a/drivers/net/ngbe/ngbe_ethdev.c +++ b/drivers/net/ngbe/ngbe_ethdev.c @@ -1058,7 +1058,11 @@ ngbe_dev_start(struct rte_eth_dev *dev) speed |= NGBE_LINK_SPEED_10M_FULL; } - hw->phy.init_hw(hw); + err = hw->phy.init_hw(hw); + if (err != 0) { + PMD_INIT_LOG(ERR, "PHY init failed"); + goto error; + } err = hw->mac.setup_link(hw, speed, link_up); if (err != 0) goto error; From patchwork Wed Feb 9 10:42:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 107113 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 15889A04A6; Wed, 9 Feb 2022 11:36:09 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2622E411B8; Wed, 9 Feb 2022 11:35:52 +0100 (CET) Received: from smtpbg506.qq.com (smtpbg506.qq.com [203.205.250.33]) by mails.dpdk.org (Postfix) with ESMTP id 0BD8641182 for ; Wed, 9 Feb 2022 11:35:48 +0100 (CET) X-QQ-mid: bizesmtp37t1644402945tb64gmx2 Received: from wxdbg.localdomain.com (unknown [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 09 Feb 2022 18:35:44 +0800 (CST) X-QQ-SSF: 01400000002000F0L000B00A0000000 X-QQ-FEAT: 1vYwxPNStGmf9bON1C5sDZ6EjmgnuYPWATcbVHq7QmpSkCKh/IFuxd8ldOhHW piotFq77SOm+xlACOsiVNaCQGdY+FWrAA9wyPtETGtr9uI7I5uExmQ3w/WzCBFaUGyvX/5A oZ0nznvQ6rltEtDAz4wKIAyg09F02whaiXytdb1+1u3fGys6DNBKSyM//f4DCsCdgMPxe2h cITiDp6sP1P8ZkNuvgu73tUSpJMyFaInaecd4Puv3vMk+uiTXC+oOoZFhDK+LIdD00JMQXs Q2MoAZh4a+UYefg28TQ74Y1N1KFSKYlCv1VuK4Ap/d3sczAzUhFhWYVOEswJLe8cFiDwwkc P1KkhZhEfnv3k8CecJXDXuvlhVWre+I8J+vIY7D6SV1KQmgvIc= X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu Subject: [PATCH v2 06/12] net/ngbe: add support to custom PHY interfaces Date: Wed, 9 Feb 2022 18:42:07 +0800 Message-Id: <20220209104213.602728-7-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220209104213.602728-1-jiawenwu@trustnetic.com> References: <20220209104213.602728-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign1 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Support sub_device ID 61/62/64 for YT8521S SFP, and 51/52 for M88E1512 PHY. Signed-off-by: Jiawen Wu --- doc/guides/rel_notes/release_22_03.rst | 7 + drivers/net/ngbe/base/ngbe_devids.h | 12 +- drivers/net/ngbe/base/ngbe_hw.c | 50 +++++-- drivers/net/ngbe/base/ngbe_phy.c | 27 ++-- drivers/net/ngbe/base/ngbe_phy.h | 2 +- drivers/net/ngbe/base/ngbe_phy_mvl.c | 55 +++++++- drivers/net/ngbe/base/ngbe_phy_mvl.h | 5 + drivers/net/ngbe/base/ngbe_phy_yt.c | 182 +++++++++++++++++++++---- drivers/net/ngbe/base/ngbe_phy_yt.h | 19 ++- drivers/net/ngbe/base/ngbe_type.h | 8 ++ drivers/net/ngbe/ngbe_ethdev.c | 6 +- 11 files changed, 314 insertions(+), 59 deletions(-) diff --git a/doc/guides/rel_notes/release_22_03.rst b/doc/guides/rel_notes/release_22_03.rst index 746f50e84f..233c34a2d0 100644 --- a/doc/guides/rel_notes/release_22_03.rst +++ b/doc/guides/rel_notes/release_22_03.rst @@ -69,6 +69,13 @@ New Features * Added AES-XCBC support in lookaside protocol (IPsec) for CN9K & CN10K. * Added AES-CMAC support in CN9K & CN10K. +* **Updated Wangxun ngbe driver.** + + * Added support for devices of custom PHY interfaces. + - M88E1512 PHY connects to RJ45 + - M88E1512 PHY connects to RGMII combo + - YT8521S PHY connects to SFP + * **Added an API to retrieve event port id of ethdev Rx adapter.** The new API ``rte_event_eth_rx_adapter_event_port_get()`` was added. diff --git a/drivers/net/ngbe/base/ngbe_devids.h b/drivers/net/ngbe/base/ngbe_devids.h index 6010cc050e..83eedf423e 100644 --- a/drivers/net/ngbe/base/ngbe_devids.h +++ b/drivers/net/ngbe/base/ngbe_devids.h @@ -19,9 +19,11 @@ #define NGBE_SUB_DEV_ID_EM_VF 0x0110 #define NGBE_DEV_ID_EM 0x0100 #define NGBE_SUB_DEV_ID_EM_MVL_RGMII 0x0200 +#define NGBE_SUB_DEV_ID_EM_MVL_MIX 0x0252 #define NGBE_SUB_DEV_ID_EM_MVL_SFP 0x0403 #define NGBE_SUB_DEV_ID_EM_RTL_SGMII 0x0410 #define NGBE_SUB_DEV_ID_EM_YT8521S_SFP 0x0460 +#define NGBE_SUB_DEV_ID_EM_RTL_YT8521S_SFP 0x0461 #define NGBE_DEV_ID_EM_WX1860AL_W 0x0100 #define NGBE_DEV_ID_EM_WX1860AL_W_VF 0x0110 @@ -67,15 +69,19 @@ #define NGBE_SUB_DEV_ID_EM_SF400_LY_YT 0x0470 /* Assign excessive id with masks */ -#define NGBE_INTERNAL_MASK 0x000F -#define NGBE_OEM_MASK 0x00F0 +#define NGBE_OEM_MASK 0x00FF #define NGBE_WOL_SUP_MASK 0x4000 #define NGBE_NCSI_SUP_MASK 0x8000 -#define NGBE_INTERNAL_SFP 0x0003 +#define NGBE_M88E1512_SFP 0x0003 #define NGBE_OCP_CARD 0x0040 #define NGBE_LY_M88E1512_SFP 0x0050 +#define NGBE_M88E1512_RJ45 0x0051 +#define NGBE_M88E1512_MIX 0x0052 #define NGBE_YT8521S_SFP 0x0060 +#define NGBE_INTERNAL_YT8521S_SFP 0x0061 +#define NGBE_YT8521S_SFP_GPIO 0x0062 +#define NGBE_INTERNAL_YT8521S_SFP_GPIO 0x0064 #define NGBE_LY_YT8521S_SFP 0x0070 #define NGBE_WOL_SUP 0x4000 #define NGBE_NCSI_SUP 0x8000 diff --git a/drivers/net/ngbe/base/ngbe_hw.c b/drivers/net/ngbe/base/ngbe_hw.c index 72d475ccf9..67e4b4a6fd 100644 --- a/drivers/net/ngbe/base/ngbe_hw.c +++ b/drivers/net/ngbe/base/ngbe_hw.c @@ -124,8 +124,7 @@ ngbe_reset_misc_em(struct ngbe_hw *hw) wr32m(hw, NGBE_GPIE, NGBE_GPIE_MSIX, NGBE_GPIE_MSIX); - if ((hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_M88E1512_SFP || - (hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_YT8521S_SFP) { + if (hw->gpio_ctl) { /* gpio0 is used to power on/off control*/ wr32(hw, NGBE_GPIODIR, NGBE_GPIODIR_DDR(1)); wr32(hw, NGBE_GPIODATA, NGBE_GPIOBIT_0); @@ -1617,19 +1616,21 @@ s32 ngbe_get_link_capabilities_em(struct ngbe_hw *hw, bool *autoneg) { s32 status = 0; - + u16 value = 0; DEBUGFUNC("\n"); hw->mac.autoneg = *autoneg; - switch (hw->sub_device_id) { - case NGBE_SUB_DEV_ID_EM_RTL_SGMII: + if (hw->phy.type == ngbe_phy_rtl) { *speed = NGBE_LINK_SPEED_1GB_FULL | NGBE_LINK_SPEED_100M_FULL | NGBE_LINK_SPEED_10M_FULL; - break; - default: - break; + } + + if (hw->phy.type == ngbe_phy_yt8521s_sfi) { + ngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &value); + if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(1)) + *speed = NGBE_LINK_SPEED_1GB_FULL; } return status; @@ -1815,11 +1816,23 @@ s32 ngbe_set_mac_type(struct ngbe_hw *hw) case NGBE_SUB_DEV_ID_EM_MVL_RGMII: hw->phy.media_type = ngbe_media_type_copper; hw->mac.type = ngbe_mac_em; + hw->mac.link_type = ngbe_link_copper; + break; + case NGBE_SUB_DEV_ID_EM_RTL_YT8521S_SFP: + hw->phy.media_type = ngbe_media_type_copper; + hw->mac.type = ngbe_mac_em; + hw->mac.link_type = ngbe_link_fiber; break; case NGBE_SUB_DEV_ID_EM_MVL_SFP: case NGBE_SUB_DEV_ID_EM_YT8521S_SFP: hw->phy.media_type = ngbe_media_type_fiber; hw->mac.type = ngbe_mac_em; + hw->mac.link_type = ngbe_link_fiber; + break; + case NGBE_SUB_DEV_ID_EM_MVL_MIX: + hw->phy.media_type = ngbe_media_type_unknown; + hw->mac.type = ngbe_mac_em; + hw->mac.link_type = ngbe_link_type_unknown; break; case NGBE_SUB_DEV_ID_EM_VF: hw->phy.media_type = ngbe_media_type_virtual; @@ -1871,7 +1884,7 @@ s32 ngbe_enable_rx_dma(struct ngbe_hw *hw, u32 regval) void ngbe_map_device_id(struct ngbe_hw *hw) { u16 oem = hw->sub_system_id & NGBE_OEM_MASK; - u16 internal = hw->sub_system_id & NGBE_INTERNAL_MASK; + hw->is_pf = true; /* move subsystem_device_id to device_id */ @@ -1905,20 +1918,31 @@ void ngbe_map_device_id(struct ngbe_hw *hw) case NGBE_DEV_ID_EM_WX1860A1: case NGBE_DEV_ID_EM_WX1860A1L: hw->device_id = NGBE_DEV_ID_EM; - if (oem == NGBE_LY_M88E1512_SFP || - internal == NGBE_INTERNAL_SFP) + if (oem == NGBE_M88E1512_SFP || oem == NGBE_LY_M88E1512_SFP) hw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_SFP; - else if (hw->sub_system_id == NGBE_SUB_DEV_ID_EM_M88E1512_RJ45) + else if (oem == NGBE_M88E1512_RJ45 || + (hw->sub_system_id == NGBE_SUB_DEV_ID_EM_M88E1512_RJ45)) hw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_RGMII; + else if (oem == NGBE_M88E1512_MIX) + hw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_MIX; else if (oem == NGBE_YT8521S_SFP || - oem == NGBE_LY_YT8521S_SFP) + oem == NGBE_YT8521S_SFP_GPIO || + oem == NGBE_LY_YT8521S_SFP) hw->sub_device_id = NGBE_SUB_DEV_ID_EM_YT8521S_SFP; + else if (oem == NGBE_INTERNAL_YT8521S_SFP || + oem == NGBE_INTERNAL_YT8521S_SFP_GPIO) + hw->sub_device_id = NGBE_SUB_DEV_ID_EM_RTL_YT8521S_SFP; else hw->sub_device_id = NGBE_SUB_DEV_ID_EM_RTL_SGMII; break; default: break; } + + if (oem == NGBE_LY_M88E1512_SFP || oem == NGBE_YT8521S_SFP_GPIO || + oem == NGBE_INTERNAL_YT8521S_SFP_GPIO || + oem == NGBE_LY_YT8521S_SFP) + hw->gpio_ctl = true; } /** diff --git a/drivers/net/ngbe/base/ngbe_phy.c b/drivers/net/ngbe/base/ngbe_phy.c index 51b0a2ec60..93450b2977 100644 --- a/drivers/net/ngbe/base/ngbe_phy.c +++ b/drivers/net/ngbe/base/ngbe_phy.c @@ -54,8 +54,7 @@ static bool ngbe_probe_phy(struct ngbe_hw *hw, u16 phy_addr) if (ngbe_get_phy_id(hw)) return false; - hw->phy.type = ngbe_get_phy_type_from_id(hw); - if (hw->phy.type == ngbe_phy_unknown) + if (ngbe_get_phy_type_from_id(hw)) return false; return true; @@ -174,37 +173,39 @@ s32 ngbe_get_phy_id(struct ngbe_hw *hw) /** * ngbe_get_phy_type_from_id - Get the phy type - * @phy_id: PHY ID information * **/ -enum ngbe_phy_type ngbe_get_phy_type_from_id(struct ngbe_hw *hw) +s32 ngbe_get_phy_type_from_id(struct ngbe_hw *hw) { - enum ngbe_phy_type phy_type; + s32 status = 0; DEBUGFUNC("ngbe_get_phy_type_from_id"); switch (hw->phy.id) { case NGBE_PHYID_RTL: - phy_type = ngbe_phy_rtl; + hw->phy.type = ngbe_phy_rtl; break; case NGBE_PHYID_MVL: if (hw->phy.media_type == ngbe_media_type_fiber) - phy_type = ngbe_phy_mvl_sfi; + hw->phy.type = ngbe_phy_mvl_sfi; + else if (hw->phy.media_type == ngbe_media_type_copper) + hw->phy.type = ngbe_phy_mvl; else - phy_type = ngbe_phy_mvl; + status = ngbe_check_phy_mode_mvl(hw); break; case NGBE_PHYID_YT: if (hw->phy.media_type == ngbe_media_type_fiber) - phy_type = ngbe_phy_yt8521s_sfi; + hw->phy.type = ngbe_phy_yt8521s_sfi; else - phy_type = ngbe_phy_yt8521s; + hw->phy.type = ngbe_phy_yt8521s; break; default: - phy_type = ngbe_phy_unknown; + hw->phy.type = ngbe_phy_unknown; + status = NGBE_ERR_DEVICE_NOT_SUPPORTED; break; } - return phy_type; + return status; } /** @@ -400,11 +401,13 @@ s32 ngbe_init_phy(struct ngbe_hw *hw) switch (hw->sub_device_id) { case NGBE_SUB_DEV_ID_EM_RTL_SGMII: + case NGBE_SUB_DEV_ID_EM_RTL_YT8521S_SFP: hw->phy.read_reg_unlocked = ngbe_read_phy_reg_rtl; hw->phy.write_reg_unlocked = ngbe_write_phy_reg_rtl; break; case NGBE_SUB_DEV_ID_EM_MVL_RGMII: case NGBE_SUB_DEV_ID_EM_MVL_SFP: + case NGBE_SUB_DEV_ID_EM_MVL_MIX: hw->phy.read_reg_unlocked = ngbe_read_phy_reg_mvl; hw->phy.write_reg_unlocked = ngbe_write_phy_reg_mvl; break; diff --git a/drivers/net/ngbe/base/ngbe_phy.h b/drivers/net/ngbe/base/ngbe_phy.h index f262ff3350..e93d6a4c4a 100644 --- a/drivers/net/ngbe/base/ngbe_phy.h +++ b/drivers/net/ngbe/base/ngbe_phy.h @@ -48,7 +48,7 @@ typedef struct mdi_reg mdi_reg_t; s32 ngbe_mdi_map_register(mdi_reg_t *reg, mdi_reg_22_t *reg22); bool ngbe_validate_phy_addr(struct ngbe_hw *hw, u32 phy_addr); -enum ngbe_phy_type ngbe_get_phy_type_from_id(struct ngbe_hw *hw); +s32 ngbe_get_phy_type_from_id(struct ngbe_hw *hw); s32 ngbe_get_phy_id(struct ngbe_hw *hw); s32 ngbe_identify_phy(struct ngbe_hw *hw); s32 ngbe_reset_phy(struct ngbe_hw *hw); diff --git a/drivers/net/ngbe/base/ngbe_phy_mvl.c b/drivers/net/ngbe/base/ngbe_phy_mvl.c index 2eb351d258..8a4df90a42 100644 --- a/drivers/net/ngbe/base/ngbe_phy_mvl.c +++ b/drivers/net/ngbe/base/ngbe_phy_mvl.c @@ -48,6 +48,31 @@ s32 ngbe_write_phy_reg_mvl(struct ngbe_hw *hw, return 0; } +s32 ngbe_check_phy_mode_mvl(struct ngbe_hw *hw) +{ + u16 value = 0; + + /* select page 18 reg 20 */ + ngbe_write_phy_reg_mdi(hw, MVL_PAGE_SEL, 0, 18); + ngbe_read_phy_reg_mdi(hw, MVL_GEN_CTL, 0, &value); + if (MVL_GEN_CTL_MODE(value) == MVL_GEN_CTL_MODE_COPPER) { + /* mode select to RGMII-to-copper */ + hw->phy.type = ngbe_phy_mvl; + hw->phy.media_type = ngbe_media_type_copper; + hw->mac.link_type = ngbe_link_copper; + } else if (MVL_GEN_CTL_MODE(value) == MVL_GEN_CTL_MODE_FIBER) { + /* mode select to RGMII-to-sfi */ + hw->phy.type = ngbe_phy_mvl_sfi; + hw->phy.media_type = ngbe_media_type_fiber; + hw->mac.link_type = ngbe_link_fiber; + } else { + DEBUGOUT("marvell 88E1512 mode %x is not supported.\n", value); + return NGBE_ERR_DEVICE_NOT_SUPPORTED; + } + + return 0; +} + s32 ngbe_init_phy_mvl(struct ngbe_hw *hw) { s32 ret_val = 0; @@ -125,6 +150,29 @@ s32 ngbe_setup_phy_link_mvl(struct ngbe_hw *hw, u32 speed, hw->phy.autoneg_advertised = 0; if (hw->phy.type == ngbe_phy_mvl) { + if (!hw->mac.autoneg) { + switch (speed) { + case NGBE_LINK_SPEED_1GB_FULL: + value = MVL_CTRL_SPEED_SELECT1; + break; + case NGBE_LINK_SPEED_100M_FULL: + value = MVL_CTRL_SPEED_SELECT0; + break; + case NGBE_LINK_SPEED_10M_FULL: + value = 0; + break; + default: + value = MVL_CTRL_SPEED_SELECT0 | + MVL_CTRL_SPEED_SELECT1; + DEBUGOUT("unknown speed = 0x%x.\n", speed); + break; + } + /* duplex full */ + value |= MVL_CTRL_DUPLEX | MVL_CTRL_RESET; + ngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value); + + goto skip_an; + } if (speed & NGBE_LINK_SPEED_1GB_FULL) { value_r9 |= MVL_PHY_1000BASET_FULL; hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL; @@ -162,7 +210,12 @@ s32 ngbe_setup_phy_link_mvl(struct ngbe_hw *hw, u32 speed, hw->phy.write_reg(hw, MVL_ANA, 0, value); } - value = MVL_CTRL_RESTART_AN | MVL_CTRL_ANE; + value = MVL_CTRL_RESTART_AN | MVL_CTRL_ANE | MVL_CTRL_RESET; + ngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value); + +skip_an: + ngbe_read_phy_reg_mdi(hw, MVL_CTRL, 0, &value); + value |= MVL_CTRL_PWDN; ngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value); hw->phy.read_reg(hw, MVL_INTR, 0, &value); diff --git a/drivers/net/ngbe/base/ngbe_phy_mvl.h b/drivers/net/ngbe/base/ngbe_phy_mvl.h index a2b5202d4b..8aee236390 100644 --- a/drivers/net/ngbe/base/ngbe_phy_mvl.h +++ b/drivers/net/ngbe/base/ngbe_phy_mvl.h @@ -12,8 +12,12 @@ /* Page 0 for Copper, Page 1 for Fiber */ #define MVL_CTRL 0x0 #define MVL_CTRL_RESET MS16(15, 0x1) +#define MVL_CTRL_SPEED_SELECT0 MS16(13, 0x1) #define MVL_CTRL_ANE MS16(12, 0x1) +#define MVL_CTRL_PWDN MS16(11, 0x1) #define MVL_CTRL_RESTART_AN MS16(9, 0x1) +#define MVL_CTRL_DUPLEX MS16(8, 0x1) +#define MVL_CTRL_SPEED_SELECT1 MS16(6, 0x1) #define MVL_ANA 0x4 /* copper */ #define MVL_CANA_ASM_PAUSE MS16(11, 0x1) @@ -86,6 +90,7 @@ s32 ngbe_read_phy_reg_mvl(struct ngbe_hw *hw, u32 reg_addr, u32 device_type, u16 *phy_data); s32 ngbe_write_phy_reg_mvl(struct ngbe_hw *hw, u32 reg_addr, u32 device_type, u16 phy_data); +s32 ngbe_check_phy_mode_mvl(struct ngbe_hw *hw); s32 ngbe_init_phy_mvl(struct ngbe_hw *hw); s32 ngbe_reset_phy_mvl(struct ngbe_hw *hw); diff --git a/drivers/net/ngbe/base/ngbe_phy_yt.c b/drivers/net/ngbe/base/ngbe_phy_yt.c index 8db0f9ce48..2d184a1c30 100644 --- a/drivers/net/ngbe/base/ngbe_phy_yt.c +++ b/drivers/net/ngbe/base/ngbe_phy_yt.c @@ -104,23 +104,22 @@ s32 ngbe_init_phy_yt(struct ngbe_hw *hw) DEBUGFUNC("ngbe_init_phy_yt"); - if (hw->phy.type != ngbe_phy_yt8521s_sfi) - return 0; - - /* select sds area register */ + /* close sds area register */ ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, 0, 0); /* enable interrupts */ - ngbe_write_phy_reg_mdi(hw, YT_INTR, 0, YT_INTR_ENA_MASK); - - /* select fiber_to_rgmii first in multiplex */ - ngbe_read_phy_reg_ext_yt(hw, YT_MISC, 0, &value); - value |= YT_MISC_FIBER_PRIO; - ngbe_write_phy_reg_ext_yt(hw, YT_MISC, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_INTR, 0, + YT_INTR_ENA_MASK | YT_SDS_INTR_ENA_MASK); + /* power down in fiber mode */ hw->phy.read_reg(hw, YT_BCR, 0, &value); value |= YT_BCR_PWDN; hw->phy.write_reg(hw, YT_BCR, 0, value); + /* power down in UTP mode */ + ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value); + value |= YT_BCR_PWDN; + ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value); + return 0; } @@ -136,15 +135,44 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, hw->phy.autoneg_advertised = 0; - if (hw->phy.type == ngbe_phy_yt8521s) { + /* check chip_mode first */ + ngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &value); + if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(0)) { + /* UTP to rgmii */ + if (!hw->mac.autoneg) { + switch (speed) { + case NGBE_LINK_SPEED_1GB_FULL: + value = YT_BCR_SPEED_SELECT1; + break; + case NGBE_LINK_SPEED_100M_FULL: + value = YT_BCR_SPEED_SELECT0; + break; + case NGBE_LINK_SPEED_10M_FULL: + value = 0; + break; + default: + value = YT_BCR_SPEED_SELECT0 | + YT_BCR_SPEED_SELECT1; + DEBUGOUT("unknown speed = 0x%x.\n", + speed); + break; + } + /* duplex full */ + value |= YT_BCR_DUPLEX | YT_BCR_RESET; + hw->phy.write_reg(hw, YT_BCR, 0, value); + + goto skip_an; + } + /*disable 100/10base-T Self-negotiation ability*/ hw->phy.read_reg(hw, YT_ANA, 0, &value); - value &= ~(YT_ANA_100BASET_FULL | YT_ANA_10BASET_FULL); + value &= ~(YT_ANA_100BASET_FULL | YT_ANA_100BASET_HALF | + YT_ANA_10BASET_FULL | YT_ANA_10BASET_HALF); hw->phy.write_reg(hw, YT_ANA, 0, value); /*disable 1000base-T Self-negotiation ability*/ hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value); - value &= ~YT_MS_1000BASET_FULL; + value &= ~(YT_MS_1000BASET_FULL | YT_MS_1000BASET_HALF); hw->phy.write_reg(hw, YT_MS_CTRL, 0, value); if (speed & NGBE_LINK_SPEED_1GB_FULL) { @@ -172,9 +200,15 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, /* software reset to make the above configuration take effect*/ hw->phy.read_reg(hw, YT_BCR, 0, &value); - value |= YT_BCR_RESET; + value |= YT_BCR_RESET | YT_BCR_ANE | YT_BCR_RESTART_AN; hw->phy.write_reg(hw, YT_BCR, 0, value); - } else { +skip_an: + /* power on in UTP mode */ + ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value); + value &= ~YT_BCR_PWDN; + ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value); + } else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(1)) { + /* fiber to rgmii */ hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL; /* RGMII_Config1 : Config rx and tx training delay */ @@ -190,6 +224,88 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, /* software reset */ ngbe_write_phy_reg_sds_ext_yt(hw, 0x0, 0, 0x9140); + /* power on phy */ + hw->phy.read_reg(hw, YT_BCR, 0, &value); + value &= ~YT_BCR_PWDN; + hw->phy.write_reg(hw, YT_BCR, 0, value); + } else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(2)) { + /* power on in UTP mode */ + ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value); + value &= ~YT_BCR_PWDN; + ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value); + /* power down in fiber mode */ + hw->phy.read_reg(hw, YT_BCR, 0, &value); + value &= ~YT_BCR_PWDN; + hw->phy.write_reg(hw, YT_BCR, 0, value); + + hw->phy.read_reg(hw, YT_SPST, 0, &value); + if (value & YT_SPST_LINK) { + /* fiber up */ + hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL; + } else { + /* utp up */ + /*disable 100/10base-T Self-negotiation ability*/ + hw->phy.read_reg(hw, YT_ANA, 0, &value); + value &= ~(YT_ANA_100BASET_FULL | YT_ANA_100BASET_HALF | + YT_ANA_10BASET_FULL | YT_ANA_10BASET_HALF); + hw->phy.write_reg(hw, YT_ANA, 0, value); + + /*disable 1000base-T Self-negotiation ability*/ + hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value); + value &= ~(YT_MS_1000BASET_FULL | YT_MS_1000BASET_HALF); + hw->phy.write_reg(hw, YT_MS_CTRL, 0, value); + + if (speed & NGBE_LINK_SPEED_1GB_FULL) { + hw->phy.autoneg_advertised |= + NGBE_LINK_SPEED_1GB_FULL; + value_r9 |= YT_MS_1000BASET_FULL; + } + if (speed & NGBE_LINK_SPEED_100M_FULL) { + hw->phy.autoneg_advertised |= + NGBE_LINK_SPEED_100M_FULL; + value_r4 |= YT_ANA_100BASET_FULL; + } + if (speed & NGBE_LINK_SPEED_10M_FULL) { + hw->phy.autoneg_advertised |= + NGBE_LINK_SPEED_10M_FULL; + value_r4 |= YT_ANA_10BASET_FULL; + } + + /* enable 1000base-T Self-negotiation ability */ + hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value); + value |= value_r9; + hw->phy.write_reg(hw, YT_MS_CTRL, 0, value); + + /* enable 100/10base-T Self-negotiation ability */ + hw->phy.read_reg(hw, YT_ANA, 0, &value); + value |= value_r4; + hw->phy.write_reg(hw, YT_ANA, 0, value); + + /* software reset to make the above configuration + * take effect + */ + hw->phy.read_reg(hw, YT_BCR, 0, &value); + value |= YT_BCR_RESET; + hw->phy.write_reg(hw, YT_BCR, 0, value); + } + } else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(4)) { + hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL; + + ngbe_read_phy_reg_ext_yt(hw, YT_RGMII_CONF1, 0, &value); + value |= YT_RGMII_CONF1_MODE; + ngbe_write_phy_reg_ext_yt(hw, YT_RGMII_CONF1, 0, value); + + ngbe_read_phy_reg_ext_yt(hw, YT_RGMII_CONF2, 0, &value); + value &= ~(YT_RGMII_CONF2_SPEED_MASK | YT_RGMII_CONF2_DUPLEX | + YT_RGMII_CONF2_LINKUP); + value |= YT_RGMII_CONF2_SPEED(2) | YT_RGMII_CONF2_DUPLEX | + YT_RGMII_CONF2_LINKUP; + ngbe_write_phy_reg_ext_yt(hw, YT_RGMII_CONF2, 0, value); + + ngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &value); + value &= ~YT_SMI_PHY_SW_RST; + ngbe_write_phy_reg_ext_yt(hw, YT_CHIP, 0, value); + /* power on phy */ hw->phy.read_reg(hw, YT_BCR, 0, &value); value &= ~YT_BCR_PWDN; @@ -214,16 +330,34 @@ s32 ngbe_reset_phy_yt(struct ngbe_hw *hw) hw->phy.type != ngbe_phy_yt8521s_sfi) return NGBE_ERR_PHY_TYPE; - status = hw->phy.read_reg(hw, YT_BCR, 0, &ctrl); - /* sds software reset */ - ctrl |= YT_BCR_RESET; - status = hw->phy.write_reg(hw, YT_BCR, 0, ctrl); - - for (i = 0; i < YT_PHY_RST_WAIT_PERIOD; i++) { + /* check chip_mode first */ + ngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &ctrl); + if (ctrl & YT_CHIP_MODE_MASK) { + /* fiber to rgmii */ status = hw->phy.read_reg(hw, YT_BCR, 0, &ctrl); - if (!(ctrl & YT_BCR_RESET)) - break; - msleep(1); + /* sds software reset */ + ctrl |= YT_BCR_RESET; + status = hw->phy.write_reg(hw, YT_BCR, 0, ctrl); + + for (i = 0; i < YT_PHY_RST_WAIT_PERIOD; i++) { + status = hw->phy.read_reg(hw, YT_BCR, 0, &ctrl); + if (!(ctrl & YT_BCR_RESET)) + break; + msleep(1); + } + } else { + /* UTP to rgmii */ + status = ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &ctrl); + /* sds software reset */ + ctrl |= YT_BCR_RESET; + status = ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, ctrl); + + for (i = 0; i < YT_PHY_RST_WAIT_PERIOD; i++) { + status = ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &ctrl); + if (!(ctrl & YT_BCR_RESET)) + break; + msleep(1); + } } if (i == YT_PHY_RST_WAIT_PERIOD) { diff --git a/drivers/net/ngbe/base/ngbe_phy_yt.h b/drivers/net/ngbe/base/ngbe_phy_yt.h index e729e0c854..c8763a90df 100644 --- a/drivers/net/ngbe/base/ngbe_phy_yt.h +++ b/drivers/net/ngbe/base/ngbe_phy_yt.h @@ -11,26 +11,41 @@ /* Common EXT */ #define YT_SMI_PHY 0xA000 +#define YT_SMI_PHY_SW_RST MS16(15, 0x1) #define YT_SMI_PHY_SDS MS16(1, 0x1) /* 0 for UTP */ #define YT_CHIP 0xA001 #define YT_CHIP_SW_RST MS16(15, 0x1) #define YT_CHIP_SW_LDO_EN MS16(6, 0x1) +#define YT_CHIP_MODE_MASK MS16(0, 0x7) #define YT_CHIP_MODE_SEL(v) LS16(v, 0, 0x7) #define YT_RGMII_CONF1 0xA003 +#define YT_RGMII_CONF1_MODE MS16(15, 0x1) #define YT_RGMII_CONF1_RXDELAY MS16(10, 0xF) #define YT_RGMII_CONF1_TXDELAY_FE MS16(4, 0xF) #define YT_RGMII_CONF1_TXDELAY MS16(0, 0x1) +#define YT_RGMII_CONF2 0xA004 +#define YT_RGMII_CONF2_SPEED_MASK MS16(6, 0x3) +#define YT_RGMII_CONF2_SPEED(v) LS16(v, 6, 0x3) +#define YT_RGMII_CONF2_DUPLEX MS16(5, 0x1) +#define YT_RGMII_CONF2_LINKUP MS16(4, 0x1) #define YT_MISC 0xA006 #define YT_MISC_FIBER_PRIO MS16(8, 0x1) /* 0 for UTP */ /* MII common registers in UTP and SDS */ #define YT_BCR 0x0 #define YT_BCR_RESET MS16(15, 0x1) +#define YT_BCR_SPEED_SELECT0 MS16(13, 0x1) +#define YT_BCR_ANE MS16(12, 0x1) #define YT_BCR_PWDN MS16(11, 0x1) +#define YT_BCR_RESTART_AN MS16(9, 0x1) +#define YT_BCR_DUPLEX MS16(8, 0x1) +#define YT_BCR_SPEED_SELECT1 MS16(6, 0x1) #define YT_ANA 0x4 /* copper */ #define YT_ANA_100BASET_FULL MS16(8, 0x1) +#define YT_ANA_100BASET_HALF MS16(7, 0x1) #define YT_ANA_10BASET_FULL MS16(6, 0x1) +#define YT_ANA_10BASET_HALF MS16(5, 0x1) /* fiber */ #define YT_FANA_PAUSE_MASK MS16(7, 0x3) @@ -41,6 +56,7 @@ #define YT_MS_CTRL 0x9 #define YT_MS_1000BASET_FULL MS16(9, 0x1) +#define YT_MS_1000BASET_HALF MS16(8, 0x1) #define YT_SPST 0x11 #define YT_SPST_SPEED_MASK MS16(14, 0x3) #define YT_SPST_SPEED_1000M LS16(2, 14, 0x3) @@ -50,7 +66,8 @@ /* UTP only */ #define YT_INTR 0x12 -#define YT_INTR_ENA_MASK MS16(2, 0x3) +#define YT_INTR_ENA_MASK MS16(10, 0x3) +#define YT_SDS_INTR_ENA_MASK MS16(2, 0x3) #define YT_INTR_STATUS 0x13 s32 ngbe_read_phy_reg_yt(struct ngbe_hw *hw, u32 reg_addr, u32 device_type, diff --git a/drivers/net/ngbe/base/ngbe_type.h b/drivers/net/ngbe/base/ngbe_type.h index 4c995e7397..cb8d65ff27 100644 --- a/drivers/net/ngbe/base/ngbe_type.h +++ b/drivers/net/ngbe/base/ngbe_type.h @@ -44,6 +44,12 @@ enum ngbe_eeprom_type { ngbe_eeprom_none /* No NVM support */ }; +enum ngbe_link_type { + ngbe_link_type_unknown = 0, + ngbe_link_fiber, + ngbe_link_copper +}; + enum ngbe_mac_type { ngbe_mac_unknown = 0, ngbe_mac_em, @@ -312,6 +318,7 @@ struct ngbe_mac_info { s32 (*check_overtemp)(struct ngbe_hw *hw); enum ngbe_mac_type type; + enum ngbe_link_type link_type; u8 addr[ETH_ADDR_LEN]; u8 perm_addr[ETH_ADDR_LEN]; #define NGBE_MAX_MTA 128 @@ -422,6 +429,7 @@ struct ngbe_hw { u32 q_tx_regs[8 * 4]; bool offset_loaded; bool is_pf; + bool gpio_ctl; struct { u64 rx_qp_packets; u64 tx_qp_packets; diff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c index cc530fdced..9f42c26f9b 100644 --- a/drivers/net/ngbe/ngbe_ethdev.c +++ b/drivers/net/ngbe/ngbe_ethdev.c @@ -1097,8 +1097,7 @@ ngbe_dev_start(struct rte_eth_dev *dev) /* resume enabled intr since HW reset */ ngbe_enable_intr(dev); - if ((hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_M88E1512_SFP || - (hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_YT8521S_SFP) { + if (hw->gpio_ctl) { /* gpio0 is used to power on/off control*/ wr32(hw, NGBE_GPIODATA, 0); } @@ -1141,8 +1140,7 @@ ngbe_dev_stop(struct rte_eth_dev *dev) rte_eal_alarm_cancel(ngbe_dev_setup_link_alarm_handler, dev); - if ((hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_M88E1512_SFP || - (hw->sub_system_id & NGBE_OEM_MASK) == NGBE_LY_YT8521S_SFP) { + if (hw->gpio_ctl) { /* gpio0 is used to power on/off control*/ wr32(hw, NGBE_GPIODATA, NGBE_GPIOBIT_0); } From patchwork Wed Feb 9 10:42:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 107116 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 154BBA04A6; Wed, 9 Feb 2022 11:36:29 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 486E9411FB; Wed, 9 Feb 2022 11:35:56 +0100 (CET) Received: from smtpbgsg2.qq.com (smtpbgsg2.qq.com [54.254.200.128]) by mails.dpdk.org (Postfix) with ESMTP id 5926D411FB for ; Wed, 9 Feb 2022 11:35:54 +0100 (CET) X-QQ-mid: bizesmtp37t1644402947tbi7asox Received: from wxdbg.localdomain.com (unknown [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 09 Feb 2022 18:35:46 +0800 (CST) X-QQ-SSF: 01400000002000F0L000B00A0000000 X-QQ-FEAT: TskX/GkkryBWuQY0AWSERXU/cQeXfHXY3Hx48VCVyjNW56CeSm07zKAY0nGZN e9U9KYZMr26og1Y9dm3BYPYjHxDVEJ6rOFRvN+03f7BppLJ84V2BSqpSe6HGU1xOpX4N8nd pb9+f+YJ91ysLBbGhmg2IHxOtbzNEZjpfBCpFu734PYyxPmce4CxjdUi1FZgPewnKJd4Bhm 34pRzX/t2mNThr2GvokXxCpvH9UpBqgAJv6kLAYEr1tZA8RYlSBWcsIDeFevlbifj992867 jDve5QOuU8v7HOBQpwUI3u4wXg7scLJjh4W/YQglrS3IP8XHEe25s4bsybq2E690ypfE5bX nQNKm3jazOFNzpHa3CFn9HZ4ZLtM2gPW3eIvgM2dV/KuqnaUs0= X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu Subject: [PATCH v2 07/12] net/ngbe: add LED OEM support Date: Wed, 9 Feb 2022 18:42:08 +0800 Message-Id: <20220209104213.602728-8-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220209104213.602728-1-jiawenwu@trustnetic.com> References: <20220209104213.602728-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign1 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Support to get OEM customized LED configuration information from firmware. And driver needs to adjust the process of PHY setup link, based on this LED configuration. Signed-off-by: Jiawen Wu --- doc/guides/rel_notes/release_22_03.rst | 1 + drivers/net/ngbe/base/ngbe_dummy.h | 5 +++ drivers/net/ngbe/base/ngbe_hw.c | 1 + drivers/net/ngbe/base/ngbe_mng.c | 49 ++++++++++++++++++++++++++ drivers/net/ngbe/base/ngbe_mng.h | 3 ++ drivers/net/ngbe/base/ngbe_phy_mvl.c | 26 ++++++++------ drivers/net/ngbe/base/ngbe_phy_rtl.c | 34 +++++++++++++----- drivers/net/ngbe/base/ngbe_type.h | 2 ++ drivers/net/ngbe/ngbe_ethdev.c | 7 ++++ 9 files changed, 109 insertions(+), 19 deletions(-) diff --git a/doc/guides/rel_notes/release_22_03.rst b/doc/guides/rel_notes/release_22_03.rst index 233c34a2d0..46bc286934 100644 --- a/doc/guides/rel_notes/release_22_03.rst +++ b/doc/guides/rel_notes/release_22_03.rst @@ -75,6 +75,7 @@ New Features - M88E1512 PHY connects to RJ45 - M88E1512 PHY connects to RGMII combo - YT8521S PHY connects to SFP + * Added LED OEM support. * **Added an API to retrieve event port id of ethdev Rx adapter.** diff --git a/drivers/net/ngbe/base/ngbe_dummy.h b/drivers/net/ngbe/base/ngbe_dummy.h index d74c9f7b54..836206e325 100644 --- a/drivers/net/ngbe/base/ngbe_dummy.h +++ b/drivers/net/ngbe/base/ngbe_dummy.h @@ -251,6 +251,10 @@ static inline s32 ngbe_set_phy_pause_adv_dummy(struct ngbe_hw *TUP0, u16 TUP1) { return NGBE_ERR_OPS_DUMMY; } +static inline s32 ngbe_phy_led_oem_chk_dummy(struct ngbe_hw *TUP0, u32 *TUP1) +{ + return NGBE_ERR_OPS_DUMMY; +} /* struct ngbe_mbx_operations */ static inline void ngbe_mbx_init_params_dummy(struct ngbe_hw *TUP0) @@ -332,6 +336,7 @@ static inline void ngbe_init_ops_dummy(struct ngbe_hw *hw) hw->phy.get_adv_pause = ngbe_get_phy_advertised_pause_dummy; hw->phy.get_lp_adv_pause = ngbe_get_phy_lp_advertised_pause_dummy; hw->phy.set_pause_adv = ngbe_set_phy_pause_adv_dummy; + hw->phy.led_oem_chk = ngbe_phy_led_oem_chk_dummy; hw->mbx.init_params = ngbe_mbx_init_params_dummy; hw->mbx.read = ngbe_mbx_read_dummy; hw->mbx.write = ngbe_mbx_write_dummy; diff --git a/drivers/net/ngbe/base/ngbe_hw.c b/drivers/net/ngbe/base/ngbe_hw.c index 67e4b4a6fd..931fe8c8cb 100644 --- a/drivers/net/ngbe/base/ngbe_hw.c +++ b/drivers/net/ngbe/base/ngbe_hw.c @@ -1972,6 +1972,7 @@ s32 ngbe_init_ops_pf(struct ngbe_hw *hw) phy->read_reg_unlocked = ngbe_read_phy_reg_mdi; phy->write_reg_unlocked = ngbe_write_phy_reg_mdi; phy->reset_hw = ngbe_reset_phy; + phy->led_oem_chk = ngbe_phy_led_oem_chk; /* MAC */ mac->init_hw = ngbe_init_hw; diff --git a/drivers/net/ngbe/base/ngbe_mng.c b/drivers/net/ngbe/base/ngbe_mng.c index 68e06e2c24..c6f4dc2e0b 100644 --- a/drivers/net/ngbe/base/ngbe_mng.c +++ b/drivers/net/ngbe/base/ngbe_mng.c @@ -338,3 +338,52 @@ s32 ngbe_hic_check_cap(struct ngbe_hw *hw) return err; } + +s32 ngbe_phy_led_oem_chk(struct ngbe_hw *hw, u32 *data) +{ + struct ngbe_hic_read_shadow_ram command; + s32 err; + int i; + + DEBUGFUNC("\n"); + + command.hdr.req.cmd = FW_PHY_LED_CONF; + command.hdr.req.buf_lenh = 0; + command.hdr.req.buf_lenl = 0; + command.hdr.req.checksum = FW_DEFAULT_CHECKSUM; + + /* convert offset from words to bytes */ + command.address = 0; + /* one word */ + command.length = 0; + + for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { + err = ngbe_host_interface_command(hw, (u32 *)&command, + sizeof(command), + NGBE_HI_COMMAND_TIMEOUT, true); + if (err) + continue; + + command.hdr.rsp.ret_status &= 0x1F; + if (command.hdr.rsp.ret_status != + FW_CEM_RESP_STATUS_SUCCESS) + err = NGBE_ERR_HOST_INTERFACE_COMMAND; + + break; + } + + if (err) + return err; + + if (command.address == FW_CHECKSUM_CAP_ST_PASS) { + *data = ((u32 *)&command)[2]; + err = 0; + } else if (command.address == FW_CHECKSUM_CAP_ST_FAIL) { + *data = FW_CHECKSUM_CAP_ST_FAIL; + err = -1; + } else { + err = NGBE_ERR_EEPROM_CHECKSUM; + } + + return err; +} diff --git a/drivers/net/ngbe/base/ngbe_mng.h b/drivers/net/ngbe/base/ngbe_mng.h index 321338a051..36257d6e5e 100644 --- a/drivers/net/ngbe/base/ngbe_mng.h +++ b/drivers/net/ngbe/base/ngbe_mng.h @@ -26,6 +26,7 @@ #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */ #define FW_NVM_DATA_OFFSET 3 #define FW_EEPROM_CHECK_STATUS 0xE9 +#define FW_PHY_LED_CONF 0xF1 #define FW_CHECKSUM_CAP_ST_PASS 0x80658383 #define FW_CHECKSUM_CAP_ST_FAIL 0x70657376 @@ -101,4 +102,6 @@ s32 ngbe_hic_pcie_read(struct ngbe_hw *hw, u16 addr, u32 *buf, int len); s32 ngbe_hic_pcie_write(struct ngbe_hw *hw, u16 addr, u32 *buf, int len); s32 ngbe_hic_check_cap(struct ngbe_hw *hw); +s32 ngbe_phy_led_oem_chk(struct ngbe_hw *hw, u32 *data); + #endif /* _NGBE_MNG_H_ */ diff --git a/drivers/net/ngbe/base/ngbe_phy_mvl.c b/drivers/net/ngbe/base/ngbe_phy_mvl.c index 8a4df90a42..01cb6b9bb3 100644 --- a/drivers/net/ngbe/base/ngbe_phy_mvl.c +++ b/drivers/net/ngbe/base/ngbe_phy_mvl.c @@ -123,16 +123,9 @@ s32 ngbe_init_phy_mvl(struct ngbe_hw *hw) value = MVL_INTR_EN_ANC | MVL_INTR_EN_LSC; hw->phy.write_reg(hw, MVL_INTR_EN, 0, value); - /* LED control */ - ngbe_write_phy_reg_mdi(hw, MVL_PAGE_SEL, 0, 3); - ngbe_read_phy_reg_mdi(hw, MVL_LEDFCR, 0, &value); - value &= ~(MVL_LEDFCR_CTL0 | MVL_LEDFCR_CTL1); - value |= MVL_LEDFCR_CTL0_CONF | MVL_LEDFCR_CTL1_CONF; - ngbe_write_phy_reg_mdi(hw, MVL_LEDFCR, 0, value); - ngbe_read_phy_reg_mdi(hw, MVL_LEDPCR, 0, &value); - value &= ~(MVL_LEDPCR_CTL0 | MVL_LEDPCR_CTL1); - value |= MVL_LEDPCR_CTL0_CONF | MVL_LEDPCR_CTL1_CONF; - ngbe_write_phy_reg_mdi(hw, MVL_LEDPCR, 0, value); + ngbe_read_phy_reg_mdi(hw, MVL_CTRL, 0, &value); + value |= MVL_CTRL_PWDN; + ngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value); return ret_val; } @@ -147,6 +140,19 @@ s32 ngbe_setup_phy_link_mvl(struct ngbe_hw *hw, u32 speed, DEBUGFUNC("ngbe_setup_phy_link_mvl"); UNREFERENCED_PARAMETER(autoneg_wait_to_complete); + if (hw->led_conf == 0xFFFF) { + /* LED control */ + ngbe_write_phy_reg_mdi(hw, MVL_PAGE_SEL, 0, 3); + ngbe_read_phy_reg_mdi(hw, MVL_LEDFCR, 0, &value); + value &= ~(MVL_LEDFCR_CTL0 | MVL_LEDFCR_CTL1); + value |= MVL_LEDFCR_CTL0_CONF | MVL_LEDFCR_CTL1_CONF; + ngbe_write_phy_reg_mdi(hw, MVL_LEDFCR, 0, value); + ngbe_read_phy_reg_mdi(hw, MVL_LEDPCR, 0, &value); + value &= ~(MVL_LEDPCR_CTL0 | MVL_LEDPCR_CTL1); + value |= MVL_LEDPCR_CTL0_CONF | MVL_LEDPCR_CTL1_CONF; + ngbe_write_phy_reg_mdi(hw, MVL_LEDPCR, 0, value); + } + hw->phy.autoneg_advertised = 0; if (hw->phy.type == ngbe_phy_mvl) { diff --git a/drivers/net/ngbe/base/ngbe_phy_rtl.c b/drivers/net/ngbe/base/ngbe_phy_rtl.c index c59efe3153..f49d829dff 100644 --- a/drivers/net/ngbe/base/ngbe_phy_rtl.c +++ b/drivers/net/ngbe/base/ngbe_phy_rtl.c @@ -36,6 +36,30 @@ s32 ngbe_write_phy_reg_rtl(struct ngbe_hw *hw, return 0; } +static void ngbe_phy_led_ctrl_rtl(struct ngbe_hw *hw) +{ + u16 value = 0; + + if (hw->led_conf != 0xFFFF) + value = hw->led_conf & 0xFFFF; + else + value = 0x205B; + + hw->phy.write_reg(hw, RTL_LCR, 0xd04, value); + hw->phy.write_reg(hw, RTL_EEELCR, 0xd04, 0); + + hw->phy.read_reg(hw, RTL_LPCR, 0xd04, &value); + if (hw->led_conf != 0xFFFF) { + value &= ~0x73; + value |= hw->led_conf >> 16; + } else { + value &= 0xFFFC; + /*act led blinking mode set to 60ms*/ + value |= 0x2; + } + hw->phy.write_reg(hw, RTL_LPCR, 0xd04, value); +} + s32 ngbe_init_phy_rtl(struct ngbe_hw *hw) { int i; @@ -219,15 +243,7 @@ s32 ngbe_setup_phy_link_rtl(struct ngbe_hw *hw, hw->phy.write_reg(hw, RTL_BMCR, RTL_DEV_ZERO, autoneg_reg); skip_an: - autoneg_reg = 0x205B; - hw->phy.write_reg(hw, RTL_LCR, 0xd04, autoneg_reg); - hw->phy.write_reg(hw, RTL_EEELCR, 0xd04, 0); - - hw->phy.read_reg(hw, RTL_LPCR, 0xd04, &autoneg_reg); - autoneg_reg = autoneg_reg & 0xFFFC; - /* act led blinking mode set to 60ms */ - autoneg_reg |= 0x2; - hw->phy.write_reg(hw, RTL_LPCR, 0xd04, autoneg_reg); + ngbe_phy_led_ctrl_rtl(hw); return 0; } diff --git a/drivers/net/ngbe/base/ngbe_type.h b/drivers/net/ngbe/base/ngbe_type.h index cb8d65ff27..666562bf22 100644 --- a/drivers/net/ngbe/base/ngbe_type.h +++ b/drivers/net/ngbe/base/ngbe_type.h @@ -355,6 +355,7 @@ struct ngbe_phy_info { bool autoneg_wait_to_complete); s32 (*check_link)(struct ngbe_hw *hw, u32 *speed, bool *link_up); s32 (*set_phy_power)(struct ngbe_hw *hw, bool on); + s32 (*led_oem_chk)(struct ngbe_hw *hw, u32 *data); s32 (*get_adv_pause)(struct ngbe_hw *hw, u8 *pause_bit); s32 (*get_lp_adv_pause)(struct ngbe_hw *hw, u8 *pause_bit); s32 (*set_pause_adv)(struct ngbe_hw *hw, u16 pause_bit); @@ -430,6 +431,7 @@ struct ngbe_hw { bool offset_loaded; bool is_pf; bool gpio_ctl; + u32 led_conf; struct { u64 rx_qp_packets; u64 tx_qp_packets; diff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c index 9f42c26f9b..4a2a9dde10 100644 --- a/drivers/net/ngbe/ngbe_ethdev.c +++ b/drivers/net/ngbe/ngbe_ethdev.c @@ -314,6 +314,7 @@ eth_ngbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) struct rte_intr_handle *intr_handle = pci_dev->intr_handle; const struct rte_memzone *mz; uint32_t ctrl_ext; + u32 led_conf = 0; int err, ret; PMD_INIT_FUNC_TRACE(); @@ -401,6 +402,12 @@ eth_ngbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) return -EIO; } + err = hw->phy.led_oem_chk(hw, &led_conf); + if (err == 0) + hw->led_conf = led_conf; + else + hw->led_conf = 0xFFFF; + err = hw->mac.init_hw(hw); if (err != 0) { PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", err); From patchwork Wed Feb 9 10:42:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 107118 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5F6CEA04A6; Wed, 9 Feb 2022 11:36:40 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3A9DC41C28; Wed, 9 Feb 2022 11:35:58 +0100 (CET) Received: from smtpbg151.qq.com (smtpbg151.qq.com [18.169.211.239]) by mails.dpdk.org (Postfix) with ESMTP id 454504122E for ; Wed, 9 Feb 2022 11:35:57 +0100 (CET) X-QQ-mid: bizesmtp37t1644402949t7z6oslb Received: from wxdbg.localdomain.com (unknown [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 09 Feb 2022 18:35:48 +0800 (CST) X-QQ-SSF: 01400000002000F0L000B00A0000000 X-QQ-FEAT: TskX/GkkryB209XEV7x65DmQvHLX8AR9LE/p900HQwSIxYeuwB7FYOr7wpwKc aR5ol3wZY63Xgmia+CJp8RUc+P4ck8DiXMI61jvypTzcNk0WguWktKN5oPJDE7y60hUJPmP T7lenaEJdiFrWQiKai8zhbhysAEa2yBWoxmcvn1KYmkuKh8DgQ6yVzWi0KbzExb/aIxhUa2 dsHe296zuY0tRUC6yp8ZNr8pCUWsO+RcyS0S++MZ1fCXtwv8kImplq2eo9G7JJv8hYxRj1Z Th6FMDwVCr3K9jS+4iGue61r2/qU4T8176yL5HV3X/kgYdxp91HBPo119OmToCnlmHKlVKn NVh1wv5Yl+mbL8P7oFPkG32ljl5R6wOqxSEeSJU0Nk45HzaPUI= X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Subject: [PATCH v2 08/12] net/ngbe: fix debug log Date: Wed, 9 Feb 2022 18:42:09 +0800 Message-Id: <20220209104213.602728-9-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220209104213.602728-1-jiawenwu@trustnetic.com> References: <20220209104213.602728-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign1 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Remove 'DEBUGFUNC' due to too many invalid debug log prints. And fix that double line was added by using 'DEBUGOUT'. Fixes: cc934df178ab ("net/ngbe: add log and error types") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/ngbe/ngbe_logs.h | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/net/ngbe/ngbe_logs.h b/drivers/net/ngbe/ngbe_logs.h index fd306419e6..b7d78fb400 100644 --- a/drivers/net/ngbe/ngbe_logs.h +++ b/drivers/net/ngbe/ngbe_logs.h @@ -15,9 +15,12 @@ extern int ngbe_logtype_init; "%s(): " fmt "\n", __func__, ##args) extern int ngbe_logtype_driver; -#define PMD_DRV_LOG(level, fmt, args...) \ +#define PMD_TLOG_DRIVER(level, fmt, args...) \ rte_log(RTE_LOG_ ## level, ngbe_logtype_driver, \ - "%s(): " fmt "\n", __func__, ##args) + "%s(): " fmt, __func__, ##args) + +#define PMD_DRV_LOG(level, fmt, args...) \ + PMD_TLOG_DRIVER(level, fmt "\n", ## args) #ifdef RTE_ETHDEV_DEBUG_RX extern int ngbe_logtype_rx; @@ -37,10 +40,10 @@ extern int ngbe_logtype_tx; #define PMD_TX_LOG(level, fmt, args...) do { } while (0) #endif -#define TLOG_DEBUG(fmt, args...) PMD_DRV_LOG(DEBUG, fmt, ##args) +#define TLOG_DEBUG(fmt, args...) PMD_TLOG_DRIVER(DEBUG, fmt, ##args) #define DEBUGOUT(fmt, args...) TLOG_DEBUG(fmt, ##args) #define PMD_INIT_FUNC_TRACE() TLOG_DEBUG(" >>") -#define DEBUGFUNC(fmt) TLOG_DEBUG(fmt) +#define DEBUGFUNC(fmt) do { } while (0) #endif /* _NGBE_LOGS_H_ */ From patchwork Wed Feb 9 10:42:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 107117 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CB8B9A04A6; Wed, 9 Feb 2022 11:36:34 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 44BC541229; Wed, 9 Feb 2022 11:35:57 +0100 (CET) Received: from smtpbgeu1.qq.com (smtpbgeu1.qq.com [52.59.177.22]) by mails.dpdk.org (Postfix) with ESMTP id 9625A41143 for ; Wed, 9 Feb 2022 11:35:54 +0100 (CET) X-QQ-mid: bizesmtp37t1644402951tnz4iipv Received: from wxdbg.localdomain.com (unknown [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 09 Feb 2022 18:35:50 +0800 (CST) X-QQ-SSF: 01400000002000F0L000B00A0000000 X-QQ-FEAT: G+mSt178IQpNPnchUQW3iPcjH1Otwvn1525/62khgyZ7oQiSS/PtkwDqsIzOq 3VOhRTGeKbxoeXrp7d8bqL5hF14PeHlGvnqB8GlZ+PQtnbXGbsdCOAtadDKEkPLYPpmiS0p vtSHn1kb+ER1r3S/ClTE/GPagtxTP82r1/4Ma84TLKhbkg0Qc92OEgfO16UE3foKOJiJrM+ TEy51gE2074OkD4vz6hRNixA10Bc12GkMf9RgnWoimr1zrURPxnIne/J9KhD3DQy8bLKrNb ry2TgeG3jZyGZHTAVG1R+11hpVx6lO0CLJ2HpF7cg6z8bPWCz5WRN3afEhqU8C++L6JsdR0 0H1g+5ZQ2ZOTT6KN9cLbGgg2YaIJpvh+WeFj3aOUNo61dEddng= X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu Subject: [PATCH v2 09/12] net/txgbe: add LED OEM support Date: Wed, 9 Feb 2022 18:42:10 +0800 Message-Id: <20220209104213.602728-10-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220209104213.602728-1-jiawenwu@trustnetic.com> References: <20220209104213.602728-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign1 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Support to configure LED in firmware. Driver commands firmware to turn the LED on and off. And OEM customize their LED solutions in firmware. Signed-off-by: Jiawen Wu --- doc/guides/nics/features/txgbe.ini | 1 + doc/guides/rel_notes/release_22_03.rst | 4 ++ drivers/net/txgbe/base/txgbe_hw.c | 21 ++++---- drivers/net/txgbe/base/txgbe_mng.c | 69 ++++++++++++++++++++++++++ drivers/net/txgbe/base/txgbe_mng.h | 7 +++ drivers/net/txgbe/base/txgbe_regs.h | 12 +++-- drivers/net/txgbe/txgbe_ethdev.c | 4 +- 7 files changed, 101 insertions(+), 17 deletions(-) diff --git a/doc/guides/nics/features/txgbe.ini b/doc/guides/nics/features/txgbe.ini index 6d0cc8afdd..22c74ba9e3 100644 --- a/doc/guides/nics/features/txgbe.ini +++ b/doc/guides/nics/features/txgbe.ini @@ -45,6 +45,7 @@ FW version = Y EEPROM dump = Y Module EEPROM dump = Y Registers dump = Y +LED = Y Multiprocess aware = Y Linux = Y ARMv8 = Y diff --git a/doc/guides/rel_notes/release_22_03.rst b/doc/guides/rel_notes/release_22_03.rst index 46bc286934..b6aaed1dcf 100644 --- a/doc/guides/rel_notes/release_22_03.rst +++ b/doc/guides/rel_notes/release_22_03.rst @@ -77,6 +77,10 @@ New Features - YT8521S PHY connects to SFP * Added LED OEM support. +* **Updated Wangxun txgbe driver.** + + * Added LED OEM support. + * **Added an API to retrieve event port id of ethdev Rx adapter.** The new API ``rte_event_eth_rx_adapter_event_port_get()`` was added. diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c index 00a8db78bf..db8ffe61a4 100644 --- a/drivers/net/txgbe/base/txgbe_hw.c +++ b/drivers/net/txgbe/base/txgbe_hw.c @@ -529,12 +529,9 @@ s32 txgbe_led_on(struct txgbe_hw *hw, u32 index) DEBUGFUNC("txgbe_led_on"); - if (index > 4) - return TXGBE_ERR_PARAM; - /* To turn on the LED, set mode to ON. */ - led_reg |= TXGBE_LEDCTL_SEL(index); - led_reg |= TXGBE_LEDCTL_ORD(index); + led_reg |= index << TXGBE_LEDCTL_ORD_SHIFT; + led_reg |= index; wr32(hw, TXGBE_LEDCTL, led_reg); txgbe_flush(hw); @@ -552,12 +549,9 @@ s32 txgbe_led_off(struct txgbe_hw *hw, u32 index) DEBUGFUNC("txgbe_led_off"); - if (index > 4) - return TXGBE_ERR_PARAM; - /* To turn off the LED, set mode to OFF. */ - led_reg &= ~(TXGBE_LEDCTL_SEL(index)); - led_reg &= ~(TXGBE_LEDCTL_ORD(index)); + led_reg &= ~(index << TXGBE_LEDCTL_ORD_SHIFT); + led_reg |= index; wr32(hw, TXGBE_LEDCTL, led_reg); txgbe_flush(hw); @@ -3054,6 +3048,10 @@ void txgbe_disable_tx_laser_multispeed_fiber(struct txgbe_hw *hw) if (txgbe_check_reset_blocked(hw)) return; + if (txgbe_close_notify(hw)) + txgbe_led_off(hw, TXGBE_LEDCTL_UP | TXGBE_LEDCTL_10G | + TXGBE_LEDCTL_1G | TXGBE_LEDCTL_ACTIVE); + /* Disable Tx laser; allow 100us to go dark per spec */ esdp_reg |= (TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1); wr32(hw, TXGBE_GPIODATA, esdp_reg); @@ -3073,6 +3071,9 @@ void txgbe_enable_tx_laser_multispeed_fiber(struct txgbe_hw *hw) { u32 esdp_reg = rd32(hw, TXGBE_GPIODATA); + if (txgbe_open_notify(hw)) + wr32(hw, TXGBE_LEDCTL, 0); + /* Enable Tx laser; allow 100ms to light up */ esdp_reg &= ~(TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1); wr32(hw, TXGBE_GPIODATA, esdp_reg); diff --git a/drivers/net/txgbe/base/txgbe_mng.c b/drivers/net/txgbe/base/txgbe_mng.c index dbe512122c..d0aa665d4a 100644 --- a/drivers/net/txgbe/base/txgbe_mng.c +++ b/drivers/net/txgbe/base/txgbe_mng.c @@ -82,6 +82,11 @@ txgbe_hic_unlocked(struct txgbe_hw *hw, u32 *buffer, u32 length, u32 timeout) return TXGBE_ERR_HOST_INTERFACE_COMMAND; } + if ((rd32(hw, TXGBE_MNGMBX) & 0xff0000) >> 16 == 0x80) { + DEBUGOUT("It's unknown command.\n"); + return TXGBE_ERR_MNG_ACCESS_FAILED; + } + return 0; } @@ -262,6 +267,70 @@ s32 txgbe_hic_sr_write(struct txgbe_hw *hw, u32 addr, u8 *buf, int len) return err; } +s32 txgbe_close_notify(struct txgbe_hw *hw) +{ + u32 tmp; + s32 status; + struct txgbe_hic_write_shadow_ram buffer; + + DEBUGFUNC("txgbe_close_notify"); + + buffer.hdr.req.cmd = FW_DW_CLOSE_NOTIFY; + buffer.hdr.req.buf_lenh = 0; + buffer.hdr.req.buf_lenl = 0; + buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; + + /* one word */ + buffer.length = 0; + buffer.address = 0; + + status = txgbe_host_interface_command(hw, (u32 *)&buffer, + sizeof(buffer), + TXGBE_HI_COMMAND_TIMEOUT, false); + if (status) + return status; + + tmp = rd32(hw, TXGBE_MNGSWSYNC); + if (tmp == TXGBE_CHECKSUM_CAP_ST_PASS) + status = 0; + else + status = TXGBE_ERR_EEPROM_CHECKSUM; + + return status; +} + +s32 txgbe_open_notify(struct txgbe_hw *hw) +{ + u32 tmp; + s32 status; + struct txgbe_hic_write_shadow_ram buffer; + + DEBUGFUNC("txgbe_open_notify"); + + buffer.hdr.req.cmd = FW_DW_OPEN_NOTIFY; + buffer.hdr.req.buf_lenh = 0; + buffer.hdr.req.buf_lenl = 0; + buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; + + /* one word */ + buffer.length = 0; + buffer.address = 0; + + status = txgbe_host_interface_command(hw, (u32 *)&buffer, + sizeof(buffer), + TXGBE_HI_COMMAND_TIMEOUT, false); + if (status) + return status; + + tmp = rd32(hw, TXGBE_MNGSWSYNC); + if (tmp == TXGBE_CHECKSUM_CAP_ST_PASS) + status = 0; + else + status = TXGBE_ERR_EEPROM_CHECKSUM; + + return status; +} + /** * txgbe_hic_set_drv_ver - Sends driver version to firmware * @hw: pointer to the HW structure diff --git a/drivers/net/txgbe/base/txgbe_mng.h b/drivers/net/txgbe/base/txgbe_mng.h index 1004f41c72..24d938fecf 100644 --- a/drivers/net/txgbe/base/txgbe_mng.h +++ b/drivers/net/txgbe/base/txgbe_mng.h @@ -51,6 +51,11 @@ #define FW_PHY_TOKEN_DELAY 5 /* milliseconds */ #define FW_PHY_TOKEN_WAIT 5 /* seconds */ #define FW_PHY_TOKEN_RETRIES ((FW_PHY_TOKEN_WAIT * 1000) / FW_PHY_TOKEN_DELAY) +#define FW_DW_OPEN_NOTIFY 0xE9 +#define FW_DW_CLOSE_NOTIFY 0xEA + +#define TXGBE_CHECKSUM_CAP_ST_PASS 0x80658383 +#define TXGBE_CHECKSUM_CAP_ST_FAIL 0x70657376 /* Host Interface Command Structures */ struct txgbe_hic_hdr { @@ -168,6 +173,8 @@ struct txgbe_hic_upg_verify { s32 txgbe_hic_sr_read(struct txgbe_hw *hw, u32 addr, u8 *buf, int len); s32 txgbe_hic_sr_write(struct txgbe_hw *hw, u32 addr, u8 *buf, int len); +s32 txgbe_close_notify(struct txgbe_hw *hw); +s32 txgbe_open_notify(struct txgbe_hw *hw); s32 txgbe_hic_set_drv_ver(struct txgbe_hw *hw, u8 maj, u8 min, u8 build, u8 ver, u16 len, const char *str); diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h index 144047ba62..3139796911 100644 --- a/drivers/net/txgbe/base/txgbe_regs.h +++ b/drivers/net/txgbe/base/txgbe_regs.h @@ -302,11 +302,13 @@ #define TXGBE_TEREDOPORT 0x01441C #define TXGBE_LEDCTL 0x014424 #define TXGBE_LEDCTL_SEL_MASK MS(0, 0xFFFF) -#define TXGBE_LEDCTL_SEL(s) MS((s), 0x1) -#define TXGBE_LEDCTL_ORD_MASK MS(16, 0xFFFF) -#define TXGBE_LEDCTL_ORD(s) MS(((s)+16), 0x1) - /* s=UP(0),10G(1),1G(2),100M(3),BSY(4) */ -#define TXGBE_LEDCTL_ACTIVE (TXGBE_LEDCTL_SEL(4) | TXGBE_LEDCTL_ORD(4)) +#define TXGBE_LEDCTL_ORD_MASK MS(16, 0xFFFF) +#define TXGBE_LEDCTL_ORD_SHIFT 16 +#define TXGBE_LEDCTL_UP MS(0, 0x1) +#define TXGBE_LEDCTL_10G MS(1, 0x1) +#define TXGBE_LEDCTL_1G MS(2, 0x1) +#define TXGBE_LEDCTL_100M MS(3, 0x1) +#define TXGBE_LEDCTL_ACTIVE MS(4, 0x1) #define TXGBE_TAGTPID(i) (0x014430 + (i) * 4) /* 0-3 */ #define TXGBE_TAGTPID_LSB_MASK MS(0, 0xFFFF) #define TXGBE_TAGTPID_LSB(v) LS(v, 0, 0xFFFF) diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c index ac4d4e08f4..4799a60116 100644 --- a/drivers/net/txgbe/txgbe_ethdev.c +++ b/drivers/net/txgbe/txgbe_ethdev.c @@ -3166,7 +3166,7 @@ txgbe_dev_led_on(struct rte_eth_dev *dev) struct txgbe_hw *hw; hw = TXGBE_DEV_HW(dev); - return txgbe_led_on(hw, 4) == 0 ? 0 : -ENOTSUP; + return txgbe_led_on(hw, TXGBE_LEDCTL_ACTIVE) == 0 ? 0 : -ENOTSUP; } static int @@ -3175,7 +3175,7 @@ txgbe_dev_led_off(struct rte_eth_dev *dev) struct txgbe_hw *hw; hw = TXGBE_DEV_HW(dev); - return txgbe_led_off(hw, 4) == 0 ? 0 : -ENOTSUP; + return txgbe_led_off(hw, TXGBE_LEDCTL_ACTIVE) == 0 ? 0 : -ENOTSUP; } static int From patchwork Wed Feb 9 10:42:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 107120 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EE6BFA04A9; Wed, 9 Feb 2022 11:36:53 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D2B044118A; Wed, 9 Feb 2022 11:36:08 +0100 (CET) Received: from smtpbgbr2.qq.com (smtpbgbr2.qq.com [54.207.22.56]) by mails.dpdk.org (Postfix) with ESMTP id 8F38441C3D for ; Wed, 9 Feb 2022 11:36:06 +0100 (CET) X-QQ-mid: bizesmtp37t1644402953ti62rr90 Received: from wxdbg.localdomain.com (unknown [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 09 Feb 2022 18:35:52 +0800 (CST) X-QQ-SSF: 01400000002000F0L000B00A0000000 X-QQ-FEAT: xoS364mEyr34hnzgQqRUYl+ZTF2j5DOI7sAz9y6OCymDYyloDggMwOxA844lJ EO6UewF1z+P+04BPntLLdQPvMbPpq/GeJbJKDDmMmJkp1rqEMZBvxmg+OlRlupPsPqOnWj6 Zc+0znooxTL/EOcyZW6L9aRaBvoryFnku3N+xTuwafd5IGT2h9XooYOXyXfOPPXz67ogzZS B5vmhhVqqgRGscKz7j+mMv56NbinWIBXY6ByQ0Beo3YgQ6Puo7zzqAWc+wsUngG2qf/+MvN 6yZv/khMJpahrZP/DTcaA4f/dNA1kYTzzVqZ7/nu4KbUGnQI4CIFAfLOikyKSFkl8mGMcyZ 3TC8rG+iVud3xi3SPKvGOOMt+I/XNJUEFfF91zysDmtHYJ/kHA= X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Subject: [PATCH v2 10/12] net/txgbe: fix debug log Date: Wed, 9 Feb 2022 18:42:11 +0800 Message-Id: <20220209104213.602728-11-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220209104213.602728-1-jiawenwu@trustnetic.com> References: <20220209104213.602728-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign2 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Remove 'DEBUGFUNC' due to too many invalid debug log prints. And fix that double line was added by using 'DEBUGOUT'. Fixes: 7dc117068a7c ("net/txgbe: support probe and remove") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/txgbe/txgbe_logs.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/net/txgbe/txgbe_logs.h b/drivers/net/txgbe/txgbe_logs.h index 67e9bfb3af..8fa80a69b2 100644 --- a/drivers/net/txgbe/txgbe_logs.h +++ b/drivers/net/txgbe/txgbe_logs.h @@ -17,10 +17,13 @@ extern int txgbe_logtype_init; "%s(): " fmt "\n", __func__, ##args) extern int txgbe_logtype_driver; -#define PMD_DRV_LOG(level, fmt, args...) \ +#define PMD_TLOG_DRIVER(level, fmt, args...) \ rte_log(RTE_LOG_ ## level, txgbe_logtype_driver, \ "%s(): " fmt "\n", __func__, ##args) +#define PMD_DRV_LOG(level, fmt, args...) \ + PMD_TLOG_DRIVER(level, fmt "\n", ## args) + #ifdef RTE_LIBRTE_TXGBE_DEBUG_RX extern int txgbe_logtype_rx; #define PMD_RX_LOG(level, fmt, args...) \ @@ -48,11 +51,11 @@ extern int txgbe_logtype_tx_free; #define PMD_TX_FREE_LOG(level, fmt, args...) do { } while (0) #endif -#define TLOG_DEBUG(fmt, args...) PMD_DRV_LOG(DEBUG, fmt, ##args) +#define TLOG_DEBUG(fmt, args...) PMD_TLOG_DRIVER(DEBUG, fmt, ##args) #define DEBUGOUT(fmt, args...) TLOG_DEBUG(fmt, ##args) #define PMD_INIT_FUNC_TRACE() TLOG_DEBUG(" >>") -#define DEBUGFUNC(fmt) TLOG_DEBUG(fmt) +#define DEBUGFUNC(fmt) do { } while (0) extern int txgbe_logtype_bp; #define BP_LOG(fmt, args...) \ From patchwork Wed Feb 9 10:42:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 107119 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3611EA04A6; Wed, 9 Feb 2022 11:36:48 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C18AE426D4; Wed, 9 Feb 2022 11:36:03 +0100 (CET) Received: from smtpproxy21.qq.com (smtpbg702.qq.com [203.205.195.102]) by mails.dpdk.org (Postfix) with ESMTP id 89B6441141 for ; Wed, 9 Feb 2022 11:36:01 +0100 (CET) X-QQ-mid: bizesmtp37t1644402955tor112ej Received: from wxdbg.localdomain.com (unknown [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 09 Feb 2022 18:35:54 +0800 (CST) X-QQ-SSF: 01400000002000F0L000B00A0000000 X-QQ-FEAT: AYaL7CbwjQ2rINL3AQrLbUquQirEO+h1dtOumtrQl++l0tIi/OpTirCO/xdaT jSBRHUxa9pEXbUqTor+m2Lg03n/jXJBUuEzD+4JST3Ei2GjNg+6xLJ0JwT4UZ5b42MlwHFB oGqgybUK3XmCQMzdU8OVYxzXlnNgJMpzGWkTXomF3/hrl5h8lrnbbrjyUlP1A5dgai5OMZc a8Sqn8KqwTGoSByXOgqrnzfCYADybSHNa5obRRew+aR+dHiUNq1U2ChWTu5Uf3UNScAJ/Tz IM+QnuxXsKgPZ4zMGR9vBXaoTECayaYdQEj6h/izcplqGW4eNXrvHqvg9X2VsPWMWqOulPa jY0bbozhQ4tl3vJRdKmvRjaE3CVOxngNvwOcvbrlvgvj5wiLY8= X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Subject: [PATCH v2 11/12] net/txgbe: fix to set link up and down Date: Wed, 9 Feb 2022 18:42:12 +0800 Message-Id: <20220209104213.602728-12-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220209104213.602728-1-jiawenwu@trustnetic.com> References: <20220209104213.602728-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign7 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add hw->dev_start status in the flow of setting link up/down, to avoid obtaining link status inconsistent with the settings. Fixes: 12a653eb53e1 ("net/txgbe: fix link status when device stopped") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/txgbe/txgbe_ethdev.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c index 4799a60116..6bc209e661 100644 --- a/drivers/net/txgbe/txgbe_ethdev.c +++ b/drivers/net/txgbe/txgbe_ethdev.c @@ -1937,6 +1937,7 @@ txgbe_dev_set_link_up(struct rte_eth_dev *dev) } else { /* Turn on the laser */ hw->mac.enable_tx_laser(hw); + hw->dev_start = true; txgbe_dev_link_update(dev, 0); } @@ -1957,6 +1958,7 @@ txgbe_dev_set_link_down(struct rte_eth_dev *dev) } else { /* Turn off the laser */ hw->mac.disable_tx_laser(hw); + hw->dev_start = false; txgbe_dev_link_update(dev, 0); } From patchwork Wed Feb 9 10:42:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 107121 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6476CA04A6; Wed, 9 Feb 2022 11:36:59 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B8211426DC; Wed, 9 Feb 2022 11:36:09 +0100 (CET) Received: from smtpbg506.qq.com (smtpbg506.qq.com [203.205.250.33]) by mails.dpdk.org (Postfix) with ESMTP id D4C92426DC for ; Wed, 9 Feb 2022 11:36:06 +0100 (CET) X-QQ-mid: bizesmtp37t1644402956tjbs2pqh Received: from wxdbg.localdomain.com (unknown [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 09 Feb 2022 18:35:56 +0800 (CST) X-QQ-SSF: 01400000002000F0L000B00A0000000 X-QQ-FEAT: jmpb/TFoY7rghX7nK2XpuIUUwokASeapyw8w9kqaZG2pVP+DFBkR1ah7jGv5L /7IeZiWSgawuGFxc0Wi++8mBs9RIxivH5gNS9wf0N+hCPVTvGSe+hDilsOCrO/cgkLILj4d peM9DaPbI9Yj05kzD3haN/uSJUzhe9BGimoH/N5aYOZAGiA40M6/FaoOGvmkMFt7KNrJ6tU JFuVu85L/CuEmKN5c+pLbR/Dg7BUMHbcX2zozqoPXFLcx8JhJe1M/Fna/4WMygpUCw4+h8T SLxmgQ/a7eAvUVFPx6a9WP+iFfoSzCx/pjp4kW/SmuK0DUoYSt0H9JM07qIqlzFeKEHlAhS Mpq5iQ4iBMf+WjEwyvbGpJd830agngiofPUTwta4Y9du9LuEVA= X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Subject: [PATCH v2 12/12] net/txgbe: fix KR auto-negotiation Date: Wed, 9 Feb 2022 18:42:13 +0800 Message-Id: <20220209104213.602728-13-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220209104213.602728-1-jiawenwu@trustnetic.com> References: <20220209104213.602728-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign5 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fix failure to enter auto-negotiation mode on some firmware versions for KR NICs. Fixes: f611dada1af8 ("net/txgbe: update link setup process of backplane NICs") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/txgbe/base/txgbe_phy.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c index 3f5229ecc2..3fb929f37a 100644 --- a/drivers/net/txgbe/base/txgbe_phy.c +++ b/drivers/net/txgbe/base/txgbe_phy.c @@ -1455,6 +1455,10 @@ txgbe_set_link_to_kr(struct txgbe_hw *hw, bool autoneg) if (!(hw->devarg.auto_neg == 1)) { wr32_epcs(hw, SR_AN_CTRL, 0); wr32_epcs(hw, VR_AN_KR_MODE_CL, 0); + } else { + value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1); + value &= ~(1 << 6); + wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); } if (hw->devarg.present == 1) { value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);