From patchwork Mon Feb 7 16:13:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Fu, Qi" X-Patchwork-Id: 106952 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D16C7A034F; Mon, 7 Feb 2022 08:39:11 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 92A3D40685; Mon, 7 Feb 2022 08:39:11 +0100 (CET) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id D6C674067C for ; Mon, 7 Feb 2022 08:39:09 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644219550; x=1675755550; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=zHvj3KjdlsqeydEI3Pdwg9yI31ZMMRIrflee8H/vi5o=; b=TPN/izI3aOMyaFheC1g08qAmsvpIYcL2HlkVO9OeS9qRa7r/VSVeJR1+ my/5ve/9+7RS0lbnSDiN/M3lski5q8YVbhgFMEFY1PoMm7jHBFt/NiJvC stST+9pMFrzyHl34a1gSkVJISJf73DJz3H8diFz4dwIIMRb1m36j6hZHL r1ZeFdJZJoVC98rkj2OA11GVGb9v/bpYEl9a2UpN0ds/eXHJx5kDQpYim KUwf9FSyE3tj/nXJyw/j1cbBtk34WxgHV60rH6INdxsKpN+avz6W9L9kq jbBtAI2jF1dOoLl/5BottmbOwoqzO7Z8b3XNU/aMm4pqF7sZwHfb9AbzF Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10250"; a="311960878" X-IronPort-AV: E=Sophos;i="5.88,349,1635231600"; d="scan'208";a="311960878" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2022 23:39:09 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,349,1635231600"; d="scan'208";a="567390091" Received: from dpdk-qifu-cxl.sh.intel.com ([10.67.119.122]) by orsmga001.jf.intel.com with ESMTP; 06 Feb 2022 23:39:07 -0800 From: Qi Fu To: dts@dpdk.org Cc: Qi Fu Subject: [dts][PATCH V4]test_plans: add test plan for cvl 1pps signal Date: Tue, 8 Feb 2022 00:13:42 +0800 Message-Id: <20220207161342.94286-1-qi.fu@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: dts@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: test suite reviews and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dts-bounces@dpdk.org Add test plan for cvl enable 1PPS signal. Signed-off-by: Qi Fu --- test_plans/cvl_1pps_signal_test_plan.rst | 160 +++++++++++++++++++++++ test_plans/index.rst | 1 + 2 files changed, 161 insertions(+) create mode 100644 test_plans/cvl_1pps_signal_test_plan.rst diff --git a/test_plans/cvl_1pps_signal_test_plan.rst b/test_plans/cvl_1pps_signal_test_plan.rst new file mode 100644 index 00000000..8d279ff7 --- /dev/null +++ b/test_plans/cvl_1pps_signal_test_plan.rst @@ -0,0 +1,160 @@ +.. Copyright (c) <2021>, Intel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + - Neither the name of Intel Corporation nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + OF THE POSSIBILITY OF SUCH DAMAGE. + +========================= +CVL 1PPS Signal Test Plan +========================= + +Description +=========== +The E810 supports a total of four single-ended GPIO signals(SPD[20:23])plus one different GPIO signal (CLK_OUT_P/N), +which is configured by default 1PPS(out). The SPD[20:23] is mapping to pin_id[0:3]. +This test plan is designed to check the value of related registers, which make up the 1PPS signal. +The registers address depends on some hardware config. +The test cases only give the example of Columbiaville_25g and Columbiaville_100g. + + +Prerequisites +============= + +Topology +-------- +DUT port 0 <----> Tester port 0 + +Hardware +-------- +Supported NICs: columbiaville_25g/columbiaville_100g + +Software +-------- +dpdk: http://dpdk.org/git/dpdk +scapy: http://www.secdev.org/projects/scapy/ + +General set up +-------------- +1. Compile DPDK:: + + # CC=gcc meson --werror -Denable_kmods=True -Dlibdir=lib --default-library=static + # ninja -C -j 110 + +2. Get the pci device id and interface of DUT and tester. + For example, 0000:18:00.0 and 0000:18:00.1 is pci device id, + ens785f0 and ens785f1 is interface:: + + # ./usertools/dpdk-devbind.py -s + + 0000:18:00.0 'Device 159b' if=ens785f0 drv=ice unused=vfio-pci + 0000:18:00.1 'Device 159b' if=ens785f1 drv=ice unused=vfio-pci + +3. Bind the DUT port to dpdk:: + + # ./usertools/dpdk-devbind.py -b vfio-pci + + +Test case +========= + +Test case 1: check registers when pin id is 0 +--------------------------------------------- + +this case is designed to check the register value is right when pin id is 0. + +test steps +~~~~~~~~~~ +1. start testpmd with different pin_id and dump registers:: + + /app/dpdk-testpmd -a ,pps_out='[pin:0]' -- -i --rxq=4 --txq=4 + testpmd> read reg 0 0x00088998 + testpmd> read reg 0 0x000889B8 + testpmd> read reg 0 0x00088928 + testpmd> read reg 0 0x00088930 + testpmd> read reg 0 0x000880C8 + +2. check the GLTSYN_AUX_OUT_0[0] 0x00088998 is 0x00000007 (7), GLTSYN_CLKO_0[0] 0x000889B8 is 0x1DCD6500 (500000000), the 0x00088928 and 0x00088930 is non-zero, + The 3rd Hexadecimal digit of GLGEN_GPIO_CTL[0] 0x000880C8 is 8. And the 4th binary digit is 1. + +Test case 2: check registers when pin id is 1 +--------------------------------------------- + +this case is designed to check the register value is right when pin id is 1. + +test steps +~~~~~~~~~~ +1. start testpmd with different pin_id and dump registers:: + + ./x86_64-native-linuxapp-gcc/app/dpdk-testpmd -c 0xf -n 4 -a 0000:18:00.0,pps_out='[pin:1]' -- -i --rxq=4 --txq=4 + testpmd> read reg 0 0x000889A0 + testpmd> read reg 0 0x000889C0 + testpmd> read reg 0 0x00088938 + testpmd> read reg 0 0x00088940 + testpmd> read reg 0 0x000880CC + +2. check the GLTSYN_AUX_OUT_1[0] 0x000889A0 is 0x00000007 (7), GLTSYN_CLKO_1[0] 0x000889C0 is 0x1DCD6500 (500000000), the 0x00088938 and 0x00088940 is non-zero, + The 3rd Hexadecimal digit of GLGEN_GPIO_CTL[1] 0x000880CC is 9. And the 4th binary digit is 1. + +Test case 3: check registers when pin id is 2 +--------------------------------------------- + +this case is designed to check the register value is right when pin id is 2. + +test steps +~~~~~~~~~~ +1. start testpmd with different pin_id and dump registers:: + + ./x86_64-native-linuxapp-gcc/app/dpdk-testpmd -c 0xf -n 4 -a 0000:18:00.0,pps_out='[pin:2]' -- -i --rxq=4 --txq=4 + testpmd> read reg 0 0x000889A8 + testpmd> read reg 0 0x000889C8 + testpmd> read reg 0 0x00088948 + testpmd> read reg 0 0x00088950 + testpmd> read reg 0 0x000880D0 + +2. check the GLTSYN_AUX_OUT_2[0] 0x000889A8 is 0x00000007 (7), GLTSYN_CLKO_2[0] 0x000889C8 is 0x1DCD6500 (500000000), the 0x00088948 and 0x00088950 is non-zero, + The 3rd Hexadecimal digit of GLGEN_GPIO_CTL[2] 0x000880D0 is A. And the 4th binary digit is 1. + +Test case 4: check registers when pin id is 3 +--------------------------------------------- + +this case is designed to check the register value is right when pin id is 3. + +test steps +~~~~~~~~~~ +1. start testpmd with different pin_id and dump registers:: + + ./x86_64-native-linuxapp-gcc/app/dpdk-testpmd -c 0xf -n 4 -a 0000:18:00.0,pps_out='[pin:3]' -- -i --rxq=4 --txq=4 + testpmd> read reg 0 0x000889B0 + testpmd> read reg 0 0x000889D0 + testpmd> read reg 0 0x00088958 + testpmd> read reg 0 0x00088960 + testpmd> read reg 0 0x000880D4 + +2. check the GLTSYN_AUX_OUT_3[0] 0x000889B0 is 0x00000007 (7), GLTSYN_CLKO_3[0] 0x000889D0 is 0x1DCD6500 (500000000), the 0x00088958 and 0x00088960 is non-zero, + The 3rd Hexadecimal digit of GLGEN_GPIO_CTL[3] 0x000880D4 is B. And the 4th binary digit is 1. \ No newline at end of file diff --git a/test_plans/index.rst b/test_plans/index.rst index 68250fca..f83bacfe 100644 --- a/test_plans/index.rst +++ b/test_plans/index.rst @@ -69,6 +69,7 @@ The following are the test plans for the DPDK DTS automated test system. cvl_switch_filter_test_plan cvl_switch_filter_pppoe_test_plan cvl_vf_support_multicast_address_test_plan + cvl_1pps_signal_test_plan cloud_filter_with_l4_port_test_plan dcf_lifecycle_test_plan crypto_perf_cryptodev_perf_test_plan