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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT026.mail.protection.outlook.com (10.13.172.161) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4713.20 via Frontend Transport; Wed, 24 Nov 2021 09:36:15 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 24 Nov 2021 09:36:11 +0000 From: Dmitry Kozlyuk To: CC: Raslan Darawsheh , Matan Azrad , Viacheslav Ovsiienko Subject: [PATCH 1/2] net/mlx5: fix indirect RSS creation when port is stopped Date: Wed, 24 Nov 2021 11:35:52 +0200 Message-ID: <20211124093556.3358394-2-dkozlyuk@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211124093556.3358394-1-dkozlyuk@nvidia.com> References: <20211123223159.3324247-1-dkozlyuk@nvidia.com> <20211124093556.3358394-1-dkozlyuk@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5415f257-1588-4f40-9e80-08d9af2ddc64 X-MS-TrafficTypeDiagnostic: CY4PR12MB1798: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2000; 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Only increment reference counter when the port is started. Fixes: ec4e11d41d12 ("net/mlx5: preserve indirect actions on restart") Signed-off-by: Dmitry Kozlyuk --- drivers/net/mlx5/mlx5_rxq.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index 47dc24793b..8f9a94572f 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -2270,6 +2270,7 @@ mlx5_ind_table_obj_setup(struct rte_eth_dev *dev, struct mlx5_ind_table_obj *ind_tbl) { struct mlx5_priv *priv = dev->data->dev_private; + bool dev_started = priv->dev_data->dev_started; uint32_t queues_n = ind_tbl->queues_n; uint16_t *queues = ind_tbl->queues; unsigned int i, j; @@ -2278,22 +2279,25 @@ mlx5_ind_table_obj_setup(struct rte_eth_dev *dev, log2above(queues_n) : log2above(priv->config.ind_table_max_size); - for (i = 0; i != queues_n; ++i) { - if (mlx5_rxq_ref(dev, queues[i]) == NULL) { - ret = -rte_errno; - goto error; + if (dev_started) + for (i = 0; i != queues_n; ++i) { + if (mlx5_rxq_ref(dev, queues[i]) == NULL) { + ret = -rte_errno; + goto error; + } } - } ret = priv->obj_ops.ind_table_new(dev, n, ind_tbl); if (ret) goto error; __atomic_fetch_add(&ind_tbl->refcnt, 1, __ATOMIC_RELAXED); return 0; error: - err = rte_errno; - for (j = 0; j < i; j++) - mlx5_rxq_deref(dev, ind_tbl->queues[j]); - rte_errno = err; + if (dev_started) { + err = rte_errno; + for (j = 0; j < i; j++) + mlx5_rxq_deref(dev, queues[j]); + rte_errno = err; + } DRV_LOG(DEBUG, "Port %u cannot setup indirection table.", dev->data->port_id); return ret; From patchwork Wed Nov 24 09:35:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Kozlyuk X-Patchwork-Id: 104656 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9A42DA0C52; Wed, 24 Nov 2021 10:36:36 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6B8394115E; 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Wed, 24 Nov 2021 09:36:13 +0000 From: Dmitry Kozlyuk To: CC: Raslan Darawsheh , Matan Azrad , Viacheslav Ovsiienko Subject: [PATCH 2/2] net/mlx5: fix RxQ reference counting for indirect RSS Date: Wed, 24 Nov 2021 11:35:53 +0200 Message-ID: <20211124093556.3358394-3-dkozlyuk@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211124093556.3358394-1-dkozlyuk@nvidia.com> References: <20211123223159.3324247-1-dkozlyuk@nvidia.com> <20211124093556.3358394-1-dkozlyuk@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 37bd8218-67ac-48de-75a7-08d9af2ddd36 X-MS-TrafficTypeDiagnostic: MWHPR12MB1423: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2089; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /NNq9pml0ElbhM16xd8KZGmhlUW9w7tFj8DxQMWk1DWClKoUkOVptvkRzcXIUcYnli0sxXjM+3DiM3DBxpBybManFU8gwiTDDcTPKMAtsWIMhmhvgm+4PZcOHOgB4JFhUZSaIAxgLJx5k9zhfo14vY/cvl2lAXgiBflEf5yDNyZ9bNCbVg2D624JBtcWS6GW2NSsfcTlFGhxm+FruvZqS79DKG9I413dm7cq8wFiYiILKI5rx6g0Df60qGM8E4oFUJg3j45BLc8pIJrtrTqerVXiBqZl4o5KvqsxWkbmciImLfzWvpYa3n4I1GDtvN4wlHKmBmfcVi5qfE+DqehT/6zulUhbQPHiqAqolniKTDknpg+nIhP8NMQ9Hk9R7ZoNtOLf4b5URXPpCukW5m5q//yroLqbeNsug7If3TUA+VMt0zpys5BDomy/C1oV6dUcvpIj9oHAnYH19wgzbnElzYqiE8pj1fKoQOHsxZhBH6Oi+tzh5TAD3nniFFhMKkMLFADoSMHSzC2vInaNuY89c3uf7bU+0HeqT/ltChfFVTCapxf0agbMrdxGTwdSbONNhl1ENZKDtCaMzh+0vG3a7Zpkyb9GFxDXfzA35oa3RU8Z5/KdGEwK9jkwDwHe2tM8ntzv7umDFKvxEO6WfGMHVn0ZzkAxcus4tEcYNXsDdxefIygf4ycpI4XKqpmYXoBPMJHkUMcKLRXygUXJPUt7iQ== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(107886003)(356005)(7636003)(70206006)(2906002)(16526019)(6286002)(70586007)(83380400001)(6916009)(8936002)(4326008)(36860700001)(2616005)(508600001)(336012)(186003)(8676002)(47076005)(36756003)(86362001)(7696005)(426003)(26005)(54906003)(5660300002)(55016003)(82310400004)(316002)(6666004)(1076003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Nov 2021 09:36:16.8079 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 37bd8218-67ac-48de-75a7-08d9af2ddd36 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT026.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1423 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org mlx5_ind_table_obj_modify() was not changing the reference counters of neither the new set of RxQs, nor the old set of RxQs. On the other hand, creation of the RSS incremented the RxQ refcnt. If an RxQ was present in both the initial and the modified set, its reference counter was incremented one extra time compared to the queues that were only present in the new set. This prevented releasing said RxQ resources on port stop: flow indirect_action 0 create action_id 1 \ action rss queues 0 1 end / end flow indirect_action 0 update 1 \ action rss queues 2 3 end / end quit ... mlx5_net: mlx5.c:1622: mlx5_dev_close(): port 0 some Rx queue objects still remain mlx5_net: mlx5.c:1626: mlx5_dev_close(): port 0 some Rx queues still remain Increment reference counters for the new set of RxQs and decrement them for the old set of RxQs. Only do this when the port is started when the port is started. Remove explicit referencing of RxQ from mlx5_ind_table_obj_attach() because it reuses mlx5_ind_table_obj_modify() code doing this. Fixes: ec4e11d41d12 ("net/mlx5: preserve indirect actions on restart") Signed-off-by: Dmitry Kozlyuk --- drivers/net/mlx5/mlx5_rxq.c | 34 +++++++++++++++++++--------------- 1 file changed, 19 insertions(+), 15 deletions(-) diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index 8f9a94572f..46d6536be5 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -2392,7 +2392,8 @@ mlx5_ind_table_obj_modify(struct rte_eth_dev *dev, bool standalone) { struct mlx5_priv *priv = dev->data->dev_private; - unsigned int i; + bool dev_started = priv->dev_data->dev_started; + unsigned int i, j; int ret = 0, err; const unsigned int n = rte_is_power_of_2(queues_n) ? log2above(queues_n) : @@ -2402,22 +2403,30 @@ mlx5_ind_table_obj_modify(struct rte_eth_dev *dev, RTE_SET_USED(standalone); if (mlx5_ind_table_obj_check_standalone(dev, ind_tbl) < 0) return -rte_errno; - for (i = 0; i != queues_n; ++i) { - if (!mlx5_rxq_get(dev, queues[i])) { - ret = -rte_errno; - goto error; + if (dev_started) + for (i = 0; i != queues_n; ++i) { + if (!mlx5_rxq_ref(dev, queues[i])) { + ret = -rte_errno; + goto error; + } } - } MLX5_ASSERT(priv->obj_ops.ind_table_modify); ret = priv->obj_ops.ind_table_modify(dev, n, queues, queues_n, ind_tbl); if (ret) goto error; + if (dev_started) + for (i = 0; i < ind_tbl->queues_n; i++) + claim_nonzero(mlx5_rxq_deref(dev, ind_tbl->queues[i])); ind_tbl->queues_n = queues_n; ind_tbl->queues = queues; return 0; error: - err = rte_errno; - rte_errno = err; + if (dev_started) { + err = rte_errno; + for (j = 0; j < i; j++) + mlx5_rxq_deref(dev, queues[j]); + rte_errno = err; + } DRV_LOG(DEBUG, "Port %u cannot setup indirection table.", dev->data->port_id); return ret; @@ -2438,19 +2447,14 @@ int mlx5_ind_table_obj_attach(struct rte_eth_dev *dev, struct mlx5_ind_table_obj *ind_tbl) { - unsigned int i; int ret; ret = mlx5_ind_table_obj_modify(dev, ind_tbl, ind_tbl->queues, ind_tbl->queues_n, true); - if (ret != 0) { + if (ret != 0) DRV_LOG(ERR, "Port %u could not modify indirect table obj %p", dev->data->port_id, (void *)ind_tbl); - return ret; - } - for (i = 0; i < ind_tbl->queues_n; i++) - mlx5_rxq_ref(dev, ind_tbl->queues[i]); - return 0; + return ret; } /**