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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT034.mail.protection.outlook.com (10.13.173.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4690.15 via Frontend Transport; Sun, 14 Nov 2021 15:36:33 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sun, 14 Nov 2021 15:36:30 +0000 From: Gregory Etelson To: , CC: , , , "Viacheslav Ovsiienko" , Raslan Darawsheh Subject: [PATCH 1/5] net/mlx5: fix VXLAN-GPE next protocol translation Date: Sun, 14 Nov 2021 17:36:12 +0200 Message-ID: <20211114153617.25085-1-getelson@nvidia.com> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 246bdb2b-8fbf-4665-0007-08d9a78489dd X-MS-TrafficTypeDiagnostic: BYAPR12MB3253: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4303; 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CAT:NONE; SFS:(4636009)(36840700001)(46966006)(47076005)(55016002)(316002)(8936002)(186003)(16526019)(70586007)(450100002)(86362001)(36906005)(508600001)(8676002)(7696005)(2616005)(1076003)(107886003)(5660300002)(70206006)(6666004)(426003)(36756003)(336012)(36860700001)(6286002)(2906002)(7049001)(83380400001)(356005)(26005)(82310400003)(4326008)(7636003)(110136005)(54906003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Nov 2021 15:36:33.9050 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 246bdb2b-8fbf-4665-0007-08d9a78489dd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT034.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3253 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org VXLAN-GPE extends VXLAN protocol and provides the next protocol field specifying the first inner header type. The application can assign some explicit value to VXLAN-GPE::next_protocol field or set it to the default one. In the latter case, the rdma-core library cannot recognize the matcher built by PMD correctly, and it results in hardware configuration missing inner headers match. The patch forces VXLAN-GPE::next_protocol assignment if the application did not explicitly assign it to the non-default value Cc: stable@dpdk.org Fixes: 90456726eb80 ("net/mlx5: fix VXLAN-GPE item translation") Signed-off-by: Gregory Etelson Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow_dv.c | 76 ++++++++++++++++++--------------- 1 file changed, 42 insertions(+), 34 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 1b4e15dff1..f9acb69cca 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -8962,46 +8962,40 @@ flow_dv_translate_item_vxlan(struct rte_eth_dev *dev, static void flow_dv_translate_item_vxlan_gpe(void *matcher, void *key, - const struct rte_flow_item *item, int inner) + const struct rte_flow_item *item, + const uint64_t pattern_flags) { + static const struct rte_flow_item_vxlan_gpe dummy_vxlan_gpe_hdr = {0, }; const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask; const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec; - void *headers_m; - void *headers_v; + /* The item was validated to be on the outer side */ + void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers); + void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers); void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3); void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3); - char *vni_m; - char *vni_v; - uint16_t dport; - int size; - int i; + char *vni_m = + MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni); + char *vni_v = + MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni); + int i, size = sizeof(vxlan_m->vni); uint8_t flags_m = 0xff; uint8_t flags_v = 0xc; + uint8_t m_protocol, v_protocol; - if (inner) { - headers_m = MLX5_ADDR_OF(fte_match_param, matcher, - inner_headers); - headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers); - } else { - headers_m = MLX5_ADDR_OF(fte_match_param, matcher, - outer_headers); - headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers); - } - dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ? - MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE; if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) { MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF); - MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport); + MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, + MLX5_UDP_PORT_VXLAN_GPE); + } + if (!vxlan_v) { + vxlan_v = &dummy_vxlan_gpe_hdr; + vxlan_m = &dummy_vxlan_gpe_hdr; + } else { + if (!vxlan_m) + vxlan_m = &rte_flow_item_vxlan_gpe_mask; } - if (!vxlan_v) - return; - if (!vxlan_m) - vxlan_m = &rte_flow_item_vxlan_gpe_mask; - size = sizeof(vxlan_m->vni); - vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni); - vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni); memcpy(vni_m, vxlan_m->vni, size); for (i = 0; i < size; ++i) vni_v[i] = vni_m[i] & vxlan_v->vni[i]; @@ -9011,10 +9005,22 @@ flow_dv_translate_item_vxlan_gpe(void *matcher, void *key, } MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m); MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v); - MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol, - vxlan_m->protocol); - MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol, - vxlan_v->protocol); + m_protocol = vxlan_m->protocol; + v_protocol = vxlan_v->protocol; + if (!m_protocol) { + m_protocol = 0xff; + /* Force next protocol to ensure next headers parsing. */ + if (pattern_flags & MLX5_FLOW_LAYER_INNER_L2) + v_protocol = RTE_VXLAN_GPE_TYPE_ETH; + else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4) + v_protocol = RTE_VXLAN_GPE_TYPE_IPV4; + else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6) + v_protocol = RTE_VXLAN_GPE_TYPE_IPV6; + } + MLX5_SET(fte_match_set_misc3, misc_m, + outer_vxlan_gpe_next_protocol, m_protocol); + MLX5_SET(fte_match_set_misc3, misc_v, + outer_vxlan_gpe_next_protocol, m_protocol & v_protocol); } /** @@ -12644,6 +12650,7 @@ flow_dv_translate(struct rte_eth_dev *dev, .std_tbl_fix = true, }; const struct rte_flow_item *integrity_items[2] = {NULL, NULL}; + const struct rte_flow_item *tunnel_item = NULL; if (!wks) return rte_flow_error_set(error, ENOMEM, @@ -13437,11 +13444,9 @@ flow_dv_translate(struct rte_eth_dev *dev, last_item = MLX5_FLOW_LAYER_VXLAN; break; case RTE_FLOW_ITEM_TYPE_VXLAN_GPE: - flow_dv_translate_item_vxlan_gpe(match_mask, - match_value, items, - tunnel); matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc); last_item = MLX5_FLOW_LAYER_VXLAN_GPE; + tunnel_item = items; break; case RTE_FLOW_ITEM_TYPE_GENEVE: flow_dv_translate_item_geneve(match_mask, match_value, @@ -13573,6 +13578,9 @@ flow_dv_translate(struct rte_eth_dev *dev, integrity_items, item_flags); } + if (item_flags & MLX5_FLOW_LAYER_VXLAN_GPE) + flow_dv_translate_item_vxlan_gpe(match_mask, match_value, + tunnel_item, item_flags); #ifdef RTE_LIBRTE_MLX5_DEBUG MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf, dev_flow->dv.value.buf)); From patchwork Sun Nov 14 15:36:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory Etelson X-Patchwork-Id: 104288 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B6969A0032; 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Sun, 14 Nov 2021 15:36:33 +0000 From: Gregory Etelson To: , CC: , , , "Viacheslav Ovsiienko" Subject: [PATCH 2/5] net/mlx5: add Ethernet header to GENEVE RSS expansion Date: Sun, 14 Nov 2021 17:36:13 +0200 Message-ID: <20211114153617.25085-2-getelson@nvidia.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211114153617.25085-1-getelson@nvidia.com> References: <20211114153617.25085-1-getelson@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ceac3e3c-22d5-4cc9-c627-08d9a7848c5a X-MS-TrafficTypeDiagnostic: SN6PR12MB2656: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:669; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: k0Z8nljgreRE9g2Ur6qdrf+VwkTXjjbrAH9pQf0Ja5YYx20X2KecU8WAP70Lov8+4q15AS67dFP3jaDrOHhZq5D6yUqK+NnKwiGEVfIZeP9pzDTKI53mb2OPK5wuY5ugDLQOBhNp0Xj8CgOM5Bg4dQEnkYC24YX0eMAaHfyMJ+4JkA9uaGxwOnoy56KBApKukt8hlmSfHhjoAgLWRt1v3sdex4f5x8mEijKepvj2v6ueEHWhdvVMAs7XVNzFMGpQXIq44SphMXgwYrLeAWaIz9NjMyjTprOfe6ckg7HQelYtM/U+Libg+gVLxHk+dJY0uGv88WQ20WlkniPGUGR22K/uWLYGEeYiFrQDcpSrC52U9i+PkGIwH3+t/ETwlaznrR7j+SJM+0SczH3sWkWYeeNZXLAifTktl3Fe0/MWG+5pbuTKD2diu94SOtI7AZs5St1isOOXyWqlDKfQyXPM9tB+1RVRCLaBWPk+1s3JW5YFblLamoNdpLI89k7JtXGoVnBVC9tyjTEwsuM1kwjZNf5H7zPQmEhLnRRSDhgS/WMM/SU+bcWNT8QHCrNpyb1PhPRS1Uhfq/tNjoq5cubg7J2Rr7OEYKGt2GRgpl9/ZvJk4AZDCr6atV9jxutKdHsct7bw4uJkInD0zlPGs+sLdo2Tjap2CHaE7iFuK5q83OHNJEnf0SVOvGy8ZpWbrzev X-Forefront-Antispam-Report: CIP:216.228.112.34; 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Current GENEVE RSS expansion created IPv4 and IPv6 paths only. The patch adds Ethernet to RSS expansion scheme. Cc: stable@dpdk.org Signed-off-by: Gregory Etelson Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow.c | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index f657980737..205fe19cdd 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -258,6 +258,29 @@ mlx5_flow_expand_rss_item_complete(const struct rte_flow_item *item) else ret = RTE_FLOW_ITEM_TYPE_END; break; + case RTE_FLOW_ITEM_TYPE_GENEVE: + ether_type_m = item->mask ? + ((const struct rte_flow_item_geneve *) + (item->mask))->protocol : + rte_flow_item_geneve_mask.protocol; + ether_type = ((const struct rte_flow_item_geneve *) + (item->spec))->protocol; + ether_type_m = rte_be_to_cpu_16(ether_type_m); + ether_type = rte_be_to_cpu_16(ether_type); + switch (ether_type_m & ether_type) { + case RTE_ETHER_TYPE_TEB: + ret = RTE_FLOW_ITEM_TYPE_ETH; + break; + case RTE_ETHER_TYPE_IPV4: + ret = RTE_FLOW_ITEM_TYPE_IPV4; + break; + case RTE_ETHER_TYPE_IPV6: + ret = RTE_FLOW_ITEM_TYPE_IPV6; + break; + default: + ret = RTE_FLOW_ITEM_TYPE_END; + } + break; default: ret = RTE_FLOW_ITEM_TYPE_VOID; break; @@ -530,7 +553,8 @@ enum mlx5_expansion { MLX5_EXPANSION_IPV6_UDP, MLX5_EXPANSION_IPV6_TCP, MLX5_EXPANSION_IPV6_FRAG_EXT, - MLX5_EXPANSION_GTP + MLX5_EXPANSION_GTP, + MLX5_EXPANSION_GENEVE, }; /** Supported expansion of items. */ @@ -574,6 +598,7 @@ static const struct mlx5_flow_expand_node mlx5_support_expansion[] = { .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, MLX5_EXPANSION_VXLAN_GPE, MLX5_EXPANSION_MPLS, + MLX5_EXPANSION_GENEVE, MLX5_EXPANSION_GTP), .type = RTE_FLOW_ITEM_TYPE_UDP, .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_UDP, @@ -598,6 +623,7 @@ static const struct mlx5_flow_expand_node mlx5_support_expansion[] = { .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, MLX5_EXPANSION_VXLAN_GPE, MLX5_EXPANSION_MPLS, + MLX5_EXPANSION_GENEVE, MLX5_EXPANSION_GTP), .type = RTE_FLOW_ITEM_TYPE_UDP, .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_UDP, @@ -701,6 +727,12 @@ static const struct mlx5_flow_expand_node mlx5_support_expansion[] = { MLX5_EXPANSION_IPV6), .type = RTE_FLOW_ITEM_TYPE_GTP, }, + [MLX5_EXPANSION_GENEVE] = { + .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, + MLX5_EXPANSION_IPV4, + MLX5_EXPANSION_IPV6), + .type = RTE_FLOW_ITEM_TYPE_GENEVE, + }, }; static struct rte_flow_action_handle * From patchwork Sun Nov 14 15:36:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory Etelson X-Patchwork-Id: 104289 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E1D86A0032; Sun, 14 Nov 2021 16:36:49 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2E5604114A; Sun, 14 Nov 2021 16:36:43 +0100 (CET) Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2040.outbound.protection.outlook.com [40.107.237.40]) by mails.dpdk.org (Postfix) with ESMTP id 6369A41142; Sun, 14 Nov 2021 16:36:42 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=DtJBrAsbb9BvIG19zCXBA9G6kxeoCEe9l/SI3RbiDdOU6RFwP+07sE/eb5NKMH1t1VcS1fdC3MOYBfKoHeDNy6KcDeubCaEpU7m7YrLVfOGJo33y1sqEsqrzqdDnHpCwsak9mTvuF0lU2qgQ01Kd6LBA/+gRo9Ot1rUwY9PJfK3hye6SlddnJRxAlg5/pVHnRg0b3gvbgvAltC+E7ohhyjJ/huPIV4yIcW4KhuyfdMTanLFEuBj4jMAXp3Tyre0ID2O6BZRvPGMzgOqlBjFioregvqNyW1KvEU/rF6ZslNQmCffe+GDpFgy3WseagffyZq0+T3YND2xYOR41aBcY2w== ARC-Message-Signature: i=1; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT021.mail.protection.outlook.com (10.13.173.76) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4690.15 via Frontend Transport; Sun, 14 Nov 2021 15:36:39 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sun, 14 Nov 2021 15:36:35 +0000 From: Gregory Etelson To: , CC: , , , "Viacheslav Ovsiienko" , Yongseok Koh , "Nelio Laranjeiro" Subject: [PATCH 3/5] net/mlx5: fix RSS expansion scheme for GRE header Date: Sun, 14 Nov 2021 17:36:14 +0200 Message-ID: <20211114153617.25085-3-getelson@nvidia.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211114153617.25085-1-getelson@nvidia.com> References: <20211114153617.25085-1-getelson@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a03a7851-8a26-45b9-f47e-08d9a7848d6c X-MS-TrafficTypeDiagnostic: BN9PR12MB5337: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1360; 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Add Ethernet to GRE RSS expansion. Cc: stable@dpdk.org Fixes: f4b901a46aec ("net/mlx5: add flow GRE item") Signed-off-by: Gregory Etelson Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 205fe19cdd..43598f92ee 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -654,7 +654,8 @@ static const struct mlx5_flow_expand_node mlx5_support_expansion[] = { .type = RTE_FLOW_ITEM_TYPE_VXLAN_GPE, }, [MLX5_EXPANSION_GRE] = { - .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, + .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, + MLX5_EXPANSION_IPV4, MLX5_EXPANSION_IPV6, MLX5_EXPANSION_GRE_KEY, MLX5_EXPANSION_MPLS), From patchwork Sun Nov 14 15:36:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory Etelson X-Patchwork-Id: 104290 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B5E3DA0032; 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Sun, 14 Nov 2021 15:36:37 +0000 From: Gregory Etelson To: , CC: , , , "Viacheslav Ovsiienko" , Moti Haimovsky Subject: [PATCH 4/5] net/mlx5: fix GENEVE protocol type translation Date: Sun, 14 Nov 2021 17:36:15 +0200 Message-ID: <20211114153617.25085-4-getelson@nvidia.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211114153617.25085-1-getelson@nvidia.com> References: <20211114153617.25085-1-getelson@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f554cfb4-e418-4ece-2724-08d9a7848e86 X-MS-TrafficTypeDiagnostic: CH2PR12MB3910: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3276; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 14Dog+Q7ph52cLW72mY3Ac+zkGSkokWia/o7nnBsJkb75mfoON6b/KhURLxfZMZAxmNnZnF/1xNKgSdWkGPUpGwduLg+UK0uGRAkp64xEXtHljX0u8CCTgTQyU28AraIS1Im3p2uSMHAcdU5D0YDZ/SnFVPSIT6mTNHUbwaRhMsqGS0on7TrwjXt8cHaSehGMtN6pFVL4PGTlkspgi0ATck+hRUtXg003bEPt6GrsZzYIhhl+MqwpzfauGaSmL0RzQid0W7GG2+69Mryxn7HhhQ6gRa8Rn6TDytLIgv4tfCdq+0dnO6euc7h/FxYRsx2+dRY46a0ZA8s+tM3lRHijJ3kzRJK8VtK77BkkUg71Esa2oRiHn7kiIcnEiVOML9gQ7Lydz981sZQBDzdhYBEmAHoJUsLT4GeenXJIGDg6DenmN9fUEdDao2TBlngp9JSki+xcUCQhWaWWFI1OtnivzaMVd1Quh7Hy23172ZBrw7gSRBM7wkSd59VWjhD2Zzm/vQaFNk6+U9v1GUnz6QYK2jCSYj0hLsUcJiYD5GNl3vshZy3FXZqJJzJbhxTOYQmTVkv7Dz+kppMieVrZGgBffhPbjEp0gzvOZFodUgqqegM7I6xAPCsP8vwKUciO3+Mta7Otlx8UkFMA90Lfp5uSovt+qHVzic6ySUVq2rwkG9UlAWCbfYGjwHcnNRY4FnjrOD1PeNtLdpqTEkjymYn/A== X-Forefront-Antispam-Report: CIP:216.228.112.34; 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RDMA-CORE cannot distinguish between different inner flow types and produces identical matchers for each zero mask. The patch extracts inner header type from flow rule and forces it in GENEVE protocol type, if application did not specify any without explicitly specifying GENEVE protocol type value in flow rules, protocol type value. Cc: stable@dpdk.org Fixes: e59a5dbcfd07 ("net/mlx5: add flow match on GENEVE item") Signed-off-by: Gregory Etelson Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow_dv.c | 78 ++++++++++++++++++++------------- 1 file changed, 47 insertions(+), 31 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index f9acb69cca..bce504391d 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -93,6 +93,20 @@ static int flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev, uint32_t rix_jump); +static inline uint16_t +mlx5_translate_tunnel_etypes(uint64_t pattern_flags) +{ + if (pattern_flags & MLX5_FLOW_LAYER_INNER_L2) + return RTE_ETHER_TYPE_TEB; + else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4) + return RTE_ETHER_TYPE_IPV4; + else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6) + return RTE_ETHER_TYPE_IPV6; + else if (pattern_flags & MLX5_FLOW_LAYER_MPLS) + return RTE_ETHER_TYPE_MPLS; + return 0; +} + static int16_t flow_dv_get_esw_manager_vport_id(struct rte_eth_dev *dev) { @@ -9038,49 +9052,39 @@ flow_dv_translate_item_vxlan_gpe(void *matcher, void *key, static void flow_dv_translate_item_geneve(void *matcher, void *key, - const struct rte_flow_item *item, int inner) + const struct rte_flow_item *item, + uint64_t pattern_flags) { + static const struct rte_flow_item_geneve empty_geneve = {0,}; const struct rte_flow_item_geneve *geneve_m = item->mask; const struct rte_flow_item_geneve *geneve_v = item->spec; - void *headers_m; - void *headers_v; + /* GENEVE flow item validation allows single tunnel item */ + void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers); + void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers); void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters); void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters); - uint16_t dport; uint16_t gbhdr_m; uint16_t gbhdr_v; - char *vni_m; - char *vni_v; - size_t size, i; + char *vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni); + char *vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni); + size_t size = sizeof(geneve_m->vni), i; + uint16_t protocol_m, protocol_v; - if (inner) { - headers_m = MLX5_ADDR_OF(fte_match_param, matcher, - inner_headers); - headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers); - } else { - headers_m = MLX5_ADDR_OF(fte_match_param, matcher, - outer_headers); - headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers); - } - dport = MLX5_UDP_PORT_GENEVE; if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) { MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF); - MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport); + MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, + MLX5_UDP_PORT_GENEVE); + } + if (!geneve_v) { + geneve_v = &empty_geneve; + geneve_m = &empty_geneve; + } else { + if (!geneve_m) + geneve_m = &rte_flow_item_geneve_mask; } - if (!geneve_v) - return; - if (!geneve_m) - geneve_m = &rte_flow_item_geneve_mask; - size = sizeof(geneve_m->vni); - vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni); - vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni); memcpy(vni_m, geneve_m->vni, size); for (i = 0; i < size; ++i) vni_v[i] = vni_m[i] & geneve_v->vni[i]; - MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type, - rte_be_to_cpu_16(geneve_m->protocol)); - MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type, - rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol)); gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0); gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0); MLX5_SET(fte_match_set_misc, misc_m, geneve_oam, @@ -9092,6 +9096,16 @@ flow_dv_translate_item_geneve(void *matcher, void *key, MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len, MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) & MLX5_GENEVE_OPTLEN_VAL(gbhdr_m)); + protocol_m = rte_be_to_cpu_16(geneve_m->protocol); + protocol_v = rte_be_to_cpu_16(geneve_v->protocol); + if (!protocol_m) { + /* Force next protocol to prevent matchers duplication */ + protocol_m = 0xFFFF; + protocol_v = mlx5_translate_tunnel_etypes(pattern_flags); + } + MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type, protocol_m); + MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type, + protocol_m & protocol_v); } /** @@ -13449,10 +13463,9 @@ flow_dv_translate(struct rte_eth_dev *dev, tunnel_item = items; break; case RTE_FLOW_ITEM_TYPE_GENEVE: - flow_dv_translate_item_geneve(match_mask, match_value, - items, tunnel); matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc); last_item = MLX5_FLOW_LAYER_GENEVE; + tunnel_item = items; break; case RTE_FLOW_ITEM_TYPE_GENEVE_OPT: ret = flow_dv_translate_item_geneve_opt(dev, match_mask, @@ -13581,6 +13594,9 @@ flow_dv_translate(struct rte_eth_dev *dev, if (item_flags & MLX5_FLOW_LAYER_VXLAN_GPE) flow_dv_translate_item_vxlan_gpe(match_mask, match_value, tunnel_item, item_flags); + else if (item_flags & MLX5_FLOW_LAYER_GENEVE) + flow_dv_translate_item_geneve(match_mask, match_value, + tunnel_item, item_flags); #ifdef RTE_LIBRTE_MLX5_DEBUG MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf, dev_flow->dv.value.buf)); From patchwork Sun Nov 14 15:36:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory Etelson X-Patchwork-Id: 104291 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C8E05A0032; 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Sun, 14 Nov 2021 15:36:40 +0000 From: Gregory Etelson To: , CC: , , , "Viacheslav Ovsiienko" , Yongseok Koh , "Ori Kam" Subject: [PATCH 5/5] net/mlx5: fix GRE protocol type translation Date: Sun, 14 Nov 2021 17:36:16 +0200 Message-ID: <20211114153617.25085-5-getelson@nvidia.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211114153617.25085-1-getelson@nvidia.com> References: <20211114153617.25085-1-getelson@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 70e80bb9-1298-4343-a62b-08d9a7848f0c X-MS-TrafficTypeDiagnostic: BYAPR12MB2615: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:462; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ACk+4eEiN2qIQzMZ7XyqVrr+GPLULqyY05d1ceojSZ8Qu+EZBYkKPbSRnqmS3mclWkwzEQUx6POPaxDKK26oSLSh9T9rbomDzXH5C0ahxAQeGy4UdKm0ZiWWQuSHiZmRsoMpemOB/to9XGycNYBW86UziCM+SybJ2r9foZF3z4Gtkpa3HLRDQ+KyS6pp5R28JfWePZt0kq54fSzInbMu68eQfHtGPb4FwrIowp0VoCK6yNMrVo6UUUJO+UqYD1HXdi7Fdw4azcZ02HLi8/7ZU+AAFd2T4VtiwIlsW9ESJXv0Lyiwwt4APxyRVBDQH0x7lxjoE46fmXPGW82aGZArKmOy+Rb43Ag90WiR08WYMlFEKtPzKt1w7v6Di/OnKmEU0HwoL2EyAMktIH2UOhFdTrkIibWwi/avKcij0vXgbLNsVJwuLk0dD2X5xNwU264GDQKXxMMhPoRD8HxC4uPa/iXkmpmfZqTNSfb/H60AdAxBFyeu8bYLrsJ0Xxo5IRoUNTlyY5bJwpOHy0PmfVfIcLSLG93CTqfKhlTb8GIZpk7x9MyEl7rigxyEAqdqFF3uA0hhUq3QC028hechGejpYVkAWQeFhWihgfd6FUy+bgseM/4oadDAlfgn8AeU2tOloeO5W2lzN6FnGX2wp4y/ifUPxtMDNtq7pRTTWQ6J0kFivU8Lstngg2C7Xs30rLEWWnHsShy430dnjPaDZIdtDA== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(2616005)(110136005)(1076003)(6286002)(26005)(8936002)(55016002)(47076005)(86362001)(7049001)(54906003)(336012)(7696005)(2906002)(36756003)(426003)(36860700001)(6666004)(8676002)(70206006)(83380400001)(316002)(107886003)(5660300002)(356005)(450100002)(186003)(7636003)(508600001)(70586007)(16526019)(4326008)(82310400003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Nov 2021 15:36:42.5869 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 70e80bb9-1298-4343-a62b-08d9a7848f0c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT021.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB2615 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When application creates several flows to match on GRE tunnel without explicitly specifying GRE protocol type value in flow rules, PMD will translate that to zero mask. RDMA-CORE cannot distinguish between different inner flow types and produces identical matchers for each zero mask. The patch extracts inner header type from flow rule and forces it in GRE protocol type, if application did not specify any without explicitly specifying GRE protocol type value in flow rules, protocol type value. Cc: stable@dpdk.org Fixes: fc2c498ccb94 ("net/mlx5: add Direct Verbs translate items") Signed-off-by: Gregory Etelson Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow_dv.c | 70 +++++++++++++++++++-------------- 1 file changed, 40 insertions(+), 30 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index bce504391d..287a17d956 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -8730,18 +8730,19 @@ flow_dv_translate_item_gre_key(void *matcher, void *key, * Flow matcher value. * @param[in] item * Flow pattern to translate. - * @param[in] inner - * Item is inner pattern. + * @param[in] pattern_flags + * Accumulated pattern flags. */ static void flow_dv_translate_item_gre(void *matcher, void *key, const struct rte_flow_item *item, - int inner) + uint64_t pattern_flags) { + static const struct rte_flow_item_gre empty_gre = {0,}; const struct rte_flow_item_gre *gre_m = item->mask; const struct rte_flow_item_gre *gre_v = item->spec; - void *headers_m; - void *headers_v; + void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers); + void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers); void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters); void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters); struct { @@ -8758,26 +8759,17 @@ flow_dv_translate_item_gre(void *matcher, void *key, uint16_t value; }; } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v; + uint16_t protocol_m, protocol_v; - if (inner) { - headers_m = MLX5_ADDR_OF(fte_match_param, matcher, - inner_headers); - headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers); - } else { - headers_m = MLX5_ADDR_OF(fte_match_param, matcher, - outer_headers); - headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers); - } MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff); MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE); - if (!gre_v) - return; - if (!gre_m) - gre_m = &rte_flow_item_gre_mask; - MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, - rte_be_to_cpu_16(gre_m->protocol)); - MLX5_SET(fte_match_set_misc, misc_v, gre_protocol, - rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol)); + if (!gre_v) { + gre_v = &empty_gre; + gre_m = &empty_gre; + } else { + if (!gre_m) + gre_m = &rte_flow_item_gre_mask; + } gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver); gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver); MLX5_SET(fte_match_set_misc, misc_m, gre_c_present, @@ -8795,6 +8787,16 @@ flow_dv_translate_item_gre(void *matcher, void *key, MLX5_SET(fte_match_set_misc, misc_v, gre_s_present, gre_crks_rsvd0_ver_v.s_present & gre_crks_rsvd0_ver_m.s_present); + protocol_m = rte_be_to_cpu_16(gre_m->protocol); + protocol_v = rte_be_to_cpu_16(gre_v->protocol); + if (!protocol_m) { + /* Force next protocol to prevent matchers duplication */ + protocol_m = 0xFFFF; + protocol_v = mlx5_translate_tunnel_etypes(pattern_flags); + } + MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, protocol_m); + MLX5_SET(fte_match_set_misc, misc_v, gre_protocol, + protocol_m & protocol_v); } /** @@ -8806,13 +8808,13 @@ flow_dv_translate_item_gre(void *matcher, void *key, * Flow matcher value. * @param[in] item * Flow pattern to translate. - * @param[in] inner - * Item is inner pattern. + * @param[in] pattern_flags + * Accumulated pattern flags. */ static void flow_dv_translate_item_nvgre(void *matcher, void *key, const struct rte_flow_item *item, - int inner) + unsigned long pattern_flags) { const struct rte_flow_item_nvgre *nvgre_m = item->mask; const struct rte_flow_item_nvgre *nvgre_v = item->spec; @@ -8839,7 +8841,7 @@ flow_dv_translate_item_nvgre(void *matcher, void *key, .mask = &gre_mask, .last = NULL, }; - flow_dv_translate_item_gre(matcher, key, &gre_item, inner); + flow_dv_translate_item_gre(matcher, key, &gre_item, pattern_flags); if (!nvgre_v) return; if (!nvgre_m) @@ -13434,10 +13436,9 @@ flow_dv_translate(struct rte_eth_dev *dev, MLX5_FLOW_LAYER_OUTER_L4_UDP; break; case RTE_FLOW_ITEM_TYPE_GRE: - flow_dv_translate_item_gre(match_mask, match_value, - items, tunnel); matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc); last_item = MLX5_FLOW_LAYER_GRE; + tunnel_item = items; break; case RTE_FLOW_ITEM_TYPE_GRE_KEY: flow_dv_translate_item_gre_key(match_mask, @@ -13445,10 +13446,9 @@ flow_dv_translate(struct rte_eth_dev *dev, last_item = MLX5_FLOW_LAYER_GRE_KEY; break; case RTE_FLOW_ITEM_TYPE_NVGRE: - flow_dv_translate_item_nvgre(match_mask, match_value, - items, tunnel); matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc); last_item = MLX5_FLOW_LAYER_GRE; + tunnel_item = items; break; case RTE_FLOW_ITEM_TYPE_VXLAN: flow_dv_translate_item_vxlan(dev, attr, @@ -13597,6 +13597,16 @@ flow_dv_translate(struct rte_eth_dev *dev, else if (item_flags & MLX5_FLOW_LAYER_GENEVE) flow_dv_translate_item_geneve(match_mask, match_value, tunnel_item, item_flags); + else if (item_flags & MLX5_FLOW_LAYER_GRE) { + if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE) + flow_dv_translate_item_gre(match_mask, match_value, + tunnel_item, item_flags); + else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_NVGRE) + flow_dv_translate_item_nvgre(match_mask, match_value, + tunnel_item, item_flags); + else + MLX5_ASSERT(false); + } #ifdef RTE_LIBRTE_MLX5_DEBUG MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf, dev_flow->dv.value.buf));